kopia lustrzana https://github.com/UU5JPP/Wolf-LITE
14 wiersze
745 B
Plaintext
14 wiersze
745 B
Plaintext
component rx_ciccomp is
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port (
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clk : in std_logic := 'X'; -- clk
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reset_n : in std_logic := 'X'; -- reset_n
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ast_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
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ast_sink_valid : in std_logic := 'X'; -- valid
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ast_sink_error : in std_logic_vector(1 downto 0) := (others => 'X'); -- error
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ast_source_data : out std_logic_vector(45 downto 0); -- data
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ast_source_valid : out std_logic; -- valid
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ast_source_error : out std_logic_vector(1 downto 0) -- error
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);
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end component rx_ciccomp;
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