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Merge branch 'master' of https://github.com/UU5JPP/Wolf-LITE

master
Антон 2021-10-26 20:53:45 +03:00
rodzic 0588c10ab9 11393b03e0
commit 29c610b3e8
61 zmienionych plików z 4996 dodań i 2390 usunięć
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4
STM32/.mxproject
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5
STM32/Core/Inc/main.h
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@ -44,6 +44,7 @@ extern SRAM_HandleTypeDef hsram1;
/* USER CODE BEGIN EC */ /* USER CODE BEGIN EC */
extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc1;
extern ADC_HandleTypeDef hadc2; extern ADC_HandleTypeDef hadc2;
extern ADC_HandleTypeDef hadc3;
extern I2S_HandleTypeDef hi2s3; extern I2S_HandleTypeDef hi2s3;
extern SPI_HandleTypeDef hspi2; extern SPI_HandleTypeDef hspi2;
extern RTC_HandleTypeDef hrtc; extern RTC_HandleTypeDef hrtc;
@ -62,7 +63,7 @@ extern DMA_HandleTypeDef hdma_memtomem_dma2_stream0;
/* USER CODE BEGIN EM */ /* USER CODE BEGIN EM */
/* USER CODE END EM */ /* USER CODE END EM */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/* Exported functions prototypes ---------------------------------------------*/ /* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void); void Error_Handler(void);
@ -149,6 +150,8 @@ void Error_Handler(void);
#define CPU_PW_Pin GPIO_PIN_7 #define CPU_PW_Pin GPIO_PIN_7
#define CPU_PW_GPIO_Port GPIOB #define CPU_PW_GPIO_Port GPIOB
#define CPU_PW_EXTI_IRQn EXTI9_5_IRQn #define CPU_PW_EXTI_IRQn EXTI9_5_IRQn
#define LCD_BL_PWM_Pin GPIO_PIN_8
#define LCD_BL_PWM_GPIO_Port GPIOB
#define KEY_IN_DASH_Pin GPIO_PIN_0 #define KEY_IN_DASH_Pin GPIO_PIN_0
#define KEY_IN_DASH_GPIO_Port GPIOE #define KEY_IN_DASH_GPIO_Port GPIOE
#define KEY_IN_DASH_EXTI_IRQn EXTI0_IRQn #define KEY_IN_DASH_EXTI_IRQn EXTI0_IRQn

34
STM32/Core/Inc/stm32f4xx_hal_conf.h
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@ -76,6 +76,7 @@
/* #define HAL_QSPI_MODULE_ENABLED */ /* #define HAL_QSPI_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_FMPI2C_MODULE_ENABLED */ /* #define HAL_FMPI2C_MODULE_ENABLED */
/* #define HAL_FMPSMBUS_MODULE_ENABLED */
/* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */
/* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */
/* #define HAL_LPTIM_MODULE_ENABLED */ /* #define HAL_LPTIM_MODULE_ENABLED */
@ -94,11 +95,11 @@
* (when HSE is used as system clock source, directly or through the PLL). * (when HSE is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT) #if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */ #endif /* HSE_STARTUP_TIMEOUT */
/** /**
@ -114,7 +115,7 @@
* @brief Internal Low Speed oscillator (LSI) value. * @brief Internal Low Speed oscillator (LSI) value.
*/ */
#if !defined (LSI_VALUE) #if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations The real value may vary depending on the variations
in voltage and temperature.*/ in voltage and temperature.*/
@ -122,11 +123,11 @@
* @brief External Low Speed oscillator (LSE) value. * @brief External Low Speed oscillator (LSE) value.
*/ */
#if !defined (LSE_VALUE) #if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */ #endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT) #if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */ #endif /* LSE_STARTUP_TIMEOUT */
/** /**
@ -135,7 +136,7 @@
* frequency, this source is inserted directly through I2S_CKIN pad. * frequency, this source is inserted directly through I2S_CKIN pad.
*/ */
#if !defined (EXTERNAL_CLOCK_VALUE) #if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External audio frequency in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */ #endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE, /* Tip: To avoid modifying this file each time you need to use different HSE,
@ -145,8 +146,8 @@
/** /**
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ #define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ #define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */
#define USE_RTOS 0U #define USE_RTOS 0U
#define PREFETCH_ENABLE 1U #define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 1U #define INSTRUCTION_CACHE_ENABLE 1U
@ -166,6 +167,7 @@
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ #define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */
#define USE_HAL_FMPSMBUS_REGISTER_CALLBACKS 0U /* FMPSMBUS register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
@ -213,20 +215,20 @@
/* Definition of the Ethernet driver buffers size and count */ /* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ #define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ #define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
/* Section 2: PHY configuration section */ /* Section 2: PHY configuration section */
/* DP83848_PHY_ADDRESS Address*/ /* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U #define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) #define PHY_RESET_DELAY 0x000000FFU
/* PHY Configuration delay */ /* PHY Configuration delay */
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) #define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO ((uint32_t)0x0000FFFFU) #define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) #define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */ /* Section 3: Common PHY Registers */
@ -444,6 +446,10 @@
#include "stm32f4xx_hal_fmpi2c.h" #include "stm32f4xx_hal_fmpi2c.h"
#endif /* HAL_FMPI2C_MODULE_ENABLED */ #endif /* HAL_FMPI2C_MODULE_ENABLED */
#ifdef HAL_FMPSMBUS_MODULE_ENABLED
#include "stm32f4xx_hal_fmpsmbus.h"
#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED #ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32f4xx_hal_spdifrx.h" #include "stm32f4xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */ #endif /* HAL_SPDIFRX_MODULE_ENABLED */

53
STM32/Core/Src/audio_processor.c
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@ -6,6 +6,7 @@
#include "usbd_audio_if.h" #include "usbd_audio_if.h"
#include "auto_notch.h" #include "auto_notch.h"
#include "trx_manager.h" #include "trx_manager.h"
#include "cw.h"
// Public variables // Public variables
volatile uint32_t AUDIOPROC_samples = 0; // audio samples processed in the processor volatile uint32_t AUDIOPROC_samples = 0; // audio samples processed in the processor
@ -283,6 +284,19 @@ void processTxAudio(void)
{ {
if (!Processor_NeedTXBuffer) if (!Processor_NeedTXBuffer)
return; return;
//sync fpga to audio-codec
/*uint32_t dma_index = CODEC_AUDIO_BUFFER_SIZE * 2 - (uint16_t)__HAL_DMA_GET_COUNTER(hi2s3.hdmatx);
if(!WM8731_DMA_state && dma_index > (CODEC_AUDIO_BUFFER_SIZE * 2 - 100))
return;
if(WM8731_DMA_state && dma_index > (CODEC_AUDIO_BUFFER_SIZE - 100))
return;*/
static bool old_WM8731_DMA_state = false;
if(WM8731_DMA_state == old_WM8731_DMA_state)
return;
old_WM8731_DMA_state = WM8731_DMA_state;
bool start_WM8731_DMA_state = old_WM8731_DMA_state;
VFO *current_vfo = CurrentVFO(); VFO *current_vfo = CurrentVFO();
AUDIOPROC_samples++; AUDIOPROC_samples++;
uint_fast8_t mode = current_vfo->Mode; uint_fast8_t mode = current_vfo->Mode;
@ -315,13 +329,6 @@ void processTxAudio(void)
//sendToDebug_uint32(CODEC_AUDIO_BUFFER_SIZE, false); //sendToDebug_uint32(CODEC_AUDIO_BUFFER_SIZE, false);
readFromCircleBuffer32((uint32_t *)&CODEC_Audio_Buffer_TX[0], (uint32_t *)&Processor_AudioBuffer_A[0], dma_index, CODEC_AUDIO_BUFFER_SIZE, AUDIO_BUFFER_SIZE); readFromCircleBuffer32((uint32_t *)&CODEC_Audio_Buffer_TX[0], (uint32_t *)&Processor_AudioBuffer_A[0], dma_index, CODEC_AUDIO_BUFFER_SIZE, AUDIO_BUFFER_SIZE);
} }
//sendToDebug_int32(convertToSPIBigEndian(CODEC_Audio_Buffer_TX[0]), false);
//sendToDebug_int32(convertToSPIBigEndian(CODEC_Audio_Buffer_TX[380]), false);
//sendToDebug_int32(convertToSPIBigEndian(CODEC_Audio_Buffer_TX[640]), false);
//sendToDebug_newline();
//sendToDebug_int32(convertToSPIBigEndian(Processor_AudioBuffer_A[0]), true);
//sendToDebug_str(" ");
//sendToDebug_int32(Processor_AudioBuffer_A[0], false);
//One-signal zero-tune generator //One-signal zero-tune generator
if (TRX_Tune && !TRX.TWO_SIGNAL_TUNE) if (TRX_Tune && !TRX.TWO_SIGNAL_TUNE)
@ -390,7 +397,6 @@ void processTxAudio(void)
FPGA_Audio_Buffer_TX_I_tmp[i] = (float32_t)convertToSPIBigEndian(Processor_AudioBuffer_A[i * 2]) / 2147483648.0f; FPGA_Audio_Buffer_TX_I_tmp[i] = (float32_t)convertToSPIBigEndian(Processor_AudioBuffer_A[i * 2]) / 2147483648.0f;
FPGA_Audio_Buffer_TX_Q_tmp[i] = (float32_t)convertToSPIBigEndian(Processor_AudioBuffer_A[i * 2 + 1]) / 2147483648.0f; FPGA_Audio_Buffer_TX_Q_tmp[i] = (float32_t)convertToSPIBigEndian(Processor_AudioBuffer_A[i * 2 + 1]) / 2147483648.0f;
} }
//sendToDebug_float32(FPGA_Audio_Buffer_TX_I_tmp[0],false); //sendToDebug_float32(FPGA_Audio_Buffer_TX_I_tmp[0],false);
if (TRX.InputType_MIC) if (TRX.InputType_MIC)
@ -398,21 +404,11 @@ void processTxAudio(void)
//Mic Gain //Mic Gain
arm_scale_f32(FPGA_Audio_Buffer_TX_I_tmp, TRX.MIC_GAIN, FPGA_Audio_Buffer_TX_I_tmp, AUDIO_BUFFER_HALF_SIZE); arm_scale_f32(FPGA_Audio_Buffer_TX_I_tmp, TRX.MIC_GAIN, FPGA_Audio_Buffer_TX_I_tmp, AUDIO_BUFFER_HALF_SIZE);
arm_scale_f32(FPGA_Audio_Buffer_TX_Q_tmp, TRX.MIC_GAIN, FPGA_Audio_Buffer_TX_Q_tmp, AUDIO_BUFFER_HALF_SIZE); arm_scale_f32(FPGA_Audio_Buffer_TX_Q_tmp, TRX.MIC_GAIN, FPGA_Audio_Buffer_TX_Q_tmp, AUDIO_BUFFER_HALF_SIZE);
// if (TRX.MIC_BOOST)
// WM8731_SendI2CCommand(B8(00001000), B8(00010101)); //R4 Analogue Audio Path Control
// else
// WM8731_SendI2CCommand(B8(00001000), B8(00010100)); //R4 Analogue Audio Path Control
//Mic Equalizer //Mic Equalizer
if (mode != TRX_MODE_DIGI_L && mode != TRX_MODE_DIGI_U && mode != TRX_MODE_IQ) if (mode != TRX_MODE_DIGI_L && mode != TRX_MODE_DIGI_U && mode != TRX_MODE_IQ)
doMIC_EQ(AUDIO_BUFFER_HALF_SIZE); doMIC_EQ(AUDIO_BUFFER_HALF_SIZE);
} }
//USB Gain (24bit)
if (TRX.InputType_USB)
{
arm_scale_f32(FPGA_Audio_Buffer_TX_I_tmp, 10.0f, FPGA_Audio_Buffer_TX_I_tmp, AUDIO_BUFFER_HALF_SIZE);
arm_scale_f32(FPGA_Audio_Buffer_TX_Q_tmp, 10.0f, FPGA_Audio_Buffer_TX_Q_tmp, AUDIO_BUFFER_HALF_SIZE);
}
//Process DC corrector filter //Process DC corrector filter
dc_filter(FPGA_Audio_Buffer_TX_I_tmp, AUDIO_BUFFER_HALF_SIZE, DC_FILTER_TX_I); dc_filter(FPGA_Audio_Buffer_TX_I_tmp, AUDIO_BUFFER_HALF_SIZE, DC_FILTER_TX_I);
@ -435,7 +431,7 @@ void processTxAudio(void)
case TRX_MODE_CW_U: case TRX_MODE_CW_U:
for (uint_fast16_t i = 0; i < AUDIO_BUFFER_HALF_SIZE; i++) for (uint_fast16_t i = 0; i < AUDIO_BUFFER_HALF_SIZE; i++)
{ {
FPGA_Audio_Buffer_TX_I_tmp[i] = TRX_GenerateCWSignal(Processor_selected_RFpower_amplitude); FPGA_Audio_Buffer_TX_I_tmp[i] = CW_GenerateSignal(Processor_selected_RFpower_amplitude);
FPGA_Audio_Buffer_TX_Q_tmp[i] = 0.0f; FPGA_Audio_Buffer_TX_Q_tmp[i] = 0.0f;
} }
break; break;
@ -591,14 +587,19 @@ void processTxAudio(void)
else else
{ {
//CW SelfHear //CW SelfHear
if (TRX.CW_SelfHear && (TRX.CW_KEYER || TRX_key_serial || TRX_key_dot_hard || TRX_key_dash_hard) && (mode == TRX_MODE_CW_L || mode == TRX_MODE_CW_U) && !TRX_Tune) if (TRX.CW_SelfHear && (TRX.CW_KEYER || CW_key_serial || CW_key_dot_hard || CW_key_dash_hard) && (mode == TRX_MODE_CW_L || mode == TRX_MODE_CW_U) && !TRX_Tune)
{ {
float32_t volume_gain_tx = volume2rate((float32_t)TRX.Volume / 100.0f); static float32_t cwgen_index = 0;
float32_t amplitude = (db2rateV(TRX.AGC_GAIN_TARGET) * volume_gain_tx * CODEC_BITS_FULL_SCALE / 2.0f); const float32_t SELFHEAR_Volume = 30.0f;
float32_t amplitude = volume2rate((float32_t)TRX.Volume / 100.0f) * volume2rate(SELFHEAR_Volume / 100.0f);
for (uint_fast16_t i = 0; i < AUDIO_BUFFER_HALF_SIZE; i++) for (uint_fast16_t i = 0; i < AUDIO_BUFFER_HALF_SIZE; i++)
{ {
int32_t data = convertToSPIBigEndian((int32_t)(amplitude * ( FPGA_Audio_Buffer_TX_I_tmp[i] / Processor_selected_RFpower_amplitude) * arm_sin_f32(((float32_t)i / (float32_t)TRX_SAMPLERATE) * PI * 2.0f * (float32_t)TRX.CW_GENERATOR_SHIFT_HZ))); const float32_t CW_Pitch_freq = 800;
if (WM8731_DMA_state) float32_t point = generateSinF(amplitude * FPGA_Audio_Buffer_TX_I_tmp[i], &cwgen_index, TRX_SAMPLERATE, CW_Pitch_freq);
int32_t sample = 0;
arm_float_to_q31(&point, &sample, 1);
int32_t data = convertToSPIBigEndian(sample);
if (start_WM8731_DMA_state)
{ {
CODEC_Audio_Buffer_RX[AUDIO_BUFFER_SIZE + i * 2] = data; CODEC_Audio_Buffer_RX[AUDIO_BUFFER_SIZE + i * 2] = data;
CODEC_Audio_Buffer_RX[AUDIO_BUFFER_SIZE + i * 2 + 1] = data; CODEC_Audio_Buffer_RX[AUDIO_BUFFER_SIZE + i * 2 + 1] = data;
@ -610,7 +611,7 @@ void processTxAudio(void)
} }
} }
} }
else if (TRX.CW_SelfHear) else if (TRX.CW_SelfHear && mode != TRX_MODE_DIGI_L && mode != TRX_MODE_DIGI_U && mode != TRX_MODE_LOOPBACK)
{ {
memset(CODEC_Audio_Buffer_RX, 0x00, sizeof CODEC_Audio_Buffer_RX); memset(CODEC_Audio_Buffer_RX, 0x00, sizeof CODEC_Audio_Buffer_RX);
} }
@ -787,7 +788,7 @@ static void DemodulateFM(uint16_t size)
b = FM_RX_HPF_ALPHA * (*hpf_prev_b + a - *hpf_prev_a); // do differentiation b = FM_RX_HPF_ALPHA * (*hpf_prev_b + a - *hpf_prev_a); // do differentiation
*hpf_prev_a = a; // save "[n-1]" samples for next iteration *hpf_prev_a = a; // save "[n-1]" samples for next iteration
*hpf_prev_b = b; *hpf_prev_b = b;
FPGA_Audio_Buffer_I_tmp[i] = b * 0.1f; // save demodulated and filtered audio in main audio processing buffer FPGA_Audio_Buffer_I_tmp[i] = b * 0.3f; // save demodulated and filtered audio in main audio processing buffer
} }
} }
else if (*squelched) // were we squelched or tone NOT detected? else if (*squelched) // were we squelched or tone NOT detected?

213
STM32/Core/Src/cw.c 100644
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@ -0,0 +1,213 @@
#include "stm32f4xx_hal.h"
#include "main.h"
#include "trx_manager.h"
#include "functions.h"
#include "lcd.h"
#include "fpga.h"
#include "settings.h"
#include "wm8731.h"
#include "fpga.h"
#include "bands.h"
#include "agc.h"
#include "audio_filters.h"
#include "usbd_audio_if.h"
#include "front_unit.h"
#include "rf_unit.h"
#include "system_menu.h"
#include "swr_analyzer.h"
volatile bool CW_key_serial = false;
volatile bool CW_old_key_serial = false;
volatile bool CW_key_dot_hard = false;
volatile bool CW_key_dash_hard = false;
volatile uint_fast16_t CW_Key_Timeout_est = 0;
volatile uint_fast8_t KEYER_symbol_status = 0; // status (signal or period) of the automatic key symbol
static uint32_t KEYER_symbol_start_time = 0; // start time of the automatic key character
static float32_t current_cw_power = 0.0f; // current amplitude (for rise/fall)
static bool iambic_first_button_pressed = false; //start symbol | false - dot, true - dash
static bool iambic_last_symbol = false; //last Iambic symbol | false - dot, true - dash
static bool iambic_sequence_started = false;
void CW_key_change(void)
{
if (TRX_Tune)
return;
if (CurrentVFO()->Mode != TRX_MODE_CW_L && CurrentVFO()->Mode != TRX_MODE_CW_U)
return;
bool TRX_new_key_dot_hard = !HAL_GPIO_ReadPin(KEY_IN_DOT_GPIO_Port, KEY_IN_DOT_Pin);
//if(TRX.CW_Invert)
//TRX_new_key_dot_hard = !HAL_GPIO_ReadPin(KEY_IN_DASH_GPIO_Port, KEY_IN_DASH_Pin);
if (CW_key_dot_hard != TRX_new_key_dot_hard)
{
CW_key_dot_hard = TRX_new_key_dot_hard;
if (CW_key_dot_hard == true && (KEYER_symbol_status == 0 || !TRX.CW_KEYER))
{
CW_Key_Timeout_est = TRX.CW_Key_timeout;
LCD_UpdateQuery.StatusInfoGUIRedraw = true;
FPGA_NeedSendParams = true;
TRX_Restart_Mode();
}
}
bool TRX_new_key_dash_hard = !HAL_GPIO_ReadPin(KEY_IN_DASH_GPIO_Port, KEY_IN_DASH_Pin);
//if(TRX.CW_Invert)
//TRX_new_key_dash_hard = !HAL_GPIO_ReadPin(KEY_IN_DOT_GPIO_Port, KEY_IN_DOT_Pin);
if (CW_key_dash_hard != TRX_new_key_dash_hard)
{
CW_key_dash_hard = TRX_new_key_dash_hard;
if (CW_key_dash_hard == true && (KEYER_symbol_status == 0 || !TRX.CW_KEYER))
{
CW_Key_Timeout_est = TRX.CW_Key_timeout;
LCD_UpdateQuery.StatusInfoGUIRedraw = true;
FPGA_NeedSendParams = true;
TRX_Restart_Mode();
}
}
if (CW_key_serial != CW_old_key_serial)
{
CW_old_key_serial = CW_key_serial;
if (CW_key_serial == true)
CW_Key_Timeout_est = TRX.CW_Key_timeout;
LCD_UpdateQuery.StatusInfoGUIRedraw = true;
FPGA_NeedSendParams = true;
TRX_Restart_Mode();
}
}
static float32_t CW_generateRiseSignal(float32_t power)
{
if (current_cw_power < power)
current_cw_power += power * 0.007f;
if (current_cw_power > power)
current_cw_power = power;
return current_cw_power;
}
static float32_t CW_generateFallSignal(float32_t power)
{
if (current_cw_power > 0.0f)
current_cw_power -= power * 0.007f;
if (current_cw_power < 0.0f)
current_cw_power = 0.0f;
return current_cw_power;
}
float32_t CW_GenerateSignal(float32_t power)
{
//Do no signal before start TX delay
//if ((HAL_GetTick() - TRX_TX_StartTime) < CALIBRATE.TX_StartDelay)
//return 0.0f;
//Keyer disabled
if (!TRX.CW_KEYER)
{
if (!CW_key_serial && !TRX_ptt_hard && !CW_key_dot_hard && !CW_key_dash_hard)
return CW_generateFallSignal(power);
return CW_generateRiseSignal(power);
}
//USB CW (Serial)
if(CW_key_serial)
return CW_generateRiseSignal(power);
//Keyer
const float32_t CW_DotToDashRate = 3.0f;
uint32_t dot_length_ms = 1200 / TRX.CW_KEYER_WPM;
uint32_t dash_length_ms = (float32_t)dot_length_ms * CW_DotToDashRate;
uint32_t sim_space_length_ms = dot_length_ms;
uint32_t curTime = HAL_GetTick();
//Iambic keyer start mode
if(CW_key_dot_hard && !CW_key_dash_hard)
iambic_first_button_pressed = false;
if(!CW_key_dot_hard && CW_key_dash_hard)
iambic_first_button_pressed = true;
if(CW_key_dot_hard && CW_key_dash_hard)
iambic_sequence_started = true;
//DOT .
if (KEYER_symbol_status == 0 && CW_key_dot_hard)
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 1;
}
if (KEYER_symbol_status == 1 && (KEYER_symbol_start_time + dot_length_ms) > curTime)
{
CW_Key_Timeout_est = TRX.CW_Key_timeout;
return CW_generateRiseSignal(power);
}
if (KEYER_symbol_status == 1 && (KEYER_symbol_start_time + dot_length_ms) < curTime)
{
iambic_last_symbol = false;
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 3;
}
//DASH -
if (KEYER_symbol_status == 0 && CW_key_dash_hard)
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 2;
}
if (KEYER_symbol_status == 2 && (KEYER_symbol_start_time + dash_length_ms) > curTime)
{
CW_Key_Timeout_est = TRX.CW_Key_timeout;
return CW_generateRiseSignal(power);
}
if (KEYER_symbol_status == 2 && (KEYER_symbol_start_time + dash_length_ms) < curTime)
{
iambic_last_symbol = true;
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 3;
}
//SPACE
if (KEYER_symbol_status == 3 && (KEYER_symbol_start_time + sim_space_length_ms) > curTime)
{
CW_Key_Timeout_est = TRX.CW_Key_timeout;
return CW_generateFallSignal(power);
}
if (KEYER_symbol_status == 3 && (KEYER_symbol_start_time + sim_space_length_ms) < curTime)
{
//if(!TRX.CW_Iambic) //classic keyer
KEYER_symbol_status = 0;
/*else //iambic keyer
{
//start iambic sequence
if(iambic_sequence_started)
{
if(!iambic_last_symbol) // iambic dot . , next dash -
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 2;
if(iambic_first_button_pressed && (!CW_key_dot_hard || !CW_key_dash_hard)) //iambic dash-dot sequence compleated
{
//println("-.e");
iambic_sequence_started = false;
KEYER_symbol_status = 0;
}
}
else // iambic dash - , next dot .
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 1;
if(!iambic_first_button_pressed && (!CW_key_dot_hard || !CW_key_dash_hard)) //iambic dot-dash sequence compleated
{
//println(".-e");
KEYER_symbol_status = 0;
iambic_sequence_started = false;
}
}
}
else //no sequence, classic mode
KEYER_symbol_status = 0;
}*/
}
return CW_generateFallSignal(power);
}

18
STM32/Core/Src/cw.h 100644
Wyświetl plik

@ -0,0 +1,18 @@
#ifndef CW_H
#define CW_H
#include "stm32f4xx_hal.h"
#include <stdbool.h>
#include "settings.h"
extern void CW_key_change(void);
extern float32_t CW_GenerateSignal(float32_t power);
volatile extern bool CW_key_serial;
volatile extern bool CW_old_key_serial;
volatile extern bool CW_key_dot_hard;
volatile extern bool CW_key_dash_hard;
volatile extern uint_fast16_t CW_Key_Timeout_est;
volatile extern uint_fast8_t KEYER_symbol_status;
#endif

119
STM32/Core/Src/fft.c
Wyświetl plik

@ -266,49 +266,6 @@ void FFT_bufferPrepare(void)
dc_filter(FFTInput_I_current, FFT_SIZE, DC_FILTER_FFT_I); dc_filter(FFTInput_I_current, FFT_SIZE, DC_FILTER_FFT_I);
dc_filter(FFTInput_Q_current, FFT_SIZE, DC_FILTER_FFT_Q); dc_filter(FFTInput_Q_current, FFT_SIZE, DC_FILTER_FFT_Q);
} }
//-----------------------------------------------------------------------------------------------------------------------------------------
//FFT Peaks
if(TRX.FFT_HoldPeaks)
{
uint32_t fft_y_prev = 0;
for (uint32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++)
{
uint32_t fft_y = LAY_WTF_HEIGHT - fft_peaks[fft_x];
int32_t y_diff = (int32_t)fft_y - (int32_t)fft_y_prev;
if (fft_x == 0 || (y_diff <= 1 && y_diff >= -1))
{
fft_output_buffer[fft_y][fft_x] = palette_fft[LAY_WTF_HEIGHT / 2];
}
else
{
for (uint32_t l = 0; l < (abs(y_diff / 2) + 1); l++) //draw line
{
fft_output_buffer[fft_y_prev + ((y_diff > 0) ? l : -l)][fft_x - 1] = palette_fft[LAY_WTF_HEIGHT / 2];
fft_output_buffer[fft_y + ((y_diff > 0) ? -l : l)][fft_x] = palette_fft[LAY_WTF_HEIGHT / 2];
}
}
fft_y_prev = fft_y;
}
}
//-----------------------------------------------------------------------------------------------------------------------------------------
//FFT Peaks
if(TRX.FFT_HoldPeaks)
{
if(lastWTFFreq == currentFFTFreq)
{
for (uint32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++)
if(fft_peaks[fft_x] <= fft_header[fft_x])
fft_peaks[fft_x] = fft_header[fft_x];
else if(fft_peaks[fft_x] > 0)
fft_peaks[fft_x]--;
}
else
{
for (uint32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++)
fft_peaks[fft_x] = fft_header[fft_x];
}
}
//-----------------------------------------------------------------------------------------------------------------------------------------
//ZoomFFT //ZoomFFT
if (TRX.FFT_Zoom > 1) if (TRX.FFT_Zoom > 1)
@ -460,7 +417,7 @@ void FFT_doFFT(void)
//tx noise scale limit //tx noise scale limit
if (TRX_on_TX() && maxValueFFT < FFT_TX_MIN_LEVEL) if (TRX_on_TX() && maxValueFFT < FFT_TX_MIN_LEVEL)
maxValueFFT = FFT_TX_MIN_LEVEL; maxValueFFT = FFT_TX_MIN_LEVEL;
sendToDebug_float32(maxValueFFT, false); //sendToDebug_float32(maxValueFFT, false);
// save values ​​for switching RX / TX // save values ​​for switching RX / TX
if (TRX_on_TX()) if (TRX_on_TX())
maxValueFFT_tx = maxValueFFT; maxValueFFT_tx = maxValueFFT;
@ -545,12 +502,8 @@ bool FFT_printFFT(void)
// calculate the colors for the waterfall // calculate the colors for the waterfall
for (uint32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++) for (uint32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++)
{ {
height = (uint16_t)((float32_t)FFTOutput_mean[(uint_fast16_t)fft_x] * LAY_FFT_HEIGHT); height = (uint16_t)((float32_t)FFTOutput_mean[(uint_fast16_t)fft_x] * LAY_FFT_HEIGHT);
// if(height < 10)
// height = 0;
if (height > LAY_FFT_HEIGHT) if (height > LAY_FFT_HEIGHT)
height = LAY_FFT_HEIGHT; height = LAY_FFT_HEIGHT;
@ -558,12 +511,52 @@ bool FFT_printFFT(void)
fft_header[fft_x] = height; fft_header[fft_x] = height;
indexed_wtf_buffer[0][fft_x] = LAY_FFT_HEIGHT - height; indexed_wtf_buffer[0][fft_x] = LAY_FFT_HEIGHT - height;
// if(indexed_wtf_buffer[0][fft_x] < 5)
// indexed_wtf_buffer[0][fft_x] = 0;
if (fft_x == (LAY_FFT_PRINT_SIZE / 2)) if (fft_x == (LAY_FFT_PRINT_SIZE / 2))
continue; continue;
} }
//FFT Peaks
if (TRX.FFT_HoldPeaks)
{
//peaks moving
if (lastWTFFreq != currentFFTFreq)
{
float32_t diff = (float32_t)currentFFTFreq - (float32_t)lastWTFFreq;
diff = diff / (float32_t)(FFT_HZ_IN_PIXEL * TRX.FFT_Zoom);
diff = roundf(diff);
if (diff > 0)
{
for (int32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++)
{
int32_t new_x = fft_x + (int32_t)diff;
if (new_x >= 0 && new_x < LAY_FFT_PRINT_SIZE)
fft_peaks[fft_x] = fft_peaks[new_x];
else
fft_peaks[fft_x] = 0;
}
}
else if (diff < 0)
{
for (int32_t fft_x = LAY_FFT_PRINT_SIZE - 1; fft_x >= 0; fft_x--)
{
int32_t new_x = fft_x + (int32_t)diff;
if (new_x >= 0 && new_x < LAY_FFT_PRINT_SIZE)
fft_peaks[fft_x] = fft_peaks[new_x];
else
fft_peaks[fft_x] = 0;
}
}
}
//peaks falling
for (uint32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++)
{
if (fft_peaks[fft_x] <= fft_header[fft_x])
fft_peaks[fft_x] = fft_header[fft_x];
else if (fft_peaks[fft_x] > 0)
fft_peaks[fft_x]--;
}
}
// calculate bw bar size // calculate bw bar size
switch (CurrentVFO()->Mode) switch (CurrentVFO()->Mode)
@ -627,6 +620,30 @@ bool FFT_printFFT(void)
} }
} }
} }
//FFT Peaks
if (TRX.FFT_HoldPeaks)
{
uint32_t fft_y_prev = 0;
for (uint32_t fft_x = 0; fft_x < LAY_FFT_PRINT_SIZE; fft_x++)
{
uint32_t fft_y = LAY_FFT_HEIGHT - fft_peaks[fft_x];
int32_t y_diff = (int32_t)fft_y - (int32_t)fft_y_prev;
if (fft_x == 0 || (y_diff <= 1 && y_diff >= -1))
{
fft_output_buffer[fft_y][fft_x] = palette_fft[LAY_FFT_HEIGHT / 2];
}
else
{
for (uint32_t l = 0; l < (abs(y_diff / 2) + 1); l++) //draw line
{
fft_output_buffer[fft_y_prev + ((y_diff > 0) ? l : -l)][fft_x - 1] = palette_fft[LAY_FFT_HEIGHT / 2];
fft_output_buffer[fft_y + ((y_diff > 0) ? -l : l)][fft_x] = palette_fft[LAY_FFT_HEIGHT / 2];
}
}
fft_y_prev = fft_y;
}
}
//draw grids //draw grids
if (TRX.FFT_Grid == 1 || TRX.FFT_Grid == 2) if (TRX.FFT_Grid == 1 || TRX.FFT_Grid == 2)

15
STM32/Core/Src/functions.c
Wyświetl plik

@ -73,7 +73,7 @@ void readHalfFromCircleUSBBuffer16Bit(uint8_t *source, int32_t *dest, uint32_t i
{ {
for (uint_fast16_t i = (index - halflen); i < index; i++) for (uint_fast16_t i = (index - halflen); i < index; i++)
{ {
dest[readed_index] = (source[i * 2 + 0] << 16) | (source[i * 2 + 1] << 24); dest[readed_index] = (source[i * 2 + 0] << 0) | (source[i * 2 + 1] << 8);
readed_index++; readed_index++;
} }
} }
@ -82,12 +82,12 @@ void readHalfFromCircleUSBBuffer16Bit(uint8_t *source, int32_t *dest, uint32_t i
uint_fast16_t prev_part = halflen - index; uint_fast16_t prev_part = halflen - index;
for (uint_fast16_t i = (length - prev_part); i < length; i++) for (uint_fast16_t i = (length - prev_part); i < length; i++)
{ {
dest[readed_index] = (source[i * 2 + 0] << 16) | (source[i * 2 + 1] << 24); dest[readed_index] = (source[i * 2 + 0] << 0) | (source[i * 2 + 1] << 8);
readed_index++; readed_index++;
} }
for (uint_fast16_t i = 0; i < (halflen - prev_part); i++) for (uint_fast16_t i = 0; i < (halflen - prev_part); i++)
{ {
dest[readed_index] = (source[i * 2 + 0] << 16) | (source[i * 2 + 1] << 24); dest[readed_index] = (source[i * 2 + 0] << 0) | (source[i * 2 + 1] << 8);
readed_index++; readed_index++;
} }
} }
@ -362,6 +362,15 @@ float32_t generateSin(float32_t amplitude, uint32_t index, uint32_t samplerate,
return ret; return ret;
} }
float32_t generateSinF(float32_t amplitude, float32_t *index, uint32_t samplerate, uint32_t freq)
{
float32_t ret = amplitude * arm_sin_f32(*index * (2.0f * F_PI));
*index += ((float32_t)freq / (float32_t)samplerate);
while (*index >= 1.0f)
*index -= 1.0f;
return ret;
}
static uint32_t CPULOAD_startWorkTime = 0; static uint32_t CPULOAD_startWorkTime = 0;
static uint32_t CPULOAD_startSleepTime = 0; static uint32_t CPULOAD_startSleepTime = 0;
static uint32_t CPULOAD_WorkingTime = 0; static uint32_t CPULOAD_WorkingTime = 0;

1
STM32/Core/Src/functions.h
Wyświetl plik

@ -138,6 +138,7 @@ extern void shiftTextLeft(char *string, uint_fast16_t shiftLength);
extern float32_t getMaxTXAmplitudeOnFreq(uint32_t freq); extern float32_t getMaxTXAmplitudeOnFreq(uint32_t freq);
//extern uint16_t getf_calibrate(uint16_t freq); //extern uint16_t getf_calibrate(uint16_t freq);
extern float32_t generateSin(float32_t amplitude, uint32_t index, uint32_t samplerate, uint32_t freq); extern float32_t generateSin(float32_t amplitude, uint32_t index, uint32_t samplerate, uint32_t freq);
extern float32_t generateSinF(float32_t amplitude, float32_t *index, uint32_t samplerate, uint32_t freq);
extern int32_t convertToSPIBigEndian(int32_t in); extern int32_t convertToSPIBigEndian(int32_t in);
extern uint8_t rev8(uint8_t data); extern uint8_t rev8(uint8_t data);
extern bool SPI_Transmit(uint8_t *out_data, uint8_t *in_data, uint16_t count, GPIO_TypeDef *CS_PORT, uint16_t CS_PIN, bool hold_cs, uint32_t prescaler); extern bool SPI_Transmit(uint8_t *out_data, uint8_t *in_data, uint16_t count, GPIO_TypeDef *CS_PORT, uint16_t CS_PIN, bool hold_cs, uint32_t prescaler);

199
STM32/Core/Src/main.c
Wyświetl plik

@ -58,6 +58,7 @@
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2; ADC_HandleTypeDef hadc2;
ADC_HandleTypeDef hadc3;
I2S_HandleTypeDef hi2s3; I2S_HandleTypeDef hi2s3;
DMA_HandleTypeDef hdma_spi3_tx; DMA_HandleTypeDef hdma_spi3_tx;
@ -107,6 +108,7 @@ static void MX_TIM5_Init(void);
static void MX_TIM6_Init(void); static void MX_TIM6_Init(void);
static void MX_TIM7_Init(void); static void MX_TIM7_Init(void);
static void MX_TIM8_Init(void); static void MX_TIM8_Init(void);
static void MX_ADC3_Init(void);
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
/* USER CODE END PFP */ /* USER CODE END PFP */
@ -161,12 +163,12 @@ int main(void)
MX_TIM6_Init(); MX_TIM6_Init();
MX_TIM7_Init(); MX_TIM7_Init();
MX_TIM8_Init(); MX_TIM8_Init();
MX_ADC3_Init();
/* USER CODE BEGIN 2 */ /* USER CODE BEGIN 2 */
//HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_3); //LCD PWM
//TIM4->CCR3 = 500; //LCD PWM
/* BUG FIX: Enabling Audio Clock Input in CubeMX does not set I2SSRC bit /* BUG FIX: Enabling Audio Clock Input in CubeMX does not set I2SSRC bit
* in RCC_CFGR register! Hence we need to set it manually here! * WARNING: A bug fix is also needed in __HAL_RCC_GET_I2S_SOURCE() * in RCC_CFGR register! Hence we need to set it manually here! * WARNING: A bug fix is also needed in __HAL_RCC_GET_I2S_SOURCE()
Line 6131 stm32f4xx_hal_rcc_ex.h -> #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) >> RCC_CFGR_I2SSRC_Pos) Line 6115 stm32f4xx_hal_rcc_ex.h -> #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) >> RCC_CFGR_I2SSRC_Pos)
*/ */
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
@ -244,7 +246,6 @@ int main(void)
sendToDebug_str("UA3REO Transceiver started!\r\n\r\n"); sendToDebug_str("UA3REO Transceiver started!\r\n\r\n");
/* USER CODE END 2 */ /* USER CODE END 2 */
//TIM4->CCR3 = TRX.LCD_Brightness*5; //LCD PWM
/* Infinite loop */ /* Infinite loop */
/* USER CODE BEGIN WHILE */ /* USER CODE BEGIN WHILE */
while (1) while (1)
@ -267,7 +268,6 @@ void SystemClock_Config(void)
{ {
RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Configure the main internal regulator output voltage /** Configure the main internal regulator output voltage
*/ */
@ -302,12 +302,6 @@ void SystemClock_Config(void)
{ {
Error_Handler(); Error_Handler();
} }
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
} }
/** /**
@ -331,7 +325,7 @@ static void MX_ADC1_Init(void)
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/ */
hadc1.Instance = ADC1; hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
hadc1.Init.Resolution = ADC_RESOLUTION_12B; hadc1.Init.Resolution = ADC_RESOLUTION_12B;
hadc1.Init.ScanConvMode = ENABLE; hadc1.Init.ScanConvMode = ENABLE;
hadc1.Init.ContinuousConvMode = ENABLE; hadc1.Init.ContinuousConvMode = ENABLE;
@ -348,18 +342,18 @@ static void MX_ADC1_Init(void)
} }
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/ */
sConfig.Channel = ADC_CHANNEL_10; sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
sConfig.Rank = 1; sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; sConfig.SamplingTime = ADC_SAMPLETIME_28CYCLES;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{ {
Error_Handler(); Error_Handler();
} }
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time /** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/ */
sConfigInjected.InjectedChannel = ADC_CHANNEL_11; sConfigInjected.InjectedChannel = ADC_CHANNEL_TEMPSENSOR;
sConfigInjected.InjectedRank = 1; sConfigInjected.InjectedRank = 1;
sConfigInjected.InjectedNbrOfConversion = 4; sConfigInjected.InjectedNbrOfConversion = 3;
sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_28CYCLES; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_28CYCLES;
sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONVEDGE_RISING; sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONVEDGE_RISING;
sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T4_TRGO; sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T4_TRGO;
@ -372,7 +366,7 @@ static void MX_ADC1_Init(void)
} }
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time /** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/ */
sConfigInjected.InjectedChannel = ADC_CHANNEL_10; sConfigInjected.InjectedChannel = ADC_CHANNEL_VREFINT;
sConfigInjected.InjectedRank = 2; sConfigInjected.InjectedRank = 2;
if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK) if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
{ {
@ -380,20 +374,12 @@ static void MX_ADC1_Init(void)
} }
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time /** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/ */
sConfigInjected.InjectedChannel = ADC_CHANNEL_8; sConfigInjected.InjectedChannel = ADC_CHANNEL_VBAT;
sConfigInjected.InjectedRank = 3; sConfigInjected.InjectedRank = 3;
if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK) if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
{ {
Error_Handler(); Error_Handler();
} }
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/
sConfigInjected.InjectedChannel = ADC_CHANNEL_9;
sConfigInjected.InjectedRank = 4;
if (HAL_ADCEx_InjectedConfigChannel(&hadc1, &sConfigInjected) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC1_Init 2 */ /* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */ /* USER CODE END ADC1_Init 2 */
@ -421,7 +407,7 @@ static void MX_ADC2_Init(void)
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/ */
hadc2.Instance = ADC2; hadc2.Instance = ADC2;
hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
hadc2.Init.Resolution = ADC_RESOLUTION_12B; hadc2.Init.Resolution = ADC_RESOLUTION_12B;
hadc2.Init.ScanConvMode = ENABLE; hadc2.Init.ScanConvMode = ENABLE;
hadc2.Init.ContinuousConvMode = ENABLE; hadc2.Init.ContinuousConvMode = ENABLE;
@ -449,7 +435,7 @@ static void MX_ADC2_Init(void)
*/ */
sConfigInjected.InjectedChannel = ADC_CHANNEL_14; sConfigInjected.InjectedChannel = ADC_CHANNEL_14;
sConfigInjected.InjectedRank = 1; sConfigInjected.InjectedRank = 1;
sConfigInjected.InjectedNbrOfConversion = 2; sConfigInjected.InjectedNbrOfConversion = 4;
sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_28CYCLES; sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_28CYCLES;
sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONVEDGE_RISING; sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONVEDGE_RISING;
sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T4_TRGO; sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T4_TRGO;
@ -468,12 +454,102 @@ static void MX_ADC2_Init(void)
{ {
Error_Handler(); Error_Handler();
} }
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/
sConfigInjected.InjectedChannel = ADC_CHANNEL_8;
sConfigInjected.InjectedRank = 3;
if (HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected) != HAL_OK)
{
Error_Handler();
}
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/
sConfigInjected.InjectedChannel = ADC_CHANNEL_9;
sConfigInjected.InjectedRank = 4;
if (HAL_ADCEx_InjectedConfigChannel(&hadc2, &sConfigInjected) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC2_Init 2 */ /* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */ /* USER CODE END ADC2_Init 2 */
} }
/**
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
ADC_InjectionConfTypeDef sConfigInjected = {0};
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc3.Instance = ADC3;
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
hadc3.Init.ScanConvMode = ENABLE;
hadc3.Init.ContinuousConvMode = ENABLE;
hadc3.Init.DiscontinuousConvMode = DISABLE;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc3.Init.NbrOfConversion = 1;
hadc3.Init.DMAContinuousRequests = DISABLE;
hadc3.Init.EOCSelection = ADC_EOC_SEQ_CONV;
if (HAL_ADC_Init(&hadc3) != HAL_OK)
{
Error_Handler();
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_10;
sConfig.Rank = 1;
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/
sConfigInjected.InjectedChannel = ADC_CHANNEL_10;
sConfigInjected.InjectedRank = 1;
sConfigInjected.InjectedNbrOfConversion = 2;
sConfigInjected.InjectedSamplingTime = ADC_SAMPLETIME_28CYCLES;
sConfigInjected.ExternalTrigInjecConvEdge = ADC_EXTERNALTRIGINJECCONVEDGE_RISING;
sConfigInjected.ExternalTrigInjecConv = ADC_EXTERNALTRIGINJECCONV_T4_TRGO;
sConfigInjected.AutoInjectedConv = DISABLE;
sConfigInjected.InjectedDiscontinuousConvMode = DISABLE;
sConfigInjected.InjectedOffset = 0;
if (HAL_ADCEx_InjectedConfigChannel(&hadc3, &sConfigInjected) != HAL_OK)
{
Error_Handler();
}
/** Configures for the selected ADC injected channel its corresponding rank in the sequencer and its sample time
*/
sConfigInjected.InjectedChannel = ADC_CHANNEL_11;
sConfigInjected.InjectedRank = 2;
if (HAL_ADCEx_InjectedConfigChannel(&hadc3, &sConfigInjected) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
/** /**
* @brief I2S3 Initialization Function * @brief I2S3 Initialization Function
* @param None * @param None
@ -630,24 +706,23 @@ static void MX_TIM3_Init(void)
* @param None * @param None
* @retval None * @retval None
*/ */
static void MX_TIM4_Init(void) //LCD PWM static void MX_TIM4_Init(void)
{ {
/* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE BEGIN TIM4_Init 0 */
/* USER CODE END TIM3_Init 0 */ /* USER CODE END TIM4_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0}; TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0}; TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
/* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE BEGIN TIM4_Init 1 */
/* USER CODE END TIM3_Init 1 */ /* USER CODE END TIM4_Init 1 */
htim4.Instance = TIM4; htim4.Instance = TIM4;
htim4.Init.Prescaler = 32-1; htim4.Init.Prescaler = 64-1;
htim4.Init.CounterMode = TIM_COUNTERMODE_UP; htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
htim4.Init.Period = 500-1; htim4.Init.Period = 500;
htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim4) != HAL_OK) if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
@ -659,28 +734,15 @@ static void MX_TIM4_Init(void) //LCD PWM
{ {
Error_Handler(); Error_Handler();
} }
if (HAL_TIM_PWM_Init(&htim4) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE; sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
{ {
Error_Handler(); Error_Handler();
} }
sConfigOC.OCMode = TIM_OCMODE_PWM1; /* USER CODE BEGIN TIM4_Init 2 */
sConfigOC.Pulse = 0;
sConfigOC.OCPolarity = TIM_OCPOLARITY_LOW;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */ /* USER CODE END TIM4_Init 2 */
HAL_TIM_MspPostInit(&htim4);
} }
@ -1104,7 +1166,7 @@ static void MX_GPIO_Init(void)
|FPGA_BUS_D4_Pin|FPGA_BUS_D5_Pin|FPGA_BUS_D6_Pin|FPGA_BUS_D7_Pin, GPIO_PIN_RESET); |FPGA_BUS_D4_Pin|FPGA_BUS_D5_Pin|FPGA_BUS_D6_Pin|FPGA_BUS_D7_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */ /*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(W25Q16_CS_GPIO_Port, W25Q16_CS_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOB, W25Q16_CS_Pin|LCD_BL_PWM_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */ /*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOD, WM8731_SCK_Pin|WM8731_SDA_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOD, WM8731_SCK_Pin|WM8731_SDA_Pin, GPIO_PIN_RESET);
@ -1118,11 +1180,11 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pin : ENC_CLK_Pin */ /*Configure GPIO pins : ENC_CLK_Pin KEY_IN_DASH_Pin KEY_IN_DOT_Pin */
GPIO_InitStruct.Pin = ENC_CLK_Pin; GPIO_InitStruct.Pin = ENC_CLK_Pin|KEY_IN_DASH_Pin|KEY_IN_DOT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(ENC_CLK_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
/*Configure GPIO pins : ENC2_SW_Pin ENC_DT_Pin ENC2_DT_Pin */ /*Configure GPIO pins : ENC2_SW_Pin ENC_DT_Pin ENC2_DT_Pin */
GPIO_InitStruct.Pin = ENC2_SW_Pin|ENC_DT_Pin|ENC2_DT_Pin; GPIO_InitStruct.Pin = ENC2_SW_Pin|ENC_DT_Pin|ENC2_DT_Pin;
@ -1158,16 +1220,14 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(PTT_IN_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(PTT_IN_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : AUDIO_48K_CLOCK_Pin CPU_PW_Pin */ /*Configure GPIO pin : AUDIO_48K_CLOCK_Pin */
GPIO_InitStruct.Pin = AUDIO_48K_CLOCK_Pin|CPU_PW_Pin; GPIO_InitStruct.Pin = AUDIO_48K_CLOCK_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(AUDIO_48K_CLOCK_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : PB11 PB4 PB5 PB8 /*Configure GPIO pins : PB11 PB4 PB5 PB9 */
PB9 */ GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_9;
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_8
|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
@ -1219,11 +1279,18 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pins : KEY_IN_DASH_Pin KEY_IN_DOT_Pin */ /*Configure GPIO pin : CPU_PW_Pin */
GPIO_InitStruct.Pin = KEY_IN_DASH_Pin|KEY_IN_DOT_Pin; GPIO_InitStruct.Pin = CPU_PW_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
GPIO_InitStruct.Pull = GPIO_PULLUP; GPIO_InitStruct.Pull = GPIO_PULLUP;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); HAL_GPIO_Init(CPU_PW_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : LCD_BL_PWM_Pin */
GPIO_InitStruct.Pin = LCD_BL_PWM_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(LCD_BL_PWM_GPIO_Port, &GPIO_InitStruct);
/* EXTI interrupt init*/ /* EXTI interrupt init*/
HAL_NVIC_SetPriority(EXTI0_IRQn, 6, 0); HAL_NVIC_SetPriority(EXTI0_IRQn, 6, 0);

31
STM32/Core/Src/rf_unit.c
Wyświetl plik

@ -38,21 +38,38 @@ static const int16_t KTY81_120_sensTable[SENS_TABLE_COUNT][2] = { // table of se
{130, 2023}, {130, 2023},
{140, 2124}, {140, 2124},
{150, 2211}}; {150, 2211}};
void RF_UNIT_ProcessSensors(void) void RF_UNIT_ProcessSensors(void)
{ {
//SWR //Get Data from ADC
float32_t forward = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc1, ADC_INJECTED_RANK_2)) * 3.3f / 4096.0f; float32_t cpu_temperature = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc1, ADC_INJECTED_RANK_1)) * 3.3f / 4096.0f;
float32_t backward = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc1, ADC_INJECTED_RANK_1)) * 3.3f / 4096.0f; float32_t cpu_vref = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc1, ADC_INJECTED_RANK_2));
float32_t ptt_sw1 = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc1, ADC_INJECTED_RANK_3)) * 3.3f / 4096.0f; float32_t cpu_vbat = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc1, ADC_INJECTED_RANK_3)) * 3.3f / 4096.0f;
float32_t ptt_sw2 = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc1, ADC_INJECTED_RANK_4)) * 3.3f / 4096.0f;
float32_t alc = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc2, ADC_INJECTED_RANK_2)) * 3.3f / 4096.0f;
float32_t power_in = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc2, ADC_INJECTED_RANK_1)) * 3.3f / 4096.0f; float32_t power_in = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc2, ADC_INJECTED_RANK_1)) * 3.3f / 4096.0f;
float32_t alc = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc2, ADC_INJECTED_RANK_2)) * 3.3f / 4096.0f;
float32_t ptt_sw1 = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc2, ADC_INJECTED_RANK_3)) * 3.3f / 4096.0f;
float32_t ptt_sw2 = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc2, ADC_INJECTED_RANK_4)) * 3.3f / 4096.0f;
float32_t forward = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc3, ADC_INJECTED_RANK_1)) * 3.3f / 4096.0f;
float32_t backward = (float32_t)(HAL_ADCEx_InjectedGetValue(&hadc3, ADC_INJECTED_RANK_2)) * 3.3f / 4096.0f;
//CPU Sensors
float32_t cpu_temperature_result = (cpu_temperature - 0.760f) / 0.0025f + 25.0f;
TRX_CPU_temperature = TRX_CPU_temperature * 0.9f + cpu_temperature_result * 0.1f;
uint16_t VREFINT_CAL = *VREFINT_CAL_ADDR;
float32_t cpu_vref_result = 3.3f * (float32_t)VREFINT_CAL / (float32_t)cpu_vref;
TRX_CPU_VRef = TRX_CPU_VRef * 0.9f + cpu_vref_result * 0.1f;
TRX_CPU_VBat = TRX_CPU_VBat * 0.9f + cpu_vbat * 2.0f * 0.1f;
//POWER
power_in = power_in * CALIBRATE.volt_cal_rate; //do voltage calibration in future!!! power_in = power_in * CALIBRATE.volt_cal_rate; //do voltage calibration in future!!!
if(fabsf(TRX_InVoltage - power_in) > 0.2f) if(fabsf(TRX_InVoltage - power_in) > 0.2f)
TRX_InVoltage = power_in; TRX_InVoltage = power_in;
//SWR
static float32_t TRX_VLT_forward = 0.0f; static float32_t TRX_VLT_forward = 0.0f;
static float32_t TRX_VLT_backward = 0.0f; static float32_t TRX_VLT_backward = 0.0f;
forward = forward / (1510.0f / (0.1f + 1510.0f)); // adjust the voltage based on the voltage divider (0.1 ohm and 510 ohm) forward = forward / (1510.0f / (0.1f + 1510.0f)); // adjust the voltage based on the voltage divider (0.1 ohm and 510 ohm)

106
STM32/Core/Src/stm32f4xx_hal_msp.c
Wyświetl plik

@ -61,7 +61,6 @@ extern DMA_HandleTypeDef hdma_i2s3_ext_rx;
/* USER CODE BEGIN 0 */ /* USER CODE BEGIN 0 */
/* USER CODE END 0 */ /* USER CODE END 0 */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/** /**
* Initializes the Global MSP. * Initializes the Global MSP.
*/ */
@ -103,7 +102,6 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
/**ADC1 GPIO Configuration /**ADC1 GPIO Configuration
PC0 ------> ADC1_IN10 PC0 ------> ADC1_IN10
PC1 ------> ADC1_IN11 PC1 ------> ADC1_IN11
PB0 ------> ADC1_IN8
PB1 ------> ADC1_IN9 PB1 ------> ADC1_IN9
*/ */
GPIO_InitStruct.Pin = SWR_FORW_Pin|SWR_BACKW_Pin; GPIO_InitStruct.Pin = SWR_FORW_Pin|SWR_BACKW_Pin;
@ -111,10 +109,10 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = PTT_SW1_Pin|PTT_SW2_Pin; GPIO_InitStruct.Pin = PTT_SW2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(PTT_SW2_GPIO_Port, &GPIO_InitStruct);
/* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE BEGIN ADC1_MspInit 1 */
@ -129,19 +127,51 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
__HAL_RCC_ADC2_CLK_ENABLE(); __HAL_RCC_ADC2_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**ADC2 GPIO Configuration /**ADC2 GPIO Configuration
PC0 ------> ADC2_IN10
PC1 ------> ADC2_IN11
PC4 ------> ADC2_IN14 PC4 ------> ADC2_IN14
PC5 ------> ADC2_IN15 PC5 ------> ADC2_IN15
PB0 ------> ADC2_IN8
PB1 ------> ADC2_IN9
*/ */
GPIO_InitStruct.Pin = Power_IN_Pin|ALC_IN_Pin; GPIO_InitStruct.Pin = SWR_FORW_Pin|SWR_BACKW_Pin|Power_IN_Pin|ALC_IN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = PTT_SW1_Pin|PTT_SW2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */
} }
else if(hadc->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspInit 0 */
/* USER CODE END ADC3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ADC3_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
/**ADC3 GPIO Configuration
PC0 ------> ADC3_IN10
PC1 ------> ADC3_IN11
*/
GPIO_InitStruct.Pin = SWR_FORW_Pin|SWR_BACKW_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
} }
@ -164,12 +194,11 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
/**ADC1 GPIO Configuration /**ADC1 GPIO Configuration
PC0 ------> ADC1_IN10 PC0 ------> ADC1_IN10
PC1 ------> ADC1_IN11 PC1 ------> ADC1_IN11
PB0 ------> ADC1_IN8
PB1 ------> ADC1_IN9 PB1 ------> ADC1_IN9
*/ */
HAL_GPIO_DeInit(GPIOC, SWR_FORW_Pin|SWR_BACKW_Pin); HAL_GPIO_DeInit(GPIOC, SWR_FORW_Pin|SWR_BACKW_Pin);
HAL_GPIO_DeInit(GPIOB, PTT_SW1_Pin|PTT_SW2_Pin); HAL_GPIO_DeInit(PTT_SW2_GPIO_Port, PTT_SW2_Pin);
/* USER CODE BEGIN ADC1_MspDeInit 1 */ /* USER CODE BEGIN ADC1_MspDeInit 1 */
@ -184,15 +213,39 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
__HAL_RCC_ADC2_CLK_DISABLE(); __HAL_RCC_ADC2_CLK_DISABLE();
/**ADC2 GPIO Configuration /**ADC2 GPIO Configuration
PC0 ------> ADC2_IN10
PC1 ------> ADC2_IN11
PC4 ------> ADC2_IN14 PC4 ------> ADC2_IN14
PC5 ------> ADC2_IN15 PC5 ------> ADC2_IN15
PB0 ------> ADC2_IN8
PB1 ------> ADC2_IN9
*/ */
HAL_GPIO_DeInit(GPIOC, Power_IN_Pin|ALC_IN_Pin); HAL_GPIO_DeInit(GPIOC, SWR_FORW_Pin|SWR_BACKW_Pin|Power_IN_Pin|ALC_IN_Pin);
HAL_GPIO_DeInit(GPIOB, PTT_SW1_Pin|PTT_SW2_Pin);
/* USER CODE BEGIN ADC2_MspDeInit 1 */ /* USER CODE BEGIN ADC2_MspDeInit 1 */
/* USER CODE END ADC2_MspDeInit 1 */ /* USER CODE END ADC2_MspDeInit 1 */
} }
else if(hadc->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspDeInit 0 */
/* USER CODE END ADC3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_ADC3_CLK_DISABLE();
/**ADC3 GPIO Configuration
PC0 ------> ADC3_IN10
PC1 ------> ADC3_IN11
*/
HAL_GPIO_DeInit(GPIOC, SWR_FORW_Pin|SWR_BACKW_Pin);
/* USER CODE BEGIN ADC3_MspDeInit 1 */
/* USER CODE END ADC3_MspDeInit 1 */
}
} }
@ -347,11 +400,21 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef* hi2s)
*/ */
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{ {
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(hrtc->Instance==RTC) if(hrtc->Instance==RTC)
{ {
/* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE BEGIN RTC_MspInit 0 */
/* USER CODE END RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */ /* Peripheral clock enable */
__HAL_RCC_RTC_ENABLE(); __HAL_RCC_RTC_ENABLE();
/* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE BEGIN RTC_MspInit 1 */
@ -545,33 +608,6 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
} }
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(htim->Instance==TIM4)
{
/* USER CODE BEGIN TIM4_MspPostInit 0 */
/* USER CODE END TIM4_MspPostInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
/**TIM4 GPIO Configuration
PB4 (NJTRST) ------> TIM4_CH3
*/
GPIO_InitStruct.Pin = GPIO_PIN_8;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF2_TIM4;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN TIM4_MspPostInit 3 */
/* USER CODE END TIM4_MspPostInit 3 */
}
}
/** /**
* @brief TIM_Base MSP De-Initialization * @brief TIM_Base MSP De-Initialization
* This function freeze the hardware resources used in this example * This function freeze the hardware resources used in this example

23
STM32/Core/Src/stm32f4xx_it.c
Wyświetl plik

@ -104,6 +104,7 @@
#include "system_menu.h" #include "system_menu.h"
#include "bootloader.h" #include "bootloader.h"
#include "swr_analyzer.h" #include "swr_analyzer.h"
#include "cw.h"
static uint32_t ms10_counter = 0; static uint32_t ms10_counter = 0;
static uint32_t tim6_delay = 0; static uint32_t tim6_delay = 0;
@ -517,12 +518,12 @@ void TIM6_DAC_IRQHandler(void)
ms10_counter++; ms10_counter++;
// transmission release time after key signal // transmission release time after key signal
if (TRX_Key_Timeout_est > 0 && !TRX_key_serial && !TRX_key_dot_hard && !TRX_key_dash_hard) if (CW_Key_Timeout_est > 0 && !CW_key_serial && !CW_key_dot_hard && !CW_key_dash_hard)
{ {
TRX_Key_Timeout_est -= 10; CW_Key_Timeout_est -= 10;
if (TRX_Key_Timeout_est == 0) if (CW_Key_Timeout_est == 0)
{ {
LCD_UpdateQuery.StatusInfoGUI = true; LCD_UpdateQuery.StatusInfoGUIRedraw = true;
FPGA_NeedSendParams = true; FPGA_NeedSendParams = true;
TRX_Restart_Mode(); TRX_Restart_Mode();
} }
@ -546,8 +547,8 @@ void TIM6_DAC_IRQHandler(void)
TRX_ptt_change(); TRX_ptt_change();
// emulate the key via the COM port // emulate the key via the COM port
if (TRX_key_serial != TRX_old_key_serial) if (CW_key_serial != CW_old_key_serial)
TRX_key_change(); CW_key_change();
if ((ms10_counter % 10) == 0) // every 100ms if ((ms10_counter % 10) == 0) // every 100ms
{ {
@ -653,6 +654,12 @@ void TIM6_DAC_IRQHandler(void)
sendToDebug_str(" / "); sendToDebug_str(" / ");
sendToDebug_int16(TRX_ADC_MAXAMPLITUDE, false); sendToDebug_int16(TRX_ADC_MAXAMPLITUDE, false);
sendToDebug_newline(); sendToDebug_newline();
sendToDebug_str("CPU Temperature: ");
sendToDebug_float32(TRX_CPU_temperature, true);
sendToDebug_str(" VRef: ");
sendToDebug_float32(TRX_CPU_VRef, true);
sendToDebug_str(" VBat: ");
sendToDebug_float32(TRX_CPU_VBat, false);
PrintProfilerResult(); PrintProfilerResult();
} }
@ -851,11 +858,11 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
} }
else if (GPIO_Pin == GPIO_PIN_1) //KEY DOT else if (GPIO_Pin == GPIO_PIN_1) //KEY DOT
{ {
TRX_key_change(); CW_key_change();
} }
else if (GPIO_Pin == GPIO_PIN_0) //KEY DASH else if (GPIO_Pin == GPIO_PIN_0) //KEY DASH
{ {
TRX_key_change(); CW_key_change();
} }
else if (GPIO_Pin == GPIO_PIN_7) //POWER OFF else if (GPIO_Pin == GPIO_PIN_7) //POWER OFF
{ {

2
STM32/Core/Src/system_menu.c
Wyświetl plik

@ -244,7 +244,7 @@ static const struct sysmenu_item_handler sysmenu_screen_handlers[] =
{"7.FFT Compressor", SYSMENU_BOOLEAN, (uint32_t *)&TRX.FFT_Compressor, SYSMENU_HANDL_SCREEN_FFT_Compressor}, {"7.FFT Compressor", SYSMENU_BOOLEAN, (uint32_t *)&TRX.FFT_Compressor, SYSMENU_HANDL_SCREEN_FFT_Compressor},
{"8.FFT Averaging", SYSMENU_UINT8, (uint32_t *)&TRX.FFT_Averaging, SYSMENU_HANDL_SCREEN_FFT_Averaging}, {"8.FFT Averaging", SYSMENU_UINT8, (uint32_t *)&TRX.FFT_Averaging, SYSMENU_HANDL_SCREEN_FFT_Averaging},
{"9.FFT Window", SYSMENU_UINT8, (uint32_t *)&TRX.FFT_Window, SYSMENU_HANDL_SCREEN_FFT_Window}, {"9.FFT Window", SYSMENU_UINT8, (uint32_t *)&TRX.FFT_Window, SYSMENU_HANDL_SCREEN_FFT_Window},
//{"FFT Hold Peaks", SYSMENU_BOOLEAN, (uint32_t *)&TRX.FFT_HoldPeaks, SYSMENU_HANDL_SCREEN_FFT_HoldPeaks}, {"10.FFT Hold Peaks", SYSMENU_BOOLEAN, (uint32_t *)&TRX.FFT_HoldPeaks, SYSMENU_HANDL_SCREEN_FFT_HoldPeaks},
}; };
static const uint8_t sysmenu_screen_item_count = sizeof(sysmenu_screen_handlers) / sizeof(sysmenu_screen_handlers[0]); static const uint8_t sysmenu_screen_item_count = sizeof(sysmenu_screen_handlers) / sizeof(sysmenu_screen_handlers[0]);

191
STM32/Core/Src/trx_manager.c
Wyświetl plik

@ -14,15 +14,11 @@
#include "front_unit.h" #include "front_unit.h"
#include "rf_unit.h" #include "rf_unit.h"
#include "system_menu.h" #include "system_menu.h"
#include "cw.h"
volatile bool TRX_ptt_hard = false; volatile bool TRX_ptt_hard = false;
volatile bool TRX_ptt_soft = false; volatile bool TRX_ptt_soft = false;
volatile bool TRX_old_ptt_soft = false; volatile bool TRX_old_ptt_soft = false;
volatile bool TRX_key_serial = false;
volatile bool TRX_old_key_serial = false;
volatile bool TRX_key_dot_hard = false;
volatile bool TRX_key_dash_hard = false;
volatile uint_fast16_t TRX_Key_Timeout_est = 0;
volatile bool TRX_RX_IQ_swap = false; volatile bool TRX_RX_IQ_swap = false;
volatile bool TRX_TX_IQ_swap = false; volatile bool TRX_TX_IQ_swap = false;
volatile bool TRX_Tune = false; volatile bool TRX_Tune = false;
@ -42,7 +38,6 @@ volatile float32_t TRX_ALC = 0;
static uint_fast8_t autogain_wait_reaction = 0; // timer for waiting for a reaction from changing the ATT / PRE modes static uint_fast8_t autogain_wait_reaction = 0; // timer for waiting for a reaction from changing the ATT / PRE modes
volatile uint8_t TRX_AutoGain_Stage = 0; // stage of working out the amplification corrector volatile uint8_t TRX_AutoGain_Stage = 0; // stage of working out the amplification corrector
static uint32_t KEYER_symbol_start_time = 0; // start time of the automatic key character static uint32_t KEYER_symbol_start_time = 0; // start time of the automatic key character
static uint_fast8_t KEYER_symbol_status = 0; // status (signal or period) of the automatic key symbol
volatile float32_t TRX_IQ_phase_error = 0.0f; volatile float32_t TRX_IQ_phase_error = 0.0f;
volatile bool TRX_NeedGoToBootloader = false; volatile bool TRX_NeedGoToBootloader = false;
volatile bool TRX_Temporary_Stop_BandMap = false; volatile bool TRX_Temporary_Stop_BandMap = false;
@ -50,7 +45,11 @@ volatile bool TRX_Mute = false;
volatile uint32_t TRX_Temporary_Mute_StartTime = 0; volatile uint32_t TRX_Temporary_Mute_StartTime = 0;
uint32_t TRX_freq_phrase = 0; uint32_t TRX_freq_phrase = 0;
uint32_t TRX_freq_phrase_tx = 0; uint32_t TRX_freq_phrase_tx = 0;
float32_t TRX_InVoltage = 12.0f; float32_t TRX_InVoltage = 12.0f;
float32_t TRX_CPU_temperature = 0.0f;
float32_t TRX_CPU_VRef = 0.0f;
float32_t TRX_CPU_VBat = 0.0f;
static void TRX_Start_RX(void); static void TRX_Start_RX(void);
static void TRX_Start_TX(void); static void TRX_Start_TX(void);
@ -58,7 +57,7 @@ static void TRX_Start_TXRX(void);
bool TRX_on_TX(void) bool TRX_on_TX(void)
{ {
if (TRX_ptt_hard || TRX_ptt_soft || TRX_Tune || CurrentVFO()->Mode == TRX_MODE_LOOPBACK || TRX_Key_Timeout_est > 0) if (TRX_ptt_hard || TRX_ptt_soft || TRX_Tune || CurrentVFO()->Mode == TRX_MODE_LOOPBACK || CW_Key_Timeout_est > 0)
return true; return true;
return false; return false;
} }
@ -73,6 +72,7 @@ void TRX_Init()
TRX_setMode(saved_mode, CurrentVFO()); TRX_setMode(saved_mode, CurrentVFO());
HAL_ADCEx_InjectedStart(&hadc1); HAL_ADCEx_InjectedStart(&hadc1);
HAL_ADCEx_InjectedStart(&hadc2); HAL_ADCEx_InjectedStart(&hadc2);
HAL_ADCEx_InjectedStart(&hadc3);
} }
void TRX_Restart_Mode() void TRX_Restart_Mode()
@ -139,47 +139,6 @@ void TRX_ptt_change(void)
} }
} }
void TRX_key_change(void)
{
if (TRX_Tune)
return;
if (CurrentVFO()->Mode != TRX_MODE_CW_L && CurrentVFO()->Mode != TRX_MODE_CW_U)
return;
bool TRX_new_key_dot_hard = !HAL_GPIO_ReadPin(KEY_IN_DOT_GPIO_Port, KEY_IN_DOT_Pin);
if (TRX_key_dot_hard != TRX_new_key_dot_hard)
{
TRX_key_dot_hard = TRX_new_key_dot_hard;
if (TRX_key_dot_hard == true && (KEYER_symbol_status == 0 || !TRX.CW_KEYER))
{
TRX_Key_Timeout_est = TRX.CW_Key_timeout;
LCD_UpdateQuery.StatusInfoGUIRedraw = true;
FPGA_NeedSendParams = true;
TRX_Restart_Mode();
}
}
bool TRX_new_key_dash_hard = !HAL_GPIO_ReadPin(KEY_IN_DASH_GPIO_Port, KEY_IN_DASH_Pin);
if (TRX_key_dash_hard != TRX_new_key_dash_hard)
{
TRX_key_dash_hard = TRX_new_key_dash_hard;
if (TRX_key_dash_hard == true && (KEYER_symbol_status == 0 || !TRX.CW_KEYER))
{
TRX_Key_Timeout_est = TRX.CW_Key_timeout;
LCD_UpdateQuery.StatusInfoGUIRedraw = true;
FPGA_NeedSendParams = true;
TRX_Restart_Mode();
}
}
if (TRX_key_serial != TRX_old_key_serial)
{
TRX_old_key_serial = TRX_key_serial;
if (TRX_key_serial == true)
TRX_Key_Timeout_est = TRX.CW_Key_timeout;
LCD_UpdateQuery.StatusInfoGUIRedraw = true;
FPGA_NeedSendParams = true;
TRX_Restart_Mode();
}
}
void TRX_setFrequency(uint32_t _freq, VFO *vfo) void TRX_setFrequency(uint32_t _freq, VFO *vfo)
{ {
if (_freq < 1) if (_freq < 1)
@ -210,61 +169,8 @@ void TRX_setFrequency(uint32_t _freq, VFO *vfo)
int8_t band = getBandFromFreq(CurrentVFO()->Freq, true); int8_t band = getBandFromFreq(CurrentVFO()->Freq, true);
VFO *current_vfo = CurrentVFO(); VFO *current_vfo = CurrentVFO();
VFO *secondary_vfo = SecondaryVFO(); VFO *secondary_vfo = SecondaryVFO();
TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT); TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT);
TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq); TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq);
// switch (band)
// {
// case 1:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_160);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_160);
// break;
// case 2:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_80);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_80);
// break;
// case 4:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_40);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_40);
// break;
// case 5:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_30);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_30);
// break;
// case 6:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_20);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_20);
// break;
// case 7:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_17);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_17);
// break;
// case 8:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_15);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_15);
// break;
// case 9:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_12);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_12);
// break;
// case 10:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_sibi);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_sibi);
// break;
// case 11:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_10);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_10);
// break;
// case 12:
// TRX_freq_phrase = getRXPhraseFromFrequency((int32_t)current_vfo->Freq + TRX_SHIFT + CALIBRATE.freq_correctur_52);
// TRX_freq_phrase_tx = getTXPhraseFromFrequency((int32_t)current_vfo->Freq + CALIBRATE.freq_correctur_52);
// break;
// }
// sendToDebug_str("TRX_freq_phrase:");
// sendToDebug_uint8(TRX_freq_phrase, false);
// sendToDebug_str("TRX_freq_phrase_tx:");
// sendToDebug_uint8(TRX_freq_phrase_tx, false);
if (!TRX_on_TX()) if (!TRX_on_TX())
{ {
@ -395,85 +301,6 @@ void TRX_DBMCalculate(void)
Processor_RX_Power_value = 0; Processor_RX_Power_value = 0;
} }
float32_t current_cw_power = 0.0f;
static float32_t TRX_generateRiseSignal(float32_t power)
{
if(current_cw_power < power)
current_cw_power += power * 0.01f;
if(current_cw_power > power)
current_cw_power = power;
return current_cw_power;
}
static float32_t TRX_generateFallSignal(float32_t power)
{
if(current_cw_power > 0.0f)
current_cw_power -= power * 0.01f;
if(current_cw_power < 0.0f)
current_cw_power = 0.0f;
return current_cw_power;
}
float32_t TRX_GenerateCWSignal(float32_t power)
{
if (!TRX.CW_KEYER)
{
if (!TRX_key_serial && !TRX_ptt_hard && !TRX_key_dot_hard && !TRX_key_dash_hard)
return TRX_generateFallSignal(power);
return TRX_generateRiseSignal(power);
}
uint32_t dot_length_ms = 1200 / TRX.CW_KEYER_WPM;
uint32_t dash_length_ms = dot_length_ms * 3;
uint32_t sim_space_length_ms = dot_length_ms;
uint32_t curTime = HAL_GetTick();
//dot
if (KEYER_symbol_status == 0 && TRX_key_dot_hard)
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 1;
}
if (KEYER_symbol_status == 1 && (KEYER_symbol_start_time + dot_length_ms) > curTime)
{
TRX_Key_Timeout_est = TRX.CW_Key_timeout;
return TRX_generateRiseSignal(power);
}
if (KEYER_symbol_status == 1 && (KEYER_symbol_start_time + dot_length_ms) < curTime)
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 3;
}
//dash
if (KEYER_symbol_status == 0 && TRX_key_dash_hard)
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 2;
}
if (KEYER_symbol_status == 2 && (KEYER_symbol_start_time + dash_length_ms) > curTime)
{
TRX_Key_Timeout_est = TRX.CW_Key_timeout;
return TRX_generateRiseSignal(power);
}
if (KEYER_symbol_status == 2 && (KEYER_symbol_start_time + dash_length_ms) < curTime)
{
KEYER_symbol_start_time = curTime;
KEYER_symbol_status = 3;
}
//space
if (KEYER_symbol_status == 3 && (KEYER_symbol_start_time + sim_space_length_ms) > curTime)
{
TRX_Key_Timeout_est = TRX.CW_Key_timeout;
return TRX_generateFallSignal(power);
}
if (KEYER_symbol_status == 3 && (KEYER_symbol_start_time + sim_space_length_ms) < curTime)
{
KEYER_symbol_status = 0;
}
return TRX_generateFallSignal(power);
}
void TRX_TemporaryMute(void) void TRX_TemporaryMute(void)
{ {
WM8731_Mute(); WM8731_Mute();

8
STM32/Core/Src/trx_manager.h
Wyświetl plik

@ -20,11 +20,6 @@ extern void TRX_TemporaryMute(void);
volatile extern bool TRX_ptt_hard; volatile extern bool TRX_ptt_hard;
volatile extern bool TRX_ptt_soft; volatile extern bool TRX_ptt_soft;
volatile extern bool TRX_old_ptt_soft; volatile extern bool TRX_old_ptt_soft;
volatile extern bool TRX_key_serial;
volatile extern bool TRX_old_key_serial;
volatile extern bool TRX_key_dot_hard;
volatile extern bool TRX_key_dash_hard;
volatile extern uint_fast16_t TRX_Key_Timeout_est;
volatile extern bool TRX_RX_IQ_swap; volatile extern bool TRX_RX_IQ_swap;
volatile extern bool TRX_TX_IQ_swap; volatile extern bool TRX_TX_IQ_swap;
volatile extern bool TRX_Tune; volatile extern bool TRX_Tune;
@ -50,5 +45,8 @@ extern uint32_t TRX_freq_phrase;
extern uint32_t TRX_freq_phrase_tx; extern uint32_t TRX_freq_phrase_tx;
volatile extern uint32_t TRX_Temporary_Mute_StartTime; volatile extern uint32_t TRX_Temporary_Mute_StartTime;
extern float32_t TRX_InVoltage; extern float32_t TRX_InVoltage;
extern float32_t TRX_CPU_temperature;
extern float32_t TRX_CPU_VRef;
extern float32_t TRX_CPU_VBat;
#endif #endif

261
STM32/Core/Src/usbd_cat_if.c
Wyświetl plik

@ -5,6 +5,7 @@
#include <stdlib.h> #include <stdlib.h>
#include "lcd.h" #include "lcd.h"
#include "fpga.h" #include "fpga.h"
#include "cw.h"
#include "audio_filters.h" #include "audio_filters.h"
#define CAT_APP_RX_DATA_SIZE 32 #define CAT_APP_RX_DATA_SIZE 32
@ -13,14 +14,15 @@
#define CAT_BUFFER_SIZE 64 #define CAT_BUFFER_SIZE 64
static char cat_buffer[CAT_BUFFER_SIZE] = {0}; static char cat_buffer[CAT_BUFFER_SIZE] = {0};
static uint8_t cat_buffer_head = 0; static uint8_t cat_buffer_head = 0;
static char command_to_parse[CAT_BUFFER_SIZE] = {0}; static char command_to_parse1[CAT_BUFFER_SIZE] = {0};
static char command_to_parse2[CAT_BUFFER_SIZE] = {0};
static uint8_t CAT_UserRxBufferFS[CAT_APP_RX_DATA_SIZE]; static uint8_t CAT_UserRxBufferFS[CAT_APP_RX_DATA_SIZE];
static uint8_t CAT_UserTxBufferFS[CAT_APP_TX_DATA_SIZE]; static uint8_t CAT_UserTxBufferFS[CAT_APP_TX_DATA_SIZE];
static uint8_t lineCoding[7] = {0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x08}; // 115200bps, 1stop, no parity, 8bit static uint8_t lineCoding[7] = {0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x08}; // 115200bps, 1stop, no parity, 8bit
extern USBD_HandleTypeDef hUsbDeviceFS; extern USBD_HandleTypeDef hUsbDeviceFS;
static uint8_t getFT450Mode(uint8_t VFO_Mode); static void getFT450Mode(uint8_t VFO_Mode, char* out);
static uint8_t setFT450Mode(char *FT450_Mode); static uint8_t setFT450Mode(char *FT450_Mode);
static int8_t CAT_Init_FS(void); static int8_t CAT_Init_FS(void);
static int8_t CAT_DeInit_FS(void); static int8_t CAT_DeInit_FS(void);
@ -115,7 +117,22 @@ static int8_t CAT_Control_FS(uint8_t cmd, uint8_t *pbuf)
break; break;
case CDC_SET_CONTROL_LINE_STATE: case CDC_SET_CONTROL_LINE_STATE:
if ((pbuf[2] & 0x2) == 0x2) //RTS
{
TRX_ptt_soft = true;
}
else
{
TRX_ptt_soft = false;
}
if ((pbuf[2] & 0x1) == 0x1) //DTR
{
CW_key_serial = true;
}
else
{
CW_key_serial = false;
}
break; break;
case CDC_SEND_BREAK: case CDC_SEND_BREAK:
@ -148,6 +165,7 @@ static int8_t CAT_Receive_FS(uint8_t *Buf, uint32_t *Len)
{ {
char charBuff[CAT_BUFFER_SIZE] = {0}; char charBuff[CAT_BUFFER_SIZE] = {0};
strncpy(charBuff, (char *)Buf, Len[0]); strncpy(charBuff, (char *)Buf, Len[0]);
memset(&Buf, 0, Len[0]);
if (Len[0] <= CAT_BUFFER_SIZE) if (Len[0] <= CAT_BUFFER_SIZE)
{ {
for (uint16_t i = 0; i < Len[0]; i++) for (uint16_t i = 0; i < Len[0]; i++)
@ -157,10 +175,19 @@ static int8_t CAT_Receive_FS(uint8_t *Buf, uint32_t *Len)
cat_buffer[cat_buffer_head] = charBuff[i]; cat_buffer[cat_buffer_head] = charBuff[i];
if (cat_buffer[cat_buffer_head] == ';') if (cat_buffer[cat_buffer_head] == ';')
{ {
memset(&command_to_parse, 0, CAT_BUFFER_SIZE); if(strlen(command_to_parse1) == 0)
memcpy(command_to_parse, cat_buffer, cat_buffer_head); {
memset(command_to_parse1, 0, sizeof(command_to_parse1));
memcpy(command_to_parse1, cat_buffer, cat_buffer_head);
}
else if(strlen(command_to_parse2) == 0)
{
memset(command_to_parse2, 0, sizeof(command_to_parse2));
memcpy(command_to_parse2, cat_buffer, cat_buffer_head);
}
cat_buffer_head = 0; cat_buffer_head = 0;
memset(&cat_buffer, 0, CAT_BUFFER_SIZE); memset(cat_buffer, 0, CAT_BUFFER_SIZE);
continue; continue;
} }
cat_buffer_head++; cat_buffer_head++;
@ -208,13 +235,22 @@ static void CAT_Transmit(char *data)
void ua3reo_dev_cat_parseCommand(void) void ua3reo_dev_cat_parseCommand(void)
{ {
USBD_CAT_ReceivePacket(&hUsbDeviceFS); //prepare next command USBD_CAT_ReceivePacket(&hUsbDeviceFS); //prepare next command
if (command_to_parse[0] == 0) if (command_to_parse1[0] == 0 && command_to_parse2[0] == 0)
return; return;
char _command_buffer[CAT_BUFFER_SIZE] = {0}; char _command_buffer[CAT_BUFFER_SIZE] = {0};
char *_command = _command_buffer; char *_command = _command_buffer;
memcpy(_command, command_to_parse, CAT_BUFFER_SIZE); if(strlen(command_to_parse1) > 0)
memset(&command_to_parse, 0, CAT_BUFFER_SIZE); {
memcpy(_command, command_to_parse1, CAT_BUFFER_SIZE);
memset(command_to_parse1, 0, CAT_BUFFER_SIZE);
}
else if(strlen(command_to_parse2) > 0)
{
memcpy(_command, command_to_parse2, CAT_BUFFER_SIZE);
memset(command_to_parse2, 0, CAT_BUFFER_SIZE);
}
while (*_command == '\r' || *_command == '\n' || *_command == ' ') //trim while (*_command == '\r' || *_command == '\n' || *_command == ' ') //trim
_command++; _command++;
if (strlen(_command) < 2) if (strlen(_command) < 2)
@ -263,16 +299,21 @@ void ua3reo_dev_cat_parseCommand(void)
{ {
if (!has_args) if (!has_args)
{ {
CAT_Transmit("FT0;"); if(!TRX.CLAR)
CAT_Transmit("FT0;");
else
CAT_Transmit("FT1;");
} }
else else
{ {
if (strcmp(arguments, "0") == 0) if (strcmp(arguments, "0") == 0)
{ {
} //SPLIT DONT SUPPOTED TRX.CLAR = false;
}
else if (strcmp(arguments, "1") == 0) else if (strcmp(arguments, "1") == 0)
{ {
} //SPLIT DONT SUPPOTED TRX.CLAR = true;
}
else else
sendToDebug_str3("Unknown CAT arguments: ", _command, "\r\n"); sendToDebug_str3("Unknown CAT arguments: ", _command, "\r\n");
} }
@ -290,13 +331,33 @@ void ua3reo_dev_cat_parseCommand(void)
} }
else else
{ {
uint8_t new_vfo = 0;
if (strcmp(arguments, "0") == 0) if (strcmp(arguments, "0") == 0)
TRX.current_vfo = 0; new_vfo = 0;
else if (strcmp(arguments, "1") == 0) else if (strcmp(arguments, "1") == 0)
TRX.current_vfo = 1; new_vfo = 1;
NeedSaveSettings = true; if(TRX.current_vfo != new_vfo)
NeedReinitAudioFilters = true; {
LCD_redraw(false); TRX.current_vfo = new_vfo;
/*if(!TRX.current_vfo)
{
CurrentVFO = &TRX.VFO_A;
SecondaryVFO = &TRX.VFO_B;
}
else
{
CurrentVFO = &TRX.VFO_B;
SecondaryVFO = &TRX.VFO_A;
}*/
LCD_UpdateQuery.TopButtons = true;
LCD_UpdateQuery.BottomButtons = true;
LCD_UpdateQuery.FreqInfoRedraw = true;
LCD_UpdateQuery.StatusInfoGUI = true;
LCD_UpdateQuery.StatusInfoBarRedraw = true;
NeedSaveSettings = true;
NeedReinitAudioFilters = true;
FFT_Init();
}
sendToDebug_str3("CAT arguments: ", _command, "\r\n"); sendToDebug_str3("CAT arguments: ", _command, "\r\n");
} }
return; return;
@ -315,8 +376,9 @@ void ua3reo_dev_cat_parseCommand(void)
strcat(answer, "+0000"); //clirifier offset strcat(answer, "+0000"); //clirifier offset
strcat(answer, "0"); //RX clar off strcat(answer, "0"); //RX clar off
strcat(answer, "0"); //TX clar off strcat(answer, "0"); //TX clar off
sprintf(ctmp, "%d", getFT450Mode((uint8_t)CurrentVFO()->Mode)); char mode[3] = {0};
strcat(answer, ctmp); //mode getFT450Mode((uint8_t)CurrentVFO()->Mode, mode);
strcat(answer, mode); //mode
strcat(answer, "0"); //VFO Memory strcat(answer, "0"); //VFO Memory
strcat(answer, "0"); //CTCSS OFF strcat(answer, "0"); //CTCSS OFF
strcat(answer, "00"); //TONE NUMBER strcat(answer, "00"); //TONE NUMBER
@ -330,6 +392,35 @@ void ua3reo_dev_cat_parseCommand(void)
return; return;
} }
if (strcmp(command, "OI") == 0) // OPPOSITE BAND INFORMATION
{
if (!has_args)
{
char answer[30] = {0};
strcat(answer, "OI001"); //memory channel
if (SecondaryVFO()->Freq < 10000000)
strcat(answer, "0");
sprintf(ctmp, "%u", SecondaryVFO()->Freq);
strcat(answer, ctmp); //freq
strcat(answer, "+0000"); //clirifier offset
strcat(answer, "0"); //RX clar off
strcat(answer, "0"); //TX clar off
char mode[3] = {0};
getFT450Mode((uint8_t)SecondaryVFO()->Mode, mode);
strcat(answer, mode); //mode
strcat(answer, "0"); //VFO Memory
strcat(answer, "0"); //CTCSS OFF
strcat(answer, "00"); //TONE NUMBER
strcat(answer, "0;"); //Simplex
CAT_Transmit(answer);
}
else
{
sendToDebug_str3("Unknown CAT arguments: ", _command, "\r\n");
}
return;
}
if (strcmp(command, "FA") == 0) // FREQUENCY VFO-A if (strcmp(command, "FA") == 0) // FREQUENCY VFO-A
{ {
if (!has_args) if (!has_args)
@ -345,9 +436,7 @@ void ua3reo_dev_cat_parseCommand(void)
} }
else else
{ {
if (TRX.current_vfo == 0) TRX_setFrequency((uint32_t)atoi(arguments), CurrentVFO());
TRX_setFrequency((uint32_t)atoi(arguments), CurrentVFO());
TRX.VFO_A.Freq = (uint32_t)atoi(arguments);
LCD_UpdateQuery.FreqInfo = true; LCD_UpdateQuery.FreqInfo = true;
LCD_UpdateQuery.TopButtons = true; LCD_UpdateQuery.TopButtons = true;
} }
@ -359,7 +448,7 @@ void ua3reo_dev_cat_parseCommand(void)
if (!has_args) if (!has_args)
{ {
char answer[30] = {0}; char answer[30] = {0};
strcat(answer, "FA"); strcat(answer, "FB");
if (TRX.VFO_B.Freq < 10000000) if (TRX.VFO_B.Freq < 10000000)
strcat(answer, "0"); strcat(answer, "0");
sprintf(ctmp, "%u", TRX.VFO_B.Freq); sprintf(ctmp, "%u", TRX.VFO_B.Freq);
@ -369,9 +458,7 @@ void ua3reo_dev_cat_parseCommand(void)
} }
else else
{ {
if (TRX.current_vfo == 1) TRX_setFrequency((uint32_t)atoi(arguments), SecondaryVFO());
TRX_setFrequency((uint32_t)atoi(arguments), CurrentVFO());
TRX.VFO_B.Freq = (uint32_t)atoi(arguments);
LCD_UpdateQuery.FreqInfo = true; LCD_UpdateQuery.FreqInfo = true;
LCD_UpdateQuery.TopButtons = true; LCD_UpdateQuery.TopButtons = true;
} }
@ -476,8 +563,9 @@ void ua3reo_dev_cat_parseCommand(void)
{ {
char answer[30] = {0}; char answer[30] = {0};
strcat(answer, "MD0"); strcat(answer, "MD0");
sprintf(ctmp, "%d", getFT450Mode((uint8_t)CurrentVFO()->Mode)); char mode[3] = {0};
strcat(answer, ctmp); //mode getFT450Mode((uint8_t)CurrentVFO()->Mode, mode);
strcat(answer, mode); //mode
strcat(answer, ";"); strcat(answer, ";");
CAT_Transmit(answer); CAT_Transmit(answer);
} }
@ -521,7 +609,7 @@ void ua3reo_dev_cat_parseCommand(void)
{ {
if (strcmp(arguments, "0") == 0) if (strcmp(arguments, "0") == 0)
{ {
CAT_Transmit("SH016;"); CAT_Transmit("SH031;");
} }
} }
return; return;
@ -660,6 +748,57 @@ void ua3reo_dev_cat_parseCommand(void)
} }
return; return;
} }
if (strcmp(command, "BS") == 0) // BAND SELECT
{
if (!has_args)
{
}
else
{
int8_t band = -1;
if (strcmp(arguments, "00") == 0)
band = 1;
else if (strcmp(arguments, "01") == 0)
band = 2;
else if (strcmp(arguments, "03") == 0)
band = 4;
else if (strcmp(arguments, "04") == 0)
band = 5;
else if (strcmp(arguments, "05") == 0)
band = 6;
else if (strcmp(arguments, "06") == 0)
band = 7;
else if (strcmp(arguments, "07") == 0)
band = 8;
else if (strcmp(arguments, "08") == 0)
band = 9;
else if (strcmp(arguments, "09") == 0)
band = 10;
else if (strcmp(arguments, "10") == 0)
band = 11;
else
sendToDebug_str3("Unknown CAT arguments: ", _command, "\r\n");
if(band > -1)
{
TRX_setFrequency(TRX.BANDS_SAVED_SETTINGS[band].Freq, CurrentVFO());
TRX_setMode(TRX.BANDS_SAVED_SETTINGS[band].Mode, CurrentVFO());
TRX.ATT = TRX.BANDS_SAVED_SETTINGS[band].ATT;
TRX.ATT_DB = TRX.BANDS_SAVED_SETTINGS[band].ATT_DB;
TRX.ADC_Driver = TRX.BANDS_SAVED_SETTINGS[band].ADC_Driver;
CurrentVFO()->AGC = TRX.BANDS_SAVED_SETTINGS[band].AGC;
TRX_Temporary_Stop_BandMap = false;
LCD_UpdateQuery.TopButtons = true;
LCD_UpdateQuery.FreqInfoRedraw = true;
LCD_UpdateQuery.StatusInfoBarRedraw = true;
LCD_UpdateQuery.StatusInfoGUI = true;
}
}
return;
}
if (strcmp(command, "NA") == 0) // NARROW if (strcmp(command, "NA") == 0) // NARROW
{ {
@ -688,6 +827,19 @@ void ua3reo_dev_cat_parseCommand(void)
} }
return; return;
} }
if (strcmp(command, "KP") == 0) // READ KEY PITCH
{
if (!has_args)
{
CAT_Transmit("KP04;");
}
else
{
sendToDebug_str3("Unknown CAT arguments: ", _command, "\r\n");
}
return;
}
if (strcmp(command, "TX") == 0) // TX SET if (strcmp(command, "TX") == 0) // TX SET
{ {
@ -719,55 +871,50 @@ void ua3reo_dev_cat_parseCommand(void)
//sendToDebug_str2(arguments,"|\r\n"); //sendToDebug_str2(arguments,"|\r\n");
} }
static uint8_t getFT450Mode(uint8_t VFO_Mode) static void getFT450Mode(uint8_t VFO_Mode, char* out)
{ {
if (VFO_Mode == TRX_MODE_LSB) if (VFO_Mode == TRX_MODE_LSB)
return 1; strcpy(out, "1");
if (VFO_Mode == TRX_MODE_USB) if (VFO_Mode == TRX_MODE_USB)
return 2; strcpy(out, "2");
if (VFO_Mode == TRX_MODE_IQ) if (VFO_Mode == TRX_MODE_IQ)
return 8; strcpy(out, "8");
if (VFO_Mode == TRX_MODE_CW_L) if (VFO_Mode == TRX_MODE_CW_L || VFO_Mode == TRX_MODE_CW_U)
return 3; strcpy(out, "3");
if (VFO_Mode == TRX_MODE_CW_U)
return 3;
if (VFO_Mode == TRX_MODE_DIGI_L) if (VFO_Mode == TRX_MODE_DIGI_L)
return 6; strcpy(out, "8");
if (VFO_Mode == TRX_MODE_DIGI_U) if (VFO_Mode == TRX_MODE_DIGI_U)
return 9; strcpy(out, "C");
if (VFO_Mode == TRX_MODE_NO_TX)
return 8;
if (VFO_Mode == TRX_MODE_NFM) if (VFO_Mode == TRX_MODE_NFM)
return 4; strcpy(out, "4");
if (VFO_Mode == TRX_MODE_WFM) if (VFO_Mode == TRX_MODE_WFM)
return 4; strcpy(out, "4");
if (VFO_Mode == TRX_MODE_AM) if (VFO_Mode == TRX_MODE_AM)
return 5; strcpy(out, "5");
if (VFO_Mode == TRX_MODE_LOOPBACK) if (VFO_Mode == TRX_MODE_LOOPBACK)
return 8; strcpy(out, "8");
return 1;
} }
static uint8_t setFT450Mode(char *FT450_Mode) static uint8_t setFT450Mode(char *FT450_Mode)
{ {
if (strcmp(FT450_Mode, "01") == 0) if (strcmp(FT450_Mode, "01") == 0 || strcmp(FT450_Mode, "1") == 0)
return TRX_MODE_LSB; return TRX_MODE_LSB;
if (strcmp(FT450_Mode, "02") == 0) if (strcmp(FT450_Mode, "02") == 0 || strcmp(FT450_Mode, "2") == 0)
return TRX_MODE_USB; return TRX_MODE_USB;
if (strcmp(FT450_Mode, "08") == 0) if (strcmp(FT450_Mode, "08") == 0 || strcmp(FT450_Mode, "8") == 0)
return TRX_MODE_IQ; return TRX_MODE_IQ;
if (strcmp(FT450_Mode, "03") == 0) if (strcmp(FT450_Mode, "03") == 0 || strcmp(FT450_Mode, "3") == 0)
return TRX_MODE_CW_L; return TRX_MODE_CW_L;
if (strcmp(FT450_Mode, "06") == 0) if (strcmp(FT450_Mode, "06") == 0 || strcmp(FT450_Mode, "6") == 0)
return TRX_MODE_DIGI_L; return TRX_MODE_DIGI_L;
if (strcmp(FT450_Mode, "09") == 0) if (strcmp(FT450_Mode, "09") == 0 || strcmp(FT450_Mode, "9") == 0)
return TRX_MODE_DIGI_U; return TRX_MODE_DIGI_U;
if (strcmp(FT450_Mode, "0C") == 0) if (strcmp(FT450_Mode, "0C") == 0 || strcmp(FT450_Mode, "C") == 0)
return TRX_MODE_DIGI_U; return TRX_MODE_DIGI_U;
if (strcmp(FT450_Mode, "04") == 0) if (strcmp(FT450_Mode, "04") == 0 || strcmp(FT450_Mode, "4") == 0)
return TRX_MODE_NFM; return TRX_MODE_NFM;
if (strcmp(FT450_Mode, "05") == 0) if (strcmp(FT450_Mode, "05") == 0 || strcmp(FT450_Mode, "5") == 0)
return TRX_MODE_AM; return TRX_MODE_AM;
sendToDebug_str3("Unknown mode ", FT450_Mode, "\r\n"); sendToDebug_str3("Unknown mode ", FT450_Mode, "\r\n");
return TRX_MODE_USB; return TRX_MODE_USB;
} }

4
STM32/Core/Src/usbd_debug_if.c
Wyświetl plik

@ -109,10 +109,6 @@ static int8_t DEBUG_Control_FS(uint8_t cmd, uint8_t *pbuf, uint32_t len)
break; break;
case CDC_SET_CONTROL_LINE_STATE: case CDC_SET_CONTROL_LINE_STATE:
if (pbuf[2] == 1)
TRX_key_serial = true;
else
TRX_key_serial = false;
break; break;
case CDC_SEND_BREAK: case CDC_SEND_BREAK:

40
STM32/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h
Wyświetl plik

@ -1148,7 +1148,15 @@ typedef struct
/** @addtogroup Exported_constants /** @addtogroup Exported_constants
* @{ * @{
*/ */
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition /** @addtogroup Peripheral_Registers_Bits_Definition
* @{ * @{
*/ */
@ -6673,17 +6681,18 @@ typedef struct
/* */ /* */
/******************************************************************************/ /******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/ /******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS 0x00000000U #define FLASH_ACR_LATENCY_0WS 0x00000000U
#define FLASH_ACR_LATENCY_1WS 0x00000001U #define FLASH_ACR_LATENCY_1WS 0x00000001U
#define FLASH_ACR_LATENCY_2WS 0x00000002U #define FLASH_ACR_LATENCY_2WS 0x00000002U
#define FLASH_ACR_LATENCY_3WS 0x00000003U #define FLASH_ACR_LATENCY_3WS 0x00000003U
#define FLASH_ACR_LATENCY_4WS 0x00000004U #define FLASH_ACR_LATENCY_4WS 0x00000004U
#define FLASH_ACR_LATENCY_5WS 0x00000005U #define FLASH_ACR_LATENCY_5WS 0x00000005U
#define FLASH_ACR_LATENCY_6WS 0x00000006U #define FLASH_ACR_LATENCY_6WS 0x00000006U
#define FLASH_ACR_LATENCY_7WS 0x00000007U #define FLASH_ACR_LATENCY_7WS 0x00000007U
#define FLASH_ACR_PRFTEN_Pos (8U) #define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
@ -6759,6 +6768,9 @@ typedef struct
#define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
@ -8122,7 +8134,7 @@ typedef struct
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
@ -8153,7 +8165,7 @@ typedef struct
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1

60
STM32/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
Wyświetl plik

@ -106,16 +106,16 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS version number V2.6.5 * @brief CMSIS version number V2.6.7
*/ */
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ #define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ #define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F4xx_CMSIS_VERSION)) |(__STM32F4xx_CMSIS_VERSION_RC))
/** /**
* @} * @}
@ -225,6 +225,60 @@ typedef enum
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/** /**
* @} * @}

324
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
Wyświetl plik

@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY #define STM32_HAL_LEGACY
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -38,7 +38,14 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
/** /**
* @} * @}
*/ */
@ -211,6 +218,10 @@
* @} * @}
*/ */
/**
* @}
*/
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@ -236,12 +247,12 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32H7) #if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif #endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif #endif
@ -313,8 +324,13 @@
#endif /* STM32L4 */ #endif /* STM32L4 */
#if defined(STM32G0) #if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif #endif
#if defined(STM32H7) #if defined(STM32H7)
@ -378,7 +394,6 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */ #endif /* STM32H7 */
/** /**
* @} * @}
*/ */
@ -466,15 +481,24 @@
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
#endif #endif
#if defined(STM32H7) #if defined(STM32H7)
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */ #endif /* STM32H7 */
#if defined(STM32U5)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U5 */
/** /**
* @} * @}
@ -517,6 +541,7 @@
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */ #endif /* STM32G4 */
/** /**
* @} * @}
*/ */
@ -591,24 +616,24 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
#if defined(STM32L1) #if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */ #endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */ #endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@ -643,6 +668,10 @@
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */ #endif /* STM32G4 */
#if defined(STM32H7) #if defined(STM32H7)
@ -765,49 +794,6 @@
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds) /** @brief Constants defining the DLL calibration periods (in micro seconds)
*/ */
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U #define HRTIM_CALIBRATIONRATE_7300 0x00000000U
@ -888,6 +874,10 @@
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
#endif /* STM32U5 */
/** /**
* @} * @}
*/ */
@ -955,11 +945,16 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif #endif
#if defined(STM32L4) || defined(STM32L5)
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
#elif defined(STM32G4)
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
#endif
/** /**
* @} * @}
@ -971,15 +966,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7) #if defined(STM32H7)
#define I2S_IT_TXE I2S_IT_TXP #define I2S_IT_TXE I2S_IT_TXP
#define I2S_IT_RXNE I2S_IT_RXP #define I2S_IT_RXNE I2S_IT_RXP
#define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP #define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif #endif
#if defined(STM32F7) #if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif #endif
/** /**
* @} * @}
@ -1114,16 +1109,16 @@
#if defined(STM32H7) #if defined(STM32H7)
#define SPI_FLAG_TXE SPI_FLAG_TXP #define SPI_FLAG_TXE SPI_FLAG_TXP
#define SPI_FLAG_RXNE SPI_FLAG_RXP #define SPI_FLAG_RXNE SPI_FLAG_RXP
#define SPI_IT_TXE SPI_IT_TXP #define SPI_IT_TXE SPI_IT_TXP
#define SPI_IT_RXNE SPI_IT_RXP #define SPI_IT_RXNE SPI_IT_RXP
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */ #endif /* STM32H7 */
@ -1409,6 +1404,20 @@
*/ */
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|| defined(STM32H7) || defined(STM32U5)
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
for compatibility with legacy code */
/**
* @}
*/
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{ * @{
*/ */
@ -1427,6 +1436,29 @@
* @} * @}
*/ */
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32U5)
#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
#endif /* STM32U5 */
/**
* @}
*/
#if !defined(STM32F2)
/** @defgroup HASH_alias HASH API alias
* @{
*/
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
/**
*
* @}
*/
#endif /* STM32F2 */
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
@ -1450,7 +1482,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@ -1472,7 +1504,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */ #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/** /**
* @} * @}
*/ */
@ -1486,7 +1518,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0) #if defined(STM32L0)
@ -1494,7 +1527,8 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif #endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
@ -1517,9 +1551,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
/** /**
* @} * @}
*/ */
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{ * @{
@ -1529,20 +1563,21 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4) #if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1554,19 +1589,19 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */ #endif /* STM32F4 */
/** /**
* @} * @}
*/ */
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{ * @{
*/ */
#if defined(STM32G0) #if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif #endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
@ -1611,9 +1646,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
/** /**
* @} * @}
*/ */
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{ * @{
@ -1862,15 +1897,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7) #if defined(STM32H7)
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else #else
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */ #endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@ -2081,8 +2116,8 @@
*/ */
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
((WAVE) == DAC_WAVE_NOISE)|| \ ((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE)) ((WAVE) == DAC_WAVE_TRIANGLE))
/** /**
* @} * @}
@ -2138,7 +2173,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7) #if defined(STM32H7)
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif #endif
/** /**
@ -2275,7 +2310,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@ -3243,9 +3279,8 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#else #else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif #endif
@ -3356,7 +3391,20 @@
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
#endif
/** /**
* @} * @}
*/ */
@ -3373,7 +3421,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#else #else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif #endif
@ -3393,19 +3441,19 @@
#else #else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */ #endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM #define IS_ALARM IS_RTC_ALARM
@ -3430,13 +3478,22 @@
* @} * @}
*/ */
/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
#endif
#if defined(STM32F4) || defined(STM32F2) #if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
@ -3481,9 +3538,9 @@
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */ /* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler #define SDIO_IRQHandler SDMMC1_IRQHandler
@ -3589,6 +3646,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
#define USART_OVERSAMPLING_16 0x00000000U
#define USART_OVERSAMPLING_8 USART_CR1_OVER8
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
((__SAMPLING__) == USART_OVERSAMPLING_8))
#endif /* STM32F0 || STM32F3 || STM32F7 */
/** /**
* @} * @}
*/ */
@ -3751,7 +3815,7 @@
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif /* STM32L4 || STM32F4 || STM32F7 */ #endif /* STM32L4 || STM32F4 || STM32F7 */
/** /**

3
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h
Wyświetl plik

@ -28,6 +28,9 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h" #include "stm32f4xx_hal_def.h"
/* Include low level driver */
#include "stm32f4xx_ll_adc.h"
/** @addtogroup STM32F4xx_HAL_Driver /** @addtogroup STM32F4xx_HAL_Driver
* @{ * @{
*/ */

17
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h
Wyświetl plik

@ -304,17 +304,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
*/ */
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) defined(STM32F412Cx)
#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18) #define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE ||
STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ #if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \
defined(STM32F469xx) || defined(STM32F479xx)
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \

32
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
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@ -107,7 +107,14 @@ typedef enum
}while (0U) }while (0U)
#endif /* USE_RTOS */ #endif /* USE_RTOS */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak #ifndef __weak
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#endif /* __weak */ #endif /* __weak */
@ -118,7 +125,14 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END #ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4))) #define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
@ -130,7 +144,7 @@ typedef enum
#define __ALIGN_END #define __ALIGN_END
#endif /* __ALIGN_END */ #endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN #ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */ #if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4) #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */ #elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN #define __ALIGN_BEGIN
@ -142,9 +156,9 @@ typedef enum
/** /**
* @brief __RAM_FUNC definition * @brief __RAM_FUNC definition
*/ */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler /* ARM Compiler V4/V5 and V6
------------ --------------------------
RAM functions are defined using the toolchain options. RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module. Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const' Using the 'Options for File' dialog you can simply change the 'Code / Const'
@ -174,9 +188,9 @@ typedef enum
/** /**
* @brief __NOINLINE definition * @brief __NOINLINE definition
*/ */
#if defined ( __CC_ARM ) || defined ( __GNUC__ ) #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM & GNUCompiler /* ARM V4/V5 and V6 & GNU Compiler
---------------- -------------------------------
*/ */
#define __NOINLINE __attribute__ ( (noinline) ) #define __NOINLINE __attribute__ ( (noinline) )

18
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
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@ -243,19 +243,19 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros /** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{ * @{
*/ */
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ #define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ #define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) #define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) #define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) #define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if !defined (GPIOD) #if !defined (GPIOD)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \

56
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
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@ -107,30 +107,30 @@ typedef enum
*/ */
/** @defgroup GPIO_mode_define GPIO mode define /** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode * @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ * Elements values convention: 0x00WX00YZ
* - X : GPIO mode or EXTI Mode * - W : EXTI trigger detection on 3 bits
* - y : External IT or Event trigger detection * - X : EXTI mode (IT or Event) on 2 bits
* - z : IO configuration on External IT or Event * - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Y : Output type (Push Pull or Open Drain) * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{ * @{
*/ */
#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */ #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */ #define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */ #define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */ #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/** /**
* @} * @}
*/ */
@ -252,6 +252,24 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/** @defgroup GPIO_Private_Constants GPIO Private Constants /** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{ * @{
*/ */
#define GPIO_MODE_Pos 0U
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4U
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16U
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20U
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
/** /**
* @} * @}

18
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
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@ -1442,21 +1442,21 @@
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/*---------------------------------------- STM32F401xx------------------------*/ /*---------------------------------------- STM32F401xx------------------------*/
#if defined(STM32F401xC) || defined(STM32F401xE) #if defined(STM32F401xC) || defined(STM32F401xE)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \ #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF12_SDIO) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \ ((AF) == GPIO_AF1_TIM1) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF4_I2C1) || \ ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM9) || \
((AF) == GPIO_AF4_I2C2) || ((AF) == GPIO_AF4_I2C3) || \ ((AF) == GPIO_AF3_TIM10) || ((AF) == GPIO_AF3_TIM11) || \
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI4) || \
((AF) == GPIO_AF8_USART6) || ((AF) == GPIO_AF10_OTG_FS) || \ ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF7_USART1) || \
((AF) == GPIO_AF7_USART2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \ ((AF) == GPIO_AF9_I2C2) || ((AF) == GPIO_AF9_I2C3) || \
((AF) == GPIO_AF15_EVENTOUT)) ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF15_EVENTOUT))
#endif /* STM32F401xC || STM32F401xE */ #endif /* STM32F401xC || STM32F401xE */
/*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/
/*---------------------------------------- STM32F410xx------------------------*/ /*---------------------------------------- STM32F410xx------------------------*/

4
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h
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@ -516,7 +516,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
*/ */
/** @brief Check whether the specified SPI flag is set or not. /** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR regsiter. * @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
@ -531,7 +531,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not. /** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 regsiter. * @param __CR2__ copy of I2S CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check. * @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_TXE: Tx buffer empty interrupt enable

26
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h
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@ -194,16 +194,20 @@ typedef struct
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK #define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@ -418,27 +422,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#ifndef USB_OTG_DOEPINT_OTEPSPR #ifndef USB_OTG_DOEPINT_OTEPSPR
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ #define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
#endif #endif /* defined USB_OTG_DOEPINT_OTEPSPR */
#ifndef USB_OTG_DOEPMSK_OTEPSPRM #ifndef USB_OTG_DOEPMSK_OTEPSPRM
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ #define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
#endif #endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
#ifndef USB_OTG_DOEPINT_NAK #ifndef USB_OTG_DOEPINT_NAK
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ #define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
#endif #endif /* defined USB_OTG_DOEPINT_NAK */
#ifndef USB_OTG_DOEPMSK_NAKM #ifndef USB_OTG_DOEPMSK_NAKM
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ #define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
#endif #endif /* defined USB_OTG_DOEPMSK_NAKM */
#ifndef USB_OTG_DOEPINT_STPKTRX #ifndef USB_OTG_DOEPINT_STPKTRX
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ #define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
#endif #endif /* defined USB_OTG_DOEPINT_STPKTRX */
#ifndef USB_OTG_DOEPMSK_NYETM #ifndef USB_OTG_DOEPMSK_NYETM
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ #define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
#endif #endif /* defined USB_OTG_DOEPMSK_NYETM */
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* Private macros ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/

12
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
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@ -976,11 +976,10 @@ typedef struct
* a Power On Reset (POR). * a Power On Reset (POR).
* @param __RTCCLKSource__ specifies the RTC clock source. * @param __RTCCLKSource__ specifies the RTC clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. * @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
* as RTC clock, where x:[2,31]
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wake-up source. * work in STOP and STANDBY modes, and can be used as wake-up source.
* However, when the HSE clock is used as RTC clock source, the RTC * However, when the HSE clock is used as RTC clock source, the RTC
@ -1007,8 +1006,7 @@ typedef struct
/** /**
* @brief Get the RTC and HSE clock divider (RTCPRE). * @brief Get the RTC and HSE clock divider (RTCPRE).
* @retval Returned value can be one of the following values: * @retval Returned value can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
* as RTC clock, where x:[2,31]
*/ */
#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)

34
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
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@ -103,7 +103,7 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock. uint32_t PLLSAIM; /*!< Specifies division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
@ -4969,7 +4969,6 @@ typedef struct
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while(0U)
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_ENABLE() do { \ #define __HAL_RCC_USART3_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \ __IO uint32_t tmpreg = 0x00U; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
@ -4977,7 +4976,6 @@ typedef struct
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0U) } while(0U)
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_ENABLE() do { \ #define __HAL_RCC_UART4_CLK_ENABLE() do { \
@ -5098,9 +5096,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */ #endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN)) #define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
@ -5140,9 +5136,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */ #endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET) #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
@ -5171,9 +5165,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */ #endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET) #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx | STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
@ -5445,9 +5437,7 @@ typedef struct
#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
#endif /* STM32F413xx || STM32F423xx */ #endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
@ -5475,9 +5465,7 @@ typedef struct
#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
#endif /* STM32F413xx || STM32F423xx */ #endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
@ -5633,9 +5621,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */ #endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN)) #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
@ -5664,9 +5650,7 @@ typedef struct
#endif /* STM32F413xx || STM32F423xx */ #endif /* STM32F413xx || STM32F423xx */
#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN)) #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F413xx) || defined(STM32F423xx)
#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
@ -6385,7 +6369,7 @@ typedef struct
* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
* @retval None * @retval None
*/ */
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__)) #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
@ -6393,7 +6377,7 @@ typedef struct
/** @brief Macro to get the DFSDM1 clock source. /** @brief Macro to get the DFSDM1 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
*/ */
#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
@ -6421,7 +6405,7 @@ typedef struct
* @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
* @retval None * @retval None
*/ */
#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__)) #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__) MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
@ -6429,7 +6413,7 @@ typedef struct
/** @brief Macro to get the DFSDM2 clock source. /** @brief Macro to get the DFSDM2 clock source.
* @retval The clock source can be one of the following values: * @retval The clock source can be one of the following values:
* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
*/ */
#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL))) #define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
@ -6868,16 +6852,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
* @{ * @{
*/ */
#if defined(STM32F411xE)
#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
#else /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||
STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410Tx || STM32F410Cx ||
STM32F410Rx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Cx || STM32F412Rx ||
STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx */
#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) #define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U)) #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
#endif /* STM32F411xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU)) #define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))

14
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h
Wyświetl plik

@ -105,12 +105,11 @@ typedef struct
with [1 Sec / SecondFraction +1] granularity. with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */ This field will be used only by HAL_RTC_GetTime function */
uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation. uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ please use HAL_RTC_DST_xxx functions */
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
in CR register to store the operation. please use HAL_RTC_DST_xxx functions */
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
}RTC_TimeTypeDef; }RTC_TimeTypeDef;
/** /**
@ -701,6 +700,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/** /**
* @} * @}
*/ */

40
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h
Wyświetl plik

@ -493,7 +493,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
/** @brief Check whether the specified SPI flag is set or not. /** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR regsiter. * @param __SR__ copy of SPI SR register.
* @param __FLAG__ specifies the flag to check. * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
@ -505,10 +505,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_FLAG_FRE: Frame format error flag * @arg SPI_FLAG_FRE: Frame format error flag
* @retval SET or RESET. * @retval SET or RESET.
*/ */
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not. /** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 regsiter. * @param __CR2__ copy of SPI CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check. * @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
@ -516,15 +517,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_IT_ERR: Error interrupt enable * @arg SPI_IT_ERR: Error interrupt enable
* @retval SET or RESET. * @retval SET or RESET.
*/ */
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
(__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range. /** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode. * @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode * This parameter can be a value of @ref SPI_Mode
* @retval None * @retval None
*/ */
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
((__MODE__) == SPI_MODE_MASTER)) ((__MODE__) == SPI_MODE_MASTER))
/** @brief Checks if SPI Direction Mode parameter is in allowed range. /** @brief Checks if SPI Direction Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Direction Mode. * @param __MODE__ specifies the SPI Direction Mode.
@ -561,25 +563,25 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be a value of @ref SPI_Clock_Polarity * This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None * @retval None
*/ */
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
((__CPOL__) == SPI_POLARITY_HIGH)) ((__CPOL__) == SPI_POLARITY_HIGH))
/** @brief Checks if SPI Clock Phase parameter is in allowed range. /** @brief Checks if SPI Clock Phase parameter is in allowed range.
* @param __CPHA__ specifies the SPI Clock Phase. * @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase * This parameter can be a value of @ref SPI_Clock_Phase
* @retval None * @retval None
*/ */
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
((__CPHA__) == SPI_PHASE_2EDGE)) ((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range. /** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Select management parameter. * @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management * This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None * @retval None
*/ */
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
((__NSS__) == SPI_NSS_HARD_INPUT) || \ ((__NSS__) == SPI_NSS_HARD_INPUT) || \
((__NSS__) == SPI_NSS_HARD_OUTPUT)) ((__NSS__) == SPI_NSS_HARD_OUTPUT))
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
* @param __PRESCALER__ specifies the SPI Baudrate prescaler. * @param __PRESCALER__ specifies the SPI Baudrate prescaler.
@ -600,16 +602,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter can be a value of @ref SPI_MSB_LSB_transmission * This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None * @retval None
*/ */
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
((__BIT__) == SPI_FIRSTBIT_LSB)) ((__BIT__) == SPI_FIRSTBIT_LSB))
/** @brief Checks if SPI TI mode parameter is in allowed range. /** @brief Checks if SPI TI mode parameter is in allowed range.
* @param __MODE__ specifies the SPI TI mode. * @param __MODE__ specifies the SPI TI mode.
* This parameter can be a value of @ref SPI_TI_mode * This parameter can be a value of @ref SPI_TI_mode
* @retval None * @retval None
*/ */
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
((__MODE__) == SPI_TIMODE_ENABLE)) ((__MODE__) == SPI_TIMODE_ENABLE))
/** @brief Checks if SPI CRC calculation enabled state is in allowed range. /** @brief Checks if SPI CRC calculation enabled state is in allowed range.
* @param __CALCULATION__ specifies the SPI CRC calculation enable state. * @param __CALCULATION__ specifies the SPI CRC calculation enable state.
@ -624,7 +626,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None * @retval None
*/ */
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
(((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid. /** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle. * @param __HANDLE__ specifies a DMA Handle.

315
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h
Wyświetl plik

@ -65,8 +65,10 @@ typedef struct
This means in PWM mode that (N+1) corresponds to: This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode - the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode - the number of half PWM period in center-aligned mode
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. GP timers: this parameter must be a number between Min_Data = 0x00 and
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */ This parameter can be a value of @ref TIM_AutoReloadPreload */
@ -218,7 +220,8 @@ typedef struct
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */ This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ This parameter must be 0: When OCRef clear feature is used with ETR source,
ETR prescaler must be off */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter uint32_t ClearInputFilter; /*!< TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef; } TIM_ClearInputConfigTypeDef;
@ -264,22 +267,22 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
uint32_t OffStateRunMode; /*!< TIM off state in run mode uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
uint32_t LockLevel; /*!< TIM Lock level uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t BreakState; /*!< TIM Break State uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t BreakFilter; /*!< Specifies the break input filter. uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef; } TIM_BreakDeadTimeConfigTypeDef;
/** /**
@ -294,6 +297,26 @@ typedef enum
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_TIM_StateTypeDef; } HAL_TIM_StateTypeDef;
/**
* @brief TIM Channel States definition
*/
typedef enum
{
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;
/**
* @brief DMA Burst States definition
*/
typedef enum
{
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
} HAL_TIM_DMABurstStateTypeDef;
/** /**
* @brief HAL Active channel structures definition * @brief HAL Active channel structures definition
*/ */
@ -315,13 +338,16 @@ typedef struct __TIM_HandleTypeDef
typedef struct typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{ {
TIM_TypeDef *Instance; /*!< Register base address */ TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */ HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */ This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */ HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@ -360,34 +386,34 @@ typedef struct
*/ */
typedef enum typedef enum
{ {
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
} HAL_TIM_CallbackIDTypeDef; } HAL_TIM_CallbackIDTypeDef;
/** /**
@ -605,10 +631,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{ * @{
*/ */
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/** /**
* @} * @}
@ -823,8 +847,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @{ * @{
*/ */
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
(if none of the break inputs BRK and BRK2 is active) */
/** /**
* @} * @}
*/ */
@ -931,24 +954,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{ * @{
*/ */
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/** /**
* @} * @}
*/ */
@ -993,25 +1016,45 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None * @retval None
*/ */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \ (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \ (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \ (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->IC_MspInitCallback = NULL; \ (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \ (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->OC_MspInitCallback = NULL; \ (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \ (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \ (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \ (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ (__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \ (__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ (__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \ (__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ (__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0) } while(0)
#else #else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/** /**
@ -1048,7 +1091,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @brief Disable the TIM main Output. * @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle * @param __HANDLE__ TIM handle
* @retval None * @retval None
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
* disabled
*/ */
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \ do { \
@ -1209,8 +1253,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @brief Indicates whether or not the TIM Counter is used as downcounter. * @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle. * @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
mode. * or Encoder mode.
*/ */
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
@ -1284,7 +1328,8 @@ mode.
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/** /**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
* function.
* @param __HANDLE__ TIM handle. * @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured. * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values: * This parameter can be one of the following values:
@ -1710,15 +1755,15 @@ mode.
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
@ -1729,6 +1774,8 @@ mode.
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@ -1759,6 +1806,48 @@ mode.
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
(__HANDLE__)->ChannelState[3])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
} while(0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelNState[0] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[1] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[2] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[3] = \
(__CHANNEL_STATE__); \
} while(0)
/** /**
* @} * @}
*/ */
@ -1930,9 +2019,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -1978,6 +2073,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/** /**
* @} * @}
*/ */
@ -1997,7 +2097,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);

109
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h
Wyświetl plik

@ -129,66 +129,66 @@ typedef struct
* @{ * @{
*/ */
#if defined(SPDIFRX) #if defined(SPDIFRX)
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
((TIM_REMAP) == TIM_TIM5_LSI) || \ ((TIM_REMAP) == TIM_TIM5_LSI) || \
((TIM_REMAP) == TIM_TIM5_LSE) || \ ((TIM_REMAP) == TIM_TIM5_LSE) || \
((TIM_REMAP) == TIM_TIM5_RTC))) || \ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \ ((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \
((TIM_REMAP) == TIM_TIM11_HSE)))) ((TIM_REMAP) == TIM_TIM11_HSE))))
#elif defined(TIM2) #elif defined(TIM2)
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
((TIM_REMAP) == TIM_TIM5_LSI) || \ ((TIM_REMAP) == TIM_TIM5_LSI) || \
((TIM_REMAP) == TIM_TIM5_LSE) || \ ((TIM_REMAP) == TIM_TIM5_LSE) || \
((TIM_REMAP) == TIM_TIM5_RTC))) || \ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
((TIM_REMAP) == TIM_TIM11_HSE))) || \ ((TIM_REMAP) == TIM_TIM11_HSE))) || \
(((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \ (((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \
((TIM_REMAP) == TIM_TIM1_LPTIM))) || \ ((TIM_REMAP) == TIM_TIM1_LPTIM))) || \
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \
((TIM_REMAP) == TIM_TIM5_LPTIM))) || \ ((TIM_REMAP) == TIM_TIM5_LPTIM))) || \
(((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \ (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \
((TIM_REMAP) == TIM_TIM9_LPTIM)))) ((TIM_REMAP) == TIM_TIM9_LPTIM))))
#elif defined(TIM8) #elif defined(TIM8)
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
((TIM_REMAP) == TIM_TIM5_LSI) || \ ((TIM_REMAP) == TIM_TIM5_LSI) || \
((TIM_REMAP) == TIM_TIM5_LSE) || \ ((TIM_REMAP) == TIM_TIM5_LSE) || \
((TIM_REMAP) == TIM_TIM5_RTC))) || \ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
((TIM_REMAP) == TIM_TIM11_HSE)))) ((TIM_REMAP) == TIM_TIM11_HSE))))
#else #else
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ ((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ ((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ ((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ (((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
((TIM_REMAP) == TIM_TIM5_LSI) || \ ((TIM_REMAP) == TIM_TIM5_LSI) || \
((TIM_REMAP) == TIM_TIM5_LSE) || \ ((TIM_REMAP) == TIM_TIM5_LSE) || \
((TIM_REMAP) == TIM_TIM5_RTC))) || \ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
((TIM_REMAP) == TIM_TIM11_HSE)))) ((TIM_REMAP) == TIM_TIM11_HSE))))
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ #endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */
#else #else
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ #define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ ((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
((TIM_REMAP) == TIM_TIM5_LSI) || \ ((TIM_REMAP) == TIM_TIM5_LSI) || \
((TIM_REMAP) == TIM_TIM5_LSE) || \ ((TIM_REMAP) == TIM_TIM5_LSE) || \
((TIM_REMAP) == TIM_TIM5_RTC))) || \ ((TIM_REMAP) == TIM_TIM5_RTC))) || \
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
((TIM_REMAP) == TIM_TIM11_HSE)))) ((TIM_REMAP) == TIM_TIM11_HSE))))
#endif /* SPDIFRX */ #endif /* SPDIFRX */
/** /**
@ -318,6 +318,7 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
*/ */
/* Extended Peripheral State functions ***************************************/ /* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/** /**
* @} * @}
*/ */

29
STM32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h
Wyświetl plik

@ -94,14 +94,15 @@ typedef struct
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed. uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed */ This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface. uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY */ This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
@ -131,7 +132,7 @@ typedef struct
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type_ */ This parameter can be any value of @ref USB_LL_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
@ -168,15 +169,16 @@ typedef struct
uint8_t ep_is_in; /*!< Endpoint direction uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t speed; /*!< USB Host speed. uint8_t speed; /*!< USB Host Channel speed.
This parameter can be any value of @ref USB_Core_Speed_ */ This parameter can be any value of @ref HCD_Device_Speed:
(HCD_DEVICE_SPEED_xxx) */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type. uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_EP_Type_ */ This parameter can be any value of @ref USB_LL_EP_Type */
uint16_t max_packet; /*!< Endpoint Max packet size. uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
@ -186,6 +188,8 @@ typedef struct
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
uint32_t XferSize; /*!< OTG Channel transfer size. */
uint32_t xfer_len; /*!< Current transfer length. */ uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
@ -395,12 +399,19 @@ typedef struct
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) #define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) #define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+ USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) #define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) #define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+ USB_OTG_HOST_CHANNEL_BASE\
+ ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
#define EP_ADDR_MSK 0xFU #define EP_ADDR_MSK 0xFU

4
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
Wyświetl plik

@ -50,11 +50,11 @@
* @{ * @{
*/ */
/** /**
* @brief STM32F4xx HAL Driver version number V1.7.10 * @brief STM32F4xx HAL Driver version number V1.7.13
*/ */
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32F4xx_HAL_VERSION_SUB2 (0x0AU) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_SUB2 (0x0DU) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\

107
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c
Wyświetl plik

@ -3,7 +3,7 @@
* @file stm32f4xx_hal_adc.c * @file stm32f4xx_hal_adc.c
* @author MCD Application Team * @author MCD Application Team
* @brief This file provides firmware functions to manage the following * @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral: * functionalities of the Analog to Digital Converter (ADC) peripheral:
* + Initialization and de-initialization functions * + Initialization and de-initialization functions
* + IO operation functions * + IO operation functions
* + State and errors functions * + State and errors functions
@ -163,11 +163,11 @@
The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_ADC_RegisterCallback() Use Functions HAL_ADC_RegisterCallback()
to register an interrupt callback. to register an interrupt callback.
[..] [..]
Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: Function HAL_ADC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback (+) ConvCpltCallback : ADC conversion complete callback
(+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
(+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
@ -183,11 +183,11 @@
and a pointer to the user callback function. and a pointer to the user callback function.
[..] [..]
Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
weak function. weak function.
[..] [..]
@ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
This function allows to reset following callbacks: This function allows to reset following callbacks:
(+) ConvCpltCallback : ADC conversion complete callback (+) ConvCpltCallback : ADC conversion complete callback
@ -203,27 +203,27 @@
(+) MspDeInitCallback : ADC Msp DeInit callback (+) MspDeInitCallback : ADC Msp DeInit callback
[..] [..]
By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
all callbacks are set to the corresponding weak functions: all callbacks are set to the corresponding weak functions:
examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
these callbacks are null (not registered beforehand). these callbacks are null (not registered beforehand).
[..] [..]
If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..] [..]
Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..] [..]
Then, the user first registers the MspInit/MspDeInit user callbacks Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
or @ref HAL_ADC_Init() function. or HAL_ADC_Init() function.
[..] [..]
When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
@ -814,6 +814,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
} }
} }
} }
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */ /* Return function status */
return HAL_OK; return HAL_OK;
@ -905,13 +913,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
{ {
if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
{ {
/* Update ADC state machine to timeout */ /* New check to avoid false timeout detection in case of preemption */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))
{
/* Process unlocked */ /* Update ADC state machine to timeout */
__HAL_UNLOCK(hadc); SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
return HAL_TIMEOUT; /* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
} }
} }
} }
@ -976,13 +988,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
{ {
if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
{ {
/* Update ADC state machine to timeout */ /* New check to avoid false timeout detection in case of preemption */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))
{
/* Process unlocked */ /* Update ADC state machine to timeout */
__HAL_UNLOCK(hadc); SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
return HAL_TIMEOUT; /* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
} }
} }
} }
@ -1122,6 +1138,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
} }
} }
} }
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */ /* Return function status */
return HAL_OK; return HAL_OK;
@ -1364,6 +1388,13 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
} }
} }
/* Check ADC DMA Mode */
/* - disable the DMA Mode if it is already enabled */
if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA)
{
CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
}
/* Start conversion if ADC is effectively enabled */ /* Start conversion if ADC is effectively enabled */
if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
{ {
@ -1457,6 +1488,14 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
} }
} }
} }
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */ /* Return function status */
return HAL_OK; return HAL_OK;
@ -1490,7 +1529,17 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
/* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* DMA transfer is on going) */ /* DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
{
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
/* Check if DMA channel effectively disabled */
if (tmp_hal_status != HAL_OK)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
}
}
/* Disable ADC overrun interrupt */ /* Disable ADC overrun interrupt */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
@ -1703,7 +1752,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
/* Enable the Temperature sensor and VREFINT channel*/ /* Enable the Temperature sensor and VREFINT channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE; tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{ {
/* Delay for temperature sensor stabilization time */ /* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */ /* Compute number of CPU cycles to wait for */

36
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c
Wyświetl plik

@ -227,6 +227,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
} }
} }
} }
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */ /* Return function status */
return HAL_OK; return HAL_OK;
@ -325,6 +333,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
} }
} }
} }
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */ /* Return function status */
return HAL_OK; return HAL_OK;
@ -411,10 +427,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
{ {
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{ {
hadc->State= HAL_ADC_STATE_TIMEOUT; /* New check to avoid false timeout detection in case of preemption */
/* Process unlocked */ if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))
__HAL_UNLOCK(hadc); {
return HAL_TIMEOUT; hadc->State= HAL_ADC_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
}
} }
} }
} }
@ -684,6 +704,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
} }
} }
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
}
/* Return function status */ /* Return function status */
return HAL_OK; return HAL_OK;

52
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
Wyświetl plik

@ -199,12 +199,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
} }
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
/* Allocate lock resource */
__HAL_UNLOCK(hdma);
/* Disable the peripheral */ /* Disable the peripheral */
__HAL_DMA_DISABLE(hdma); __HAL_DMA_DISABLE(hdma);
@ -550,12 +550,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/* Update error code */ /* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */ /* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT; hdma->State = HAL_DMA_STATE_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
} }
@ -563,11 +563,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/* Clear all interrupt flags at correct offset within the register */ /* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex; regs->IFCR = 0x3FU << hdma->StreamIndex;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state*/ /* Change the DMA state*/
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
} }
return HAL_OK; return HAL_OK;
} }
@ -657,13 +657,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
{ {
/* Update error code */ /* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */ /* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
} }
@ -708,12 +708,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Clear the half transfer and transfer complete flags */ /* Clear the half transfer and transfer complete flags */
regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */ /* Change the DMA state */
hdma->State= HAL_DMA_STATE_READY; hdma->State= HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
return HAL_ERROR; return HAL_ERROR;
} }
} }
@ -724,10 +724,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Clear the half transfer and transfer complete flags */ /* Clear the half transfer and transfer complete flags */
regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hdma); __HAL_UNLOCK(hdma);
hdma->State = HAL_DMA_STATE_READY;
} }
else else
{ {
@ -863,12 +863,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Clear all interrupt flags at correct offset within the register */ /* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex; regs->IFCR = 0x3FU << hdma->StreamIndex;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */ /* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
if(hdma->XferAbortCallback != NULL) if(hdma->XferAbortCallback != NULL)
{ {
hdma->XferAbortCallback(hdma); hdma->XferAbortCallback(hdma);
@ -905,11 +905,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
/* Disable the transfer complete interrupt */ /* Disable the transfer complete interrupt */
hdma->Instance->CR &= ~(DMA_IT_TC); hdma->Instance->CR &= ~(DMA_IT_TC);
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */ /* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
} }
if(hdma->XferCpltCallback != NULL) if(hdma->XferCpltCallback != NULL)
@ -940,11 +940,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
} }
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */ /* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY; hdma->State = HAL_DMA_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
} }
if(hdma->XferErrorCallback != NULL) if(hdma->XferErrorCallback != NULL)

18
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
Wyświetl plik

@ -276,6 +276,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
pExtiConfig->Mode |= EXTI_MODE_EVENT; pExtiConfig->Mode |= EXTI_MODE_EVENT;
} }
/* Get default Trigger and GPIOSel configuration */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
/* 2] Get trigger for configurable lines : rising */ /* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{ {
@ -284,10 +288,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
{ {
pExtiConfig->Trigger = EXTI_TRIGGER_RISING; pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
} }
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */ /* Get falling configuration */
/* Check if configuration of selected line is enable */ /* Check if configuration of selected line is enable */
@ -304,16 +304,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
regval = SYSCFG->EXTICR[linepos >> 2u]; regval = SYSCFG->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
} }
else
{
pExtiConfig->GPIOSel = 0x00u;
}
}
else
{
/* No Trigger selected */
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
} }
return HAL_OK; return HAL_OK;

604
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
Wyświetl plik

Plik diff jest za duży Load Diff

57
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
Wyświetl plik

@ -123,13 +123,6 @@
/** @addtogroup GPIO_Private_Constants GPIO Private Constants /** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{ * @{
*/ */
#define GPIO_MODE 0x00000003U
#define EXTI_MODE 0x10000000U
#define GPIO_MODE_IT 0x00010000U
#define GPIO_MODE_EVT 0x00020000U
#define RISING_EDGE 0x00100000U
#define FALLING_EDGE 0x00200000U
#define GPIO_OUTPUT_TYPE 0x00000010U
#define GPIO_NUMBER 16U #define GPIO_NUMBER 16U
/** /**
@ -179,7 +172,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */ /* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++) for(position = 0U; position < GPIO_NUMBER; position++)
@ -193,8 +185,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{ {
/*--------------------- GPIO Mode Configuration ------------------------*/ /*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */ /* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{ {
/* Check the Speed parameter */ /* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
@ -207,18 +199,24 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Configure the IO Output Type */ /* Configure the IO Output Type */
temp = GPIOx->OTYPER; temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT_0 << position) ; temp &= ~(GPIO_OTYPER_OT_0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
GPIOx->OTYPER = temp; GPIOx->OTYPER = temp;
} }
/* Activate the Pull-up or Pull down resistor for the current IO */ if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
temp = GPIOx->PUPDR; {
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); /* Check the parameters */
temp |= ((GPIO_Init->Pull) << (position * 2U)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
GPIOx->PUPDR = temp;
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
temp |= ((GPIO_Init->Pull) << (position * 2U));
GPIOx->PUPDR = temp;
}
/* In case of Alternate function mode selection */ /* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
{ {
/* Check the Alternate function parameter */ /* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
@ -237,7 +235,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/*--------------------- EXTI Mode Configuration ------------------------*/ /*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */ /* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
{ {
/* Enable SYSCFG Clock */ /* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE();
@ -250,7 +248,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Clear EXTI line configuration */ /* Clear EXTI line configuration */
temp = EXTI->IMR; temp = EXTI->IMR;
temp &= ~((uint32_t)iocurrent); temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
{ {
temp |= iocurrent; temp |= iocurrent;
} }
@ -258,7 +256,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp = EXTI->EMR; temp = EXTI->EMR;
temp &= ~((uint32_t)iocurrent); temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
{ {
temp |= iocurrent; temp |= iocurrent;
} }
@ -267,7 +265,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
/* Clear Rising Falling edge configuration */ /* Clear Rising Falling edge configuration */
temp = EXTI->RTSR; temp = EXTI->RTSR;
temp &= ~((uint32_t)iocurrent); temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
{ {
temp |= iocurrent; temp |= iocurrent;
} }
@ -275,7 +273,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
temp = EXTI->FTSR; temp = EXTI->FTSR;
temp &= ~((uint32_t)iocurrent); temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
{ {
temp |= iocurrent; temp |= iocurrent;
} }
@ -434,17 +432,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
*/ */
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{ {
uint32_t odr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) /* get current Ouput Data Register value */
{ odr = GPIOx->ODR;
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
} /* Set selected pins that were at low level, and reset ones that were high */
else GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
{
GPIOx->BSRR = GPIO_Pin;
}
} }
/** /**

40
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c
Wyświetl plik

@ -90,7 +90,7 @@
(+) Stop the DMA Transfer using HAL_I2S_DMAStop() (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error
HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data.
In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data
inside DR register and avoid using DeInit/Init process for the next transfer. inside DR register and avoid using DeInit/Init process for the next transfer.
*** I2S HAL driver macros list *** *** I2S HAL driver macros list ***
@ -103,8 +103,8 @@
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
(+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data
[..] [..]
(@) You can refer to the I2S HAL driver header file for more useful macros (@) You can refer to the I2S HAL driver header file for more useful macros
@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
#endif #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
#if defined (SPI_I2S_FULLDUPLEX_SUPPORT) #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
#endif #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
if (hi2s->MspInitCallback == NULL) if (hi2s->MspInitCallback == NULL)
@ -352,7 +352,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
/* I2S standard */ /* I2S standard */
if (hi2s->Init.Standard <= I2S_STANDARD_LSB) if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
{ {
/* In I2S standard packet lenght is multiplied by 2 */ /* In I2S standard packet length is multiplied by 2 */
packetlength = packetlength * 2U; packetlength = packetlength * 2U;
} }
@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
} }
#else #else
i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S);
#endif #endif /* I2S_APB1_APB2_FEATURE */
/* Compute the Real divider depending on the MCLK output state, with a floating point */ /* Compute the Real divider depending on the MCLK output state, with a floating point */
if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
@ -469,9 +469,11 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
} }
/* Configure the I2S Slave with the I2S Master parameter values */ /* Configure the I2S Slave with the I2S Master parameter values */
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | \
(uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ (uint16_t)tmp | \
(uint16_t)hi2s->Init.CPOL)))); (uint16_t)hi2s->Init.Standard | \
(uint16_t)hi2s->Init.DataFormat | \
(uint16_t)hi2s->Init.CPOL);
/* Write to SPIx I2SCFGR */ /* Write to SPIx I2SCFGR */
WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg); WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR, tmpreg);
@ -601,7 +603,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
case HAL_I2S_TX_RX_COMPLETE_CB_ID : case HAL_I2S_TX_RX_COMPLETE_CB_ID :
hi2s->TxRxCpltCallback = pCallback; hi2s->TxRxCpltCallback = pCallback;
break; break;
#endif #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
case HAL_I2S_TX_HALF_COMPLETE_CB_ID : case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
hi2s->TxHalfCpltCallback = pCallback; hi2s->TxHalfCpltCallback = pCallback;
@ -615,7 +617,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
hi2s->TxRxHalfCpltCallback = pCallback; hi2s->TxRxHalfCpltCallback = pCallback;
break; break;
#endif #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
case HAL_I2S_ERROR_CB_ID : case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = pCallback; hi2s->ErrorCallback = pCallback;
@ -704,7 +706,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
case HAL_I2S_TX_RX_COMPLETE_CB_ID : case HAL_I2S_TX_RX_COMPLETE_CB_ID :
hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
break; break;
#endif #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
case HAL_I2S_TX_HALF_COMPLETE_CB_ID : case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
@ -718,7 +720,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
break; break;
#endif #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
case HAL_I2S_ERROR_CB_ID : case HAL_I2S_ERROR_CB_ID :
hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
@ -831,7 +833,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length * configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length. * the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
@ -948,7 +950,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length * configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length. * the Size parameter means the number of 24-bit or 32-bit data length.
* @param Timeout Timeout duration * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
@ -1049,7 +1051,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length * configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length. * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
* @retval HAL status * @retval HAL status
@ -1113,7 +1115,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length * configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length. * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
@ -1179,7 +1181,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length * configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length. * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
* @retval HAL status * @retval HAL status
@ -1270,7 +1272,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length * configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length. * the Size parameter means the number of 24-bit or 32-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
* @retval HAL status * @retval HAL status

110
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c
Wyświetl plik

@ -129,8 +129,11 @@ static void I2SEx_RxISR_I2S(I2S_HandleTypeDef *hi2s);
static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s); static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s);
static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s); static void I2SEx_TxISR_I2S(I2S_HandleTypeDef *hi2s);
static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s); static void I2SEx_TxISR_I2SExt(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed); uint32_t Flag,
uint32_t State,
uint32_t Timeout,
I2S_UseTypeDef i2sUsed);
/** /**
* @} * @}
*/ */
@ -202,8 +205,11 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s,
uint16_t Size, uint32_t Timeout) uint16_t *pTxData,
uint16_t *pRxData,
uint16_t Size,
uint32_t Timeout)
{ {
uint32_t tmp1 = 0U; uint32_t tmp1 = 0U;
HAL_StatusTypeDef errorcode = HAL_OK; HAL_StatusTypeDef errorcode = HAL_OK;
@ -420,7 +426,9 @@ error :
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s,
uint16_t *pTxData,
uint16_t *pRxData,
uint16_t Size) uint16_t Size)
{ {
uint32_t tmp1 = 0U; uint32_t tmp1 = 0U;
@ -530,7 +538,9 @@ error :
* between Master and Slave(example: audio streaming). * between Master and Slave(example: audio streaming).
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s,
uint16_t *pTxData,
uint16_t *pRxData,
uint16_t Size) uint16_t Size)
{ {
uint32_t *tmp = NULL; uint32_t *tmp = NULL;
@ -586,11 +596,11 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
/* Set the I2S Rx DMA error callback */ /* Set the I2S Rx DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError; hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
/* Set the I2S Tx DMA Half transfer complete callback */ /* Set the I2S Tx DMA Half transfer complete callback as NULL */
hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt; hi2s->hdmatx->XferHalfCpltCallback = NULL;
/* Set the I2S Tx DMA transfer complete callback */ /* Set the I2S Tx DMA transfer complete callback as NULL */
hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt; hi2s->hdmatx->XferCpltCallback = NULL;
/* Set the I2S Tx DMA error callback */ /* Set the I2S Tx DMA error callback */
hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError; hi2s->hdmatx->XferErrorCallback = I2SEx_TxRxDMAError;
@ -877,65 +887,34 @@ static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma)
{ {
I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* if DMA is configured in DMA_NORMAL mode */ /* If DMA is configured in DMA_NORMAL mode */
if (hdma->Init.Mode == DMA_NORMAL) if (hdma->Init.Mode == DMA_NORMAL)
{ {
if (hi2s->hdmarx == hdma) if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
/* Disable Tx & Rx DMA Requests */
{ {
/* Disable Rx DMA Request */ CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN);
if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \ CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)) }
{ else
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_RXDMAEN); {
} CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
else CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
{
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
}
hi2s->RxXferCount = 0U;
if (hi2s->TxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
/* Call user TxRx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxRxCpltCallback(hi2s);
#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
} }
if (hi2s->hdmatx == hdma) hi2s->RxXferCount = 0U;
{ hi2s->TxXferCount = 0U;
/* Disable Tx DMA Request */
if (((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || \
((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
{
CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
}
else
{
CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2, SPI_CR2_TXDMAEN);
}
hi2s->TxXferCount = 0U; hi2s->State = HAL_I2S_STATE_READY;
if (hi2s->RxXferCount == 0U)
{
hi2s->State = HAL_I2S_STATE_READY;
/* Call user TxRx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxRxCpltCallback(hi2s);
#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
}
}
} }
/* Call user TxRx complete callback */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
hi2s->TxRxCpltCallback(hi2s);
#else
HAL_I2SEx_TxRxCpltCallback(hi2s);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
} }
/** /**
@ -1091,8 +1070,11 @@ static void I2SEx_RxISR_I2SExt(I2S_HandleTypeDef *hi2s)
* @param i2sUsed I2S instance reference * @param i2sUsed I2S instance reference
* @retval HAL status * @retval HAL status
*/ */
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
uint32_t State, uint32_t Timeout, I2S_UseTypeDef i2sUsed) uint32_t Flag,
uint32_t State,
uint32_t Timeout,
I2S_UseTypeDef i2sUsed)
{ {
uint32_t tickstart = HAL_GetTick(); uint32_t tickstart = HAL_GetTick();

26
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c
Wyświetl plik

@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->USB_Address = 0U; hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY; hpcd->State = HAL_PCD_STATE_READY;
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Activate LPM */ /* Activate LPM */
if (hpcd->Init.lpm_enable == 1U) if (hpcd->Init.lpm_enable == 1U)
{ {
@ -721,7 +721,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
/** /**
* @brief Unregister the USB PCD Iso OUT incomplete Callback * @brief Unregister the USB PCD Iso OUT incomplete Callback
* USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * USB PCD Iso OUT incomplete Callback is redirected
* to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle * @param hpcd PCD handle
* @retval HAL status * @retval HAL status
*/ */
@ -795,7 +796,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
/** /**
* @brief Unregister the USB PCD Iso IN incomplete Callback * @brief Unregister the USB PCD Iso IN incomplete Callback
* USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * USB PCD Iso IN incomplete Callback is redirected
* to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle * @param hpcd PCD handle
* @retval HAL status * @retval HAL status
*/ */
@ -1037,6 +1039,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
/* Disable USB Transceiver */ /* Disable USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
} }
__HAL_UNLOCK(hpcd); __HAL_UNLOCK(hpcd);
return HAL_OK; return HAL_OK;
@ -1052,9 +1055,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{ {
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t i, ep_intr, epint, epnum;
uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep; USB_OTG_EPTypeDef *ep;
uint32_t i;
uint32_t ep_intr;
uint32_t epint;
uint32_t epnum;
uint32_t fifoemptymsk;
uint32_t temp;
/* ensure that we are in device mode */ /* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@ -1651,19 +1658,16 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
*/ */
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{ {
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
__HAL_LOCK(hpcd); __HAL_LOCK(hpcd);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
if ((hpcd->Init.battery_charging_enable == 1U) && if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
{ {
/* Enable USB Transceiver */ /* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
} }
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
(void)USB_DevConnect(hpcd->Instance); (void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd); __HAL_UNLOCK(hpcd);
@ -1677,21 +1681,17 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
*/ */
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{ {
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
__HAL_LOCK(hpcd); __HAL_LOCK(hpcd);
(void)USB_DevDisconnect(hpcd->Instance); (void)USB_DevDisconnect(hpcd->Instance);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
if ((hpcd->Init.battery_charging_enable == 1U) && if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
{ {
/* Disable USB Transceiver */ /* Disable USB Transceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
} }
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
__HAL_UNLOCK(hpcd); __HAL_UNLOCK(hpcd);

2
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c
Wyświetl plik

@ -164,7 +164,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
/* Enable DCD : Data Contact Detect */ /* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait Detect flag or a timeout is happen*/ /* Wait Detect flag or a timeout is happen */
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
{ {
/* Check for the Timeout */ /* Check for the Timeout */

16
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
Wyświetl plik

@ -100,11 +100,19 @@ void HAL_PWR_DeInit(void)
* backup data registers and backup SRAM). * backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled. * Backup Domain Access should be kept enabled.
* @note The following sequence is required to bypass the delay between
* DBP bit programming and the effective enabling of the backup domain.
* Please check the Errata Sheet for more details under "Possible delay
* in backup domain protection disabling/enabling after programming the
* DBP bit" section.
* @retval None * @retval None
*/ */
void HAL_PWR_EnableBkUpAccess(void) void HAL_PWR_EnableBkUpAccess(void)
{ {
__IO uint32_t dummyread;
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
dummyread = PWR->CR;
UNUSED(dummyread);
} }
/** /**
@ -112,11 +120,19 @@ void HAL_PWR_EnableBkUpAccess(void)
* backup data registers and backup SRAM). * backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled. * Backup Domain Access should be kept enabled.
* @note The following sequence is required to bypass the delay between
* DBP bit programming and the effective disabling of the backup domain.
* Please check the Errata Sheet for more details under "Possible delay
* in backup domain protection disabling/enabling after programming the
* DBP bit" section.
* @retval None * @retval None
*/ */
void HAL_PWR_DisableBkUpAccess(void) void HAL_PWR_DisableBkUpAccess(void)
{ {
__IO uint32_t dummyread;
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
dummyread = PWR->CR;
UNUSED(dummyread);
} }
/** /**

21
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
Wyświetl plik

@ -540,11 +540,22 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
{ {
/* Do not return HAL_ERROR if request repeats the current configuration */ /* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR; pll_config = RCC->PLLCFGR;
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || #if defined (RCC_PLLCFGR_PLLR)
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ)) (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
{ {
return HAL_ERROR; return HAL_ERROR;
} }

51
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
Wyświetl plik

@ -3334,7 +3334,13 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
*/ */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{ {
uint32_t tickstart = 0U; uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */ /* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
@ -3612,13 +3618,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
} }
/* Configure the main PLL clock source, multiplication and division factors. */ /* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
RCC_OscInitStruct->PLL.PLLM, RCC_OscInitStruct->PLL.PLLM | \
RCC_OscInitStruct->PLL.PLLN, (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
RCC_OscInitStruct->PLL.PLLP, (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
RCC_OscInitStruct->PLL.PLLQ, (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
RCC_OscInitStruct->PLL.PLLR); (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
/* Enable the main PLL. */ /* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE(); __HAL_RCC_PLL_ENABLE();
@ -3654,7 +3659,35 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
} }
else else
{ {
return HAL_ERROR; /* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
{
return HAL_ERROR;
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
#if defined (RCC_PLLCFGR_PLLR)
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
{
return HAL_ERROR;
}
}
} }
} }
return HAL_OK; return HAL_OK;

85
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c
Wyświetl plik

@ -108,10 +108,10 @@
[..] [..]
The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
[..] [..]
Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: Function HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback.
(+) TimeStampEventCallback : RTC TimeStamp Event callback. (+) TimeStampEventCallback : RTC TimeStamp Event callback.
@ -125,9 +125,9 @@
and a pointer to the user callback function. and a pointer to the user callback function.
[..] [..]
Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function. weak function.
@ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
This function allows to reset following callbacks: This function allows to reset following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmAEventCallback : RTC Alarm A Event callback.
@ -140,13 +140,13 @@
(+) MspDeInitCallback : RTC MspDeInit callback. (+) MspDeInitCallback : RTC MspDeInit callback.
[..] [..]
By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions : all callbacks are set to the corresponding weak functions :
examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). examples AlarmAEventCallback(), WakeUpTimerEventCallback().
Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
(not registered beforehand). (not registered beforehand).
If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..] [..]
@ -155,8 +155,8 @@
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
or @ref HAL_RTC_Init() function. or HAL_RTC_Init() function.
[..] [..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
@ -798,10 +798,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/* Set the RTC_TR register */ /* Set the RTC_TR register */
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
/* Clear the bits to be configured */ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
/* Configure the RTC_CR register */ /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
/* Exit Initialization mode */ /* Exit Initialization mode */
@ -1757,6 +1757,67 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
return hrtc->State; return hrtc->State;
} }
/**
* @brief Daylight Saving Time, Add one hour to the calendar in one single operation
* without going through the initialization procedure.
* @param hrtc RTC handle
* @retval None
*/
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc)
{
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, Substract one hour from the calendar in one
* single operation without going through the initialization procedure.
* @param hrtc RTC handle
* @retval None
*/
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc)
{
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, Set the store operation bit.
* @note It can be used by the software in order to memorize the DST status.
* @param hrtc RTC handle
* @retval None
*/
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc)
{
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
SET_BIT(hrtc->Instance->CR, RTC_CR_BKP);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, Clear the store operation bit.
* @param hrtc RTC handle
* @retval None
*/
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc)
{
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP);
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief Daylight Saving Time, Read the store operation bit.
* @param hrtc RTC handle
* @retval operation see RTC_StoreOperation_Definitions
*/
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc)
{
return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP);
}
/** /**
* @} * @}
*/ */

144
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c
Wyświetl plik

@ -131,7 +131,7 @@
DataSize = SPI_DATASIZE_8BIT: DataSize = SPI_DATASIZE_8BIT:
+----------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
| Process | Tranfert mode |---------------------|----------------------|----------------------| | Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave | | | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================| |==============================================================================================|
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
@ -156,7 +156,7 @@
DataSize = SPI_DATASIZE_16BIT: DataSize = SPI_DATASIZE_16BIT:
+----------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
| Process | Tranfert mode |---------------------|----------------------|----------------------| | Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave | | | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================| |==============================================================================================|
| T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | | T | Polling | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
@ -331,6 +331,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{ {
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
}
}
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
} }
#if (USE_SPI_CRC != 0U) #if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
@ -379,19 +397,25 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */ Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); (hspi->Init.DataSize & SPI_CR1_DFF) |
(hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
(hspi->Init.CLKPhase & SPI_CR1_CPHA) |
(hspi->Init.NSS & SPI_CR1_SSM) |
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management, TI Mode */ /* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
#if (USE_SPI_CRC != 0U) #if (USE_SPI_CRC != 0U)
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */ /* Configure : CRC Polynomial */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{ {
WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
} }
#endif /* USE_SPI_CRC */ #endif /* USE_SPI_CRC */
@ -789,6 +813,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
/* Configure communication direction : 1Line */ /* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE) if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{ {
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi); SPI_1LINE_TX(hspi);
} }
@ -909,6 +935,9 @@ error:
*/ */
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{ {
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
uint32_t tickstart; uint32_t tickstart;
HAL_StatusTypeDef errorcode = HAL_OK; HAL_StatusTypeDef errorcode = HAL_OK;
@ -964,6 +993,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
/* Configure communication direction: 1Line */ /* Configure communication direction: 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE) if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{ {
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi); SPI_1LINE_RX(hspi);
} }
@ -1058,7 +1089,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
} }
/* Read CRC to Flush DR and RXNE flag */ /* Read CRC to Flush DR and RXNE flag */
READ_REG(hspi->Instance->DR); tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
} }
#endif /* USE_SPI_CRC */ #endif /* USE_SPI_CRC */
@ -1105,6 +1138,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
uint32_t tmp_mode; uint32_t tmp_mode;
HAL_SPI_StateTypeDef tmp_state; HAL_SPI_StateTypeDef tmp_state;
uint32_t tickstart; uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
/* Variable used to alternate Rx and Tx during transfer */ /* Variable used to alternate Rx and Tx during transfer */
uint32_t txallowed = 1U; uint32_t txallowed = 1U;
@ -1275,7 +1311,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
goto error; goto error;
} }
/* Read CRC */ /* Read CRC */
READ_REG(hspi->Instance->DR); tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
} }
/* Check if CRC error occurred */ /* Check if CRC error occurred */
@ -1365,6 +1403,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */ /* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE) if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{ {
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi); SPI_1LINE_TX(hspi);
} }
@ -1452,6 +1492,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
/* Configure communication direction : 1Line */ /* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE) if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{ {
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi); SPI_1LINE_RX(hspi);
} }
@ -1622,6 +1664,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
/* Configure communication direction : 1Line */ /* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE) if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{ {
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi); SPI_1LINE_TX(hspi);
} }
@ -1735,6 +1779,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Configure communication direction : 1Line */ /* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE) if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{ {
/* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
__HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi); SPI_1LINE_RX(hspi);
} }
@ -2685,6 +2731,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{ {
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
uint32_t tickstart; uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/ /* Init tickstart for timeout management*/
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
@ -2706,7 +2755,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
} }
/* Read CRC */ /* Read CRC */
READ_REG(hspi->Instance->DR); tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
} }
#endif /* USE_SPI_CRC */ #endif /* USE_SPI_CRC */
@ -2769,6 +2820,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
{ {
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
uint32_t tickstart; uint32_t tickstart;
#if (USE_SPI_CRC != 0U)
__IO uint32_t tmpreg = 0U;
#endif /* USE_SPI_CRC */
/* Init tickstart for timeout management*/ /* Init tickstart for timeout management*/
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
@ -2789,7 +2843,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
} }
/* Read CRC to Flush DR and RXNE flag */ /* Read CRC to Flush DR and RXNE flag */
READ_REG(hspi->Instance->DR); tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
} }
#endif /* USE_SPI_CRC */ #endif /* USE_SPI_CRC */
@ -3100,8 +3156,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/ */
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{ {
/* Read 8bit CRC to flush Data Regsiter */ __IO uint8_t * ptmpreg8;
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); __IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC to flush Data Register */
tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
UNUSED(tmpreg8);
/* Disable RXNE and ERR interrupt */ /* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@ -3191,8 +3254,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/ */
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{ {
/* Read 16bit CRC to flush Data Regsiter */ __IO uint32_t tmpreg = 0U;
READ_REG(hspi->Instance->DR);
/* Read 16bit CRC to flush Data Register */
tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
/* Disable RXNE interrupt */ /* Disable RXNE interrupt */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
@ -3247,8 +3314,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
*/ */
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{ {
__IO uint8_t * ptmpreg8;
__IO uint8_t tmpreg8 = 0;
/* Initialize the 8bit temporary pointer */
ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
/* Read 8bit CRC to flush Data Register */ /* Read 8bit CRC to flush Data Register */
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); tmpreg8 = *ptmpreg8;
/* To avoid GCC warning */
UNUSED(tmpreg8);
SPI_CloseRx_ISR(hspi); SPI_CloseRx_ISR(hspi);
} }
@ -3296,8 +3370,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
*/ */
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{ {
__IO uint32_t tmpreg = 0U;
/* Read 16bit CRC to flush Data Register */ /* Read 16bit CRC to flush Data Register */
READ_REG(hspi->Instance->DR); tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
/* Disable RXNE and ERR interrupt */ /* Disable RXNE and ERR interrupt */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
@ -3403,15 +3481,26 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart) uint32_t Timeout, uint32_t Tickstart)
{ {
__IO uint32_t count;
uint32_t tmp_timeout;
uint32_t tmp_tickstart;
/* Adjust Timeout value in case of end of transfer */
tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
tmp_tickstart = HAL_GetTick();
/* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{ {
if (Timeout != HAL_MAX_DELAY) if (Timeout != HAL_MAX_DELAY)
{ {
if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
{ {
/* Disable the SPI and reset the CRC: the CRC value should be cleared /* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master on both master and slave sides in order to resynchronize the master
and slave for their respective CRC calculation */ and slave for their respective CRC calculation */
/* Disable TXE, RXNE and ERR interrupts for the interrupt process */ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
@ -3436,6 +3525,12 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi,
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
/* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
if(count == 0U)
{
tmp_timeout = 0U;
}
count--;
} }
} }
@ -3545,7 +3640,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
uint32_t tickstart; uint32_t tickstart;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Init tickstart for timeout managment*/ /* Init tickstart for timeout management */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
/* Disable ERR interrupt */ /* Disable ERR interrupt */
@ -3761,6 +3856,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
*/ */
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
{ {
__IO uint32_t tmpreg = 0U;
__IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
/* Wait until TXE flag is set */ /* Wait until TXE flag is set */
@ -3780,8 +3876,10 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
/* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
/* Read CRC to flush Data Register */ /* Flush Data Register by a blank read */
READ_REG(hspi->Instance->DR); tmpreg = READ_REG(hspi->Instance->DR);
/* To avoid GCC warning */
UNUSED(tmpreg);
hspi->State = HAL_SPI_STATE_ABORT; hspi->State = HAL_SPI_STATE_ABORT;
} }

1934
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
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Plik diff jest za duży Load Diff

769
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
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Plik diff jest za duży Load Diff

9
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c
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@ -523,8 +523,13 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
| ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
); );
/* Reset register SQR3 */
CLEAR_BIT(ADCx->SQR3,
( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4
| ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1)
);
/* Reset register JSQR */ /* Reset register JSQR */
CLEAR_BIT(ADCx->JSQR, CLEAR_BIT(ADCx->JSQR,
( ADC_JSQR_JL ( ADC_JSQR_JL

163
STM32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c
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@ -96,7 +96,8 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
{ {
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
} }
/* Reset after a PHY select */
/* Reset after a PHY select */
ret = USB_CoreReset(USBx); ret = USB_CoreReset(USBx);
} }
else /* FS interface (embedded Phy) */ else /* FS interface (embedded Phy) */
@ -247,21 +248,39 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
*/ */
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
{ {
uint32_t ms = 0U;
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
if (mode == USB_HOST_MODE) if (mode == USB_HOST_MODE)
{ {
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
do
{
HAL_Delay(1U);
ms++;
} while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U));
} }
else if (mode == USB_DEVICE_MODE) else if (mode == USB_DEVICE_MODE)
{ {
USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
do
{
HAL_Delay(1U);
ms++;
} while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U));
} }
else else
{ {
return HAL_ERROR; return HAL_ERROR;
} }
HAL_Delay(50U);
if (ms == 50U)
{
return HAL_ERROR;
}
return HAL_OK; return HAL_OK;
} }
@ -452,7 +471,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
*/ */
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
{ {
uint32_t count = 0U; __IO uint32_t count = 0U;
USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
@ -474,7 +493,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
*/ */
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{ {
uint32_t count = 0; __IO uint32_t count = 0U;
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
@ -513,8 +532,8 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
* @param USBx Selected device * @param USBx Selected device
* @retval speed device speed * @retval speed device speed
* This parameter can be one of these values: * This parameter can be one of these values:
* @arg PCD_SPEED_HIGH: High speed mode * @arg USBD_HS_SPEED: High speed mode
* @arg PCD_SPEED_FULL: Full speed mode * @arg USBD_FS_SPEED: Full speed mode
*/ */
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{ {
@ -736,7 +755,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
*/ */
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
(((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
if (ep->type == EP_TYPE_ISOC) if (ep->type == EP_TYPE_ISOC)
@ -957,8 +978,9 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
uint8_t ch_ep_num, uint16_t len, uint8_t dma) uint8_t ch_ep_num, uint16_t len, uint8_t dma)
{ {
uint32_t USBx_BASE = (uint32_t)USBx; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t *pSrc = (uint32_t *)src; uint8_t *pSrc = src;
uint32_t count32b, i; uint32_t count32b;
uint32_t i;
if (dma == 0U) if (dma == 0U)
{ {
@ -967,6 +989,9 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
{ {
USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);
pSrc++; pSrc++;
pSrc++;
pSrc++;
pSrc++;
} }
} }
@ -983,14 +1008,34 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{ {
uint32_t USBx_BASE = (uint32_t)USBx; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t *pDest = (uint32_t *)dest; uint8_t *pDest = dest;
uint32_t pData;
uint32_t i; uint32_t i;
uint32_t count32b = ((uint32_t)len + 3U) / 4U; uint32_t count32b = (uint32_t)len >> 2U;
uint16_t remaining_bytes = len % 4U;
for (i = 0U; i < count32b; i++) for (i = 0U; i < count32b; i++)
{ {
__UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));
pDest++; pDest++;
pDest++;
pDest++;
pDest++;
}
/* When Number of data is not word aligned, read the remaining byte */
if (remaining_bytes != 0U)
{
i = 0U;
__UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
do
{
*(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
i++;
pDest++;
remaining_bytes--;
} while (remaining_bytes != 0U);
} }
return ((void *)pDest); return ((void *)pDest);
@ -1222,7 +1267,9 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
{ {
uint32_t USBx_BASE = (uint32_t)USBx; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tmpreg, msk, emp; uint32_t tmpreg;
uint32_t msk;
uint32_t emp;
msk = USBx_DEVICE->DIEPMSK; msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK; emp = USBx_DEVICE->DIEPEMPMSK;
@ -1318,7 +1365,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin
*/ */
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{ {
uint32_t count = 0U; __IO uint32_t count = 0U;
/* Wait for AHB master IDLE state. */ /* Wait for AHB master IDLE state. */
do do
@ -1407,11 +1454,6 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
USBx_HC(i)->HCINTMSK = 0U; USBx_HC(i)->HCINTMSK = 0U;
} }
/* Enable VBUS driving */
(void)USB_DriveVbus(USBx, 1U);
HAL_Delay(200U);
/* Disable all interrupts. */ /* Disable all interrupts. */
USBx->GINTMSK = 0U; USBx->GINTMSK = 0U;
@ -1586,7 +1628,7 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
* @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type * @arg EP_TYPE_INTR: Interrupt type
* @param mps Max Packet Size * @param mps Max Packet Size
* This parameter can be a value from 0 to32K * This parameter can be a value from 0 to 32K
* @retval HAL state * @retval HAL state
*/ */
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
@ -1595,7 +1637,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
{ {
HAL_StatusTypeDef ret = HAL_OK; HAL_StatusTypeDef ret = HAL_OK;
uint32_t USBx_BASE = (uint32_t)USBx; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t HCcharEpDir, HCcharLowSpeed; uint32_t HCcharEpDir;
uint32_t HCcharLowSpeed;
uint32_t HostCoreSpeed;
/* Clear old interrupt conditions for this host channel. */ /* Clear old interrupt conditions for this host channel. */
USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
@ -1620,7 +1664,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
{ {
if ((USBx->CID & (0x1U << 8)) != 0U) if ((USBx->CID & (0x1U << 8)) != 0U)
{ {
USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
USB_OTG_HCINTMSK_ACKM;
} }
} }
break; break;
@ -1674,7 +1719,10 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
HCcharEpDir = 0U; HCcharEpDir = 0U;
} }
if (speed == HPRT0_PRTSPD_LOW_SPEED) HostCoreSpeed = USB_GetHostSpeed(USBx);
/* LS device plugged to HUB */
if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))
{ {
HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;
} }
@ -1710,7 +1758,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
{ {
uint32_t USBx_BASE = (uint32_t)USBx; uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t ch_num = (uint32_t)hc->ch_num; uint32_t ch_num = (uint32_t)hc->ch_num;
static __IO uint32_t tmpreg = 0U; __IO uint32_t tmpreg;
uint8_t is_oddframe; uint8_t is_oddframe;
uint16_t len_words; uint16_t len_words;
uint16_t num_packets; uint16_t num_packets;
@ -1718,20 +1766,20 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
{ {
/* in DMA mode host Core automatically issues ping in case of NYET/NAK */
if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)))
{
USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
USB_OTG_HCINTMSK_ACKM |
USB_OTG_HCINTMSK_NAKM);
}
if ((dma == 0U) && (hc->do_ping == 1U)) if ((dma == 0U) && (hc->do_ping == 1U))
{ {
(void)USB_DoPing(USBx, hc->ch_num); (void)USB_DoPing(USBx, hc->ch_num);
return HAL_OK; return HAL_OK;
} }
else if (dma == 1U)
{
USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
hc->do_ping = 0U;
}
else
{
/* ... */
}
} }
/* Compute the expected number of packets associated to the transfer */ /* Compute the expected number of packets associated to the transfer */
@ -1742,20 +1790,29 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
if (num_packets > max_hc_pkt_count) if (num_packets > max_hc_pkt_count)
{ {
num_packets = max_hc_pkt_count; num_packets = max_hc_pkt_count;
hc->xfer_len = (uint32_t)num_packets * hc->max_packet; hc->XferSize = (uint32_t)num_packets * hc->max_packet;
} }
} }
else else
{ {
num_packets = 1U; num_packets = 1U;
} }
/*
* For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
* max_packet size.
*/
if (hc->ep_is_in != 0U) if (hc->ep_is_in != 0U)
{ {
hc->xfer_len = (uint32_t)num_packets * hc->max_packet; hc->XferSize = (uint32_t)num_packets * hc->max_packet;
}
else
{
hc->XferSize = hc->xfer_len;
} }
/* Initialize the HCTSIZn register */ /* Initialize the HCTSIZn register */
USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |
(((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |
(((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);
@ -1856,28 +1913,38 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
uint32_t hcnum = (uint32_t)hc_num; uint32_t hcnum = (uint32_t)hc_num;
uint32_t count = 0U; uint32_t count = 0U;
uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
(ChannelEna == 0U))
{
return HAL_OK;
}
/* Check for space in the request queue to issue the halt. */ /* Check for space in the request queue to issue the halt. */
if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))
{ {
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)
{ {
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{ {
if (++count > 1000U) USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
do
{ {
break; if (++count > 1000U)
} {
} while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); break;
} }
else } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
{ }
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; else
{
USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
}
} }
} }
else else

42
STM32/MDK-ARM/RTE/_WOLF-Lite/RTE_Components.h
Wyświetl plik

@ -1,21 +1,21 @@
/* /*
* Auto generated Run-Time-Environment Configuration File * Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! *** * *** Do not modify ! ***
* *
* Project: 'WOLF-Lite' * Project: 'WOLF-Lite'
* Target: 'WOLF-Lite' * Target: 'WOLF-Lite'
*/ */
#ifndef RTE_COMPONENTS_H #ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H #define RTE_COMPONENTS_H
/* /*
* Define the Device Header File: * Define the Device Header File:
*/ */
#define CMSIS_device_header "stm32f4xx.h" #define CMSIS_device_header "stm32f4xx.h"
#endif /* RTE_COMPONENTS_H */ #endif /* RTE_COMPONENTS_H */

390
STM32/MDK-ARM/WOLF-Lite.uvoptx
Wyświetl plik

Plik diff jest za duży Load Diff

72
STM32/MDK-ARM/WOLF-Lite.uvprojx
Wyświetl plik

@ -10,7 +10,7 @@
<TargetName>WOLF-Lite</TargetName> <TargetName>WOLF-Lite</TargetName>
<ToolsetNumber>0x4</ToolsetNumber> <ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName> <ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6150000::V6.15::ARMCLANG</pCCUsed> <pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
<uAC6>1</uAC6> <uAC6>1</uAC6>
<TargetOption> <TargetOption>
<TargetCommonOption> <TargetCommonOption>
@ -339,7 +339,7 @@
<MiscControls></MiscControls> <MiscControls></MiscControls>
<Define>USE_HAL_DRIVER,STM32F407xx,ARM_MATH_MATRIX_CHECK,ARM_MATH_ROUNDING,ARM_MATH_LOOPUNROLL</Define> <Define>USE_HAL_DRIVER,STM32F407xx,ARM_MATH_MATRIX_CHECK,ARM_MATH_ROUNDING,ARM_MATH_LOOPUNROLL</Define>
<Undefine></Undefine> <Undefine></Undefine>
<IncludePath>../Core/Inc; ../Drivers/STM32F4xx_HAL_Driver/Inc; ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy; ../Drivers/CMSIS/Device/ST/STM32F4xx/Include; ../Drivers/CMSIS/Include; ..\Core\USBDevice; ..\Core\Src; ..\Core\Src</IncludePath> <IncludePath>../Core/Inc; ../Drivers/STM32F4xx_HAL_Driver/Inc; ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy; ../Drivers/CMSIS/Device/ST/STM32F4xx/Include; ../Drivers/CMSIS/Include; ..\Core\USBDevice; ..\Core\Src; ..\Core\Src</IncludePath>
</VariousControls> </VariousControls>
</Cads> </Cads>
<Aads> <Aads>
@ -458,6 +458,16 @@
<FileType>5</FileType> <FileType>5</FileType>
<FilePath>..\Core\Src\color_themes.h</FilePath> <FilePath>..\Core\Src\color_themes.h</FilePath>
</File> </File>
<File>
<FileName>cw.c</FileName>
<FileType>1</FileType>
<FilePath>..\Core\Src\cw.c</FilePath>
</File>
<File>
<FileName>cw.h</FileName>
<FileType>5</FileType>
<FilePath>..\Core\Src\cw.h</FilePath>
</File>
<File> <File>
<FileName>fft.c</FileName> <FileName>fft.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@ -703,6 +713,62 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c</FilePath> <FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c</FilePath>
</File> </File>
<File>
<FileName>stm32f4xx_ll_adc.c</FileName>
<FileType>1</FileType>
<FilePath>../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c</FilePath>
<FileOption>
<CommonProperty>
<UseCPPCompiler>2</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<FileArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
</FileArmAds>
</FileOption>
</File>
<File> <File>
<FileName>stm32f4xx_hal_rcc.c</FileName> <FileName>stm32f4xx_hal_rcc.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
@ -939,7 +1005,7 @@
<LayerInfo> <LayerInfo>
<Layers> <Layers>
<Layer> <Layer>
<LayName>&lt;Project Info&gt;</LayName> <LayName>WOLF-Lite</LayName>
<LayTarg>0</LayTarg> <LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark> <LayPrjMark>1</LayPrjMark>
</Layer> </Layer>

17
STM32/MDK-ARM/WOLF-Lite/WOLF-Lite.lnp
Wyświetl plik

@ -6,6 +6,7 @@
"wolf-lite\auto_notch.o" "wolf-lite\auto_notch.o"
"wolf-lite\bands.o" "wolf-lite\bands.o"
"wolf-lite\bootloader.o" "wolf-lite\bootloader.o"
"wolf-lite\cw.o"
"wolf-lite\fft.o" "wolf-lite\fft.o"
"wolf-lite\fpga.o" "wolf-lite\fpga.o"
"wolf-lite\functions.o" "wolf-lite\functions.o"
@ -30,6 +31,7 @@
"wolf-lite\stm32f4xx_hal_msp.o" "wolf-lite\stm32f4xx_hal_msp.o"
"wolf-lite\stm32f4xx_hal_adc.o" "wolf-lite\stm32f4xx_hal_adc.o"
"wolf-lite\stm32f4xx_hal_adc_ex.o" "wolf-lite\stm32f4xx_hal_adc_ex.o"
"wolf-lite\stm32f4xx_ll_adc.o"
"wolf-lite\stm32f4xx_hal_rcc.o" "wolf-lite\stm32f4xx_hal_rcc.o"
"wolf-lite\stm32f4xx_hal_rcc_ex.o" "wolf-lite\stm32f4xx_hal_rcc_ex.o"
"wolf-lite\stm32f4xx_hal_flash.o" "wolf-lite\stm32f4xx_hal_flash.o"
@ -63,18 +65,33 @@
"wolf-lite\usbd_desc.o" "wolf-lite\usbd_desc.o"
"wolf-lite\usbd_ioreq.o" "wolf-lite\usbd_ioreq.o"
"wolf-lite\basicmathfunctions.o" "wolf-lite\basicmathfunctions.o"
"wolf-lite\basicmathfunctionsf16.o"
"wolf-lite\bayesfunctions.o" "wolf-lite\bayesfunctions.o"
"wolf-lite\bayesfunctionsf16.o"
"wolf-lite\commontables.o" "wolf-lite\commontables.o"
"wolf-lite\commontablesf16.o"
"wolf-lite\complexmathfunctions.o" "wolf-lite\complexmathfunctions.o"
"wolf-lite\complexmathfunctionsf16.o"
"wolf-lite\controllerfunctions.o" "wolf-lite\controllerfunctions.o"
"wolf-lite\distancefunctions.o" "wolf-lite\distancefunctions.o"
"wolf-lite\distancefunctionsf16.o"
"wolf-lite\fastmathfunctions.o" "wolf-lite\fastmathfunctions.o"
"wolf-lite\fastmathfunctionsf16.o"
"wolf-lite\filteringfunctions.o" "wolf-lite\filteringfunctions.o"
"wolf-lite\filteringfunctionsf16.o"
"wolf-lite\interpolationfunctions.o"
"wolf-lite\interpolationfunctionsf16.o"
"wolf-lite\matrixfunctions.o" "wolf-lite\matrixfunctions.o"
"wolf-lite\matrixfunctionsf16.o"
"wolf-lite\quaternionmathfunctions.o"
"wolf-lite\svmfunctions.o" "wolf-lite\svmfunctions.o"
"wolf-lite\svmfunctionsf16.o"
"wolf-lite\statisticsfunctions.o" "wolf-lite\statisticsfunctions.o"
"wolf-lite\statisticsfunctionsf16.o"
"wolf-lite\supportfunctions.o" "wolf-lite\supportfunctions.o"
"wolf-lite\supportfunctionsf16.o"
"wolf-lite\transformfunctions.o" "wolf-lite\transformfunctions.o"
"wolf-lite\transformfunctionsf16.o"
--strict --scatter ".\WOLF-Lite\WOLF-Lite-custom.sct" --strict --scatter ".\WOLF-Lite\WOLF-Lite-custom.sct"
--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
--info sizes --info totals --info unused --info veneers --info sizes --info totals --info unused --info veneers

179
STM32/WOLF-Lite.ioc
Wyświetl plik

@ -1,52 +1,71 @@
#MicroXplorer Configuration settings - do not modify #MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10 ADC1.Channel-10\#ChannelInjectedConversion=ADC_CHANNEL_VBAT
ADC1.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_11 ADC1.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_TEMPSENSOR
ADC1.Channel-2\#ChannelInjectedConversion=ADC_CHANNEL_10 ADC1.Channel-8\#ChannelInjectedConversion=ADC_CHANNEL_TEMPSENSOR
ADC1.Channel-3\#ChannelInjectedConversion=ADC_CHANNEL_8 ADC1.Channel-9\#ChannelInjectedConversion=ADC_CHANNEL_VREFINT
ADC1.Channel-4\#ChannelInjectedConversion=ADC_CHANNEL_9
ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4
ADC1.ContinuousConvMode=ENABLE ADC1.ContinuousConvMode=ENABLE
ADC1.EOCSelection=ADC_EOC_SEQ_CONV ADC1.EOCSelection=ADC_EOC_SEQ_CONV
ADC1.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T4_TRGO
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ScanConvMode,ContinuousConvMode,EOCSelection,NbrOfConversion,InjectedRank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,InjectedRank-2\#ChannelInjectedConversion,Channel-2\#ChannelInjectedConversion,SamplingTime-2\#ChannelInjectedConversion,InjectedOffset-2\#ChannelInjectedConversion,InjNumberOfConversion,ExternalTrigInjecConv,InjectedRank-3\#ChannelInjectedConversion,Channel-3\#ChannelInjectedConversion,SamplingTime-3\#ChannelInjectedConversion,InjectedOffset-3\#ChannelInjectedConversion,InjectedRank-4\#ChannelInjectedConversion,Channel-4\#ChannelInjectedConversion,SamplingTime-4\#ChannelInjectedConversion,InjectedOffset-4\#ChannelInjectedConversion,ClockPrescaler ADC1.IPParameters=Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,NbrOfConversionFlag,master,NbrOfConversion,ContinuousConvMode,EOCSelection,InjectedRank-8\#ChannelInjectedConversion,Channel-8\#ChannelInjectedConversion,SamplingTime-8\#ChannelInjectedConversion,InjectedOffset-8\#ChannelInjectedConversion,InjectedRank-9\#ChannelInjectedConversion,Channel-9\#ChannelInjectedConversion,SamplingTime-9\#ChannelInjectedConversion,InjectedOffset-9\#ChannelInjectedConversion,InjectedRank-10\#ChannelInjectedConversion,Channel-10\#ChannelInjectedConversion,SamplingTime-10\#ChannelInjectedConversion,InjectedOffset-10\#ChannelInjectedConversion,InjNumberOfConversion,ExternalTrigInjecConv
ADC1.InjNumberOfConversion=4 ADC1.InjNumberOfConversion=3
ADC1.InjectedOffset-1\#ChannelInjectedConversion=0 ADC1.InjectedOffset-10\#ChannelInjectedConversion=0
ADC1.InjectedOffset-2\#ChannelInjectedConversion=0 ADC1.InjectedOffset-8\#ChannelInjectedConversion=0
ADC1.InjectedOffset-3\#ChannelInjectedConversion=0 ADC1.InjectedOffset-9\#ChannelInjectedConversion=0
ADC1.InjectedOffset-4\#ChannelInjectedConversion=0 ADC1.InjectedRank-10\#ChannelInjectedConversion=3
ADC1.InjectedRank-1\#ChannelInjectedConversion=1 ADC1.InjectedRank-8\#ChannelInjectedConversion=1
ADC1.InjectedRank-2\#ChannelInjectedConversion=2 ADC1.InjectedRank-9\#ChannelInjectedConversion=2
ADC1.InjectedRank-3\#ChannelInjectedConversion=3
ADC1.InjectedRank-4\#ChannelInjectedConversion=4
ADC1.NbrOfConversion=1 ADC1.NbrOfConversion=1
ADC1.NbrOfConversionFlag=1 ADC1.NbrOfConversionFlag=1
ADC1.Rank-0\#ChannelRegularConversion=1 ADC1.Rank-5\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC1.SamplingTime-10\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC1.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLETIME_28CYCLES
ADC1.SamplingTime-2\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES ADC1.SamplingTime-8\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC1.SamplingTime-3\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES ADC1.SamplingTime-9\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC1.SamplingTime-4\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC1.ScanConvMode=ENABLE
ADC1.master=1 ADC1.master=1
ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_14 ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_14
ADC2.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_14 ADC2.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_14
ADC2.Channel-2\#ChannelInjectedConversion=ADC_CHANNEL_15 ADC2.Channel-2\#ChannelInjectedConversion=ADC_CHANNEL_15
ADC2.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4 ADC2.Channel-3\#ChannelInjectedConversion=ADC_CHANNEL_8
ADC2.Channel-4\#ChannelInjectedConversion=ADC_CHANNEL_9
ADC2.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2
ADC2.ContinuousConvMode=ENABLE ADC2.ContinuousConvMode=ENABLE
ADC2.EOCSelection=ADC_EOC_SEQ_CONV ADC2.EOCSelection=ADC_EOC_SEQ_CONV
ADC2.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC2.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T4_TRGO
ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,ScanConvMode,ContinuousConvMode,EOCSelection,InjectedRank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,InjNumberOfConversion,ExternalTrigInjecConv,InjectedRank-2\#ChannelInjectedConversion,Channel-2\#ChannelInjectedConversion,SamplingTime-2\#ChannelInjectedConversion,InjectedOffset-2\#ChannelInjectedConversion ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,ScanConvMode,ContinuousConvMode,EOCSelection,InjectedRank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,InjNumberOfConversion,ExternalTrigInjecConv,InjectedRank-2\#ChannelInjectedConversion,Channel-2\#ChannelInjectedConversion,SamplingTime-2\#ChannelInjectedConversion,InjectedOffset-2\#ChannelInjectedConversion,InjectedRank-3\#ChannelInjectedConversion,Channel-3\#ChannelInjectedConversion,SamplingTime-3\#ChannelInjectedConversion,InjectedOffset-3\#ChannelInjectedConversion,InjectedRank-4\#ChannelInjectedConversion,Channel-4\#ChannelInjectedConversion,SamplingTime-4\#ChannelInjectedConversion,InjectedOffset-4\#ChannelInjectedConversion
ADC2.InjNumberOfConversion=2 ADC2.InjNumberOfConversion=4
ADC2.InjectedOffset-1\#ChannelInjectedConversion=0 ADC2.InjectedOffset-1\#ChannelInjectedConversion=0
ADC2.InjectedOffset-2\#ChannelInjectedConversion=0 ADC2.InjectedOffset-2\#ChannelInjectedConversion=0
ADC2.InjectedOffset-3\#ChannelInjectedConversion=0
ADC2.InjectedOffset-4\#ChannelInjectedConversion=0
ADC2.InjectedRank-1\#ChannelInjectedConversion=1 ADC2.InjectedRank-1\#ChannelInjectedConversion=1
ADC2.InjectedRank-2\#ChannelInjectedConversion=2 ADC2.InjectedRank-2\#ChannelInjectedConversion=2
ADC2.InjectedRank-3\#ChannelInjectedConversion=3
ADC2.InjectedRank-4\#ChannelInjectedConversion=4
ADC2.NbrOfConversionFlag=1 ADC2.NbrOfConversionFlag=1
ADC2.Rank-0\#ChannelRegularConversion=1 ADC2.Rank-0\#ChannelRegularConversion=1
ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC2.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES ADC2.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC2.SamplingTime-2\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES ADC2.SamplingTime-2\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC2.SamplingTime-3\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC2.SamplingTime-4\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC2.ScanConvMode=ENABLE ADC2.ScanConvMode=ENABLE
ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10
ADC3.Channel-1\#ChannelInjectedConversion=ADC_CHANNEL_10
ADC3.Channel-2\#ChannelInjectedConversion=ADC_CHANNEL_11
ADC3.EOCSelection=ADC_EOC_SEQ_CONV
ADC3.ExternalTrigInjecConv=ADC_EXTERNALTRIGINJECCONV_T4_TRGO
ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,InjectedRank-1\#ChannelInjectedConversion,Channel-1\#ChannelInjectedConversion,SamplingTime-1\#ChannelInjectedConversion,InjectedOffset-1\#ChannelInjectedConversion,InjectedRank-2\#ChannelInjectedConversion,Channel-2\#ChannelInjectedConversion,SamplingTime-2\#ChannelInjectedConversion,InjectedOffset-2\#ChannelInjectedConversion,InjNumberOfConversion,NbrOfConversion,ExternalTrigInjecConv,EOCSelection
ADC3.InjNumberOfConversion=2
ADC3.InjectedOffset-1\#ChannelInjectedConversion=0
ADC3.InjectedOffset-2\#ChannelInjectedConversion=0
ADC3.InjectedRank-1\#ChannelInjectedConversion=1
ADC3.InjectedRank-2\#ChannelInjectedConversion=2
ADC3.NbrOfConversion=1
ADC3.NbrOfConversionFlag=1
ADC3.Rank-0\#ChannelRegularConversion=1
ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES
ADC3.SamplingTime-1\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
ADC3.SamplingTime-2\#ChannelInjectedConversion=ADC_SAMPLETIME_28CYCLES
Dma.I2S3_EXT_RX.9.Direction=DMA_PERIPH_TO_MEMORY Dma.I2S3_EXT_RX.9.Direction=DMA_PERIPH_TO_MEMORY
Dma.I2S3_EXT_RX.9.FIFOMode=DMA_FIFOMODE_ENABLE Dma.I2S3_EXT_RX.9.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.I2S3_EXT_RX.9.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL Dma.I2S3_EXT_RX.9.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
@ -208,22 +227,23 @@ KeepUserPlacement=false
Mcu.Family=STM32F4 Mcu.Family=STM32F4
Mcu.IP0=ADC1 Mcu.IP0=ADC1
Mcu.IP1=ADC2 Mcu.IP1=ADC2
Mcu.IP10=TIM3 Mcu.IP10=SYS
Mcu.IP11=TIM4 Mcu.IP11=TIM3
Mcu.IP12=TIM5 Mcu.IP12=TIM4
Mcu.IP13=TIM6 Mcu.IP13=TIM5
Mcu.IP14=TIM7 Mcu.IP14=TIM6
Mcu.IP15=TIM8 Mcu.IP15=TIM7
Mcu.IP16=USB_OTG_FS Mcu.IP16=TIM8
Mcu.IP2=DMA Mcu.IP17=USB_OTG_FS
Mcu.IP3=FSMC Mcu.IP2=ADC3
Mcu.IP4=I2S3 Mcu.IP3=DMA
Mcu.IP5=NVIC Mcu.IP4=FSMC
Mcu.IP6=RCC Mcu.IP5=I2S3
Mcu.IP7=RTC Mcu.IP6=NVIC
Mcu.IP8=SPI2 Mcu.IP7=RCC
Mcu.IP9=SYS Mcu.IP8=RTC
Mcu.IPNb=17 Mcu.IP9=SPI2
Mcu.IPNb=18
Mcu.Name=STM32F407V(E-G)Tx Mcu.Name=STM32F407V(E-G)Tx
Mcu.Package=LQFP100 Mcu.Package=LQFP100
Mcu.Pin0=PE3 Mcu.Pin0=PE3
@ -294,22 +314,25 @@ Mcu.Pin67=PB8
Mcu.Pin68=PE0 Mcu.Pin68=PE0
Mcu.Pin69=PE1 Mcu.Pin69=PE1
Mcu.Pin7=PH0-OSC_IN Mcu.Pin7=PH0-OSC_IN
Mcu.Pin70=VP_RTC_VS_RTC_Activate Mcu.Pin70=VP_ADC1_TempSens_Input
Mcu.Pin71=VP_SYS_VS_Systick Mcu.Pin71=VP_ADC1_Vref_Input
Mcu.Pin72=VP_TIM3_VS_ClockSourceINT Mcu.Pin72=VP_ADC1_Vbat_Input
Mcu.Pin73=VP_TIM4_VS_ClockSourceINT Mcu.Pin73=VP_RTC_VS_RTC_Activate
Mcu.Pin74=VP_TIM5_VS_ClockSourceINT Mcu.Pin74=VP_SYS_VS_Systick
Mcu.Pin75=VP_TIM6_VS_ClockSourceINT Mcu.Pin75=VP_TIM3_VS_ClockSourceINT
Mcu.Pin76=VP_TIM7_VS_ClockSourceINT Mcu.Pin76=VP_TIM4_VS_ClockSourceINT
Mcu.Pin77=VP_TIM8_VS_ClockSourceINT Mcu.Pin77=VP_TIM5_VS_ClockSourceINT
Mcu.Pin78=VP_TIM6_VS_ClockSourceINT
Mcu.Pin79=VP_TIM7_VS_ClockSourceINT
Mcu.Pin8=PH1-OSC_OUT Mcu.Pin8=PH1-OSC_OUT
Mcu.Pin80=VP_TIM8_VS_ClockSourceINT
Mcu.Pin9=PC0 Mcu.Pin9=PC0
Mcu.PinsNb=78 Mcu.PinsNb=81
Mcu.ThirdPartyNb=0 Mcu.ThirdPartyNb=0
Mcu.UserConstants= Mcu.UserConstants=
Mcu.UserName=STM32F407VETx Mcu.UserName=STM32F407VETx
MxCube.Version=6.2.1 MxCube.Version=6.3.0
MxDb.Version=DB.6.0.21 MxDb.Version=DB.6.0.30
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DMA1_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true NVIC.DMA1_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.DMA1_Stream5_IRQn=true\:1\:0\:true\:false\:true\:false\:true NVIC.DMA1_Stream5_IRQn=true\:1\:0\:true\:false\:true\:false\:true
@ -428,7 +451,6 @@ PA7.PinState=GPIO_PIN_RESET
PA7.Signal=GPIO_Output PA7.Signal=GPIO_Output
PB0.GPIOParameters=GPIO_Label PB0.GPIOParameters=GPIO_Label
PB0.GPIO_Label=PTT_SW1 PB0.GPIO_Label=PTT_SW1
PB0.Locked=true
PB0.Signal=ADCx_IN8 PB0.Signal=ADCx_IN8
PB1.GPIOParameters=GPIO_Label PB1.GPIOParameters=GPIO_Label
PB1.GPIO_Label=PTT_SW2 PB1.GPIO_Label=PTT_SW2
@ -478,13 +500,17 @@ PB6.GPIO_PuPd=GPIO_PULLUP
PB6.Locked=true PB6.Locked=true
PB6.PinState=GPIO_PIN_SET PB6.PinState=GPIO_PIN_SET
PB6.Signal=GPIO_Output PB6.Signal=GPIO_Output
PB7.GPIOParameters=GPIO_PuPd,GPIO_Label PB7.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
PB7.GPIO_Label=CPU_PW PB7.GPIO_Label=CPU_PW
PB7.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
PB7.GPIO_PuPd=GPIO_PULLUP PB7.GPIO_PuPd=GPIO_PULLUP
PB7.Locked=true PB7.Locked=true
PB7.Signal=GPXTI7 PB7.Signal=GPXTI7
PB8.GPIOParameters=GPIO_PuPd,GPIO_Label
PB8.GPIO_Label=LCD_BL_PWM
PB8.GPIO_PuPd=GPIO_PULLDOWN
PB8.Locked=true PB8.Locked=true
PB8.Signal=S_TIM4_CH3 PB8.Signal=GPIO_Output
PC0.GPIOParameters=GPIO_Label PC0.GPIOParameters=GPIO_Label
PC0.GPIO_Label=SWR_FORW PC0.GPIO_Label=SWR_FORW
PC0.Locked=true PC0.Locked=true
@ -616,13 +642,15 @@ PD9.GPIO_PuPd=GPIO_NOPULL
PD9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_LOW PD9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_LOW
PD9.Mode=16b-d1 PD9.Mode=16b-d1
PD9.Signal=FSMC_D14 PD9.Signal=FSMC_D14
PE0.GPIOParameters=GPIO_PuPd,GPIO_Label PE0.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
PE0.GPIO_Label=KEY_IN_DASH PE0.GPIO_Label=KEY_IN_DASH
PE0.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
PE0.GPIO_PuPd=GPIO_PULLUP PE0.GPIO_PuPd=GPIO_PULLUP
PE0.Locked=true PE0.Locked=true
PE0.Signal=GPXTI0 PE0.Signal=GPXTI0
PE1.GPIOParameters=GPIO_PuPd,GPIO_Label PE1.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
PE1.GPIO_Label=KEY_IN_DOT PE1.GPIO_Label=KEY_IN_DOT
PE1.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING
PE1.GPIO_PuPd=GPIO_PULLUP PE1.GPIO_PuPd=GPIO_PULLUP
PE1.Locked=true PE1.Locked=true
PE1.Signal=GPXTI1 PE1.Signal=GPXTI1
@ -706,10 +734,10 @@ ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F407VETx ProjectManager.DeviceId=STM32F407VETx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.26.1 ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.26.2
ProjectManager.FreePins=true ProjectManager.FreePins=true
ProjectManager.HalAssertFull=false ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x1F00 ProjectManager.HeapSize=0x0000
ProjectManager.KeepUserCode=true ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1 ProjectManager.LibraryCopy=1
@ -765,18 +793,23 @@ RCC.VCOI2SOutputFreq_Value=128000000
RCC.VCOInputFreq_Value=1000000 RCC.VCOInputFreq_Value=1000000
RCC.VCOOutputFreq_Value=336000000 RCC.VCOOutputFreq_Value=336000000
RCC.VcooutputI2S=32000000 RCC.VcooutputI2S=32000000
SH.ADCx_IN10.0=ADC1_IN10,IN10 SH.ADCx_IN10.0=ADC1_IN10
SH.ADCx_IN10.ConfNb=1 SH.ADCx_IN10.1=ADC2_IN10
SH.ADCx_IN11.0=ADC1_IN11,IN11 SH.ADCx_IN10.2=ADC3_IN10,IN10
SH.ADCx_IN11.ConfNb=1 SH.ADCx_IN10.ConfNb=3
SH.ADCx_IN11.0=ADC1_IN11
SH.ADCx_IN11.1=ADC2_IN11
SH.ADCx_IN11.2=ADC3_IN11,IN11
SH.ADCx_IN11.ConfNb=3
SH.ADCx_IN14.0=ADC2_IN14,IN14 SH.ADCx_IN14.0=ADC2_IN14,IN14
SH.ADCx_IN14.ConfNb=1 SH.ADCx_IN14.ConfNb=1
SH.ADCx_IN15.0=ADC2_IN15,IN15 SH.ADCx_IN15.0=ADC2_IN15,IN15
SH.ADCx_IN15.ConfNb=1 SH.ADCx_IN15.ConfNb=1
SH.ADCx_IN8.0=ADC1_IN8,IN8 SH.ADCx_IN8.0=ADC2_IN8,IN8
SH.ADCx_IN8.ConfNb=1 SH.ADCx_IN8.ConfNb=1
SH.ADCx_IN9.0=ADC1_IN9,IN9 SH.ADCx_IN9.0=ADC1_IN9
SH.ADCx_IN9.ConfNb=1 SH.ADCx_IN9.1=ADC2_IN9,IN9
SH.ADCx_IN9.ConfNb=2
SH.GPXTI0.0=GPIO_EXTI0 SH.GPXTI0.0=GPIO_EXTI0
SH.GPXTI0.ConfNb=1 SH.GPXTI0.ConfNb=1
SH.GPXTI1.0=GPIO_EXTI1 SH.GPXTI1.0=GPIO_EXTI1
@ -789,8 +822,6 @@ SH.GPXTI3.0=GPIO_EXTI3
SH.GPXTI3.ConfNb=1 SH.GPXTI3.ConfNb=1
SH.GPXTI7.0=GPIO_EXTI7 SH.GPXTI7.0=GPIO_EXTI7
SH.GPXTI7.ConfNb=1 SH.GPXTI7.ConfNb=1
SH.S_TIM4_CH3.0=TIM4_CH3,PWM Generation3 CH3
SH.S_TIM4_CH3.ConfNb=1
SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
SPI2.CalculateBaudRate=2.625 MBits/s SPI2.CalculateBaudRate=2.625 MBits/s
SPI2.Direction=SPI_DIRECTION_2LINES SPI2.Direction=SPI_DIRECTION_2LINES
@ -801,9 +832,7 @@ TIM3.IPParameters=Prescaler,Period,TIM_MasterOutputTrigger
TIM3.Period=199 TIM3.Period=199
TIM3.Prescaler=419 TIM3.Prescaler=419
TIM3.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM3.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
TIM4.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 TIM4.IPParameters=Prescaler,Period,TIM_MasterOutputTrigger
TIM4.IPParameters=Prescaler,Period,TIM_MasterOutputTrigger,Channel-PWM Generation3 CH3,OCPolarity_3
TIM4.OCPolarity_3=TIM_OCPOLARITY_LOW
TIM4.Period=500 TIM4.Period=500
TIM4.Prescaler=64-1 TIM4.Prescaler=64-1
TIM4.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE TIM4.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
@ -826,6 +855,12 @@ TIM8.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
USB_OTG_FS.IPParameters=VirtualMode,Sof_enable USB_OTG_FS.IPParameters=VirtualMode,Sof_enable
USB_OTG_FS.Sof_enable=ENABLE USB_OTG_FS.Sof_enable=ENABLE
USB_OTG_FS.VirtualMode=Device_Only USB_OTG_FS.VirtualMode=Device_Only
VP_ADC1_TempSens_Input.Mode=IN-TempSens
VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input
VP_ADC1_Vbat_Input.Mode=IN-Vbat
VP_ADC1_Vbat_Input.Signal=ADC1_Vbat_Input
VP_ADC1_Vref_Input.Mode=IN-Vrefint
VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Mode=SysTick