kopia lustrzana https://github.com/OpenRTX/OpenRTX
Boot code for STM32F401xC MCUs
Silvano Seva
rodzic
323566040a
commit
c35604aee8
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@ -232,6 +232,15 @@ stm32f4xx_inc = ['platform/mcu/CMSIS/Include',
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'platform/mcu/STM32F4xx/drivers',
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'platform/mcu/STM32F4xx/drivers/usb']
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##
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## STM32F401
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##
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stm32f401_src = stm32f4xx_src + ['platform/mcu/STM32F4xx/boot/startup_f401.cpp',
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'platform/mcu/STM32F4xx/boot/bsp_f401.cpp']
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stm32f401_inc = stm32f4xx_inc
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stm32f401_def = {'STM32F401xx': '', 'HSE_VALUE':'8000000', 'SYSCLK_FREQ_84MHz':''}
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##
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## STM32F405
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##
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Plik diff jest za duży
Load Diff
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@ -150,6 +150,14 @@ uint32_t SystemCoreClock = 180000000;
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uint32_t SystemCoreClock = 168000000;
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#elif defined(SYSCLK_FREQ_84MHz)
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#define PLL_N 336
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#define PLL_P 4
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#define PLL_Q 7
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uint32_t SystemCoreClock = 84000000;
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#else
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#error System clock frequency not supported
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#endif
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@ -333,11 +341,13 @@ static void SetSysClock(void)
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/* HCLK = SYSCLK / 1 */
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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/* PCLK2 = HCLK / 2 */
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RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
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/* PCLK1 = HCLK / 4 */
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
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#if defined(SYSCLK_FREQ_84MHz)
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; /* APB1 = SYSCLK/2 */
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RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; /* APB2 = SYSCLK */
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#else
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RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; /* APB1 = SYSCLK/4 */
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RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; /* APB2 = SYSCLK/2 */
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#endif
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/* Configure the main PLL */
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RCC->PLLCFGR = (PLL_Q << 24) /* PLL divider for USB clock */
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@ -0,0 +1,75 @@
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/***************************************************************************
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* Copyright (C) 2023 by Silvano Seva IU2KWO, *
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* Federico Terraneo *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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/***********************************************************************
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* bsp.cpp Part of the Miosix Embedded OS.
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* Board support package, this file initializes hardware.
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************************************************************************/
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#include <interfaces/delays.h>
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#include <interfaces/bsp.h>
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#include <kernel/kernel.h>
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#include <kernel/sync.h>
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#include <stm32f4xx.h>
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#include "../drivers/usb_vcom.h"
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namespace miosix
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{
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//
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// Initialization
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//
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void IRQbspInit()
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{
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN
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| RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN
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| RCC_AHB1ENR_GPIOHEN;
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RCC_SYNC();
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GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS
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GPIOB->OSPEEDR=0xaaaaaaaa;
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GPIOC->OSPEEDR=0xaaaaaaaa;
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GPIOD->OSPEEDR=0xaaaaaaaa;
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GPIOH->OSPEEDR=0xaaaaaaaa;
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// Configure SysTick
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SysTick->LOAD = SystemCoreClock / miosix::TICK_FREQ;
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}
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void bspInit2()
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{
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vcom_init();
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}
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//
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// Shutdown and reboot
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//
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void shutdown()
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{
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reboot();
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}
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void reboot()
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{
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disableInterrupts();
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miosix_private::IRQsystemReboot();
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}
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} //namespace miosix
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@ -0,0 +1,347 @@
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/***************************************************************************
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* Copyright (C) 2023 by Silvano Seva IU2KWO, *
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* Federico Terraneo *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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/*
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* startup.cpp
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* STM32 C++ startup.
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* NOTE: for stm32f4 devices ONLY.
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* Supports interrupt handlers in C++ without extern "C"
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* Developed by Terraneo Federico, based on ST startup code.
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* Additionally modified to boot Miosix.
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*/
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#include "interfaces/arch_registers.h"
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#include "kernel/stage_2_boot.h"
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#include "core/interrupts.h" //For the unexpected interrupt call
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#include <string.h>
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/**
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* Called by Reset_Handler, performs initialization and calls main.
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* Never returns.
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*/
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void program_startup() __attribute__((noreturn));
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void program_startup()
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{
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//Cortex M3 core appears to get out of reset with interrupts already enabled
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__disable_irq();
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//SystemInit() is called *before* initializing .data and zeroing .bss
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//Despite all startup files provided by ST do the opposite, there are three
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//good reasons to do so:
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//First, the CMSIS specifications say that SystemInit() must not access
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//global variables, so it is actually possible to call it before
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//Second, when running Miosix with the xram linker scripts .data and .bss
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//are placed in the external RAM, so we *must* call SystemInit(), which
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//enables xram, before touching .data and .bss
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//Third, this is a performance improvement since the loops that initialize
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//.data and zeros .bss now run with the CPU at full speed instead of 8MHz
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SystemInit();
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//These are defined in the linker script
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extern unsigned char _etext asm("_etext");
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extern unsigned char _data asm("_data");
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extern unsigned char _edata asm("_edata");
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extern unsigned char _bss_start asm("_bss_start");
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extern unsigned char _bss_end asm("_bss_end");
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//Initialize .data section, clear .bss section
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unsigned char *etext=&_etext;
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unsigned char *data=&_data;
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unsigned char *edata=&_edata;
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unsigned char *bss_start=&_bss_start;
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unsigned char *bss_end=&_bss_end;
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memcpy(data, etext, edata-data);
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memset(bss_start, 0, bss_end-bss_start);
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//Move on to stage 2
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_init();
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//If main returns, reboot
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NVIC_SystemReset();
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for(;;) ;
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}
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/**
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* Reset handler, called by hardware immediately after reset
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*/
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void Reset_Handler() __attribute__((__interrupt__, noreturn));
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void Reset_Handler()
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{
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/*
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* Initialize process stack and switch to it.
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* This is required for booting Miosix, a small portion of the top of the
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* heap area will be used as stack until the first thread starts. After,
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* this stack will be abandoned and the process stack will point to the
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* current thread's stack.
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*/
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asm volatile("ldr r0, =_heap_end \n\t"
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"msr psp, r0 \n\t"
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"movw r0, #2 \n\n" //Privileged, process stack
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"msr control, r0 \n\t"
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"isb \n\t":::"r0");
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program_startup();
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}
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/**
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* All unused interrupts call this function.
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*/
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extern "C" void Default_Handler()
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{
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unexpectedInterrupt();
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}
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//System handlers
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void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not
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void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are
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void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
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void /*__attribute__((weak))*/ MemManage_Handler();
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void /*__attribute__((weak))*/ BusFault_Handler();
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void /*__attribute__((weak))*/ UsageFault_Handler();
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void /*__attribute__((weak))*/ SVC_Handler();
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void /*__attribute__((weak))*/ DebugMon_Handler();
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void /*__attribute__((weak))*/ PendSV_Handler();
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void /*__attribute__((weak))*/ SysTick_Handler();
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//Interrupt handlers
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void __attribute__((weak)) WWDG_IRQHandler();
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void __attribute__((weak)) PVD_IRQHandler();
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void __attribute__((weak)) TAMP_STAMP_IRQHandler();
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void __attribute__((weak)) RTC_WKUP_IRQHandler();
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void __attribute__((weak)) FLASH_IRQHandler();
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void __attribute__((weak)) RCC_IRQHandler();
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void __attribute__((weak)) EXTI0_IRQHandler();
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void __attribute__((weak)) EXTI1_IRQHandler();
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void __attribute__((weak)) EXTI2_IRQHandler();
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void __attribute__((weak)) EXTI3_IRQHandler();
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void __attribute__((weak)) EXTI4_IRQHandler();
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void __attribute__((weak)) DMA1_Stream0_IRQHandler();
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void __attribute__((weak)) DMA1_Stream1_IRQHandler();
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void __attribute__((weak)) DMA1_Stream2_IRQHandler();
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void __attribute__((weak)) DMA1_Stream3_IRQHandler();
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void __attribute__((weak)) DMA1_Stream4_IRQHandler();
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void __attribute__((weak)) DMA1_Stream5_IRQHandler();
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void __attribute__((weak)) DMA1_Stream6_IRQHandler();
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void __attribute__((weak)) ADC_IRQHandler();
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void __attribute__((weak)) EXTI9_5_IRQHandler();
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void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler();
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void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler();
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void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler();
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void __attribute__((weak)) TIM1_CC_IRQHandler();
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void __attribute__((weak)) TIM2_IRQHandler();
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void __attribute__((weak)) TIM3_IRQHandler();
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void __attribute__((weak)) TIM4_IRQHandler();
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void __attribute__((weak)) I2C1_EV_IRQHandler();
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void __attribute__((weak)) I2C1_ER_IRQHandler();
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void __attribute__((weak)) I2C2_EV_IRQHandler();
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void __attribute__((weak)) I2C2_ER_IRQHandler();
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void __attribute__((weak)) SPI1_IRQHandler();
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void __attribute__((weak)) SPI2_IRQHandler();
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void __attribute__((weak)) USART1_IRQHandler();
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void __attribute__((weak)) USART2_IRQHandler();
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void __attribute__((weak)) EXTI15_10_IRQHandler();
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void __attribute__((weak)) RTC_Alarm_IRQHandler();
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void __attribute__((weak)) OTG_FS_WKUP_IRQHandler();
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void __attribute__((weak)) DMA1_Stream7_IRQHandler();
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void __attribute__((weak)) SDIO_IRQHandler();
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void __attribute__((weak)) TIM5_IRQHandler();
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void __attribute__((weak)) SPI3_IRQHandler();
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void __attribute__((weak)) DMA2_Stream0_IRQHandler();
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void __attribute__((weak)) DMA2_Stream1_IRQHandler();
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void __attribute__((weak)) DMA2_Stream2_IRQHandler();
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void __attribute__((weak)) DMA2_Stream3_IRQHandler();
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void __attribute__((weak)) DMA2_Stream4_IRQHandler();
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void __attribute__((weak)) OTG_FS_IRQHandler();
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void __attribute__((weak)) DMA2_Stream5_IRQHandler();
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void __attribute__((weak)) DMA2_Stream6_IRQHandler();
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void __attribute__((weak)) DMA2_Stream7_IRQHandler();
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void __attribute__((weak)) USART6_IRQHandler();
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void __attribute__((weak)) I2C3_EV_IRQHandler();
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void __attribute__((weak)) I2C3_ER_IRQHandler();
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void __attribute__((weak)) FPU_IRQHandler();
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void __attribute__((weak)) SPI4_IRQHandler();
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//Stack top, defined in the linker script
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extern char _main_stack_top asm("_main_stack_top");
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//Interrupt vectors, must be placed @ address 0x00000000
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//The extern declaration is required otherwise g++ optimizes it out
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extern void (* const __Vectors[])();
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void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
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{
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reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
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Reset_Handler, /* Reset Handler */
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NMI_Handler, /* NMI Handler */
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HardFault_Handler, /* Hard Fault Handler */
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MemManage_Handler, /* MPU Fault Handler */
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BusFault_Handler, /* Bus Fault Handler */
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UsageFault_Handler, /* Usage Fault Handler */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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SVC_Handler, /* SVCall Handler */
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DebugMon_Handler, /* Debug Monitor Handler */
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0, /* Reserved */
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PendSV_Handler, /* PendSV Handler */
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SysTick_Handler, /* SysTick Handler */
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/* External Interrupts */
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WWDG_IRQHandler,
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PVD_IRQHandler,
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TAMP_STAMP_IRQHandler,
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RTC_WKUP_IRQHandler,
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FLASH_IRQHandler,
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RCC_IRQHandler,
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EXTI0_IRQHandler,
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EXTI1_IRQHandler,
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EXTI2_IRQHandler,
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EXTI3_IRQHandler,
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EXTI4_IRQHandler,
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DMA1_Stream0_IRQHandler,
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DMA1_Stream1_IRQHandler,
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DMA1_Stream2_IRQHandler,
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DMA1_Stream3_IRQHandler,
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DMA1_Stream4_IRQHandler,
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DMA1_Stream5_IRQHandler,
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DMA1_Stream6_IRQHandler,
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ADC_IRQHandler,
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0,
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0,
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0,
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0,
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EXTI9_5_IRQHandler,
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TIM1_BRK_TIM9_IRQHandler,
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TIM1_UP_TIM10_IRQHandler,
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TIM1_TRG_COM_TIM11_IRQHandler,
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TIM1_CC_IRQHandler,
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TIM2_IRQHandler,
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TIM3_IRQHandler,
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TIM4_IRQHandler,
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I2C1_EV_IRQHandler,
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I2C1_ER_IRQHandler,
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I2C2_EV_IRQHandler,
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I2C2_ER_IRQHandler,
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SPI1_IRQHandler,
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SPI2_IRQHandler,
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USART1_IRQHandler,
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USART2_IRQHandler,
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0,
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EXTI15_10_IRQHandler,
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RTC_Alarm_IRQHandler,
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OTG_FS_WKUP_IRQHandler,
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0,
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0,
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0,
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0,
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DMA1_Stream7_IRQHandler,
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0,
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SDIO_IRQHandler,
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TIM5_IRQHandler,
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SPI3_IRQHandler,
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0,
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0,
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0,
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0,
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DMA2_Stream0_IRQHandler,
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DMA2_Stream1_IRQHandler,
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DMA2_Stream2_IRQHandler,
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DMA2_Stream3_IRQHandler,
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DMA2_Stream4_IRQHandler,
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0,
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0,
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0,
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0,
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0,
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0,
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OTG_FS_IRQHandler,
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DMA2_Stream5_IRQHandler,
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DMA2_Stream6_IRQHandler,
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DMA2_Stream7_IRQHandler,
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USART6_IRQHandler,
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I2C3_EV_IRQHandler,
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I2C3_ER_IRQHandler,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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FPU_IRQHandler,
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0,
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0,
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SPI4_IRQHandler
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};
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#pragma weak WWDG_IRQHandler = Default_Handler
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#pragma weak PVD_IRQHandler = Default_Handler
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#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
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#pragma weak RTC_WKUP_IRQHandler = Default_Handler
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#pragma weak FLASH_IRQHandler = Default_Handler
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#pragma weak RCC_IRQHandler = Default_Handler
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#pragma weak EXTI0_IRQHandler = Default_Handler
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#pragma weak EXTI1_IRQHandler = Default_Handler
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#pragma weak EXTI2_IRQHandler = Default_Handler
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#pragma weak EXTI3_IRQHandler = Default_Handler
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#pragma weak EXTI4_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
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#pragma weak ADC_IRQHandler = Default_Handler
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#pragma weak EXTI9_5_IRQHandler = Default_Handler
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#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
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#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
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#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
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#pragma weak TIM1_CC_IRQHandler = Default_Handler
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#pragma weak TIM2_IRQHandler = Default_Handler
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#pragma weak TIM3_IRQHandler = Default_Handler
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#pragma weak TIM4_IRQHandler = Default_Handler
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#pragma weak I2C1_EV_IRQHandler = Default_Handler
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#pragma weak I2C1_ER_IRQHandler = Default_Handler
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#pragma weak I2C2_EV_IRQHandler = Default_Handler
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#pragma weak I2C2_ER_IRQHandler = Default_Handler
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||||
#pragma weak SPI1_IRQHandler = Default_Handler
|
||||
#pragma weak SPI2_IRQHandler = Default_Handler
|
||||
#pragma weak USART1_IRQHandler = Default_Handler
|
||||
#pragma weak USART2_IRQHandler = Default_Handler
|
||||
#pragma weak EXTI15_10_IRQHandler = Default_Handler
|
||||
#pragma weak RTC_Alarm_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
|
||||
#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
|
||||
#pragma weak SDIO_IRQHandler = Default_Handler
|
||||
#pragma weak TIM5_IRQHandler = Default_Handler
|
||||
#pragma weak SPI3_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
|
||||
#pragma weak OTG_FS_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
|
||||
#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
|
||||
#pragma weak USART6_IRQHandler = Default_Handler
|
||||
#pragma weak I2C3_EV_IRQHandler = Default_Handler
|
||||
#pragma weak I2C3_ER_IRQHandler = Default_Handler
|
||||
#pragma weak FPU_IRQHandler = Default_Handler
|
||||
#pragma weak SPI4_IRQHandler = Default_Handler
|
||||
|
|
@ -43,6 +43,14 @@ void delayUs(unsigned int useconds)
|
|||
" itt lo \n"
|
||||
" addlo r1, r1, #1 \n"
|
||||
" blo ___loop_u \n"::"r"(useconds):"r1","r2");
|
||||
#elif defined(SYSCLK_FREQ_84MHz)
|
||||
asm volatile(" mov r1, #21 \n"
|
||||
" mul r2, %0, r1 \n"
|
||||
" mov r1, #0 \n"
|
||||
"___loop_u: cmp r1, r2 \n"
|
||||
" itt lo \n"
|
||||
" addlo r1, r1, #1 \n"
|
||||
" blo ___loop_u \n"::"r"(useconds):"r1","r2");
|
||||
#else
|
||||
#error delayUs() is not calibrated for this frequency
|
||||
#endif
|
||||
|
|
@ -54,6 +62,8 @@ void delayMs(unsigned int mseconds)
|
|||
register const unsigned int count=45000;
|
||||
#elif defined(SYSCLK_FREQ_168MHz)
|
||||
register const unsigned int count=42000;
|
||||
#elif defined(SYSCLK_FREQ_84MHz)
|
||||
register const unsigned int count=21000;
|
||||
#else
|
||||
#error delayMs() is not calibrated for this frequency
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,161 @@
|
|||
/*
|
||||
* C++ enabled linker script for stm32 (256K FLASH, 64K RAM)
|
||||
* Developed by TFT: Terraneo Federico Technologies
|
||||
* Optimized for use with the Miosix kernel
|
||||
*/
|
||||
|
||||
/*
|
||||
* The main stack is used for interrupt handling by the kernel.
|
||||
*
|
||||
* *** Readme ***
|
||||
* This linker script places the main stack (used by the kernel for interrupts)
|
||||
* at the bottom of the ram, instead of the top. This is done for two reasons:
|
||||
*
|
||||
* - as an optimization for microcontrollers with little ram memory. In fact
|
||||
* the implementation of malloc from newlib requests memory to the OS in 4KB
|
||||
* block (except the first block that can be smaller). This is probably done
|
||||
* for compatibility with OSes with an MMU and paged memory. To see why this
|
||||
* is bad, consider a microcontroller with 8KB of ram: when malloc finishes
|
||||
* up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
|
||||
* fail because the top part of the ram is used by the main stack. As a
|
||||
* result, the top part of the memory will not be used by malloc, even if
|
||||
* available (and it is nearly *half* the ram on an 8KB mcu). By placing the
|
||||
* main stack at the bottom of the ram, the upper 4KB block will be entirely
|
||||
* free and available as heap space.
|
||||
*
|
||||
* - In case of main stack overflow the cpu will fault because access to memory
|
||||
* before the beginning of the ram faults. Instead with the default stack
|
||||
* placement the main stack will silently collide with the heap.
|
||||
* Note: if increasing the main stack size also increase the ORIGIN value in
|
||||
* the MEMORY definitions below accordingly.
|
||||
*/
|
||||
_main_stack_size = 0x00000200; /* main stack = 512Bytes */
|
||||
_main_stack_top = 0x20000000 + _main_stack_size;
|
||||
ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
|
||||
|
||||
_heap_end = 0x20010000; /* end of available ram */
|
||||
|
||||
/* identify the Entry Point */
|
||||
ENTRY(_Z13Reset_Handlerv)
|
||||
|
||||
/* specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
/*
|
||||
* Note, the ram starts at 0x20000000 but it is necessary to add the size of
|
||||
* the main stack, so it is 0x20000200.
|
||||
*/
|
||||
ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200
|
||||
}
|
||||
|
||||
/* now define the output sections */
|
||||
SECTIONS
|
||||
{
|
||||
. = 0;
|
||||
|
||||
/* .text section: code goes to flash */
|
||||
.text :
|
||||
{
|
||||
/* Startup code must go at address 0 */
|
||||
KEEP(*(.isr_vector))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
/* these sections for thumb interwork? */
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
/* these sections for C++? */
|
||||
*(.gcc_except_table)
|
||||
*(.gcc_except_table.*)
|
||||
*(.ARM.extab*)
|
||||
*(.gnu.linkonce.armextab.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* .rodata: constant data */
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* C++ Static constructors/destructors (eabi) */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__miosix_init_array_start = .;
|
||||
KEEP (*(SORT(.miosix_init_array.*)))
|
||||
KEEP (*(.miosix_init_array))
|
||||
__miosix_init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
/* C++ Static constructors/destructors (elf) */
|
||||
. = ALIGN(4);
|
||||
_ctor_start = .;
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
_ctor_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
} > flash
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > flash
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section: global variables go to ram, but also store a copy to
|
||||
flash to initialize them */
|
||||
.data : ALIGN(8)
|
||||
{
|
||||
_data = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
_edata = .;
|
||||
} > ram AT > flash
|
||||
_etext = LOADADDR(.data);
|
||||
|
||||
/* .bss section: uninitialized global variables go to ram */
|
||||
_bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
. = ALIGN(8);
|
||||
} > ram
|
||||
_bss_end = .;
|
||||
|
||||
_end = .;
|
||||
PROVIDE(end = .);
|
||||
}
|
||||
Ładowanie…
Reference in New Issue