kopia lustrzana https://github.com/OpenRTX/OpenRTX
348 wiersze
13 KiB
C++
348 wiersze
13 KiB
C++
/***************************************************************************
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* Copyright (C) 2023 by Silvano Seva IU2KWO, *
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* Federico Terraneo *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 3 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, see <http://www.gnu.org/licenses/> *
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***************************************************************************/
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/*
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* startup.cpp
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* STM32 C++ startup.
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* NOTE: for stm32f4 devices ONLY.
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* Supports interrupt handlers in C++ without extern "C"
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* Developed by Terraneo Federico, based on ST startup code.
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* Additionally modified to boot Miosix.
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*/
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#include "interfaces/arch_registers.h"
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#include "kernel/stage_2_boot.h"
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#include "core/interrupts.h" //For the unexpected interrupt call
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#include <string.h>
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/**
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* Called by Reset_Handler, performs initialization and calls main.
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* Never returns.
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*/
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void program_startup() __attribute__((noreturn));
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void program_startup()
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{
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//Cortex M3 core appears to get out of reset with interrupts already enabled
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__disable_irq();
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//SystemInit() is called *before* initializing .data and zeroing .bss
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//Despite all startup files provided by ST do the opposite, there are three
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//good reasons to do so:
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//First, the CMSIS specifications say that SystemInit() must not access
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//global variables, so it is actually possible to call it before
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//Second, when running Miosix with the xram linker scripts .data and .bss
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//are placed in the external RAM, so we *must* call SystemInit(), which
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//enables xram, before touching .data and .bss
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//Third, this is a performance improvement since the loops that initialize
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//.data and zeros .bss now run with the CPU at full speed instead of 8MHz
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SystemInit();
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//These are defined in the linker script
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extern unsigned char _etext asm("_etext");
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extern unsigned char _data asm("_data");
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extern unsigned char _edata asm("_edata");
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extern unsigned char _bss_start asm("_bss_start");
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extern unsigned char _bss_end asm("_bss_end");
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//Initialize .data section, clear .bss section
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unsigned char *etext=&_etext;
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unsigned char *data=&_data;
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unsigned char *edata=&_edata;
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unsigned char *bss_start=&_bss_start;
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unsigned char *bss_end=&_bss_end;
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memcpy(data, etext, edata-data);
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memset(bss_start, 0, bss_end-bss_start);
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//Move on to stage 2
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_init();
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//If main returns, reboot
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NVIC_SystemReset();
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for(;;) ;
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}
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/**
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* Reset handler, called by hardware immediately after reset
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*/
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void Reset_Handler() __attribute__((__interrupt__, noreturn));
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void Reset_Handler()
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{
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/*
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* Initialize process stack and switch to it.
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* This is required for booting Miosix, a small portion of the top of the
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* heap area will be used as stack until the first thread starts. After,
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* this stack will be abandoned and the process stack will point to the
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* current thread's stack.
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*/
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asm volatile("ldr r0, =_heap_end \n\t"
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"msr psp, r0 \n\t"
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"movw r0, #2 \n\n" //Privileged, process stack
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"msr control, r0 \n\t"
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"isb \n\t":::"r0");
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program_startup();
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}
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/**
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* All unused interrupts call this function.
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*/
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extern "C" void Default_Handler()
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{
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unexpectedInterrupt();
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}
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//System handlers
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void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not
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void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are
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void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
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void /*__attribute__((weak))*/ MemManage_Handler();
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void /*__attribute__((weak))*/ BusFault_Handler();
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void /*__attribute__((weak))*/ UsageFault_Handler();
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void /*__attribute__((weak))*/ SVC_Handler();
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void /*__attribute__((weak))*/ DebugMon_Handler();
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void /*__attribute__((weak))*/ PendSV_Handler();
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void /*__attribute__((weak))*/ SysTick_Handler();
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//Interrupt handlers
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void __attribute__((weak)) WWDG_IRQHandler();
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void __attribute__((weak)) PVD_IRQHandler();
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void __attribute__((weak)) TAMP_STAMP_IRQHandler();
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void __attribute__((weak)) RTC_WKUP_IRQHandler();
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void __attribute__((weak)) FLASH_IRQHandler();
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void __attribute__((weak)) RCC_IRQHandler();
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void __attribute__((weak)) EXTI0_IRQHandler();
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void __attribute__((weak)) EXTI1_IRQHandler();
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void __attribute__((weak)) EXTI2_IRQHandler();
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void __attribute__((weak)) EXTI3_IRQHandler();
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void __attribute__((weak)) EXTI4_IRQHandler();
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void __attribute__((weak)) DMA1_Stream0_IRQHandler();
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void __attribute__((weak)) DMA1_Stream1_IRQHandler();
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void __attribute__((weak)) DMA1_Stream2_IRQHandler();
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void __attribute__((weak)) DMA1_Stream3_IRQHandler();
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void __attribute__((weak)) DMA1_Stream4_IRQHandler();
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void __attribute__((weak)) DMA1_Stream5_IRQHandler();
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void __attribute__((weak)) DMA1_Stream6_IRQHandler();
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void __attribute__((weak)) ADC_IRQHandler();
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void __attribute__((weak)) EXTI9_5_IRQHandler();
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void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler();
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void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler();
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void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler();
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void __attribute__((weak)) TIM1_CC_IRQHandler();
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void __attribute__((weak)) TIM2_IRQHandler();
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void __attribute__((weak)) TIM3_IRQHandler();
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void __attribute__((weak)) TIM4_IRQHandler();
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void __attribute__((weak)) I2C1_EV_IRQHandler();
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void __attribute__((weak)) I2C1_ER_IRQHandler();
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void __attribute__((weak)) I2C2_EV_IRQHandler();
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void __attribute__((weak)) I2C2_ER_IRQHandler();
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void __attribute__((weak)) SPI1_IRQHandler();
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void __attribute__((weak)) SPI2_IRQHandler();
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void __attribute__((weak)) USART1_IRQHandler();
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void __attribute__((weak)) USART2_IRQHandler();
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void __attribute__((weak)) EXTI15_10_IRQHandler();
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void __attribute__((weak)) RTC_Alarm_IRQHandler();
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void __attribute__((weak)) OTG_FS_WKUP_IRQHandler();
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void __attribute__((weak)) DMA1_Stream7_IRQHandler();
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void __attribute__((weak)) SDIO_IRQHandler();
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void __attribute__((weak)) TIM5_IRQHandler();
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void __attribute__((weak)) SPI3_IRQHandler();
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void __attribute__((weak)) DMA2_Stream0_IRQHandler();
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void __attribute__((weak)) DMA2_Stream1_IRQHandler();
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void __attribute__((weak)) DMA2_Stream2_IRQHandler();
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void __attribute__((weak)) DMA2_Stream3_IRQHandler();
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void __attribute__((weak)) DMA2_Stream4_IRQHandler();
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void __attribute__((weak)) OTG_FS_IRQHandler();
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void __attribute__((weak)) DMA2_Stream5_IRQHandler();
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void __attribute__((weak)) DMA2_Stream6_IRQHandler();
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void __attribute__((weak)) DMA2_Stream7_IRQHandler();
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void __attribute__((weak)) USART6_IRQHandler();
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void __attribute__((weak)) I2C3_EV_IRQHandler();
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void __attribute__((weak)) I2C3_ER_IRQHandler();
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void __attribute__((weak)) FPU_IRQHandler();
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void __attribute__((weak)) SPI4_IRQHandler();
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//Stack top, defined in the linker script
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extern char _main_stack_top asm("_main_stack_top");
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//Interrupt vectors, must be placed @ address 0x00000000
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//The extern declaration is required otherwise g++ optimizes it out
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extern void (* const __Vectors[])();
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void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
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{
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reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
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Reset_Handler, /* Reset Handler */
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NMI_Handler, /* NMI Handler */
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HardFault_Handler, /* Hard Fault Handler */
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MemManage_Handler, /* MPU Fault Handler */
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BusFault_Handler, /* Bus Fault Handler */
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UsageFault_Handler, /* Usage Fault Handler */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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SVC_Handler, /* SVCall Handler */
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DebugMon_Handler, /* Debug Monitor Handler */
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0, /* Reserved */
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PendSV_Handler, /* PendSV Handler */
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SysTick_Handler, /* SysTick Handler */
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/* External Interrupts */
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WWDG_IRQHandler,
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PVD_IRQHandler,
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TAMP_STAMP_IRQHandler,
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RTC_WKUP_IRQHandler,
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FLASH_IRQHandler,
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RCC_IRQHandler,
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EXTI0_IRQHandler,
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EXTI1_IRQHandler,
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EXTI2_IRQHandler,
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EXTI3_IRQHandler,
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EXTI4_IRQHandler,
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DMA1_Stream0_IRQHandler,
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DMA1_Stream1_IRQHandler,
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DMA1_Stream2_IRQHandler,
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DMA1_Stream3_IRQHandler,
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DMA1_Stream4_IRQHandler,
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DMA1_Stream5_IRQHandler,
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DMA1_Stream6_IRQHandler,
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ADC_IRQHandler,
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0,
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0,
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0,
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0,
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EXTI9_5_IRQHandler,
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TIM1_BRK_TIM9_IRQHandler,
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TIM1_UP_TIM10_IRQHandler,
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TIM1_TRG_COM_TIM11_IRQHandler,
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TIM1_CC_IRQHandler,
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TIM2_IRQHandler,
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TIM3_IRQHandler,
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TIM4_IRQHandler,
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I2C1_EV_IRQHandler,
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I2C1_ER_IRQHandler,
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I2C2_EV_IRQHandler,
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I2C2_ER_IRQHandler,
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SPI1_IRQHandler,
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SPI2_IRQHandler,
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USART1_IRQHandler,
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USART2_IRQHandler,
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0,
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EXTI15_10_IRQHandler,
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RTC_Alarm_IRQHandler,
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OTG_FS_WKUP_IRQHandler,
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0,
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0,
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0,
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0,
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DMA1_Stream7_IRQHandler,
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0,
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SDIO_IRQHandler,
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TIM5_IRQHandler,
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SPI3_IRQHandler,
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0,
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0,
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0,
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0,
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DMA2_Stream0_IRQHandler,
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DMA2_Stream1_IRQHandler,
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DMA2_Stream2_IRQHandler,
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DMA2_Stream3_IRQHandler,
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DMA2_Stream4_IRQHandler,
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0,
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0,
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0,
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0,
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0,
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0,
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OTG_FS_IRQHandler,
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DMA2_Stream5_IRQHandler,
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DMA2_Stream6_IRQHandler,
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DMA2_Stream7_IRQHandler,
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USART6_IRQHandler,
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I2C3_EV_IRQHandler,
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I2C3_ER_IRQHandler,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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FPU_IRQHandler,
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0,
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0,
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SPI4_IRQHandler
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};
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#pragma weak WWDG_IRQHandler = Default_Handler
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#pragma weak PVD_IRQHandler = Default_Handler
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#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
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#pragma weak RTC_WKUP_IRQHandler = Default_Handler
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#pragma weak FLASH_IRQHandler = Default_Handler
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#pragma weak RCC_IRQHandler = Default_Handler
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#pragma weak EXTI0_IRQHandler = Default_Handler
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#pragma weak EXTI1_IRQHandler = Default_Handler
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#pragma weak EXTI2_IRQHandler = Default_Handler
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#pragma weak EXTI3_IRQHandler = Default_Handler
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#pragma weak EXTI4_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
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#pragma weak ADC_IRQHandler = Default_Handler
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#pragma weak EXTI9_5_IRQHandler = Default_Handler
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#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
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#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
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#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
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#pragma weak TIM1_CC_IRQHandler = Default_Handler
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#pragma weak TIM2_IRQHandler = Default_Handler
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#pragma weak TIM3_IRQHandler = Default_Handler
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#pragma weak TIM4_IRQHandler = Default_Handler
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#pragma weak I2C1_EV_IRQHandler = Default_Handler
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#pragma weak I2C1_ER_IRQHandler = Default_Handler
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#pragma weak I2C2_EV_IRQHandler = Default_Handler
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#pragma weak I2C2_ER_IRQHandler = Default_Handler
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#pragma weak SPI1_IRQHandler = Default_Handler
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#pragma weak SPI2_IRQHandler = Default_Handler
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#pragma weak USART1_IRQHandler = Default_Handler
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#pragma weak USART2_IRQHandler = Default_Handler
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#pragma weak EXTI15_10_IRQHandler = Default_Handler
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#pragma weak RTC_Alarm_IRQHandler = Default_Handler
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#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
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#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
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#pragma weak SDIO_IRQHandler = Default_Handler
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#pragma weak TIM5_IRQHandler = Default_Handler
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#pragma weak SPI3_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
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#pragma weak OTG_FS_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
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#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
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#pragma weak USART6_IRQHandler = Default_Handler
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#pragma weak I2C3_EV_IRQHandler = Default_Handler
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#pragma weak I2C3_ER_IRQHandler = Default_Handler
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#pragma weak FPU_IRQHandler = Default_Handler
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#pragma weak SPI4_IRQHandler = Default_Handler
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