kopia lustrzana https://github.com/sq8vps/vp-digi
82 wiersze
2.7 KiB
C
82 wiersze
2.7 KiB
C
/*
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Copyright 2020-2023 Piotr Wilkon
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This file is part of VP-Digi.
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VP-Digi is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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VP-Digi is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file is kind of HAL for UART
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*/
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#ifndef DRIVERS_UART_LL_H_
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#define DRIVERS_UART_LL_H_
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#if defined(STM32F103xB) || defined(STM32F103x8)
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#include "stm32f1xx.h"
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#define UART_LL_ENABLE(port) {port->CR1 |= USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE | USART_CR1_UE | USART_CR1_IDLEIE;}
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#define UART_LL_DISABLE(port) {port->CR1 &= (~USART_CR1_RXNEIE) & (~USART_CR1_TE) & (~USART_CR1_RE) & (~USART_CR1_UE) & (~USART_CR1_IDLEIE);}
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#define UART_LL_CHECK_RX_NOT_EMPTY(port) (port->SR & USART_SR_RXNE)
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#define UART_LL_CLEAR_RX_NOT_EMPTY(port) {port->SR &= ~USART_SR_RXNE;}
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#define UART_LL_CHECK_TX_EMPTY(port) (port->SR & USART_SR_TXE)
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#define UART_LL_ENABLE_TX_EMPTY_INTERRUPT(port) {port->CR1 |= USART_CR1_TXEIE;}
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#define UART_LL_DISABLE_TX_EMPTY_INTERRUPT(port) {port->CR1 &= ~USART_CR1_TXEIE;}
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#define UART_LL_CHECK_ENABLED_TX_EMPTY_INTERRUPT(port) (port->CR1 & USART_CR1_TXEIE)
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#define UART_LL_CHECK_RX_IDLE(port) (port->SR & USART_SR_IDLE)
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#define UART_LL_GET_DATA(port) (port->DR)
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#define UART_LL_PUT_DATA(port, data) {port->DR = (data);}
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#define UART_LL_UART1_INTERUPT_HANDLER USART1_IRQHandler
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#define UART_LL_UART2_INTERUPT_HANDLER USART2_IRQHandler
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#define UART_LL_UART1_STRUCTURE USART1
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#define UART_LL_UART2_STRUCTURE USART2
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#define UART_LL_UART1_IRQ USART1_IRQn
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#define UART_LL_UART2_IRQ USART2_IRQn
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#define UART_LL_UART1_INITIALIZE_PERIPHERAL(baudrate) { \
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; \
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RCC->APB2ENR |= RCC_APB2ENR_USART1EN; \
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GPIOA->CRH |= GPIO_CRH_MODE9_1; \
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GPIOA->CRH &= ~GPIO_CRH_CNF9_0; \
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GPIOA->CRH |= GPIO_CRH_CNF9_1; \
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GPIOA->CRH |= GPIO_CRH_CNF10_0; \
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GPIOA->CRH &= ~GPIO_CRH_CNF10_1; \
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UART_LL_UART1_STRUCTURE->BRR = (SystemCoreClock / baudrate); \
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} \
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#define UART_LL_UART2_INITIALIZE_PERIPHERAL(baudrate) { \
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; \
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RCC->APB1ENR |= RCC_APB1ENR_USART2EN; \
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GPIOA->CRL |= GPIO_CRL_MODE2_1; \
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GPIOA->CRL &= ~GPIO_CRL_CNF2_0; \
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GPIOA->CRL |= GPIO_CRL_CNF2_1; \
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GPIOA->CRL |= GPIO_CRL_CNF3_0; \
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GPIOA->CRL &= ~GPIO_CRL_CNF3_1; \
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UART_LL_UART2_STRUCTURE->BRR = (SystemCoreClock / (baudrate * 2)); \
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} \
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#endif
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#endif /* INC_DRIVERS_UART_LL_H_ */
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