kopia lustrzana https://github.com/sq8vps/vp-digi
197 wiersze
6.3 KiB
C
197 wiersze
6.3 KiB
C
/*
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Copyright 2020-2023 Piotr Wilkon
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This file is part of VP-Digi.
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VP-Digi is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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VP-Digi is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with VP-Digi. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This file is kind of HAL for modem
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*/
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#ifndef DRIVERS_MODEM_LL_H_
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#define DRIVERS_MODEM_LL_H_
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#include <stdint.h>
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//Oversampling factor
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//This is a helper value, not a setting that can be changed without further code modification!
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#define MODEM_LL_OVERSAMPLING_FACTOR 4
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#if defined(STM32F103xB) || defined(STM32F103x8)
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#include "stm32f1xx.h"
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/**
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* TIM1 is used for pushing samples to DAC (R2R or PWM) (clocked at 18 MHz)
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* TIM3 is the baudrate generator for TX (clocked at 18 MHz)
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* TIM4 is the PWM generator with no software interrupt
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* TIM2 is the RX sampling timer with no software interrupt, but it directly calls DMA
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*/
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#define MODEM_LL_DMA_INTERRUPT_HANDLER DMA1_Channel2_IRQHandler
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#define MODEM_LL_DAC_INTERRUPT_HANDLER TIM1_UP_IRQHandler
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#define MODEM_LL_BAUDRATE_TIMER_INTERRUPT_HANDLER TIM3_IRQHandler
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#define MODEM_LL_DMA_IRQ DMA1_Channel2_IRQn
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#define MODEM_LL_DAC_IRQ TIM1_UP_IRQn
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#define MODEM_LL_BAUDRATE_TIMER_IRQ TIM3_IRQn
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#define MODEM_LL_DMA_TRANSFER_COMPLETE_FLAG (DMA1->ISR & DMA_ISR_TCIF2)
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#define MODEM_LL_DMA_CLEAR_TRANSFER_COMPLETE_FLAG() {DMA1->IFCR |= DMA_IFCR_CTCIF2;}
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#define MODEM_LL_BAUDRATE_TIMER_CLEAR_INTERRUPT_FLAG() {TIM3->SR &= ~TIM_SR_UIF;}
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#define MODEM_LL_BAUDRATE_TIMER_ENABLE() {TIM3->CR1 = TIM_CR1_CEN;}
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#define MODEM_LL_BAUDRATE_TIMER_DISABLE() {TIM3->CR1 &= ~TIM_CR1_CEN;}
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#define MODEM_LL_BAUDRATE_TIMER_SET_RELOAD_VALUE(val) {TIM3->ARR = (val);}
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#define MODEM_LL_DAC_TIMER_CLEAR_INTERRUPT_FLAG {TIM1->SR &= ~TIM_SR_UIF;}
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#define MODEM_LL_DAC_TIMER_SET_RELOAD_VALUE(val) {TIM1->ARR = (val);}
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#define MODEM_LL_DAC_TIMER_SET_CURRENT_VALUE(val) {TIM1->CNT = (val);}
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#define MODEM_LL_DAC_TIMER_ENABLE() {TIM1->CR1 |= TIM_CR1_CEN;}
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#define MODEM_LL_DAC_TIMER_DISABLE() {TIM1->CR1 &= ~TIM_CR1_CEN;}
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#define MODEM_LL_ADC_TIMER_ENABLE() {TIM2->CR1 |= TIM_CR1_CEN;}
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#define MODEM_LL_ADC_TIMER_DISABLE() {TIM2->CR1 &= ~TIM_CR1_CEN;}
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#define MODEM_LL_PWM_PUT_VALUE(value) {TIM4->CCR1 = (value);}
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#define MODEM_LL_R2R_PUT_VALUE(value) {GPIOB->ODR &= ~0xF000; \
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GPIOB->ODR |= ((uint32_t)(value) << 12); }\
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#define MODEM_LL_DCD_LED_ON() { \
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GPIOC->BSRR = GPIO_BSRR_BR13; \
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GPIOB->BSRR = GPIO_BSRR_BS5; \
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} \
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#define MODEM_LL_DCD_LED_OFF() { \
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GPIOC->BSRR = GPIO_BSRR_BS13; \
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GPIOB->BSRR = GPIO_BSRR_BR5; \
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} \
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#define MODEM_LL_PTT_ON() {GPIOB->BSRR = GPIO_BSRR_BS7;}
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#define MODEM_LL_PTT_OFF() {GPIOB->BSRR = GPIO_BSRR_BR7;}
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#define MODEM_LL_INITIALIZE_RCC() { \
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RCC->APB2ENR |= RCC_APB2ENR_IOPBEN; \
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RCC->APB2ENR |= RCC_APB2ENR_IOPCEN; \
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN; \
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; \
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; \
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RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; \
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RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; \
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RCC->AHBENR |= RCC_AHBENR_DMA1EN; \
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RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; \
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} \
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#define MODEM_LL_INITIALIZE_OUTPUTS() { \
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/* DCD LEDs: PC13 (cathode driven - built-in LED on Blue Pill) and PB5 (anode driven) */ \
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GPIOC->CRH |= GPIO_CRH_MODE13_1; \
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GPIOC->CRH &= ~GPIO_CRH_MODE13_0; \
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GPIOC->CRH &= ~GPIO_CRH_CNF13; \
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GPIOB->CRL |= GPIO_CRL_MODE5_1; \
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GPIOB->CRL &= ~GPIO_CRL_MODE5_0; \
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GPIOB->CRL &= ~GPIO_CRL_CNF5; \
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/* PTT: PB7 */ \
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GPIOB->CRL |= GPIO_CRL_MODE7_1; \
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GPIOB->CRL &= ~GPIO_CRL_MODE7_0; \
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GPIOB->CRL &= ~GPIO_CRL_CNF7; \
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/* R2R: 4 bits, PB12-PB15 */ \
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GPIOB->CRH &= ~0xFFFF0000; \
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GPIOB->CRH |= 0x22220000; \
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/* PWM output: PB6 */ \
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GPIOB->CRL |= GPIO_CRL_CNF6_1; \
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GPIOB->CRL |= GPIO_CRL_MODE6; \
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GPIOB->CRL &= ~GPIO_CRL_CNF6_0; \
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} \
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#define MODEM_LL_INITIALIZE_ADC() { \
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/* ADC input: PA0 */ \
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GPIOA->CRL &= ~GPIO_CRL_CNF0; \
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GPIOA->CRL &= ~GPIO_CRL_MODE0; \
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/*/6 prescaler */ \
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RCC->CFGR |= RCC_CFGR_ADCPRE_1; \
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RCC->CFGR &= ~RCC_CFGR_ADCPRE_0; \
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ADC1->CR2 |= ADC_CR2_CONT; \
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ADC1->CR2 |= ADC_CR2_EXTSEL; \
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ADC1->SQR1 &= ~ADC_SQR1_L; \
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/* 41.5 cycle sampling */ \
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ADC1->SMPR2 |= ADC_SMPR2_SMP0_2; \
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ADC1->SQR3 &= ~ADC_SQR3_SQ1; \
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ADC1->CR2 |= ADC_CR2_ADON; \
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/* calibrate */ \
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ADC1->CR2 |= ADC_CR2_RSTCAL; \
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while(ADC1->CR2 & ADC_CR2_RSTCAL) \
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; \
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ADC1->CR2 |= ADC_CR2_CAL; \
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while(ADC1->CR2 & ADC_CR2_CAL) \
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; \
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ADC1->CR2 |= ADC_CR2_EXTTRIG; \
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ADC1->CR2 |= ADC_CR2_SWSTART; \
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} \
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#define MODEM_LL_INITIALIZE_DMA(buffer) { \
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/* 16 bit memory region */ \
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DMA1_Channel2->CCR |= DMA_CCR_MSIZE_0; \
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DMA1_Channel2->CCR &= ~DMA_CCR_MSIZE_1; \
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DMA1_Channel2->CCR |= DMA_CCR_PSIZE_0; \
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DMA1_Channel2->CCR &= ~DMA_CCR_PSIZE_1; \
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/* enable memory pointer increment, circular mode and interrupt generation */ \
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DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_CIRC| DMA_CCR_TCIE; \
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DMA1_Channel2->CNDTR = MODEM_LL_OVERSAMPLING_FACTOR; \
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DMA1_Channel2->CPAR = (uintptr_t)&(ADC1->DR); \
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DMA1_Channel2->CMAR = (uintptr_t)buffer; \
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DMA1_Channel2->CCR |= DMA_CCR_EN; \
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} \
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#define MODEM_LL_ADC_TIMER_INITIALIZE() { \
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/* 72 / 9 = 8 MHz */ \
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TIM2->PSC = 8; \
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/* enable DMA call instead of standard interrupt */ \
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TIM2->DIER |= TIM_DIER_UDE; \
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} \
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#define MODEM_LL_DAC_TIMER_INITIALIZE() { \
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/* 72 / 4 = 18 MHz */ \
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TIM1->PSC = 3; \
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TIM1->DIER |= TIM_DIER_UIE; \
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} \
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#define MODEM_LL_BAUDRATE_TIMER_INITIALIZE() { \
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/* 72 / 4 = 18 MHz */ \
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TIM3->PSC = 3; \
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TIM3->DIER |= TIM_DIER_UIE; \
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} \
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#define MODEM_LL_PWM_INITIALIZE() { \
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/* 72 / 3 = 24 MHz to provide 8 bit resolution at around 100 kHz */ \
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TIM4->PSC = 2; \
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/* 24 MHz / 258 = 93 kHz */ \
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TIM4->ARR = 257; \
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TIM4->CCMR1 |= TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; \
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TIM4->CCER |= TIM_CCER_CC1E; \
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TIM4->CR1 |= TIM_CR1_CEN; \
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} \
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#define MODEM_LL_ADC_SET_SAMPLE_RATE(rate) {TIM2->ARR = (8000000 / (rate)) - 1;}
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#define MODEM_LL_DAC_TIMER_CALCULATE_STEP(frequency) ((18000000 / (frequency)) - 1)
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#define MODEM_LL_BAUDRATE_TIMER_CALCULATE_STEP(frequency) ((18000000 / (frequency)) - 1)
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#endif
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#endif /* DRIVERS_MODEM_LL_H_ */
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