kopia lustrzana https://github.com/threeme3/usdx
Minor changes. Added simplifications display_vfo, si5351.
guido
rodzic
bd4899aaac
commit
beac1235aa
262
QCX-SSB.ino
262
QCX-SSB.ino
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@ -29,7 +29,6 @@
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#define SDA 18 //PC4
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#define SCL 19 //PC5
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#include <inttypes.h>
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#include <avr/sleep.h>
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#include <avr/wdt.h>
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@ -83,6 +82,8 @@ public: // LCD1602 display in 4-bit mode, RS is pull-up and kept low when idle
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void createChar(uint8_t l, uint8_t glyph[]){ cmd(0x40 | ((l & 0x7) << 3)); for(int i = 0; i != 8; i++) write(glyph[i]); }
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};
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LCD lcd;
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//#include <LiquidCrystal.h>
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//LiquidCrystal lcd(LCD_RS, LCD_EN, LCD_D4, LCD_D5, LCD_D6, LCD_D7);
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volatile int8_t encoder_val = 0;
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volatile int8_t encoder_step = 0;
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@ -223,10 +224,138 @@ public:
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}
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};
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#define log2(n) (log(n) / log(2))
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// /*
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I2C i2c;
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class SI5351 {
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public:
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volatile int32_t _fout;
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volatile uint8_t _div; // note: uint8_t asserts fout > 3.5MHz with R_DIV=1
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volatile uint16_t _msa128min512;
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volatile uint32_t _msb128;
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volatile uint8_t pll_regs[8];
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#define BB0(x) ((uint8_t)(x)) // Bash byte x of int32_t
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#define BB1(x) ((uint8_t)((x)>>8))
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#define BB2(x) ((uint8_t)((x)>>16))
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#define FAST __attribute__((optimize("Ofast")))
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inline void FAST freq_calc_fast(int16_t df) // note: relies on cached variables: _msb128, _msa128min512, _div, _fout, fxtal
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{
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//#define _MSC 0x80000 //0x80000: 98% CPU load 0xFFFFF: 114% CPU load
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//uint32_t msb128 = _msb128 + ((int64_t)(_div * (int32_t)df) * _MSC * 128) / fxtal;
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//#define _MSC 0xFFFFF // Old algorithm 114% CPU load
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//register uint32_t xmsb = (_div * (_fout + (int32_t)df)) % fxtal; // xmsb = msb * fxtal/(128 * _MSC);
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//uint32_t msb128 = xmsb * 5*(32/32) - (xmsb/32); // msb128 = xmsb * 159/32, where 159/32 = 128 * 0xFFFFF / fxtal; fxtal=27e6
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#define _MSC (27004800/128) // 114% CPU load perfect alignment
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uint32_t msb128 = (_div * (_fout + (int32_t)df)) % fxtal;
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uint32_t msp1 = _msa128min512 + msb128 / _MSC; // = 128 * _msa + msb128 / _MSC - 512;
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uint32_t msp2 = msb128 % _MSC; // = msb128 - msb128/_MSC * _MSC;
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//pll_regs[0] = BB1(msc); // 3 regs are constant
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//pll_regs[1] = BB0(msc);
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//pll_regs[2] = BB2(msp1);
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pll_regs[3] = BB1(msp1);
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pll_regs[4] = BB0(msp1);
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pll_regs[5] = ((_MSC&0xF0000)>>(16-4))|BB2(msp2); // top nibble MUST be same as top nibble of _MSC !
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pll_regs[6] = BB1(msp2);
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pll_regs[7] = BB0(msp2);
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}
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#define SI5351_ADDR 0x60 // I2C address of Si5351 (typical)
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inline void SendPLLBRegisterBulk(){
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i2c.start();
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i2c.SendByte(SI5351_ADDR << 1);
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i2c.SendByte(26+1*8 + 3); // Write to PLLB
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i2c.SendByte(pll_regs[3]);
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i2c.SendByte(pll_regs[4]);
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i2c.SendByte(pll_regs[5]);
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i2c.SendByte(pll_regs[6]);
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i2c.SendByte(pll_regs[7]);
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i2c.stop();
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}
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void SendRegister(uint8_t reg, uint8_t* data, uint8_t n){
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i2c.start();
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i2c.SendByte(SI5351_ADDR << 1);
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i2c.SendByte(reg);
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while (n--) i2c.SendByte(*data++);
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i2c.stop();
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}
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void SendRegister(uint8_t reg, uint8_t val){ SendRegister(reg, &val, 1); }
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uint32_t fxtal = 27004900; // Crystal freq in Hz, nominal frequency 27004300
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uint8_t iqmsa; // to detect a need for a PLL reset
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void freq(uint32_t fout, uint8_t i, uint8_t q){ // Set a CLK0,1 to fout Hz with phase i, q
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uint8_t msa; uint32_t msb, msc, msp1, msp2, msp3p2;
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uint8_t rdiv = 0; // CLK pin sees fout/(2^rdiv)
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if(fout < 500000){ rdiv = 7; fout *= 128; }; // Divide by 128 for fout 4..500kHz
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uint16_t d = (16 * fxtal) / fout; // Integer part
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if( (d * (fout - 5000) / fxtal) != (d * (fout + 5000) / fxtal) ) d--; // Test if multiplier remains same for freq deviation +/- 5kHz, if not use different divider to make same
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uint32_t fvcoa = d * fout; // Variable PLLA VCO frequency at integer multiple of fout at around 27MHz*16 = 432MHz
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msa = fvcoa / fxtal; // Integer part of vco/fxtal
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msb = ((uint64_t)(fvcoa % fxtal)*_MSC) / fxtal; // Fractional part
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msc = _MSC;
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msp1 = 128*msa + 128*msb/msc - 512;
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msp2 = 128*msb - 128*msb/msc * msc; // msp3 == msc
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msp3p2 = (((msc & 0x0F0000) <<4) | msp2); // msp3 on top nibble
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uint8_t pll_regs[8] = { BB1(msc), BB0(msc), BB2(msp1), BB1(msp1), BB0(msp1), BB2(msp3p2), BB1(msp2), BB0(msp2) };
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SendRegister(26+0*8, pll_regs, 8); // Write to PLLA
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SendRegister(26+1*8, pll_regs, 8); // Write to PLLB
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msa = fvcoa / fout; // Integer part of vco/fout
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msp1 = (128*msa - 512) | (((uint32_t)rdiv)<<20); // msp1 and msp2=0, msp3=1, not fractional
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uint8_t ms_regs[8] = {0, 1, BB2(msp1), BB1(msp1), BB0(msp1), 0, 0, 0};
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SendRegister(42+0*8, ms_regs, 8); // Write to MS0
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SendRegister(42+1*8, ms_regs, 8); // Write to MS1
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SendRegister(42+2*8, ms_regs, 8); // Write to MS2
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SendRegister(16+0, 0x0C|3); // CLK0: PLLA local msynth; 3=8mA
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SendRegister(16+1, 0x0C|3); // CLK1: PLLA local msynth; 3=8mA
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SendRegister(16+2, 0x2C|3); // CLK2: PLLB local msynth; 3=8mA
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SendRegister(165, i * msa / 90); // CLK0: I-phase (on change -> Reset PLL)
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SendRegister(166, q * msa / 90); // CLK1: Q-phase (on change -> Reset PLL)
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if(iqmsa != ((i-q)*msa/90)){ iqmsa = (i-q)*msa/90; SendRegister(177, 0xA0); } // 0x20 reset PLLA; 0x80 reset PLLB
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SendRegister(3, 0b11111100); // Enable/disable clock
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_fout = fout; // cache
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_div = d;
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_msa128min512 = fvcoa / fxtal * 128 - 512;
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_msb128=((uint64_t)(fvcoa % fxtal)*_MSC*128) / fxtal;
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}
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volatile int32_t prev_pll_freq;
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uint8_t RecvRegister(uint8_t reg){
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i2c.start(); // Data write to set the register address
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i2c.SendByte(SI5351_ADDR << 1);
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i2c.SendByte(reg);
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i2c.stop();
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i2c.start(); // Data read to retrieve the data from the set address
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i2c.SendByte((SI5351_ADDR << 1) | 1);
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uint8_t data = i2c.RecvByte(true);
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i2c.stop();
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return data;
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}
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void powerDown(){
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for(int addr = 16; addr != 24; addr++) SendRegister(addr, 0b11000000); // Conserve power when output is disabled
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SendRegister(3, 0b11111111); // Disable all CLK outputs
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}
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#define SI_CLK_OE 3
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};
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static SI5351 si5351;
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// */
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/*
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class SI5351 : public I2C {
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public:
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#define log2(n) (log(n) / log(2))
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#define SI_I2C_ADDR 0x60 // SI5351A I2C address: 0x60 for SI5351A-B-GT; 0x62 for SI5351A-B-04486-GT; 0x6F for SI5351A-B02075-GT; see here for other variants: https://www.silabs.com/TimingUtility/timing-download-document.aspx?OPN=Si5351A-B02075-GT&OPNRevision=0&FileType=PublicAddendum
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#define SI_CLK_OE 3 // Register definitions
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#define SI_CLK0_CONTROL 16
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@ -254,7 +383,7 @@ public:
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volatile int32_t raw_freq;
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volatile uint8_t divider; // note: because of int8 only freq > 3.6MHz can be covered for R_DIV=1
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volatile uint8_t mult;
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volatile uint8_t pll_data[8];
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volatile uint8_t pll_regs[8];
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volatile int32_t prev_pll_freq;
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volatile int32_t pll_freq; // temporary
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@ -315,18 +444,18 @@ public:
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{
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start();
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SendByte(SI_I2C_ADDR << 1);
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SendByte(SI_SYNTH_PLL_B + 3); // Skip the first three pll_data bytes (first two always 0xFF and third not often changing
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SendByte(pll_data[3]);
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SendByte(pll_data[4]);
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SendByte(pll_data[5]);
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SendByte(pll_data[6]);
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SendByte(pll_data[7]);
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SendByte(SI_SYNTH_PLL_B + 3); // Skip the first three pll_regs bytes (first two always 0xFF and third not often changing
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SendByte(pll_regs[3]);
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SendByte(pll_regs[4]);
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SendByte(pll_regs[5]);
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SendByte(pll_regs[6]);
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SendByte(pll_regs[7]);
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stop();
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}
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#define FAST __attribute__((optimize("Ofast")))
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// this function relies on cached (global) variables: divider, mult, raw_freq, pll_data
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// this function relies on cached (global) variables: divider, mult, raw_freq, pll_regs
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inline void FAST freq_calc_fast(int16_t freq_offset)
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{ // freq_offset is relative to freq set in freq(freq)
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// uint32_t num128 = ((divider * (raw_freq + offset)) % fxtal) * (float)(0xFFFFF * 128) / fxtal;
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@ -339,14 +468,14 @@ public:
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// Set up specified PLL with mult, num and denom: mult is 15..90, num128 is 0..128*1,048,575 (128*0xFFFFF), denom is 0..1,048,575 (0xFFFFF)
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uint32_t P1 = 128 * mult + (num128 / 0xFFFFF) - 512;
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uint32_t P2 = num128 % 0xFFFFF;
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//pll_data[0] = 0xFF;
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//pll_data[1] = 0xFF;
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//pll_data[2] = (P1 >> 14) & 0x0C;
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pll_data[3] = P1 >> 8;
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pll_data[4] = P1;
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pll_data[5] = 0xF0 | (P2 >> 16);
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pll_data[6] = P2 >> 8;
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pll_data[7] = P2;
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//pll_regs[0] = 0xFF;
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//pll_regs[1] = 0xFF;
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//pll_regs[2] = (P1 >> 14) & 0x0C;
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pll_regs[3] = P1 >> 8;
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pll_regs[4] = P1;
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pll_regs[5] = 0xF0 | (P2 >> 16);
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pll_regs[6] = P2 >> 8;
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pll_regs[7] = P2;
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}
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uint16_t div(uint32_t num, uint32_t denom, uint32_t* b, uint32_t* c)
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{ // returns a + b / c = num / denom, where a is the integer part and b and c is the optional fractional part 20 bits each (range 0..1048575)
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@ -362,14 +491,15 @@ public:
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}
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void freq(uint32_t freq, uint8_t i, uint8_t q)
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{ // Fout = Fvco / (R * [MSx_a + MSx_b/MSx_c]), Fvco = Fxtal * [MSPLLx_a + MSPLLx_b/MSPLLx_c]; MSx as integer reduce spur
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uint8_t r_div = (freq > (SI_PLL_FREQ/256/1)) ? 1 : (freq > (SI_PLL_FREQ/256/32)) ? 32 : 128; // helps divider to be in range
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//uint8_t r_div = (freq > (SI_PLL_FREQ/256/1)) ? 1 : (freq > (SI_PLL_FREQ/256/32)) ? 32 : 128; // helps divider to be in range
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uint8_t r_div = (freq < 500000) ? 128 : 1;
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freq *= r_div; // take r_div into account, now freq is in the range 1MHz to 150MHz
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raw_freq = freq; // cache frequency generated by PLL and MS stages (excluding R divider stage); used by freq_calc_fast()
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divider = SI_PLL_FREQ / freq; // Calculate the division ratio. 900,000,000 is the maximum internal PLL freq (official range 600..900MHz but can be pushed to 300MHz..~1200Mhz)
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if(divider % 2) divider--; // divider in range 8.. 900 (including 4,6 for integer mode), even numbers preferred. Note that uint8 datatype is used, so 254 is upper limit
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if( (divider * (freq - 5000) / fxtal) != (divider * (freq + 5000) / fxtal) ) divider -= 2; // Test if multiplier remains same for freq deviation +/- 5kHz, if not use different divider to make same
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/*int32_t*/ pll_freq = divider * freq; // Calculate the pll_freq: the divider * desired output freq
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pll_freq = divider * freq; // Calculate the pll_freq: the divider * desired output freq
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uint32_t num, denom;
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mult = div(pll_freq, fxtal, &num, &denom); // Determine the mult to get to the required pll_freq (in the range 15..90)
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@ -435,6 +565,7 @@ public:
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}
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};
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static SI5351 si5351;
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*/
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#undef F_CPU
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#define F_CPU 20007000 // myqcx1:20008440, myqcx2:20006000 // Actual crystal frequency of 20MHz XTAL1, note that this declaration is just informative and does not correct the timing in Arduino functions like delay(); hence a 1.25 factor needs to be added for correction.
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@ -558,7 +689,7 @@ void dsp_tx()
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int16_t adc = ADC - 512; // current ADC sample 10-bits analog input, NOTE: first ADCL, then ADCH
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int16_t df = ssb(adc >> MIC_ATTEN); // convert analog input into phase-shifts (carrier out by periodic frequency shifts)
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si5351.freq_calc_fast(df); // calculate SI5351 registers based on frequency shift and carrier frequency
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#define CARRIER_COMPLETELY_OFF_ON_LOW 1
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//#define CARRIER_COMPLETELY_OFF_ON_LOW 1
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#ifdef CARRIER_COMPLETELY_OFF_ON_LOW
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if(OCR1BL == 0){ si5351.SendRegister(SI_CLK_OE, (amp) ? 0b11111011 : 0b11111111); } // experimental carrier-off for low amplitudes
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#endif
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@ -1120,65 +1251,6 @@ ISR(TIMER2_COMPA_vect) // Timer2 COMPA interrupt
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#endif
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}
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/*
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ISR(TIMER2_COMPA_vect, ISR_NAKED) // Timer2 COMPA interrupt, naked ISR: no prologue/epilogue generated (an ISR takes at least 38 clock cycles)
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{
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asm volatile( //prologue (register explanation: https://stackoverflow.com/questions/23943129/gcc-generating-useless-code-in-isr )
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"push r1\n\r" //Fixed Registers: R1 always contains zero. During an insn the content might be destroyed, e.g. by a MUL instruction that uses R0/R1 as implicit output register. If an insn destroys R1, the insn must restore R1 to zero afterwards. This register must be saved in ISR prologues and must then be set to zero because R1 might contain values other than zero. The ISR epilogue restores the value. In inline assembler you can use __zero_reg__ for the zero register.
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"push r0\n\r" //Fixed Registers: R0 is used as scratch register that need not to be restored after its usage. It must be saved and restored in interrupt service routine's (ISR) prologue and epilogue. In inline assembler you can use __tmp_reg__ for the scratch register.
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"in r0,__SREG__\n\r"
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"push r0\n\r"
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"clr __zero_reg__\n\r"
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"push r18\n\r" //Call-Clobbered Registers: R18–R27, R30, R31 These GPRs are call clobbered. An ordinary function may use them without restoring the contents. Interrupt service routines (ISRs) must save and restore each register they use.
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"push r19\n\r"
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"push r20\n\r"
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"push r21\n\r"
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"push r22\n\r"
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"push r23\n\r"
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"push r24\n\r"
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"push r25\n\r"
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"push r26\n\r"
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"push r27\n\r"
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"push r30\n\r"
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"push r31\n\r"
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); // Call-Saved Registers: R2–R17, R28, R29 The remaining GPRs are call-saved, i.e. a function that uses such a registers must restore its original content. This applies even if the register is used to pass a function argument.
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func_ptr();
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// asm volatile(
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// "lds r30,func_ptr\n\r"
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// "lds r31,func_ptr+1\n\r"
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// "icall\n\r"
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// );
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#ifdef DEBUG
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//numSamples++;
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asm volatile(
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"lds r24,numSamples\n\r"
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"lds r25,numSamples+1\n\r"
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"adiw r24,1\n\r"
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"sts numSamples+1,r25\n\r"
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"sts numSamples,r24\n\r"
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);
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#endif
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asm volatile( //epilogue
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"pop r31\n\r"
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"pop r30\n\r"
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"pop r27\n\r"
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"pop r26\n\r"
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"pop r25\n\r"
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"pop r24\n\r"
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"pop r23\n\r"
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"pop r22\n\r"
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"pop r21\n\r"
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"pop r20\n\r"
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"pop r19\n\r"
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"pop r18\n\r"
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"pop r0\n\r"
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"out __SREG__,r0\n\r"
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"pop r0\n\r"
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"pop r1\n\r"
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"reti\n\r"
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);
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}*/
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void adc_start(uint8_t adcpin, bool ref1v1, uint32_t fs)
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{
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DIDR0 |= (1 << adcpin); // disable digital input
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@ -1538,22 +1610,17 @@ void show_banner(){
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const char* mode_label[5] = { "LSB", "USB", "CW ", "AM ", "FM " };
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void display_vfo(uint32_t freq){
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void display_vfo(uint32_t f){
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||||
lcd.setCursor(0, 1);
|
||||
lcd.print('\x06'); // VFO
|
||||
uint32_t n = freq / 1000000; // lcd.print(f) with commas
|
||||
uint32_t n2 = freq % 1000000;
|
||||
uint32_t scale = 1000000;
|
||||
char buf[16];
|
||||
sprintf(buf, "%2u", n); lcd.print(buf);
|
||||
while(scale != 1){
|
||||
scale /= 1000;
|
||||
n = n2 / scale;
|
||||
n2 = n2 % scale;
|
||||
if(scale == 1) sprintf(buf, ",%02u", n / 10); else // leave last digit out
|
||||
sprintf(buf, ",%03u", n);
|
||||
lcd.print(buf);
|
||||
lcd.print('\x06'); // VFO A/B
|
||||
|
||||
uint32_t scale=10e6; // VFO frequency
|
||||
if(f/scale == 0){ lcd.print(' '); scale/=10; } // Initial space instead of zero
|
||||
for(; scale!=1; f%=scale, scale/=10){
|
||||
lcd.print(f/scale);
|
||||
if(scale == (uint32_t)1e3 || scale == (uint32_t)1e6) lcd.print(','); // Thousands separator
|
||||
}
|
||||
|
||||
lcd.print(" "); lcd.print(mode_label[mode]); lcd.print(" ");
|
||||
lcd.setCursor(15, 1); lcd.print("R");
|
||||
}
|
||||
|
|
@ -1897,9 +1964,10 @@ void setup()
|
|||
uint16_t i2c_error = 0; // number of I2C byte transfer errors
|
||||
for(i = 0; i != 1000; i++){
|
||||
si5351.freq_calc_fast(i);
|
||||
//for(int j = 3; j != 8; j++) si5351.pll_data[j] = rand();
|
||||
//for(int j = 3; j != 8; j++) si5351.pll_regs[j] = rand();
|
||||
si5351.SendPLLBRegisterBulk();
|
||||
for(int j = 3; j != 8; j++) if(si5351.RecvRegister(SI_SYNTH_PLL_B + j) != si5351.pll_data[j]) i2c_error++;
|
||||
#define SI_SYNTH_PLL_B 34
|
||||
for(int j = 3; j != 8; j++) if(si5351.RecvRegister(SI_SYNTH_PLL_B + j) != si5351.pll_regs[j]) i2c_error++;
|
||||
}
|
||||
if(i2c_error){
|
||||
lcd.setCursor(0, 1); lcd.print(F("!!BER_i2c=")); lcd.print(i2c_error); lcd_blanks();
|
||||
|
|
|
|||
|
|
@ -250,6 +250,8 @@ The following performance measurements were made with QCX-SSB R1.01, a modified
|
|||
|
||||
[RX3DPK]: https://www.facebook.com/photo.php?fbid=2382353591830446&set=pcb.2382353628497109&type=3&theater
|
||||
|
||||
[QRP-BR]: https://groups.io/g/QRP-BR/topic/gerando_ssb_digitalmente/29628623
|
||||
|
||||
[Opzij]: https://youtu.be/uN706PiFLm0
|
||||
|
||||
[lyrics]: https://www.google.com/search?q=lyrics+opzij
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue