kopia lustrzana https://github.com/ArjanteMarvelde/uSDR-pico
433 wiersze
16 KiB
C
433 wiersze
16 KiB
C
/*
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* si5351.c
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*
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* Created: Jan 2020
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* Author: Arjan
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*
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* Driver for the SI5351A VCO
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*
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Si5351 principle of operation:
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==============================
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Crystal frequency Fxtal (usually 25MHz) is multiplied in a PLL by MSN to obtain Fvco.
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PLL A and B have independent MSN values, the Fout channel i can be derived from either.
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Fvco is between 600MHz and 900MHz, but the spec in reality is more relaxed.
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Fvco is divided by MSi and Ri to obtain the output frequency Fout.
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MSi and Ri are selected to be in the ballpark of desired frequency range.
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MSN is then used for tuning.
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Only certain values of MSi and Ri are allowed when quadrature output is needed.
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+-------+ +-------+ +------+
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- Fxtal --> | * MSN | -- Fvco --> | / MSi | --> | / Ri | -- Fout -->
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+-------+ +-------+ +------+
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Details:
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========
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---Derivation of Fout---
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MSN determines: Fvco = Fxtal * (MSN) , where MSN = a + b/c
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MSi and Ri determine: Fout = Fvco / (Ri*MSi) , where MSi = a + b/c (different a, b and c)
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---Derivation of register values, for MSN and MSi---
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P1 = 128*a + Floor(128*b/c) - 512
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P2 = 128*b - c*Floor(128*b/c) (P2 = 0 for MSi integer mode, or calculated for MSN tuning)
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P3 = c (P3 = 1 for MSi integer mode, or P3 = 1000000 for MSN tuning)
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This VFO implementation assumes PLLA is used for clk0 and clk1, PLLB is used for clk2
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Algorithm to get from frequency to synthesizer settings:
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(this assumes that the current settings are consistent, i.e. must be initialized at startup)
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| calculate new MSN from the desired Fout, based on current Ri and MSi
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| if MSN is still inside [600/Fxtal, 900/Fxtal]
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| then
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| just write the MSN parameter registers
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| else
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| re-calculate MSi, Ri and MSN from desired Fout
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| write the MSi and Ri parameter registers, including phase offset (MSi equals phase offset for 90 deg, use INV to shift 180deg more)
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| write the MSN parameter registers
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| reset PLL
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Ri=128 for Fout <1 MHz
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Ri= 32 for Fout 1-6 MHz
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Ri= 1 for Fout >6 MHz
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Some boundary values:
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Ri MSi Lo MHz Hi MHz
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1 4 150.000000 225.000000
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1 126 4.761905 7.142857
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32 4 4.687500 7.031250
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32 126 0.148810 0.223214
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128 4 1.171875 1.757813
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128 126 0.037202 0.055804
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MSi: target for mid-band, i.e. Fvco=750MHz
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MSi = 750MHz/(Fout*Ri)
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MSi &= 0xfe // Make it even
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MSN = MSi*Ri*Fout/Fxtal (should be between 24 and 36)
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Only use MSi even-integers, i.e. d=[4, 6, 8..126], e=0 and f=100000, and set INT bits in reg 22, 23.
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Quadrature Phase offsets (i.e. delay):
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- Offset for MS0 (reg 165) must be 0 (cosine),
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- Offset for MS1 (reg 166) must be equal to divider MS1 for 90 deg (sine),
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- Set INV bit (reg 17) to add 180 deg.
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NOTE: Phase offsets only work when Ri = 1, this means minimum Fout is 4.762MHz at Fvco = 600MHz. Additional flip/flop dividers are needed to get 80m band frequencies, or Fvco must be tuned below spec.
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Control Si5351 (see AN619):
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===========================
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----+---------+---------+---------+---------+---------+---------+---------+---------+
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@ | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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----+---------+---------+---------+---------+---------+---------+---------+---------+
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0 |SYS_INIT | LOL_B | LOL_A | LOS | Reserved | REVID[1:0] |
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1 |SYS_INIT | LOS_B | LOL_A | LOS | Reserved |
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| _STKY| _STKY| _STKY| _STKY| Reserved |
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2 |SYS_INIT | LOS_B | LOL_A | LOS | Reserved |
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| _MASK| _MASK| _MASK| _MASK| Reserved |
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3 | Reserved | CLK2_EN | CLK1_EN | CLK0_EN |
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====
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9 | Reserved |OEB_MASK2|OEB_MASK1|OEB_MASK0|
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====
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15 | CLKIN_DIV[2:0] | 0 | 0 | PLLB_SRC| PLLA_SRC| 0 | 0 |
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16 | CLK0_PDN| MS0_INT | MS0_SRC | CLK0_INV| CLK0_SRC[1:0] | CLK0_IDRV[1:0] |
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17 | CLK1_PDN| MS1_INT | MS1_SRC | CLK1_INV| CLK1_SRC[1:0] | CLK1_IDRV[1:0] |
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18 | CLK2_PDN| MS2_INT | MS2_SRC | CLK2_INV| CLK2_SRC[1:0] | CLK2_IDRV[1:0] |
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====
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22 | Reserved| FBA_INT | Reserved |
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23 | Reserved| FBB_INT | Reserved |
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24 | Reserved | CLK2_DIS_STATE | CLK1_DIS_STATE | CLK0_DIS_STATE |
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====
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26 | MSNA_P3[15:8] |
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27 | MSNA_P3[7:0] |
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28 | Reserved | MSNA_P1[17:16] |
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29 | MSNA_P1[15:8] |
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30 | MSNA_P1[7:0] |
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31 | MSNA_P3[19:16] | MSNA_P2[19:16] |
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32 | MSNA_P2[15:8] |
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33 | MSNA_P2[7:0] |
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34: Same pattern for PLLB
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42 | MS0_P3[15:8] |
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43 | MS0_P3[7:0] |
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44 | Reserved| R0_DIV[2:0] | MS0_DIVBY4[1:0] | MS0_P1[17:16] |
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45 | MS0_P1[15:8] |
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46 | MS0_P1[7:0] |
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47 | MS0_P3[19:16] | MS0_P2[19:16] |
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48 | MS0_P2[15:8] |
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49 | MS0_P2[7:0] |
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50: Same pattern for CLK1
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58: Same pattern for CLK2
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====
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165 | Reserved| CLK0_PHOFF[6:0] |
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166 | Reserved| CLK1_PHOFF[6:0] |
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167 | Reserved| CLK2_PHOFF[6:0] |
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====
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177 | PLLB_RST| Reserved| PLLA_RST| Reserved |
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====
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183 | XTAL_CL | Reserved |
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====
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*
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*/
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#include <stdio.h>
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#include <math.h>
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#include "pico/stdlib.h"
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#include "hardware/i2c.h"
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#include "hardware/timer.h"
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#include "hardware/clocks.h"
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#include "si5351.h"
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#define I2C_VFO 0x60 // I2C address
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// SI5351 register address definitions
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#define SI_CLK_OE 3
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#define SI_CLK0_CTL 16
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#define SI_CLK1_CTL 17
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#define SI_CLK2_CTL 18
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#define SI_SYNTH_PLLA 26
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#define SI_SYNTH_PLLB 34
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#define SI_SYNTH_MS0 42
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#define SI_SYNTH_MS1 50
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#define SI_SYNTH_MS2 58
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#define SI_SS_EN 149
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#define SI_CLK0_PHOFF 165
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#define SI_CLK1_PHOFF 166
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#define SI_CLK2_PHOFF 167
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#define SI_PLL_RESET 177
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#define SI_XTAL_LOAD 183
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// CLK_OE register 3 values
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#define SI_CLK0_ENABLE 0b00000001 // Enable clock 0 output
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#define SI_CLK1_ENABLE 0b00000010 // Enable clock 1 output
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#define SI_CLK2_ENABLE 0b00000100 // Enable clock 2 output
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// CLKi_CTL register 16, 17, 18 values
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// Normally 0x4f for clk 0 and 1, 0x6f for clk 2
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#define SI_CLK_INT 0b01000000 // Set integer mode
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#define SI_CLK_PLL 0b00100000 // Select PLL B as MS source (default 0 = PLL A)
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#define SI_CLK_INV 0b00010000 // Invert output (i.e. phase + 180deg)
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#define SI_CLK_SRC 0b00001100 // Select output source: 11=MS, 00=XTAL direct
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#define SI_CLK_DRV 0b00000011 // Select output drive, increasingly: 2-4-6-8 mA (best risetime, use max = 11)
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// PLL_RESET register 177 values
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#define SI_PLLB_RST 0b10000000 // Reset PLL B
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#define SI_PLLA_RST 0b00100000 // Reset PLL A
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#define SI_XTAL_FREQ 25001414UL // Replace with measured crystal frequency of XTAL for CL = 10pF (default)
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#define SI_MSN_LO ((0.6e9)/SI_XTAL_FREQ)
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#define SI_MSN_HI ((0.9e9)/SI_XTAL_FREQ)
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#define SI_PLL_C 1000000UL // Parameter c for PLL-A and -B setting
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vfo_t vfo[2]; // 0: clk0 & clk1 1: clk2
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/*
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* read contents of SI5351 registers, from reg to reg+len-1, output in data array
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*/
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int si_getreg(uint8_t *data, uint8_t reg, uint8_t len)
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{
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int ret;
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ret = i2c_write_blocking(i2c0, I2C_VFO, ®, 1, true);
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if (ret<0) printf ("I2C write error\n");
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ret = i2c_read_blocking(i2c0, I2C_VFO, data, len, false);
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if (ret<0) printf ("I2C read error\n");
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return(len);
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}
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/*
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* Set up MSN PLL divider for vfo[i], assuming MSN has been set in vfo[i]
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* Optimize for speed, this may be called with short intervals
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* See also SiLabs AN619 section 3.2
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*/
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void si_setmsn(uint8_t i)
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{
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uint8_t data[16]; // I2C trx buffer
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uint32_t P1, P2; // MSN parameters
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uint32_t A;
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uint32_t B;
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i=(i>0?1:0);
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A = (uint32_t)(floor(vfo[i].msn)); // A is integer part of MSN
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B = (uint32_t)((vfo[i].msn - (float)A) * SI_PLL_C); // B is C * fraction part of MSN (C is a constant)
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P2 = (uint32_t)(floor((float)(128 * B) / (float)SI_PLL_C));
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P1 = (uint32_t)(128 * A + P2 - 512);
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P2 = (uint32_t)(128 * B - SI_PLL_C * P2);
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// transfer registers
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data[0] = (i==0?SI_SYNTH_PLLA:SI_SYNTH_PLLB);
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data[1] = (SI_PLL_C & 0x0000FF00) >> 8;
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data[2] = (SI_PLL_C & 0x000000FF);
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data[3] = (P1 & 0x00030000) >> 16;
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data[4] = (P1 & 0x0000FF00) >> 8;
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data[5] = (P1 & 0x000000FF);
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data[6] = ((SI_PLL_C & 0x000F0000) >> 12) | ((P2 & 0x000F0000) >> 16);
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data[7] = (P2 & 0x0000FF00) >> 8;
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data[8] = (P2 & 0x000000FF);
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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}
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/*
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* Set up registers with MS and R divider for vfo[i], assuming values have been set in vfo[i]
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* In this implementation we only use integer mode, i.e. b=0 and P3=1
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* See also SiLabs AN619 section 4.1
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*/
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void si_setmsi(uint8_t i)
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{
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uint8_t data[16]; // I2C trx buffer
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uint32_t P1;
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uint8_t R;
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i=(i>0?1:0);
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P1 = (uint32_t)(128*(uint32_t)floor(vfo[i].msi) - 512);
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R = vfo[i].ri;
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R = (R&0xf0) ? ((R&0xc0)?((R&0x80)?7:6):(R&0x20)?5:4) : ((R&0x0c)?((R&0x08)?3:2):(R&0x02)?1:0); // quick log2(r)
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data[0] = (i==0?SI_SYNTH_MS0:SI_SYNTH_MS2);
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data[1] = 0x00;
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data[2] = 0x01;
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data[3] = ((P1 & 0x00030000) >> 16) | (R << 4 );
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data[4] = (P1 & 0x0000FF00) >> 8;
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data[5] = (P1 & 0x000000FF);
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data[6] = 0x00;
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data[7] = 0x00;
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data[8] = 0x00;
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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// If vfo[0] also set clk 1
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if (i==0)
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{
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data[0] = SI_SYNTH_MS1; // Same data in synthesizer
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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if (vfo[0].phase&1) // Phase is either 90 or 270 deg?
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{
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data[0] = SI_CLK1_PHOFF;
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data[1] = vfo[0].msi;
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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else // Phase is 0 or 180 deg
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{
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data[0] = SI_CLK1_PHOFF;
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data[1] = 0;
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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if (vfo[0].phase&2) // Phase is 180 or 270 deg?
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{
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data[0] = SI_CLK1_CTL;
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data[1] = 0x5d; // CLK1: INT, PLLA, INV, MS, 8mA
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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}
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// Reset associated PLL
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data[0] = SI_PLL_RESET;
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data[1] = (i==1)?0x80:0x20;
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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/*
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* For each vfo, calculate required MSN setting, MSN = MSi*Ri*Fout/Fxtal
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* If in range, just set MSN registers
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* If not in range, recalculate MSi and Ri and also MSN
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* Set MSN, MSi and Ri registers (implicitly resets PLL)
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*/
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void si_evaluate(void)
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{
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float msn;
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if (vfo[0].flag)
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{
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msn = (float)(vfo[0].msi); // Re-calculate MSN
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msn = msn * (float)(vfo[0].ri);
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msn = msn * (float)(vfo[0].freq) / SI_XTAL_FREQ;
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if ((msn>=SI_MSN_LO)&&(msn<SI_MSN_HI))
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{
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vfo[0].msn = msn;
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si_setmsn(0);
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}
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else
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{
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vfo[0].ri = (vfo[0].freq<1000000)?128:((vfo[0].freq<3000000)?32:1); // Pre-scale Ri, stretch down Ri=1 range
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if ((vfo[0].freq >= 3000000)&&(vfo[0].freq < 6000000)) // Low end of Ri=1 range
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vfo[0].msi = (uint8_t)126; // Maximum MSi on Fvco=(4x126)MHz
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else
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vfo[0].msi = (uint8_t)(750000000UL / (vfo[0].freq * vfo[0].ri)) & 0xfe; // Calculate MSi on Fvco=750MHz
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msn = (float)(vfo[0].msi); // Re-calculate MSN
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msn = msn * (float)(vfo[0].ri);
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msn = msn * (float)(vfo[0].freq) / SI_XTAL_FREQ;
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vfo[0].msn = msn;
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si_setmsn(0);
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si_setmsi(0);
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}
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vfo[0].flag = 0;
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}
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if (vfo[1].flag)
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{
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vfo[1].flag = 0;
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}
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}
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/*
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* Initialize the Si5351 VFO registers
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* Hard initialize Synth registers to: 7.074MHz, CLK1 90 deg ahead, PLLA for CLK 0&1, PLLB for CLK2
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| Ri=1,
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| MSi=68, P1=8192, P2=0, P3=1
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| MSN=27.2 P1=2969, P2=600000, P3=1000000
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*/
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void si_init(void)
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{
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uint8_t data[16]; // I2C trx buffer
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vfo[0].freq = 10000000; // Check this, should be 7074000?
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vfo[0].flag = 0;
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vfo[0].phase = 1;
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vfo[0].ri = 1;
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vfo[0].msi = 68;
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vfo[0].msn = 27.2;
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vfo[1].freq = 10000000; // Check this, should be 7074000?
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vfo[1].flag = 0;
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vfo[1].phase = 0;
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vfo[1].ri = 1;
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vfo[1].msi = 68;
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vfo[1].msn = 27.2;
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// PLLA: MSN P1=0x00000b99, P2=0x000927c0, P3=0x000f4240
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data[0] = SI_SYNTH_PLLA;
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data[1] = 0x42; // MSNA_P3[15:8]
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data[2] = 0x40; // MSNA_P3[7:0]
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data[3] = 0x00; // 0b000000 , MSNA_P1[17:16]
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data[4] = 0x0b; // MSNA_P1[15:8]
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data[5] = 0x99; // MSNA_P1[7:0]
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data[6] = 0xf9; // MSNA_P3[19:16] , MSNA_P2[19:16]
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data[7] = 0x27; // MSNA_P2[15:8]
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data[8] = 0xc0; // MSNA_P2[7:0]
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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// PLLB: MSN P1=0x00000b99, P2=0x000927c0, P3=0x000f4240
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data[0] = SI_SYNTH_PLLB; // Same content
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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// MS0 P1=0x00002000, P2=0x00000000, P3=0x00000001, R=1
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data[0] = SI_SYNTH_MS0;
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data[1] = 0x00; // MS0_P3[15:8]
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data[2] = 0x01; // MS0_P3[7:0]
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data[3] = 0x00; // 0b0, R0_DIV[2:0] , MS0_DIVBY4[1:0] , MS0_P1[17:16]
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data[4] = 0x20; // MS0_P1[15:8]
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data[5] = 0x00; // MS0_P1[7:0]
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data[6] = 0x00; // MS0_P3[19:16] , MS0_P2[19:16]
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data[7] = 0x00; // MS0_P2[15:8]
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data[8] = 0x00; // MS0_P2[7:0]
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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// MS1 P1=0x00002000, P2=0x00000000, P3=0x00000001, R=1
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data[0] = SI_SYNTH_MS1; // Same content
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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// MS2 P1=0x00002000, P2=0x00000000, P3=0x00000001, R=1
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data[0] = SI_SYNTH_MS2; // Same content
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i2c_write_blocking(i2c0, I2C_VFO, data, 9, false);
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// Phase offsets for 3 clocks
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data[0] = SI_CLK0_PHOFF;
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data[1] = 0x00; // CLK0: phase 0 deg
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data[2] = 0x44; // CLK1: phase 90 deg (=MSi)
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data[3] = 0x00; // CLK2: phase 0 deg
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i2c_write_blocking(i2c0, I2C_VFO, data, 4, false);
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// Output port settings for 3 clocks
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data[0] = SI_CLK0_CTL;
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data[1] = 0x4d; // CLK0: INT, PLLA, nonINV, MS, 4mA
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data[2] = 0x4d; // CLK1: INT, PLLA, nonINV, MS, 4mA
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data[3] = 0x6f; // CLK2: INT, PLLB, nonINV, MS, 8mA
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i2c_write_blocking(i2c0, I2C_VFO, data, 4, false);
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// Disable spread spectrum (startup state is undefined)
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data[0] = SI_SS_EN;
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data[1] = 0x00;
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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// Reset both PLL
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data[0] = SI_PLL_RESET;
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data[1] = 0xa0;
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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// Enable all outputs
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data[0] = SI_CLK_OE;
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data[1] = 0x00;
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i2c_write_blocking(i2c0, I2C_VFO, data, 2, false);
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}
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