kopia lustrzana https://github.com/ArjanteMarvelde/uSDR-pico
ArjanteMarvelde
rodzic
2fa37a0f70
commit
70cf9074e8
228
dsp.c
228
dsp.c
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@ -34,6 +34,8 @@
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#include "hardware/timer.h"
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#include "hardware/clocks.h"
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#define ADC0_IRQ_FIFO 22
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#include "dsp.h"
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/*
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@ -73,34 +75,51 @@ int16_t lpf7_31[15] = { -1, 4, 9, 2,-12, -2, 40, 66, 40, -2,-12, 2, 9, 4,
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int16_t lpf15_62[15] = { -1, 3, 12, 6,-12, -4, 40, 69, 40, -4,-12, 6, 12, 3, -1}; // Pass: 0-15000, Stop: 20000-31250
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volatile uint16_t dac_iq, dac_audio;
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volatile uint32_t fifo_overrun;
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volatile bool tx_enabled;
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void dsp_ptt(bool active)
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{
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tx_enabled = active;
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}
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/*
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* CORE1:
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* ADC IRQ handler.
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* Fills the results array in RR fashion, for 3 channels (~2usec per channel).
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*/
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volatile uint16_t adc_result[3];
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volatile int adc_next; // Remember which ADC the result is from
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uint32_t adc_count=0;
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void adcfifo_handler(void)
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{
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adc_result[adc_next] = adc_fifo_get();
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adc_next = adc_hw->cs;
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adc_next = (adc_next >> ADC_CS_AINSEL_LSB) & 3; // Only 0, 1 and are valid
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adc_count++;
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}
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/*
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* CORE1:
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* Execute RX branch signal processing
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* No interleaving, since only 2us per conversion
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* Execute RX branch signal processing, max time to spend is <16us !
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* No ADC sample interleaving, take both I and Q channels.
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* The delay is only 2us per conversion, which causes less distortion than interpolation of samples.
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*/
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volatile int16_t i_s_raw[15], q_s_raw[15]; // Raw I/Q samples minus DC bias
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volatile int16_t i_s[15], q_s[15]; // Filtered I/Q samples
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volatile int16_t i_dc, q_dc; // DC bias for I/Q channel
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volatile int dec_cnt=0; // Decimation counter
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volatile int rx_cnt=0; // Decimation counter
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bool rx(void)
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{
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int16_t q_sample, i_sample;
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int32_t q_accu, i_accu;
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int16_t qh;
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int i;
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adc_select_input(1); // Q channel ADC
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q_sample = (int16_t)adc_read(); // Take Q sample
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adc_select_input(0); // I channel ADC
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i_sample = (int16_t)adc_read(); // Take I sample
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i_sample = adc_result[0]; // Take last ADC 0 result
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q_sample = adc_result[1]; // Take last ADC 1 result
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/*
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* Shift in I and Q raw samples
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@ -113,32 +132,27 @@ bool rx(void)
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/*
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* Remove DC and store new sample
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//Other algo: y[i] = alpha * x[i] + (1-alpha) * y[i-1]
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* w(t) = x(t) + a*w(t-1) (use a=7/8, ca 0.87)
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* y(t) = w(t) - w(t-1)
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* IIR filter: dc = a*sample + (1-a)*dc where a = 1/128
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*/
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// q_sample += (((q_dc<<3)-q_dc)>>3); // Use sample as temporary q_dc
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// q_s_raw[14] = q_sample - q_dc; // Calculate output
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// q_dc = q_sample; // Store new q_dc
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q_s_raw[14] = (q_sample&0x0fff) - ADC_BIAS; // just clip and subtract mid-level
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// -_sample += (((i_dc<<3)-i_dc)>>3); // Use sample as temporary i_dc
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// i_s_raw[14] = i_sample - i_dc; // Calculate output
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// i_dc = i_sample; // Store new i_dc
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i_s_raw[14] = (i_sample&0x0fff) - ADC_BIAS; // just clip and subtract mid-level
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q_sample = (q_sample&0x0fff) - ADC_BIAS; // Clip and subtract mid-range
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q_dc = (q_sample>>7) + q_dc - (q_dc>>7); // then IIR running average
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q_s_raw[14] = q_sample - q_dc; // and subtract DC, store in shift register
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i_sample = (i_sample&0x0fff) - ADC_BIAS;
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i_dc = (i_sample>>7) + i_dc - (i_dc>>7);
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i_s_raw[14] = i_sample - i_dc;
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/*
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* Low pass filter + decimation
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*/
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dec_cnt = (dec_cnt+1)&0x03; // Use only every fourth sample
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if (dec_cnt>0) return true;
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rx_cnt = (rx_cnt+1)&0x03; // Calculate only every fourth sample
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if (rx_cnt>0) return true;
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for (i=0; i<14; i++) // Shift samples
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for (i=0; i<14; i++) // Shift decimated samples
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{
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q_s[i] = q_s[i+1];
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i_s[i] = i_s[i+1];
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}
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q_accu = 0;
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q_accu = 0; // Initialize accumulator
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i_accu = 0;
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for (i=0; i<15; i++) // Low pass FIR filter
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{
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@ -148,6 +162,11 @@ bool rx(void)
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q_s[14] = q_accu >> 8;
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i_s[14] = q_accu >> 8;
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/*
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* From here things get dependent on receive mode.
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* We assume USB for now, e.g. supporting FT8
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*/
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/*
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* Classic Hilbert transform 15 taps, 12 bits (see Iowa Hills)
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*/
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@ -158,26 +177,26 @@ bool rx(void)
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* SSB demodulate: I[7] - Qh
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* Add DAC_BIAS offset, Clip to DAC_RANGE and send to audio DAC output
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*/
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q_sample = ((i_s[7] - qh)/8)+DAC_BIAS;
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q_sample = ((i_s[7] - qh)/2)+DAC_BIAS;
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q_sample = (q_sample>DAC_RANGE)?DAC_RANGE:((q_sample<0)?0:q_sample);
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pwm_set_chan_level(dac_audio, PWM_CHAN_A, q_sample);
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/* AGC ALGORITHM
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if(m_Peak>m_AttackAve) //if power is rising (use m_AttackRiseAlpha time constant)
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if(m_Peak>m_AttackAve) //if power is rising (use m_AttackRiseAlpha time constant)
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m_AttackAve = (1.0-m_AttackRiseAlpha)*m_AttackAve + m_AttackRiseAlpha*m_Peak;
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else //else magnitude is falling (use m_AttackFallAlpha time constant)
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else //else magnitude is falling (use m_AttackFallAlpha time constant)
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m_AttackAve = (1.0-m_AttackFallAlpha)*m_AttackAve + m_AttackFallAlpha*m_Peak;
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if(m_Peak>m_DecayAve) //if magnitude is rising (use m_DecayRiseAlpha time constant)
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if(m_Peak>m_DecayAve) //if magnitude is rising (use m_DecayRiseAlpha time constant)
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{
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m_DecayAve = (1.0-m_DecayRiseAlpha)*m_DecayAve + m_DecayRiseAlpha*m_Peak;
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m_HangTimer = 0; //reset hang timer
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m_HangTimer = 0; //reset hang timer
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}
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else
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{ //here if decreasing signal
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{ //here if decreasing signal
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if(m_HangTimer<m_HangTime)
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m_HangTimer++; //just inc and hold current m_DecayAve
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else //else decay with m_DecayFallAlpha which is RELEASE_TIMECONST
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m_HangTimer++; //just inc and hold current m_DecayAve
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else //else decay with m_DecayFallAlpha which is RELEASE_TIMECONST
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m_DecayAve = (1.0-m_DecayFallAlpha)*m_DecayAve + m_DecayFallAlpha*m_Peak;
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}
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*/
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@ -189,55 +208,58 @@ else //else decay with m_DecayFallAlpha which is RELEASE_TIM
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* CORE1:
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* Execute TX branch signal processing
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*/
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volatile int16_t a_s_pre[15]; // Raw samples, minus DC bias
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volatile int16_t a_s_raw[15]; // Raw samples, minus DC bias
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volatile int16_t a_s[15]; // Filtered and decimated samples
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volatile int16_t a_dc; // DC level
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volatile int tx_cnt=0; // Decimation counter
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bool tx(void)
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{
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static int tx_phase = 0;
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int16_t sample;
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int32_t accu;
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int16_t a_sample;
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int32_t a_accu;
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int16_t qh;
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int i;
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/*
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* Get sample and shift into delay line
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*/
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adc_select_input(2); // Audio channel ADC
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a_sample = adc_result[2]; // Take last ADC 0 result
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for (i=0; i<14; i++)
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a_s_pre[i] = a_s_pre[i+1]; // Audio samples delay line
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a_s_pre[14] = (int16_t)adc_read()-ADC_RANGE/2; // Subtract half range (is appr. dc bias)
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tx_phase = (tx_phase+1)&0x01; // Count to 2
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if (tx_phase != 0) //
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return true; // early bail out 1 out of 2 times
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/*
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* Downsample and low pass
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*/
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for (i=0; i<14; i++) // Shift decimated samples
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a_s[i] = a_s[i+1];
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accu = 0;
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for (i=0; i<15; i++) // Low pass FIR filter
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accu += (int32_t)a_s_pre[i]*lpf3_62[i]; // 3kHz, at 62.5 kHz sampling
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a_s[14] = accu / 256;
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a_s_raw[i] = a_s_raw[i+1]; // Audio raw samples shift register
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/*
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* Remove DC and store new sample
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* w(t) = x(t) + a*w(t-1) (use a=31/32, ca 0.97)
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* y(t) = w(t) - w(t-1)
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* IIR filter: dc = a*sample + (1-a)*dc where a = 1/128
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*/
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a_sample = (a_sample&0x0fff) - ADC_BIAS; // Clip and subtract mid-range
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a_dc = (a_sample>>7) + a_dc - (a_dc>>7); // then IIR running average
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a_s_raw[14] = a_sample - a_dc; // and subtract DC, store in shift register
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/*
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* Low pass filter + decimation
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*/
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tx_cnt = (tx_cnt+1)&0x03; // Calculate only every fourth sample
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if (tx_cnt>0) return true;
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for (i=0; i<14; i++) // Shift decimated samples
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a_s[i] = a_s[i+1];
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a_accu = 0; // Initialize accumulator
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for (i=0; i<15; i++) // Low pass FIR filter
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a_accu += (int32_t)a_s_raw[i]*lpf3_62[i]; // Fc=3kHz, at 62.5 kHz sampling
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a_s[14] = a_accu >> 8;
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/*
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* From here things get dependent on transmit mode.
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* We assume USB for now, e.g. supporting FT8
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*/
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//temp = a_dc; // a_dc is w(t-1)
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//sample += (int16_t)(((temp<<5)-temp)>>5); // Use sample as w(t)
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//a_s[14] = sample - a_dc; // Calculate output
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//a_dc = sample; // Store new w(t)
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/*
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* Classic Hilbert transform 15 taps, 12 bits (see Iowa Hills):
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*/
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accu = (a_s[0]-a_s[14])*315L + (a_s[2]-a_s[12])*440L + (a_s[4]-a_s[10])*734L + (a_s[6]-a_s[ 8])*2202L;
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qh = accu / 4096;
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a_accu = (a_s[0]-a_s[14])*315L + (a_s[2]-a_s[12])*440L + (a_s[4]-a_s[10])*734L + (a_s[6]-a_s[ 8])*2202L;
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qh = a_accu / 4096;
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/*
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* Write I and Q to QSE DACs, phase is 7 back.
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@ -257,43 +279,11 @@ bool tx(void)
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void dsp_loop()
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{
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uint32_t cmd;
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while(1)
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{
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cmd = multicore_fifo_pop_blocking(); // Wait for fifo output
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if (cmd == DSP_TX) // Change to switch(cmd) when more commands added
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tx();
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else
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rx();
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}
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}
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/*
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* CORE0:
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* Timer callback, triggers core1 through inter-core fifo.
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* Either TX or RX, but could do both when testing in loopback on I+Q channels.
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*/
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struct repeating_timer dsp_timer;
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bool dsp_callback(struct repeating_timer *t)
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{
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if (tx_enabled)
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multicore_fifo_push_blocking(DSP_TX); // Write TX in fifo to core 1
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else
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multicore_fifo_push_blocking(DSP_RX); // Write RX in fifo to core 1
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return true;
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}
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/*
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* CORE0:
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* Initialize dsp context and spawn core1 process
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*/
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void dsp_init()
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{
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uint16_t slice_num;
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tx_enabled = false;
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fifo_overrun = 0;
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/* Initialize DACs */
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gpio_set_function(20, GPIO_FUNC_PWM); // GP20 is PWM for I DAC (Slice 2, Channel A)
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gpio_set_function(21, GPIO_FUNC_PWM); // GP21 is PWM for Q DAC (Slice 2, Channel B)
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@ -309,14 +299,54 @@ void dsp_init()
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pwm_set_enabled(dac_audio, true); // Set the PWM running
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/* Initialize ADCs */
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adc_init();
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adc_init(); // Initialize ADC to known state
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adc_set_clkdiv(0); // Fastest clock (500 kSps)
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adc_gpio_init(26); // GP26 is ADC 0 for I channel
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adc_gpio_init(27); // GP27 is ADC 1 for Q channel
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adc_gpio_init(28); // GP28 is ADC 2 for Audio channel
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adc_select_input(0); // Select ADC 0
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adc_select_input(0); // Start with ADC0
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adc_next = 0;
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adc_set_round_robin(1+2+4); // Sequence ADC 0-1-2 free running
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adc_fifo_setup(true,false,1,false,false); // IRQ for everty result (threshold = 1)
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irq_set_exclusive_handler(ADC0_IRQ_FIFO, adcfifo_handler);
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adc_irq_set_enabled(true);
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irq_set_enabled(ADC0_IRQ_FIFO, true);
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adc_run(true);
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while(1)
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{
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if (multicore_fifo_rvalid()) fifo_overrun++;// Check for missed events
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cmd = multicore_fifo_pop_blocking(); // Wait for fifo output
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if (cmd == DSP_RX) rx();
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if (cmd == DSP_TX) tx();
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}
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}
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tx_enabled = false; // RX mode
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/*
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* CORE0:
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* Timer callback, triggers core1 through inter-core fifo.
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* Either TX or RX, but could do both when testing in loopback on I+Q channels.
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*/
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struct repeating_timer dsp_timer;
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bool dsp_callback(struct repeating_timer *t)
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{
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if (tx_enabled)
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multicore_fifo_push_blocking(DSP_TX); // Send TX to core 1 through fifo
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else
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multicore_fifo_push_blocking(DSP_RX); // Send RX to core 1 through fifo
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return true;
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}
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/*
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* CORE0:
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* Initialize dsp context and spawn core1 process
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*/
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void dsp_init()
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{
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multicore_launch_core1(dsp_loop); // Start processing on core1
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add_repeating_timer_us(-DSP_US, dsp_callback, NULL, &dsp_timer);
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}
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37
hmi.c
37
hmi.c
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@ -110,6 +110,13 @@ uint32_t hmi_step[6] = {10000000, 1000000, 100000, 10000, 1000, 100}; // Frequen
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#define HMI_MAXFREQ 30000000
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#define HMI_MINFREQ 100
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#ifndef MIN
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#define MIN(x, y) ((x)<(y)?(x):(y)) // Get min value
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#endif
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#ifndef MAX
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#define MAX(x, y) ((x)>(y)?(x):(y)) // Get max value
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#endif
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/*
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* Finite State Machine,
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* Handle event according to current state
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@ -120,9 +127,9 @@ void hmi_handler(uint8_t event)
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{
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case HMI_S_MENU:
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if ((event==HMI_E_INCREMENT)||(event==HMI_E_RIGHT))
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hmi_option = (hmi_option<HMI_NSTATES-1)?hmi_option+1:1;
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hmi_option = (hmi_option<HMI_NSTATES-1)?hmi_option+1:HMI_NSTATES-1;
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if ((event==HMI_E_DECREMENT)||(event==HMI_E_LEFT))
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hmi_option = (hmi_option>1)?hmi_option-1:HMI_NSTATES-1;
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hmi_option = (hmi_option>1)?hmi_option-1:0;
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if (event==HMI_E_ENTER)
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{
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hmi_state = hmi_option; // Enter new submenu
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@ -143,18 +150,15 @@ void hmi_handler(uint8_t event)
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}
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if (event==HMI_E_INCREMENT)
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{
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hmi_freq += hmi_step[hmi_option];
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if (hmi_freq > HMI_MAXFREQ) hmi_freq = HMI_MAXFREQ;
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hmi_freq+= hmi_step[hmi_option];
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hmi_freq = MIN(hmi_freq , HMI_MAXFREQ);
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}
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if (event==HMI_E_DECREMENT)
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{
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hmi_freq -= hmi_step[hmi_option];
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if (hmi_freq < HMI_MINFREQ) hmi_freq = HMI_MINFREQ;
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}
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hmi_freq = (hmi_freq>hmi_step[hmi_option]+HMI_MINFREQ)?hmi_freq-hmi_step[hmi_option]:HMI_MINFREQ;
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||||
if (event==HMI_E_RIGHT)
|
||||
hmi_option = (hmi_option<6)?hmi_option+1:0;
|
||||
hmi_option = (hmi_option<6)?hmi_option+1:6;
|
||||
if (event==HMI_E_LEFT)
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:6;
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:0;
|
||||
break;
|
||||
case HMI_S_MODE:
|
||||
if (event==HMI_E_ENTER)
|
||||
|
|
@ -170,9 +174,9 @@ void hmi_handler(uint8_t event)
|
|||
hmi_state = HMI_S_MENU; // Leave submenu
|
||||
}
|
||||
if ((event==HMI_E_INCREMENT)||(event==HMI_E_RIGHT))
|
||||
hmi_option = (hmi_option<HMI_NMODE-1)?hmi_option+1:0;
|
||||
hmi_option = (hmi_option<HMI_NMODE-1)?hmi_option+1:HMI_NMODE-1;
|
||||
if ((event==HMI_E_DECREMENT)||(event==HMI_E_LEFT))
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:HMI_NMODE-1;
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:0;
|
||||
break;
|
||||
case HMI_S_AGC:
|
||||
if (event==HMI_E_ENTER)
|
||||
|
|
@ -188,9 +192,9 @@ void hmi_handler(uint8_t event)
|
|||
hmi_state = HMI_S_MENU; // Leave submenu
|
||||
}
|
||||
if ((event==HMI_E_INCREMENT)||(event==HMI_E_RIGHT))
|
||||
hmi_option = (hmi_option<HMI_NAGC-1)?hmi_option+1:0;
|
||||
hmi_option = (hmi_option<HMI_NAGC-1)?hmi_option+1:HMI_NAGC-1;
|
||||
if ((event==HMI_E_DECREMENT)||(event==HMI_E_LEFT))
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:HMI_NAGC-1;
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:0;
|
||||
break;
|
||||
case HMI_S_PRE:
|
||||
if (event==HMI_E_ENTER)
|
||||
|
|
@ -206,9 +210,9 @@ void hmi_handler(uint8_t event)
|
|||
hmi_state = HMI_S_MENU; // Leave submenu
|
||||
}
|
||||
if ((event==HMI_E_INCREMENT)||(event==HMI_E_RIGHT))
|
||||
hmi_option = (hmi_option<HMI_NPRE-1)?hmi_option+1:0;
|
||||
hmi_option = (hmi_option<HMI_NPRE-1)?hmi_option+1:HMI_NPRE-1;
|
||||
if ((event==HMI_E_DECREMENT)||(event==HMI_E_LEFT))
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:HMI_NPRE-1;
|
||||
hmi_option = (hmi_option>0)?hmi_option-1:0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -337,5 +341,6 @@ void hmi_evaluate(void)
|
|||
default:
|
||||
break;
|
||||
}
|
||||
SI_SETFREQ(0, 2*hmi_freq); // Set freq to latest
|
||||
}
|
||||
|
||||
|
|
|
|||
12
monitor.c
12
monitor.c
|
|
@ -28,12 +28,13 @@ char mon_cmd[CMD_LEN+1];
|
|||
|
||||
uint8_t si5351_reg[200];
|
||||
bool ptt = false;
|
||||
|
||||
extern volatile uint32_t fifo_overrun;
|
||||
extern uint32_t adc_count;
|
||||
|
||||
/* Commandstring parser */
|
||||
char delim[] = " ";
|
||||
#define NCMD 4
|
||||
char shell[NCMD][3] = {"si", "lt", "fb", "pt"};
|
||||
#define NCMD 5
|
||||
char shell[NCMD][3] = {"si", "lt", "fo", "pt", "ad"};
|
||||
void mon_parse(char* s)
|
||||
{
|
||||
char *p;
|
||||
|
|
@ -56,7 +57,7 @@ void mon_parse(char* s)
|
|||
lcd_test();
|
||||
break;
|
||||
case 2:
|
||||
printf("%s\n", p);
|
||||
printf("Fifo overruns: %lu\n", fifo_overrun);
|
||||
break;
|
||||
case 3:
|
||||
if (ptt)
|
||||
|
|
@ -71,6 +72,9 @@ void mon_parse(char* s)
|
|||
}
|
||||
dsp_ptt(ptt);
|
||||
break;
|
||||
case 4:
|
||||
printf("ADC IRQ count: %lu\n", adc_count);
|
||||
break;
|
||||
default:
|
||||
printf("??\n");
|
||||
break;
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue