Rob Riggs
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6420bd4f58
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Add StdDev/SNR calc for debug.
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2020-04-14 21:02:15 -05:00 |
Rob Riggs
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a78c3df323
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Loosen DCD requirement for decode.
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2020-03-05 20:30:13 -06:00 |
Rob Riggs
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5503b329e8
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Add passall setter. Move battery level code to demodulators because they own the ADC.
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2020-02-23 15:58:08 -06:00 |
Rob Riggs
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79f145ccd9
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Fix AFSK modem after FSK changes. Revert changes to DigitalPLL. Remove intrusive diagnostics in AudioInput, along with dead code. Clean up FIR filter code. Add initial passall support. Disable LSCO when transmitting in debug mode. Set fixed mid-range DAC output in FSK modulator when not transmitting to eliminate DC offset. New way to compute IDLE bytes for TX Delay. Clean up HDLC decoder, improve HDLC diagnostics, add Passall support. Add new extended response types for modem support. Update API version to 0x0201. Update firmware version to 2.0.0b1.
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2020-02-22 19:35:11 -06:00 |
Rob Riggs
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4e218d36e9
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Add new HDLC decoder.
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2019-06-08 22:49:16 -05:00 |
Rob Riggs
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0eb70c4746
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Fix timing behavior and a potential null pointer derefernce in the serial port driver. Fix an off-by-one error that caused short packets to be discarded. Update version to 1.1.1.
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2019-01-31 18:01:27 -06:00 |
Rob Riggs
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e2bc1bc488
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Add debug logging to the pool allocator.
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2018-09-21 21:06:06 -05:00 |
Rob Riggs
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b98e6c1c2c
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Commit bulk of code for new project. Still some cleanup to do to make it work with new PCB.
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2018-08-26 22:28:24 -05:00 |