kopia lustrzana https://github.com/stlink-org/stlink
1904 wiersze
68 KiB
C
1904 wiersze
68 KiB
C
/*
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* Copyright (C) 2011 Peter Zotov <whitequark@whitequark.org>
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* Use of this source code is governed by a BSD-style
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* license that can be found in the LICENSE file.
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*/
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#include <ctype.h>
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#include <getopt.h>
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#include <signal.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <sys/types.h>
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#if defined(_MSC_VER)
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#include <stdbool.h>
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#define __attribute__(x)
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#endif
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#if defined(_WIN32)
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#include <mingw.h>
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#else
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#include <unistd.h>
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#include <sys/socket.h>
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#include <netinet/in.h>
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#include <arpa/inet.h>
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#endif
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#include <stlink.h>
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#include <stlink/logging.h>
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#include "gdb-remote.h"
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#include "gdb-server.h"
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#include "semihosting.h"
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#define FLASH_BASE 0x08000000
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/* Semihosting doesn't have a short option, we define a value to identify it */
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#define SEMIHOSTING_OPTION 128
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#define SERIAL_OPTION 127
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//Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize
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#define FLASH_PAGE (sl->flash_pgsz)
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static stlink_t *connected_stlink = NULL;
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static bool semihosting = false;
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static bool serial_specified = false;
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static char serialnumber[28] = {0};
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#if defined(_WIN32)
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#define close_socket win32_close_socket
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#define IS_SOCK_VALID(__sock) ((__sock) != INVALID_SOCKET)
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#else
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#define close_socket close
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#define SOCKET int
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#define IS_SOCK_VALID(__sock) ((__sock) > 0)
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#endif
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static const char hex[] = "0123456789abcdef";
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static const char* current_memory_map = NULL;
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typedef struct _st_state_t {
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// things from command line, bleh
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int stlink_version;
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int logging_level;
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int listen_port;
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int persistent;
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int reset;
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} st_state_t;
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int serve(stlink_t *sl, st_state_t *st);
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char* make_memory_map(stlink_t *sl);
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static void init_cache (stlink_t *sl);
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static void cleanup(int signum) {
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(void)signum;
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if (connected_stlink) {
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/* Switch back to mass storage mode before closing. */
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stlink_run(connected_stlink);
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stlink_exit_debug_mode(connected_stlink);
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stlink_close(connected_stlink);
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}
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exit(1);
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}
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static stlink_t* do_connect(st_state_t *st) {
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stlink_t *ret = NULL;
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switch (st->stlink_version) {
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case 2:
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if (serial_specified){
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ret = stlink_open_usb(st->logging_level, st->reset, serialnumber);
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}
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else {
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ret = stlink_open_usb(st->logging_level, st->reset, NULL);
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}
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break;
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case 1:
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ret = stlink_v1_open(st->logging_level, st->reset);
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break;
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}
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return ret;
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}
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int parse_options(int argc, char** argv, st_state_t *st) {
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static struct option long_options[] = {
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{"help", no_argument, NULL, 'h'},
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{"verbose", optional_argument, NULL, 'v'},
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{"stlink_version", required_argument, NULL, 's'},
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{"stlinkv1", no_argument, NULL, '1'},
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{"listen_port", required_argument, NULL, 'p'},
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{"multi", optional_argument, NULL, 'm'},
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{"no-reset", optional_argument, NULL, 'n'},
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{"version", no_argument, NULL, 'V'},
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{"semihosting", no_argument, NULL, SEMIHOSTING_OPTION},
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{"serial", required_argument, NULL, SERIAL_OPTION},
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{0, 0, 0, 0},
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};
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const char * help_str = "%s - usage:\n\n"
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" -h, --help\t\tPrint this help\n"
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" -V, --version\t\tPrint the version\n"
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" -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n"
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" -v, --verbose\t\tSpecify generally verbose logging\n"
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" -s X, --stlink_version=X\n"
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"\t\t\tChoose what version of stlink to use, (defaults to 2)\n"
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" -1, --stlinkv1\tForce stlink version 1\n"
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" -p 4242, --listen_port=1234\n"
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"\t\t\tSet the gdb server listen port. "
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"(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n"
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" -m, --multi\n"
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"\t\t\tSet gdb server to extended mode.\n"
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"\t\t\tst-util will continue listening for connections after disconnect.\n"
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" -n, --no-reset\n"
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"\t\t\tDo not reset board on connection.\n"
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" --semihosting\n"
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"\t\t\tEnable semihosting support.\n"
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" --serial <serial>\n"
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"\t\t\tUse a specific serial number.\n"
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"\n"
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"The STLINKv2 device to use can be specified in the environment\n"
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"variable STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.\n"
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"\n"
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;
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int option_index = 0;
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int c;
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int q;
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while ((c = getopt_long(argc, argv, "hv::s:1p:mn", long_options, &option_index)) != -1) {
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switch (c) {
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case 0:
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break;
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case 'h':
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printf(help_str, argv[0]);
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exit(EXIT_SUCCESS);
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break;
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case 'v':
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if (optarg) {
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st->logging_level = atoi(optarg);
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} else {
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st->logging_level = DEBUG_LOGGING_LEVEL;
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}
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break;
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case '1':
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st->stlink_version = 1;
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break;
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case 's':
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sscanf(optarg, "%i", &q);
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if (q < 0 || q > 2) {
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fprintf(stderr, "stlink version %d unknown!\n", q);
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exit(EXIT_FAILURE);
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}
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st->stlink_version = q;
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break;
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case 'p':
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sscanf(optarg, "%i", &q);
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if (q < 0) {
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fprintf(stderr, "Can't use a negative port to listen on: %d\n", q);
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exit(EXIT_FAILURE);
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}
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st->listen_port = q;
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break;
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case 'm':
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st->persistent = 1;
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break;
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case 'n':
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st->reset = 0;
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break;
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case 'V':
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printf("v%s\n", STLINK_VERSION);
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exit(EXIT_SUCCESS);
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case SEMIHOSTING_OPTION:
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semihosting = true;
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break;
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case SERIAL_OPTION:
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printf("use serial %s\n",optarg);
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/** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */
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int j = (int)strlen(optarg);
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int length = j / 2; //the length of the destination-array
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if (j % 2 != 0) return -1;
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for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) {
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char buffer[3] = {0};
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memcpy(buffer, optarg + j, 2);
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serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16);
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}
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serial_specified = true;
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break;
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}
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}
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if (optind < argc) {
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printf("non-option ARGV-elements: ");
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while (optind < argc)
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printf("%s ", argv[optind++]);
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printf("\n");
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}
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return 0;
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}
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int main(int argc, char** argv) {
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stlink_t *sl = NULL;
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st_state_t state;
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memset(&state, 0, sizeof(state));
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// set defaults...
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state.stlink_version = 2;
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state.logging_level = DEFAULT_LOGGING_LEVEL;
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state.listen_port = DEFAULT_GDB_LISTEN_PORT;
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state.reset = 1; /* By default, reset board */
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parse_options(argc, argv, &state);
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printf("st-util %s\n", STLINK_VERSION);
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sl = do_connect(&state);
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if (sl == NULL) return 1;
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connected_stlink = sl;
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signal(SIGINT, &cleanup);
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signal(SIGTERM, &cleanup);
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signal(SIGSEGV, &cleanup);
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if (state.reset) {
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stlink_reset(sl);
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}
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// This is low-level information for debugging, not useful for normal use.
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// So: Demoted to a debug meesage. -- REW
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DLOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id);
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sl->verbose=0;
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current_memory_map = make_memory_map(sl);
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#if defined(__MINGW32__) || defined(_MSC_VER)
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WSADATA wsadata;
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if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0){
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goto winsock_error;
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}
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#endif
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init_cache(sl);
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do {
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if (serve(sl, &state)) {
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usleep (1 * 1000); // don't go bezurk if serve returns with error
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}
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/* in case serve() changed the connection */
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sl = connected_stlink;
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/* Continue */
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stlink_run(sl);
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} while (state.persistent);
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#if defined(__MINGW32__) || defined(_MSC_VER)
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winsock_error:
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WSACleanup();
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#endif
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/* Switch back to mass storage mode before closing. */
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stlink_exit_debug_mode(sl);
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stlink_close(sl);
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return 0;
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}
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static const char* const target_description_F4 =
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"<?xml version=\"1.0\"?>"
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"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
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"<target version=\"1.0\">"
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" <architecture>arm</architecture>"
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" <feature name=\"org.gnu.gdb.arm.m-profile\">"
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" <reg name=\"r0\" bitsize=\"32\"/>"
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" <reg name=\"r1\" bitsize=\"32\"/>"
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" <reg name=\"r2\" bitsize=\"32\"/>"
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" <reg name=\"r3\" bitsize=\"32\"/>"
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" <reg name=\"r4\" bitsize=\"32\"/>"
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" <reg name=\"r5\" bitsize=\"32\"/>"
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" <reg name=\"r6\" bitsize=\"32\"/>"
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" <reg name=\"r7\" bitsize=\"32\"/>"
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" <reg name=\"r8\" bitsize=\"32\"/>"
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" <reg name=\"r9\" bitsize=\"32\"/>"
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" <reg name=\"r10\" bitsize=\"32\"/>"
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" <reg name=\"r11\" bitsize=\"32\"/>"
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" <reg name=\"r12\" bitsize=\"32\"/>"
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" <reg name=\"sp\" bitsize=\"32\" type=\"data_ptr\"/>"
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" <reg name=\"lr\" bitsize=\"32\"/>"
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" <reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\"/>"
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" <reg name=\"xpsr\" bitsize=\"32\" regnum=\"25\"/>"
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" <reg name=\"msp\" bitsize=\"32\" regnum=\"26\" type=\"data_ptr\" group=\"general\" />"
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" <reg name=\"psp\" bitsize=\"32\" regnum=\"27\" type=\"data_ptr\" group=\"general\" />"
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" <reg name=\"control\" bitsize=\"8\" regnum=\"28\" type=\"int\" group=\"general\" />"
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" <reg name=\"faultmask\" bitsize=\"8\" regnum=\"29\" type=\"int\" group=\"general\" />"
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" <reg name=\"basepri\" bitsize=\"8\" regnum=\"30\" type=\"int\" group=\"general\" />"
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" <reg name=\"primask\" bitsize=\"8\" regnum=\"31\" type=\"int\" group=\"general\" />"
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" <reg name=\"s0\" bitsize=\"32\" regnum=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s1\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s2\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s3\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s4\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s5\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s6\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s7\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s8\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s9\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s10\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s11\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s12\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s13\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s14\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s15\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s16\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s17\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s18\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s19\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s20\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s21\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s22\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s23\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s24\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s25\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s26\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s27\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s28\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s29\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s30\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"s31\" bitsize=\"32\" type=\"float\" group=\"float\" />"
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" <reg name=\"fpscr\" bitsize=\"32\" type=\"int\" group=\"float\" />"
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" </feature>"
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"</target>";
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static const char* const memory_map_template_F4 =
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"<?xml version=\"1.0\"?>"
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"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
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"<memory-map>"
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" <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
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" <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x20000\"/>" // sram
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" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
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" <property name=\"blocksize\">0x4000</property>" //16kB
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" </memory>"
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" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
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" <property name=\"blocksize\">0x10000</property>" //64kB
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" </memory>"
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" <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" //Sectors 5..11
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" <property name=\"blocksize\">0x20000</property>" //128kB
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" </memory>"
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" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
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" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
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" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
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" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
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" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
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"</memory-map>";
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static const char* const memory_map_template_F4_HD =
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"<?xml version=\"1.0\"?>"
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"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
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"<memory-map>"
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" <memory type=\"rom\" start=\"0x00000000\" length=\"0x100000\"/>" // code = sram, bootrom or flash; flash is bigger
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" <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // ccm ram
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x40000\"/>" // sram
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" <memory type=\"ram\" start=\"0x60000000\" length=\"0x10000000\"/>" // fmc bank 1 (nor/psram/sram)
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" <memory type=\"ram\" start=\"0x70000000\" length=\"0x20000000\"/>" // fmc bank 2 & 3 (nand flash)
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" <memory type=\"ram\" start=\"0x90000000\" length=\"0x10000000\"/>" // fmc bank 4 (pc card)
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" <memory type=\"ram\" start=\"0xC0000000\" length=\"0x20000000\"/>" // fmc sdram bank 1 & 2
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" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
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" <property name=\"blocksize\">0x4000</property>" //16kB
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" </memory>"
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" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
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" <property name=\"blocksize\">0x10000</property>" //64kB
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" </memory>"
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" <memory type=\"flash\" start=\"0x08020000\" length=\"0xE0000\">" //Sectors 5..11
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" <property name=\"blocksize\">0x20000</property>" //128kB
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" </memory>"
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" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
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" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
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" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
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" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
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"</memory-map>";
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static const char* const memory_map_template_F2 =
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"<?xml version=\"1.0\"?>"
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"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
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" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
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"<memory-map>"
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" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
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" <memory type=\"ram\" start=\"0x20000000\" length=\"0x%x\"/>" // sram
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" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
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" <property name=\"blocksize\">0x4000</property>" //16kB
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" </memory>"
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" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
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" <property name=\"blocksize\">0x10000</property>" //64kB
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" </memory>"
|
|
" <memory type=\"flash\" start=\"0x08020000\" length=\"0x%x\">" //Sectors 5..
|
|
" <property name=\"blocksize\">0x20000</property>" //128kB
|
|
" </memory>"
|
|
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
|
|
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
|
|
" <memory type=\"rom\" start=\"0x%08x\" length=\"0x%x\"/>" // bootrom
|
|
" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
|
|
"</memory-map>";
|
|
|
|
static const char* const memory_map_template_L4 =
|
|
"<?xml version=\"1.0\"?>"
|
|
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
|
|
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
|
|
"<memory-map>"
|
|
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
|
|
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x8000\"/>" // SRAM2 (32 KB)
|
|
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x18000\"/>" // SRAM1 (96 KB)
|
|
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
|
|
" <property name=\"blocksize\">0x800</property>"
|
|
" </memory>"
|
|
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
|
|
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
|
|
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
|
|
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7000\"/>" // bootrom
|
|
" <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x10\"/>" // option byte area
|
|
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
|
|
"</memory-map>";
|
|
|
|
static const char* const memory_map_template_L496 =
|
|
"<?xml version=\"1.0\"?>"
|
|
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
|
|
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
|
|
"<memory-map>"
|
|
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
|
|
" <memory type=\"ram\" start=\"0x10000000\" length=\"0x10000\"/>" // SRAM2 (64 KB)
|
|
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x50000\"/>" // SRAM1 + aliased SRAM2 (256+64=320 KB)
|
|
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
|
|
" <property name=\"blocksize\">0x800</property>"
|
|
" </memory>"
|
|
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
|
|
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
|
|
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
|
|
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7000\"/>" // bootrom
|
|
" <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x10\"/>" // option byte area
|
|
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
|
|
"</memory-map>";
|
|
|
|
static const char* const memory_map_template =
|
|
"<?xml version=\"1.0\"?>"
|
|
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
|
|
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
|
|
"<memory-map>"
|
|
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x%x\"/>" // code = sram, bootrom or flash; flash is bigger
|
|
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x%x\"/>" // sram 8k
|
|
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x%x\">"
|
|
" <property name=\"blocksize\">0x%x</property>"
|
|
" </memory>"
|
|
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
|
|
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
|
|
" <memory type=\"rom\" start=\"0x%08x\" length=\"0x%x\"/>" // bootrom
|
|
" <memory type=\"rom\" start=\"0x1ffff800\" length=\"0x10\"/>" // option byte area
|
|
"</memory-map>";
|
|
|
|
static const char* const memory_map_template_F7 =
|
|
"<?xml version=\"1.0\"?>"
|
|
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
|
|
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
|
|
"<memory-map>"
|
|
" <memory type=\"ram\" start=\"0x00000000\" length=\"0x4000\"/>" // ITCM ram 16kB
|
|
" <memory type=\"rom\" start=\"0x00200000\" length=\"0x100000\"/>" // ITCM flash
|
|
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x%x\"/>" // sram
|
|
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x20000\">" // Sectors 0..3
|
|
" <property name=\"blocksize\">0x8000</property>" // 32kB
|
|
" </memory>"
|
|
" <memory type=\"flash\" start=\"0x08020000\" length=\"0x20000\">" // Sector 4
|
|
" <property name=\"blocksize\">0x20000</property>" // 128kB
|
|
" </memory>"
|
|
" <memory type=\"flash\" start=\"0x08040000\" length=\"0xC0000\">" // Sectors 5..7
|
|
" <property name=\"blocksize\">0x40000</property>" // 128kB
|
|
" </memory>"
|
|
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
|
|
" <memory type=\"ram\" start=\"0x60000000\" length=\"0x7fffffff\"/>" // AHB3 Peripherals
|
|
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
|
|
" <memory type=\"rom\" start=\"0x00100000\" length=\"0xEDC0\"/>" // bootrom
|
|
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x20\"/>" // option byte area
|
|
"</memory-map>";
|
|
|
|
|
|
static const char* const memory_map_template_F4_DE =
|
|
"<?xml version=\"1.0\"?>"
|
|
"<!DOCTYPE memory-map PUBLIC \"+//IDN gnu.org//DTD GDB Memory Map V1.0//EN\""
|
|
" \"http://sourceware.org/gdb/gdb-memory-map.dtd\">"
|
|
"<memory-map>"
|
|
" <memory type=\"rom\" start=\"0x00000000\" length=\"0x80000\"/>" // code = sram, bootrom or flash; flash is bigger
|
|
" <memory type=\"ram\" start=\"0x20000000\" length=\"0x18000\"/>" // sram
|
|
" <memory type=\"flash\" start=\"0x08000000\" length=\"0x10000\">" //Sectors 0..3
|
|
" <property name=\"blocksize\">0x4000</property>" //16kB
|
|
" </memory>"
|
|
" <memory type=\"flash\" start=\"0x08010000\" length=\"0x10000\">" //Sector 4
|
|
" <property name=\"blocksize\">0x10000</property>" //64kB
|
|
" </memory>"
|
|
" <memory type=\"flash\" start=\"0x08020000\" length=\"0x60000\">" //Sectors 5..7
|
|
" <property name=\"blocksize\">0x20000</property>" //128kB
|
|
" </memory>"
|
|
" <memory type=\"ram\" start=\"0x40000000\" length=\"0x1fffffff\"/>" // peripheral regs
|
|
" <memory type=\"ram\" start=\"0xe0000000\" length=\"0x1fffffff\"/>" // cortex regs
|
|
" <memory type=\"rom\" start=\"0x1fff0000\" length=\"0x7800\"/>" // bootrom
|
|
" <memory type=\"rom\" start=\"0x1fff7800\" length=\"0x210\"/>" // otp
|
|
" <memory type=\"rom\" start=\"0x1fffc000\" length=\"0x10\"/>" // option byte area
|
|
"</memory-map>";
|
|
|
|
char* make_memory_map(stlink_t *sl) {
|
|
/* This will be freed in serve() */
|
|
const size_t sz = 4096;
|
|
char* map = malloc(sz);
|
|
map[0] = '\0';
|
|
|
|
if (sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446 || sl->chip_id==STLINK_CHIPID_STM32_F411RE) {
|
|
strcpy(map, memory_map_template_F4);
|
|
} else if (sl->chip_id==STLINK_CHIPID_STM32_F4_DE) {
|
|
strcpy(map, memory_map_template_F4_DE);
|
|
} else if (sl->core_id==STM32F7_CORE_ID) {
|
|
snprintf(map, sz, memory_map_template_F7,
|
|
(unsigned int)sl->sram_size);
|
|
} else if (sl->chip_id==STLINK_CHIPID_STM32_F4_HD) {
|
|
strcpy(map, memory_map_template_F4_HD);
|
|
} else if (sl->chip_id==STLINK_CHIPID_STM32_F2) {
|
|
snprintf(map, sz, memory_map_template_F2,
|
|
(unsigned int)sl->flash_size,
|
|
(unsigned int)sl->sram_size,
|
|
(unsigned int)sl->flash_size - 0x20000,
|
|
(unsigned int)sl->sys_base, (unsigned int)sl->sys_size);
|
|
} else if ((sl->chip_id==STLINK_CHIPID_STM32_L4) ||
|
|
(sl->chip_id==STLINK_CHIPID_STM32_L43X) ||
|
|
(sl->chip_id==STLINK_CHIPID_STM32_L46X)) {
|
|
snprintf(map, sz, memory_map_template_L4,
|
|
(unsigned int)sl->flash_size, (unsigned int)sl->flash_size);
|
|
} else if (sl->chip_id==STLINK_CHIPID_STM32_L496X) {
|
|
snprintf(map, sz, memory_map_template_L496,
|
|
(unsigned int)sl->flash_size, (unsigned int)sl->flash_size);
|
|
} else {
|
|
snprintf(map, sz, memory_map_template,
|
|
(unsigned int)sl->flash_size,
|
|
(unsigned int)sl->sram_size,
|
|
(unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz,
|
|
(unsigned int)sl->sys_base, (unsigned int)sl->sys_size);
|
|
}
|
|
return map;
|
|
}
|
|
|
|
|
|
/*
|
|
* DWT_COMP0 0xE0001020
|
|
* DWT_MASK0 0xE0001024
|
|
* DWT_FUNCTION0 0xE0001028
|
|
* DWT_COMP1 0xE0001030
|
|
* DWT_MASK1 0xE0001034
|
|
* DWT_FUNCTION1 0xE0001038
|
|
* DWT_COMP2 0xE0001040
|
|
* DWT_MASK2 0xE0001044
|
|
* DWT_FUNCTION2 0xE0001048
|
|
* DWT_COMP3 0xE0001050
|
|
* DWT_MASK3 0xE0001054
|
|
* DWT_FUNCTION3 0xE0001058
|
|
*/
|
|
|
|
#define DATA_WATCH_NUM 4
|
|
|
|
enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 };
|
|
|
|
struct code_hw_watchpoint {
|
|
stm32_addr_t addr;
|
|
uint8_t mask;
|
|
enum watchfun fun;
|
|
};
|
|
|
|
static struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
|
|
|
|
static void init_data_watchpoints(stlink_t *sl) {
|
|
uint32_t data;
|
|
DLOG("init watchpoints\n");
|
|
|
|
stlink_read_debug32(sl, 0xE000EDFC, &data);
|
|
data |= 1<<24;
|
|
// set trcena in debug command to turn on dwt unit
|
|
stlink_write_debug32(sl, 0xE000EDFC, data);
|
|
|
|
// make sure all watchpoints are cleared
|
|
for (int i = 0; i < DATA_WATCH_NUM; i++) {
|
|
data_watches[i].fun = WATCHDISABLED;
|
|
stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
|
|
}
|
|
}
|
|
|
|
static int add_data_watchpoint(stlink_t *sl, enum watchfun wf,
|
|
stm32_addr_t addr, unsigned int len) {
|
|
int i = 0;
|
|
uint32_t mask, dummy;
|
|
|
|
// computer mask
|
|
// find a free watchpoint
|
|
// configure
|
|
|
|
mask = -1;
|
|
i = len;
|
|
while (i) {
|
|
i >>= 1;
|
|
mask++;
|
|
}
|
|
|
|
if ((mask != (uint32_t)-1) && (mask < 16)) {
|
|
for (i = 0; i < DATA_WATCH_NUM; i++) {
|
|
// is this an empty slot ?
|
|
if (data_watches[i].fun == WATCHDISABLED) {
|
|
DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len);
|
|
|
|
data_watches[i].fun = wf;
|
|
data_watches[i].addr = addr;
|
|
data_watches[i].mask = mask;
|
|
|
|
// insert comparator address
|
|
stlink_write_debug32(sl, 0xE0001020 + i * 16, addr);
|
|
|
|
// insert mask
|
|
stlink_write_debug32(sl, 0xE0001024 + i * 16, mask);
|
|
|
|
// insert function
|
|
stlink_write_debug32(sl, 0xE0001028 + i * 16, wf);
|
|
|
|
// just to make sure the matched bit is clear !
|
|
stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy);
|
|
return 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len);
|
|
return -1;
|
|
}
|
|
|
|
static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0 ; i < DATA_WATCH_NUM; i++) {
|
|
if ((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) {
|
|
DLOG("delete watchpoint %d addr %x\n", i, addr);
|
|
|
|
data_watches[i].fun = WATCHDISABLED;
|
|
stlink_write_debug32(sl, 0xe0001028 + i * 16, 0);
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
DLOG("failure: delete watchpoint addr %x\n", addr);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int code_break_num;
|
|
static int code_lit_num;
|
|
#define CODE_BREAK_NUM_MAX 15
|
|
#define CODE_BREAK_LOW 0x01
|
|
#define CODE_BREAK_HIGH 0x02
|
|
|
|
struct code_hw_breakpoint {
|
|
stm32_addr_t addr;
|
|
int type;
|
|
};
|
|
|
|
static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
|
|
|
|
static void init_code_breakpoints(stlink_t *sl) {
|
|
unsigned int val;
|
|
memset(sl->q_buf, 0, 4);
|
|
stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
|
|
stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val);
|
|
code_break_num = ((val >> 4) & 0xf);
|
|
code_lit_num = ((val >> 8) & 0xf);
|
|
|
|
ILOG("Found %i hw breakpoint registers\n", code_break_num);
|
|
|
|
for (int i = 0; i < code_break_num; i++) {
|
|
code_breaks[i].type = 0;
|
|
stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMP0 + i * 4, 0);
|
|
}
|
|
}
|
|
|
|
static int has_breakpoint(stm32_addr_t addr)
|
|
{
|
|
for (int i = 0; i < code_break_num; i++) {
|
|
if (code_breaks[i].addr == addr) {
|
|
return 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) {
|
|
stm32_addr_t fpb_addr;
|
|
uint32_t mask;
|
|
int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW;
|
|
|
|
if (addr & 1) {
|
|
ELOG("update_code_breakpoint: unaligned address %08x\n", addr);
|
|
return -1;
|
|
}
|
|
|
|
if (sl->core_id==STM32F7_CORE_ID) {
|
|
fpb_addr = addr;
|
|
} else {
|
|
fpb_addr = addr & ~0x3;
|
|
}
|
|
|
|
int id = -1;
|
|
for (int i = 0; i < code_break_num; i++) {
|
|
if (fpb_addr == code_breaks[i].addr ||
|
|
(set && code_breaks[i].type == 0)) {
|
|
id = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (id == -1) {
|
|
if (set) return -1; // Free slot not found
|
|
else return 0; // Breakpoint is already removed
|
|
}
|
|
|
|
struct code_hw_breakpoint* bp = &code_breaks[id];
|
|
|
|
bp->addr = fpb_addr;
|
|
|
|
if (sl->core_id==STM32F7_CORE_ID) {
|
|
if (set) bp->type = type;
|
|
else bp->type = 0;
|
|
|
|
mask = (bp->addr) | 1;
|
|
} else {
|
|
if (set) bp->type |= type;
|
|
else bp->type &= ~type;
|
|
|
|
mask = (bp->addr) | 1 | (bp->type << 30);
|
|
}
|
|
|
|
if (bp->type == 0) {
|
|
DLOG("clearing hw break %d\n", id);
|
|
|
|
stlink_write_debug32(sl, 0xe0002008 + id * 4, 0);
|
|
} else {
|
|
DLOG("setting hw break %d at %08x (%d)\n",
|
|
id, bp->addr, bp->type);
|
|
DLOG("reg %08x \n",
|
|
mask);
|
|
|
|
stlink_write_debug32(sl, 0xe0002008 + id * 4, mask);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
struct flash_block {
|
|
stm32_addr_t addr;
|
|
unsigned length;
|
|
uint8_t* data;
|
|
|
|
struct flash_block* next;
|
|
};
|
|
|
|
static struct flash_block* flash_root;
|
|
|
|
static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) {
|
|
|
|
if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) {
|
|
ELOG("flash_add_block: incorrect bounds\n");
|
|
return -1;
|
|
}
|
|
|
|
stlink_calculate_pagesize(sl, addr);
|
|
if (addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) {
|
|
ELOG("flash_add_block: unaligned block\n");
|
|
return -1;
|
|
}
|
|
|
|
struct flash_block* new = malloc(sizeof(struct flash_block));
|
|
new->next = flash_root;
|
|
|
|
new->addr = addr;
|
|
new->length = length;
|
|
new->data = calloc(length, 1);
|
|
|
|
flash_root = new;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) {
|
|
unsigned int fit_blocks = 0, fit_length = 0;
|
|
|
|
for (struct flash_block* fb = flash_root; fb; fb = fb->next) {
|
|
/* Block: ------X------Y--------
|
|
* Data: a-----b
|
|
* a--b
|
|
* a-----------b
|
|
* Block intersects with data, if:
|
|
* a < Y && b > x
|
|
*/
|
|
|
|
unsigned X = fb->addr, Y = fb->addr + fb->length;
|
|
unsigned a = addr, b = addr + length;
|
|
if (a < Y && b > X) {
|
|
// from start of the block
|
|
unsigned start = (a > X ? a : X) - X;
|
|
unsigned end = (b > Y ? Y : b) - X;
|
|
|
|
memcpy(fb->data + start, data, end - start);
|
|
|
|
fit_blocks++;
|
|
fit_length += end - start;
|
|
}
|
|
}
|
|
|
|
if (fit_blocks == 0) {
|
|
ELOG("Unfit data block %08x -> %04x\n", addr, length);
|
|
return -1;
|
|
}
|
|
|
|
if (fit_length != length) {
|
|
WLOG("data block %08x -> %04x truncated to %04x\n",
|
|
addr, length, fit_length);
|
|
WLOG("(this is not an error, just a GDB glitch)\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int flash_go(stlink_t *sl) {
|
|
int error = -1;
|
|
|
|
// Some kinds of clock settings do not allow writing to flash.
|
|
stlink_reset(sl);
|
|
stlink_force_debug(sl);
|
|
|
|
for (struct flash_block* fb = flash_root; fb; fb = fb->next) {
|
|
DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length);
|
|
|
|
for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) {
|
|
unsigned length = fb->length - (page - fb->addr);
|
|
|
|
//Update FLASH_PAGE
|
|
stlink_calculate_pagesize(sl, page);
|
|
|
|
DLOG("flash_do: page %08x\n", page);
|
|
unsigned len = (length > FLASH_PAGE) ? (unsigned int) FLASH_PAGE : length;
|
|
int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0);
|
|
if (ret < 0)
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
stlink_reset(sl);
|
|
|
|
error = 0;
|
|
|
|
error:
|
|
for (struct flash_block* fb = flash_root, *next; fb; fb = next) {
|
|
next = fb->next;
|
|
free(fb->data);
|
|
free(fb);
|
|
}
|
|
|
|
flash_root = NULL;
|
|
|
|
return error;
|
|
}
|
|
|
|
#define CLIDR 0xE000ED78
|
|
#define CTR 0xE000ED7C
|
|
#define CCSIDR 0xE000ED80
|
|
#define CSSELR 0xE000ED84
|
|
#define CCR 0xE000ED14
|
|
#define CCR_DC (1 << 16)
|
|
#define CCR_IC (1 << 17)
|
|
#define DCCSW 0xE000EF6C
|
|
#define ICIALLU 0xE000EF50
|
|
|
|
struct cache_level_desc
|
|
{
|
|
unsigned int nsets;
|
|
unsigned int nways;
|
|
unsigned int log2_nways;
|
|
unsigned int width;
|
|
};
|
|
|
|
struct cache_desc_t
|
|
{
|
|
/* Minimal line size in bytes. */
|
|
unsigned int dminline;
|
|
unsigned int iminline;
|
|
|
|
/* Last level of unification (uniprocessor). */
|
|
unsigned int louu;
|
|
|
|
struct cache_level_desc icache[7];
|
|
struct cache_level_desc dcache[7];
|
|
};
|
|
|
|
static struct cache_desc_t cache_desc;
|
|
|
|
/* Return the smallest R so that V <= (1 << R). Not performance critical. */
|
|
static unsigned ceil_log2(unsigned v)
|
|
{
|
|
unsigned res;
|
|
for (res = 0; (1U << res) < v; res++)
|
|
;
|
|
return res;
|
|
}
|
|
|
|
static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc)
|
|
{
|
|
unsigned int ccsidr;
|
|
unsigned int log2_nsets;
|
|
|
|
stlink_read_debug32(sl, CCSIDR, &ccsidr);
|
|
desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1;
|
|
desc->nways = ((ccsidr >> 3) & 0x1ff) + 1;
|
|
desc->log2_nways = ceil_log2 (desc->nways);
|
|
log2_nsets = ceil_log2 (desc->nsets);
|
|
desc->width = 4 + (ccsidr & 7) + log2_nsets;
|
|
ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n",
|
|
ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width);
|
|
}
|
|
|
|
static void init_cache (stlink_t *sl) {
|
|
unsigned int clidr;
|
|
unsigned int ccr;
|
|
unsigned int ctr;
|
|
int i;
|
|
|
|
/* Assume only F7 has a cache. */
|
|
if (sl->core_id!=STM32F7_CORE_ID)
|
|
return;
|
|
|
|
stlink_read_debug32(sl, CLIDR, &clidr);
|
|
stlink_read_debug32(sl, CCR, &ccr);
|
|
stlink_read_debug32(sl, CTR, &ctr);
|
|
cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f);
|
|
cache_desc.iminline = 4 << (ctr & 0x0f);
|
|
cache_desc.louu = (clidr >> 27) & 7;
|
|
|
|
ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n",
|
|
clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off");
|
|
ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n",
|
|
(clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7);
|
|
ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr,
|
|
cache_desc.dminline, cache_desc.iminline);
|
|
for (i = 0; i < 7; i++)
|
|
{
|
|
unsigned int ct = (clidr >> (3 * i)) & 0x07;
|
|
|
|
cache_desc.dcache[i].width = 0;
|
|
cache_desc.icache[i].width = 0;
|
|
|
|
if (ct == 2 || ct == 3 || ct == 4)
|
|
{
|
|
/* Data. */
|
|
stlink_write_debug32(sl, CSSELR, i << 1);
|
|
ILOG("D-Cache L%d: ", i);
|
|
read_cache_level_desc(sl, &cache_desc.dcache[i]);
|
|
}
|
|
|
|
if (ct == 1 || ct == 3)
|
|
{
|
|
/* Instruction. */
|
|
stlink_write_debug32(sl, CSSELR, (i << 1) | 1);
|
|
ILOG("I-Cache L%d: ", i);
|
|
read_cache_level_desc(sl, &cache_desc.icache[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void cache_flush(stlink_t *sl, unsigned ccr) {
|
|
int level;
|
|
|
|
if (ccr & CCR_DC)
|
|
for (level = cache_desc.louu - 1; level >= 0; level--) {
|
|
struct cache_level_desc *desc = &cache_desc.dcache[level];
|
|
unsigned addr;
|
|
unsigned max_addr = 1 << desc->width;
|
|
unsigned way_sh = 32 - desc->log2_nways;
|
|
|
|
/* D-cache clean by set-ways. */
|
|
for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) {
|
|
unsigned int way;
|
|
|
|
for (way = 0; way < desc->nways; way++)
|
|
stlink_write_debug32(sl, DCCSW, addr | (way << way_sh));
|
|
}
|
|
}
|
|
|
|
/* Invalidate all I-cache to oPU. */
|
|
if (ccr & CCR_IC)
|
|
stlink_write_debug32(sl, ICIALLU, 0);
|
|
}
|
|
|
|
static int cache_modified;
|
|
|
|
static void cache_change(stm32_addr_t start, unsigned count)
|
|
{
|
|
if (count == 0)
|
|
return;
|
|
(void)start;
|
|
cache_modified = 1;
|
|
}
|
|
|
|
static void cache_sync(stlink_t *sl)
|
|
{
|
|
unsigned ccr;
|
|
|
|
if (sl->core_id!=STM32F7_CORE_ID)
|
|
return;
|
|
if (!cache_modified)
|
|
return;
|
|
cache_modified = 0;
|
|
|
|
stlink_read_debug32(sl, CCR, &ccr);
|
|
if (ccr & (CCR_IC | CCR_DC))
|
|
cache_flush(sl, ccr);
|
|
}
|
|
|
|
static size_t unhexify(const char *in, char *out, size_t out_count)
|
|
{
|
|
size_t i;
|
|
unsigned int c;
|
|
|
|
for (i = 0; i < out_count; i++) {
|
|
if (sscanf(in + (2 * i), "%02x", &c) != 1) {
|
|
return i;
|
|
}
|
|
out[i] = (char)c;
|
|
}
|
|
|
|
return i;
|
|
}
|
|
|
|
int serve(stlink_t *sl, st_state_t *st) {
|
|
SOCKET sock = socket(AF_INET, SOCK_STREAM, 0);
|
|
if (!IS_SOCK_VALID(sock)) {
|
|
perror("socket");
|
|
return 1;
|
|
}
|
|
|
|
unsigned int val = 1;
|
|
setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
|
|
|
|
struct sockaddr_in serv_addr;
|
|
memset(&serv_addr,0,sizeof(struct sockaddr_in));
|
|
serv_addr.sin_family = AF_INET;
|
|
serv_addr.sin_addr.s_addr = INADDR_ANY;
|
|
serv_addr.sin_port = htons(st->listen_port);
|
|
|
|
if (bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) {
|
|
perror("bind");
|
|
close_socket(sock);
|
|
return 1;
|
|
}
|
|
|
|
if (listen(sock, 5) < 0) {
|
|
perror("listen");
|
|
close_socket(sock);
|
|
return 1;
|
|
}
|
|
|
|
ILOG("Listening at *:%d...\n", st->listen_port);
|
|
|
|
SOCKET client = accept(sock, NULL, NULL);
|
|
//signal (SIGINT, SIG_DFL);
|
|
if (!IS_SOCK_VALID(client)) {
|
|
perror("accept");
|
|
close_socket(sock);
|
|
return 1;
|
|
}
|
|
|
|
close_socket(sock);
|
|
|
|
stlink_force_debug(sl);
|
|
if (st->reset) {
|
|
stlink_reset(sl);
|
|
}
|
|
init_code_breakpoints(sl);
|
|
init_data_watchpoints(sl);
|
|
|
|
ILOG("GDB connected.\n");
|
|
|
|
/*
|
|
* To allow resetting the chip from GDB it is required to
|
|
* emulate attaching and detaching to target.
|
|
*/
|
|
unsigned int attached = 1;
|
|
/*
|
|
* If a critical error is detected, break from the loop
|
|
*/
|
|
int critical_error = 0;
|
|
int ret;
|
|
while (1) {
|
|
ret = 0;
|
|
char* packet;
|
|
|
|
int status = gdb_recv_packet(client, &packet);
|
|
if (status < 0) {
|
|
ELOG("cannot recv: %d\n", status);
|
|
close_socket(client);
|
|
return 1;
|
|
}
|
|
|
|
DLOG("recv: %s\n", packet);
|
|
|
|
char* reply = NULL;
|
|
struct stlink_reg regp;
|
|
|
|
switch(packet[0]) {
|
|
case 'q': {
|
|
if (packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') {
|
|
reply = strdup("");
|
|
break;
|
|
}
|
|
|
|
char *separator = strstr(packet, ":"), *params = "";
|
|
if (separator == NULL) {
|
|
separator = packet + strlen(packet);
|
|
} else {
|
|
params = separator + 1;
|
|
}
|
|
|
|
unsigned queryNameLength = (unsigned int) (separator - &packet[1]);
|
|
char* queryName = calloc(queryNameLength + 1, 1);
|
|
strncpy(queryName, &packet[1], queryNameLength);
|
|
|
|
DLOG("query: %s;%s\n", queryName, params);
|
|
|
|
if (!strcmp(queryName, "Supported")) {
|
|
if (sl->chip_id==STLINK_CHIPID_STM32_F4
|
|
|| sl->chip_id==STLINK_CHIPID_STM32_F4_HD
|
|
|| sl->core_id==STM32F7_CORE_ID) {
|
|
reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+");
|
|
}
|
|
else {
|
|
reply = strdup("PacketSize=3fff;qXfer:memory-map:read+");
|
|
}
|
|
} else if (!strcmp(queryName, "Xfer")) {
|
|
char *type, *op, *__s_addr, *s_length;
|
|
char *tok = params;
|
|
char *annex __attribute__((unused));
|
|
|
|
type = strsep(&tok, ":");
|
|
op = strsep(&tok, ":");
|
|
annex = strsep(&tok, ":");
|
|
__s_addr = strsep(&tok, ",");
|
|
s_length = tok;
|
|
|
|
unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16),
|
|
length = (unsigned int) strtoul(s_length, NULL, 16);
|
|
|
|
DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n",
|
|
type, op, annex, addr, length);
|
|
|
|
const char* data = NULL;
|
|
|
|
if (!strcmp(type, "memory-map") && !strcmp(op, "read"))
|
|
data = current_memory_map;
|
|
|
|
if (!strcmp(type, "features") && !strcmp(op, "read"))
|
|
data = target_description_F4;
|
|
|
|
if (data) {
|
|
unsigned data_length = (unsigned int) strlen(data);
|
|
if (addr + length > data_length)
|
|
length = data_length - addr;
|
|
|
|
if (length == 0) {
|
|
reply = strdup("l");
|
|
} else {
|
|
reply = calloc(length + 2, 1);
|
|
reply[0] = 'm';
|
|
strncpy(&reply[1], data, length);
|
|
}
|
|
}
|
|
} else if (!strncmp(queryName, "Rcmd,",4)) {
|
|
// Rcmd uses the wrong separator
|
|
separator = strstr(packet, ",");
|
|
params = "";
|
|
if (separator == NULL) {
|
|
separator = packet + strlen(packet);
|
|
} else {
|
|
params = separator + 1;
|
|
}
|
|
|
|
size_t hex_len = strlen(params);
|
|
size_t alloc_size = (hex_len / 2) + 1;
|
|
size_t cmd_len;
|
|
char *cmd = malloc(alloc_size);
|
|
|
|
if (cmd == NULL) {
|
|
DLOG("Rcmd unhexify allocation error\n");
|
|
break;
|
|
}
|
|
|
|
cmd_len = unhexify(params, cmd, alloc_size - 1);
|
|
cmd[cmd_len] = 0;
|
|
|
|
DLOG("unhexified Rcmd: '%s'\n", cmd);
|
|
|
|
if (!strncmp(cmd, "resume", 6)) {// resume
|
|
DLOG("Rcmd: resume\n");
|
|
cache_sync(sl);
|
|
ret = stlink_run(sl);
|
|
if (ret) {
|
|
DLOG("Rcmd: resume failed\n");
|
|
reply = strdup("E00");
|
|
|
|
} else {
|
|
reply = strdup("OK");
|
|
}
|
|
|
|
} else if (!strncmp(cmd, "halt", 4)) { //halt
|
|
ret = stlink_force_debug(sl);
|
|
if (ret) {
|
|
DLOG("Rcmd: halt failed\n");
|
|
reply = strdup("E00");
|
|
|
|
} else {
|
|
reply = strdup("OK");
|
|
DLOG("Rcmd: halt\n");
|
|
}
|
|
|
|
} else if (!strncmp(cmd, "jtag_reset", 10)) { //jtag_reset
|
|
reply = strdup("OK");
|
|
|
|
ret = stlink_jtag_reset(sl, 0);
|
|
if (ret) {
|
|
DLOG("Rcmd: jtag_reset failed with jtag_reset\n");
|
|
reply = strdup("E00");
|
|
|
|
}
|
|
|
|
ret = stlink_jtag_reset(sl, 1);
|
|
if (ret) {
|
|
DLOG("Rcmd: jtag_reset failed with jtag_reset\n");
|
|
reply = strdup("E00");
|
|
|
|
}
|
|
|
|
ret = stlink_force_debug(sl);
|
|
if (ret) {
|
|
DLOG("Rcmd: jtag_reset failed with force_debug\n");
|
|
reply = strdup("E00");
|
|
|
|
}
|
|
if (strcmp(reply, "E00")) {
|
|
// no errors have been found
|
|
DLOG("Rcmd: jtag_reset\n");
|
|
}
|
|
} else if (!strncmp(cmd, "reset", 5)) { //reset
|
|
|
|
ret = stlink_force_debug(sl);
|
|
if (ret) {
|
|
DLOG("Rcmd: reset failed with force_debug\n");
|
|
reply = strdup("E00");
|
|
}
|
|
|
|
ret = stlink_reset(sl);
|
|
if (ret) {
|
|
DLOG("Rcmd: reset failed with reset\n");
|
|
reply = strdup("E00");
|
|
}
|
|
|
|
init_code_breakpoints(sl);
|
|
init_data_watchpoints(sl);
|
|
|
|
if (reply == NULL) {
|
|
reply = strdup("OK");
|
|
DLOG("Rcmd: reset\n");
|
|
}
|
|
|
|
} else if (!strncmp(cmd, "semihosting ", 12)) {
|
|
DLOG("Rcmd: got semihosting cmd '%s'", cmd);
|
|
char *arg = cmd + 12;
|
|
|
|
/* Skip whitespaces */
|
|
while (isspace(*arg)) {
|
|
arg++;
|
|
}
|
|
|
|
if (!strncmp(arg, "enable", 6)
|
|
|| !strncmp(arg, "1", 1))
|
|
{
|
|
semihosting = true;
|
|
reply = strdup("OK");
|
|
} else if (!strncmp(arg, "disable", 7)
|
|
|| !strncmp(arg, "0", 1))
|
|
{
|
|
semihosting = false;
|
|
reply = strdup("OK");
|
|
} else {
|
|
DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg);
|
|
}
|
|
} else {
|
|
DLOG("Rcmd: %s\n", cmd);
|
|
}
|
|
free(cmd);
|
|
}
|
|
|
|
if (reply == NULL)
|
|
reply = strdup("");
|
|
|
|
free(queryName);
|
|
|
|
break;
|
|
}
|
|
|
|
case 'v': {
|
|
char *params = NULL;
|
|
char *cmdName = strtok_r(packet, ":;", ¶ms);
|
|
|
|
cmdName++; // vCommand -> Command
|
|
|
|
if (!strcmp(cmdName, "FlashErase")) {
|
|
char *__s_addr, *s_length;
|
|
char *tok = params;
|
|
|
|
__s_addr = strsep(&tok, ",");
|
|
s_length = tok;
|
|
|
|
unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16),
|
|
length = (unsigned int) strtoul(s_length, NULL, 16);
|
|
|
|
DLOG("FlashErase: addr:%08x,len:%04x\n",
|
|
addr, length);
|
|
|
|
if (flash_add_block(addr, length, sl) < 0) {
|
|
reply = strdup("E00");
|
|
} else {
|
|
reply = strdup("OK");
|
|
}
|
|
} else if (!strcmp(cmdName, "FlashWrite")) {
|
|
char *__s_addr, *data;
|
|
char *tok = params;
|
|
|
|
__s_addr = strsep(&tok, ":");
|
|
data = tok;
|
|
|
|
unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16);
|
|
unsigned data_length = status - (unsigned int) (data - packet);
|
|
|
|
// Length of decoded data cannot be more than
|
|
// encoded, as escapes are removed.
|
|
// Additional byte is reserved for alignment fix.
|
|
uint8_t *decoded = calloc(data_length + 1, 1);
|
|
unsigned dec_index = 0;
|
|
for (unsigned int i = 0; i < data_length; i++) {
|
|
if (data[i] == 0x7d) {
|
|
i++;
|
|
decoded[dec_index++] = data[i] ^ 0x20;
|
|
} else {
|
|
decoded[dec_index++] = data[i];
|
|
}
|
|
}
|
|
|
|
// Fix alignment
|
|
if (dec_index % 2 != 0)
|
|
dec_index++;
|
|
|
|
DLOG("binary packet %d -> %d\n", data_length, dec_index);
|
|
|
|
if (flash_populate(addr, decoded, dec_index) < 0) {
|
|
reply = strdup("E00");
|
|
} else {
|
|
reply = strdup("OK");
|
|
}
|
|
|
|
free(decoded);
|
|
} else if (!strcmp(cmdName, "FlashDone")) {
|
|
if (flash_go(sl) < 0) {
|
|
reply = strdup("E00");
|
|
} else {
|
|
reply = strdup("OK");
|
|
}
|
|
} else if (!strcmp(cmdName, "Kill")) {
|
|
attached = 0;
|
|
|
|
reply = strdup("OK");
|
|
}
|
|
|
|
if (reply == NULL)
|
|
reply = strdup("");
|
|
|
|
break;
|
|
}
|
|
|
|
case 'c':
|
|
cache_sync(sl);
|
|
ret = stlink_run(sl);
|
|
if (ret) {
|
|
DLOG("Semihost: run failed\n");
|
|
}
|
|
|
|
while (1) {
|
|
status = gdb_check_for_interrupt(client);
|
|
if (status < 0) {
|
|
ELOG("cannot check for int: %d\n", status);
|
|
close_socket(client);
|
|
return 1;
|
|
}
|
|
|
|
if (status == 1) {
|
|
stlink_force_debug(sl);
|
|
break;
|
|
}
|
|
|
|
ret = stlink_status(sl);
|
|
if (ret) {
|
|
DLOG("Semihost: status failed\n");
|
|
}
|
|
if (sl->core_stat == STLINK_CORE_HALTED) {
|
|
struct stlink_reg reg;
|
|
stm32_addr_t pc;
|
|
stm32_addr_t addr;
|
|
int offset = 0;
|
|
uint16_t insn;
|
|
|
|
if (!semihosting) {
|
|
break;
|
|
}
|
|
|
|
ret = stlink_read_all_regs (sl, ®);
|
|
if (ret) {
|
|
DLOG("Semihost: read_all_regs failed\n");
|
|
}
|
|
|
|
/* Read PC */
|
|
pc = reg.r[15];
|
|
|
|
/* Compute aligned value */
|
|
offset = pc % 4;
|
|
addr = pc - offset;
|
|
|
|
/* Read instructions (address and length must be
|
|
* aligned).
|
|
*/
|
|
ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4));
|
|
|
|
if (ret != 0) {
|
|
DLOG("Semihost: cannot read instructions at: "
|
|
"0x%08x\n", addr);
|
|
break;
|
|
}
|
|
|
|
memcpy(&insn, &sl->q_buf[offset], sizeof(insn));
|
|
|
|
if (insn == 0xBEAB && !has_breakpoint(addr)) {
|
|
|
|
ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]);
|
|
if (ret) {
|
|
DLOG("Semihost: do_semihosting failed\n");
|
|
}
|
|
|
|
/* Write return value */
|
|
ret = stlink_write_reg(sl, reg.r[0], 0);
|
|
if (ret) {
|
|
DLOG("Semihost: write_reg failed for return value\n");
|
|
}
|
|
|
|
/* Jump over the break instruction */
|
|
ret = stlink_write_reg(sl, reg.r[15] + 2, 15);
|
|
if (ret) {
|
|
DLOG("Semihost: write_reg failed for jumping over break\n");
|
|
}
|
|
|
|
/* continue execution */
|
|
cache_sync(sl);
|
|
ret = stlink_run(sl);
|
|
if (ret) {
|
|
DLOG("Semihost: continue execution failed with stlink_run\n");
|
|
}
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
|
|
usleep(100000);
|
|
}
|
|
|
|
reply = strdup("S05"); // TRAP
|
|
break;
|
|
|
|
case 's':
|
|
cache_sync(sl);
|
|
ret = stlink_step(sl);
|
|
if (ret) {
|
|
// have problem sending step packet
|
|
ELOG("Step: cannot send step request\n");
|
|
reply = strdup("E00");
|
|
critical_error = 1; // absolutely critical
|
|
} else {
|
|
reply = strdup("S05"); // TRAP
|
|
}
|
|
|
|
break;
|
|
|
|
case '?':
|
|
if (attached) {
|
|
reply = strdup("S05"); // TRAP
|
|
} else {
|
|
/* Stub shall reply OK if not attached. */
|
|
reply = strdup("OK");
|
|
}
|
|
break;
|
|
|
|
case 'g':
|
|
ret = stlink_read_all_regs(sl, ®p);
|
|
if (ret) {
|
|
DLOG("g packet: read_all_regs failed\n");
|
|
}
|
|
|
|
reply = calloc(8 * 16 + 1, 1);
|
|
for (int i = 0; i < 16; i++)
|
|
sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i]));
|
|
|
|
break;
|
|
|
|
case 'p': {
|
|
unsigned id = (unsigned int) strtoul(&packet[1], NULL, 16);
|
|
unsigned myreg = 0xDEADDEAD;
|
|
|
|
if (id < 16) {
|
|
ret = stlink_read_reg(sl, id, ®p);
|
|
myreg = htonl(regp.r[id]);
|
|
} else if (id == 0x19) {
|
|
ret = stlink_read_reg(sl, 16, ®p);
|
|
myreg = htonl(regp.xpsr);
|
|
} else if (id == 0x1A) {
|
|
ret = stlink_read_reg(sl, 17, ®p);
|
|
myreg = htonl(regp.main_sp);
|
|
} else if (id == 0x1B) {
|
|
ret = stlink_read_reg(sl, 18, ®p);
|
|
myreg = htonl(regp.process_sp);
|
|
} else if (id == 0x1C) {
|
|
ret = stlink_read_unsupported_reg(sl, id, ®p);
|
|
myreg = htonl(regp.control);
|
|
} else if (id == 0x1D) {
|
|
ret = stlink_read_unsupported_reg(sl, id, ®p);
|
|
myreg = htonl(regp.faultmask);
|
|
} else if (id == 0x1E) {
|
|
ret = stlink_read_unsupported_reg(sl, id, ®p);
|
|
myreg = htonl(regp.basepri);
|
|
} else if (id == 0x1F) {
|
|
ret = stlink_read_unsupported_reg(sl, id, ®p);
|
|
myreg = htonl(regp.primask);
|
|
} else if (id >= 0x20 && id < 0x40) {
|
|
ret = stlink_read_unsupported_reg(sl, id, ®p);
|
|
myreg = htonl(regp.s[id-0x20]);
|
|
} else if (id == 0x40) {
|
|
ret = stlink_read_unsupported_reg(sl, id, ®p);
|
|
myreg = htonl(regp.fpscr);
|
|
} else {
|
|
ret = 1;
|
|
reply = strdup("E00");
|
|
}
|
|
if (ret) {
|
|
DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id);
|
|
}
|
|
|
|
if (reply == NULL) {
|
|
// if reply is set to "E00", skip
|
|
reply = calloc(8 + 1, 1);
|
|
sprintf(reply, "%08x", myreg);
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
case 'P': {
|
|
char* s_reg = &packet[1];
|
|
char* s_value = strstr(&packet[1], "=") + 1;
|
|
|
|
unsigned reg = (unsigned int) strtoul(s_reg, NULL, 16);
|
|
unsigned value = (unsigned int) strtoul(s_value, NULL, 16);
|
|
|
|
|
|
if (reg < 16) {
|
|
ret = stlink_write_reg(sl, ntohl(value), reg);
|
|
} else if (reg == 0x19) {
|
|
ret = stlink_write_reg(sl, ntohl(value), 16);
|
|
} else if (reg == 0x1A) {
|
|
ret = stlink_write_reg(sl, ntohl(value), 17);
|
|
} else if (reg == 0x1B) {
|
|
ret = stlink_write_reg(sl, ntohl(value), 18);
|
|
} else if (reg == 0x1C) {
|
|
ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
|
|
} else if (reg == 0x1D) {
|
|
ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
|
|
} else if (reg == 0x1E) {
|
|
ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
|
|
} else if (reg == 0x1F) {
|
|
ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
|
|
} else if (reg >= 0x20 && reg < 0x40) {
|
|
ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
|
|
} else if (reg == 0x40) {
|
|
ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p);
|
|
} else {
|
|
ret = 1;
|
|
reply = strdup("E00");
|
|
}
|
|
if (ret) {
|
|
DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg);
|
|
}
|
|
if (reply == NULL) {
|
|
// note that NULL may not be zero
|
|
reply = strdup("OK");
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
case 'G':
|
|
for (int i = 0; i < 16; i++) {
|
|
char str[9] = {0};
|
|
strncpy(str, &packet[1 + i * 8], 8);
|
|
uint32_t reg = (uint32_t) strtoul(str, NULL, 16);
|
|
ret = stlink_write_reg(sl, ntohl(reg), i);
|
|
if (ret) {
|
|
DLOG("G packet: stlink_write_reg failed");
|
|
}
|
|
}
|
|
|
|
reply = strdup("OK");
|
|
break;
|
|
|
|
case 'm': {
|
|
char* s_start = &packet[1];
|
|
char* s_count = strstr(&packet[1], ",") + 1;
|
|
|
|
stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16);
|
|
unsigned count = (unsigned int) strtoul(s_count, NULL, 16);
|
|
|
|
unsigned adj_start = start % 4;
|
|
unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4;
|
|
if (count_rnd > sl->flash_pgsz)
|
|
count_rnd = (unsigned int) sl->flash_pgsz;
|
|
if (count_rnd > 0x1800)
|
|
count_rnd = 0x1800;
|
|
if (count_rnd < count)
|
|
count = count_rnd;
|
|
|
|
if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) {
|
|
/* read failed somehow, don't return stale buffer */
|
|
count = 0;
|
|
}
|
|
|
|
reply = calloc(count * 2 + 1, 1);
|
|
for (unsigned int i = 0; i < count; i++) {
|
|
reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4];
|
|
reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf];
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
case 'M': {
|
|
char* s_start = &packet[1];
|
|
char* s_count = strstr(&packet[1], ",") + 1;
|
|
char* hexdata = strstr(packet, ":") + 1;
|
|
|
|
stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16);
|
|
unsigned count = (unsigned int) strtoul(s_count, NULL, 16);
|
|
int err = 0;
|
|
|
|
if (start % 4) {
|
|
unsigned align_count = 4 - start % 4;
|
|
if (align_count > count) align_count = count;
|
|
for (unsigned int i = 0; i < align_count; i ++) {
|
|
char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
|
|
uint8_t byte = strtoul(hextmp, NULL, 16);
|
|
sl->q_buf[i] = byte;
|
|
}
|
|
err |= stlink_write_mem8(sl, start, align_count);
|
|
cache_change(start, align_count);
|
|
start += align_count;
|
|
count -= align_count;
|
|
hexdata += 2*align_count;
|
|
}
|
|
|
|
if (count - count % 4) {
|
|
unsigned aligned_count = count - count % 4;
|
|
|
|
for (unsigned int i = 0; i < aligned_count; i ++) {
|
|
char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
|
|
uint8_t byte = strtoul(hextmp, NULL, 16);
|
|
sl->q_buf[i] = byte;
|
|
}
|
|
err |= stlink_write_mem32(sl, start, aligned_count);
|
|
cache_change(start, aligned_count);
|
|
count -= aligned_count;
|
|
start += aligned_count;
|
|
hexdata += 2*aligned_count;
|
|
}
|
|
|
|
if (count) {
|
|
for (unsigned int i = 0; i < count; i ++) {
|
|
char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 };
|
|
uint8_t byte = strtoul(hextmp, NULL, 16);
|
|
sl->q_buf[i] = byte;
|
|
}
|
|
err |= stlink_write_mem8(sl, start, count);
|
|
cache_change(start, count);
|
|
}
|
|
reply = strdup(err ? "E00" : "OK");
|
|
break;
|
|
}
|
|
|
|
case 'Z': {
|
|
char *endptr;
|
|
stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16);
|
|
stm32_addr_t len = (stm32_addr_t) strtoul(&endptr[1], NULL, 16);
|
|
|
|
switch (packet[1]) {
|
|
case '1':
|
|
if (update_code_breakpoint(sl, addr, 1) < 0) {
|
|
reply = strdup("E00");
|
|
} else {
|
|
reply = strdup("OK");
|
|
}
|
|
break;
|
|
|
|
case '2': // insert write watchpoint
|
|
case '3': // insert read watchpoint
|
|
case '4': { // insert access watchpoint
|
|
enum watchfun wf;
|
|
if (packet[1] == '2') {
|
|
wf = WATCHWRITE;
|
|
} else if (packet[1] == '3') {
|
|
wf = WATCHREAD;
|
|
} else {
|
|
wf = WATCHACCESS;
|
|
}
|
|
|
|
if (add_data_watchpoint(sl, wf, addr, len) < 0) {
|
|
reply = strdup("E00");
|
|
} else {
|
|
reply = strdup("OK");
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
reply = strdup("");
|
|
}
|
|
break;
|
|
}
|
|
case 'z': {
|
|
char *endptr;
|
|
stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16);
|
|
//stm32_addr_t len = strtoul(&endptr[1], NULL, 16);
|
|
|
|
switch (packet[1]) {
|
|
case '1': // remove breakpoint
|
|
update_code_breakpoint(sl, addr, 0);
|
|
reply = strdup("OK");
|
|
break;
|
|
|
|
case '2' : // remove write watchpoint
|
|
case '3' : // remove read watchpoint
|
|
case '4' : // remove access watchpoint
|
|
if (delete_data_watchpoint(sl, addr) < 0) {
|
|
reply = strdup("E00");
|
|
break;
|
|
} else {
|
|
reply = strdup("OK");
|
|
break;
|
|
}
|
|
|
|
default:
|
|
reply = strdup("");
|
|
}
|
|
break;
|
|
}
|
|
|
|
case '!': {
|
|
/*
|
|
* Enter extended mode which allows restarting.
|
|
* We do support that always.
|
|
*/
|
|
|
|
/*
|
|
* Also, set to persistent mode
|
|
* to allow GDB disconnect.
|
|
*/
|
|
st->persistent = 1;
|
|
|
|
reply = strdup("OK");
|
|
|
|
break;
|
|
}
|
|
|
|
case 'R': {
|
|
|
|
/* Reset the core. */
|
|
|
|
ret = stlink_reset(sl);
|
|
if (ret) {
|
|
DLOG("R packet : stlink_reset failed\n");
|
|
}
|
|
init_code_breakpoints(sl);
|
|
init_data_watchpoints(sl);
|
|
|
|
attached = 1;
|
|
|
|
reply = strdup("OK");
|
|
|
|
break;
|
|
}
|
|
case 'k':
|
|
/* Kill request - reset the connection itself */
|
|
ret = stlink_run(sl);
|
|
if (ret) {
|
|
DLOG("Kill: stlink_run failed\n");
|
|
}
|
|
|
|
ret = stlink_exit_debug_mode(sl);
|
|
if (ret) {
|
|
DLOG("Kill: stlink_exit_debug_mode failed\n");
|
|
}
|
|
stlink_close(sl);
|
|
|
|
sl = do_connect(st);
|
|
if (sl == NULL) cleanup(0);
|
|
connected_stlink = sl;
|
|
|
|
if (st->reset) {
|
|
stlink_reset(sl);
|
|
}
|
|
ret = stlink_force_debug(sl);
|
|
if (ret) {
|
|
DLOG("Kill: stlink_force_debug failed\n");
|
|
}
|
|
init_cache(sl);
|
|
init_code_breakpoints(sl);
|
|
init_data_watchpoints(sl);
|
|
|
|
reply = NULL; /* no response */
|
|
|
|
break;
|
|
|
|
default:
|
|
reply = strdup("");
|
|
}
|
|
|
|
if (reply) {
|
|
DLOG("send: %s\n", reply);
|
|
|
|
int result = gdb_send_packet(client, reply);
|
|
if (result != 0) {
|
|
ELOG("cannot send: %d\n", result);
|
|
free(reply);
|
|
free(packet);
|
|
close_socket(client);
|
|
return 1;
|
|
}
|
|
|
|
free(reply);
|
|
}
|
|
|
|
if (critical_error) {
|
|
close_socket(client);
|
|
return 1;
|
|
}
|
|
|
|
free(packet);
|
|
}
|
|
|
|
close_socket(client);
|
|
|
|
return 0;
|
|
}
|