kopia lustrzana https://github.com/stlink-org/stlink
133 wiersze
6.2 KiB
C
133 wiersze
6.2 KiB
C
/*
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* File: register.h
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*
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* Common STM32 registers
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*/
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#ifndef REGISTER_H
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#define REGISTER_H
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#define STLINK_REG_CM3_CPUID 0xE000ED00
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#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC20
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#define STLINK_REG_CMx_CPUID_PARTNO_CM0P 0xC60
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#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC23
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#define STLINK_REG_CMx_CPUID_PARTNO_CM4 0xC24
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#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC27
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#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD21
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#define STLINK_REG_CMx_CPUID_IMPL_ARM 0x41
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#define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register
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#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4)
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#define STLINK_REG_CM3_FP_CTRL_KEY (1 << 1)
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#define STLINK_REG_CM7_FP_LAR 0xE0000FB0
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#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55
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#define STLINK_REG_CM3_DEMCR 0xE000EDFC
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#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24)
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#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10)
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#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8)
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#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0)
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#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16)
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#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16)
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#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16)
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/* Cortex™-M3 Technical Reference Manual */
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/* Configurable Fault Status Register */
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#define STLINK_REG_CFSR 0xE000ED28
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/* Hard Fault Status Register */
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#define STLINK_REG_HFSR 0xE000ED2C
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/* Debug Halting Control and Status Register */
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#define STLINK_REG_DFSR 0xE000ED30
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#define STLINK_REG_DFSR_HALT (1 << 0)
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#define STLINK_REG_DFSR_BKPT (1 << 1)
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#define STLINK_REG_DFSR_VCATCH (1 << 3)
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#define STLINK_REG_DFSR_EXTERNAL (1 << 4)
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#define STLINK_REG_DFSR_CLEAR 0x0000001F
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#define STLINK_REG_DHCSR 0xe000edf0
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#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16)
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#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0)
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#define STLINK_REG_DHCSR_C_HALT (1 << 1)
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#define STLINK_REG_DHCSR_C_STEP (1 << 2)
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#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3)
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#define STLINK_REG_DHCSR_S_REGRDY (1 << 16)
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#define STLINK_REG_DHCSR_S_HALT (1 << 17)
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#define STLINK_REG_DHCSR_S_SLEEP (1 << 18)
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#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19)
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#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24)
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#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25)
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#define STLINK_REG_DCRSR 0xe000edf4
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#define STLINK_REG_DCRDR 0xe000edf8
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#define STLINK_REG_DEMCR 0xe000edfc
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#define STLINK_REG_DEMCR_TRCENA (1 << 24)
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/* MCU Debug Component Registers */
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#define STLINK_REG_DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register
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#define STLINK_REG_DBGMCU_CR_DBG_SLEEP (1 << 0)
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#define STLINK_REG_DBGMCU_CR_DBG_STOP (1 << 1)
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#define STLINK_REG_DBGMCU_CR_DBG_STANDBY (1 << 2)
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#define STLINK_REG_DBGMCU_CR_TRACE_IOEN (1 << 5)
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#define STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6)
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/* Data Watchpoint and Trace (DWT) Registers */
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#define STLINK_REG_DWT_CTRL 0xE0001000 // DWT Control Register
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#define STLINK_REG_DWT_CTRL_NUM_COMP (1 << 28)
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#define STLINK_REG_DWT_CTRL_CYC_TAP (1 << 9)
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#define STLINK_REG_DWT_CTRL_POST_INIT (1 << 5)
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#define STLINK_REG_DWT_CTRL_POST_PRESET (1 << 1)
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#define STLINK_REG_DWT_CTRL_CYCCNT_ENA (1 << 0)
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#define STLINK_REG_DWT_FUNCTION0 0xE0001028 // DWT Function Register 0
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#define STLINK_REG_DWT_FUNCTION1 0xE0001038 // DWT Function Register 1
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#define STLINK_REG_DWT_FUNCTION2 0xE0001048 // DWT Function Register 2
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#define STLINK_REG_DWT_FUNCTION3 0xE0001058 // DWT Function Register 3
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/* Instrumentation Trace Macrocell (ITM) Registers */
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#define STLINK_REG_ITM_TER 0xE0000E00 // ITM Trace Enable Register
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#define STLINK_REG_ITM_TER_PORTS_ALL (0xFFFFFFFF)
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#define STLINK_REG_ITM_TPR 0xE0000E40 // ITM Trace Privilege Register
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#define STLINK_REG_ITM_TPR_PORTS_ALL (0x0F)
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#define STLINK_REG_ITM_TCR 0xE0000E80 // ITM Trace Control Register
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#define STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16)
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#define STLINK_REG_ITM_TCR_SWO_ENA (1 << 4)
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#define STLINK_REG_ITM_TCR_DWT_ENA (1 << 3)
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#define STLINK_REG_ITM_TCR_SYNC_ENA (1 << 2)
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#define STLINK_REG_ITM_TCR_TS_ENA (1 << 1)
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#define STLINK_REG_ITM_TCR_ITM_ENA (1 << 0)
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#define STLINK_REG_ITM_TCC 0xE0000E90 // ITM Trace Cycle Count
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#define STLINK_REG_ITM_LAR 0xE0000FB0 // ITM Lock Access Register
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#define STLINK_REG_ITM_LAR_KEY 0xC5ACCE55
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/* Trace Port Interface (TPI) Registers */
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#define STLINK_REG_TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Reg
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#define STLINK_REG_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0)
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#define STLINK_REG_TPI_ACPR 0xE0040010 // TPI Async Clock Prescaler Register
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#define STLINK_REG_TPI_ACPR_MAX (0x1FFF)
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#define STLINK_REG_TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register
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#define STLINK_REG_TPI_SPPR_SWO_MANCHESTER (0x01 << 0)
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#define STLINK_REG_TPI_SPPR_SWO_NRZ (0x02 << 0)
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#define STLINK_REG_TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register
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#define STLINK_REG_TPI_FFCR_TRIG_IN (0x01 << 8)
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/* Application Interrupt and Reset Control Register */
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#define STLINK_REG_AIRCR 0xe000ed0c
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#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000
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#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004
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#define STLINK_REG_AIRCR_VECTRESET 0x00000001
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/* ARM Cortex-M7 Processor Technical Reference Manual */
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/* Cache Control and Status Register */
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#define STLINK_REG_CM7_CTR 0xE000ED7C
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#define STLINK_REG_CM7_CLIDR 0xE000ED78
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#define STLINK_REG_CM7_CCR 0xE000ED14
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#define STLINK_REG_CM7_CCR_DC (1 << 16)
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#define STLINK_REG_CM7_CCR_IC (1 << 17)
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#define STLINK_REG_CM7_CSSELR 0xE000ED84
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#define STLINK_REG_CM7_DCCSW 0xE000EF6C
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#define STLINK_REG_CM7_ICIALLU 0xE000EF50
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#define STLINK_REG_CM7_CCSIDR 0xE000ED80
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#endif // REGISTER_H
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