From df7c7d21728f9804225c04912b45e34578b0d9ca Mon Sep 17 00:00:00 2001 From: Brian Date: Wed, 11 Oct 2023 19:55:50 -0400 Subject: [PATCH 01/15] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every push and pull request to the main branch. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for third-party code, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation. Signed-off-by: Brian --- .github/workflows/codeql-buildscript.sh | 6 ++ .github/workflows/codeql.yml | 123 ++++++++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 .github/workflows/codeql-buildscript.sh create mode 100644 .github/workflows/codeql.yml diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh new file mode 100644 index 0000000..d626d42 --- /dev/null +++ b/.github/workflows/codeql-buildscript.sh @@ -0,0 +1,6 @@ +#!/usr/bin/env bash + +sudo apt-get -y update +sudo apt-get -y install libusb-1.0 libusb-1.0-0-dev libgtk-3-dev +make clean +make release -j$(nproc) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml new file mode 100644 index 0000000..eaa9599 --- /dev/null +++ b/.github/workflows/codeql.yml @@ -0,0 +1,123 @@ +# For most projects, this workflow file will not need changing; you simply need +# to commit it to your repository. +# +# You may wish to alter this file to override the set of languages analyzed, +# or to provide custom queries or build logic. +# +# ******** NOTE ******** +# We have attempted to detect the languages in your repository. Please check +# the `language` matrix defined below to confirm you have the correct set of +# supported CodeQL languages. +# +name: "CodeQL" + +on: + push: + branches: [ "main", "master" ] + pull_request: + # The branches below must be a subset of the branches above + branches: [ "main", "master" ] + schedule: + - cron: '28 21 * * 0' + +jobs: + analyze: + name: Analyze + # Runner size impacts CodeQL analysis time. To learn more, please see: + # - https://gh.io/recommended-hardware-resources-for-running-codeql + # - https://gh.io/supported-runners-and-hardware-resources + # - https://gh.io/using-larger-runners + # Consider using larger runners for possible analysis time improvements. + runs-on: ${{ (matrix.language == 'swift' && 'macos-latest') || 'ubuntu-20.04' }} + timeout-minutes: ${{ (matrix.language == 'swift' && 120) || 360 }} + permissions: + actions: read + contents: read + security-events: write + + strategy: + fail-fast: false + matrix: + language: [ 'cpp' ] + # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python', 'ruby', 'swift' ] + # Use only 'java' to analyze code written in Java, Kotlin or both + # Use only 'javascript' to analyze code written in JavaScript, TypeScript or both + # Learn more about CodeQL language support at https://aka.ms/codeql-docs/language-support + + steps: + - name: Checkout repository + uses: actions/checkout@v3 + with: + submodules: recursive + + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v2 + with: + languages: ${{ matrix.language }} + # If you wish to specify custom queries, you can do so here or in a config file. + # By default, queries listed here will override any specified in a config file. + # Prefix the list here with "+" to use these queries and those in the config file. + + # For more details on CodeQL's query packs, refer to: https://docs.github.com/en/code-security/code-scanning/automatically-scanning-your-code-for-vulnerabilities-and-errors/configuring-code-scanning#using-queries-in-ql-packs + # queries: security-extended,security-and-quality + queries: security-and-quality + + + # Autobuild attempts to build any compiled languages (C/C++, C#, Go, Java, or Swift). + # If this step fails, then you should remove it and run the build manually (see below) + #- name: Autobuild + # uses: github/codeql-action/autobuild@v2 + + # ℹī¸ Command-line programs to run using the OS shell. + # 📚 See https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions#jobsjob_idstepsrun + + # If the Autobuild fails above, remove it and uncomment the following three lines. + # modify them (or add more) to build your code if your project, please refer to the EXAMPLE below for guidance. + + - run: | + ./.github/workflows/codeql-buildscript.sh + + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v2 + with: + category: "/language:${{matrix.language}}" + upload: false + id: step1 + + # Filter out rules with low severity or high false positve rate + # Also filter out warnings in third-party code + - name: Filter out unwanted errors and warnings + uses: advanced-security/filter-sarif@v1 + with: + patterns: | + -**:cpp/path-injection + -**:cpp/world-writable-file-creation + -**:cpp/poorly-documented-function + -**:cpp/potentially-dangerous-function + -**:cpp/use-of-goto + -**:cpp/integer-multiplication-cast-to-long + -**:cpp/comparison-with-wider-type + -**:cpp/leap-year/* + -**:cpp/ambiguously-signed-bit-field + -**:cpp/suspicious-pointer-scaling + -**:cpp/suspicious-pointer-scaling-void + -**:cpp/unsigned-comparison-zero + -**/third*party/** + -**/3rd*party/** + -**/external/** + input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif + output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif + + - name: Upload SARIF + uses: github/codeql-action/upload-sarif@v2 + with: + sarif_file: ${{ steps.step1.outputs.sarif-output }} + category: "/language:${{matrix.language}}" + + - name: Archive CodeQL results + uses: actions/upload-artifact@v3 + with: + name: codeql-results + path: ${{ steps.step1.outputs.sarif-output }} + retention-days: 5 \ No newline at end of file From ed8fa62d098ad52bafc78507146899b5738f01d8 Mon Sep 17 00:00:00 2001 From: Brian Date: Wed, 18 Oct 2023 16:49:46 -0400 Subject: [PATCH 02/15] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/codeql.yml | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index eaa9599..3ef873f 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -14,11 +14,10 @@ name: "CodeQL" on: push: branches: [ "main", "master" ] - pull_request: - # The branches below must be a subset of the branches above - branches: [ "main", "master" ] schedule: - - cron: '28 21 * * 0' + - cron: '0 0 * * *' + pull_request: + branches: '*' jobs: analyze: @@ -103,21 +102,25 @@ jobs: -**:cpp/suspicious-pointer-scaling -**:cpp/suspicious-pointer-scaling-void -**:cpp/unsigned-comparison-zero - -**/third*party/** - -**/3rd*party/** - -**/external/** + -**/cmake*/Modules/** input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - - name: Upload SARIF + - name: Upload CodeQL results to code scanning uses: github/codeql-action/upload-sarif@v2 with: sarif_file: ${{ steps.step1.outputs.sarif-output }} category: "/language:${{matrix.language}}" - - name: Archive CodeQL results + - name: Upload CodeQL results as an artifact + if: success() || failure() uses: actions/upload-artifact@v3 with: name: codeql-results path: ${{ steps.step1.outputs.sarif-output }} - retention-days: 5 \ No newline at end of file + retention-days: 5 + + - name: Fail if an error is found + run: | + ./.github/workflows/fail_on_error.py \ + ${{ steps.step1.outputs.sarif-output }}/cpp.sarif From b9a0a49a5423706433796605fb1511882603f635 Mon Sep 17 00:00:00 2001 From: Brian Date: Fri, 20 Oct 2023 01:02:15 -0400 Subject: [PATCH 03/15] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/fail_on_error.py | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100755 .github/workflows/fail_on_error.py diff --git a/.github/workflows/fail_on_error.py b/.github/workflows/fail_on_error.py new file mode 100755 index 0000000..2979174 --- /dev/null +++ b/.github/workflows/fail_on_error.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 + +import json +import sys + +# Return whether SARIF file contains error-level results +def codeql_sarif_contain_error(filename): + with open(filename, 'r') as f: + s = json.load(f) + + for run in s.get('runs', []): + rules_metadata = run['tool']['driver']['rules'] + if not rules_metadata: + rules_metadata = run['tool']['extensions'][0]['rules'] + + for res in run.get('results', []): + if 'ruleIndex' in res: + rule_index = res['ruleIndex'] + elif 'rule' in res and 'index' in res['rule']: + rule_index = res['rule']['index'] + else: + continue + try: + rule_level = rules_metadata[rule_index]['defaultConfiguration']['level'] + except IndexError as e: + print(e, rule_index, len(rules_metadata)) + else: + if rule_level == 'error': + return True + return False + +if __name__ == "__main__": + if codeql_sarif_contain_error(sys.argv[1]): + sys.exit(1) From abf354a1558215fe9909c5d2c4947dd9aa35eb6c Mon Sep 17 00:00:00 2001 From: Brian Date: Sun, 29 Oct 2023 15:28:16 -0400 Subject: [PATCH 04/15] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/codeql.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index 3ef873f..8164922 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -12,8 +12,8 @@ name: "CodeQL" on: - push: - branches: [ "main", "master" ] + # push: + # branches: [ "main", "master" ] schedule: - cron: '0 0 * * *' pull_request: From 2d21188cdce20cfdcf9126044a2368a6ccc8dfc0 Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 14:51:19 +0000 Subject: [PATCH 05/15] first commit --- config/chips/L45x_L46x.chip | 2 ++ config/chips/L496x_L4A6x.chip | 2 ++ src/st-flash/flash.c | 24 +++++++++++++++ src/st-flash/flash_opts.c | 18 +++++------- src/stlink-lib/chipid.c | 16 ++++++++-- src/stlink-lib/chipid.h | 2 ++ src/stlink-lib/common.c | 3 ++ src/stlink-lib/common_flash.c | 55 ++++++++++++++++++++++++++++++++++- src/stlink-lib/common_flash.h | 2 ++ 9 files changed, 111 insertions(+), 13 deletions(-) diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index cbe948c..1c8fc2e 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -12,3 +12,5 @@ bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 flags swo +otp_base 0x1fff7000 +otp_size 0x400 // 1 KB \ No newline at end of file diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 24788c0..8a4a93b 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -12,3 +12,5 @@ bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE option_size 0x4 // 4 B flags swo +otp_base 0x1fff7000 +otp_size 0x400 // 1 KB \ No newline at end of file diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 0577ee1..6553298 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -61,6 +61,7 @@ static void usage(void) { puts("example write option control register1 byte: ./st-flash --area=optcr write 0xXXXXXXXX"); puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); + puts("example read OTP area: ./st-flash --area=otp read [path]"); } int32_t main(int32_t ac, char** av) { @@ -180,6 +181,18 @@ int32_t main(int32_t ac, char** av) { DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); err = stlink_write_option_bytes_boot_add32(sl, o.val); + } else if (o.area == FLASH_OTP) { + if(sl->otp_base == 0) { + err = -1; + printf("OTP Write Not implimented\n"); + goto on_error; + } + err = stlink_fwrite_flash(sl, o.filename, o.addr); + + if (err == -1) { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } } else { err = -1; printf("Unknown memory region\n"); @@ -284,6 +297,17 @@ int32_t main(int32_t ac, char** av) { } else { printf("%08x\n",option_byte); } + } else if (o.area == FLASH_OTP) { + if(sl->otp_base == 0) { + err = -1; + printf("OTP Read not implimented\n"); + goto on_error; + } + err = stlink_fread(sl, o.filename, 0, sl->otp_base, sl->otp_size); + if (err == -1) { + printf("could not read OTP area (%d)\n", err); + goto on_error; + } } } diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 300203a..cf80407 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,7 +86,6 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { - // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; @@ -270,13 +269,13 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) address; - } + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } uint32_t size; result = get_integer_from_char_array(av[2], &size); @@ -288,8 +287,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { break; } else if (o->area == FLASH_OTP) { - return bad_arg("TODO: otp not implemented yet"); - if (ac > 1) { return invalid_args("otp read: [path]"); } + if (ac > 1 || ac ==0 ) { return invalid_args("otp read: [path]"); } if (ac > 0) { o->filename = av[0]; } break; } else if (o->area == FLASH_OPTION_BYTES) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06edb26..1b6fc13 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -34,6 +34,7 @@ void dump_a_chip(struct stlink_chipid_params *dev) { DLOG("option_base 0x%x\n", dev->option_base); DLOG("option_size 0x%x\n", dev->option_size); DLOG("flags %d\n\n", dev->flags); + DLOG("otp_base %d\n\n", dev->otp_base); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { @@ -57,7 +58,6 @@ void process_chipfile(char *fname) { // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); - if (!fp) { perror(fname); return; @@ -180,8 +180,19 @@ void process_chipfile(char *fname) { fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } } - sscanf(value, "%x", &ts->flags); + } else if (strcmp(word, "otp_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->otp_base) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } + } else if (strcmp(word, "otp_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->otp_size) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } } else { fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } @@ -191,6 +202,7 @@ void process_chipfile(char *fname) { devicelist = ts; } + #if defined(STLINK_HAVE_DIRENT_H) #include diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 6726a74..cf97e66 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -21,6 +21,8 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; + uint32_t otp_base; + uint32_t otp_size; struct stlink_chipid_params *next; }; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index dbfcc8b..c470f90 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -290,6 +290,9 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->option_base = params->option_base; sl->option_size = params->option_size; sl->chip_flags = params->flags; + sl->otp_base = params->otp_base; + sl->otp_size = params->otp_size; + // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53..60d8f42 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1310,9 +1310,17 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * If the file is identified to be all-empty and four-bytes aligned, * still flash the whole file even if ignoring message is printed. */ - err = stlink_write_flash(sl, addr, mf.base, + + /* In case the address is within the OTP area we use a different flash method */ + if(addr >= sl->otp_base && addr <= sl->otp_base + sl->otp_size) { + err = stlink_write_otp(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty); + } else { + err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); + } + stlink_fwrite_finalize(sl, addr); unmap_file(&mf); return (err); @@ -1389,6 +1397,22 @@ int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uin return 0; } +// Check if an address and size are within the flash (otp area) +int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, uint32_t size) { + uint32_t logvar; + if (addr < sl->otp_base || addr >= (sl->otp_base + sl->otp_size)) { + logvar = sl->otp_base + sl->otp_size - 1; + ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->otp_base, logvar); + return (-1); + } + if ((addr + size) > (sl->otp_base + sl->otp_size)) { + logvar = sl->otp_base + sl->otp_size - addr; + ELOG("The size exceeds the size of the OTP Area (0x%08x bytes available)\n", logvar); + return (-1); + } + return 0; +} + // Check if an address is aligned with the beginning of a page int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { stm32_addr_t page = sl->flash_base; @@ -1408,6 +1432,9 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + + (void)eraseonly; + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); @@ -1437,7 +1464,33 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 if (eraseonly) { return (0); } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; + return (stlink_verify_write_flash(sl, addr, base, len)); +} + +int32_t stlink_write_otp(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + int32_t ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + + // Check the address and size validity + if (stlink_check_address_range_validity_otp(sl, addr, len) < 0) { + return (-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + ret = stlink_flashloader_start(sl, &fl); if (ret) return ret; diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 9b2b840..238f040 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -44,8 +44,10 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size); +int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, uint32_t size); int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); +int32_t stlink_write_otp(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); #endif // COMMON_FLASH_H From b1d99a2fc22af6935f714525641a01483c076b3c Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 15:04:10 +0000 Subject: [PATCH 06/15] cleaning ident --- config/chips/L45x_L46x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- src/st-flash/flash.c | 4 ++-- src/st-flash/flash_opts.c | 15 ++++++++------- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/common.c | 1 - 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 1c8fc2e..c32030b 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -13,4 +13,4 @@ option_base 0x0 option_size 0x0 flags swo otp_base 0x1fff7000 -otp_size 0x400 // 1 KB \ No newline at end of file +otp_size 0x400 // 1 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 8a4a93b..65fa3dc 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -13,4 +13,4 @@ option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE option_size 0x4 // 4 B flags swo otp_base 0x1fff7000 -otp_size 0x400 // 1 KB \ No newline at end of file +otp_size 0x400 // 1 KB diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6553298..c2cd77a 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -184,7 +184,7 @@ int32_t main(int32_t ac, char** av) { } else if (o.area == FLASH_OTP) { if(sl->otp_base == 0) { err = -1; - printf("OTP Write Not implimented\n"); + printf("OTP Write NOT implemented\n"); goto on_error; } err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -300,7 +300,7 @@ int32_t main(int32_t ac, char** av) { } else if (o.area == FLASH_OTP) { if(sl->otp_base == 0) { err = -1; - printf("OTP Read not implimented\n"); + printf("OTP Read NOT implemented\n"); goto on_error; } err = stlink_fread(sl, o.filename, 0, sl->otp_base, sl->otp_size); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index cf80407..8f88f6e 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,6 +86,7 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { + // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; @@ -269,13 +270,13 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) address; - } + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } uint32_t size; result = get_integer_from_char_array(av[2], &size); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 1b6fc13..77cbfb1 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -58,6 +58,7 @@ void process_chipfile(char *fname) { // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); + if (!fp) { perror(fname); return; @@ -202,7 +203,6 @@ void process_chipfile(char *fname) { devicelist = ts; } - #if defined(STLINK_HAVE_DIRENT_H) #include diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index c470f90..337fe6e 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -293,7 +293,6 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->otp_base = params->otp_base; sl->otp_size = params->otp_size; - // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { From 3cb15d7da2deb69a38940d1fa82570771252951b Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 15:14:19 +0000 Subject: [PATCH 07/15] final --- src/st-flash/flash.c | 1 + src/st-flash/flash_opts.c | 2 +- src/stlink-lib/chipid.c | 2 ++ src/stlink-lib/common_flash.c | 3 --- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index c2cd77a..0b7c0cf 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -62,6 +62,7 @@ static void usage(void) { puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); puts("example read OTP area: ./st-flash --area=otp read [path]"); + puts("example write OTP area: ./st-flash --area=otp write [path] 0xXXXXXXXX"); } int32_t main(int32_t ac, char** av) { diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 8f88f6e..e2d4154 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,7 +86,7 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { - + // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 77cbfb1..ceeed31 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -35,6 +35,7 @@ void dump_a_chip(struct stlink_chipid_params *dev) { DLOG("option_size 0x%x\n", dev->option_size); DLOG("flags %d\n\n", dev->flags); DLOG("otp_base %d\n\n", dev->otp_base); + DLOG("otp_size %d\n\n", dev->otp_size); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { @@ -181,6 +182,7 @@ void process_chipfile(char *fname) { fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } } + sscanf(value, "%x", &ts->flags); } else if (strcmp(word, "otp_base") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 60d8f42..5005a63 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1320,7 +1320,6 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); } - stlink_fwrite_finalize(sl, addr); unmap_file(&mf); return (err); @@ -1433,8 +1432,6 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - (void)eraseonly; - // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); From e122764f214fb9821b173a63f7ae18690611dc0a Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 22:58:05 +0000 Subject: [PATCH 08/15] forgot to include this --- inc/stlink.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/inc/stlink.h b/inc/stlink.h index dec608e..557a9ee 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -232,6 +232,9 @@ struct _stlink { uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx uint32_t max_trace_freq; // set by stlink_open_usb() + + uint32_t otp_base; + uint32_t otp_size; }; /* Functions defined in common.c */ From 99a2be4d287198ea8072e0db1865fc1757255b7b Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 17:27:05 +0100 Subject: [PATCH 09/15] initial commit --- c0.patch | 618 ++++++++++++++++++++++++++++++++++ doc/supported_devices.md | 1 + inc/stm32.h | 30 +- inc/stm32flash.h | 24 ++ src/stlink-lib/chipid.c | 4 +- src/stlink-lib/common_flash.c | 98 ++++-- src/stlink-lib/flash_loader.c | 31 +- src/stlink-lib/option_bytes.c | 107 +++++- 8 files changed, 870 insertions(+), 43 deletions(-) create mode 100644 c0.patch diff --git a/c0.patch b/c0.patch new file mode 100644 index 0000000..5b59834 --- /dev/null +++ b/c0.patch @@ -0,0 +1,618 @@ +diff --git a/doc/supported_devices.md b/doc/supported_devices.md +index 2e96dcd..103c7fb 100644 +--- a/doc/supported_devices.md ++++ b/doc/supported_devices.md +@@ -6,6 +6,7 @@ More commonly these are: + | Product-Family | ARM Cortex Core | Product Line | + | -------------- | --------------- | ---------------------------------------------------------- | + | STM32F0 | M0 | | ++| STM32C0 | M0+ | | + | STM32G0 | M0+ | | + | STM32L0 | M0+ | | + | STM32F10**0** | M3 | Value line | +diff --git a/inc/stm32.h b/inc/stm32.h +index cf9a8a2..017ea0a 100644 +--- a/inc/stm32.h ++++ b/inc/stm32.h +@@ -51,17 +51,18 @@ enum stm32_core_id { + /* STM32 flash types */ + enum stm32_flash_type { + STM32_FLASH_TYPE_UNKNOWN = 0, +- STM32_FLASH_TYPE_F0_F1_F3 = 1, +- STM32_FLASH_TYPE_F1_XL = 2, +- STM32_FLASH_TYPE_F2_F4 = 3, +- STM32_FLASH_TYPE_F7 = 4, +- STM32_FLASH_TYPE_G0 = 5, +- STM32_FLASH_TYPE_G4 = 6, +- STM32_FLASH_TYPE_H7 = 7, +- STM32_FLASH_TYPE_L0_L1 = 8, +- STM32_FLASH_TYPE_L4 = 9, +- STM32_FLASH_TYPE_L5_U5_H5 = 10, +- STM32_FLASH_TYPE_WB_WL = 11, ++ STM32_FLASH_TYPE_C0 = 1, ++ STM32_FLASH_TYPE_F0_F1_F3 = 2, ++ STM32_FLASH_TYPE_F1_XL = 3, ++ STM32_FLASH_TYPE_F2_F4 = 4, ++ STM32_FLASH_TYPE_F7 = 5, ++ STM32_FLASH_TYPE_G0 = 6, ++ STM32_FLASH_TYPE_G4 = 7, ++ STM32_FLASH_TYPE_H7 = 8, ++ STM32_FLASH_TYPE_L0_L1 = 9, ++ STM32_FLASH_TYPE_L4 = 10, ++ STM32_FLASH_TYPE_L5_U5_H5 = 11, ++ STM32_FLASH_TYPE_WB_WL = 12, + }; + + /* STM32 chip-ids */ +@@ -102,6 +103,7 @@ enum stm32_chipids { + STM32_CHIPID_F0 = 0x440, + STM32_CHIPID_F412 = 0x441, + STM32_CHIPID_F09x = 0x442, ++ STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ + STM32_CHIPID_F0xx_SMALL = 0x444, + STM32_CHIPID_F04 = 0x445, + STM32_CHIPID_F303_HD = 0x446, /* high density */ +@@ -111,6 +113,7 @@ enum stm32_chipids { + STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_F76xxx = 0x451, + STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ ++ STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ + STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_L0_CAT1 = 0x457, + STM32_CHIPID_F410 = 0x458, +@@ -136,6 +139,8 @@ enum stm32_chipids { + }; + + /* Constant STM32 option bytes base memory address */ ++#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) ++ + #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) + + #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) +@@ -189,6 +194,9 @@ enum stm32_chipids { + #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 + #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + ++#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" ++#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" ++ + #define STM32F1_RCC_AHBENR 0x40021014 + #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +diff --git a/inc/stm32flash.h b/inc/stm32flash.h +index 69c6206..b5e47e0 100644 +--- a/inc/stm32flash.h ++++ b/inc/stm32flash.h +@@ -58,6 +58,30 @@ + #define FLASH_OBR_OFF ((uint32_t)0x1c) + #define FLASH_WRPR_OFF ((uint32_t)0x20) + ++// == STM32C0 == (RM0490) ++// C0 Flash registers ++#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) ++#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) ++#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) ++#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) ++#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) ++#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) ++ ++// C0 Flash control register ++#define FLASH_C0_CR_PNB 3 ++#define FLASH_C0_CR_STRT 16 ++#define FLASH_C0_CR_OPTSTRT 17 ++#define FLASH_C0_CR_OBL_LAUNCH 27 ++#define FLASH_C0_CR_OPTLOCK 30 ++#define FLASH_C0_CR_LOCK 31 ++ ++// C0 Flash status register ++#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] ++#define FLASH_C0_SR_PROGERR 3 ++#define FLASH_C0_SR_WRPERR 4 ++#define FLASH_C0_SR_PGAERR 5 ++#define FLASH_C0_SR_BSY 16 ++ + // == STM32F0 == + #define FLASH_F0_OPTKEY1 0x45670123 + #define FLASH_F0_OPTKEY2 0xcdef89ab +diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c +index 06edb26..86f01f4 100644 +--- a/src/stlink-lib/chipid.c ++++ b/src/stlink-lib/chipid.c +@@ -97,7 +97,9 @@ void process_chipfile(char *fname) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + // Match human readable flash_type with enum stm32_flash_type { }. +- if (strcmp(value, "F0_F1_F3") == 0) { ++ if(strcmp(value, "C0") == 0) { ++ ts->flash_type = STM32_FLASH_TYPE_C0; ++ } else if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; +diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c +index 3038b53..491cf46 100644 +--- a/src/stlink-lib/common_flash.c ++++ b/src/stlink-lib/common_flash.c +@@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { + uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { + uint32_t reg, res; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; +@@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { + uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + +- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_lock_shift = FLASH_C0_CR_LOCK; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { +@@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { + static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { + uint32_t sr_reg; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_reg = FLASH_C0_SR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; +@@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) + + void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; +@@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { + uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { + uint32_t res, sr_reg; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_reg = FLASH_C0_SR; ++ } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || ++ (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; +@@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { + uint32_t sr_busy_shift; + uint32_t res; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || +- (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_busy_shift = FLASH_C0_SR_BSY; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL || ++ sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; +@@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; ++ WRPERR = (1 << FLASH_C0_SR_WRPERR); ++ PROGERR = (1 << FLASH_C0_SR_PROGERR); ++ PGAERR = (1 << FLASH_C0_SR_PGAERR); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; +@@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { + uint32_t cr_reg; + uint32_t n; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_lock_shift = FLASH_C0_CR_LOCK; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { +@@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { + * definitive lock of the FPEC block until next reset. + */ + +- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ key_reg = FLASH_C0_KEYR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; +@@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { + int32_t active_bit_level = 1; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optcr_reg = FLASH_C0_CR; ++ optlock_shift = FLASH_C0_CR_OPTLOCK; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; +@@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { + uint32_t n; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optcr_reg = FLASH_C0_CR; ++ optlock_shift = FLASH_C0_CR_OPTLOCK; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; +@@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optkey_reg = FLASH_C0_OPT_KEYR; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; +@@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; +@@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { + static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg, val; + +- if (sl->flash_type == STM32_FLASH_TYPE_G0 || +- sl->flash_type == STM32_FLASH_TYPE_G4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || ++ sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = FLASH_Gx_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + cr_reg = FLASH_L5_NSCR; +@@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { + static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg; + +- if (sl->flash_type == STM32_FLASH_TYPE_G0 || +- sl->flash_type == STM32_FLASH_TYPE_G4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || ++ sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = FLASH_Gx_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + cr_reg = FLASH_L5_NSCR; +@@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { + uint32_t val, cr_reg, cr_strt; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_strt = 1 << FLASH_C0_CR_STRT; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { +@@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { + static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { + uint32_t val, cr_reg, cr_mer, cr_pg; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_mer = 1 << FLASH_CR_MER; ++ cr_pg = 1 << FLASH_CR_PG; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; +@@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || +- sl->flash_type == STM32_FLASH_TYPE_WB_WL) { ++ sl->flash_type == STM32_FLASH_TYPE_WB_WL || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit +@@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, FLASH_WB_CR, val); ++ } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ ++ val &= ~(0xF << FLASH_C0_CR_PNB); ++ val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); ++ ++ stlink_write_debug32(sl, FLASH_C0_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit +diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c +index ea1f6d9..0d01dfd 100644 +--- a/src/stlink-lib/flash_loader.c ++++ b/src/stlink-lib/flash_loader.c +@@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { + + x = read_flash_cr(sl, bank); + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ x |= (1 << FLASH_CR_PG); ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; +- x |= 1 << FLASH_CR_PG; ++ x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; +- x |= 1 << FLASH_CR_PG; ++ x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = FLASH_L4_CR; + x &= ~FLASH_L4_CR_OPBITS; +@@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ rcc = STM32C0_RCC_AHBENR; ++ rcc_dma_mask = STM32C0_RCC_DMAEN; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; +@@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || +- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { +- ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); ++ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { ++ ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit +@@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + + int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + uint32_t off; ++ + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4)) { +@@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || +- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { ++ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { + DLOG("Starting %3u page write\n", len / sl->flash_pgsz); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { +- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); ++ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fflush(stdout); + } + +@@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { +- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); ++ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fflush(stdout); + } + +@@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading +- fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, ++ fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, + (len + sl->flash_pgsz - 1) / sl->flash_pgsz); + fflush(stdout); + } +@@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || ++ if ((sl->flash_type == STM32_FLASH_TYPE_C0) || ++ (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || +diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c +index ee03dce..2ee45c9 100644 +--- a/src/stlink-lib/option_bytes.c ++++ b/src/stlink-lib/option_bytes.c +@@ -18,6 +18,101 @@ + #include "md5.h" + #include "read_write.h" + ++/** ++ * Read option control register C0 ++ * @param sl ++ * @param option_byte ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { ++ return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); ++} ++ ++/** ++ * Read option bytes C0 ++ * @param sl ++ * @param option_byte ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { ++ return stlink_read_option_control_register_c0(sl, option_byte); ++} ++ ++/** ++ * Write option control register C0 ++ * @param sl ++ * @param option_cr ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { ++ int32_t ret = 0; ++ ++ clear_flash_error(sl); ++ ++ if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) ++ return ret; ++ ++ wait_flash_busy(sl); ++ ++ uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); ++ if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) ++ return ret; ++ ++ wait_flash_busy(sl); ++ ++ if ((ret = check_flash_error(sl))) ++ return ret; ++ ++ // trigger the load of option bytes into option registers ++ cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); ++ stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); ++ ++ return ret; ++} ++ ++/** ++ * Write option bytes C0 ++ * @param sl ++ * @param addr of the memory mapped option bytes ++ * @param base option bytes ++ * @param len of option bytes ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { ++#if 0 ++ uint32_t val; ++ int32_t ret = 0; ++ (void)len; ++ uint32_t data; ++ ++ clear_flash_error(sl); ++ ++ write_uint32((unsigned char *)&data, *(uint32_t *)(base)); ++ WLOG("Writing option bytes %#10x to %#10x\n", data, addr); ++ stlink_write_debug32(sl, FLASH_C0_OPTR, data); ++ ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ val |= (1 << FLASH_C0_CR_OPTSTRT); ++ stlink_write_debug32(sl, FLASH_C0_CR, val); ++ ++ wait_flash_busy(sl); ++ ++ ret = check_flash_error(sl); ++ ++ // trigger the load of option bytes into option registers ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ val |= (1 << FLASH_C0_CR_OBL_LAUNCH); ++ stlink_write_debug32(sl, FLASH_C0_CR, val); ++ ++ return (ret); ++#else ++ (void)addr; ++ (void)len; ++ ++ return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); ++#endif ++} ++ + /** + * Read option control register F0 + * @param sl +@@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, sl->option_base, option_byte); + } + +- + /** + * Write option bytes + * @param sl +@@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ ret = stlink_write_option_bytes_c0(sl, addr, base, len); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, addr, base, len); +@@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ return stlink_read_option_control_register_c0(sl, option_byte); + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); +@@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ ret = stlink_write_option_control_register_c0(sl, option_cr); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_cr); +@@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + } + + switch (sl->chip_id) { ++ case STM32_CHIPID_C011xx: ++ case STM32_CHIPID_C031xx: ++ return stlink_read_option_bytes_c0(sl, option_byte); + case STM32_CHIPID_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STM32_CHIPID_F4: diff --git a/doc/supported_devices.md b/doc/supported_devices.md index 2e96dcd..103c7fb 100644 --- a/doc/supported_devices.md +++ b/doc/supported_devices.md @@ -6,6 +6,7 @@ More commonly these are: | Product-Family | ARM Cortex Core | Product Line | | -------------- | --------------- | ---------------------------------------------------------- | | STM32F0 | M0 | | +| STM32C0 | M0+ | | | STM32G0 | M0+ | | | STM32L0 | M0+ | | | STM32F10**0** | M3 | Value line | diff --git a/inc/stm32.h b/inc/stm32.h index cf9a8a2..017ea0a 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -51,17 +51,18 @@ enum stm32_core_id { /* STM32 flash types */ enum stm32_flash_type { STM32_FLASH_TYPE_UNKNOWN = 0, - STM32_FLASH_TYPE_F0_F1_F3 = 1, - STM32_FLASH_TYPE_F1_XL = 2, - STM32_FLASH_TYPE_F2_F4 = 3, - STM32_FLASH_TYPE_F7 = 4, - STM32_FLASH_TYPE_G0 = 5, - STM32_FLASH_TYPE_G4 = 6, - STM32_FLASH_TYPE_H7 = 7, - STM32_FLASH_TYPE_L0_L1 = 8, - STM32_FLASH_TYPE_L4 = 9, - STM32_FLASH_TYPE_L5_U5_H5 = 10, - STM32_FLASH_TYPE_WB_WL = 11, + STM32_FLASH_TYPE_C0 = 1, + STM32_FLASH_TYPE_F0_F1_F3 = 2, + STM32_FLASH_TYPE_F1_XL = 3, + STM32_FLASH_TYPE_F2_F4 = 4, + STM32_FLASH_TYPE_F7 = 5, + STM32_FLASH_TYPE_G0 = 6, + STM32_FLASH_TYPE_G4 = 7, + STM32_FLASH_TYPE_H7 = 8, + STM32_FLASH_TYPE_L0_L1 = 9, + STM32_FLASH_TYPE_L4 = 10, + STM32_FLASH_TYPE_L5_U5_H5 = 11, + STM32_FLASH_TYPE_WB_WL = 12, }; /* STM32 chip-ids */ @@ -102,6 +103,7 @@ enum stm32_chipids { STM32_CHIPID_F0 = 0x440, STM32_CHIPID_F412 = 0x441, STM32_CHIPID_F09x = 0x442, + STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ STM32_CHIPID_F0xx_SMALL = 0x444, STM32_CHIPID_F04 = 0x445, STM32_CHIPID_F303_HD = 0x446, /* high density */ @@ -111,6 +113,7 @@ enum stm32_chipids { STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, @@ -136,6 +139,8 @@ enum stm32_chipids { }; /* Constant STM32 option bytes base memory address */ +#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) + #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) @@ -189,6 +194,9 @@ enum stm32_chipids { #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 +#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" +#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" + #define STM32F1_RCC_AHBENR 0x40021014 #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 69c6206..b5e47e0 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -58,6 +58,30 @@ #define FLASH_OBR_OFF ((uint32_t)0x1c) #define FLASH_WRPR_OFF ((uint32_t)0x20) +// == STM32C0 == (RM0490) +// C0 Flash registers +#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) +#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) +#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) +#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) +#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) + +// C0 Flash control register +#define FLASH_C0_CR_PNB 3 +#define FLASH_C0_CR_STRT 16 +#define FLASH_C0_CR_OPTSTRT 17 +#define FLASH_C0_CR_OBL_LAUNCH 27 +#define FLASH_C0_CR_OPTLOCK 30 +#define FLASH_C0_CR_LOCK 31 + +// C0 Flash status register +#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] +#define FLASH_C0_SR_PROGERR 3 +#define FLASH_C0_SR_WRPERR 4 +#define FLASH_C0_SR_PGAERR 5 +#define FLASH_C0_SR_BSY 16 + // == STM32F0 == #define FLASH_F0_OPTKEY1 0x45670123 #define FLASH_F0_OPTKEY2 0xcdef89ab diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06edb26..86f01f4 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -97,7 +97,9 @@ void process_chipfile(char *fname) { buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); // Match human readable flash_type with enum stm32_flash_type { }. - if (strcmp(value, "F0_F1_F3") == 0) { + if(strcmp(value, "C0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_C0; + } else if (strcmp(value, "F0_F1_F3") == 0) { ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; } else if (strcmp(value, "F1_XL") == 0) { ts->flash_type = STM32_FLASH_TYPE_F1_XL; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53..491cf46 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { uint32_t reg, res; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; @@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_lock_shift = FLASH_C0_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { @@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_reg = FLASH_C0_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; @@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); + break; case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; @@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_reg = FLASH_C0_SR; + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; @@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; uint32_t res; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_busy_shift = FLASH_C0_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL || + sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; @@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; + WRPERR = (1 << FLASH_C0_SR_WRPERR); + PROGERR = (1 << FLASH_C0_SR_PROGERR); + PGAERR = (1 << FLASH_C0_SR_PGAERR); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; @@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_lock_shift = FLASH_C0_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + key_reg = FLASH_C0_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; @@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { int32_t active_bit_level = 1; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optcr_reg = FLASH_C0_CR; + optlock_shift = FLASH_C0_CR_OPTLOCK; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; @@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optcr_reg = FLASH_C0_CR; + optlock_shift = FLASH_C0_CR_OPTLOCK; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; @@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optkey_reg = FLASH_C0_OPT_KEYR; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; @@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; @@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, val; - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; @@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg; - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; @@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_strt = 1 << FLASH_C0_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { @@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; @@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || - sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_C0) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit @@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, FLASH_WB_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, FLASH_C0_CR, &val); + + val &= ~(0xF << FLASH_C0_CR_PNB); + val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); + + stlink_write_debug32(sl, FLASH_C0_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ea1f6d9..0d01dfd 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; x &= ~FLASH_L4_CR_OPBITS; @@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + rcc = STM32C0_RCC_AHBENR; + rcc_dma_mask = STM32C0_RCC_DMAEN; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; @@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || + sl->flash_type == STM32_FLASH_TYPE_C0) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t off; + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || (sl->flash_type == STM32_FLASH_TYPE_L4)) { @@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || + sl->flash_type == STM32_FLASH_TYPE_C0) { DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } @@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } @@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, (len + sl->flash_pgsz - 1) / sl->flash_pgsz); fflush(stdout); } @@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + if ((sl->flash_type == STM32_FLASH_TYPE_C0) || + (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index ee03dce..2ee45c9 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -18,6 +18,101 @@ #include "md5.h" #include "read_write.h" +/** + * Read option control register C0 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); +} + +/** + * Read option bytes C0 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_c0(sl, option_byte); +} + +/** + * Write option control register C0 + * @param sl + * @param option_cr + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; + + clear_flash_error(sl); + + if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) + return ret; + + wait_flash_busy(sl); + + uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); + if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) + return ret; + + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) + return ret; + + // trigger the load of option bytes into option registers + cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); + + return ret; +} + +/** + * Write option bytes C0 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +#if 0 + uint32_t val; + int32_t ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, FLASH_C0_OPTR, data); + + stlink_read_debug32(sl, FLASH_C0_CR, &val); + val |= (1 << FLASH_C0_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_C0_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // trigger the load of option bytes into option registers + stlink_read_debug32(sl, FLASH_C0_CR, &val); + val |= (1 << FLASH_C0_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_C0_CR, val); + + return (ret); +#else + (void)addr; + (void)len; + + return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); +#endif +} + /** * Read option control register F0 * @param sl @@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, sl->option_base, option_byte); } - /** * Write option bytes * @param sl @@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + ret = stlink_write_option_bytes_c0(sl, addr, base, len); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, addr, base, len); @@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + return stlink_read_option_control_register_c0(sl, option_byte); case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); @@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + ret = stlink_write_option_control_register_c0(sl, option_cr); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_cr); @@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { + case STM32_CHIPID_C011xx: + case STM32_CHIPID_C031xx: + return stlink_read_option_bytes_c0(sl, option_byte); case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); case STM32_CHIPID_F4: From eb083ae7539eccd3532156a829b3a8008736485b Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 17:40:28 +0100 Subject: [PATCH 10/15] removed redundant lines --- src/stlink-lib/option_bytes.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 2ee45c9..d49c346 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -79,38 +79,10 @@ static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t op * @return 0 on success, -ve on failure. */ static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { -#if 0 - uint32_t val; - int32_t ret = 0; - (void)len; - uint32_t data; - - clear_flash_error(sl); - - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, FLASH_C0_OPTR, data); - - stlink_read_debug32(sl, FLASH_C0_CR, &val); - val |= (1 << FLASH_C0_CR_OPTSTRT); - stlink_write_debug32(sl, FLASH_C0_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - - // trigger the load of option bytes into option registers - stlink_read_debug32(sl, FLASH_C0_CR, &val); - val |= (1 << FLASH_C0_CR_OBL_LAUNCH); - stlink_write_debug32(sl, FLASH_C0_CR, val); - - return (ret); -#else (void)addr; (void)len; return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); -#endif } /** From 4a7b8cdb2678e64fccedf4f49508c4f5ce80868e Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 18:19:04 +0100 Subject: [PATCH 11/15] removed the patch file itself --- c0.patch | 618 ------------------------------------------------------- 1 file changed, 618 deletions(-) delete mode 100644 c0.patch diff --git a/c0.patch b/c0.patch deleted file mode 100644 index 5b59834..0000000 --- a/c0.patch +++ /dev/null @@ -1,618 +0,0 @@ -diff --git a/doc/supported_devices.md b/doc/supported_devices.md -index 2e96dcd..103c7fb 100644 ---- a/doc/supported_devices.md -+++ b/doc/supported_devices.md -@@ -6,6 +6,7 @@ More commonly these are: - | Product-Family | ARM Cortex Core | Product Line | - | -------------- | --------------- | ---------------------------------------------------------- | - | STM32F0 | M0 | | -+| STM32C0 | M0+ | | - | STM32G0 | M0+ | | - | STM32L0 | M0+ | | - | STM32F10**0** | M3 | Value line | -diff --git a/inc/stm32.h b/inc/stm32.h -index cf9a8a2..017ea0a 100644 ---- a/inc/stm32.h -+++ b/inc/stm32.h -@@ -51,17 +51,18 @@ enum stm32_core_id { - /* STM32 flash types */ - enum stm32_flash_type { - STM32_FLASH_TYPE_UNKNOWN = 0, -- STM32_FLASH_TYPE_F0_F1_F3 = 1, -- STM32_FLASH_TYPE_F1_XL = 2, -- STM32_FLASH_TYPE_F2_F4 = 3, -- STM32_FLASH_TYPE_F7 = 4, -- STM32_FLASH_TYPE_G0 = 5, -- STM32_FLASH_TYPE_G4 = 6, -- STM32_FLASH_TYPE_H7 = 7, -- STM32_FLASH_TYPE_L0_L1 = 8, -- STM32_FLASH_TYPE_L4 = 9, -- STM32_FLASH_TYPE_L5_U5_H5 = 10, -- STM32_FLASH_TYPE_WB_WL = 11, -+ STM32_FLASH_TYPE_C0 = 1, -+ STM32_FLASH_TYPE_F0_F1_F3 = 2, -+ STM32_FLASH_TYPE_F1_XL = 3, -+ STM32_FLASH_TYPE_F2_F4 = 4, -+ STM32_FLASH_TYPE_F7 = 5, -+ STM32_FLASH_TYPE_G0 = 6, -+ STM32_FLASH_TYPE_G4 = 7, -+ STM32_FLASH_TYPE_H7 = 8, -+ STM32_FLASH_TYPE_L0_L1 = 9, -+ STM32_FLASH_TYPE_L4 = 10, -+ STM32_FLASH_TYPE_L5_U5_H5 = 11, -+ STM32_FLASH_TYPE_WB_WL = 12, - }; - - /* STM32 chip-ids */ -@@ -102,6 +103,7 @@ enum stm32_chipids { - STM32_CHIPID_F0 = 0x440, - STM32_CHIPID_F412 = 0x441, - STM32_CHIPID_F09x = 0x442, -+ STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ - STM32_CHIPID_F0xx_SMALL = 0x444, - STM32_CHIPID_F04 = 0x445, - STM32_CHIPID_F303_HD = 0x446, /* high density */ -@@ -111,6 +113,7 @@ enum stm32_chipids { - STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ - STM32_CHIPID_F76xxx = 0x451, - STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ -+ STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ - STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_L0_CAT1 = 0x457, - STM32_CHIPID_F410 = 0x458, -@@ -136,6 +139,8 @@ enum stm32_chipids { - }; - - /* Constant STM32 option bytes base memory address */ -+#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) -+ - #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) - - #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) -@@ -189,6 +194,9 @@ enum stm32_chipids { - #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 - #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -+#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" -+#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" -+ - #define STM32F1_RCC_AHBENR 0x40021014 - #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -diff --git a/inc/stm32flash.h b/inc/stm32flash.h -index 69c6206..b5e47e0 100644 ---- a/inc/stm32flash.h -+++ b/inc/stm32flash.h -@@ -58,6 +58,30 @@ - #define FLASH_OBR_OFF ((uint32_t)0x1c) - #define FLASH_WRPR_OFF ((uint32_t)0x20) - -+// == STM32C0 == (RM0490) -+// C0 Flash registers -+#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) -+#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) -+#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) -+#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) -+#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) -+#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) -+ -+// C0 Flash control register -+#define FLASH_C0_CR_PNB 3 -+#define FLASH_C0_CR_STRT 16 -+#define FLASH_C0_CR_OPTSTRT 17 -+#define FLASH_C0_CR_OBL_LAUNCH 27 -+#define FLASH_C0_CR_OPTLOCK 30 -+#define FLASH_C0_CR_LOCK 31 -+ -+// C0 Flash status register -+#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] -+#define FLASH_C0_SR_PROGERR 3 -+#define FLASH_C0_SR_WRPERR 4 -+#define FLASH_C0_SR_PGAERR 5 -+#define FLASH_C0_SR_BSY 16 -+ - // == STM32F0 == - #define FLASH_F0_OPTKEY1 0x45670123 - #define FLASH_F0_OPTKEY2 0xcdef89ab -diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c -index 06edb26..86f01f4 100644 ---- a/src/stlink-lib/chipid.c -+++ b/src/stlink-lib/chipid.c -@@ -97,7 +97,9 @@ void process_chipfile(char *fname) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - // Match human readable flash_type with enum stm32_flash_type { }. -- if (strcmp(value, "F0_F1_F3") == 0) { -+ if(strcmp(value, "C0") == 0) { -+ ts->flash_type = STM32_FLASH_TYPE_C0; -+ } else if (strcmp(value, "F0_F1_F3") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; - } else if (strcmp(value, "F1_XL") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F1_XL; -diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c -index 3038b53..491cf46 100644 ---- a/src/stlink-lib/common_flash.c -+++ b/src/stlink-lib/common_flash.c -@@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { - uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { - uint32_t reg, res; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; -@@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - -- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_lock_shift = FLASH_C0_CR_LOCK; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { -@@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { - static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { - uint32_t sr_reg; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_reg = FLASH_C0_SR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; -@@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) - - void clear_flash_error(stlink_t *sl) { - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; -@@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { - uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { - uint32_t res, sr_reg; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_reg = FLASH_C0_SR; -+ } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -+ (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; -@@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - uint32_t res; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || -- (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_busy_shift = FLASH_C0_SR_BSY; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL || -+ sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; -@@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { - WRPERR = PROGERR = PGAERR = 0; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; -+ WRPERR = (1 << FLASH_C0_SR_WRPERR); -+ PROGERR = (1 << FLASH_C0_SR_PROGERR); -+ PGAERR = (1 << FLASH_C0_SR_PGAERR); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; -@@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { - uint32_t cr_reg; - uint32_t n; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_lock_shift = FLASH_C0_CR_LOCK; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -@@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { - * definitive lock of the FPEC block until next reset. - */ - -- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ key_reg = FLASH_C0_KEYR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; -@@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { - int32_t active_bit_level = 1; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optcr_reg = FLASH_C0_CR; -+ optlock_shift = FLASH_C0_CR_OPTLOCK; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; -@@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { - uint32_t n; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optcr_reg = FLASH_C0_CR; -+ optlock_shift = FLASH_C0_CR_OPTLOCK; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; -@@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { - uint32_t optkey2 = FLASH_OPTKEY2; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optkey_reg = FLASH_C0_OPT_KEYR; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; -@@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; -@@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { - static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg, val; - -- if (sl->flash_type == STM32_FLASH_TYPE_G0 || -- sl->flash_type == STM32_FLASH_TYPE_G4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || -+ sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - cr_reg = FLASH_L5_NSCR; -@@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { - static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg; - -- if (sl->flash_type == STM32_FLASH_TYPE_G0 || -- sl->flash_type == STM32_FLASH_TYPE_G4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || -+ sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - cr_reg = FLASH_L5_NSCR; -@@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { - uint32_t val, cr_reg, cr_strt; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_strt = 1 << FLASH_C0_CR_STRT; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { -@@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { - static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_mer = 1 << FLASH_CR_MER; -+ cr_pg = 1 << FLASH_CR_PG; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; -@@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -- sl->flash_type == STM32_FLASH_TYPE_WB_WL) { -+ sl->flash_type == STM32_FLASH_TYPE_WB_WL || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit -@@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, FLASH_WB_CR, val); -+ } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ -+ val &= ~(0xF << FLASH_C0_CR_PNB); -+ val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); -+ -+ stlink_write_debug32(sl, FLASH_C0_CR, val); - } - - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit -diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c -index ea1f6d9..0d01dfd 100644 ---- a/src/stlink-lib/flash_loader.c -+++ b/src/stlink-lib/flash_loader.c -@@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { - - x = read_flash_cr(sl, bank); - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ x |= (1 << FLASH_CR_PG); -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; -- x |= 1 << FLASH_CR_PG; -+ x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; -- x |= 1 << FLASH_CR_PG; -+ x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = FLASH_L4_CR; - x &= ~FLASH_L4_CR_OPBITS; -@@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { - rcc = rcc_dma_mask = value = 0; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ rcc = STM32C0_RCC_AHBENR; -+ rcc_dma_mask = STM32C0_RCC_DMAEN; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; -@@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || -- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { -- ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); -+ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { -+ ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit -@@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - - int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { - uint32_t off; -+ - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4)) { -@@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || -- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { -+ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { - DLOG("Starting %3u page write\n", len / sl->flash_pgsz); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { -- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); -+ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); - fflush(stdout); - } - -@@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { -- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); -+ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); - fflush(stdout); - } - -@@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading -- fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, -+ fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, - (len + sl->flash_pgsz - 1) / sl->flash_pgsz); - fflush(stdout); - } -@@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -+ if ((sl->flash_type == STM32_FLASH_TYPE_C0) || -+ (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || -diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c -index ee03dce..2ee45c9 100644 ---- a/src/stlink-lib/option_bytes.c -+++ b/src/stlink-lib/option_bytes.c -@@ -18,6 +18,101 @@ - #include "md5.h" - #include "read_write.h" - -+/** -+ * Read option control register C0 -+ * @param sl -+ * @param option_byte -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { -+ return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); -+} -+ -+/** -+ * Read option bytes C0 -+ * @param sl -+ * @param option_byte -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { -+ return stlink_read_option_control_register_c0(sl, option_byte); -+} -+ -+/** -+ * Write option control register C0 -+ * @param sl -+ * @param option_cr -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { -+ int32_t ret = 0; -+ -+ clear_flash_error(sl); -+ -+ if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) -+ return ret; -+ -+ wait_flash_busy(sl); -+ -+ uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); -+ if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) -+ return ret; -+ -+ wait_flash_busy(sl); -+ -+ if ((ret = check_flash_error(sl))) -+ return ret; -+ -+ // trigger the load of option bytes into option registers -+ cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); -+ stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); -+ -+ return ret; -+} -+ -+/** -+ * Write option bytes C0 -+ * @param sl -+ * @param addr of the memory mapped option bytes -+ * @param base option bytes -+ * @param len of option bytes -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { -+#if 0 -+ uint32_t val; -+ int32_t ret = 0; -+ (void)len; -+ uint32_t data; -+ -+ clear_flash_error(sl); -+ -+ write_uint32((unsigned char *)&data, *(uint32_t *)(base)); -+ WLOG("Writing option bytes %#10x to %#10x\n", data, addr); -+ stlink_write_debug32(sl, FLASH_C0_OPTR, data); -+ -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ val |= (1 << FLASH_C0_CR_OPTSTRT); -+ stlink_write_debug32(sl, FLASH_C0_CR, val); -+ -+ wait_flash_busy(sl); -+ -+ ret = check_flash_error(sl); -+ -+ // trigger the load of option bytes into option registers -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ val |= (1 << FLASH_C0_CR_OBL_LAUNCH); -+ stlink_write_debug32(sl, FLASH_C0_CR, val); -+ -+ return (ret); -+#else -+ (void)addr; -+ (void)len; -+ -+ return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); -+#endif -+} -+ - /** - * Read option control register F0 - * @param sl -@@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_debug32(sl, sl->option_base, option_byte); - } - -- - /** - * Write option bytes - * @param sl -@@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ ret = stlink_write_option_bytes_c0(sl, addr, base, len); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, addr, base, len); -@@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ return stlink_read_option_control_register_c0(sl, option_byte); - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); -@@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ ret = stlink_write_option_control_register_c0(sl, option_cr); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_cr); -@@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - } - - switch (sl->chip_id) { -+ case STM32_CHIPID_C011xx: -+ case STM32_CHIPID_C031xx: -+ return stlink_read_option_bytes_c0(sl, option_byte); - case STM32_CHIPID_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_F4: From 3fd714052485156f7be332d0da1d8bbc30ccbce8 Mon Sep 17 00:00:00 2001 From: rcubee Date: Tue, 14 Nov 2023 17:30:00 +0100 Subject: [PATCH 12/15] forgot to include these --- config/chips/C011xx.chip | 14 ++++++++++++++ config/chips/C031xx.chip | 14 ++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 config/chips/C011xx.chip create mode 100644 config/chips/C031xx.chip diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip new file mode 100644 index 0000000..9124c6a --- /dev/null +++ b/config/chips/C011xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32C011xx device +# +dev_type STM32C011xx +ref_manual_id 0490 +chip_id 0x453 // STM32_CHIPID_C011xx +flash_type C0 +flash_size_reg 0x1fff75a0 +flash_pagesize 0x800 // 2 KB +sram_size 0x1800 // 6 KB +bootrom_base 0x1fff0000 +bootrom_size 0x1800 // 6 KB +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B +flags none diff --git a/config/chips/C031xx.chip b/config/chips/C031xx.chip new file mode 100644 index 0000000..30017ae --- /dev/null +++ b/config/chips/C031xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32C031xx device +# +dev_type STM32C031xx +ref_manual_id 0490 +chip_id 0x453 // STM32_CHIPID_C031xx +flash_type C0 +flash_size_reg 0x1fff75a0 +flash_pagesize 0x800 // 2 KB +sram_size 0x3000 // 12 KB +bootrom_base 0x1fff0000 +bootrom_size 0x1800 // 6 KB +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B +flags none From cf840b5f3d8d4154efb8058adeddb20e14c934cd Mon Sep 17 00:00:00 2001 From: rcubee Date: Tue, 14 Nov 2023 17:38:12 +0100 Subject: [PATCH 13/15] fixed formatting --- config/chips/C011xx.chip | 4 ++-- config/chips/C031xx.chip | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip index 9124c6a..b961a18 100644 --- a/config/chips/C011xx.chip +++ b/config/chips/C011xx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x1800 // 6 KB bootrom_base 0x1fff0000 bootrom_size 0x1800 // 6 KB -option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE -option_size 0x80 // 128 B +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B flags none diff --git a/config/chips/C031xx.chip b/config/chips/C031xx.chip index 30017ae..921c1f1 100644 --- a/config/chips/C031xx.chip +++ b/config/chips/C031xx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x3000 // 12 KB bootrom_base 0x1fff0000 bootrom_size 0x1800 // 6 KB -option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE -option_size 0x80 // 128 B +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B flags none From 0d16dbac9a7cb89dddc92f1c5b1a1274362d6906 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 22 Nov 2023 01:13:44 +0100 Subject: [PATCH 14/15] CodeQL Workflow Maintenance - Removed incompatible workflow - Updated existing workflow --- .github/workflows/codeql-analysis.yml | 14 +-- .github/workflows/codeql-buildscript.sh | 6 -- .github/workflows/codeql.yml | 126 ------------------------ .github/workflows/fail_on_error.py | 34 ------- 4 files changed, 7 insertions(+), 173 deletions(-) delete mode 100644 .github/workflows/codeql-buildscript.sh delete mode 100644 .github/workflows/codeql.yml delete mode 100755 .github/workflows/fail_on_error.py diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index 55a2129..94f2562 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -13,12 +13,12 @@ name: "CodeQL" on: push: - branches: [ testing, develop, master ] + branches: [testing, develop, master] pull_request: # The branches below must be a subset of the branches above - branches: [ testing, develop ] + branches: [testing, develop] schedule: - - cron: '00 20 * * 1' + - cron: "00 20 * * 1" jobs: analyze: @@ -28,7 +28,7 @@ jobs: strategy: fail-fast: false matrix: - language: [ 'cpp' ] + language: ["cpp"] # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] # Learn more: # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed @@ -41,7 +41,7 @@ jobs: # Initializes the CodeQL tools for scanning. - name: Initialize CodeQL - uses: github/codeql-action/init@v1 + uses: github/codeql-action/init@v2 with: languages: ${{ matrix.language }} # If you wish to specify custom queries, you can do so here or in a config file. @@ -52,7 +52,7 @@ jobs: # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). # If this step fails, then you should remove it and run the build manually (see below) - name: Autobuild - uses: github/codeql-action/autobuild@v1 + uses: github/codeql-action/autobuild@v2 # ℹī¸ Command-line programs to run using the OS shell. # 📚 https://git.io/JvXDl @@ -66,4 +66,4 @@ jobs: # make release - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v1 + uses: github/codeql-action/analyze@v2 diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh deleted file mode 100644 index d626d42..0000000 --- a/.github/workflows/codeql-buildscript.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash - -sudo apt-get -y update -sudo apt-get -y install libusb-1.0 libusb-1.0-0-dev libgtk-3-dev -make clean -make release -j$(nproc) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml deleted file mode 100644 index 8164922..0000000 --- a/.github/workflows/codeql.yml +++ /dev/null @@ -1,126 +0,0 @@ -# For most projects, this workflow file will not need changing; you simply need -# to commit it to your repository. -# -# You may wish to alter this file to override the set of languages analyzed, -# or to provide custom queries or build logic. -# -# ******** NOTE ******** -# We have attempted to detect the languages in your repository. Please check -# the `language` matrix defined below to confirm you have the correct set of -# supported CodeQL languages. -# -name: "CodeQL" - -on: - # push: - # branches: [ "main", "master" ] - schedule: - - cron: '0 0 * * *' - pull_request: - branches: '*' - -jobs: - analyze: - name: Analyze - # Runner size impacts CodeQL analysis time. To learn more, please see: - # - https://gh.io/recommended-hardware-resources-for-running-codeql - # - https://gh.io/supported-runners-and-hardware-resources - # - https://gh.io/using-larger-runners - # Consider using larger runners for possible analysis time improvements. - runs-on: ${{ (matrix.language == 'swift' && 'macos-latest') || 'ubuntu-20.04' }} - timeout-minutes: ${{ (matrix.language == 'swift' && 120) || 360 }} - permissions: - actions: read - contents: read - security-events: write - - strategy: - fail-fast: false - matrix: - language: [ 'cpp' ] - # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python', 'ruby', 'swift' ] - # Use only 'java' to analyze code written in Java, Kotlin or both - # Use only 'javascript' to analyze code written in JavaScript, TypeScript or both - # Learn more about CodeQL language support at https://aka.ms/codeql-docs/language-support - - steps: - - name: Checkout repository - uses: actions/checkout@v3 - with: - submodules: recursive - - # Initializes the CodeQL tools for scanning. - - name: Initialize CodeQL - uses: github/codeql-action/init@v2 - with: - languages: ${{ matrix.language }} - # If you wish to specify custom queries, you can do so here or in a config file. - # By default, queries listed here will override any specified in a config file. - # Prefix the list here with "+" to use these queries and those in the config file. - - # For more details on CodeQL's query packs, refer to: https://docs.github.com/en/code-security/code-scanning/automatically-scanning-your-code-for-vulnerabilities-and-errors/configuring-code-scanning#using-queries-in-ql-packs - # queries: security-extended,security-and-quality - queries: security-and-quality - - - # Autobuild attempts to build any compiled languages (C/C++, C#, Go, Java, or Swift). - # If this step fails, then you should remove it and run the build manually (see below) - #- name: Autobuild - # uses: github/codeql-action/autobuild@v2 - - # ℹī¸ Command-line programs to run using the OS shell. - # 📚 See https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions#jobsjob_idstepsrun - - # If the Autobuild fails above, remove it and uncomment the following three lines. - # modify them (or add more) to build your code if your project, please refer to the EXAMPLE below for guidance. - - - run: | - ./.github/workflows/codeql-buildscript.sh - - - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v2 - with: - category: "/language:${{matrix.language}}" - upload: false - id: step1 - - # Filter out rules with low severity or high false positve rate - # Also filter out warnings in third-party code - - name: Filter out unwanted errors and warnings - uses: advanced-security/filter-sarif@v1 - with: - patterns: | - -**:cpp/path-injection - -**:cpp/world-writable-file-creation - -**:cpp/poorly-documented-function - -**:cpp/potentially-dangerous-function - -**:cpp/use-of-goto - -**:cpp/integer-multiplication-cast-to-long - -**:cpp/comparison-with-wider-type - -**:cpp/leap-year/* - -**:cpp/ambiguously-signed-bit-field - -**:cpp/suspicious-pointer-scaling - -**:cpp/suspicious-pointer-scaling-void - -**:cpp/unsigned-comparison-zero - -**/cmake*/Modules/** - input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - - - name: Upload CodeQL results to code scanning - uses: github/codeql-action/upload-sarif@v2 - with: - sarif_file: ${{ steps.step1.outputs.sarif-output }} - category: "/language:${{matrix.language}}" - - - name: Upload CodeQL results as an artifact - if: success() || failure() - uses: actions/upload-artifact@v3 - with: - name: codeql-results - path: ${{ steps.step1.outputs.sarif-output }} - retention-days: 5 - - - name: Fail if an error is found - run: | - ./.github/workflows/fail_on_error.py \ - ${{ steps.step1.outputs.sarif-output }}/cpp.sarif diff --git a/.github/workflows/fail_on_error.py b/.github/workflows/fail_on_error.py deleted file mode 100755 index 2979174..0000000 --- a/.github/workflows/fail_on_error.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 - -import json -import sys - -# Return whether SARIF file contains error-level results -def codeql_sarif_contain_error(filename): - with open(filename, 'r') as f: - s = json.load(f) - - for run in s.get('runs', []): - rules_metadata = run['tool']['driver']['rules'] - if not rules_metadata: - rules_metadata = run['tool']['extensions'][0]['rules'] - - for res in run.get('results', []): - if 'ruleIndex' in res: - rule_index = res['ruleIndex'] - elif 'rule' in res and 'index' in res['rule']: - rule_index = res['rule']['index'] - else: - continue - try: - rule_level = rules_metadata[rule_index]['defaultConfiguration']['level'] - except IndexError as e: - print(e, rule_index, len(rules_metadata)) - else: - if rule_level == 'error': - return True - return False - -if __name__ == "__main__": - if codeql_sarif_contain_error(sys.argv[1]): - sys.exit(1) From 033007fd2713aba630d28c706499959dc8792277 Mon Sep 17 00:00:00 2001 From: Mirko Matonti Date: Thu, 23 Nov 2023 17:46:09 +0000 Subject: [PATCH 15/15] pr adjustment --- src/stlink-lib/common_flash.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 5005a63..7172352 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1312,7 +1312,7 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { */ /* In case the address is within the OTP area we use a different flash method */ - if(addr >= sl->otp_base && addr <= sl->otp_base + sl->otp_size) { + if(addr >= sl->otp_base && addr < sl->otp_base + sl->otp_size) { err = stlink_write_otp(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty); } else { @@ -1404,7 +1404,7 @@ int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->otp_base, logvar); return (-1); } - if ((addr + size) > (sl->otp_base + sl->otp_size)) { + if ((addr + size) >= (sl->otp_base + sl->otp_size)) { logvar = sl->otp_base + sl->otp_size - addr; ELOG("The size exceeds the size of the OTP Area (0x%08x bytes available)\n", logvar); return (-1); @@ -1431,7 +1431,7 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr);