kopia lustrzana https://github.com/stlink-org/stlink
Merge branch 'develop' into common-c-refactor
nightwalker-87
GitHub
commit
d9e79fe295
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@ -1,13 +1,14 @@
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|||
# Chip-ID file for F03x
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||||
# Chip-ID file for STM32F03x device
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||||
#
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chip_id 0x444
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description F03x
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||||
flash_type 1
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||||
flash_pagesize 0x400
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||||
sram_size 0x1000
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||||
dev_type STM32F03x
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||||
ref_manual_id 0091
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||||
chip_id 0x444 // STM32_CHIPID_F0xx_SMALL
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||||
flash_type F0_F1_F3
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||||
flash_size_reg 0x1ffff7cc
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||||
flash_pagesize 0x400 // 1 KB
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||||
sram_size 0x1000 // 4 KB
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||||
bootrom_base 0x1fffec00
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||||
bootrom_size 0xc00
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||||
option_base 0x1ffff800
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||||
option_size 0x10
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||||
bootrom_size 0xc00 // 3 KB
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||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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||||
option_size 0x10 // 16 B
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||||
flags none
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||||
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@ -1,13 +1,14 @@
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# Chip-ID file for F04x
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# Chip-ID file for STM32F04x device
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#
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chip_id 0x445
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description F04x
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flash_type 1
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flash_pagesize 0x400
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sram_size 0x1800
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dev_type STM32F04x
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ref_manual_id 0091
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chip_id 0x445 // STM32_CHIPID_F04
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7cc
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flash_pagesize 0x400 // 1 KB
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||||
sram_size 0x1800 // 6 KB
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||||
bootrom_base 0x1fffec00
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bootrom_size 0xc00
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||||
option_base 0x1ffff800
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||||
option_size 0x10
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bootrom_size 0xc00 // 3 KB
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||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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||||
flags none
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||||
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||||
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@ -1,13 +1,14 @@
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# Chip-ID file for F05x
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# Chip-ID file for STM32F05x device
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#
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chip_id 0x440
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description F05x
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flash_type 1
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flash_pagesize 0x400
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sram_size 0x2000
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dev_type STM32F05x
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ref_manual_id 0091
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chip_id 0x440 // STM32_CHIPID_F0
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7cc
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flash_pagesize 0x400 // 1 KB
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sram_size 0x2000 // 8 KB
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||||
bootrom_base 0x1fffec00
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bootrom_size 0xc00
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option_base 0x1ffff800
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option_size 0x10
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bootrom_size 0xc00 // 3 KB
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option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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flags none
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@ -1,13 +1,14 @@
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# Chip-ID file for F07x
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# Chip-ID file for STM32F07x device
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#
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chip_id 0x448
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description F07x
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flash_type 1
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flash_pagesize 0x800
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sram_size 0x4000
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dev_type STM32F07x
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ref_manual_id 0091
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chip_id 0x448 // STM32_CHIPID_F0_CAN
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7cc
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flash_pagesize 0x800 // 2 KB
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sram_size 0x4000 // 16 KB
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bootrom_base 0x1fffc800
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bootrom_size 0x3000
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option_base 0x1ffff800
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option_size 0x10
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bootrom_size 0x3000 // 12 KB
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option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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flags none
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@ -1,13 +1,15 @@
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# Chip-ID file for F09x
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# Chip-ID file for STM32F09x device
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#
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chip_id 0x442
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description F09x
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flash_type 1
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flash_pagesize 0x800
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sram_size 0x8000
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dev_type STM32F09x
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ref_manual_id 0091
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chip_id 0x442 // STM32_CHIPID_F09x
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7cc
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flash_pagesize 0x800 // 2 KB
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sram_size 0x8000 // 32 KB
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bootrom_base 0x1fffd800
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bootrom_size 0x2000
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option_base 0x1ffff800
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option_size 0x10
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bootrom_size 0x2000 // 8 KB
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option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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flags none
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@ -1,13 +0,0 @@
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# Chip-ID file for F1 Low-density device
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#
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chip_id 0x412
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description F1 Low-density device
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flash_type 1
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flash_pagesize 0x400
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sram_size 0x2800
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bootrom_base 0x1ffff000
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bootrom_size 0x800
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option_base 0x1ffff800
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option_size 0x10
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flags swo
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@ -1,13 +1,15 @@
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# Chip-ID file for F1xx CL
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# Chip-ID file for STM32F1xx Connectivity Line device
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#
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chip_id 0x418
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description F1xx CL
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flash_type 1
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flash_pagesize 0x800
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sram_size 0x10000
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dev_type STM32F1xx_CL
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ref_manual_id 0008
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chip_id 0x418 // STM32_CHIPID_F1_CONN
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7e0
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flash_pagesize 0x800 // 2 KB
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sram_size 0x10000 // 64 KB
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bootrom_base 0x1fffb000
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bootrom_size 0x4800
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option_base 0x1ffff800
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option_size 0x10
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bootrom_size 0x4800 // 18 KB
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option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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flags swo
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@ -0,0 +1,14 @@
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# Chip-ID file for STM32F1xx high density device
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#
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dev_type F1xx_HD
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ref_manual_id 0008
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chip_id 0x414 // STM32_CHIPID_F1_HD
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7e0
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flash_pagesize 0x800 // 2 KB
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sram_size 0x10000 // 64 KB
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bootrom_base 0x1ffff000
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bootrom_size 0x800 // 2 KB
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option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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flags swo
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@ -1,13 +0,0 @@
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# Chip-ID file for F1xx High-density
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#
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chip_id 0x414
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description F1xx High-density
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flash_type 1
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flash_pagesize 0x800
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sram_size 0x10000
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bootrom_base 0x1ffff000
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bootrom_size 0x800
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option_base 0x1ffff800
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option_size 0x10
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flags swo
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@ -1,13 +0,0 @@
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# Chip-ID file for F1xx High-density value line
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#
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chip_id 0x428
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description F1xx High-density value line
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flash_type 1
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flash_pagesize 0x800
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sram_size 0x8000
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bootrom_base 0x1ffff000
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bootrom_size 0x800
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||||
option_base 0x1ffff800
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option_size 0x10
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flags swo
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@ -0,0 +1,14 @@
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# Chip-ID file for STM32F1 low density device
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#
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dev_type STM32F1xx_LD
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ref_manual_id 0008
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chip_id 0x412 // STM32_CHIPID_F1_LD
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7e0
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flash_pagesize 0x400 // 1 KB
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sram_size 0x2800 // 10 KB
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bootrom_base 0x1ffff000
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bootrom_size 0x800 // 2 KB
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option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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flags swo
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@ -0,0 +1,14 @@
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# Chip-ID file for STM32F1xx medium density device
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#
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dev_type STM32F1xx_MD
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ref_manual_id 0008
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chip_id 0x410 // STM32_CHIPID_F1_MD
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7e0
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flash_pagesize 0x400 // 1 KB
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sram_size 0x5000 // 20 KB
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||||
bootrom_base 0x1ffff000
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bootrom_size 0x800 // 2 KB
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option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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option_size 0x10 // 16 B
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flags swo
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@ -1,13 +0,0 @@
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# Chip-ID file for F1xx Medium-density
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#
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chip_id 0x410
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description F1xx Medium-density
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flash_type 1
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flash_pagesize 0x400
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sram_size 0x5000
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bootrom_base 0x1ffff000
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bootrom_size 0x800
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option_base 0x1ffff800
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option_size 0x10
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flags swo
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@ -0,0 +1,14 @@
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# Chip-ID file for STM32F1xx high density Value Line device
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#
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dev_type STM32F1xx_VL_HD
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ref_manual_id 0041
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||||
chip_id 0x428 // STM32_CHIPID_F1_VL_HD
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7e0
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flash_pagesize 0x800 // 2 KB
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sram_size 0x8000 // 32 KB
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||||
bootrom_base 0x1ffff000
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||||
bootrom_size 0x800 // 2 KB
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||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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||||
option_size 0x10 // 16 B
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||||
flags swo
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@ -0,0 +1,14 @@
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# Chip-ID file for STMF1xx Value Line medium & low density device
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#
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dev_type STM32F1xx_VL_MD_LD
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ref_manual_id 0041
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chip_id 0x420 // STM32_CHIPID_F1_VL_MD_LD
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flash_type F0_F1_F3
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flash_size_reg 0x1ffff7e0
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flash_pagesize 0x400 // 1 KB
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sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */
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bootrom_base 0x1ffff000
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||||
bootrom_size 0x800 // 2 KB
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||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
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||||
option_size 0x10 // 16 B
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||||
flags swo
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||||
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@ -1,13 +0,0 @@
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# Chip-ID file for F1xx Value Line
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#
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chip_id 0x420
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description F1xx Value Line
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||||
flash_type 1
|
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flash_pagesize 0x400
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||||
sram_size 0x2000
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bootrom_base 0x1ffff000
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||||
bootrom_size 0x800
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||||
option_base 0x1ffff800
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||||
option_size 0x10
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||||
flags swo
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@ -0,0 +1,14 @@
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# Chip-ID file for STM32F1xx XL density device
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#
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dev_type STM32F1xx_XLD
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ref_manual_id 0008
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chip_id 0x430 // STM32_CHIPID_F1_XLD
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||||
flash_type F1_XL
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flash_size_reg 0x1ffff7e0
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||||
flash_pagesize 0x800 // 2 KB
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sram_size 0x18000 // 96 KB
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||||
bootrom_base 0x1fffe000
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||||
bootrom_size 0x1800 // 6 KB
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||||
option_base 0x0
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||||
option_size 0x0
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||||
flags swo
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@ -1,13 +0,0 @@
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# Chip-ID file for F1xx XL-density
|
||||
#
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chip_id 0x430
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description F1xx XL-density
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flash_type 2
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||||
flash_pagesize 0x800
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||||
sram_size 0x18000
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||||
bootrom_base 0x1fffe000
|
||||
bootrom_size 0x1800
|
||||
option_base 0x0
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||||
option_size 0x0
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||||
flags swo
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||||
|
||||
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@ -1,13 +1,14 @@
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# Chip-ID file for F2xx
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||||
# Chip-ID file for STM32F2xx device
|
||||
#
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||||
chip_id 0x411
|
||||
description F2xx
|
||||
flash_type 3
|
||||
flash_pagesize 0x20000
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||||
sram_size 0x20000
|
||||
dev_type STM32F2xx
|
||||
ref_manual_id 0033
|
||||
chip_id 0x411 // STM32_CHIPID_F2
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
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||||
flash_pagesize 0x20000 // 128 KB
|
||||
sram_size 0x20000 // 128 KB
|
||||
bootrom_base 0x1fff0000
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||||
bootrom_size 0x7800
|
||||
option_base 0x1fffc000
|
||||
option_size 0x4
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
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|
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@ -1,13 +1,14 @@
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# Chip-ID file for F301/F302/F318
|
||||
# Chip-ID file for STM32F3xx device (F301x6/8, F302x6x8, F318x8)
|
||||
#
|
||||
chip_id 0x439
|
||||
description F301/F302/F318
|
||||
flash_type 1
|
||||
flash_pagesize 0x800
|
||||
sram_size 0xa000
|
||||
dev_type STM32F301_F302_F318
|
||||
ref_manual_id 0365 // also RM0366
|
||||
chip_id 0x439 // STM32_CHIPID_F3xx_SMALL
|
||||
flash_type F0_F1_F3
|
||||
flash_size_reg 0x1ffff7cc
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0xa000 // 40 KB
|
||||
bootrom_base 0x1fffd800
|
||||
bootrom_size 0x2000
|
||||
option_base 0x1ffff800
|
||||
option_size 0x10
|
||||
bootrom_size 0x2000 // 8 KB
|
||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
|
||||
option_size 0x10 // 16 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
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@ -1,13 +1,14 @@
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|||
# Chip-ID file for F302/F303/F358
|
||||
# Chip-ID file for STM32F3xx device (F302xBxC, F303xB/C, F358)
|
||||
#
|
||||
chip_id 0x422
|
||||
description F302/F303/F358
|
||||
flash_type 1
|
||||
flash_pagesize 0x800
|
||||
sram_size 0xa000
|
||||
dev_type STM32F302_F303_358
|
||||
ref_manual_id 0365 // also RM0316
|
||||
chip_id 0x422 // STM32_CHIPID_F3
|
||||
flash_type F0_F1_F3
|
||||
flash_size_reg 0x1ffff7cc
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0xa000 // 40 KB
|
||||
bootrom_base 0x1ffff000
|
||||
bootrom_size 0x800
|
||||
option_base 0x1ffff800
|
||||
option_size 0x10
|
||||
bootrom_size 0x800 // 2 KB
|
||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
|
||||
option_size 0x10 // 16 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32F3xx high density device (F302xD/E, F303xD/E, F398xE)
|
||||
#
|
||||
dev_type STM32F302_F303_F398_HD
|
||||
ref_manual_id 0365 // also RM0316 (Rev 5)
|
||||
chip_id 0x446 // STM32_CHIPID_F303_HD
|
||||
flash_type F0_F1_F3
|
||||
flash_size_reg 0x1ffff7cc
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x10000 // 64 KB
|
||||
bootrom_base 0x1fffd800
|
||||
bootrom_size 0x2000 // 8 KB
|
||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
|
||||
option_size 0x10 // 16 B
|
||||
flags swo
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F303/F328/F334
|
||||
# Chip-ID file for STM32F3xx device (F303x6/8, F328, F334)
|
||||
#
|
||||
chip_id 0x438
|
||||
description F303/F328/F334
|
||||
flash_type 1
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x3000
|
||||
dev_type STM32F303_F328_F334
|
||||
ref_manual_id 0364 // also RM0316
|
||||
chip_id 0x438 // STM32_CHIPID_F334
|
||||
flash_type F0_F1_F3
|
||||
flash_size_reg 0x1ffff7cc
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x3000 // 12 KB
|
||||
bootrom_base 0x1fffd800
|
||||
bootrom_size 0x2000
|
||||
option_base 0x1ffff800
|
||||
option_size 0x10
|
||||
bootrom_size 0x2000 // 8 KB
|
||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
|
||||
option_size 0x10 // 16 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for F303 high density
|
||||
#
|
||||
chip_id 0x446
|
||||
description F303 high density
|
||||
flash_type 1
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x10000
|
||||
bootrom_base 0x1fffd800
|
||||
bootrom_size 0x2000
|
||||
option_base 0x1ffff800
|
||||
option_size 0x10
|
||||
flags swo
|
||||
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F37x
|
||||
# Chip-ID file for STM32F37x device
|
||||
#
|
||||
chip_id 0x432
|
||||
description F37x
|
||||
flash_type 1
|
||||
flash_pagesize 0x800
|
||||
sram_size 0xa000
|
||||
dev_type STM32F37x
|
||||
ref_manual_id 0313
|
||||
chip_id 0x432 // STM32_CHIPID_F37x
|
||||
flash_type F0_F1_F3
|
||||
flash_size_reg 0x1ffff7cc
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0xa000 // 40 KB
|
||||
bootrom_base 0x1ffff000
|
||||
bootrom_size 0x800
|
||||
option_base 0x1ffff800
|
||||
option_size 0x10
|
||||
bootrom_size 0x800 // 2 KB
|
||||
option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE
|
||||
option_size 0x10 // 16 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for F401xB/C
|
||||
#
|
||||
chip_id 0x423
|
||||
description F401xB/C
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x10000
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32F401xB/xC device
|
||||
#
|
||||
dev_type STM32F401xB_xC
|
||||
ref_manual_id 0368
|
||||
chip_id 0x423 // STM32_CHIPID_F4_LP
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x10000 // 64 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for F401xD/E
|
||||
#
|
||||
chip_id 0x433
|
||||
description F401xD/E
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x18000
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32F401xD/xE device
|
||||
#
|
||||
dev_type STM32F401xD_xE
|
||||
ref_manual_id 0368
|
||||
chip_id 0x433 // STM32_CHIPID_F4_DE
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x18000 // 96 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F410
|
||||
# Chip-ID file for STM32F410 device
|
||||
#
|
||||
chip_id 0x458
|
||||
description F410
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x8000
|
||||
dev_type STM32F410
|
||||
ref_manual_id 0401
|
||||
chip_id 0x458 // STM32_CHIPID_F410
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x8000 // 32 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for F411xC/E
|
||||
#
|
||||
chip_id 0x431
|
||||
description F411xC/E
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x20000
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32F411xC/xE device
|
||||
#
|
||||
dev_type STM32F411xC_xE
|
||||
ref_manual_id 0383
|
||||
chip_id 0x431 // STM32_CHIPID_F411xx
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x20000 // 128 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F412
|
||||
# Chip-ID file for STM32F412 device
|
||||
#
|
||||
chip_id 0x441
|
||||
description F412
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x40000
|
||||
dev_type STM32F412
|
||||
ref_manual_id 0402
|
||||
chip_id 0x441 // STM32_CHIPID_F412
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x40000 // 256 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F413/F423
|
||||
# Chip-ID file for STM32F413 / STM32F423 device
|
||||
#
|
||||
chip_id 0x463
|
||||
description F413/F423
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x50000
|
||||
dev_type STM32F413_F423
|
||||
ref_manual_id 0430 // RM0430 (Rev 2)
|
||||
chip_id 0x463 // STM32_CHIPID_F413
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x50000 // 320 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F42x/F43x
|
||||
# Chip-ID file for STM32F42x / STM32F43x device
|
||||
#
|
||||
chip_id 0x419
|
||||
description F42x/F43x
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x40000
|
||||
dev_type STM32F42x_F43x
|
||||
ref_manual_id 0090 // RM0090 (Rev. 2)
|
||||
chip_id 0x419 // STM32_CHIPID_F4_HD
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x40000 // 256 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F446
|
||||
# Chip-ID file for STM32F446 device
|
||||
#
|
||||
chip_id 0x421
|
||||
description F446
|
||||
flash_type 3
|
||||
flash_pagesize 0x20000
|
||||
sram_size 0x20000
|
||||
dev_type STM32F446
|
||||
ref_manual_id 0390
|
||||
chip_id 0x421 // STM32_CHIPID_F446
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x20000 // 128 KB
|
||||
sram_size 0x20000 // 128 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
option_base 0x1fffc000
|
||||
option_size 0x4
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F46x/F47x
|
||||
# Chip-ID file for STM32F46x / STM32F47x device
|
||||
#
|
||||
chip_id 0x434
|
||||
description F46x/F47x
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x40000
|
||||
dev_type STM32F46x_F47x
|
||||
ref_manual_id 0090 // RM0090 (Rev. 2)
|
||||
chip_id 0x434 // STM32_CHIPID_F4_DSI
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x40000 // 256 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F4x5/F4x7
|
||||
# Chip-ID file for STM32F4x5 / STM32F4x7 device
|
||||
#
|
||||
chip_id 0x413
|
||||
description F4x5/F4x7
|
||||
flash_type 3
|
||||
flash_pagesize 0x4000
|
||||
sram_size 0x30000
|
||||
dev_type STM32F4x5_F4x7
|
||||
ref_manual_id 0090 // RM0090 (Rev. 2)
|
||||
chip_id 0x413 // STM32_CHIPID_F4
|
||||
flash_type F2_F4
|
||||
flash_size_reg 0x1fff7a22
|
||||
flash_pagesize 0x4000 // 16 KB
|
||||
sram_size 0x30000 // 192 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7800
|
||||
option_base 0x40023c14
|
||||
option_size 0x4
|
||||
bootrom_size 0x7800 // 30 KB
|
||||
option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F72x/F73x
|
||||
# Chip-ID file for STM32F72x / STM32F73x device
|
||||
#
|
||||
chip_id 0x452
|
||||
description F72x/F73x
|
||||
flash_type 3
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x40000
|
||||
dev_type STM32F72x_F73x
|
||||
ref_manual_id 0431
|
||||
chip_id 0x452 // STM32_CHIPID_F72xxx
|
||||
flash_type F7
|
||||
flash_size_reg 0x1ff07a22
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x40000 // 256 KB
|
||||
bootrom_base 0x100000
|
||||
bootrom_size 0xedc0
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
bootrom_size 0xedc0 // 59.4375 KB
|
||||
option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE
|
||||
option_size 0x20 // 32 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F74x/F75x
|
||||
# Chip-ID file for STM32F74x / STM32F75x device
|
||||
#
|
||||
chip_id 0x449
|
||||
description F74x/F75x
|
||||
flash_type 3
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x50000
|
||||
dev_type STM32F74x_F75x
|
||||
ref_manual_id 0385
|
||||
chip_id 0x449 // STM32_CHIPID_F7
|
||||
flash_type F7
|
||||
flash_size_reg 0x1ff0f442
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x50000 // 320 KB
|
||||
bootrom_base 0x100000
|
||||
bootrom_size 0xedc0
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
bootrom_size 0xedc0 // 59.4375 KB
|
||||
option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE
|
||||
option_size 0x20 // 32 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for F76x/F77x
|
||||
# Chip-ID file for STM32F76x / STM32F77x device
|
||||
#
|
||||
chip_id 0x451
|
||||
description F76x/F77x
|
||||
flash_type 4
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x80000
|
||||
dev_type STM32F76x_F77x
|
||||
ref_manual_id 0410
|
||||
chip_id 0x451 // STM32_CHIPID_F76xxx
|
||||
flash_type F7
|
||||
flash_size_reg 0x1ff0f442
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x80000 // 512 KB
|
||||
bootrom_base 0x200000
|
||||
bootrom_size 0xedc0
|
||||
option_base 0x1fff0000
|
||||
option_size 0x20
|
||||
flags dualbank swo
|
||||
|
||||
bootrom_size 0xedc0 // 59.4375 KB
|
||||
option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE /* Used for reading back option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 */
|
||||
option_size 0x20 // 32 B
|
||||
flags swo dualbank
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for G03x/G04x
|
||||
# Chip-ID file for STM32G030 / STM32G031 / STM32G041 device
|
||||
#
|
||||
chip_id 0x466
|
||||
description G03x/G04x
|
||||
flash_type 7
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x2000
|
||||
dev_type STM32G03x_G04x
|
||||
ref_manual_id 0444 // also RM454
|
||||
chip_id 0x466 // STM32_CHIPID_G0_CAT1
|
||||
flash_type G0
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x2000 // 8 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x2000
|
||||
option_base 0x1fff7800
|
||||
option_size 0x4
|
||||
bootrom_size 0x2000 // 8 KB
|
||||
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags none
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for G05x/G06x
|
||||
# Chip-ID file for STM32G05x / STM32G06x device
|
||||
#
|
||||
chip_id 0x456
|
||||
description G05x/G06x
|
||||
flash_type 7
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x9000
|
||||
dev_type STM32G05x_G06x
|
||||
ref_manual_id 0444
|
||||
chip_id 0x456 // STM32_CHIPID_G0_CAT4
|
||||
flash_type G0
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x9000 // 36 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1fff7800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags none
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for G07x/G08x
|
||||
# Chip-ID file for STM32G07x / STM32G08x device
|
||||
#
|
||||
chip_id 0x460
|
||||
description G07x/G08x
|
||||
flash_type 7
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x9000
|
||||
dev_type STM32G07x_G08x
|
||||
ref_manual_id 0444
|
||||
chip_id 0x460 // STM32_CHIPID_G0_CAT2
|
||||
flash_type G0
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x9000 // 36 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1fff7800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags none
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for G0Bx/G0Cx
|
||||
# Chip-ID file for STM32G0Bx / STM32G0Cx device
|
||||
#
|
||||
chip_id 0x467
|
||||
description G0Bx/G0Cx
|
||||
flash_type 7
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x9000
|
||||
dev_type STM32G0Bx_G0Cx
|
||||
ref_manual_id 0444
|
||||
chip_id 0x467 // STM32_CHIPID_G0_CAT3
|
||||
flash_type G0
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x9000 // 36 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1fff7800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags dualbank
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for G43x/G44x
|
||||
# Chip-ID file for STM32G43x / STM32G44x device
|
||||
#
|
||||
chip_id 0x468
|
||||
description G43x/G44x
|
||||
flash_type 8
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x8000
|
||||
dev_type STM32G43x_G44x
|
||||
ref_manual_id 0440
|
||||
chip_id 0x468 // STM32_CHIPID_G4_CAT2
|
||||
flash_type G4
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x8000 // 32 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1ffff800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for G47x/G48x
|
||||
# Chip-ID file for STM32G47x / STM32G48x device
|
||||
#
|
||||
chip_id 0x469
|
||||
description G47x/G48x
|
||||
flash_type 8
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x20000
|
||||
dev_type STM32G47x_G48x
|
||||
ref_manual_id 0440
|
||||
chip_id 0x469 // STM32_CHIPID_G4_CAT3
|
||||
flash_type G4
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x20000 // 128 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1ffff800
|
||||
option_size 0x4
|
||||
flags dualbank swo
|
||||
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo dualbank
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for G49x/G4Ax
|
||||
# Chip-ID file for STM32G49x / STM32G4Ax device
|
||||
#
|
||||
chip_id 0x479
|
||||
description G49x/G4Ax
|
||||
flash_type 8
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x1c000
|
||||
dev_type STM32G49x_G4Ax
|
||||
ref_manual_id 0440
|
||||
chip_id 0x479 // STM32_CHIPID_G4_CAT4
|
||||
flash_type G4
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x1c000 // 112 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1ffff800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for H72x/H73x
|
||||
# Chip-ID file for STM32H72x / STM32H73x device
|
||||
#
|
||||
chip_id 0x483
|
||||
description H72x/H73x
|
||||
flash_type 10
|
||||
flash_pagesize 0x20000
|
||||
sram_size 0x20000
|
||||
dev_type STM32H72x_H73x
|
||||
ref_manual_id 0468
|
||||
chip_id 0x483 // STM32_CHIPID_H72x
|
||||
flash_type H7
|
||||
flash_size_reg 0x1ff1e880
|
||||
flash_pagesize 0x20000 // 128 KB
|
||||
sram_size 0x20000 // 128 KB "DTCM"
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x20000
|
||||
option_base 0x5200201c
|
||||
option_size 0x2c
|
||||
bootrom_size 0x20000 // 128 KB
|
||||
option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE
|
||||
option_size 0x2c // 44 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for H74x/H75x
|
||||
# Chip-ID file for STM32H74x / STM32H75x device
|
||||
#
|
||||
chip_id 0x450
|
||||
description H74x/H75x
|
||||
flash_type 10
|
||||
flash_pagesize 0x20000
|
||||
sram_size 0x20000
|
||||
dev_type STM32H74x_H75x
|
||||
ref_manual_id 0433
|
||||
chip_id 0x450 // STM32_CHIPID_H74xxx
|
||||
flash_type H7
|
||||
flash_size_reg 0x1ff1e880
|
||||
flash_pagesize 0x20000 // 128 KB
|
||||
sram_size 0x20000 // 128 KB "DTCM"
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x20000
|
||||
option_base 0x5200201c
|
||||
option_size 0x2c
|
||||
flags dualbank swo
|
||||
|
||||
bootrom_size 0x20000 // 128 KB
|
||||
option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE
|
||||
option_size 0x2c // 44 B /* FLASH_OPTSR_CUR to FLASH_BOOT_PRGR */
|
||||
flags swo dualbank
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for H7Ax/H7Bx
|
||||
# Chip-ID file for STM32H7Ax / STM32H7Bx device
|
||||
#
|
||||
chip_id 0x480
|
||||
description H7Ax/H7Bx
|
||||
flash_type 10
|
||||
flash_pagesize 0x2000
|
||||
sram_size 0x20000
|
||||
dev_type STM32H7Ax_H7Bx
|
||||
ref_manual_id 0455
|
||||
chip_id 0x480 // STM32_CHIPID_H7Ax
|
||||
flash_type H7
|
||||
flash_size_reg 0x08fff80c
|
||||
flash_pagesize 0x2000 // 8 KB
|
||||
sram_size 0x20000 // 128 KB "DTCM"
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x20000
|
||||
option_base 0x5200201c
|
||||
option_size 0x2c
|
||||
flags dualbank swo
|
||||
|
||||
bootrom_size 0x20000 // 128 KB
|
||||
option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE
|
||||
option_size 0x2c // 44 B
|
||||
flags swo dualbank
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for L01x/L02x
|
||||
#
|
||||
chip_id 0x457
|
||||
description L01x/L02x
|
||||
flash_type 5
|
||||
flash_pagesize 0x80
|
||||
sram_size 0x2000
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x2000
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags none
|
||||
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for L0xx Cat.2
|
||||
#
|
||||
chip_id 0x425
|
||||
description L0xx Cat.2
|
||||
flash_type 5
|
||||
flash_pagesize 0x80
|
||||
sram_size 0x2000
|
||||
bootrom_base 0x1ff0000
|
||||
bootrom_size 0x1000
|
||||
option_base 0x1ff80000
|
||||
option_size 0x14
|
||||
flags none
|
||||
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for L0xx Cat.3
|
||||
#
|
||||
chip_id 0x417
|
||||
description L0xx Cat.3
|
||||
flash_type 5
|
||||
flash_pagesize 0x80
|
||||
sram_size 0x2000
|
||||
bootrom_base 0x1ff0000
|
||||
bootrom_size 0x1000
|
||||
option_base 0x1ff80000
|
||||
option_size 0x14
|
||||
flags none
|
||||
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for L0xx Cat.5
|
||||
#
|
||||
chip_id 0x447
|
||||
description L0xx Cat.5
|
||||
flash_type 5
|
||||
flash_pagesize 0x80
|
||||
sram_size 0x5000
|
||||
bootrom_base 0x1ff0000
|
||||
bootrom_size 0x2000
|
||||
option_base 0x1ff80000
|
||||
option_size 0x14
|
||||
flags dualbank
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32L0xxx (Cat.1) device (L010x3 / L010x4 / L011x / L021x)
|
||||
#
|
||||
dev_type STM32L0xxx_Cat_1
|
||||
ref_manual_id 0451 // also RM0377
|
||||
chip_id 0x457 // STM32_CHIPID_L011
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff8007c
|
||||
flash_pagesize 0x80 // 128 B
|
||||
sram_size 0x2000 // 8 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x2000 // 8 KB
|
||||
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
|
||||
option_size 0x20 // 32 B
|
||||
flags none
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32L0xxx (Cat.2) device (L010x6 / L031x / L041x)
|
||||
#
|
||||
dev_type STM32L0xxx_Cat_2
|
||||
ref_manual_id 0451 // also RM0377
|
||||
chip_id 0x425 // STM32_CHIPID_L0_CAT2
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff8007c
|
||||
flash_pagesize 0x80 // 128 B
|
||||
sram_size 0x2000 // 8 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x1000 // 4 KB
|
||||
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
|
||||
option_size 0x20 // 32 B
|
||||
flags none
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32L0xxx (Cat.3) device (L010x8 / L051x / L053x / L063x)
|
||||
#
|
||||
dev_type STM32L0xxx_Cat_3
|
||||
ref_manual_id 0451 // also RM0367 & RM0377
|
||||
chip_id 0x417 // STM32_CHIPID_L0
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff8007c
|
||||
flash_pagesize 0x80 // 128 B
|
||||
sram_size 0x2000 // 8 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x1000 // 4 KB
|
||||
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
|
||||
option_size 0x20 // 32 B
|
||||
flags none
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32L0xxx (Cat.5) device (L010xB / L071x / L081x / L073x / L083x)
|
||||
#
|
||||
dev_type STM32L0xxx_Cat_5
|
||||
ref_manual_id 0451 // also RM0367 & RM0377
|
||||
chip_id 0x447 // STM32_CHIPID_L0_CAT5
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff8007c
|
||||
flash_pagesize 0x80 // 128 B
|
||||
sram_size 0x5000 // 20 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x2000 // 8 KB
|
||||
option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE
|
||||
option_size 0x20 // 32 B
|
||||
flags dualbank
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L1xx Cat.1
|
||||
# Chip-ID file for STM32L1xx (Cat.1) device (L100C6 / L100R8 / L100RB)
|
||||
#
|
||||
chip_id 0x416
|
||||
description L1xx Cat.1
|
||||
flash_type 5
|
||||
flash_pagesize 0x100
|
||||
sram_size 0x4000
|
||||
dev_type STM32L1xx_Cat_1
|
||||
ref_manual_id 0038
|
||||
chip_id 0x416 // STM32_CHIPID_L1_MD
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff8004c
|
||||
flash_pagesize 0x100 // 128 B
|
||||
sram_size 0x4000 // 16 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x1000
|
||||
bootrom_size 0x1000 // 4 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L1xx Cat.2
|
||||
# Chip-ID file for STM32L1xx (Cat.2) device (L100C6-A / L100R8-A / L100RB-A)
|
||||
#
|
||||
chip_id 0x429
|
||||
description L1xx Cat.2
|
||||
flash_type 5
|
||||
flash_pagesize 0x100
|
||||
sram_size 0x8000
|
||||
dev_type STM32L1xx_Cat_2
|
||||
ref_manual_id 0038
|
||||
chip_id 0x429 // STM32_CHIPID_L1_CAT2
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff8004c
|
||||
flash_pagesize 0x100 // 128 B
|
||||
sram_size 0x8000 // 32 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x1000
|
||||
bootrom_size 0x1000 // 4 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L1xx Cat.3
|
||||
# Chip-ID file for STM32L1xx (Cat.3) device (L100RC / L15xxC)
|
||||
#
|
||||
chip_id 0x427
|
||||
description L1xx Cat.3
|
||||
flash_type 5
|
||||
flash_pagesize 0x100
|
||||
sram_size 0x8000
|
||||
dev_type STM32L1xx_Cat_3
|
||||
ref_manual_id 0038
|
||||
chip_id 0x427 // STM32_CHIPID_L1_MD_PLUS
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff800cc
|
||||
flash_pagesize 0x100 // 128 B
|
||||
sram_size 0x8000 // 32 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x1000
|
||||
bootrom_size 0x1000 // 4 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L1xx Cat.4
|
||||
# Chip-ID file for STM32L1xx (Cat.4) device (L15xxD / L162xD)
|
||||
#
|
||||
chip_id 0x436
|
||||
description L1xx Cat.4
|
||||
flash_type 5
|
||||
flash_pagesize 0x100
|
||||
sram_size 0xc000
|
||||
dev_type STM32L1xx_Cat_4
|
||||
ref_manual_id 0038
|
||||
chip_id 0x436 // STM32_CHIPID_L1_MD_PLUS_HD
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff800cc
|
||||
flash_pagesize 0x100 // 128 B
|
||||
sram_size 0xc000 // 48 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x1000
|
||||
option_base 0x1ff80000
|
||||
option_size 0x8
|
||||
bootrom_size 0x1000 // 4 KB
|
||||
option_base 0x1ff80000 // STM32_L1_OPTION_BYTES_BASE
|
||||
option_size 0x8 // 8 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L1xx Cat.5
|
||||
# Chip-ID file for STM32L1xx (Cat.5) device (L15xxE / L162xE)
|
||||
#
|
||||
chip_id 0x437
|
||||
description L1xx Cat.5
|
||||
flash_type 5
|
||||
flash_pagesize 0x100
|
||||
sram_size 0x14000
|
||||
dev_type STM32L1xx_Cat_5
|
||||
ref_manual_id 0038
|
||||
chip_id 0x437 // STM32_CHIPID_L152_RE
|
||||
flash_type L0_L1
|
||||
flash_size_reg 0x1ff800cc
|
||||
flash_pagesize 0x100 // 128 B
|
||||
sram_size 0x14000 // 80 KB
|
||||
bootrom_base 0x1ff00000
|
||||
bootrom_size 0x1000
|
||||
bootrom_size 0x1000 // 4 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L41x/L42x
|
||||
# Chip-ID file for STM32L41x / STM32L42x device
|
||||
#
|
||||
chip_id 0x464
|
||||
description L41x/L42x
|
||||
flash_type 6
|
||||
flash_pagesize 0x800
|
||||
sram_size 0xa000
|
||||
dev_type STM32L41x_L42x
|
||||
ref_manual_id 0394
|
||||
chip_id 0x464 // STM32_CHIPID_L41x_L42x
|
||||
flash_type L4_L4P
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0xa000 // 40 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L43x/L44x
|
||||
# Chip-ID file for STM32L43x / STM32L44x device
|
||||
#
|
||||
chip_id 0x435
|
||||
description L43x/L44x
|
||||
flash_type 6
|
||||
flash_pagesize 0x800
|
||||
sram_size 0xc000
|
||||
dev_type STM32L41x_L42x
|
||||
ref_manual_id 0392
|
||||
chip_id 0x435 // STM32_CHIPID_L43x_L44x
|
||||
flash_type L4_L4P
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0xc000 // 48 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1fff7800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for L45x/46x
|
||||
#
|
||||
chip_id 0x462
|
||||
description L45x/46x
|
||||
flash_type 6
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x20000
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32L45x / STM32L46x device
|
||||
#
|
||||
dev_type STM32L45x_L46x
|
||||
ref_manual_id 0394
|
||||
chip_id 0x462 // STM32_CHIPID_L45x_L46x
|
||||
flash_type L4_L4P
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x20000 // 128 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L47x/L48x
|
||||
# Chip-ID file for STM32L47x / STM32L48x device
|
||||
#
|
||||
chip_id 0x415
|
||||
description L47x/L48x
|
||||
flash_type 6
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x18000
|
||||
dev_type STM32L47x_L48x
|
||||
ref_manual_id 0351
|
||||
chip_id 0x415 // STM32_CHIPID_L4
|
||||
flash_type L4_L4P
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x18000 // 96 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1fff7800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L496x/L4A6x
|
||||
# Chip-ID file for STM32L496x / STM32L4A6x device
|
||||
#
|
||||
chip_id 0x461
|
||||
description L496x/L4A6x
|
||||
flash_type 6
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x40000
|
||||
dev_type STM32L496x_L4A6x
|
||||
ref_manual_id 0351
|
||||
chip_id 0x461 // STM32_CHIPID_L496x_L4A6x
|
||||
flash_type L4_L4P
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x40000 // 256 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x1fff7800
|
||||
option_size 0x4
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE
|
||||
option_size 0x4 // 4 B
|
||||
flags swo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L4Px
|
||||
# Chip-ID file for STM32L4Px device
|
||||
#
|
||||
chip_id 0x471
|
||||
description L4Px
|
||||
flash_type 6
|
||||
flash_pagesize 0x1000
|
||||
sram_size 0xa0000
|
||||
dev_type STM32L4Px
|
||||
ref_manual_id 0432
|
||||
chip_id 0x471 // STM32_CHIPID_L4PX
|
||||
flash_type L4_L4P
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x1000 // 4 KB
|
||||
sram_size 0xa0000 // 640 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags dualbank swo
|
||||
|
||||
flags swo
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
# Chip-ID file for L4Rx
|
||||
# Chip-ID file for STM32L4Rx device
|
||||
#
|
||||
chip_id 0x470
|
||||
description L4Rx
|
||||
flash_type 6
|
||||
flash_pagesize 0x1000
|
||||
sram_size 0xa0000
|
||||
dev_type STM32L4Rx
|
||||
ref_manual_id 0432
|
||||
chip_id 0x470 // STM32_CHIPID_L4RX
|
||||
flash_type L4_L4P
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x1000 // 4 KB
|
||||
sram_size 0xa0000 // 640 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags dualbank swo
|
||||
|
||||
flags swo
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
# Chip-ID file for STM32L5x2 device
|
||||
#
|
||||
dev_type STM32L5x2
|
||||
ref_manual_id 0438
|
||||
chip_id 0x0 // (temporary setting only!)
|
||||
flash_type 0 // (temporary setting only!)
|
||||
flash_size_reg 0x0bfa07a0
|
||||
flash_pagesize 0x2000 // 8 KB
|
||||
sram_size 0x40000 // 256 KB
|
||||
bootrom_base 0x0bf90000
|
||||
bootrom_size 0x8000 // 32 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags none
|
||||
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Chip-ID file for STM32U5x5 device
|
||||
#
|
||||
dev_type STM32U5x5
|
||||
ref_manual_id 0456
|
||||
chip_id 0x0 // (temporary setting only!)
|
||||
flash_type 0 // (temporary setting only!)
|
||||
flash_size_reg 0x0bfa07a0
|
||||
flash_pagesize 0x2000 // 8 KB
|
||||
sram_size 0xc4800 // 786 KB
|
||||
bootrom_base 0x0bf90000
|
||||
bootrom_size 0x8000 // 32 KB
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags none
|
||||
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for WB5x/3x
|
||||
#
|
||||
chip_id 0x495
|
||||
description WB5x/3x
|
||||
flash_type 9
|
||||
flash_pagesize 0x1000
|
||||
sram_size 0x40000
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32WBx0 / STM32WBx5 device
|
||||
#
|
||||
dev_type STM32WBx0_WBx5
|
||||
ref_manual_id 0434 // also RM0471
|
||||
chip_id 0x495 // STM32_CHIPID_WB55
|
||||
flash_type WB_WL
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x1000 // 4 KB
|
||||
sram_size 0x40000 // 256 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fff8000
|
||||
option_size 0x80 // 128 B
|
||||
flags swo
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
# Chip-ID file for WLEx
|
||||
#
|
||||
chip_id 0x497
|
||||
description WLEx
|
||||
flash_type 9
|
||||
flash_pagesize 0x800
|
||||
sram_size 0x10000
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000
|
||||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags swo
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# Chip-ID file for STM32WLEx device
|
||||
#
|
||||
dev_type STM32WLEx
|
||||
ref_manual_id 0033
|
||||
chip_id 0x497 // STM32_CHIPID_WLE
|
||||
flash_type WB_WL
|
||||
flash_size_reg 0x1fff75e0
|
||||
flash_pagesize 0x800 // 2 KB
|
||||
sram_size 0x10000 // 64 KB
|
||||
bootrom_base 0x1fff0000
|
||||
bootrom_size 0x7000 // 28 KB
|
||||
option_base 0x1fffc000
|
||||
option_size 0x10 // 16 B
|
||||
flags swo
|
||||
|
|
@ -1,8 +1,10 @@
|
|||
# Chip-ID file for unknown device
|
||||
#
|
||||
chip_id 0x0
|
||||
description unknown device
|
||||
flash_type 0
|
||||
dev_type unknown
|
||||
ref_manual_id 0000
|
||||
chip_id 0x0 // STM32_CHIPID_UNKNOWN
|
||||
flash_type UNKNOWN
|
||||
flash_size_reg 0x0
|
||||
flash_pagesize 0x0
|
||||
sram_size 0x0
|
||||
bootrom_base 0x0
|
||||
|
|
@ -10,4 +12,3 @@ bootrom_size 0x0
|
|||
option_base 0x0
|
||||
option_size 0x0
|
||||
flags none
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
The following devices are supported by the stlink toolset.
|
||||
|
||||
## STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)
|
||||
## STM32F0 / ARM Cortex M0
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | ------------------- |
|
||||
|
|
@ -19,7 +19,7 @@ The following devices are supported by the stlink toolset.
|
|||
| 0x442 | STM32F0**9**xxx |
|
||||
|
||||
|
||||
## STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)
|
||||
## STM32F1 / ARM Cortex M3
|
||||
|
||||
| Product-Code | Product Line |
|
||||
| ----------------- | ----------------------- |
|
||||
|
|
@ -45,20 +45,20 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
- HY-STM32 (STM32F103VETx) [v1, v2]
|
||||
- DecaWave EVB1000 (STM32F105RCTx) [v1, v2]
|
||||
|
||||
## STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID)
|
||||
## STM32F2 / ARM Cortex M3
|
||||
|
||||
| Chip-ID | Product-Code | Product Line |
|
||||
| ------- | ------------ | ------------- |
|
||||
| 0x411 | STM32F2yyxx | (all devices) |
|
||||
|
||||
## STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID)
|
||||
## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!]
|
||||
|
||||
| Product-Code | Chip-ID | STLink<br />Programmer | Boards |
|
||||
| ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- |
|
||||
| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )<br />STM32F103C8T6 clone from China Key Systems (CKS) |
|
||||
| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)<br />STM32F103C8T6 clone from China Key Systems (CKS) |
|
||||
|
||||
## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID)
|
||||
## STM32F3 / ARM Cortex M4F
|
||||
|
||||
| Product-Code | Product Line |
|
||||
| ----------------- | ------------------------------------------------------------- |
|
||||
|
|
@ -85,13 +85,13 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x446 | _N/A_ | xD xE | | F302 | F303 | |
|
||||
| 0x446 | _N/A_ | - | | | | F398 |
|
||||
|
||||
## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)
|
||||
## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) [may work, but without support!]
|
||||
|
||||
| Product-Code | Chip-ID | STLINK<br />Programmer | Boards |
|
||||
| ------------ | ------- | ---------------------- | ---------------------------------- |
|
||||
| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD |
|
||||
|
||||
## STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)
|
||||
## STM32F4 / ARM Cortex M4F
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | ------------------- |
|
||||
|
|
@ -112,7 +112,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x463 | STM32F4**13**xx |
|
||||
| 0x463 | STM32F4**23**xx |
|
||||
|
||||
## STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)
|
||||
## STM32F7 / ARM Cortex M7F
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | --------------- |
|
||||
|
|
@ -123,7 +123,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x451 | STM32F7**6**xxx |
|
||||
| 0x451 | STM32F7**7**xxx |
|
||||
|
||||
## STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)
|
||||
## STM32H7 / ARM Cortex M7F
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | ------------- |
|
||||
|
|
@ -132,7 +132,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x480 | STM32H7**A**x |
|
||||
| 0x480 | STM32H7**B**x |
|
||||
|
||||
## STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)
|
||||
## STM32G0 / ARM Cortex M0+
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | --------------- |
|
||||
|
|
@ -141,7 +141,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x460 | STM32G0**7**xxx |
|
||||
| 0x460 | STM32G0**8**xxx |
|
||||
|
||||
## STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID)
|
||||
## STM32G4 / ARM Cortex M4F
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | --------------- |
|
||||
|
|
@ -151,7 +151,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x469 | STM32G4**8**xxx |
|
||||
| 0x479 | STM32G4**91**xx |
|
||||
|
||||
## STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)
|
||||
## STM32L0 / ARM Cortex M0+
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | --------------- |
|
||||
|
|
@ -164,7 +164,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x447 | STM32L0**7**xxx |
|
||||
| 0x447 | STM32L0**8**xxx |
|
||||
|
||||
## STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)
|
||||
## STM32L1 / ARM Cortex M3
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | ---------------- |
|
||||
|
|
@ -178,7 +178,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x436 | STM32L1xxx**D** |
|
||||
| 0x437 | STM32L1xxx**E** |
|
||||
|
||||
## STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)
|
||||
## STM32L4 / ARM Cortex M4F
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | --------------- |
|
||||
|
|
@ -197,7 +197,7 @@ Tested non-official ST boards [incl. STLINK programmers]:
|
|||
| 0x471 | STM32L4**P5**xx |
|
||||
| 0x471 | STM32L4**Q5**xx |
|
||||
|
||||
## STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)
|
||||
## STM32W / ARM Cortex M3
|
||||
|
||||
| Chip-ID | Product-Code |
|
||||
| ------- | --------------- |
|
||||
|
|
|
|||
|
|
@ -20,8 +20,7 @@ You can use this instead of st-util(1) if you prefer, but remember to use the
|
|||
|
||||
Use hexadecimal format for the *ADDR* and *SIZE*.
|
||||
|
||||
The STLink device to use can be specified using the --serial parameter, or via
|
||||
the environment variable STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.
|
||||
The STLink device to use can be specified using the --serial parameter.
|
||||
|
||||
# COMMANDS
|
||||
|
||||
|
|
@ -52,7 +51,7 @@ reset
|
|||
: Enable ignore ending empty bytes optimization
|
||||
|
||||
\--serial *iSerial*
|
||||
: TODO
|
||||
: Serial number of ST-LINK device to use
|
||||
|
||||
\--flash=fsize
|
||||
: Where fsize is the size in decimal, octal, or hex followed by an optional multiplier
|
||||
|
|
|
|||
|
|
@ -15,9 +15,6 @@ st-info - Provides information about connected STLink and STM32 devices
|
|||
Provides information about connected STLink programmers and STM32 devices:
|
||||
Serial code, flash, page size, sram, chipid, description.
|
||||
|
||||
The STLink device to probe can be specified via the environment variable
|
||||
STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.
|
||||
|
||||
# OPTIONS
|
||||
|
||||
\--version
|
||||
|
|
|
|||
|
|
@ -18,9 +18,6 @@ option, the default \f[B]4242\f[R] port will be used.
|
|||
.PP
|
||||
Stlink version 2 is used by default unless the option
|
||||
\f[B]\[en]stlinkv1\f[R] is given.
|
||||
.PP
|
||||
The STLinkV2 device to use can be specified in the environment variable
|
||||
STLINK_DEVICE on the format :.
|
||||
.SH OPTIONS
|
||||
.TP
|
||||
.B \-h, \-\-help
|
||||
|
|
|
|||
|
|
@ -17,8 +17,7 @@ Run the main binary of the local package (src/main.rs).
|
|||
If a port number is not specified using the **--listen_port** option, the
|
||||
default **4242** port will be used.
|
||||
|
||||
The STLink device to use can be specified using the --serial parameter, or via
|
||||
the environment variable STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.
|
||||
The STLink device to use can be specified using the --serial parameter.
|
||||
|
||||
# OPTIONS
|
||||
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \
|
|||
|
||||
and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output.
|
||||
|
||||
Make sure that you have all 4 files from here: https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following:
|
||||
Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following:
|
||||
|
||||
```
|
||||
sudo udevadm control --reload-rules
|
||||
|
|
@ -244,8 +244,7 @@ There are a few options:
|
|||
Do not reset board on connection.
|
||||
```
|
||||
|
||||
The STLink device to use can be specified using the --serial parameter, or via
|
||||
the environment variable STLINK_DEVICE on the format <USB_BUS>:<USB_ADDR>.
|
||||
The STLink device to use can be specified using the --serial parameter.
|
||||
|
||||
Then, in your project directory, someting like this...
|
||||
(remember, you need to run an _ARM_ gdb, not an x86 gdb)
|
||||
|
|
|
|||
24
inc/stlink.h
24
inc/stlink.h
|
|
@ -85,6 +85,10 @@ enum target_state {
|
|||
#define STLINK_F_HAS_DPBANKSEL (1 << 8)
|
||||
#define STLINK_F_HAS_RW8_512BYTES (1 << 9)
|
||||
|
||||
/* Additional MCU features */
|
||||
#define CHIP_F_HAS_DUAL_BANK (1 << 0)
|
||||
#define CHIP_F_HAS_SWO_TRACING (1 << 1)
|
||||
|
||||
/* Error code */
|
||||
#define STLINK_DEBUG_ERR_OK 0x80
|
||||
#define STLINK_DEBUG_ERR_FAULT 0x81
|
||||
|
|
@ -104,21 +108,6 @@ enum target_state {
|
|||
|
||||
#define C_BUF_LEN 32
|
||||
|
||||
enum stlink_flash_type {
|
||||
STLINK_FLASH_TYPE_UNKNOWN = 0,
|
||||
STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */
|
||||
STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */
|
||||
STLINK_FLASH_TYPE_F4, // used by f2, f4 */
|
||||
STLINK_FLASH_TYPE_F7,
|
||||
STLINK_FLASH_TYPE_L0, // l0, l1 */
|
||||
STLINK_FLASH_TYPE_L4, // l4, l4+ */
|
||||
STLINK_FLASH_TYPE_G0,
|
||||
STLINK_FLASH_TYPE_G4,
|
||||
STLINK_FLASH_TYPE_WB,
|
||||
STLINK_FLASH_TYPE_H7,
|
||||
STLINK_FLASH_TYPE_MAX,
|
||||
};
|
||||
|
||||
struct stlink_reg {
|
||||
uint32_t r[16];
|
||||
uint32_t s[32];
|
||||
|
|
@ -196,6 +185,7 @@ enum run_type {
|
|||
|
||||
typedef struct _stlink stlink_t;
|
||||
|
||||
#include <stm32.h>
|
||||
#include <backend.h>
|
||||
|
||||
struct _stlink {
|
||||
|
|
@ -218,8 +208,8 @@ struct _stlink {
|
|||
char serial[STLINK_SERIAL_BUFFER_SIZE];
|
||||
int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR
|
||||
|
||||
enum stlink_flash_type flash_type;
|
||||
// stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx
|
||||
enum stm32_flash_type flash_type;
|
||||
// stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx
|
||||
|
||||
stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params()
|
||||
size_t flash_size; // calculated by stlink_load_device_params()
|
||||
|
|
|
|||
543
inc/stm32.h
543
inc/stm32.h
|
|
@ -1,39 +1,536 @@
|
|||
/*
|
||||
* File: stm32.h
|
||||
*
|
||||
* STM32-specific defines
|
||||
* STM32-specific defines & identification parametres
|
||||
*/
|
||||
|
||||
#ifndef STM32_H
|
||||
#define STM32_H
|
||||
|
||||
/* Cortex core ids */
|
||||
#define STM32VL_CORE_ID 0x1ba01477
|
||||
#define STM32F7_CORE_ID 0x5ba02477
|
||||
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code
|
||||
#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065)
|
||||
/* STM32 Cortex-M core ids (CPUTAPID) */
|
||||
enum stm32_core_id {
|
||||
STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP
|
||||
// (RM0444 Section 40.5.3) G0 SW-DP
|
||||
STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP
|
||||
STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP
|
||||
STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG
|
||||
STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP
|
||||
// (RM0038 Section 30.8.3) L1 SW-DP
|
||||
STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG
|
||||
// (RM0038 Section 30.6.2) L1 JTAG
|
||||
STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP
|
||||
// (RM0351 Section 48.8.3) L4 SW-DP
|
||||
// (RM0432 Section 57.8.3) L4+ SW-DP
|
||||
STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG
|
||||
// (RM0351 Section 48.6.3) L4 JTAG
|
||||
// (RM0432 Section 57.6.3) L4+ JTAG
|
||||
STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP
|
||||
// (RM0090 Section 47.8.3) G4 SW-DP
|
||||
STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG
|
||||
// (RM0090 Section 47.6.3) G4 JTAG
|
||||
STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP
|
||||
STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG
|
||||
STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP
|
||||
STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG
|
||||
STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP
|
||||
// (RM0456 Section 65.3.3) U5 SW-DP
|
||||
STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP
|
||||
// (RM0456 Section 65.3.3) U5 JTAG-DP
|
||||
STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG
|
||||
// (RM0456 Section 56.3.1) U5 JTAG
|
||||
};
|
||||
|
||||
/* Constant STM32 memory map figures */
|
||||
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
|
||||
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
|
||||
#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000)
|
||||
#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000)
|
||||
/* STM32 flash types */
|
||||
enum stm32_flash_type {
|
||||
STM32_FLASH_TYPE_UNKNOWN = 0,
|
||||
STM32_FLASH_TYPE_F0_F1_F3 = 1,
|
||||
STM32_FLASH_TYPE_F1_XL = 2,
|
||||
STM32_FLASH_TYPE_F2_F4 = 3,
|
||||
STM32_FLASH_TYPE_F7 = 4,
|
||||
STM32_FLASH_TYPE_G0 = 5,
|
||||
STM32_FLASH_TYPE_G4 = 6,
|
||||
STM32_FLASH_TYPE_H7 = 7,
|
||||
STM32_FLASH_TYPE_L0_L1 = 8,
|
||||
STM32_FLASH_TYPE_L4_L4P = 9,
|
||||
STM32_FLASH_TYPE_L5_U5 = 10,
|
||||
STM32_FLASH_TYPE_WB_WL = 11,
|
||||
};
|
||||
|
||||
#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000)
|
||||
#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14)
|
||||
#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000)
|
||||
#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C)
|
||||
/* STM32 chip-ids */
|
||||
// See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual
|
||||
// stm32 chipids, only lower 12 bits...
|
||||
|
||||
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
|
||||
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
|
||||
enum stm32_chipids {
|
||||
STM32_CHIPID_UNKNOWN = 0x000,
|
||||
|
||||
#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
|
||||
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
|
||||
STM32_CHIPID_F1_MD = 0x410, /* medium density */
|
||||
STM32_CHIPID_F2 = 0x411,
|
||||
STM32_CHIPID_F1_LD = 0x412, /* low density */
|
||||
STM32_CHIPID_F4 = 0x413,
|
||||
STM32_CHIPID_F1_HD = 0x414, /* high density */
|
||||
STM32_CHIPID_L4 = 0x415,
|
||||
STM32_CHIPID_L1_MD = 0x416, /* medium density */
|
||||
STM32_CHIPID_L0 = 0x417,
|
||||
STM32_CHIPID_F1_CONN = 0x418, /* connectivity line */
|
||||
STM32_CHIPID_F4_HD = 0x419, /* high density */
|
||||
STM32_CHIPID_F1_VL_MD_LD = 0x420, /* value line medium & low density */
|
||||
STM32_CHIPID_F446 = 0x421,
|
||||
STM32_CHIPID_F3 = 0x422,
|
||||
STM32_CHIPID_F4_LP = 0x423,
|
||||
STM32_CHIPID_L0_CAT2 = 0x425,
|
||||
STM32_CHIPID_L1_MD_PLUS = 0x427, /* medium density plus */
|
||||
STM32_CHIPID_F1_VL_HD = 0x428, /* value line high density */
|
||||
STM32_CHIPID_L1_CAT2 = 0x429,
|
||||
STM32_CHIPID_F1_XLD = 0x430, /* extra low density plus */
|
||||
STM32_CHIPID_F411xx = 0x431,
|
||||
STM32_CHIPID_F37x = 0x432,
|
||||
STM32_CHIPID_F4_DE = 0x433,
|
||||
STM32_CHIPID_F4_DSI = 0x434,
|
||||
STM32_CHIPID_L43x_L44x = 0x435,
|
||||
STM32_CHIPID_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */
|
||||
STM32_CHIPID_L152_RE = 0x437,
|
||||
STM32_CHIPID_F334 = 0x438,
|
||||
STM32_CHIPID_F3xx_SMALL = 0x439,
|
||||
STM32_CHIPID_F0 = 0x440,
|
||||
STM32_CHIPID_F412 = 0x441,
|
||||
STM32_CHIPID_F09x = 0x442,
|
||||
STM32_CHIPID_F0xx_SMALL = 0x444,
|
||||
STM32_CHIPID_F04 = 0x445,
|
||||
STM32_CHIPID_F303_HD = 0x446, /* high density */
|
||||
STM32_CHIPID_L0_CAT5 = 0x447,
|
||||
STM32_CHIPID_F0_CAN = 0x448,
|
||||
STM32_CHIPID_F7 = 0x449, /* Nucleo F746ZG board */
|
||||
STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */
|
||||
STM32_CHIPID_F76xxx = 0x451,
|
||||
STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */
|
||||
STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */
|
||||
STM32_CHIPID_L011 = 0x457,
|
||||
STM32_CHIPID_F410 = 0x458,
|
||||
STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */
|
||||
STM32_CHIPID_L496x_L4A6x = 0x461,
|
||||
STM32_CHIPID_L45x_L46x = 0x462,
|
||||
STM32_CHIPID_F413 = 0x463,
|
||||
STM32_CHIPID_L41x_L42x = 0x464,
|
||||
STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */
|
||||
STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */
|
||||
STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */
|
||||
STM32_CHIPID_G4_CAT3 = 0x469,
|
||||
STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */
|
||||
STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */
|
||||
STM32_CHIPID_G4_CAT4 = 0x479,
|
||||
STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */
|
||||
STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */
|
||||
STM32_CHIPID_WB55 = 0x495,
|
||||
STM32_CHIPID_WLE = 0x497,
|
||||
};
|
||||
|
||||
#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
|
||||
#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
|
||||
#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
|
||||
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
|
||||
/* Constant STM32 option bytes base memory address */
|
||||
#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14)
|
||||
|
||||
#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c)
|
||||
|
||||
#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1ff80000)
|
||||
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1ff80000)
|
||||
|
||||
#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1fff0000)
|
||||
|
||||
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800)
|
||||
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1fff7800)
|
||||
|
||||
#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1fffc000)
|
||||
|
||||
#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
|
||||
#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
|
||||
#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
|
||||
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
|
||||
|
||||
/* ============ */
|
||||
/* Old defines from common.c are below */
|
||||
/* ============ */
|
||||
|
||||
/* Constant STM32 memory address */
|
||||
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
|
||||
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
|
||||
|
||||
#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000)
|
||||
#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000)
|
||||
|
||||
/* stm32f FPEC flash controller interface, pm0063 manual */
|
||||
// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012)
|
||||
#define FLASH_REGS_ADDR 0x40022000
|
||||
#define FLASH_REGS_SIZE 0x28
|
||||
|
||||
#define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
|
||||
#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
|
||||
#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08)
|
||||
#define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
|
||||
#define FLASH_CR (FLASH_REGS_ADDR + 0x10)
|
||||
#define FLASH_AR (FLASH_REGS_ADDR + 0x14)
|
||||
#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
|
||||
#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
|
||||
|
||||
// STM32F10x_XL has two flash memory banks with separate registers to control
|
||||
// the second bank.
|
||||
#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44)
|
||||
#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c)
|
||||
#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50)
|
||||
#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54)
|
||||
|
||||
// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere...
|
||||
#define FLASH_RDPTR_KEY 0x00a5
|
||||
#define FLASH_KEY1 0x45670123
|
||||
#define FLASH_KEY2 0xcdef89ab
|
||||
|
||||
#define FLASH_L0_PRGKEY1 0x8c9daebf
|
||||
#define FLASH_L0_PRGKEY2 0x13141516
|
||||
|
||||
#define FLASH_L0_PEKEY1 0x89abcdef
|
||||
#define FLASH_L0_PEKEY2 0x02030405
|
||||
|
||||
#define FLASH_OPTKEY1 0x08192A3B
|
||||
#define FLASH_OPTKEY2 0x4C5D6E7F
|
||||
|
||||
#define FLASH_F0_OPTKEY1 0x45670123
|
||||
#define FLASH_F0_OPTKEY2 0xCDEF89AB
|
||||
|
||||
#define FLASH_L0_OPTKEY1 0xFBEAD9C8
|
||||
#define FLASH_L0_OPTKEY2 0x24252627
|
||||
|
||||
#define FLASH_SR_BSY 0
|
||||
#define FLASH_SR_PG_ERR 2
|
||||
#define FLASH_SR_WRPRT_ERR 4
|
||||
#define FLASH_SR_EOP 5
|
||||
|
||||
#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR))
|
||||
|
||||
#define FLASH_CR_PG 0
|
||||
#define FLASH_CR_PER 1
|
||||
#define FLASH_CR_MER 2
|
||||
#define FLASH_CR_OPTPG 4
|
||||
#define FLASH_CR_OPTER 5
|
||||
#define FLASH_CR_STRT 6
|
||||
#define FLASH_CR_LOCK 7
|
||||
#define FLASH_CR_OPTWRE 9
|
||||
#define FLASH_CR_OBL_LAUNCH 13
|
||||
|
||||
#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
|
||||
#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
|
||||
#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
|
||||
#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
|
||||
#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
|
||||
#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
|
||||
#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
|
||||
#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
|
||||
#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
|
||||
#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
|
||||
#define FLASH_L1_FPRG 10
|
||||
#define FLASH_L1_PROG 3
|
||||
|
||||
// Flash registers common to STM32G0 and STM32G4 series.
|
||||
#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000)
|
||||
#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00)
|
||||
#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08)
|
||||
#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c)
|
||||
#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10)
|
||||
#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14)
|
||||
#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18)
|
||||
#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20)
|
||||
|
||||
// G0 (RM0444 Table 1, sec 3.7)
|
||||
// Mostly the same as G4 chips, but the notation
|
||||
// varies a bit after the 'OPTR' register.
|
||||
#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR)
|
||||
#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24)
|
||||
#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28)
|
||||
#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C)
|
||||
#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30)
|
||||
#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34)
|
||||
#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38)
|
||||
#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80)
|
||||
|
||||
// G4 (RM0440 Table 17, sec 3.7.19)
|
||||
// Mostly the same as STM32G0 chips, but there are a few extra
|
||||
// registers because 'cat 3' devices can have two Flash banks.
|
||||
#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR)
|
||||
#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04)
|
||||
#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24)
|
||||
#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28)
|
||||
#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C)
|
||||
#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30)
|
||||
#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44)
|
||||
#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48)
|
||||
#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C)
|
||||
#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50)
|
||||
#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70)
|
||||
#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74)
|
||||
|
||||
// G0/G4 FLASH control register
|
||||
#define STM32Gx_FLASH_CR_PG (0) /* Program */
|
||||
#define STM32Gx_FLASH_CR_PER (1) /* Page erase */
|
||||
#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */
|
||||
#define STM32Gx_FLASH_CR_PNB (3) /* Page number */
|
||||
#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */
|
||||
#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */
|
||||
#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/
|
||||
#define STM32Gx_FLASH_CR_STRT (16) /* Start */
|
||||
#define STM32Gx_FLASH_CR_OPTSTRT \
|
||||
(17) /* Start of modification of option bytes */
|
||||
#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */
|
||||
#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */
|
||||
#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */
|
||||
#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */
|
||||
#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */
|
||||
#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */
|
||||
|
||||
// G0/G4 FLASH status register
|
||||
#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa)
|
||||
#define STM32Gx_FLASH_SR_PROGERR (3)
|
||||
#define STM32Gx_FLASH_SR_WRPERR (4)
|
||||
#define STM32Gx_FLASH_SR_PGAERR (5)
|
||||
#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */
|
||||
#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */
|
||||
|
||||
// G4 FLASH option register
|
||||
#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */
|
||||
|
||||
// WB (RM0434)
|
||||
#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000)
|
||||
#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00)
|
||||
#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08)
|
||||
#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C)
|
||||
#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10)
|
||||
#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14)
|
||||
#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18)
|
||||
#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20)
|
||||
#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24)
|
||||
#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28)
|
||||
#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C)
|
||||
#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30)
|
||||
#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34)
|
||||
#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38)
|
||||
#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C)
|
||||
#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C)
|
||||
#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60)
|
||||
#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64)
|
||||
#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80)
|
||||
#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84)
|
||||
|
||||
// WB Flash control register.
|
||||
#define STM32WB_FLASH_CR_STRT (16) /* Start */
|
||||
#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */
|
||||
#define STM32WB_FLASH_CR_LOCK (31) /* Lock */
|
||||
// WB Flash status register.
|
||||
#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */
|
||||
#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */
|
||||
#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */
|
||||
#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */
|
||||
#define STM32WB_FLASH_SR_BSY (16) /* Busy */
|
||||
|
||||
// 32L4 register base is at FLASH_REGS_ADDR (0x40022000)
|
||||
#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08)
|
||||
#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C)
|
||||
#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10)
|
||||
#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14)
|
||||
#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20)
|
||||
|
||||
#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */
|
||||
#define STM32L4_FLASH_SR_PROGERR 3
|
||||
#define STM32L4_FLASH_SR_WRPERR 4
|
||||
#define STM32L4_FLASH_SR_PGAERR 5
|
||||
#define STM32L4_FLASH_SR_BSY 16
|
||||
|
||||
#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */
|
||||
#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */
|
||||
#define STM32L4_FLASH_CR_PG 0 /* Program */
|
||||
#define STM32L4_FLASH_CR_PER 1 /* Page erase */
|
||||
#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */
|
||||
#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */
|
||||
#define STM32L4_FLASH_CR_STRT 16 /* Start command */
|
||||
#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */
|
||||
#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */
|
||||
#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */
|
||||
#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */
|
||||
// Bits requesting flash operations (useful when we want to clear them)
|
||||
#define STM32L4_FLASH_CR_OPBITS \
|
||||
(uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \
|
||||
(1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1))
|
||||
// Page is fully specified by BKER and PNB
|
||||
#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB)
|
||||
|
||||
#define STM32L4_FLASH_OPTR_DUALBANK 21
|
||||
|
||||
// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf
|
||||
#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000)
|
||||
|
||||
#define STM32L0_FLASH_PELOCK (0)
|
||||
#define STM32L0_FLASH_OPTLOCK (2)
|
||||
#define STM32L0_FLASH_OBL_LAUNCH (18)
|
||||
|
||||
#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00
|
||||
#define STM32L0_FLASH_SR_WRPERR 8
|
||||
#define STM32L0_FLASH_SR_PGAERR 9
|
||||
#define STM32L0_FLASH_SR_NOTZEROERR 16
|
||||
|
||||
#define FLASH_ACR_OFF ((uint32_t)0x00)
|
||||
#define FLASH_PECR_OFF ((uint32_t)0x04)
|
||||
#define FLASH_PDKEYR_OFF ((uint32_t)0x08)
|
||||
#define FLASH_PEKEYR_OFF ((uint32_t)0x0c)
|
||||
#define FLASH_PRGKEYR_OFF ((uint32_t)0x10)
|
||||
#define FLASH_OPTKEYR_OFF ((uint32_t)0x14)
|
||||
#define FLASH_SR_OFF ((uint32_t)0x18)
|
||||
#define FLASH_OBR_OFF ((uint32_t)0x1c)
|
||||
#define FLASH_WRPR_OFF ((uint32_t)0x20)
|
||||
|
||||
// STM32F7
|
||||
#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00)
|
||||
#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04)
|
||||
#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08)
|
||||
#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c)
|
||||
#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10)
|
||||
#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14)
|
||||
#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18)
|
||||
#define FLASH_F7_OPTCR_LOCK 0
|
||||
#define FLASH_F7_OPTCR_START 1
|
||||
#define FLASH_F7_CR_STRT 16
|
||||
#define FLASH_F7_CR_LOCK 31
|
||||
#define FLASH_F7_CR_SER 1
|
||||
#define FLASH_F7_CR_SNB 3
|
||||
#define FLASH_F7_CR_SNB_MASK 0xf8
|
||||
#define FLASH_F7_SR_BSY 16
|
||||
#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */
|
||||
#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */
|
||||
#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */
|
||||
#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */
|
||||
#define FLASH_F7_SR_OP_ERR 1 /* Operation error */
|
||||
#define FLASH_F7_SR_EOP 0 /* End of operation */
|
||||
#define FLASH_F7_OPTCR1_BOOT_ADD0 0
|
||||
#define FLASH_F7_OPTCR1_BOOT_ADD1 16
|
||||
|
||||
#define FLASH_F7_SR_ERROR_MASK \
|
||||
((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \
|
||||
(1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \
|
||||
(1 << FLASH_F7_SR_OP_ERR))
|
||||
|
||||
// STM32F4
|
||||
#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
|
||||
#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
|
||||
#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
|
||||
#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
|
||||
#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
|
||||
#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14)
|
||||
#define FLASH_F4_OPTCR_LOCK 0
|
||||
#define FLASH_F4_OPTCR_START 1
|
||||
#define FLASH_F4_CR_STRT 16
|
||||
#define FLASH_F4_CR_LOCK 31
|
||||
#define FLASH_F4_CR_SER 1
|
||||
#define FLASH_F4_CR_SNB 3
|
||||
#define FLASH_F4_CR_SNB_MASK 0xf8
|
||||
#define FLASH_F4_SR_ERROR_MASK 0x000000F0
|
||||
#define FLASH_F4_SR_PGAERR 5
|
||||
#define FLASH_F4_SR_WRPERR 4
|
||||
#define FLASH_F4_SR_BSY 16
|
||||
|
||||
// STM32F2
|
||||
#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00)
|
||||
#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04)
|
||||
#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08)
|
||||
#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c)
|
||||
#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10)
|
||||
#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14)
|
||||
#define FLASH_F2_OPT_LOCK_BIT (1u << 0)
|
||||
#define FLASH_F2_CR_STRT 16
|
||||
#define FLASH_F2_CR_LOCK 31
|
||||
|
||||
#define FLASH_F2_CR_SER 1
|
||||
#define FLASH_F2_CR_SNB 3
|
||||
#define FLASH_F2_CR_SNB_MASK 0x78
|
||||
#define FLASH_F2_SR_BSY 16
|
||||
|
||||
// STM32H7xx
|
||||
#define FLASH_H7_CR_LOCK 0
|
||||
#define FLASH_H7_CR_PG 1
|
||||
#define FLASH_H7_CR_SER 2
|
||||
#define FLASH_H7_CR_BER 3
|
||||
#define FLASH_H7_CR_PSIZE 4
|
||||
#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7)
|
||||
#define FLASH_H7_CR_SNB 8
|
||||
#define FLASH_H7_CR_SNB_MASK 0x700
|
||||
|
||||
#define FLASH_H7_SR_QW 2
|
||||
#define FLASH_H7_SR_WRPERR 17
|
||||
#define FLASH_H7_SR_PGSERR 18
|
||||
#define FLASH_H7_SR_STRBERR 19
|
||||
#define FLASH_H7_SR_ERROR_MASK \
|
||||
((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \
|
||||
(1 << FLASH_H7_SR_WRPERR))
|
||||
|
||||
#define FLASH_H7_OPTCR_OPTLOCK 0
|
||||
#define FLASH_H7_OPTCR_OPTSTART 1
|
||||
#define FLASH_H7_OPTCR_MER 4
|
||||
|
||||
#define FLASH_H7_OPTSR_OPT_BUSY 0
|
||||
#define FLASH_H7_OPTSR_OPTCHANGEERR 30
|
||||
|
||||
#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30
|
||||
|
||||
#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000)
|
||||
#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04)
|
||||
#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104)
|
||||
#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08)
|
||||
#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108)
|
||||
#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c)
|
||||
#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c)
|
||||
#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10)
|
||||
#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110)
|
||||
#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14)
|
||||
#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114)
|
||||
#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18)
|
||||
#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118)
|
||||
#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c)
|
||||
#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24)
|
||||
|
||||
#define STM32F0_DBGMCU_CR 0xE0042004
|
||||
#define STM32F0_DBGMCU_CR_IWDG_STOP 8
|
||||
#define STM32F0_DBGMCU_CR_WWDG_STOP 9
|
||||
|
||||
#define STM32F4_DBGMCU_APB1FZR1 0xE0042008
|
||||
#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11
|
||||
#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12
|
||||
|
||||
#define STM32L0_DBGMCU_APB1_FZ 0x40015808
|
||||
#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11
|
||||
#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12
|
||||
|
||||
#define STM32H7_DBGMCU_APB1HFZ 0x5C001054
|
||||
#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18
|
||||
|
||||
#define STM32WB_DBGMCU_APB1FZR1 0xE004203C
|
||||
#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11
|
||||
#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12
|
||||
|
||||
#define STM32F1_RCC_AHBENR 0x40021014
|
||||
#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
|
||||
|
||||
#define STM32F4_RCC_AHB1ENR 0x40023830
|
||||
#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN
|
||||
|
||||
#define STM32G0_RCC_AHBENR 0x40021038
|
||||
#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
|
||||
|
||||
#define STM32G4_RCC_AHB1ENR 0x40021048
|
||||
#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
|
||||
|
||||
#define STM32L0_RCC_AHBENR 0x40021030
|
||||
#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN
|
||||
|
||||
#define STM32H7_RCC_AHB1ENR 0x58024538
|
||||
#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
|
||||
|
||||
#define STM32WB_RCC_AHB1ENR 0x58000048
|
||||
#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN
|
||||
|
||||
#define L1_WRITE_BLOCK_SIZE 0x80
|
||||
#define L0_WRITE_BLOCK_SIZE 0x40
|
||||
|
||||
#define STM32F0_DBGMCU_CR 0xE0042004
|
||||
#define STM32F0_DBGMCU_CR_IWDG_STOP 8
|
||||
|
|
|
|||
28
src/common.c
28
src/common.c
|
|
@ -64,7 +64,7 @@ void stlink_close(stlink_t *sl) {
|
|||
int stlink_exit_debug_mode(stlink_t *sl) {
|
||||
DLOG("*** stlink_exit_debug_mode ***\n");
|
||||
|
||||
if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN &&
|
||||
if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN &&
|
||||
sl->core_stat != TARGET_RESET) {
|
||||
// stop debugging if the target has been identified
|
||||
stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY);
|
||||
|
|
@ -225,7 +225,7 @@ int stlink_load_device_params(stlink_t *sl) {
|
|||
return (-1);
|
||||
}
|
||||
|
||||
if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) {
|
||||
if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) {
|
||||
WLOG("Invalid flash type, please check device declaration\n");
|
||||
sl->flash_size = 0;
|
||||
return (0);
|
||||
|
|
@ -287,7 +287,7 @@ int stlink_load_device_params(stlink_t *sl) {
|
|||
|
||||
// H7 devices with small flash has one bank
|
||||
if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK &&
|
||||
sl->flash_type == STLINK_FLASH_TYPE_H7) {
|
||||
sl->flash_type == STM32_FLASH_TYPE_H7) {
|
||||
if ((sl->flash_size / sl->flash_pgsz) <= 1)
|
||||
sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK;
|
||||
}
|
||||
|
|
@ -913,7 +913,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem,
|
|||
}
|
||||
// 280
|
||||
uint8_t stlink_get_erased_pattern(stlink_t *sl) {
|
||||
if (sl->flash_type == STLINK_FLASH_TYPE_L0) {
|
||||
if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) {
|
||||
return (0x00);
|
||||
} else {
|
||||
return (0xff);
|
||||
|
|
@ -975,31 +975,31 @@ static void stop_wdg_in_debug(stlink_t *sl) {
|
|||
uint32_t value;
|
||||
|
||||
switch (sl->flash_type) {
|
||||
case STLINK_FLASH_TYPE_F0:
|
||||
case STLINK_FLASH_TYPE_F1_XL:
|
||||
case STLINK_FLASH_TYPE_G4:
|
||||
case STM32_FLASH_TYPE_F0_F1_F3:
|
||||
case STM32_FLASH_TYPE_F1_XL:
|
||||
case STM32_FLASH_TYPE_G4:
|
||||
dbgmcu_cr = STM32F0_DBGMCU_CR;
|
||||
set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) |
|
||||
(1 << STM32F0_DBGMCU_CR_WWDG_STOP);
|
||||
break;
|
||||
case STLINK_FLASH_TYPE_F4:
|
||||
case STLINK_FLASH_TYPE_F7:
|
||||
case STLINK_FLASH_TYPE_L4:
|
||||
case STM32_FLASH_TYPE_F2_F4:
|
||||
case STM32_FLASH_TYPE_F7:
|
||||
case STM32_FLASH_TYPE_L4:
|
||||
dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1;
|
||||
set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) |
|
||||
(1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP);
|
||||
break;
|
||||
case STLINK_FLASH_TYPE_L0:
|
||||
case STLINK_FLASH_TYPE_G0:
|
||||
case STM32_FLASH_TYPE_L0_L1:
|
||||
case STM32_FLASH_TYPE_G0:
|
||||
dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ;
|
||||
set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) |
|
||||
(1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP);
|
||||
break;
|
||||
case STLINK_FLASH_TYPE_H7:
|
||||
case STM32_FLASH_TYPE_H7:
|
||||
dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ;
|
||||
set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP);
|
||||
break;
|
||||
case STLINK_FLASH_TYPE_WB:
|
||||
case STM32_FLASH_TYPE_WB:
|
||||
dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1;
|
||||
set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) |
|
||||
(1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP);
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
#include <string.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <stm32.h>
|
||||
#include <stlink.h>
|
||||
#include "flash.h"
|
||||
|
||||
|
|
@ -67,7 +68,7 @@ int main(int ac, char** av) {
|
|||
|
||||
if (sl == NULL) { return(-1); }
|
||||
|
||||
if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) {
|
||||
if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) {
|
||||
printf("Failed to connect to target\n");
|
||||
goto on_error;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,16 +33,14 @@ static void stlink_print_info(stlink_t *sl) {
|
|||
|
||||
if (!sl) { return; }
|
||||
|
||||
printf(" version: ");
|
||||
stlink_print_version(sl);
|
||||
printf(" version: "); stlink_print_version(sl);
|
||||
printf(" serial: %s\n", sl->serial);
|
||||
printf(" flash: %u (pagesize: %u)\n",
|
||||
(uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz);
|
||||
printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz);
|
||||
printf(" sram: %u\n", (uint32_t)sl->sram_size);
|
||||
printf(" chipid: 0x%.4x\n", sl->chip_id);
|
||||
printf(" chipid: 0x%.3x\n", sl->chip_id);
|
||||
|
||||
params = stlink_chipid_get_params(sl->chip_id);
|
||||
if (params) { printf(" descr: %s\n", params->description); }
|
||||
if (params) { printf(" dev-type: %s\n", params->dev_type); }
|
||||
}
|
||||
|
||||
static void stlink_probe(enum connect_type connect, int freq) {
|
||||
|
|
@ -118,7 +116,7 @@ static int print_data(int ac, char **av) {
|
|||
const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id);
|
||||
if (params == NULL) { return(-1); }
|
||||
|
||||
printf("%s\n", params->description);
|
||||
printf("%s\n", params->dev_type);
|
||||
}
|
||||
|
||||
if (sl) {
|
||||
|
|
|
|||
|
|
@ -540,7 +540,7 @@ int main(int argc, char **argv) {
|
|||
|
||||
stlink->verbose = settings.logging_level;
|
||||
|
||||
if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) {
|
||||
if (stlink->chip_id == STM32_CHIPID_UNKNOWN) {
|
||||
ELOG("Your stlink is not connected to a device\n");
|
||||
if (!settings.force)
|
||||
return APP_RESULT_STLINK_MISSING_DEVICE;
|
||||
|
|
@ -555,7 +555,7 @@ int main(int argc, char **argv) {
|
|||
if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) {
|
||||
const struct stlink_chipid_params *params =
|
||||
stlink_chipid_get_params(stlink->chip_id);
|
||||
ELOG("We do not support SWO output for device '%s'\n", params->description);
|
||||
ELOG("We do not support SWO output for device '%s'\n", params->dev_type);
|
||||
if (!settings.force)
|
||||
return APP_RESULT_STLINK_UNSUPPORTED_DEVICE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -226,7 +226,7 @@ int main(int argc, char** argv) {
|
|||
sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq);
|
||||
if (sl == NULL) { return(1); }
|
||||
|
||||
if (sl->chip_id == STLINK_CHIPID_UNKNOWN) {
|
||||
if (sl->chip_id == STM32_CHIPID_UNKNOWN) {
|
||||
ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id);
|
||||
return(1);
|
||||
}
|
||||
|
|
@ -553,39 +553,39 @@ char* make_memory_map(stlink_t *sl) {
|
|||
char* map = malloc(sz);
|
||||
map[0] = '\0';
|
||||
|
||||
if (sl->chip_id == STLINK_CHIPID_STM32_F4 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F446 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F411xx) {
|
||||
if (sl->chip_id == STM32_CHIPID_F4 ||
|
||||
sl->chip_id == STM32_CHIPID_F446 ||
|
||||
sl->chip_id == STM32_CHIPID_F411xx) {
|
||||
strcpy(map, memory_map_template_F4);
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_F4_DE) {
|
||||
strcpy(map, memory_map_template_F4_DE);
|
||||
} else if (sl->core_id == STM32F7_CORE_ID) {
|
||||
} else if (sl->core_id == STM32_CORE_ID_M7F_SWD) {
|
||||
snprintf(map, sz, memory_map_template_F7,
|
||||
(unsigned int)sl->sram_size);
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_H74xxx) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_H74xxx) {
|
||||
snprintf(map, sz, memory_map_template_H7,
|
||||
(unsigned int)sl->flash_size,
|
||||
(unsigned int)sl->flash_pgsz);
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_F4_HD) {
|
||||
strcpy(map, memory_map_template_F4_HD);
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_F2) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_F2) {
|
||||
snprintf(map, sz, memory_map_template_F2,
|
||||
(unsigned int)sl->flash_size,
|
||||
(unsigned int)sl->sram_size,
|
||||
(unsigned int)sl->flash_size - 0x20000,
|
||||
(unsigned int)sl->sys_base,
|
||||
(unsigned int)sl->sys_size);
|
||||
} else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) ||
|
||||
(sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) ||
|
||||
(sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x)) {
|
||||
} else if ((sl->chip_id == STM32_CHIPID_L4) ||
|
||||
(sl->chip_id == STM32_CHIPID_L43x_L44x) ||
|
||||
(sl->chip_id == STM32_CHIPID_L45x_L46x)) {
|
||||
snprintf(map, sz, memory_map_template_L4,
|
||||
(unsigned int)sl->flash_size,
|
||||
(unsigned int)sl->flash_size);
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) {
|
||||
snprintf(map, sz, memory_map_template_L496,
|
||||
(unsigned int)sl->flash_size,
|
||||
(unsigned int)sl->flash_size);
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_H72x) {
|
||||
snprintf(map, sz, memory_map_template_H72x3x,
|
||||
(unsigned int)sl->flash_size,
|
||||
(unsigned int)sl->flash_pgsz);
|
||||
|
|
@ -1847,7 +1847,7 @@ int serve(stlink_t *sl, st_state_t *st) {
|
|||
stlink_close(sl);
|
||||
|
||||
sl = stlink_open_usb(st->logging_level, st->connect_mode, st->serialnumber, st->freq);
|
||||
if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); }
|
||||
if (sl == NULL || sl->chip_id == STM32_CHIPID_UNKNOWN) { cleanup(0); }
|
||||
|
||||
connected_stlink = sl;
|
||||
|
||||
|
|
|
|||
|
|
@ -429,7 +429,7 @@ static gchar *dev_format_chip_id(guint32 chip_id) {
|
|||
|
||||
if (!params) { return(g_strdup_printf("0x%x", chip_id)); }
|
||||
|
||||
return(g_strdup(params->description));
|
||||
return(g_strdup(params->dev_type));
|
||||
}
|
||||
|
||||
static gchar *dev_format_mem_size(gsize flash_size) {
|
||||
|
|
|
|||
Plik diff jest za duży
Load Diff
|
|
@ -1,87 +1,15 @@
|
|||
#ifndef STLINK_CHIPID_H_
|
||||
#define STLINK_CHIPID_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include <stm32.h>
|
||||
#include <stlink.h>
|
||||
|
||||
/**
|
||||
* Chip IDs are explained in the appropriate programming manual for the
|
||||
* DBGMCU_IDCODE register (0xE0042000)
|
||||
* stm32 chipids, only lower 12 bits...
|
||||
*/
|
||||
enum stlink_stm32_chipids {
|
||||
STLINK_CHIPID_UNKNOWN = 0x000,
|
||||
|
||||
STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */
|
||||
STLINK_CHIPID_STM32_F2 = 0x411,
|
||||
STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */
|
||||
STLINK_CHIPID_STM32_F4 = 0x413,
|
||||
STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */
|
||||
STLINK_CHIPID_STM32_L4 = 0x415,
|
||||
STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */
|
||||
STLINK_CHIPID_STM32_L0 = 0x417,
|
||||
STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */
|
||||
STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */
|
||||
STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */
|
||||
STLINK_CHIPID_STM32_F446 = 0x421,
|
||||
STLINK_CHIPID_STM32_F3 = 0x422,
|
||||
STLINK_CHIPID_STM32_F4_LP = 0x423,
|
||||
STLINK_CHIPID_STM32_L0_CAT2 = 0x425,
|
||||
STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */
|
||||
STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */
|
||||
STLINK_CHIPID_STM32_L1_CAT2 = 0x429,
|
||||
STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */
|
||||
STLINK_CHIPID_STM32_F411xx = 0x431,
|
||||
STLINK_CHIPID_STM32_F37x = 0x432,
|
||||
STLINK_CHIPID_STM32_F4_DE = 0x433,
|
||||
STLINK_CHIPID_STM32_F4_DSI = 0x434,
|
||||
STLINK_CHIPID_STM32_L43x_L44x = 0x435,
|
||||
STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */
|
||||
STLINK_CHIPID_STM32_L152_RE = 0x437,
|
||||
STLINK_CHIPID_STM32_F334 = 0x438,
|
||||
STLINK_CHIPID_STM32_F3xx_SMALL = 0x439,
|
||||
STLINK_CHIPID_STM32_F0 = 0x440,
|
||||
STLINK_CHIPID_STM32_F412 = 0x441,
|
||||
STLINK_CHIPID_STM32_F09x = 0x442,
|
||||
STLINK_CHIPID_STM32_F0xx_SMALL = 0x444,
|
||||
STLINK_CHIPID_STM32_F04 = 0x445,
|
||||
STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */
|
||||
STLINK_CHIPID_STM32_L0_CAT5 = 0x447,
|
||||
STLINK_CHIPID_STM32_F0_CAN = 0x448,
|
||||
STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the Nucleo F746ZG board */
|
||||
STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */
|
||||
STLINK_CHIPID_STM32_F76xxx = 0x451,
|
||||
STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the Nucleo F722ZE board */
|
||||
STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */
|
||||
STLINK_CHIPID_STM32_L011 = 0x457,
|
||||
STLINK_CHIPID_STM32_F410 = 0x458,
|
||||
STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */
|
||||
STLINK_CHIPID_STM32_L496x_L4A6x = 0x461,
|
||||
STLINK_CHIPID_STM32_L45x_L46x = 0x462,
|
||||
STLINK_CHIPID_STM32_F413 = 0x463,
|
||||
STLINK_CHIPID_STM32_L41x_L42x = 0x464,
|
||||
STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */
|
||||
STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */
|
||||
STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */
|
||||
STLINK_CHIPID_STM32_G4_CAT3 = 0x469,
|
||||
STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p. 2247, found on the STM32L4R9I-DISCO board */
|
||||
STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */
|
||||
STLINK_CHIPID_STM32_G4_CAT4 = 0x479,
|
||||
STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */
|
||||
STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */
|
||||
STLINK_CHIPID_STM32_WB55 = 0x495,
|
||||
STLINK_CHIPID_STM32_WLE = 0x497
|
||||
};
|
||||
|
||||
#define CHIP_F_HAS_DUAL_BANK (1 << 0)
|
||||
#define CHIP_F_HAS_SWO_TRACING (1 << 1)
|
||||
|
||||
/** Chipid parameters */
|
||||
/** Chipid parametres */
|
||||
struct stlink_chipid_params {
|
||||
char *dev_type;
|
||||
char *ref_manual_id;
|
||||
uint32_t chip_id;
|
||||
char *description;
|
||||
enum stlink_flash_type flash_type;
|
||||
enum stm32_flash_type flash_type;
|
||||
uint32_t flash_size_reg;
|
||||
uint32_t flash_pagesize;
|
||||
uint32_t sram_size;
|
||||
|
|
@ -93,12 +21,7 @@ struct stlink_chipid_params {
|
|||
struct stlink_chipid_params * next;
|
||||
};
|
||||
|
||||
|
||||
struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid);
|
||||
void init_chipids(char *dir_to_scan);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // STLINK_CHIPID_H_
|
||||
|
|
|
|||
|
|
@ -2,21 +2,21 @@
|
|||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <stm32.h>
|
||||
#include <stlink.h>
|
||||
#include <helper.h>
|
||||
#include "flash_loader.h"
|
||||
|
||||
#define FLASH_REGS_BANK2_OFS 0x40
|
||||
#define FLASH_BANK2_START_ADDR 0x08080000
|
||||
#define FLASH_REGS_BANK2_OFS 0x40
|
||||
#define FLASH_BANK2_START_ADDR 0x08080000
|
||||
|
||||
#define STM32F0_WDG_KR 0x40003000
|
||||
#define STM32H7_WDG_KR 0x58004800
|
||||
|
||||
#define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA
|
||||
|
||||
/* !!!
|
||||
* !!! DO NOT MODIFY FLASH LOADERS DIRECTLY!
|
||||
* !!!
|
||||
/*
|
||||
* !!! DO NOT MODIFY FLASH LOADERS DIRECTLY !!!
|
||||
*
|
||||
* Edit assembly files in the '/flashloaders' instead. The sizes of binary
|
||||
* flash loaders must be aligned by 4 (it's written by stlink_write_mem32)
|
||||
|
|
@ -154,8 +154,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) {
|
|||
size_t size = 0;
|
||||
uint32_t dfsr, cfsr, hfsr;
|
||||
|
||||
/* Interrupt masking.
|
||||
* According to DDI0419C, Table C1-7 firstly force halt */
|
||||
/* Interrupt masking according to DDI0419C, Table C1-7 firstly force halt */
|
||||
stlink_write_debug32(sl, STLINK_REG_DHCSR,
|
||||
STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN |
|
||||
STLINK_REG_DHCSR_C_HALT);
|
||||
|
|
@ -176,7 +175,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) {
|
|||
ILOG("Successfully loaded flash loader in sram\n");
|
||||
|
||||
// set address of IWDG key register for reset it
|
||||
if (sl->flash_type == STLINK_FLASH_TYPE_H7) {
|
||||
if (sl->flash_type == STM32_FLASH_TYPE_H7) {
|
||||
fl->iwdg_kr = STM32H7_WDG_KR;
|
||||
} else {
|
||||
fl->iwdg_kr = STM32F0_WDG_KR;
|
||||
|
|
@ -233,43 +232,43 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
|
|||
const uint8_t* loader_code;
|
||||
size_t loader_size;
|
||||
|
||||
if (sl->chip_id == STLINK_CHIPID_STM32_L1_MD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS_HD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L152_RE ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L011 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L0 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) {
|
||||
if (sl->chip_id == STM32_CHIPID_L1_MD ||
|
||||
sl->chip_id == STM32_CHIPID_L1_CAT2 ||
|
||||
sl->chip_id == STM32_CHIPID_L1_MD_PLUS ||
|
||||
sl->chip_id == STM32_CHIPID_L1_MD_PLUS_HD ||
|
||||
sl->chip_id == STM32_CHIPID_L152_RE ||
|
||||
sl->chip_id == STM32_CHIPID_L011 ||
|
||||
sl->chip_id == STM32_CHIPID_L0 ||
|
||||
sl->chip_id == STM32_CHIPID_L0_CAT5 ||
|
||||
sl->chip_id == STM32_CHIPID_L0_CAT2) {
|
||||
loader_code = loader_code_stm32lx;
|
||||
loader_size = sizeof(loader_code_stm32lx);
|
||||
} else if (sl->core_id == STM32VL_CORE_ID ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F1_MD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F1_HD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F1_LD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F1_XLD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F1_CONN ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F3 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F3xx_SMALL ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F303_HD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F37x ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F334) {
|
||||
} else if (sl->core_id == STM32_CORE_ID_M3_r1p1_SWD ||
|
||||
sl->chip_id == STM32_CHIPID_F1_MD ||
|
||||
sl->chip_id == STM32_CHIPID_F1_HD ||
|
||||
sl->chip_id == STM32_CHIPID_F1_LD ||
|
||||
sl->chip_id == STM32_CHIPID_F1_VL_MD_LD ||
|
||||
sl->chip_id == STM32_CHIPID_F1_VL_HD ||
|
||||
sl->chip_id == STM32_CHIPID_F1_XLD ||
|
||||
sl->chip_id == STM32_CHIPID_F1_CONN ||
|
||||
sl->chip_id == STM32_CHIPID_F3 ||
|
||||
sl->chip_id == STM32_CHIPID_F3xx_SMALL ||
|
||||
sl->chip_id == STM32_CHIPID_F303_HD ||
|
||||
sl->chip_id == STM32_CHIPID_F37x ||
|
||||
sl->chip_id == STM32_CHIPID_F334) {
|
||||
loader_code = loader_code_stm32vl;
|
||||
loader_size = sizeof(loader_code_stm32vl);
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_F2 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F4 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F4_DE ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F4_LP ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F4_HD ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F4_DSI ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F410 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F411xx ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F412 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F413 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F446) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_F2 ||
|
||||
sl->chip_id == STM32_CHIPID_F4 ||
|
||||
sl->chip_id == STM32_CHIPID_F4_DE ||
|
||||
sl->chip_id == STM32_CHIPID_F4_LP ||
|
||||
sl->chip_id == STM32_CHIPID_F4_HD ||
|
||||
sl->chip_id == STM32_CHIPID_F4_DSI ||
|
||||
sl->chip_id == STM32_CHIPID_F410 ||
|
||||
sl->chip_id == STM32_CHIPID_F411xx ||
|
||||
sl->chip_id == STM32_CHIPID_F412 ||
|
||||
sl->chip_id == STM32_CHIPID_F413 ||
|
||||
sl->chip_id == STM32_CHIPID_F446) {
|
||||
int retval;
|
||||
retval = loader_v_dependent_assignment(sl,
|
||||
&loader_code, &loader_size,
|
||||
|
|
@ -277,10 +276,10 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
|
|||
loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv));
|
||||
|
||||
if (retval == -1) { return(retval); }
|
||||
} else if (sl->core_id == STM32F7_CORE_ID ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F7 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F76xxx ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F72xxx) {
|
||||
} else if (sl->core_id == STM32_CORE_ID_M7F_SWD ||
|
||||
sl->chip_id == STM32_CHIPID_F7 ||
|
||||
sl->chip_id == STM32_CHIPID_F76xxx ||
|
||||
sl->chip_id == STM32_CHIPID_F72xxx) {
|
||||
int retval;
|
||||
retval = loader_v_dependent_assignment(sl,
|
||||
&loader_code, &loader_size,
|
||||
|
|
@ -288,19 +287,19 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t*
|
|||
loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv));
|
||||
|
||||
if (retval == -1) { return(retval); }
|
||||
} else if (sl->chip_id == STLINK_CHIPID_STM32_F0 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F04 ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F0_CAN ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F0xx_SMALL ||
|
||||
sl->chip_id == STLINK_CHIPID_STM32_F09x) {
|
||||
} else if (sl->chip_id == STM32_CHIPID_F0 ||
|
||||
sl->chip_id == STM32_CHIPID_F04 ||
|
||||
sl->chip_id == STM32_CHIPID_F0_CAN ||
|
||||
sl->chip_id == STM32_CHIPID_F0xx_SMALL ||
|
||||
sl->chip_id == STM32_CHIPID_F09x) {
|
||||
loader_code = loader_code_stm32f0;
|
||||
loader_size = sizeof(loader_code_stm32f0);
|
||||
} else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) ||
|
||||
(sl->chip_id == STLINK_CHIPID_STM32_L41x_L42x) ||
|
||||
(sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) ||
|
||||
(sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) ||
|
||||
(sl->chip_id == STLINK_CHIPID_STM32_L4Rx) ||
|
||||
(sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x)) {
|
||||
} else if ((sl->chip_id == STM32_CHIPID_L4) ||
|
||||
(sl->chip_id == STM32_CHIPID_L41x_L42x) ||
|
||||
(sl->chip_id == STM32_CHIPID_L43x_L44x) ||
|
||||
(sl->chip_id == STM32_CHIPID_L45x_L46x) ||
|
||||
(sl->chip_id == STM32_CHIPID_L4Rx) ||
|
||||
(sl->chip_id == STM32_CHIPID_L496x_L4A6x)) {
|
||||
loader_code = loader_code_stm32l4;
|
||||
loader_size = sizeof(loader_code_stm32l4);
|
||||
} else {
|
||||
|
|
@ -333,7 +332,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe
|
|||
return(-1);
|
||||
}
|
||||
|
||||
if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) {
|
||||
if ((sl->flash_type == STM32_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) {
|
||||
flash_base = FLASH_REGS_BANK2_OFS;
|
||||
}
|
||||
|
||||
|
|
@ -353,7 +352,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe
|
|||
/* Run loader */
|
||||
stlink_run(sl, RUN_FLASH_LOADER);
|
||||
|
||||
/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs.
|
||||
/*
|
||||
* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs.
|
||||
* But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick"
|
||||
* (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when
|
||||
* "something goes wrong" that requires the error message "flash loader run error" would wait
|
||||
|
|
@ -382,7 +382,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe
|
|||
// check written byte count
|
||||
stlink_read_reg(sl, 2, &rr);
|
||||
|
||||
/* The chunk size for loading is not rounded. The flash loader
|
||||
/*
|
||||
* The chunk size for loading is not rounded. The flash loader
|
||||
* subtracts the size of the written block (1-8 bytes) from
|
||||
* the remaining size each time. A negative value may mean that
|
||||
* several bytes garbage has been written due to the unaligned
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
* This should contain all the common top level stlink interfaces,
|
||||
* regardless of how the backend does the work....
|
||||
*/
|
||||
|
||||
#ifndef STLINK_FLASH_LOADER_H_
|
||||
#define STLINK_FLASH_LOADER_H_
|
||||
|
||||
|
|
@ -12,16 +13,8 @@
|
|||
|
||||
#include <stlink.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl);
|
||||
int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
|
||||
int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // STLINK_FLASH_LOADER_H_
|
||||
|
|
|
|||
|
|
@ -4,21 +4,20 @@
|
|||
#include <libusb.h>
|
||||
|
||||
/*
|
||||
|
||||
libusb ver | LIBUSB_API_VERSION
|
||||
-----------+--------------------
|
||||
v1.0.13 | 0x01000100
|
||||
v1.0.14 | 0x010000FF
|
||||
v1.0.15 | 0x01000101
|
||||
v1.0.16 | 0x01000102
|
||||
v1.0.17 | 0x01000102
|
||||
v1.0.18 | 0x01000102
|
||||
v1.0.19 | 0x01000103
|
||||
v1.0.20 | 0x01000104
|
||||
v1.0.21 | 0x01000105
|
||||
v1.0.22 | 0x01000106
|
||||
v1.0.23 | 0x01000107
|
||||
|
||||
* libusb ver | LIBUSB_API_VERSION
|
||||
* -----------+--------------------
|
||||
* v1.0.13 | 0x01000100
|
||||
* v1.0.14 | 0x010000FF
|
||||
* v1.0.15 | 0x01000101
|
||||
* v1.0.16 | 0x01000102
|
||||
* v1.0.17 | 0x01000102
|
||||
* v1.0.18 | 0x01000102
|
||||
* v1.0.19 | 0x01000103
|
||||
* v1.0.20 | 0x01000104
|
||||
* v1.0.21 | 0x01000105
|
||||
* v1.0.22 | 0x01000106
|
||||
* v1.0.23 | 0x01000107
|
||||
* v1.0.24 | 0x01000108
|
||||
*/
|
||||
|
||||
#if defined (__FreeBSD__)
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
* Slow, yet another wheel reinvented, but enough to make the rest of our code
|
||||
* pretty enough.
|
||||
*/
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include <stdio.h>
|
||||
|
|
|
|||
|
|
@ -74,7 +74,6 @@
|
|||
* part to an existing options line for usb-storage).
|
||||
*/
|
||||
|
||||
|
||||
#define __USE_GNU
|
||||
#include <assert.h>
|
||||
#include <stdio.h>
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Ładowanie…
Reference in New Issue