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Minor fixes & additions 

- [doc] Update on OS version support
- Minor fixes for G0-series from #1293
- [doc] Added core-IDs for WB/WL-series
- [doc] Correction for G0/L0-series core-IDs
- Set option_size to 128 B for G0-series (#1194)
pull/1300/head
nightwalker-87 2023-03-18 21:53:27 +01:00
rodzic 2ff79959f4
commit 186e38a0fa
10 zmienionych plików z 83 dodań i 85 usunięć
Pokaż statystyki Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files

4
config/chips/F401xD_xE.chip
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@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB
sram_size 0x18000 // 96 KB
bootrom_base 0x1fff0000
bootrom_size 0x7800 // 30 KB
option_base 0x40023C14
option_size 0x4
option_base 0x40023C14 // STM32_F4_OPTION_BYTES_BASE
option_size 0x4 // 4 B
flags swo

2
config/chips/F446.chip
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@ -10,5 +10,5 @@ sram_size 0x20000 // 128 KB
bootrom_base 0x1fff0000
bootrom_size 0x7800 // 30 KB
option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE
option_size 0x4 // 4 B
option_size 0x10 // 16 B
flags swo

2
config/chips/G03x_G04x.chip
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@ -10,5 +10,5 @@ sram_size 0x2000 // 8 KB
bootrom_base 0x1fff0000
bootrom_size 0x2000 // 8 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_size 0x4 // 4 B
option_size 0x80 // 128 B
flags none

6
config/chips/G05x_G06x.chip
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@ -1,14 +1,14 @@
# Chip-ID file for STM32G05x / STM32G06x device
#
dev_type STM32G05x_G06x
ref_manual_id 0444
ref_manual_id 0444 // also RM454
chip_id 0x456 // STM32_CHIPID_G0_CAT4
flash_type G0
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x9000 // 36 KB
sram_size 0x4800 // 18 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_size 0x4 // 4 B
option_size 0x80 // 128 B
flags none

4
config/chips/G07x_G08x.chip
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@ -1,7 +1,7 @@
# Chip-ID file for STM32G07x / STM32G08x device
#
dev_type STM32G07x_G08x
ref_manual_id 0444
ref_manual_id 0444 // also RM454
chip_id 0x460 // STM32_CHIPID_G0_CAT2
flash_type G0
flash_size_reg 0x1fff75e0
@ -10,5 +10,5 @@ sram_size 0x9000 // 36 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_size 0x4 // 4 B
option_size 0x80 // 128 B
flags none

6
config/chips/G0Bx_G0Cx.chip
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@ -1,14 +1,14 @@
# Chip-ID file for STM32G0Bx / STM32G0Cx device
#
dev_type STM32G0Bx_G0Cx
ref_manual_id 0444
ref_manual_id 0444 // also RM454
chip_id 0x467 // STM32_CHIPID_G0_CAT3
flash_type G0
flash_size_reg 0x1fff75e0
flash_pagesize 0x800 // 2 KB
sram_size 0x9000 // 36 KB
sram_size 0x24000 // 144 KB
bootrom_base 0x1fff0000
bootrom_size 0x7000 // 28 KB
option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE
option_size 0x4 // 4 B
option_size 0x80 // 128 B
flags dualbank

60
doc/version_support.md
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@ -59,43 +59,41 @@ Other Linux-/Unix-based Operating Systems:
| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | |
| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | |
| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | |
| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | |
| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | |
| Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | |
## Unsupported Operating Systems (as of Release v1.7.1)
Systems with highlighted versions remain compatible with this toolset.
| Operating System | libusb | cmake | End of<br />OS-Support |
| ------------------------- | ------------------------------ | ---------- | ---------------------- |
| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 |
| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 |
| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 |
| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 |
| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 |
| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 |
| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 |
| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 |
| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 |
| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 |
| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 |
| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 |
| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 |
| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 |
| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 |
| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 |
| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 |
| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 |
| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 |
| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 |
| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 |
| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** |
| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 |
| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 |
| Slackware 14.2 | 1.0.20 | 3.5.2 | |
| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | |
| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 |
| Operating System | libusb | cmake | End of<br />OS-Support |
| ---------------------------------------- | ------------------------------ | ---------- | ---------------------- |
| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 |
| CentOS / Rocky Linux / AlmaLinux 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 |
| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 |
| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 |
| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 |
| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 |
| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 |
| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 |
| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 |
| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 |
| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 |
| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 |
| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 |
| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 |
| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 |
| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 |
| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 |
| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 |
| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 |
| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 |
| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 |
| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** |
| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 |
| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 |
| Slackware 14.2 | 1.0.20 | 3.5.2 | |
| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | |
| CentOS / Rocky Linux / AlmaLinux 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 |
_All other operating systems which are not listed are unsupported._

72
inc/stm32.h
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@ -9,37 +9,41 @@
/* STM32 Cortex-M core ids (CPUTAPID) */
enum stm32_core_id {
STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP
// (RM0444 Section 40.5.3) G0 SW-DP
STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP
STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP
STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG
STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP
// (RM0038 Section 30.8.3) L1 SW-DP
STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG
// (RM0038 Section 30.6.2) L1 JTAG
STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP
// (RM0351 Section 48.8.3) L4 SW-DP
// (RM0432 Section 57.8.3) L4+ SW-DP
STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG
// (RM0351 Section 48.6.3) L4 JTAG
// (RM0432 Section 57.6.3) L4+ JTAG
STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP
// (RM0090 Section 47.8.3) G4 SW-DP
STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG
// (RM0090 Section 47.6.3) G4 JTAG
STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP
STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG
STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP
// (RM0433 Section 60.4.1) H7 SW-DP
STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG
// (RM0433 Section 60.4.1) H7 SW-DP
STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP
// (RM0456 Section 65.3.3) U5 SW-DP
STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP
// (RM0456 Section 65.3.3) U5 JTAG-DP
STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG
// (RM0456 Section 56.3.1) U5 JTAG
STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP
STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0444 Section 40.5.3) G0 SW-DP
// (RM0377 Section 27.5.3) L0 SW-DP
STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP
STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG
STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP
// (RM0038 Section 30.8.3) L1 SW-DP
STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG
// (RM0038 Section 30.6.2) L1 JTAG
STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP
// (RM0351 Section 48.8.3) L4 SW-DP
// (RM0432 Section 57.8.3) L4+ SW-DP
STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG
// (RM0351 Section 48.6.3) L4 JTAG
// (RM0432 Section 57.6.3) L4+ JTAG
STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP
// (RM0090 Section 47.8.3) G4 SW-DP
STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG
// (RM0090 Section 47.6.3) G4 JTAG
STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP
// (RM0473 Section 33.4.4) WB SW-DP
// (RM0453 Section 38.4.1) WL SW-DP
STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG
STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP
// (RM0433 Section 60.4.1) H7 SW-DP
STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG
// (RM0433 Section 60.4.1) H7 JTAG
// (RM0473 Section 33.4.1) WB JTAG
// (RM0453 Section 38.3.8) WL JTAG
STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP
// (RM0456 Section 65.3.3) U5 SW-DP
STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP
// (RM0456 Section 65.3.3) U5 JTAG-DP
STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG
// (RM0456 Section 56.3.1) U5 JTAG
};
/* STM32 flash types */
@ -108,13 +112,13 @@ enum stm32_chipids {
STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */
STM32_CHIPID_L011 = 0x457,
STM32_CHIPID_F410 = 0x458,
STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */
STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */
STM32_CHIPID_L496x_L4A6x = 0x461,
STM32_CHIPID_L45x_L46x = 0x462,
STM32_CHIPID_F413 = 0x463,
STM32_CHIPID_L41x_L42x = 0x464,
STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */
STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */
STM32_CHIPID_G0_CAT1 = 0x466, /* G03x/G04x */
STM32_CHIPID_G0_CAT3 = 0x467, /* G0Bx/G0Cx */
STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */
STM32_CHIPID_G4_CAT3 = 0x469,
STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */

3
src/stlink-lib/common.c
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@ -279,8 +279,7 @@ int stlink_load_device_params(stlink_t *sl) {
// medium and low devices have the same chipid. ram size depends on flash
// size. STM32F100xx datasheet Doc ID 16455 Table 2
if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD &&
sl->flash_size < 64 * 1024) {
if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) {
sl->sram_size = 0x1000;
}

9
src/stlink-lib/option_bytes.c
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@ -242,8 +242,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t
int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) {
int err = -1;
for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) {
err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t),
option_byte);
err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte);
if (err == -1) {
return err;
} else {
@ -272,8 +271,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t
// Clear errors
clear_flash_error(sl);
ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base),
addr);
ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), addr);
write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base));
ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr);
@ -306,8 +304,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t
ret = check_flash_error(sl);
if (!ret)
ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base,
addr);
ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, addr);
/* option bytes are reloaded at reset only, no obl. */