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Restructuring of STM32 definitions 

- Moved enum stlink_stm32_chipids to stm32.h
- Moved additional MCU defines to stlink.h
- Minor formatting improvements
- Commented comparison for old/new chipid db
pull/1216/head
nightwalker-87 2022-01-09 16:39:54 +01:00
rodzic f55dd8d08f
commit 14498bb3c0
4 zmienionych plików z 137 dodań i 127 usunięć
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4
inc/stlink.h
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@ -83,6 +83,10 @@ enum target_state {
#define STLINK_F_HAS_DPBANKSEL (1 << 8)
#define STLINK_F_HAS_RW8_512BYTES (1 << 9)
/* Additional MCU features */
#define CHIP_F_HAS_DUAL_BANK (1 << 0)
#define CHIP_F_HAS_SWO_TRACING (1 << 1)
/* Error code */
#define STLINK_DEBUG_ERR_OK 0x80
#define STLINK_DEBUG_ERR_FAULT 0x81

118
inc/stm32.h
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@ -7,37 +7,111 @@
#ifndef STM32_H
#define STM32_H
/* Cortex core ids */
#define STM32VL_CORE_ID 0x1ba01477
#define STM32F7_CORE_ID 0x5ba02477
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code
#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065)
/* Cortex-M core ids */
#define STM32VL_CORE_ID 0x1ba01477
#define STM32F7_CORE_ID 0x5ba02477
#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code
#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 p.3065)
/* Constant STM32 memory map figures */
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000)
/* Constant STM32 memory address */
#define STM32_SRAM_BASE ((uint32_t)0x20000000)
#define STM32_FLASH_BASE ((uint32_t)0x08000000)
#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000)
#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000)
#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000)
#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14)
#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C)
/* Constant STM32 option bytes base memory address */
#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14)
#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000)
#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c)
#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000)
#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1ff80000)
#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1ff80000)
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800)
#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1fff0000)
#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000)
#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800)
#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1fff7800)
#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800)
#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1fffc000)
#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800)
/*
* Chip IDs
* See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual
*/
// stm32 chipids, only lower 12 bits...
enum stlink_stm32_chipids {
STLINK_CHIPID_UNKNOWN = 0x000,
STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */
STLINK_CHIPID_STM32_F2 = 0x411,
STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */
STLINK_CHIPID_STM32_F4 = 0x413,
STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */
STLINK_CHIPID_STM32_L4 = 0x415,
STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */
STLINK_CHIPID_STM32_L0 = 0x417,
STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */
STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */
STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */
STLINK_CHIPID_STM32_F446 = 0x421,
STLINK_CHIPID_STM32_F3 = 0x422,
STLINK_CHIPID_STM32_F4_LP = 0x423,
STLINK_CHIPID_STM32_L0_CAT2 = 0x425,
STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */
STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */
STLINK_CHIPID_STM32_L1_CAT2 = 0x429,
STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */
STLINK_CHIPID_STM32_F411xx = 0x431,
STLINK_CHIPID_STM32_F37x = 0x432,
STLINK_CHIPID_STM32_F4_DE = 0x433,
STLINK_CHIPID_STM32_F4_DSI = 0x434,
STLINK_CHIPID_STM32_L43x_L44x = 0x435,
STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */
STLINK_CHIPID_STM32_L152_RE = 0x437,
STLINK_CHIPID_STM32_F334 = 0x438,
STLINK_CHIPID_STM32_F3xx_SMALL = 0x439,
STLINK_CHIPID_STM32_F0 = 0x440,
STLINK_CHIPID_STM32_F412 = 0x441,
STLINK_CHIPID_STM32_F09x = 0x442,
STLINK_CHIPID_STM32_F0xx_SMALL = 0x444,
STLINK_CHIPID_STM32_F04 = 0x445,
STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */
STLINK_CHIPID_STM32_L0_CAT5 = 0x447,
STLINK_CHIPID_STM32_F0_CAN = 0x448,
STLINK_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */
STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */
STLINK_CHIPID_STM32_F76xxx = 0x451,
STLINK_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */
STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */
STLINK_CHIPID_STM32_L011 = 0x457,
STLINK_CHIPID_STM32_F410 = 0x458,
STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */
STLINK_CHIPID_STM32_L496x_L4A6x = 0x461,
STLINK_CHIPID_STM32_L45x_L46x = 0x462,
STLINK_CHIPID_STM32_F413 = 0x463,
STLINK_CHIPID_STM32_L41x_L42x = 0x464,
STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */
STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */
STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */
STLINK_CHIPID_STM32_G4_CAT3 = 0x469,
STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */
STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */
STLINK_CHIPID_STM32_G4_CAT4 = 0x479,
STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */
STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */
STLINK_CHIPID_STM32_WB55 = 0x495,
STLINK_CHIPID_STM32_WLE = 0x497,
};
#endif // STM32_H

65
src/stlink-lib/chipid.c
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@ -39,45 +39,46 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) {
fprintf(fp, "flags %d\n\n", dev->flags);
}
static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2)
{
return p1->chip_id == p2->chip_id &&
p1->dev_type && p2->dev_type &&
strcmp(p1->dev_type, p2->dev_type) == 0 &&
p1->flash_type == p2->flash_type &&
p1->flash_size_reg == p2->flash_size_reg &&
p1->flash_pagesize == p2->flash_pagesize &&
p1->sram_size == p2->sram_size &&
p1->bootrom_base == p2->bootrom_base &&
p1->bootrom_size == p2->bootrom_size &&
p1->option_base == p2->option_base &&
p1->option_size == p2->option_size &&
p1->flags == p2->flags;
}
// static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2)
// {
// return p1->chip_id == p2->chip_id &&
// p1->dev_type && p2->dev_type &&
// strcmp(p1->dev_type, p2->dev_type) == 0 &&
// p1->flash_type == p2->flash_type &&
// p1->flash_size_reg == p2->flash_size_reg &&
// p1->flash_pagesize == p2->flash_pagesize &&
// p1->sram_size == p2->sram_size &&
// p1->bootrom_base == p2->bootrom_base &&
// p1->bootrom_size == p2->bootrom_size &&
// p1->option_base == p2->option_base &&
// p1->option_size == p2->option_size &&
// p1->flags == p2->flags;
// }
struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) {
struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) {
struct stlink_chipid_params *params = NULL;
struct stlink_chipid_params *p2;
// struct stlink_chipid_params *p2;
for (params = devicelist; params != NULL; params = params->next)
if (params->chip_id == chipid) {
if (params->chip_id == chip_id) {
fprintf(stderr, "\ndetected chip_id parametres\n\n");
dump_a_chip(stderr, params);
break;
}
p2 = stlink_chipid_get_params_old(chipid);
// p2 = stlink_chipid_get_params_old(chipid);
#if 1
if (params == NULL) {
params = p2;
} else if (!chipid_params_eq(params, p2)) {
// fprintf (stderr, "Error, chipid params not identical\n");
// return NULL;
fprintf(stderr, "---------- old ------------\n");
dump_a_chip(stderr, p2);
fprintf(stderr, "---------- new ------------\n");
dump_a_chip(stderr, params);
}
#endif
// #if 1
// if (params == NULL) {
// params = p2;
// } else if (!chipid_params_eq(params, p2)) {
// // fprintf (stderr, "Error, chipid params not identical\n");
// // return NULL;
// fprintf(stderr, "---------- old ------------\n");
// dump_a_chip(stderr, p2);
// fprintf(stderr, "---------- new ------------\n");
// dump_a_chip(stderr, params);
// }
// #endif
return(params);
}

77
src/stlink-lib/chipid.h
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@ -1,83 +1,14 @@
#ifndef STLINK_CHIPID_H_
#define STLINK_CHIPID_H_
#include <stm32.h>
#include <stlink.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* Chip IDs are explained in the appropriate programming manual for the
* DBGMCU_IDCODE register (0xE0042000)
* stm32 chipids, only lower 12 bits...
*/
enum stlink_stm32_chipids {
STLINK_CHIPID_UNKNOWN = 0x000,
STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */
STLINK_CHIPID_STM32_F2 = 0x411,
STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */
STLINK_CHIPID_STM32_F4 = 0x413,
STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */
STLINK_CHIPID_STM32_L4 = 0x415,
STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */
STLINK_CHIPID_STM32_L0 = 0x417,
STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */
STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */
STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */
STLINK_CHIPID_STM32_F446 = 0x421,
STLINK_CHIPID_STM32_F3 = 0x422,
STLINK_CHIPID_STM32_F4_LP = 0x423,
STLINK_CHIPID_STM32_L0_CAT2 = 0x425,
STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */
STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */
STLINK_CHIPID_STM32_L1_CAT2 = 0x429,
STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */
STLINK_CHIPID_STM32_F411xx = 0x431,
STLINK_CHIPID_STM32_F37x = 0x432,
STLINK_CHIPID_STM32_F4_DE = 0x433,
STLINK_CHIPID_STM32_F4_DSI = 0x434,
STLINK_CHIPID_STM32_L43x_L44x = 0x435,
STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */
STLINK_CHIPID_STM32_L152_RE = 0x437,
STLINK_CHIPID_STM32_F334 = 0x438,
STLINK_CHIPID_STM32_F3xx_SMALL = 0x439,
STLINK_CHIPID_STM32_F0 = 0x440,
STLINK_CHIPID_STM32_F412 = 0x441,
STLINK_CHIPID_STM32_F09x = 0x442,
STLINK_CHIPID_STM32_F0xx_SMALL = 0x444,
STLINK_CHIPID_STM32_F04 = 0x445,
STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */
STLINK_CHIPID_STM32_L0_CAT5 = 0x447,
STLINK_CHIPID_STM32_F0_CAN = 0x448,
STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the Nucleo F746ZG board */
STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */
STLINK_CHIPID_STM32_F76xxx = 0x451,
STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the Nucleo F722ZE board */
STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */
STLINK_CHIPID_STM32_L011 = 0x457,
STLINK_CHIPID_STM32_F410 = 0x458,
STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */
STLINK_CHIPID_STM32_L496x_L4A6x = 0x461,
STLINK_CHIPID_STM32_L45x_L46x = 0x462,
STLINK_CHIPID_STM32_F413 = 0x463,
STLINK_CHIPID_STM32_L41x_L42x = 0x464,
STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */
STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */
STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */
STLINK_CHIPID_STM32_G4_CAT3 = 0x469,
STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p. 2247, found on the STM32L4R9I-DISCO board */
STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */
STLINK_CHIPID_STM32_G4_CAT4 = 0x479,
STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */
STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */
STLINK_CHIPID_STM32_WB55 = 0x495,
STLINK_CHIPID_STM32_WLE = 0x497
};
#define CHIP_F_HAS_DUAL_BANK (1 << 0)
#define CHIP_F_HAS_SWO_TRACING (1 << 1)
/** Chipid parameters */
/** Chipid parametres */
struct stlink_chipid_params {
char *dev_type;
char *ref_manual_id;