From 4da1addbbea4dd65305d78b14670fd6811c14876 Mon Sep 17 00:00:00 2001
From: Piotr <Piotr@192.168.0.17>
Date: Sat, 4 Apr 2020 17:35:22 +0200
Subject: [PATCH] new modifications

---
 rf96/src/main.c | 34 ++++++++++++++-------
 rf96/src/rf96.c |  8 ++++-
 rf96/src/rf96.h | 81 ++++++-------------------------------------------
 3 files changed, 40 insertions(+), 83 deletions(-)

diff --git a/rf96/src/main.c b/rf96/src/main.c
index 45510b6..b911806 100644
--- a/rf96/src/main.c
+++ b/rf96/src/main.c
@@ -27,6 +27,9 @@ void clockInit();
 **
 **===========================================================================
 */
+
+uint8_t rssi_u8 = 0;
+rf96_config conf;
 int main(void)
 {
 	clockInit();
@@ -40,13 +43,12 @@ SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PB;	//przypisanie szyny B do EXTI0
 	EXTI->IMR |= EXTI_IMR_MR0;
 	EXTI->FTSR |= EXTI_FTSR_TR0;
 /////////////////////////////////////for intterupt enf
-
+conf.freqency_u32 = 433000000UL;
+rf_set_params(&conf);
+//spiWrite(0x06,0x64);
+//spiWrite(0x07,0xC0);
+//spiWrite(0x08,0x11);
 uint32_t freq_u32 =0;
-uint8_t rssi_u8 = 0;
-spiWrite(0x06,0x64);
-spiWrite(0x07,0xC0);
-spiWrite(0x08,0x11);
-
 freq_u32 = 	(spiRead(0x08) |
 			(spiRead(0x07) << 8) |
 			(spiRead(0x06) << 16) ) * (float)61.035;
@@ -62,15 +64,22 @@ spiWrite(RegPreambleLsb, 40);
 spiWrite(RegPaRamp, (0x9 | (0b01 << 5)));
 spiWrite(RegDioMapping1, (0b01 << 6));	//enabling preamble detect pn DIO0
 spiWrite(RegDioMapping2, 0b1);			//setting to preamble detect
-//spiWrite(RegFifoThresh, 0x80);
-//spiWrite(RegSyncConfig, (spiRead(RegSyncConfig) & 0b00111111));
-//while(!(spiRead(RegOpMode) & FSK_SBY_MODE)){};
+
+spiWrite(RegRxConfig, 0b00011110);	//setting rxtrigger to preable detect
+									//and enabling agc
+spiWrite(RegPacketConfig1,0b10000000);
+spiWrite(RegSyncConfig,0b00001000);
 spiWrite(RegOpMode, FSK_SBY_MODE);
 
-//spiWrite(LR_RegFifoAddrPtr, spiRead(LR_RegFifoTxBaseAddr) );	//0x80
+
+spiWrite(RegSeqConfig1,0b10000110);
+spiWrite(RegSeqConfig2,0b01010010);
 
 
-spiWrite(RegOpMode,FSK_RX_MODE);
+int iii;//spiWrite(LR_RegFifoAddrPtr, spiRead(LR_RegFifoTxBaseAddr) );	//0x80
+
+
+//spiWrite(RegOpMode,FSK_RX_MODE);
 //SysTick_Config(8000000);
 NVIC_EnableIRQ(EXTI0_IRQn);
 	while (1)
@@ -183,6 +192,9 @@ __attribute__ ((interrupt)) void EXTI0_IRQHandler(void)
 {
 	if(EXTI->PR & EXTI_PR_PR0){
 		EXTI->PR = EXTI_PR_PR0;
+		uint8_t test[16];
+		for(int j=0; j <16; j++)
+					test[j]=spiRead(RegFIFO);
 		printMsg("RSSI: %i, IRQ1 %x, IRQ2 %x\n",(-1*spiRead(0x11)/2),spiRead(RegIrqFlags1),spiRead(RegIrqFlags2));
 	}
 }
diff --git a/rf96/src/rf96.c b/rf96/src/rf96.c
index d5d00f3..d4f20e1 100644
--- a/rf96/src/rf96.c
+++ b/rf96/src/rf96.c
@@ -14,7 +14,13 @@
 
 
 
-
+void rf_set_params(rf96_config * _conf)
+{
+	uint32_t val = (_conf->freqency_u32) / F_STEP;
+	spiWrite(RegFreqLsb, val & 0xFF);
+	spiWrite(RegFreqMid, (val >> 8) & 0xFF);
+	spiWrite(RegFreqMsb, (val >> 16) & 0xFF);
+}
 
 
 
diff --git a/rf96/src/rf96.h b/rf96/src/rf96.h
index 5e34bdf..2af7205 100644
--- a/rf96/src/rf96.h
+++ b/rf96/src/rf96.h
@@ -12,7 +12,7 @@
 #define SX1278_MAX_PACKET	256
 #define SX1278_DEFAULT_TIMEOUT		3000
 
-
+#define F_STEP 61.035F
 /********************LoRa mode***************************/
 #define LR_RegFifo                                  0x00
 // Common settings
@@ -70,10 +70,6 @@
 /********************FSK/ook mode***************************/
 
 
-#define FSK_SBY_MODE 	0b00001001
-#define FSK_TX_MODE 	0b00001011
-#define FSK_RX_MODE 	0b00001101
-#define FSK_SLEEP_MODE 	0b00001000
 
 
 //registers
@@ -145,75 +141,18 @@
 #define  RegPaDac				0x4d
 #define  RegBitRateFrac			0x5d
 
+//values for OpMode register
+#define FSK_SBY_MODE 	0b00001001
+#define FSK_TX_MODE 	0b00001011
+#define FSK_RX_MODE 	0b00001101
+#define FSK_SLEEP_MODE 	0b00001000
 
+typedef struct{
+	uint32_t freqency_u32;
 
-//
-//#define FSK_SLEEP_MODE 		 0x00
-//#define FSK_STANDBY_MODE 	 0x01
-//#define FSK_TX_MODE 		 0x03
-//#define FSK_RX_MODE 		 0x05
-//
-//
+}rf96_config;
 
-
-
-
-
-
-
-
-
-/**********************************************************
- **Parameter table define
- **********************************************************/
-#define SX1278_433MHZ			0
-
-static const uint8_t SX1278_Frequency[1][3] = { { 0x6C, 0x80, 0x00 }, //434MHz
-		};
-
-#define SX1278_POWER_20DBM		0
-#define SX1278_POWER_17DBM		1
-#define SX1278_POWER_14DBM		2
-#define SX1278_POWER_11DBM		3
-
-static const uint8_t SX1278_Power[4] = { 0xFF, //20dbm
-		0xFC, //17dbm
-		0xF9, //14dbm
-		0xF6, //11dbm
-		};
-
-#define SX1278_LORA_SF_6		0
-#define SX1278_LORA_SF_7		1
-#define SX1278_LORA_SF_8		2
-#define SX1278_LORA_SF_9		3
-#define SX1278_LORA_SF_10		4
-#define SX1278_LORA_SF_11		5
-#define SX1278_LORA_SF_12		6
-
-static const uint8_t SX1278_SpreadFactor[7] = { 6, 7, 8, 9, 10, 11, 12 };
-
-#define	SX1278_LORA_BW_7_8KHZ		0
-#define	SX1278_LORA_BW_10_4KHZ		1
-#define	SX1278_LORA_BW_15_6KHZ		2
-#define	SX1278_LORA_BW_20_8KHZ		3
-#define	SX1278_LORA_BW_31_2KHZ		4
-#define	SX1278_LORA_BW_41_7KHZ		5
-#define	SX1278_LORA_BW_62_5KHZ		6
-#define	SX1278_LORA_BW_125KHZ		7
-#define	SX1278_LORA_BW_250KHZ		8
-#define	SX1278_LORA_BW_500KHZ		9
-
-static const uint8_t SX1278_LoRaBandwidth[10] = { 0, //   7.8KHz,
-		1, //  10.4KHz,
-		2, //  15.6KHz,
-		3, //  20.8KHz,
-		4, //  31.2KHz,
-		5, //  41.7KHz,
-		6, //  62.5KHz,
-		7, // 125.0KHz,
-		8, // 250.0KHz,
-		9  // 500.0KHz
-		};
+void rf_set_params(rf96_config * _conf);
 
 
 #endif /* RF96_H_ */