kopia lustrzana https://github.com/pimoroni/pimoroni-pico
223 wiersze
6.4 KiB
Plaintext
223 wiersze
6.4 KiB
Plaintext
; Pins:
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; - CSn is side-set 0
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; - SCK is side-set 1
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; - D0 is IN/OUT/SET pin 0
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;
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; DMA is 32 bit. Stream takes form:
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; 32 bits For read: length of read in nibbles, minus 4
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; For write: length of write in nibbles, minus 1
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; Original data length in bits must be a multiple of 32
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; 8 bits AP6404 cmd (0xeb = read, 0x38 = write)
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; 24 bits address
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; 32 bits sram_offset_do_read or sram_offset_do_write
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; For write, data
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; Program for running at high frequencies (130MHz-290MHz RP2040 system clock)
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; Waits an extra half cycle on read as the data back from the PSRAM appears a fixed
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; amount of *time* after the CLK
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.program sram
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.side_set 2
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.wrap_target
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top:
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set x, 6 side 0b01
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out y, 32 side 0b01
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set pindirs, 0xf side 0b01
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; Write command, followed by data
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addr_lp:
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out pins, 4 side 0b00
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jmp x--, addr_lp side 0b10
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out pins, 4 side 0b00
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out pc, 32 side 0b10
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PUBLIC do_write:
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out pins, 4 side 0b00
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jmp y--, do_write side 0b10
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set pindirs, 0 side 0b00
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out null, 32 side 0b01
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jmp top side 0b01
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; Read command
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PUBLIC do_read:
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; Wait for 8.5 clocks (6 + 2.5 for latencies)
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set x, 7 side 0b00
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rwt_lp:
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set pindirs, 0 side 0b10
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jmp x-- rwt_lp side 0b00
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set x, 2 side 0b10
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rd_lp:
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in pins, 4 side 0b00
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jmp y--, rd_lp side 0b10
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; Read the remaining 3 nibbles, but no more clocks so we don't read beyond
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; the requested length from the SRAM.
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rd_rem:
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in pins, 4 side 0b01
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jmp x--, rd_rem side 0b01
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.wrap
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; Program for running at low frequencies (<130MHz RP2040 system clock)
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.program sram_slow
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.side_set 2
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.wrap_target
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top:
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set x, 6 side 0b01
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out y, 32 side 0b01
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set pindirs, 0xf side 0b01
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; Write command, followed by data
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addr_lp:
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out pins, 4 side 0b00
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jmp x--, addr_lp side 0b10
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out pins, 4 side 0b00
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out pc, 32 side 0b10
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PUBLIC do_write:
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out pins, 4 side 0b00
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jmp y--, do_write side 0b10
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set pindirs, 0 side 0b00
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out null, 32 side 0b01
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jmp top side 0b01
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; Read command
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PUBLIC do_read:
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set pindirs, 0 side 0b00
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; Wait for 8 clocks (6 + 2 for latencies)
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set x, 6 side 0b10
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rwt_lp:
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nop side 0b00
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jmp x-- rwt_lp side 0b10
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set x, 2 side 0b00
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rd_lp:
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in pins, 4 side 0b10
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jmp y--, rd_lp side 0b00
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; Read the remaining 3 nibbles, but no more clocks so we don't read beyond
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; the requested length from the SRAM.
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rd_rem:
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in pins, 4 side 0b01
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jmp x--, rd_rem side 0b01
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.wrap
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; Program for running at extreme frequencies (>290MHz RP2040 system clock)
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; Runs clock at 1/3rd RP2040 clock with 66% duty cycle. Out of spec but
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; then everything we are doing here is!
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.program sram_fast
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.side_set 2
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.wrap_target
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top:
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set x, 6 side 0b01
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out y, 32 side 0b01
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set pindirs, 0xf side 0b01
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; Write command, followed by data
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addr_lp:
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out pins, 4 side 0b00
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jmp x--, addr_lp [1] side 0b10
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out pins, 4 side 0b00
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out pc, 32 [1] side 0b10
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PUBLIC do_write:
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out pins, 4 side 0b00
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jmp y--, do_write [1] side 0b10
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set pindirs, 0 side 0b00
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out null, 32 side 0b01
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jmp top side 0b01
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; Read command
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PUBLIC do_read:
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set pindirs, 0 side 0b00
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; Wait for 8 clocks (6 + 2 for latencies)
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set x, 6 [1] side 0b10
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rwt_lp:
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nop side 0b00
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jmp x-- rwt_lp [1] side 0b10
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set x, 2 side 0b00
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rd_lp:
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nop side 0b10
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in pins, 4 side 0b10
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jmp y--, rd_lp side 0b00
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; Read the remaining 2 nibbles, but no more clocks so we don't read beyond
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; the requested length from the SRAM.
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rd_rem:
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in pins, 4 [1] side 0b01
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jmp x--, rd_rem side 0b01
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.wrap
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; Write only program that writes a short (<32 bit) command,
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; ignoring the rest of the 32 bit input word.
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; This is used to write the reset command and enter QPI mode.
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.program sram_reset
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.side_set 2
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.wrap_target
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out y, 32 side 0b01
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pull side 0b01
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wr_lp:
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out pins, 1 side 0b00
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jmp y--, wr_lp side 0b10
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out null, 32 [7] side 0b01 ; Ensure large enough gap between commands for reset time
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nop [7] side 0b01
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.wrap
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.program sram_reset_qpi
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.side_set 2
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.wrap_target
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out y, 32 side 0b01
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pull side 0b01
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set pindirs, 0xF side 0b01
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wr_lp:
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out pins, 4 side 0b00
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jmp y--, wr_lp side 0b10
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out null, 32 [7] side 0b01 ; Ensure large enough gap between commands for reset time
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set pindirs, 0 [7] side 0b01
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.wrap
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% c-sdk {
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void aps6404_reset_program_init(PIO pio, uint sm, uint offset, uint csn, uint mosi) {
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uint miso = mosi + 1;
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pio_gpio_init(pio, csn);
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pio_gpio_init(pio, csn + 1);
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pio_gpio_init(pio, mosi);
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pio_sm_set_consecutive_pindirs(pio, sm, csn, 2, true);
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pio_sm_set_consecutive_pindirs(pio, sm, mosi, 1, true);
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pio_sm_set_consecutive_pindirs(pio, sm, miso, 1, false);
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pio_sm_config c = sram_reset_program_get_default_config(offset);
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sm_config_set_in_pins(&c, miso);
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sm_config_set_in_shift(&c, false, true, 32);
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sm_config_set_out_pins(&c, mosi, 1);
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sm_config_set_out_shift(&c, false, true, 32);
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sm_config_set_sideset_pins(&c, csn);
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sm_config_set_clkdiv(&c, 4.f);
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pio_sm_init(pio, sm, offset, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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void aps6404_program_init(PIO pio, uint sm, uint offset, uint csn, uint mosi, bool slow, bool fast, bool reset) {
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pio_gpio_init(pio, csn);
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pio_gpio_init(pio, csn + 1);
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pio_gpio_init(pio, mosi);
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pio_gpio_init(pio, mosi + 1);
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pio_gpio_init(pio, mosi + 2);
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pio_gpio_init(pio, mosi + 3);
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pio_sm_set_consecutive_pindirs(pio, sm, csn, 2, true);
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pio_sm_set_consecutive_pindirs(pio, sm, mosi, 4, false);
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pio_sm_config c = slow ? sram_slow_program_get_default_config(offset) :
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fast ? sram_fast_program_get_default_config(offset) :
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reset ? sram_reset_qpi_program_get_default_config(offset) :
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sram_program_get_default_config(offset);
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sm_config_set_in_pins(&c, mosi);
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sm_config_set_in_shift(&c, false, true, 32);
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sm_config_set_out_pins(&c, mosi, 4);
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sm_config_set_out_shift(&c, false, true, 32);
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sm_config_set_set_pins(&c, mosi, 4);
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sm_config_set_sideset_pins(&c, csn);
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pio_sm_init(pio, sm, offset, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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