kopia lustrzana https://github.com/majbthrd/pico-debug
585 wiersze
23 KiB
C
585 wiersze
23 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : PSM
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// Version : 1
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// Bus type : apb
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// Description : None
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// =============================================================================
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#ifndef HARDWARE_REGS_PSM_DEFINED
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#define HARDWARE_REGS_PSM_DEFINED
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// =============================================================================
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// Register : PSM_FRCE_ON
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// Description : Force block out of reset (i.e. power it on)
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#define PSM_FRCE_ON_OFFSET 0x00000000
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#define PSM_FRCE_ON_BITS 0x0001ffff
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#define PSM_FRCE_ON_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_PROC1
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// Description : None
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#define PSM_FRCE_ON_PROC1_RESET 0x0
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#define PSM_FRCE_ON_PROC1_BITS 0x00010000
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#define PSM_FRCE_ON_PROC1_MSB 16
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#define PSM_FRCE_ON_PROC1_LSB 16
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#define PSM_FRCE_ON_PROC1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_PROC0
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// Description : None
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#define PSM_FRCE_ON_PROC0_RESET 0x0
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#define PSM_FRCE_ON_PROC0_BITS 0x00008000
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#define PSM_FRCE_ON_PROC0_MSB 15
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#define PSM_FRCE_ON_PROC0_LSB 15
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#define PSM_FRCE_ON_PROC0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_SIO
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// Description : None
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#define PSM_FRCE_ON_SIO_RESET 0x0
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#define PSM_FRCE_ON_SIO_BITS 0x00004000
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#define PSM_FRCE_ON_SIO_MSB 14
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#define PSM_FRCE_ON_SIO_LSB 14
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#define PSM_FRCE_ON_SIO_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
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// Description : None
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#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0
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#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000
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#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13
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#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13
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#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_XIP
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// Description : None
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#define PSM_FRCE_ON_XIP_RESET 0x0
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#define PSM_FRCE_ON_XIP_BITS 0x00001000
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#define PSM_FRCE_ON_XIP_MSB 12
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#define PSM_FRCE_ON_XIP_LSB 12
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#define PSM_FRCE_ON_XIP_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_SRAM5
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// Description : None
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#define PSM_FRCE_ON_SRAM5_RESET 0x0
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#define PSM_FRCE_ON_SRAM5_BITS 0x00000800
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#define PSM_FRCE_ON_SRAM5_MSB 11
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#define PSM_FRCE_ON_SRAM5_LSB 11
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#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_SRAM4
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// Description : None
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#define PSM_FRCE_ON_SRAM4_RESET 0x0
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#define PSM_FRCE_ON_SRAM4_BITS 0x00000400
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#define PSM_FRCE_ON_SRAM4_MSB 10
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#define PSM_FRCE_ON_SRAM4_LSB 10
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#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_SRAM3
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// Description : None
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#define PSM_FRCE_ON_SRAM3_RESET 0x0
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#define PSM_FRCE_ON_SRAM3_BITS 0x00000200
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#define PSM_FRCE_ON_SRAM3_MSB 9
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#define PSM_FRCE_ON_SRAM3_LSB 9
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#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_SRAM2
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// Description : None
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#define PSM_FRCE_ON_SRAM2_RESET 0x0
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#define PSM_FRCE_ON_SRAM2_BITS 0x00000100
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#define PSM_FRCE_ON_SRAM2_MSB 8
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#define PSM_FRCE_ON_SRAM2_LSB 8
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#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_SRAM1
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// Description : None
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#define PSM_FRCE_ON_SRAM1_RESET 0x0
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#define PSM_FRCE_ON_SRAM1_BITS 0x00000080
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#define PSM_FRCE_ON_SRAM1_MSB 7
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#define PSM_FRCE_ON_SRAM1_LSB 7
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#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_SRAM0
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// Description : None
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#define PSM_FRCE_ON_SRAM0_RESET 0x0
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#define PSM_FRCE_ON_SRAM0_BITS 0x00000040
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#define PSM_FRCE_ON_SRAM0_MSB 6
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#define PSM_FRCE_ON_SRAM0_LSB 6
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#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_ROM
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// Description : None
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#define PSM_FRCE_ON_ROM_RESET 0x0
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#define PSM_FRCE_ON_ROM_BITS 0x00000020
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#define PSM_FRCE_ON_ROM_MSB 5
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#define PSM_FRCE_ON_ROM_LSB 5
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#define PSM_FRCE_ON_ROM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_BUSFABRIC
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// Description : None
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#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0
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#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010
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#define PSM_FRCE_ON_BUSFABRIC_MSB 4
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#define PSM_FRCE_ON_BUSFABRIC_LSB 4
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#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_RESETS
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// Description : None
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#define PSM_FRCE_ON_RESETS_RESET 0x0
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#define PSM_FRCE_ON_RESETS_BITS 0x00000008
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#define PSM_FRCE_ON_RESETS_MSB 3
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#define PSM_FRCE_ON_RESETS_LSB 3
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#define PSM_FRCE_ON_RESETS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_CLOCKS
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// Description : None
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#define PSM_FRCE_ON_CLOCKS_RESET 0x0
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#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004
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#define PSM_FRCE_ON_CLOCKS_MSB 2
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#define PSM_FRCE_ON_CLOCKS_LSB 2
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#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_XOSC
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// Description : None
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#define PSM_FRCE_ON_XOSC_RESET 0x0
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#define PSM_FRCE_ON_XOSC_BITS 0x00000002
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#define PSM_FRCE_ON_XOSC_MSB 1
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#define PSM_FRCE_ON_XOSC_LSB 1
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#define PSM_FRCE_ON_XOSC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_ON_ROSC
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// Description : None
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#define PSM_FRCE_ON_ROSC_RESET 0x0
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#define PSM_FRCE_ON_ROSC_BITS 0x00000001
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#define PSM_FRCE_ON_ROSC_MSB 0
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#define PSM_FRCE_ON_ROSC_LSB 0
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#define PSM_FRCE_ON_ROSC_ACCESS "RW"
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// =============================================================================
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// Register : PSM_FRCE_OFF
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// Description : Force into reset (i.e. power it off)
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#define PSM_FRCE_OFF_OFFSET 0x00000004
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#define PSM_FRCE_OFF_BITS 0x0001ffff
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#define PSM_FRCE_OFF_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_PROC1
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// Description : None
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#define PSM_FRCE_OFF_PROC1_RESET 0x0
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#define PSM_FRCE_OFF_PROC1_BITS 0x00010000
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#define PSM_FRCE_OFF_PROC1_MSB 16
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#define PSM_FRCE_OFF_PROC1_LSB 16
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#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_PROC0
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// Description : None
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#define PSM_FRCE_OFF_PROC0_RESET 0x0
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#define PSM_FRCE_OFF_PROC0_BITS 0x00008000
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#define PSM_FRCE_OFF_PROC0_MSB 15
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#define PSM_FRCE_OFF_PROC0_LSB 15
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#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_SIO
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// Description : None
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#define PSM_FRCE_OFF_SIO_RESET 0x0
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#define PSM_FRCE_OFF_SIO_BITS 0x00004000
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#define PSM_FRCE_OFF_SIO_MSB 14
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#define PSM_FRCE_OFF_SIO_LSB 14
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#define PSM_FRCE_OFF_SIO_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
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// Description : None
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#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0
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#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000
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#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13
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#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13
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#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_XIP
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// Description : None
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#define PSM_FRCE_OFF_XIP_RESET 0x0
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#define PSM_FRCE_OFF_XIP_BITS 0x00001000
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#define PSM_FRCE_OFF_XIP_MSB 12
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#define PSM_FRCE_OFF_XIP_LSB 12
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#define PSM_FRCE_OFF_XIP_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_SRAM5
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// Description : None
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#define PSM_FRCE_OFF_SRAM5_RESET 0x0
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#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800
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#define PSM_FRCE_OFF_SRAM5_MSB 11
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#define PSM_FRCE_OFF_SRAM5_LSB 11
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#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_SRAM4
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// Description : None
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#define PSM_FRCE_OFF_SRAM4_RESET 0x0
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#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400
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#define PSM_FRCE_OFF_SRAM4_MSB 10
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#define PSM_FRCE_OFF_SRAM4_LSB 10
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#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_SRAM3
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// Description : None
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#define PSM_FRCE_OFF_SRAM3_RESET 0x0
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#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200
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#define PSM_FRCE_OFF_SRAM3_MSB 9
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#define PSM_FRCE_OFF_SRAM3_LSB 9
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#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_SRAM2
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// Description : None
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#define PSM_FRCE_OFF_SRAM2_RESET 0x0
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#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100
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#define PSM_FRCE_OFF_SRAM2_MSB 8
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#define PSM_FRCE_OFF_SRAM2_LSB 8
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#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_SRAM1
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// Description : None
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#define PSM_FRCE_OFF_SRAM1_RESET 0x0
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#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080
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#define PSM_FRCE_OFF_SRAM1_MSB 7
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#define PSM_FRCE_OFF_SRAM1_LSB 7
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#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_SRAM0
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// Description : None
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#define PSM_FRCE_OFF_SRAM0_RESET 0x0
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#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040
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#define PSM_FRCE_OFF_SRAM0_MSB 6
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#define PSM_FRCE_OFF_SRAM0_LSB 6
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#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_ROM
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// Description : None
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#define PSM_FRCE_OFF_ROM_RESET 0x0
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#define PSM_FRCE_OFF_ROM_BITS 0x00000020
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#define PSM_FRCE_OFF_ROM_MSB 5
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#define PSM_FRCE_OFF_ROM_LSB 5
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#define PSM_FRCE_OFF_ROM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_BUSFABRIC
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// Description : None
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#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0
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#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010
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#define PSM_FRCE_OFF_BUSFABRIC_MSB 4
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#define PSM_FRCE_OFF_BUSFABRIC_LSB 4
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#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_RESETS
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// Description : None
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#define PSM_FRCE_OFF_RESETS_RESET 0x0
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#define PSM_FRCE_OFF_RESETS_BITS 0x00000008
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#define PSM_FRCE_OFF_RESETS_MSB 3
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#define PSM_FRCE_OFF_RESETS_LSB 3
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#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_CLOCKS
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// Description : None
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#define PSM_FRCE_OFF_CLOCKS_RESET 0x0
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#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004
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#define PSM_FRCE_OFF_CLOCKS_MSB 2
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#define PSM_FRCE_OFF_CLOCKS_LSB 2
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#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_XOSC
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// Description : None
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#define PSM_FRCE_OFF_XOSC_RESET 0x0
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#define PSM_FRCE_OFF_XOSC_BITS 0x00000002
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#define PSM_FRCE_OFF_XOSC_MSB 1
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#define PSM_FRCE_OFF_XOSC_LSB 1
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#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_FRCE_OFF_ROSC
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// Description : None
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#define PSM_FRCE_OFF_ROSC_RESET 0x0
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#define PSM_FRCE_OFF_ROSC_BITS 0x00000001
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#define PSM_FRCE_OFF_ROSC_MSB 0
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#define PSM_FRCE_OFF_ROSC_LSB 0
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#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
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// =============================================================================
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// Register : PSM_WDSEL
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// Description : Set to 1 if this peripheral should be reset when the watchdog
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// fires.
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#define PSM_WDSEL_OFFSET 0x00000008
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#define PSM_WDSEL_BITS 0x0001ffff
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#define PSM_WDSEL_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_PROC1
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// Description : None
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#define PSM_WDSEL_PROC1_RESET 0x0
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#define PSM_WDSEL_PROC1_BITS 0x00010000
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#define PSM_WDSEL_PROC1_MSB 16
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#define PSM_WDSEL_PROC1_LSB 16
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#define PSM_WDSEL_PROC1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_PROC0
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// Description : None
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#define PSM_WDSEL_PROC0_RESET 0x0
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#define PSM_WDSEL_PROC0_BITS 0x00008000
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#define PSM_WDSEL_PROC0_MSB 15
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#define PSM_WDSEL_PROC0_LSB 15
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#define PSM_WDSEL_PROC0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_SIO
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// Description : None
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#define PSM_WDSEL_SIO_RESET 0x0
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#define PSM_WDSEL_SIO_BITS 0x00004000
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#define PSM_WDSEL_SIO_MSB 14
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#define PSM_WDSEL_SIO_LSB 14
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#define PSM_WDSEL_SIO_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
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// Description : None
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#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0
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#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000
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#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13
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#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13
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#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_XIP
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// Description : None
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#define PSM_WDSEL_XIP_RESET 0x0
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#define PSM_WDSEL_XIP_BITS 0x00001000
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#define PSM_WDSEL_XIP_MSB 12
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#define PSM_WDSEL_XIP_LSB 12
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#define PSM_WDSEL_XIP_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_SRAM5
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// Description : None
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#define PSM_WDSEL_SRAM5_RESET 0x0
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#define PSM_WDSEL_SRAM5_BITS 0x00000800
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#define PSM_WDSEL_SRAM5_MSB 11
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#define PSM_WDSEL_SRAM5_LSB 11
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#define PSM_WDSEL_SRAM5_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_SRAM4
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// Description : None
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#define PSM_WDSEL_SRAM4_RESET 0x0
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#define PSM_WDSEL_SRAM4_BITS 0x00000400
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#define PSM_WDSEL_SRAM4_MSB 10
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#define PSM_WDSEL_SRAM4_LSB 10
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#define PSM_WDSEL_SRAM4_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_SRAM3
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// Description : None
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#define PSM_WDSEL_SRAM3_RESET 0x0
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#define PSM_WDSEL_SRAM3_BITS 0x00000200
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#define PSM_WDSEL_SRAM3_MSB 9
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#define PSM_WDSEL_SRAM3_LSB 9
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#define PSM_WDSEL_SRAM3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_SRAM2
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// Description : None
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#define PSM_WDSEL_SRAM2_RESET 0x0
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#define PSM_WDSEL_SRAM2_BITS 0x00000100
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#define PSM_WDSEL_SRAM2_MSB 8
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#define PSM_WDSEL_SRAM2_LSB 8
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#define PSM_WDSEL_SRAM2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_SRAM1
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// Description : None
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#define PSM_WDSEL_SRAM1_RESET 0x0
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#define PSM_WDSEL_SRAM1_BITS 0x00000080
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#define PSM_WDSEL_SRAM1_MSB 7
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#define PSM_WDSEL_SRAM1_LSB 7
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#define PSM_WDSEL_SRAM1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_SRAM0
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// Description : None
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#define PSM_WDSEL_SRAM0_RESET 0x0
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#define PSM_WDSEL_SRAM0_BITS 0x00000040
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#define PSM_WDSEL_SRAM0_MSB 6
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#define PSM_WDSEL_SRAM0_LSB 6
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#define PSM_WDSEL_SRAM0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_ROM
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// Description : None
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#define PSM_WDSEL_ROM_RESET 0x0
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#define PSM_WDSEL_ROM_BITS 0x00000020
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#define PSM_WDSEL_ROM_MSB 5
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#define PSM_WDSEL_ROM_LSB 5
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#define PSM_WDSEL_ROM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_BUSFABRIC
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// Description : None
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#define PSM_WDSEL_BUSFABRIC_RESET 0x0
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#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010
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#define PSM_WDSEL_BUSFABRIC_MSB 4
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#define PSM_WDSEL_BUSFABRIC_LSB 4
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#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_RESETS
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// Description : None
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#define PSM_WDSEL_RESETS_RESET 0x0
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#define PSM_WDSEL_RESETS_BITS 0x00000008
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#define PSM_WDSEL_RESETS_MSB 3
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#define PSM_WDSEL_RESETS_LSB 3
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#define PSM_WDSEL_RESETS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_CLOCKS
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// Description : None
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#define PSM_WDSEL_CLOCKS_RESET 0x0
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#define PSM_WDSEL_CLOCKS_BITS 0x00000004
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#define PSM_WDSEL_CLOCKS_MSB 2
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#define PSM_WDSEL_CLOCKS_LSB 2
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#define PSM_WDSEL_CLOCKS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_XOSC
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// Description : None
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#define PSM_WDSEL_XOSC_RESET 0x0
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#define PSM_WDSEL_XOSC_BITS 0x00000002
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#define PSM_WDSEL_XOSC_MSB 1
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#define PSM_WDSEL_XOSC_LSB 1
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#define PSM_WDSEL_XOSC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PSM_WDSEL_ROSC
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// Description : None
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#define PSM_WDSEL_ROSC_RESET 0x0
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#define PSM_WDSEL_ROSC_BITS 0x00000001
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#define PSM_WDSEL_ROSC_MSB 0
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#define PSM_WDSEL_ROSC_LSB 0
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#define PSM_WDSEL_ROSC_ACCESS "RW"
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// =============================================================================
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// Register : PSM_DONE
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// Description : Indicates the peripheral's registers are ready to access.
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#define PSM_DONE_OFFSET 0x0000000c
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#define PSM_DONE_BITS 0x0001ffff
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#define PSM_DONE_RESET 0x00000000
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// -----------------------------------------------------------------------------
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// Field : PSM_DONE_PROC1
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// Description : None
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#define PSM_DONE_PROC1_RESET 0x0
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#define PSM_DONE_PROC1_BITS 0x00010000
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#define PSM_DONE_PROC1_MSB 16
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#define PSM_DONE_PROC1_LSB 16
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#define PSM_DONE_PROC1_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : PSM_DONE_PROC0
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// Description : None
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#define PSM_DONE_PROC0_RESET 0x0
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#define PSM_DONE_PROC0_BITS 0x00008000
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#define PSM_DONE_PROC0_MSB 15
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#define PSM_DONE_PROC0_LSB 15
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#define PSM_DONE_PROC0_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : PSM_DONE_SIO
|
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// Description : None
|
|
#define PSM_DONE_SIO_RESET 0x0
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#define PSM_DONE_SIO_BITS 0x00004000
|
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#define PSM_DONE_SIO_MSB 14
|
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#define PSM_DONE_SIO_LSB 14
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#define PSM_DONE_SIO_ACCESS "RO"
|
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// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_VREG_AND_CHIP_RESET
|
|
// Description : None
|
|
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0
|
|
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000
|
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#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13
|
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#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13
|
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#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_XIP
|
|
// Description : None
|
|
#define PSM_DONE_XIP_RESET 0x0
|
|
#define PSM_DONE_XIP_BITS 0x00001000
|
|
#define PSM_DONE_XIP_MSB 12
|
|
#define PSM_DONE_XIP_LSB 12
|
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#define PSM_DONE_XIP_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_SRAM5
|
|
// Description : None
|
|
#define PSM_DONE_SRAM5_RESET 0x0
|
|
#define PSM_DONE_SRAM5_BITS 0x00000800
|
|
#define PSM_DONE_SRAM5_MSB 11
|
|
#define PSM_DONE_SRAM5_LSB 11
|
|
#define PSM_DONE_SRAM5_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_SRAM4
|
|
// Description : None
|
|
#define PSM_DONE_SRAM4_RESET 0x0
|
|
#define PSM_DONE_SRAM4_BITS 0x00000400
|
|
#define PSM_DONE_SRAM4_MSB 10
|
|
#define PSM_DONE_SRAM4_LSB 10
|
|
#define PSM_DONE_SRAM4_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_SRAM3
|
|
// Description : None
|
|
#define PSM_DONE_SRAM3_RESET 0x0
|
|
#define PSM_DONE_SRAM3_BITS 0x00000200
|
|
#define PSM_DONE_SRAM3_MSB 9
|
|
#define PSM_DONE_SRAM3_LSB 9
|
|
#define PSM_DONE_SRAM3_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_SRAM2
|
|
// Description : None
|
|
#define PSM_DONE_SRAM2_RESET 0x0
|
|
#define PSM_DONE_SRAM2_BITS 0x00000100
|
|
#define PSM_DONE_SRAM2_MSB 8
|
|
#define PSM_DONE_SRAM2_LSB 8
|
|
#define PSM_DONE_SRAM2_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_SRAM1
|
|
// Description : None
|
|
#define PSM_DONE_SRAM1_RESET 0x0
|
|
#define PSM_DONE_SRAM1_BITS 0x00000080
|
|
#define PSM_DONE_SRAM1_MSB 7
|
|
#define PSM_DONE_SRAM1_LSB 7
|
|
#define PSM_DONE_SRAM1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_SRAM0
|
|
// Description : None
|
|
#define PSM_DONE_SRAM0_RESET 0x0
|
|
#define PSM_DONE_SRAM0_BITS 0x00000040
|
|
#define PSM_DONE_SRAM0_MSB 6
|
|
#define PSM_DONE_SRAM0_LSB 6
|
|
#define PSM_DONE_SRAM0_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_ROM
|
|
// Description : None
|
|
#define PSM_DONE_ROM_RESET 0x0
|
|
#define PSM_DONE_ROM_BITS 0x00000020
|
|
#define PSM_DONE_ROM_MSB 5
|
|
#define PSM_DONE_ROM_LSB 5
|
|
#define PSM_DONE_ROM_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_BUSFABRIC
|
|
// Description : None
|
|
#define PSM_DONE_BUSFABRIC_RESET 0x0
|
|
#define PSM_DONE_BUSFABRIC_BITS 0x00000010
|
|
#define PSM_DONE_BUSFABRIC_MSB 4
|
|
#define PSM_DONE_BUSFABRIC_LSB 4
|
|
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_RESETS
|
|
// Description : None
|
|
#define PSM_DONE_RESETS_RESET 0x0
|
|
#define PSM_DONE_RESETS_BITS 0x00000008
|
|
#define PSM_DONE_RESETS_MSB 3
|
|
#define PSM_DONE_RESETS_LSB 3
|
|
#define PSM_DONE_RESETS_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_CLOCKS
|
|
// Description : None
|
|
#define PSM_DONE_CLOCKS_RESET 0x0
|
|
#define PSM_DONE_CLOCKS_BITS 0x00000004
|
|
#define PSM_DONE_CLOCKS_MSB 2
|
|
#define PSM_DONE_CLOCKS_LSB 2
|
|
#define PSM_DONE_CLOCKS_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_XOSC
|
|
// Description : None
|
|
#define PSM_DONE_XOSC_RESET 0x0
|
|
#define PSM_DONE_XOSC_BITS 0x00000002
|
|
#define PSM_DONE_XOSC_MSB 1
|
|
#define PSM_DONE_XOSC_LSB 1
|
|
#define PSM_DONE_XOSC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : PSM_DONE_ROSC
|
|
// Description : None
|
|
#define PSM_DONE_ROSC_RESET 0x0
|
|
#define PSM_DONE_ROSC_BITS 0x00000001
|
|
#define PSM_DONE_ROSC_MSB 0
|
|
#define PSM_DONE_ROSC_LSB 0
|
|
#define PSM_DONE_ROSC_ACCESS "RO"
|
|
// =============================================================================
|
|
#endif // HARDWARE_REGS_PSM_DEFINED
|