From 3871718a35317d4d45a7e5bd720daa97159242e4 Mon Sep 17 00:00:00 2001 From: Peter Lawrence <12226419+majbthrd@users.noreply.github.com> Date: Thu, 4 Feb 2021 16:51:59 -0600 Subject: [PATCH] initial commit --- .gitmodules | 6 + CMSIS_5 | 1 + DAP_config.h | 502 + Makefile | 11 + README.md | 24 + RP2040_Startup.s | 113 + clock_setup.c | 92 + main.c | 79 + myboard.c | 70 + pico-debug.hzp | 100 + pico/config_autogen.h | 7 + pico/version.h | 19 + picodebug_MemoryMap.xml | 5 + picodebug_Startup.s | 163 + picodebug_placement.xml | 14 + ram_placement.xml | 37 + rp2040/hardware/address_mapped.h | 123 + rp2040/hardware/platform_defs.h | 48 + rp2040/hardware/regs/adc.h | 314 + rp2040/hardware/regs/addressmap.h | 72 + rp2040/hardware/regs/busctrl.h | 160 + rp2040/hardware/regs/clocks.h | 2359 +++ rp2040/hardware/regs/dma.h | 5257 ++++++ rp2040/hardware/regs/dreq.h | 50 + rp2040/hardware/regs/i2c.h | 2685 +++ rp2040/hardware/regs/intctrl.h | 63 + rp2040/hardware/regs/io_bank0.h | 14937 ++++++++++++++++ rp2040/hardware/regs/io_qspi.h | 2931 +++ rp2040/hardware/regs/m0plus.h | 1149 ++ rp2040/hardware/regs/pads_bank0.h | 2300 +++ rp2040/hardware/regs/pads_qspi.h | 454 + rp2040/hardware/regs/pio.h | 2591 +++ rp2040/hardware/regs/pll.h | 135 + rp2040/hardware/regs/psm.h | 584 + rp2040/hardware/regs/pwm.h | 1505 ++ rp2040/hardware/regs/resets.h | 637 + rp2040/hardware/regs/rosc.h | 312 + rp2040/hardware/regs/rtc.h | 398 + rp2040/hardware/regs/sio.h | 1656 ++ rp2040/hardware/regs/spi.h | 521 + rp2040/hardware/regs/ssi.h | 809 + rp2040/hardware/regs/syscfg.h | 257 + rp2040/hardware/regs/sysinfo.h | 77 + rp2040/hardware/regs/tbman.h | 38 + rp2040/hardware/regs/timer.h | 332 + rp2040/hardware/regs/uart.h | 1148 ++ rp2040/hardware/regs/usb.h | 3603 ++++ rp2040/hardware/regs/vreg_and_chip_reset.h | 151 + rp2040/hardware/regs/watchdog.h | 226 + rp2040/hardware/regs/xip.h | 187 + rp2040/hardware/regs/xosc.h | 159 + rp2040/hardware/structs/adc.h | 28 + rp2040/hardware/structs/bus_ctrl.h | 48 + rp2040/hardware/structs/clocks.h | 72 + rp2040/hardware/structs/dma.h | 65 + rp2040/hardware/structs/i2c.h | 141 + rp2040/hardware/structs/interp.h | 28 + rp2040/hardware/structs/iobank0.h | 35 + rp2040/hardware/structs/ioqspi.h | 23 + rp2040/hardware/structs/mpu.h | 23 + rp2040/hardware/structs/pads_qspi.h | 21 + rp2040/hardware/structs/padsbank0.h | 21 + rp2040/hardware/structs/pio.h | 48 + rp2040/hardware/structs/pll.h | 25 + rp2040/hardware/structs/psm.h | 23 + rp2040/hardware/structs/pwm.h | 33 + rp2040/hardware/structs/resets.h | 22 + rp2040/hardware/structs/rosc.h | 29 + rp2040/hardware/structs/rtc.h | 31 + rp2040/hardware/structs/scb.h | 24 + rp2040/hardware/structs/sio.h | 61 + rp2040/hardware/structs/spi.h | 29 + rp2040/hardware/structs/ssi.h | 47 + rp2040/hardware/structs/syscfg.h | 26 + rp2040/hardware/structs/systick.h | 22 + rp2040/hardware/structs/timer.h | 35 + rp2040/hardware/structs/uart.h | 35 + rp2040/hardware/structs/usb.h | 147 + rp2040/hardware/structs/vreg_and_chip_reset.h | 22 + rp2040/hardware/structs/watchdog.h | 24 + rp2040/hardware/structs/xip_ctrl.h | 29 + rp2040/hardware/structs/xosc.h | 27 + rp2040/pico.h | 12 + rp2040/rp2040.h | 111 + tinyusb | 1 + tusb_config.h | 110 + usb_descriptors.c | 140 + 87 files changed, 51089 insertions(+) create mode 100644 .gitmodules create mode 160000 CMSIS_5 create mode 100644 DAP_config.h create mode 100644 Makefile create mode 100644 README.md create mode 100644 RP2040_Startup.s create mode 100644 clock_setup.c create mode 100644 main.c create mode 100644 myboard.c create mode 100644 pico-debug.hzp create mode 100644 pico/config_autogen.h create mode 100644 pico/version.h create mode 100644 picodebug_MemoryMap.xml create mode 100644 picodebug_Startup.s create mode 100644 picodebug_placement.xml create mode 100644 ram_placement.xml create mode 100644 rp2040/hardware/address_mapped.h create mode 100644 rp2040/hardware/platform_defs.h create mode 100644 rp2040/hardware/regs/adc.h create mode 100644 rp2040/hardware/regs/addressmap.h create mode 100644 rp2040/hardware/regs/busctrl.h create mode 100644 rp2040/hardware/regs/clocks.h create mode 100644 rp2040/hardware/regs/dma.h create mode 100644 rp2040/hardware/regs/dreq.h create mode 100644 rp2040/hardware/regs/i2c.h create mode 100644 rp2040/hardware/regs/intctrl.h create mode 100644 rp2040/hardware/regs/io_bank0.h create mode 100644 rp2040/hardware/regs/io_qspi.h create mode 100644 rp2040/hardware/regs/m0plus.h create mode 100644 rp2040/hardware/regs/pads_bank0.h create mode 100644 rp2040/hardware/regs/pads_qspi.h create mode 100644 rp2040/hardware/regs/pio.h create mode 100644 rp2040/hardware/regs/pll.h create mode 100644 rp2040/hardware/regs/psm.h create mode 100644 rp2040/hardware/regs/pwm.h create mode 100644 rp2040/hardware/regs/resets.h create mode 100644 rp2040/hardware/regs/rosc.h create mode 100644 rp2040/hardware/regs/rtc.h create mode 100644 rp2040/hardware/regs/sio.h create mode 100644 rp2040/hardware/regs/spi.h create mode 100644 rp2040/hardware/regs/ssi.h create mode 100644 rp2040/hardware/regs/syscfg.h create mode 100644 rp2040/hardware/regs/sysinfo.h create mode 100644 rp2040/hardware/regs/tbman.h create mode 100644 rp2040/hardware/regs/timer.h create mode 100644 rp2040/hardware/regs/uart.h create mode 100644 rp2040/hardware/regs/usb.h create mode 100644 rp2040/hardware/regs/vreg_and_chip_reset.h create mode 100644 rp2040/hardware/regs/watchdog.h create mode 100644 rp2040/hardware/regs/xip.h create mode 100644 rp2040/hardware/regs/xosc.h create mode 100644 rp2040/hardware/structs/adc.h create mode 100644 rp2040/hardware/structs/bus_ctrl.h create mode 100644 rp2040/hardware/structs/clocks.h create mode 100644 rp2040/hardware/structs/dma.h create mode 100644 rp2040/hardware/structs/i2c.h create mode 100644 rp2040/hardware/structs/interp.h create mode 100644 rp2040/hardware/structs/iobank0.h create mode 100644 rp2040/hardware/structs/ioqspi.h create mode 100644 rp2040/hardware/structs/mpu.h create mode 100644 rp2040/hardware/structs/pads_qspi.h create mode 100644 rp2040/hardware/structs/padsbank0.h create mode 100644 rp2040/hardware/structs/pio.h create mode 100644 rp2040/hardware/structs/pll.h create mode 100644 rp2040/hardware/structs/psm.h create mode 100644 rp2040/hardware/structs/pwm.h create mode 100644 rp2040/hardware/structs/resets.h create mode 100644 rp2040/hardware/structs/rosc.h create mode 100644 rp2040/hardware/structs/rtc.h create mode 100644 rp2040/hardware/structs/scb.h create mode 100644 rp2040/hardware/structs/sio.h create mode 100644 rp2040/hardware/structs/spi.h create mode 100644 rp2040/hardware/structs/ssi.h create mode 100644 rp2040/hardware/structs/syscfg.h create mode 100644 rp2040/hardware/structs/systick.h create mode 100644 rp2040/hardware/structs/timer.h create mode 100644 rp2040/hardware/structs/uart.h create mode 100644 rp2040/hardware/structs/usb.h create mode 100644 rp2040/hardware/structs/vreg_and_chip_reset.h create mode 100644 rp2040/hardware/structs/watchdog.h create mode 100644 rp2040/hardware/structs/xip_ctrl.h create mode 100644 rp2040/hardware/structs/xosc.h create mode 100644 rp2040/pico.h create mode 100644 rp2040/rp2040.h create mode 160000 tinyusb create mode 100644 tusb_config.h create mode 100644 usb_descriptors.c diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..2cbc82b --- /dev/null +++ b/.gitmodules @@ -0,0 +1,6 @@ +[submodule "tinyusb"] + path = tinyusb + url = https://github.com/hathach/tinyusb.git +[submodule "CMSIS_5"] + path = CMSIS_5 + url = https://github.com/ARM-software/CMSIS_5.git diff --git a/CMSIS_5 b/CMSIS_5 new file mode 160000 index 0000000..61cfe5d --- /dev/null +++ b/CMSIS_5 @@ -0,0 +1 @@ +Subproject commit 61cfe5d56fc68ffcfdba74b8c21747801ac88b2e diff --git a/DAP_config.h b/DAP_config.h new file mode 100644 index 0000000..f04b40b --- /dev/null +++ b/DAP_config.h @@ -0,0 +1,502 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Peter Lawrence + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* +This DAP_config provides for core0 of a Raspberry Pi Pico RP2040 to debug core1. + +At the time of writing, host software that supports "multi-drop" SWD +(particularly with CMSIS-DAP) is hard to come by. As a result, your favorite +software may not function with this target, even though it works with other +ARM targets. + +As a stopgap measure, PORT_SWD_SETUP() below has been enhanced to perform some +of the "multi-drop" initialization that would normally be done by host software. +*/ + +#ifndef __DAP_CONFIG_H__ +#define __DAP_CONFIG_H__ + +//************************************************************************************************** +/** +\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information +\ingroup DAP_ConfigIO_gr +@{ +Provides definitions about the hardware and configuration of the Debug Unit. + +This information includes: + - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. + - Debug Unit Identification strings (Vendor, Product, Serial Number). + - Debug Unit communication packet size. + - Debug Access Port supported modes and settings (JTAG/SWD and SWO). + - Optional information about a connected Target Device (for Evaluation Boards). +*/ + +#include "cmsis_compiler.h" +#include "bsp/board.h" + +#include +#include +#include +#include +#include + +/// Processor Clock of the Cortex-M MCU used in the Debug Unit. +/// This value is used to calculate the SWD/JTAG clock speed. +#define CPU_CLOCK 48000000U ///< Specifies the CPU Clock in Hz. + +/// Number of processor cycles for I/O Port write operations. +/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O +/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors +/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses +/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be +/// required. +#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0. + +/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available. + +/// Indicate that JTAG communication mode is available at the Debug Port. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available. + +/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. +/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. +#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain. + +/// Default communication mode on the Debug Access Port. +/// Used for the command \ref DAP_Connect when Port Default mode is selected. +#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. + +/// Default communication speed on the Debug Access Port for SWD and JTAG mode. +/// Used to initialize the default SWD/JTAG clock frequency. +/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. +#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz. + +/// Maximum Package Size for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. Typical vales are 64 for Full-speed USB HID or WinUSB, +/// 1024 for High-speed USB HID and 512 for High-speed USB WinUSB. +#define DAP_PACKET_SIZE CFG_TUD_HID_EP_BUFSIZE ///< Specifies Packet Size in bytes. + +/// Maximum Package Buffers for Command and Response data. +/// This configuration settings is used to optimize the communication performance with the +/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the +/// setting can be reduced (valid range is 1 .. 255). +#define DAP_PACKET_COUNT 1U ///< Specifies number of packets buffered. + +/// Indicate that UART Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available. + +/// Maximum SWO UART Baudrate. +#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz. + +/// Indicate that Manchester Serial Wire Output (SWO) trace is available. +/// This information is returned by the command \ref DAP_Info as part of Capabilities. +#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available. + +/// SWO Trace Buffer Size. +#define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n). + +/// SWO Streaming Trace. +#define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. + +/// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. +#define TIMESTAMP_CLOCK 0U ///< Timestamp clock in Hz (0 = timestamps not supported). + +/// Debug Unit is connected to fixed Target Device. +/// The Debug Unit may be part of an evaluation board and always connected to a fixed +/// known device. In this case a Device Vendor and Device Name string is stored which +/// may be used by the debugger or IDE to configure device parameters. +#define TARGET_DEVICE_FIXED 1 ///< Target Device: 1 = known, 0 = unknown; + +#if TARGET_DEVICE_FIXED +#define TARGET_DEVICE_VENDOR "Raspberry Pi" ///< String indicating the Silicon Vendor +#define TARGET_DEVICE_NAME "Pico" ///< String indicating the Target Device +#endif + +#include "DAP.h" + +/** Get Vendor ID string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetVendorString (char *str) { + (void)str; + return (0U); +} + +/** Get Product ID string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetProductString (char *str) { + (void)str; + return (0U); +} + +/** Get Serial Number string. +\param str Pointer to buffer to store the string. +\return String length. +*/ +__STATIC_INLINE uint8_t DAP_GetSerNumString (char *str) { + (void)str; + return (0U); +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access +\ingroup DAP_ConfigIO_gr +@{ + +Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode +and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug +interface of a device. The following I/O Pins are provided: + +JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode +---------------------------- | -------------------- | --------------------------------------------- +TCK: Test Clock | SWCLK: Clock | Output Push/Pull +TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) +TDI: Test Data Input | | Output Push/Pull +TDO: Test Data Output | | Input +nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor +nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor + + +DAP Hardware I/O Pin Access Functions +------------------------------------- +The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to +these I/O Pins. + +For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. +This functions are provided to achieve faster I/O that is possible with some advanced GPIO +peripherals that can independently write/read a single I/O pin without affecting any other pins +of the same I/O port. The following SWDIO I/O Pin functions are provided: + - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. + - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. + - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. + - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. +*/ + + +// Configure DAP I/O pins ------------------------------ + +/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. +Configures the DAP Hardware I/O pins for JTAG mode: + - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. + - TDO to input mode. +*/ +__STATIC_INLINE void PORT_JTAG_SETUP (void) { + ; +} + +/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. +Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: + - SWCLK, SWDIO, nRESET to output mode and set to default high level. + - TDI, nTRST to HighZ mode (pins are unused in SWD mode). +*/ +__STATIC_INLINE void PORT_SWD_SETUP (void) { + + /* enable the peripheral and enable local control of core1's SWD interface */ + resets_hw->reset &= ~RESETS_RESET_SYSCFG_BITS; + syscfg_hw->dbgforce = SYSCFG_DBGFORCE_PROC1_ATTACH_BITS; + +#if 1 + /* this #if block is a temporary measure to perform target selection even if the host IDE doesn't know how */ + + static const uint8_t sequence_alert[] = { + 0xff, 0x92, 0xf3, 0x09, 0x62, 0x95, 0x2d, 0x85, 0x86, 0xe9, 0xaf, 0xdd, 0xe3, 0xa2, 0x0e, 0xbc, + 0x19, 0xa0, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0x00, + }; + SWJ_Sequence(8*sizeof(sequence_alert), sequence_alert); + + /* it is possible to do this with SWJ_Sequence on the rp2040 since data input and output are distinct */ + static const uint8_t write_targetsel[] = { 0x99, 0xff, 0x24, 0x05, 0x20, 0x22, 0x00, }; + SWJ_Sequence(8*sizeof(write_targetsel), write_targetsel); +#endif + + /* set to default high level */ + syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWCLK_BITS | SYSCFG_DBGFORCE_PROC1_SWDI_BITS; +} + +/** Disable JTAG/SWD I/O Pins. +Disables the DAP Hardware I/O pins which configures: + - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. +*/ +__STATIC_INLINE void PORT_OFF (void) { + syscfg_hw->dbgforce = 0; +} + + +// SWCLK/TCK I/O pin ------------------------------------- + +/** SWCLK/TCK I/O pin: Get Input. +\return Current status of the SWCLK/TCK DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN (void) { + return (0U); +} + +/** SWCLK/TCK I/O pin: Set Output to High. +Set the SWCLK/TCK DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET (void) { + syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWCLK_BITS; +} + +/** SWCLK/TCK I/O pin: Set Output to Low. +Set the SWCLK/TCK DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR (void) { + syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC1_SWCLK_BITS; +} + + +// SWDIO/TMS Pin I/O -------------------------------------- + +/** SWDIO/TMS I/O pin: Get Input. +\return Current status of the SWDIO/TMS DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN (void) { + return (0U); +} + +/* PIN_SWDIO_TMS_SET and PIN_SWDIO_TMS_CLR are used by SWJ_Sequence */ + +/** SWDIO/TMS I/O pin: Set Output to High. +Set the SWDIO/TMS DAP hardware I/O pin to high level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET (void) { + syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWDI_BITS; +} + +/** SWDIO/TMS I/O pin: Set Output to Low. +Set the SWDIO/TMS DAP hardware I/O pin to low level. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR (void) { + syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC1_SWDI_BITS; +} + +/** SWDIO I/O pin: Get Input (used in SWD mode only). +\return Current status of the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN (void) { + return (syscfg_hw->dbgforce & SYSCFG_DBGFORCE_PROC1_SWDO_BITS) ? 1U : 0U; +} + +/** SWDIO I/O pin: Set Output (used in SWD mode only). +\param bit Output value for the SWDIO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT (uint32_t bit) { + if (bit & 1) + syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWDI_BITS; + else + syscfg_hw->dbgforce &= ~SYSCFG_DBGFORCE_PROC1_SWDI_BITS; +} + +/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to output mode. This function is +called prior \ref PIN_SWDIO_OUT function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE (void) { + ; +} + +/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). +Configure the SWDIO DAP hardware I/O pin to input mode. This function is +called prior \ref PIN_SWDIO_IN function calls. +*/ +__STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE (void) { + syscfg_hw->dbgforce |= SYSCFG_DBGFORCE_PROC1_SWDI_BITS; +} + + +// TDI Pin I/O --------------------------------------------- + +/** TDI I/O pin: Get Input. +\return Current status of the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDI_IN (void) { + return (0U); +} + +/** TDI I/O pin: Set Output. +\param bit Output value for the TDI DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE void PIN_TDI_OUT (uint32_t bit) { + (void)bit; +} + + +// TDO Pin I/O --------------------------------------------- + +/** TDO I/O pin: Get Input. +\return Current status of the TDO DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_TDO_IN (void) { + return (0U); +} + + +// nTRST Pin I/O ------------------------------------------- + +/** nTRST I/O pin: Get Input. +\return Current status of the nTRST DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nTRST_IN (void) { + return (0U); +} + +/** nTRST I/O pin: Set Output. +\param bit JTAG TRST Test Reset pin status: + - 0: issue a JTAG TRST Test Reset. + - 1: release JTAG TRST Test Reset. +*/ +__STATIC_FORCEINLINE void PIN_nTRST_OUT (uint32_t bit) { + (void)bit; +} + +// nRESET Pin I/O------------------------------------------ + +/** nRESET I/O pin: Get Input. +\return Current status of the nRESET DAP hardware I/O pin. +*/ +__STATIC_FORCEINLINE uint32_t PIN_nRESET_IN (void) { + return (0U); +} + +/** nRESET I/O pin: Set Output. +\param bit target device hardware reset pin status: + - 0: issue a device hardware reset. + - 1: release device hardware reset. +*/ +__STATIC_FORCEINLINE void PIN_nRESET_OUT (uint32_t bit) { + (void)bit; +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. + +It is recommended to provide the following LEDs for status indication: + - Connect LED: is active when the DAP hardware is connected to a debugger. + - Running LED: is active when the debugger has put the target device into running state. +*/ + +/** Debug Unit: Set status of Connected LED. +\param bit status of the Connect LED. + - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. + - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. +*/ +__STATIC_INLINE void LED_CONNECTED_OUT (uint32_t bit) { + (void)bit; +} + +/** Debug Unit: Set status Target Running LED. +\param bit status of the Target Running LED. + - 1: Target Running LED ON: program execution in target started. + - 0: Target Running LED OFF: program execution in target stopped. +*/ +__STATIC_INLINE void LED_RUNNING_OUT (uint32_t bit) { + (void)bit; +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp +\ingroup DAP_ConfigIO_gr +@{ +Access function for Test Domain Timer. + +The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By +default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. + +*/ + +/** Get timestamp of Test Domain Timer. +\return Current timestamp value. +*/ +__STATIC_INLINE uint32_t TIMESTAMP_GET (void) { +#if TIMESTAMP_CLOCK > 0 + return (DWT->CYCCNT); +#else + return 0; +#endif +} + +///@} + + +//************************************************************************************************** +/** +\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization +\ingroup DAP_ConfigIO_gr +@{ + +CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. +*/ + +/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). +This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the +Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: + - I/O clock system enabled. + - all I/O pins: input buffer enabled, output pins are set to HighZ mode. + - for nTRST, nRESET a weak pull-up (if available) is enabled. + - LED output pins are enabled and LEDs are turned off. +*/ +__STATIC_INLINE void DAP_SETUP (void) { + ; +} + +/** Reset Target Device with custom specific I/O pin or command sequence. +This function allows the optional implementation of a device specific reset sequence. +It is called when the command \ref DAP_ResetTarget and is for example required +when a device needs a time-critical unlock sequence that enables the debug port. +\return 0 = no device specific reset sequence is implemented.\n + 1 = a device specific reset sequence is implemented. +*/ +__STATIC_INLINE uint8_t RESET_TARGET (void) { + return (0U); // change to '1' when a device reset sequence is implemented +} + +///@} + + +#endif /* __DAP_CONFIG_H__ */ diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..b5208bf --- /dev/null +++ b/Makefile @@ -0,0 +1,11 @@ +include ../tinyusb/tools/top.mk +include ../tinyusb/examples/make.mk + +INC += \ + . \ + $(TOP)/hw \ + +APP_SOURCE += $(wildcard ./*.c) +SRC_C += $(addprefix $(CURRENT_PATH)/, $(APP_SOURCE)) + +include ../tinyusb/examples/rules.mk diff --git a/README.md b/README.md new file mode 100644 index 0000000..d2ee0e0 --- /dev/null +++ b/README.md @@ -0,0 +1,24 @@ +## Description + +RP2040 has two ARM Cortex-M0+ cores, and the second core normally remains dormant. + +pico-debug runs on one core in a RP2040 and provides a USB CMSIS-DAP interface to debug the other core. No hardware is added; it is as if there were a virtual debug pod built-in. + +Boot the RP2040 with the BOOTSEL button pressed, copy over pico-debug.uf2, and it immediately reboots as a CMSIS-DAP adapter. pico-debug loads as a RAM only .uf2 image, meaning that it is never written to flash and doesn't replace existing user code. + +*All* 264kBytes of SRAM on the RP2040 is available for running user code; pico-debug shoehorns itself entirely into the 16kBytes of XIP_SRAM (aka flash cache). + +If viewing this on github, a pre-built binary is available for download on the right under "Releases". + +## Caveats whilst using pico-debug + +- the flash cache cannot be used by the user code, as pico-debug is using this memory +- user code cannot reconfigure the PLL and clocks, as the USB peripheral needs this +- the USB peripheral is used to provide the debugger, so the user code cannot use it as well + +## License + +TinyUSB and code specific to pico-debug is licensed under the [MIT license](https://opensource.org/licenses/MIT). + +ARM's CMSIS_5 code is licensed under the [Apache 2.0 license](https://opensource.org/licenses/Apache-2.0). + diff --git a/RP2040_Startup.s b/RP2040_Startup.s new file mode 100644 index 0000000..eedbb2d --- /dev/null +++ b/RP2040_Startup.s @@ -0,0 +1,113 @@ +/***************************************************************************** + * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE * + * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * + *****************************************************************************/ + +//#define STARTUP_FROM_RESET + +.macro ISR_HANDLER name= + .section .vectors, "ax" + .word \name + .section .init, "ax" + .thumb_func + .weak \name +\name: +1: b 1b /* endless loop */ +.endm + +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + + .syntax unified + .global reset_handler + + .section .boot, "ax" + .thumb_func + +reset_handler: + +#ifndef __NO_SYSTEM_INIT + ldr r0, =__SRAM_segment_end__ + mov sp, r0 + bl SystemInit +#endif + +#ifdef VECTORS_IN_RAM + ldr r0, =__vectors_load_start__ + ldr r1, =__vectors_load_end__ + ldr r2, =_vectors_ram +l0: + cmp r0, r1 + beq l1 + ldr r3, [r0] + str r3, [r2] + adds r0, r0, #4 + adds r2, r2, #4 + b l0 +l1: +#endif + + /* origin of user app */ +#ifdef VECTORS_IN_RAM + ldr r1, =_vectors_ram +#else + ldr r1, =_vectors +#endif + ldr r0, =0xE000ED08 /* VTOR register */ + str r1, [r0] /* point VTOR to user app */ + ldr r0, [r1] /* load stack pointer from user app */ + msr msp, r0 + msr psp, r0 + + b _start + +#ifndef __NO_SYSTEM_INIT + .thumb_func + .weak SystemInit +SystemInit: + bx lr +#endif + +#ifndef STARTUP_FROM_RESET + .thumb_func +reset_wait: +1: b 1b /* endless loop */ +#endif /* STARTUP_FROM_RESET */ + + .section .vectors, "ax" + .code 16 + .global _vectors + .align 8 + +_vectors: + .word __stack_end__ +#ifdef STARTUP_FROM_RESET + .word reset_handler +#else + .word reset_wait +#endif /* STARTUP_FROM_RESET */ +ISR_HANDLER NMI_Handler +ISR_HANDLER HardFault_Handler +ISR_HANDLER MemManage_Handler +ISR_HANDLER BusFault_Handler +ISR_HANDLER UsageFault_Handler +ISR_RESERVED +ISR_RESERVED +ISR_RESERVED +ISR_RESERVED +ISR_HANDLER SVC_Handler +ISR_HANDLER DebugMon_Handler +ISR_RESERVED +ISR_HANDLER PendSV_Handler +ISR_HANDLER SysTick_Handler +#include "RP2040.vec" + .section .vectors, "ax" +_vectors_end: + +#ifdef VECTORS_IN_RAM + .section .vectors_ram, "ax" +_vectors_ram: + .space _vectors_end-_vectors, 0 +#endif diff --git a/clock_setup.c b/clock_setup.c new file mode 100644 index 0000000..6f40c17 --- /dev/null +++ b/clock_setup.c @@ -0,0 +1,92 @@ +/* this function was salvaged from pico-bootrom/bootrom/bootrom_main.c */ + +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +// USB bootloader requires clk_sys and clk_usb at 48 MHz. For this to work, +// xosc must be running at 12 MHz. It is possible that: +// +// - No crystal is present (and XI may not be properly grounded) +// - xosc output is much greater than 12 MHz +// +// In this case we *must* leave clk_sys in a safe state, and ideally, never +// return from this function. This is because boards which are not designed to +// use USB will still enter the USB bootcode when booted with a blank flash. + +void _usb_clock_setup(void) { + // First make absolutely sure clk_ref is running: needed for resuscitate, + // and to run clk_sys while configuring sys PLL. Assume that rosc is not + // configured to run faster than clk_sys max (as this is officially out of + // spec) + // If user previously configured clk_ref to a different source (e.g. + // GPINx), then halted that source, the glitchless mux can't switch away + // from the dead source-- nothing we can do about this here. + rosc_hw->ctrl = ROSC_CTRL_ENABLE_VALUE_ENABLE << ROSC_CTRL_ENABLE_LSB; + hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); + + // Resuscitate logic will switch clk_sys to clk_ref if it is inadvertently stopped + clocks_hw->resus.ctrl = + CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | + (CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET + << CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB); + + // Resetting PLL regs or changing XOSC range can glitch output, so switch + // clk_sys away before touching. Not worried about clk_usb as USB is held + // in reset. + hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); + while (!(clocks_hw->clk[clk_sys].selected & 1u)); + // rosc can not (while following spec) run faster than clk_sys max, so + // it's safe now to clear dividers in clkslices. + clocks_hw->clk[clk_sys].div = 0x100; // int 1 frac 0 + clocks_hw->clk[clk_usb].div = 0x100; + + // Try to get the crystal running. If no crystal is present, XI should be + // grounded, so STABLE counter will never complete. Poor designs might + // leave XI floating, in which case we may eventually drop through... in + // this case we rely on PLL not locking, and/or resuscitate counter. + // + // Don't touch range setting: user would only have changed if crystal + // needs it, and running crystal out of range can produce glitchy output. + // Note writing a "bad" value (non-aax) to RANGE has no effect. + xosc_hw->ctrl = XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB; + while (!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)); + + // Sys PLL setup: + // - VCO freq 1200 MHz, so feedback divisor of 100. Range is 400 MHz to 1.6 GHz + // - Postdiv1 of 5, down to 240 MHz (appnote recommends postdiv1 >= postdiv2) + // - Postdiv2 of 5, down to 48 MHz + // + // Total postdiv of 25 means that too-fast xtal will push VCO out of + // lockable range *before* clk_sys goes out of closure (factor of 1.88) + hw_set_bits(&resets_hw->reset, RESETS_RESET_PLL_SYS_BITS); + hw_clear_bits(&resets_hw->reset, RESETS_RESET_PLL_SYS_BITS); + while (!(resets_hw->reset_done & RESETS_RESET_DONE_PLL_SYS_BITS)); + pll_sys_hw->cs = 1u << PLL_CS_REFDIV_LSB; + pll_sys_hw->fbdiv_int = 100; + pll_sys_hw->prim = + (5u << PLL_PRIM_POSTDIV1_LSB) | + (5u << PLL_PRIM_POSTDIV2_LSB); + + // Power up VCO, wait for lock + hw_clear_bits(&pll_sys_hw->pwr, PLL_PWR_PD_BITS | PLL_PWR_VCOPD_BITS); + while (!(pll_sys_hw->cs & PLL_CS_LOCK_BITS)); + + // Power up post-dividers, which ungates PLL final output + hw_clear_bits(&pll_sys_hw->pwr, PLL_PWR_POSTDIVPD_BITS); + + // Glitchy switch of clk_usb, clk_sys aux to sys PLL output. + clocks_hw->clk[clk_sys].ctrl = 0; + clocks_hw->clk[clk_usb].ctrl = + CLOCKS_CLK_USB_CTRL_ENABLE_BITS | + (CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS + << CLOCKS_CLK_USB_CTRL_AUXSRC_LSB); + + // Glitchless switch of clk_sys to aux source (sys PLL) + hw_set_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); + while (!(clocks_hw->clk[clk_sys].selected & 0x2u)); +} diff --git a/main.c b/main.c new file mode 100644 index 0000000..96871d0 --- /dev/null +++ b/main.c @@ -0,0 +1,79 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include +#include +#include + +#include "bsp/board.h" +#include "tusb.h" +#include "DAP.h" + +int main(void) +{ + board_init(); + DAP_Setup(); + + tusb_init(); + + while (1) + { + tud_task(); // tinyusb device task + } + + return 0; +} + +//--------------------------------------------------------------------+ +// USB HID +//--------------------------------------------------------------------+ + +// Invoked when received GET_REPORT control request +// Application must fill buffer report's content and return its length. +// Return zero will cause the stack to STALL request +uint16_t tud_hid_get_report_cb(uint8_t report_id, hid_report_type_t report_type, uint8_t* buffer, uint16_t reqlen) +{ + // TODO not Implemented + (void) report_id; + (void) report_type; + (void) buffer; + (void) reqlen; + + return 0; +} + +void tud_hid_set_report_cb(uint8_t report_id, hid_report_type_t report_type, uint8_t const* RxDataBuffer, uint16_t bufsize) +{ + static uint8_t TxDataBuffer[CFG_TUD_HID_EP_BUFSIZE]; + uint32_t response_size = TU_MIN(CFG_TUD_HID_EP_BUFSIZE, bufsize); + + // This doesn't use multiple report and report ID + (void) report_id; + (void) report_type; + + DAP_ProcessCommand(RxDataBuffer, TxDataBuffer); + + tud_hid_report(0, TxDataBuffer, response_size); +} diff --git a/myboard.c b/myboard.c new file mode 100644 index 0000000..960c2ed --- /dev/null +++ b/myboard.c @@ -0,0 +1,70 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Peter Lawrence + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "bsp/board.h" +#include "tusb.h" +#include + +/* +This is a more streamlined alternative to the current pico-sdk based TinyUSB board support package. +Sticking to C and avoiding all that C++ yields a much smaller executable. +*/ + +void _usb_clock_setup(void); /* clock initialization routine borrowed from pico-bootrom */ + +void board_init(void) +{ + _usb_clock_setup(); +} + +void irq_set_exclusive_handler(unsigned int num, void *handler) {} + +/* cut out the middleman and map the interrupt directly to the handler */ +void USB_IRQHandler(void) +{ + dcd_int_handler(0); +} + +/* map rp2040 USB driver call into CMSIS standard calls */ +void irq_set_enabled(unsigned int num, bool enabled) +{ + if (enabled) + NVIC_EnableIRQ(USB_IRQn); + else + NVIC_DisableIRQ(USB_IRQn); +} + +/* provide something basic to handle when the rp2040 USB driver gets upset */ + +__NO_RETURN static void bad_happened(void) +{ +#ifdef DEBUG + while (1) __BKPT(); +#else + NVIC_SystemReset(); +#endif +} + +void panic(const char *fmt, ...) { bad_happened(); } +void __assert(const char *__expression, const char *__filename, int __line) { bad_happened(); } diff --git a/pico-debug.hzp b/pico-debug.hzp new file mode 100644 index 0000000..950ef4c --- /dev/null +++ b/pico-debug.hzp @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pico/config_autogen.h b/pico/config_autogen.h new file mode 100644 index 0000000..cc3322b --- /dev/null +++ b/pico/config_autogen.h @@ -0,0 +1,7 @@ +#ifndef CONFIG_H +#define CONFIG_H + +#define bi_decl_if_func_used(_decl) ((void)0); + +#endif + diff --git a/pico/version.h b/pico/version.h new file mode 100644 index 0000000..cf2df68 --- /dev/null +++ b/pico/version.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// --------------------------------------- +// THIS FILE IS AUTOGENERATED; DO NOT EDIT +// --------------------------------------- + +#ifndef _PICO_VERSION_H +#define _PICO_VERSION_H + +#define PICO_SDK_VERSION_MAJOR 1 +#define PICO_SDK_VERSION_MINOR 0 +#define PICO_SDK_VERSION_REVISION 0 +#define PICO_SDK_VERSION_STRING "1.0.0" + +#endif diff --git a/picodebug_MemoryMap.xml b/picodebug_MemoryMap.xml new file mode 100644 index 0000000..0bd2cd1 --- /dev/null +++ b/picodebug_MemoryMap.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/picodebug_Startup.s b/picodebug_Startup.s new file mode 100644 index 0000000..987f2f0 --- /dev/null +++ b/picodebug_Startup.s @@ -0,0 +1,163 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Peter Lawrence + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* this code was tweaked specifically for pico-debug; it is *NOT* a generic crt implementation */ + +.macro ISR_HANDLER name= + .section .vectors, "ax" + .word \name +.endm + +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +.macro ISR_UNUSED name= + .section .vectors, "ax" + .word exit_handler +.endm + + .syntax unified + .global boot_entry + .extern main + .global exit + .weak exit + + .section .boot, "ax" + .thumb_func + +boot_entry: + /* disable flash cache (allowing XIP_SRAM access) */ + ldr r0, =0x14000000 + ldr r1, =0 + str r1, [r0] + + /* copy initialized memory sections en masse into final destinations */ + ldr r0, =__vectors_load_start__ + ldr r1, =__vectors_start__ + ldr r2, =__rodata_end__ + cmp r0, r1 + beq copy_finished + subs r2, r2, r1 + beq copy_finished +copy_loop: + ldrb r3, [r0] + adds r0, r0, #1 + strb r3, [r1] + adds r1, r1, #1 + subs r2, r2, #1 + bne copy_loop +copy_finished: + + ldr r1, =__vectors_start__ /* origin of where vector table now resides */ + ldr r0, =0xE000ED08 /* VTOR register */ + str r1, [r0] /* point VTOR to user app */ + ldr r0, [r1] /* load stack pointer from user app */ + msr msp, r0 + msr psp, r0 + ldr r0, [r1, #4] /* load reset address from user app */ + mov pc, r0 + + .section .vectors, "ax" + .code 16 + .global _vectors + .align 8 + +_vectors: + .word __stack_end__ + .word reset_handler +ISR_UNUSED NMI_Handler +ISR_UNUSED HardFault_Handler +ISR_UNUSED MemManage_Handler +ISR_UNUSED BusFault_Handler +ISR_UNUSED UsageFault_Handler +ISR_RESERVED +ISR_RESERVED +ISR_RESERVED +ISR_RESERVED +ISR_UNUSED SVC_Handler +ISR_UNUSED DebugMon_Handler +ISR_RESERVED +ISR_UNUSED PendSV_Handler +ISR_UNUSED SysTick_Handler +ISR_UNUSED TIMER0_IRQHandler +ISR_UNUSED TIMER1_IRQHandler +ISR_UNUSED TIMER2_IRQHandler +ISR_UNUSED TIMER3_IRQHandler +ISR_UNUSED PWM_IRQHandler +ISR_HANDLER USB_IRQHandler +ISR_UNUSED XIP_IRQHandler +ISR_UNUSED PIO0_0_IRQHandler +ISR_UNUSED PIO0_1_IRQHandler +ISR_UNUSED PIO1_0_IRQHandler +ISR_UNUSED PIO1_1_IRQHandler +ISR_UNUSED DMA0_IRQHandler +ISR_UNUSED DMA1_IRQHandler +ISR_UNUSED IO_IRQHandler +ISR_UNUSED QSPI_IRQHandler +ISR_UNUSED SIO0_IRQHandler +ISR_UNUSED SIO1_IRQHandler +ISR_UNUSED CLOCKS_Handler +ISR_UNUSED SPI0_Handler +ISR_UNUSED SPI1_IRQHandler +ISR_UNUSED UART0_IRQHandler +ISR_UNUSED UART1_Handler +ISR_UNUSED ADC_Handler +ISR_UNUSED I2C0_IRQHandler +ISR_UNUSED I2C1_IRQHandler +ISR_UNUSED RTC_IRQHandler + + .thumb_func +reset_handler: + /* zero-ize the bss */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + movs r2, #0 +bss_loop: + cmp r0, r1 + beq bss_finished + strb r2, [r0] + adds r0, r0, #1 + b bss_loop +bss_finished: + + /* Setup initial call frame */ + movs r0, #0 + mov lr, r0 + mov r12, sp + + /* jump to app entry point */ + ldr r2, =main + blx r2 + + .thumb_func +exit: + + /* handler if app returned or unexpected IRQ happened */ +exit_handler: + b exit_handler + + /* Setup attributes of stack section so that it doesn't take up room in the elf file */ + .section .stack, "wa", %nobits diff --git a/picodebug_placement.xml b/picodebug_placement.xml new file mode 100644 index 0000000..03d20ec --- /dev/null +++ b/picodebug_placement.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/ram_placement.xml b/ram_placement.xml new file mode 100644 index 0000000..a3ddb6b --- /dev/null +++ b/ram_placement.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/rp2040/hardware/address_mapped.h b/rp2040/hardware/address_mapped.h new file mode 100644 index 0000000..6645fbd --- /dev/null +++ b/rp2040/hardware/address_mapped.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_ADDRESS_MAPPED_H +#define _HARDWARE_ADDRESS_MAPPED_H + +#include "pico.h" +#include "hardware/regs/addressmap.h" + +/** \file address_mapped.h + * \defgroup hardware_base hardware_base + * + * Low-level types and (atomic) accessors for memory-mapped hardware registers + * + * `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included + * by default by all other hardware libraries. + * + * The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register. + * The register type names are formed by concatenating one from each of the 3 parts A, B, C + + * A | B | C | Meaning + * ------|---|---|-------- + * io_ | | | A Memory mapped IO register + *  |ro_| | read-only access + *  |rw_| | read-write access + *  |wo_| | write-only access (can't actually be enforced via C API) + *  | | 8| 8-bit wide access + *  | | 16| 16-bit wide access + *  | | 32| 32-bit wide access + * + * When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write + * 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`. + * + * RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within + * a hardware register so that concurrent access by two cores is always consistent with one atomic operation + * being performed first, followed by the second. + * + * See hw_set_bits(), hw_clear_bits() and hw_xor_bits() provide for atomic access via a pointer to a 32 bit register + * + * Additionally given a pointer to a structure representing a piece of hardware (e.g. `dma_hw_t *dma_hw` for the DMA controller), you can + * get an alias to the entire structure such that writing any member (register) within the structure is equivalent + * to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()... + * + * For example `hw_set_alias(dma_hw)->inte1 = 0x80;` will set bit 7 of the INTE1 register of the DMA controller, + * leaving the other bits unchanged. + */ + +#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch") +#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch") + +typedef volatile uint32_t io_rw_32; +typedef const volatile uint32_t io_ro_32; +typedef volatile uint32_t io_wo_32; +typedef volatile uint16_t io_rw_16; +typedef const volatile uint16_t io_ro_16; +typedef volatile uint16_t io_wo_16; +typedef volatile uint8_t io_rw_8; +typedef const volatile uint8_t io_ro_8; +typedef volatile uint8_t io_wo_8; + +typedef volatile uint8_t *const ioptr; +typedef ioptr const const_ioptr; + +// Untyped conversion alias pointer generation macros +#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr))) +#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr))) +#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr))) + +// Typed conversion alias pointer generation macros +#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p)) +#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p)) +#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p)) + +/*! \brief Atomically set the specified bits to 1 in a HW register + * \ingroup hardware_base + * + * \param addr Address of writable register + * \param mask Bit-mask specifying bits to set + */ +inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { + *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask; +} + +/*! \brief Atomically clear the specified bits to 0 in a HW register + * \ingroup hardware_base + * + * \param addr Address of writable register + * \param mask Bit-mask specifying bits to clear + */ +inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { + *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask; +} + +/*! \brief Atomically flip the specified bits in a HW register + * \ingroup hardware_base + * + * \param addr Address of writable register + * \param mask Bit-mask specifying bits to invert + */ +inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) { + *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; +} + +/*! \brief Set new values for a sub-set of the bits in a HW register + * \ingroup hardware_base + * + * Sets destination bits to values specified in \p values, if and only if corresponding bit in \p write_mask is set + * + * Note: this method allows safe concurrent modification of *different* bits of + * a register, but multiple concurrent access to the same bits is still unsafe. + * + * \param addr Address of writable register + * \param values Bits values + * \param write_mask Mask of bits to change + */ +inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) { + hw_xor_bits(addr, (*addr ^ values) & write_mask); +} + +#endif diff --git a/rp2040/hardware/platform_defs.h b/rp2040/hardware/platform_defs.h new file mode 100644 index 0000000..51c0272 --- /dev/null +++ b/rp2040/hardware/platform_defs.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLATFORM_DEFS_H +#define _HARDWARE_PLATFORM_DEFS_H + +// This header is included from C and assembler - only define macros + +#include "hardware/regs/addressmap.h" + +#define NUM_CORES 2u +#define NUM_DMA_CHANNELS 12u +#define NUM_IRQS 32u +#define NUM_PIOS 2u +#define NUM_PIO_STATE_MACHINES 4u +#define NUM_PWM_SLICES 8u +#define NUM_SPIN_LOCKS 32u +#define NUM_UARTS 2u +#define NUM_BANK0_GPIOS 30u + +#define PIO_INSTRUCTION_COUNT 32u + +#define XOSC_MHZ 12u + +// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link +#ifndef PICO_STACK_SIZE +#define PICO_STACK_SIZE 0x800u +#endif + +// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link +#ifndef PICO_HEAP_SIZE +#define PICO_HEAP_SIZE 0x800 +#endif + +// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime +#ifndef PICO_NO_RAM_VECTOR_TABLE +#define PICO_NO_RAM_VECTOR_TABLE 0 +#endif + +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024) +#endif + +#endif + diff --git a/rp2040/hardware/regs/adc.h b/rp2040/hardware/regs/adc.h new file mode 100644 index 0000000..82bb0f8 --- /dev/null +++ b/rp2040/hardware/regs/adc.h @@ -0,0 +1,314 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ADC +// Version : 2 +// Bus type : apb +// Description : Control and data interface to SAR ADC +// ============================================================================= +#ifndef HARDWARE_REGS_ADC_DEFINED +#define HARDWARE_REGS_ADC_DEFINED +// ============================================================================= +// Register : ADC_CS +// Description : ADC Control and Status +#define ADC_CS_OFFSET 0x00000000 +#define ADC_CS_BITS 0x001f770f +#define ADC_CS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_CS_RROBIN +// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to +// disable. +// Otherwise, the ADC will cycle through each enabled channel in a +// round-robin fashion. +// The first channel to be sampled will be the one currently +// indicated by AINSEL. +// AINSEL will be updated after each conversion with the +// newly-selected channel. +#define ADC_CS_RROBIN_RESET 0x00 +#define ADC_CS_RROBIN_BITS 0x001f0000 +#define ADC_CS_RROBIN_MSB 20 +#define ADC_CS_RROBIN_LSB 16 +#define ADC_CS_RROBIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_AINSEL +// Description : Select analog mux input. Updated automatically in round-robin +// mode. +#define ADC_CS_AINSEL_RESET 0x0 +#define ADC_CS_AINSEL_BITS 0x00007000 +#define ADC_CS_AINSEL_MSB 14 +#define ADC_CS_AINSEL_LSB 12 +#define ADC_CS_AINSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR_STICKY +// Description : Some past ADC conversion encountered an error. Write 1 to +// clear. +#define ADC_CS_ERR_STICKY_RESET 0x0 +#define ADC_CS_ERR_STICKY_BITS 0x00000400 +#define ADC_CS_ERR_STICKY_MSB 10 +#define ADC_CS_ERR_STICKY_LSB 10 +#define ADC_CS_ERR_STICKY_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR +// Description : The most recent ADC conversion encountered an error; result is +// undefined or noisy. +#define ADC_CS_ERR_RESET 0x0 +#define ADC_CS_ERR_BITS 0x00000200 +#define ADC_CS_ERR_MSB 9 +#define ADC_CS_ERR_LSB 9 +#define ADC_CS_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_READY +// Description : 1 if the ADC is ready to start a new conversion. Implies any +// previous conversion has completed. +// 0 whilst conversion in progress. +#define ADC_CS_READY_RESET 0x0 +#define ADC_CS_READY_BITS 0x00000100 +#define ADC_CS_READY_MSB 8 +#define ADC_CS_READY_LSB 8 +#define ADC_CS_READY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_MANY +// Description : Continuously perform conversions whilst this bit is 1. A new +// conversion will start immediately after the previous finishes. +#define ADC_CS_START_MANY_RESET 0x0 +#define ADC_CS_START_MANY_BITS 0x00000008 +#define ADC_CS_START_MANY_MSB 3 +#define ADC_CS_START_MANY_LSB 3 +#define ADC_CS_START_MANY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_ONCE +// Description : Start a single conversion. Self-clearing. Ignored if start_many +// is asserted. +#define ADC_CS_START_ONCE_RESET 0x0 +#define ADC_CS_START_ONCE_BITS 0x00000004 +#define ADC_CS_START_ONCE_MSB 2 +#define ADC_CS_START_ONCE_LSB 2 +#define ADC_CS_START_ONCE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_TS_EN +// Description : Power on temperature sensor. 1 - enabled. 0 - disabled. +#define ADC_CS_TS_EN_RESET 0x0 +#define ADC_CS_TS_EN_BITS 0x00000002 +#define ADC_CS_TS_EN_MSB 1 +#define ADC_CS_TS_EN_LSB 1 +#define ADC_CS_TS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_EN +// Description : Power on ADC and enable its clock. +// 1 - enabled. 0 - disabled. +#define ADC_CS_EN_RESET 0x0 +#define ADC_CS_EN_BITS 0x00000001 +#define ADC_CS_EN_MSB 0 +#define ADC_CS_EN_LSB 0 +#define ADC_CS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_RESULT +// Description : Result of most recent ADC conversion +#define ADC_RESULT_OFFSET 0x00000004 +#define ADC_RESULT_BITS 0x00000fff +#define ADC_RESULT_RESET 0x00000000 +#define ADC_RESULT_MSB 11 +#define ADC_RESULT_LSB 0 +#define ADC_RESULT_ACCESS "RO" +// ============================================================================= +// Register : ADC_FCS +// Description : FIFO control and status +#define ADC_FCS_OFFSET 0x00000008 +#define ADC_FCS_BITS 0x0f0f0f0f +#define ADC_FCS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_THRESH +// Description : DREQ/IRQ asserted when level >= threshold +#define ADC_FCS_THRESH_RESET 0x0 +#define ADC_FCS_THRESH_BITS 0x0f000000 +#define ADC_FCS_THRESH_MSB 27 +#define ADC_FCS_THRESH_LSB 24 +#define ADC_FCS_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_LEVEL +// Description : The number of conversion results currently waiting in the FIFO +#define ADC_FCS_LEVEL_RESET 0x0 +#define ADC_FCS_LEVEL_BITS 0x000f0000 +#define ADC_FCS_LEVEL_MSB 19 +#define ADC_FCS_LEVEL_LSB 16 +#define ADC_FCS_LEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_OVER +// Description : 1 if the FIFO has been overflowed. Write 1 to clear. +#define ADC_FCS_OVER_RESET 0x0 +#define ADC_FCS_OVER_BITS 0x00000800 +#define ADC_FCS_OVER_MSB 11 +#define ADC_FCS_OVER_LSB 11 +#define ADC_FCS_OVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_UNDER +// Description : 1 if the FIFO has been underflowed. Write 1 to clear. +#define ADC_FCS_UNDER_RESET 0x0 +#define ADC_FCS_UNDER_BITS 0x00000400 +#define ADC_FCS_UNDER_MSB 10 +#define ADC_FCS_UNDER_LSB 10 +#define ADC_FCS_UNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_FULL +// Description : None +#define ADC_FCS_FULL_RESET 0x0 +#define ADC_FCS_FULL_BITS 0x00000200 +#define ADC_FCS_FULL_MSB 9 +#define ADC_FCS_FULL_LSB 9 +#define ADC_FCS_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EMPTY +// Description : None +#define ADC_FCS_EMPTY_RESET 0x0 +#define ADC_FCS_EMPTY_BITS 0x00000100 +#define ADC_FCS_EMPTY_MSB 8 +#define ADC_FCS_EMPTY_LSB 8 +#define ADC_FCS_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_DREQ_EN +// Description : If 1: assert DMA requests when FIFO contains data +#define ADC_FCS_DREQ_EN_RESET 0x0 +#define ADC_FCS_DREQ_EN_BITS 0x00000008 +#define ADC_FCS_DREQ_EN_MSB 3 +#define ADC_FCS_DREQ_EN_LSB 3 +#define ADC_FCS_DREQ_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_ERR +// Description : If 1: conversion error bit appears in the FIFO alongside the +// result +#define ADC_FCS_ERR_RESET 0x0 +#define ADC_FCS_ERR_BITS 0x00000004 +#define ADC_FCS_ERR_MSB 2 +#define ADC_FCS_ERR_LSB 2 +#define ADC_FCS_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_SHIFT +// Description : If 1: FIFO results are right-shifted to be one byte in size. +// Enables DMA to byte buffers. +#define ADC_FCS_SHIFT_RESET 0x0 +#define ADC_FCS_SHIFT_BITS 0x00000002 +#define ADC_FCS_SHIFT_MSB 1 +#define ADC_FCS_SHIFT_LSB 1 +#define ADC_FCS_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EN +// Description : If 1: write result to the FIFO after each conversion. +#define ADC_FCS_EN_RESET 0x0 +#define ADC_FCS_EN_BITS 0x00000001 +#define ADC_FCS_EN_MSB 0 +#define ADC_FCS_EN_LSB 0 +#define ADC_FCS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_FIFO +// Description : Conversion result FIFO +#define ADC_FIFO_OFFSET 0x0000000c +#define ADC_FIFO_BITS 0x00008fff +#define ADC_FIFO_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_ERR +// Description : 1 if this particular sample experienced a conversion error. +// Remains in the same location if the sample is shifted. +#define ADC_FIFO_ERR_RESET "-" +#define ADC_FIFO_ERR_BITS 0x00008000 +#define ADC_FIFO_ERR_MSB 15 +#define ADC_FIFO_ERR_LSB 15 +#define ADC_FIFO_ERR_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_VAL +// Description : None +#define ADC_FIFO_VAL_RESET "-" +#define ADC_FIFO_VAL_BITS 0x00000fff +#define ADC_FIFO_VAL_MSB 11 +#define ADC_FIFO_VAL_LSB 0 +#define ADC_FIFO_VAL_ACCESS "RF" +// ============================================================================= +// Register : ADC_DIV +// Description : Clock divider. If non-zero, CS_START_MANY will start +// conversions +// at regular intervals rather than back-to-back. +// The divider is reset when either of these fields are written. +// Total period is 1 + INT + FRAC / 256 +#define ADC_DIV_OFFSET 0x00000010 +#define ADC_DIV_BITS 0x00ffffff +#define ADC_DIV_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_INT +// Description : Integer part of clock divisor. +#define ADC_DIV_INT_RESET 0x0000 +#define ADC_DIV_INT_BITS 0x00ffff00 +#define ADC_DIV_INT_MSB 23 +#define ADC_DIV_INT_LSB 8 +#define ADC_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_FRAC +// Description : Fractional part of clock divisor. First-order delta-sigma. +#define ADC_DIV_FRAC_RESET 0x00 +#define ADC_DIV_FRAC_BITS 0x000000ff +#define ADC_DIV_FRAC_MSB 7 +#define ADC_DIV_FRAC_LSB 0 +#define ADC_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTR +// Description : Raw Interrupts +#define ADC_INTR_OFFSET 0x00000014 +#define ADC_INTR_BITS 0x00000001 +#define ADC_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTR_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTR_FIFO_RESET 0x0 +#define ADC_INTR_FIFO_BITS 0x00000001 +#define ADC_INTR_FIFO_MSB 0 +#define ADC_INTR_FIFO_LSB 0 +#define ADC_INTR_FIFO_ACCESS "RO" +// ============================================================================= +// Register : ADC_INTE +// Description : Interrupt Enable +#define ADC_INTE_OFFSET 0x00000018 +#define ADC_INTE_BITS 0x00000001 +#define ADC_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTE_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTE_FIFO_RESET 0x0 +#define ADC_INTE_FIFO_BITS 0x00000001 +#define ADC_INTE_FIFO_MSB 0 +#define ADC_INTE_FIFO_LSB 0 +#define ADC_INTE_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTF +// Description : Interrupt Force +#define ADC_INTF_OFFSET 0x0000001c +#define ADC_INTF_BITS 0x00000001 +#define ADC_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTF_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTF_FIFO_RESET 0x0 +#define ADC_INTF_FIFO_BITS 0x00000001 +#define ADC_INTF_FIFO_MSB 0 +#define ADC_INTF_FIFO_LSB 0 +#define ADC_INTF_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTS +// Description : Interrupt status after masking & forcing +#define ADC_INTS_OFFSET 0x00000020 +#define ADC_INTS_BITS 0x00000001 +#define ADC_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ADC_INTS_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTS_FIFO_RESET 0x0 +#define ADC_INTS_FIFO_BITS 0x00000001 +#define ADC_INTS_FIFO_MSB 0 +#define ADC_INTS_FIFO_LSB 0 +#define ADC_INTS_FIFO_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_ADC_DEFINED diff --git a/rp2040/hardware/regs/addressmap.h b/rp2040/hardware/regs/addressmap.h new file mode 100644 index 0000000..39451ac --- /dev/null +++ b/rp2040/hardware/regs/addressmap.h @@ -0,0 +1,72 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _ADDRESSMAP_H_ +#define _ADDRESSMAP_H_ + +// Register address offsets for atomic RMW aliases +#define REG_ALIAS_RW_BITS (0x0u << 12u) +#define REG_ALIAS_XOR_BITS (0x1u << 12u) +#define REG_ALIAS_SET_BITS (0x2u << 12u) +#define REG_ALIAS_CLR_BITS (0x3u << 12u) + +#define ROM_BASE 0x00000000 +#define XIP_BASE 0x10000000 +#define XIP_MAIN_BASE 0x10000000 +#define XIP_NOALLOC_BASE 0x11000000 +#define XIP_NOCACHE_BASE 0x12000000 +#define XIP_NOCACHE_NOALLOC_BASE 0x13000000 +#define XIP_CTRL_BASE 0x14000000 +#define XIP_SRAM_BASE 0x15000000 +#define XIP_SRAM_END 0x15004000 +#define XIP_SSI_BASE 0x18000000 +#define SRAM_BASE 0x20000000 +#define SRAM_STRIPED_BASE 0x20000000 +#define SRAM_STRIPED_END 0x20040000 +#define SRAM4_BASE 0x20040000 +#define SRAM5_BASE 0x20041000 +#define SRAM_END 0x20042000 +#define SRAM0_BASE 0x21000000 +#define SRAM1_BASE 0x21010000 +#define SRAM2_BASE 0x21020000 +#define SRAM3_BASE 0x21030000 +#define SYSINFO_BASE 0x40000000 +#define SYSCFG_BASE 0x40004000 +#define CLOCKS_BASE 0x40008000 +#define RESETS_BASE 0x4000c000 +#define PSM_BASE 0x40010000 +#define IO_BANK0_BASE 0x40014000 +#define IO_QSPI_BASE 0x40018000 +#define PADS_BANK0_BASE 0x4001c000 +#define PADS_QSPI_BASE 0x40020000 +#define XOSC_BASE 0x40024000 +#define PLL_SYS_BASE 0x40028000 +#define PLL_USB_BASE 0x4002c000 +#define BUSCTRL_BASE 0x40030000 +#define UART0_BASE 0x40034000 +#define UART1_BASE 0x40038000 +#define SPI0_BASE 0x4003c000 +#define SPI1_BASE 0x40040000 +#define I2C0_BASE 0x40044000 +#define I2C1_BASE 0x40048000 +#define ADC_BASE 0x4004c000 +#define PWM_BASE 0x40050000 +#define TIMER_BASE 0x40054000 +#define WATCHDOG_BASE 0x40058000 +#define RTC_BASE 0x4005c000 +#define ROSC_BASE 0x40060000 +#define VREG_AND_CHIP_RESET_BASE 0x40064000 +#define TBMAN_BASE 0x4006c000 +#define DMA_BASE 0x50000000 +#define USBCTRL_DPRAM_BASE 0x50100000 +#define USBCTRL_BASE 0x50100000 +#define USBCTRL_REGS_BASE 0x50110000 +#define PIO0_BASE 0x50200000 +#define PIO1_BASE 0x50300000 +#define XIP_AUX_BASE 0x50400000 +#define SIO_BASE 0xd0000000 +#define PPB_BASE 0xe0000000 + +#endif // _ADDRESSMAP_H_ diff --git a/rp2040/hardware/regs/busctrl.h b/rp2040/hardware/regs/busctrl.h new file mode 100644 index 0000000..6c02aee --- /dev/null +++ b/rp2040/hardware/regs/busctrl.h @@ -0,0 +1,160 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : BUSCTRL +// Version : 1 +// Bus type : apb +// Description : Register block for busfabric control signals and performance +// counters +// ============================================================================= +#ifndef HARDWARE_REGS_BUSCTRL_DEFINED +#define HARDWARE_REGS_BUSCTRL_DEFINED +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY +// Description : Set the priority of each master for bus arbitration. +#define BUSCTRL_BUS_PRIORITY_OFFSET 0x00000000 +#define BUSCTRL_BUS_PRIORITY_BITS 0x00001111 +#define BUSCTRL_BUS_PRIORITY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_W +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS 0x00001000 +#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB 12 +#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB 12 +#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_R +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS 0x00000100 +#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB 8 +#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB 8 +#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC1 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC1_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_PROC1_BITS 0x00000010 +#define BUSCTRL_BUS_PRIORITY_PROC1_MSB 4 +#define BUSCTRL_BUS_PRIORITY_PROC1_LSB 4 +#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC0 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC0_RESET 0x0 +#define BUSCTRL_BUS_PRIORITY_PROC0_BITS 0x00000001 +#define BUSCTRL_BUS_PRIORITY_PROC0_MSB 0 +#define BUSCTRL_BUS_PRIORITY_PROC0_LSB 0 +#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY_ACK +// Description : Bus priority acknowledge +// Goes to 1 once all arbiters have registered the new global +// priority levels. +// Arbiters update their local priority when servicing a new +// nonsequential access. +// In normal circumstances this will happen almost immediately. +#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET 0x00000004 +#define BUSCTRL_BUS_PRIORITY_ACK_BITS 0x00000001 +#define BUSCTRL_BUS_PRIORITY_ACK_RESET 0x00000000 +#define BUSCTRL_BUS_PRIORITY_ACK_MSB 0 +#define BUSCTRL_BUS_PRIORITY_ACK_LSB 0 +#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" +// ============================================================================= +// Register : BUSCTRL_PERFCTR0 +// Description : Bus fabric performance counter 0 +// Busfabric saturating performance counter 0 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL0 +#define BUSCTRL_PERFCTR0_OFFSET 0x00000008 +#define BUSCTRL_PERFCTR0_BITS 0x00ffffff +#define BUSCTRL_PERFCTR0_RESET 0x00000000 +#define BUSCTRL_PERFCTR0_MSB 23 +#define BUSCTRL_PERFCTR0_LSB 0 +#define BUSCTRL_PERFCTR0_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL0 +// Description : Bus fabric performance event select for PERFCTR0 +// Select a performance event for PERFCTR0 +#define BUSCTRL_PERFSEL0_OFFSET 0x0000000c +#define BUSCTRL_PERFSEL0_BITS 0x0000001f +#define BUSCTRL_PERFSEL0_RESET 0x0000001f +#define BUSCTRL_PERFSEL0_MSB 4 +#define BUSCTRL_PERFSEL0_LSB 0 +#define BUSCTRL_PERFSEL0_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR1 +// Description : Bus fabric performance counter 1 +// Busfabric saturating performance counter 1 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL1 +#define BUSCTRL_PERFCTR1_OFFSET 0x00000010 +#define BUSCTRL_PERFCTR1_BITS 0x00ffffff +#define BUSCTRL_PERFCTR1_RESET 0x00000000 +#define BUSCTRL_PERFCTR1_MSB 23 +#define BUSCTRL_PERFCTR1_LSB 0 +#define BUSCTRL_PERFCTR1_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL1 +// Description : Bus fabric performance event select for PERFCTR1 +// Select a performance event for PERFCTR1 +#define BUSCTRL_PERFSEL1_OFFSET 0x00000014 +#define BUSCTRL_PERFSEL1_BITS 0x0000001f +#define BUSCTRL_PERFSEL1_RESET 0x0000001f +#define BUSCTRL_PERFSEL1_MSB 4 +#define BUSCTRL_PERFSEL1_LSB 0 +#define BUSCTRL_PERFSEL1_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR2 +// Description : Bus fabric performance counter 2 +// Busfabric saturating performance counter 2 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL2 +#define BUSCTRL_PERFCTR2_OFFSET 0x00000018 +#define BUSCTRL_PERFCTR2_BITS 0x00ffffff +#define BUSCTRL_PERFCTR2_RESET 0x00000000 +#define BUSCTRL_PERFCTR2_MSB 23 +#define BUSCTRL_PERFCTR2_LSB 0 +#define BUSCTRL_PERFCTR2_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL2 +// Description : Bus fabric performance event select for PERFCTR2 +// Select a performance event for PERFCTR2 +#define BUSCTRL_PERFSEL2_OFFSET 0x0000001c +#define BUSCTRL_PERFSEL2_BITS 0x0000001f +#define BUSCTRL_PERFSEL2_RESET 0x0000001f +#define BUSCTRL_PERFSEL2_MSB 4 +#define BUSCTRL_PERFSEL2_LSB 0 +#define BUSCTRL_PERFSEL2_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR3 +// Description : Bus fabric performance counter 3 +// Busfabric saturating performance counter 3 +// Count some event signal from the busfabric arbiters. +// Write any value to clear. Select an event to count using +// PERFSEL3 +#define BUSCTRL_PERFCTR3_OFFSET 0x00000020 +#define BUSCTRL_PERFCTR3_BITS 0x00ffffff +#define BUSCTRL_PERFCTR3_RESET 0x00000000 +#define BUSCTRL_PERFCTR3_MSB 23 +#define BUSCTRL_PERFCTR3_LSB 0 +#define BUSCTRL_PERFCTR3_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL3 +// Description : Bus fabric performance event select for PERFCTR3 +// Select a performance event for PERFCTR3 +#define BUSCTRL_PERFSEL3_OFFSET 0x00000024 +#define BUSCTRL_PERFSEL3_BITS 0x0000001f +#define BUSCTRL_PERFSEL3_RESET 0x0000001f +#define BUSCTRL_PERFSEL3_MSB 4 +#define BUSCTRL_PERFSEL3_LSB 0 +#define BUSCTRL_PERFSEL3_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_BUSCTRL_DEFINED diff --git a/rp2040/hardware/regs/clocks.h b/rp2040/hardware/regs/clocks.h new file mode 100644 index 0000000..1b44490 --- /dev/null +++ b/rp2040/hardware/regs/clocks.h @@ -0,0 +1,2359 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : CLOCKS +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_CLOCKS_DEFINED +#define HARDWARE_REGS_CLOCKS_DEFINED +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET 0x00000000 +#define CLOCKS_CLK_GPOUT0_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT0_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT0_DIV_OFFSET 0x00000004 +#define CLOCKS_CLK_GPOUT0_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT0_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET 0x00000008 +#define CLOCKS_CLK_GPOUT0_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT0_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT0_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT0_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET 0x0000000c +#define CLOCKS_CLK_GPOUT1_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT1_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x4 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT1_DIV_OFFSET 0x00000010 +#define CLOCKS_CLK_GPOUT1_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT1_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET 0x00000014 +#define CLOCKS_CLK_GPOUT1_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT1_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT1_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT1_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET 0x00000018 +#define CLOCKS_CLK_GPOUT2_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT2_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc_ph +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT2_DIV_OFFSET 0x0000001c +#define CLOCKS_CLK_GPOUT2_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT2_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET 0x00000020 +#define CLOCKS_CLK_GPOUT2_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT2_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT2_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT2_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET 0x00000024 +#define CLOCKS_CLK_GPOUT3_CTRL_BITS 0x00131de0 +#define CLOCKS_CLK_GPOUT3_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS 0x00001000 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB 12 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB 12 +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> rosc_clksrc_ph +// 0x5 -> xosc_clksrc +// 0x6 -> clk_sys +// 0x7 -> clk_usb +// 0x8 -> clk_adc +// 0x9 -> clk_rtc +// 0xa -> clk_ref +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS 0x000001e0 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB 8 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x3 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x4 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x5 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS 0x6 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB 0x7 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC 0x8 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC 0x9 +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF 0xa +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT3_DIV_OFFSET 0x00000028 +#define CLOCKS_CLK_GPOUT3_DIV_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT3_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB 31 +#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB 8 +#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET 0x0000002c +#define CLOCKS_CLK_GPOUT3_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_GPOUT3_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_GPOUT3_SELECTED_MSB 31 +#define CLOCKS_CLK_GPOUT3_SELECTED_LSB 0 +#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_REF_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_REF_CTRL_OFFSET 0x00000030 +#define CLOCKS_CLK_REF_CTRL_BITS 0x00000063 +#define CLOCKS_CLK_REF_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS 0x00000060 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB 6 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x1 +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x2 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed +// on-the-fly +// 0x0 -> rosc_clksrc_ph +// 0x1 -> clksrc_clk_ref_aux +// 0x2 -> xosc_clksrc +#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" +#define CLOCKS_CLK_REF_CTRL_SRC_BITS 0x00000003 +#define CLOCKS_CLK_REF_CTRL_SRC_MSB 1 +#define CLOCKS_CLK_REF_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH 0x0 +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX 0x1 +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC 0x2 +// ============================================================================= +// Register : CLOCKS_CLK_REF_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_REF_DIV_OFFSET 0x00000034 +#define CLOCKS_CLK_REF_DIV_BITS 0x00000300 +#define CLOCKS_CLK_REF_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_REF_DIV_INT_RESET 0x1 +#define CLOCKS_CLK_REF_DIV_INT_BITS 0x00000300 +#define CLOCKS_CLK_REF_DIV_INT_MSB 9 +#define CLOCKS_CLK_REF_DIV_INT_LSB 8 +#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_REF_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_REF_SELECTED_OFFSET 0x00000038 +#define CLOCKS_CLK_REF_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_REF_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_REF_SELECTED_MSB 31 +#define CLOCKS_CLK_REF_SELECTED_LSB 0 +#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_SYS_CTRL_OFFSET 0x0000003c +#define CLOCKS_CLK_SYS_CTRL_BITS 0x000000e1 +#define CLOCKS_CLK_SYS_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_pll_usb +// 0x2 -> rosc_clksrc +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x0 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x1 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC 0x2 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed +// on-the-fly +// 0x0 -> clk_ref +// 0x1 -> clksrc_clk_sys_aux +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET 0x0 +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS 0x00000001 +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB 0 +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB 0 +#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF 0x0 +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX 0x1 +// ============================================================================= +// Register : CLOCKS_CLK_SYS_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_SYS_DIV_OFFSET 0x00000040 +#define CLOCKS_CLK_SYS_DIV_BITS 0xffffffff +#define CLOCKS_CLK_SYS_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_SYS_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_SYS_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_SYS_DIV_INT_MSB 31 +#define CLOCKS_CLK_SYS_DIV_INT_LSB 8 +#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_SYS_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_SYS_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_SYS_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_SYS_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_SYS_SELECTED_OFFSET 0x00000044 +#define CLOCKS_CLK_SYS_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_SYS_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_SYS_SELECTED_MSB 31 +#define CLOCKS_CLK_SYS_SELECTED_LSB 0 +#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_PERI_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_PERI_CTRL_OFFSET 0x00000048 +#define CLOCKS_CLK_PERI_CTRL_BITS 0x00000ce0 +#define CLOCKS_CLK_PERI_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_PERI_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_PERI_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_PERI_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_PERI_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clk_sys +// 0x1 -> clksrc_pll_sys +// 0x2 -> clksrc_pll_usb +// 0x3 -> rosc_clksrc_ph +// 0x4 -> xosc_clksrc +// 0x5 -> clksrc_gpin0 +// 0x6 -> clksrc_gpin1 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS 0x0 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x2 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x3 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x4 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x5 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x6 +// ============================================================================= +// Register : CLOCKS_CLK_PERI_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_PERI_SELECTED_OFFSET 0x00000050 +#define CLOCKS_CLK_PERI_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_PERI_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_PERI_SELECTED_MSB 31 +#define CLOCKS_CLK_PERI_SELECTED_LSB 0 +#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_USB_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_USB_CTRL_OFFSET 0x00000054 +#define CLOCKS_CLK_USB_CTRL_BITS 0x00130ce0 +#define CLOCKS_CLK_USB_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_USB_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_USB_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_USB_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_USB_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_USB_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_USB_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ============================================================================= +// Register : CLOCKS_CLK_USB_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_USB_DIV_OFFSET 0x00000058 +#define CLOCKS_CLK_USB_DIV_BITS 0x00000300 +#define CLOCKS_CLK_USB_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_USB_DIV_INT_RESET 0x1 +#define CLOCKS_CLK_USB_DIV_INT_BITS 0x00000300 +#define CLOCKS_CLK_USB_DIV_INT_MSB 9 +#define CLOCKS_CLK_USB_DIV_INT_LSB 8 +#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_USB_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_USB_SELECTED_OFFSET 0x0000005c +#define CLOCKS_CLK_USB_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_USB_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_USB_SELECTED_MSB 31 +#define CLOCKS_CLK_USB_SELECTED_LSB 0 +#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_ADC_CTRL_OFFSET 0x00000060 +#define CLOCKS_CLK_ADC_CTRL_BITS 0x00130ce0 +#define CLOCKS_CLK_ADC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_ADC_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_ADC_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_ADC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ============================================================================= +// Register : CLOCKS_CLK_ADC_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_ADC_DIV_OFFSET 0x00000064 +#define CLOCKS_CLK_ADC_DIV_BITS 0x00000300 +#define CLOCKS_CLK_ADC_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_ADC_DIV_INT_RESET 0x1 +#define CLOCKS_CLK_ADC_DIV_INT_BITS 0x00000300 +#define CLOCKS_CLK_ADC_DIV_INT_MSB 9 +#define CLOCKS_CLK_ADC_DIV_INT_LSB 8 +#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_ADC_SELECTED_OFFSET 0x00000068 +#define CLOCKS_CLK_ADC_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_ADC_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_ADC_SELECTED_MSB 31 +#define CLOCKS_CLK_ADC_SELECTED_LSB 0 +#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_RTC_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_RTC_CTRL_OFFSET 0x0000006c +#define CLOCKS_CLK_RTC_CTRL_BITS 0x00130ce0 +#define CLOCKS_CLK_RTC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS 0x00100000 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB 20 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB 20 +#define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS 0x00030000 +#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB 17 +#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB 16 +#define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS 0x00000800 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB 11 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB 11 +#define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_KILL +// Description : Asynchronously kills the clock generator +#define CLOCKS_CLK_RTC_CTRL_KILL_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_KILL_BITS 0x00000400 +#define CLOCKS_CLK_RTC_CTRL_KILL_MSB 10 +#define CLOCKS_CLK_RTC_CTRL_KILL_LSB 10 +#define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET 0x0 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS 0x000000e0 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB 7 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB 5 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB 0x0 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS 0x1 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH 0x2 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC 0x3 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 0x4 +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 0x5 +// ============================================================================= +// Register : CLOCKS_CLK_RTC_DIV +// Description : Clock divisor, can be changed on-the-fly +#define CLOCKS_CLK_RTC_DIV_OFFSET 0x00000070 +#define CLOCKS_CLK_RTC_DIV_BITS 0xffffffff +#define CLOCKS_CLK_RTC_DIV_RESET 0x00000100 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_DIV_INT +// Description : Integer component of the divisor, 0 -> divide by 2^16 +#define CLOCKS_CLK_RTC_DIV_INT_RESET 0x000001 +#define CLOCKS_CLK_RTC_DIV_INT_BITS 0xffffff00 +#define CLOCKS_CLK_RTC_DIV_INT_MSB 31 +#define CLOCKS_CLK_RTC_DIV_INT_LSB 8 +#define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_RTC_DIV_FRAC +// Description : Fractional component of the divisor +#define CLOCKS_CLK_RTC_DIV_FRAC_RESET 0x00 +#define CLOCKS_CLK_RTC_DIV_FRAC_BITS 0x000000ff +#define CLOCKS_CLK_RTC_DIV_FRAC_MSB 7 +#define CLOCKS_CLK_RTC_DIV_FRAC_LSB 0 +#define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_RTC_SELECTED +// Description : Indicates which src is currently selected (one-hot) +#define CLOCKS_CLK_RTC_SELECTED_OFFSET 0x00000074 +#define CLOCKS_CLK_RTC_SELECTED_BITS 0xffffffff +#define CLOCKS_CLK_RTC_SELECTED_RESET 0x00000001 +#define CLOCKS_CLK_RTC_SELECTED_MSB 31 +#define CLOCKS_CLK_RTC_SELECTED_LSB 0 +#define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_CTRL +// Description : None +#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET 0x00000078 +#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS 0x000111ff +#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET 0x000000ff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR +// Description : For clearing the resus after the fault that triggered it has +// been corrected +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS 0x00010000 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB 16 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB 16 +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE +// Description : Force a resus, for test purposes only +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS 0x00001000 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB 12 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB 12 +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE +// Description : Enable resus +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS 0x00000100 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB 8 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB 8 +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT +// Description : This is expressed as a number of clk_ref cycles +// and must be >= 2x clk_ref_freq/min_clk_tst_freq +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET 0xff +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS 0x000000ff +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB 7 +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_STATUS +// Description : None +#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET 0x0000007c +#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS 0x00000001 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED +// Description : Clock has been resuscitated, correct the error then send +// ctrl_clear=1 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET 0x0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS 0x00000001 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB 0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB 0 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_REF_KHZ +// Description : Reference clock frequency in kHz +#define CLOCKS_FC0_REF_KHZ_OFFSET 0x00000080 +#define CLOCKS_FC0_REF_KHZ_BITS 0x000fffff +#define CLOCKS_FC0_REF_KHZ_RESET 0x00000000 +#define CLOCKS_FC0_REF_KHZ_MSB 19 +#define CLOCKS_FC0_REF_KHZ_LSB 0 +#define CLOCKS_FC0_REF_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MIN_KHZ +// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if +// you are not using the pass/fail flags +#define CLOCKS_FC0_MIN_KHZ_OFFSET 0x00000084 +#define CLOCKS_FC0_MIN_KHZ_BITS 0x01ffffff +#define CLOCKS_FC0_MIN_KHZ_RESET 0x00000000 +#define CLOCKS_FC0_MIN_KHZ_MSB 24 +#define CLOCKS_FC0_MIN_KHZ_LSB 0 +#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MAX_KHZ +// Description : Maximum pass frequency in kHz. This is optional. Set to +// 0x1ffffff if you are not using the pass/fail flags +#define CLOCKS_FC0_MAX_KHZ_OFFSET 0x00000088 +#define CLOCKS_FC0_MAX_KHZ_BITS 0x01ffffff +#define CLOCKS_FC0_MAX_KHZ_RESET 0x01ffffff +#define CLOCKS_FC0_MAX_KHZ_MSB 24 +#define CLOCKS_FC0_MAX_KHZ_LSB 0 +#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_DELAY +// Description : Delays the start of frequency counting to allow the mux to +// settle +// Delay is measured in multiples of the reference clock period +#define CLOCKS_FC0_DELAY_OFFSET 0x0000008c +#define CLOCKS_FC0_DELAY_BITS 0x00000007 +#define CLOCKS_FC0_DELAY_RESET 0x00000001 +#define CLOCKS_FC0_DELAY_MSB 2 +#define CLOCKS_FC0_DELAY_LSB 0 +#define CLOCKS_FC0_DELAY_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_INTERVAL +// Description : The test interval is 0.98us * 2**interval, but let's call it +// 1us * 2**interval +// The default gives a test interval of 250us +#define CLOCKS_FC0_INTERVAL_OFFSET 0x00000090 +#define CLOCKS_FC0_INTERVAL_BITS 0x0000000f +#define CLOCKS_FC0_INTERVAL_RESET 0x00000008 +#define CLOCKS_FC0_INTERVAL_MSB 3 +#define CLOCKS_FC0_INTERVAL_LSB 0 +#define CLOCKS_FC0_INTERVAL_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_SRC +// Description : Clock sent to frequency counter, set to 0 when not required +// Writing to this register initiates the frequency count +// 0x00 -> NULL +// 0x01 -> pll_sys_clksrc_primary +// 0x02 -> pll_usb_clksrc_primary +// 0x03 -> rosc_clksrc +// 0x04 -> rosc_clksrc_ph +// 0x05 -> xosc_clksrc +// 0x06 -> clksrc_gpin0 +// 0x07 -> clksrc_gpin1 +// 0x08 -> clk_ref +// 0x09 -> clk_sys +// 0x0a -> clk_peri +// 0x0b -> clk_usb +// 0x0c -> clk_adc +// 0x0d -> clk_rtc +#define CLOCKS_FC0_SRC_OFFSET 0x00000094 +#define CLOCKS_FC0_SRC_BITS 0x000000ff +#define CLOCKS_FC0_SRC_RESET 0x00000000 +#define CLOCKS_FC0_SRC_MSB 7 +#define CLOCKS_FC0_SRC_LSB 0 +#define CLOCKS_FC0_SRC_ACCESS "RW" +#define CLOCKS_FC0_SRC_VALUE_NULL 0x00 +#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY 0x01 +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY 0x02 +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC 0x03 +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH 0x04 +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC 0x05 +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 0x06 +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 0x07 +#define CLOCKS_FC0_SRC_VALUE_CLK_REF 0x08 +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS 0x09 +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI 0x0a +#define CLOCKS_FC0_SRC_VALUE_CLK_USB 0x0b +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC 0x0c +#define CLOCKS_FC0_SRC_VALUE_CLK_RTC 0x0d +// ============================================================================= +// Register : CLOCKS_FC0_STATUS +// Description : Frequency counter status +#define CLOCKS_FC0_STATUS_OFFSET 0x00000098 +#define CLOCKS_FC0_STATUS_BITS 0x11111111 +#define CLOCKS_FC0_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DIED +// Description : Test clock stopped during test +#define CLOCKS_FC0_STATUS_DIED_RESET 0x0 +#define CLOCKS_FC0_STATUS_DIED_BITS 0x10000000 +#define CLOCKS_FC0_STATUS_DIED_MSB 28 +#define CLOCKS_FC0_STATUS_DIED_LSB 28 +#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAST +// Description : Test clock faster than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_FAST_RESET 0x0 +#define CLOCKS_FC0_STATUS_FAST_BITS 0x01000000 +#define CLOCKS_FC0_STATUS_FAST_MSB 24 +#define CLOCKS_FC0_STATUS_FAST_LSB 24 +#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_SLOW +// Description : Test clock slower than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_SLOW_RESET 0x0 +#define CLOCKS_FC0_STATUS_SLOW_BITS 0x00100000 +#define CLOCKS_FC0_STATUS_SLOW_MSB 20 +#define CLOCKS_FC0_STATUS_SLOW_LSB 20 +#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAIL +// Description : Test failed +#define CLOCKS_FC0_STATUS_FAIL_RESET 0x0 +#define CLOCKS_FC0_STATUS_FAIL_BITS 0x00010000 +#define CLOCKS_FC0_STATUS_FAIL_MSB 16 +#define CLOCKS_FC0_STATUS_FAIL_LSB 16 +#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_WAITING +// Description : Waiting for test clock to start +#define CLOCKS_FC0_STATUS_WAITING_RESET 0x0 +#define CLOCKS_FC0_STATUS_WAITING_BITS 0x00001000 +#define CLOCKS_FC0_STATUS_WAITING_MSB 12 +#define CLOCKS_FC0_STATUS_WAITING_LSB 12 +#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_RUNNING +// Description : Test running +#define CLOCKS_FC0_STATUS_RUNNING_RESET 0x0 +#define CLOCKS_FC0_STATUS_RUNNING_BITS 0x00000100 +#define CLOCKS_FC0_STATUS_RUNNING_MSB 8 +#define CLOCKS_FC0_STATUS_RUNNING_LSB 8 +#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DONE +// Description : Test complete +#define CLOCKS_FC0_STATUS_DONE_RESET 0x0 +#define CLOCKS_FC0_STATUS_DONE_BITS 0x00000010 +#define CLOCKS_FC0_STATUS_DONE_MSB 4 +#define CLOCKS_FC0_STATUS_DONE_LSB 4 +#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_PASS +// Description : Test passed +#define CLOCKS_FC0_STATUS_PASS_RESET 0x0 +#define CLOCKS_FC0_STATUS_PASS_BITS 0x00000001 +#define CLOCKS_FC0_STATUS_PASS_MSB 0 +#define CLOCKS_FC0_STATUS_PASS_LSB 0 +#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_RESULT +// Description : Result of frequency measurement, only valid when status_done=1 +#define CLOCKS_FC0_RESULT_OFFSET 0x0000009c +#define CLOCKS_FC0_RESULT_BITS 0x3fffffff +#define CLOCKS_FC0_RESULT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_KHZ +// Description : None +#define CLOCKS_FC0_RESULT_KHZ_RESET 0x0000000 +#define CLOCKS_FC0_RESULT_KHZ_BITS 0x3fffffe0 +#define CLOCKS_FC0_RESULT_KHZ_MSB 29 +#define CLOCKS_FC0_RESULT_KHZ_LSB 5 +#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_FRAC +// Description : None +#define CLOCKS_FC0_RESULT_FRAC_RESET 0x00 +#define CLOCKS_FC0_RESULT_FRAC_BITS 0x0000001f +#define CLOCKS_FC0_RESULT_FRAC_MSB 4 +#define CLOCKS_FC0_RESULT_FRAC_LSB 0 +#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_WAKE_EN0 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN0_OFFSET 0x000000a0 +#define CLOCKS_WAKE_EN0_BITS 0xffffffff +#define CLOCKS_WAKE_EN0_RESET 0xffffffff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS 0x80000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB 31 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS 0x40000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB 30 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS 0x20000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB 29 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS 0x10000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB 28 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS 0x08000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB 27 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS 0x04000000 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB 26 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS 0x02000000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB 25 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS 0x01000000 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB 24 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS 0x00800000 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB 23 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS 0x00400000 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB 22 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS 0x00200000 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB 21 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS 0x00100000 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB 20 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS 0x00080000 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB 19 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS 0x00040000 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB 18 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS 0x00020000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB 17 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS 0x00010000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB 16 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB 15 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB 14 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS 0x00002000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB 13 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS 0x00001000 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB 12 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS 0x00000800 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB 11 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS 0x00000200 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB 9 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS 0x00000100 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB 8 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS 0x00000080 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB 7 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS 0x00000040 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB 6 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS 0x00000020 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB 5 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB 4 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB 3 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS 0x00000004 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB 2 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC +// Description : None +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS 0x00000002 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB 1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS +// Description : None +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET 0x1 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB 0 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_WAKE_EN1 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN1_OFFSET 0x000000a4 +#define CLOCKS_WAKE_EN1_BITS 0x00007fff +#define CLOCKS_WAKE_EN1_RESET 0x00007fff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS 0x00004000 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB 14 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS 0x00002000 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB 13 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB 12 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL +// Description : None +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS 0x00000800 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB 11 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB 10 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS 0x00000200 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB 9 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS 0x00000100 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB 8 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS 0x00000080 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB 7 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS 0x00000040 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB 6 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS 0x00000020 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB 5 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS 0x00000010 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB 4 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB 3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB 2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS 0x00000002 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB 1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 +// Description : None +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET 0x1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS 0x00000001 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB 0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN0 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN0_OFFSET 0x000000a8 +#define CLOCKS_SLEEP_EN0_BITS 0xffffffff +#define CLOCKS_SLEEP_EN0_RESET 0xffffffff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS 0x80000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB 31 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS 0x40000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB 30 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS 0x20000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB 29 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS 0x10000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB 28 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS 0x08000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB 27 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS 0x04000000 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB 26 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS 0x02000000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB 25 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS 0x01000000 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB 24 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS 0x00800000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB 23 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS 0x00400000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB 22 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS 0x00200000 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB 21 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS 0x00100000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB 20 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS 0x00080000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB 19 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS 0x00040000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB 18 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS 0x00020000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB 17 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS 0x00010000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB 16 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS 0x00008000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB 15 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS 0x00004000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB 14 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS 0x00002000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB 13 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS 0x00001000 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB 12 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS 0x00000800 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB 11 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS 0x00000200 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB 9 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS 0x00000100 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB 8 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB 8 +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS 0x00000080 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB 7 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS 0x00000040 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB 6 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS 0x00000020 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB 5 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS 0x00000010 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB 4 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS 0x00000008 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB 3 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS 0x00000004 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB 2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS 0x00000002 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB 1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS +// Description : None +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET 0x1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS 0x00000001 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB 0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN1 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN1_OFFSET 0x000000ac +#define CLOCKS_SLEEP_EN1_BITS 0x00007fff +#define CLOCKS_SLEEP_EN1_RESET 0x00007fff +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS 0x00004000 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB 14 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS 0x00002000 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB 13 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS 0x00001000 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB 12 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS 0x00000800 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB 11 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS 0x00000400 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB 10 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS 0x00000200 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB 9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS 0x00000100 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB 8 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS 0x00000080 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB 7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS 0x00000040 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB 6 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS 0x00000020 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB 5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS 0x00000010 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB 4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS 0x00000008 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB 3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS 0x00000004 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB 2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS 0x00000002 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB 1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 +// Description : None +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET 0x1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS 0x00000001 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB 0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_ENABLED0 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED0_OFFSET 0x000000b0 +#define CLOCKS_ENABLED0_BITS 0xffffffff +#define CLOCKS_ENABLED0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS 0x80000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB 31 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB 31 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS 0x40000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB 30 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB 30 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS 0x20000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB 29 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB 29 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS 0x10000000 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB 28 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB 28 +#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SPI1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS 0x08000000 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB 27 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB 27 +#define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_PERI_SPI1 +// Description : None +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS 0x04000000 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB 26 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB 26 +#define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SPI0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS 0x02000000 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB 25 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB 25 +#define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_PERI_SPI0 +// Description : None +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS 0x01000000 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB 24 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB 24 +#define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SIO +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS 0x00800000 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB 23 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB 23 +#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_RTC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS 0x00400000 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB 22 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB 22 +#define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_RTC_RTC +// Description : None +#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS 0x00200000 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB 21 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB 21 +#define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS 0x00100000 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB 20 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB 20 +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROM +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS 0x00080000 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB 19 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB 19 +#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS 0x00040000 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB 18 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB 18 +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PWM +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS 0x00020000 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB 17 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB 17 +#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PSM +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS 0x00010000 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB 16 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB 16 +#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS 0x00008000 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB 15 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB 15 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS 0x00004000 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB 14 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB 14 +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS 0x00002000 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB 13 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB 13 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS 0x00001000 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB 12 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB 12 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PADS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS 0x00000800 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB 11 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB 11 +#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS 0x00000400 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB 10 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB 10 +#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS 0x00000200 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB 9 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB 9 +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_IO +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS 0x00000100 +#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB 8 +#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB 8 +#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS 0x00000080 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB 7 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB 7 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS 0x00000040 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB 6 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB 6 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_DMA +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS 0x00000020 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB 5 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB 5 +#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS 0x00000010 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB 4 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB 4 +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS 0x00000008 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB 3 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB 3 +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ADC +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS 0x00000004 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB 2 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB 2 +#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_ADC_ADC +// Description : None +#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS 0x00000002 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB 1 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB 1 +#define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS +// Description : None +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET 0x0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS 0x00000001 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB 0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB 0 +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_ENABLED1 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED1_OFFSET 0x000000b4 +#define CLOCKS_ENABLED1_BITS 0x00007fff +#define CLOCKS_ENABLED1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS 0x00004000 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB 14 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB 14 +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XIP +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS 0x00002000 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB 13 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB 13 +#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS 0x00001000 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB 12 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB 12 +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL +// Description : None +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS 0x00000800 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB 11 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB 11 +#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS 0x00000400 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB 10 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB 10 +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART1 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS 0x00000200 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB 9 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB 9 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART1 +// Description : None +#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS 0x00000100 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB 8 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB 8 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART0 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS 0x00000080 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB 7 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB 7 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART0 +// Description : None +#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS 0x00000040 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB 6 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB 6 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS 0x00000020 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB 5 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB 5 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS 0x00000010 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB 4 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB 4 +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS 0x00000008 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB 3 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB 3 +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS 0x00000004 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB 2 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB 2 +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS 0x00000002 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB 1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB 1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 +// Description : None +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET 0x0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS 0x00000001 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB 0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB 0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTR +// Description : Raw Interrupts +#define CLOCKS_INTR_OFFSET 0x000000b8 +#define CLOCKS_INTR_BITS 0x00000001 +#define CLOCKS_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTR_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTR_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTR_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTR_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTR_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTE +// Description : Interrupt Enable +#define CLOCKS_INTE_OFFSET 0x000000bc +#define CLOCKS_INTE_BITS 0x00000001 +#define CLOCKS_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTE_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTE_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTE_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTE_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTE_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTF +// Description : Interrupt Force +#define CLOCKS_INTF_OFFSET 0x000000c0 +#define CLOCKS_INTF_BITS 0x00000001 +#define CLOCKS_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTF_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTF_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTF_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTF_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTF_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTS +// Description : Interrupt status after masking & forcing +#define CLOCKS_INTS_OFFSET 0x000000c4 +#define CLOCKS_INTS_BITS 0x00000001 +#define CLOCKS_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTS_CLK_SYS_RESUS +// Description : None +#define CLOCKS_INTS_CLK_SYS_RESUS_RESET 0x0 +#define CLOCKS_INTS_CLK_SYS_RESUS_BITS 0x00000001 +#define CLOCKS_INTS_CLK_SYS_RESUS_MSB 0 +#define CLOCKS_INTS_CLK_SYS_RESUS_LSB 0 +#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_CLOCKS_DEFINED diff --git a/rp2040/hardware/regs/dma.h b/rp2040/hardware/regs/dma.h new file mode 100644 index 0000000..884b0d3 --- /dev/null +++ b/rp2040/hardware/regs/dma.h @@ -0,0 +1,5257 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : DMA +// Version : 1 +// Bus type : apb +// Description : DMA with separate read and write masters +// ============================================================================= +#ifndef HARDWARE_REGS_DMA_DEFINED +#define HARDWARE_REGS_DMA_DEFINED +// ============================================================================= +// Register : DMA_CH0_READ_ADDR +// Description : DMA Channel 0 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH0_READ_ADDR_OFFSET 0x00000000 +#define DMA_CH0_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_READ_ADDR_RESET 0x00000000 +#define DMA_CH0_READ_ADDR_MSB 31 +#define DMA_CH0_READ_ADDR_LSB 0 +#define DMA_CH0_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_WRITE_ADDR +// Description : DMA Channel 0 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH0_WRITE_ADDR_OFFSET 0x00000004 +#define DMA_CH0_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH0_WRITE_ADDR_MSB 31 +#define DMA_CH0_WRITE_ADDR_LSB 0 +#define DMA_CH0_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_TRANS_COUNT +// Description : DMA Channel 0 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH0_TRANS_COUNT_OFFSET 0x00000008 +#define DMA_CH0_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH0_TRANS_COUNT_MSB 31 +#define DMA_CH0_TRANS_COUNT_LSB 0 +#define DMA_CH0_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_CTRL_TRIG +// Description : DMA Channel 0 Control and Status +#define DMA_CH0_CTRL_TRIG_OFFSET 0x0000000c +#define DMA_CH0_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH0_CTRL_TRIG_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH0_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH0_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH0_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH0_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH0_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH0_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (0). +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH0_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH0_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH0_CTRL_TRIG_EN_MSB 0 +#define DMA_CH0_CTRL_TRIG_EN_LSB 0 +#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL1_CTRL_OFFSET 0x00000010 +#define DMA_CH0_AL1_CTRL_BITS 0xffffffff +#define DMA_CH0_AL1_CTRL_RESET "-" +#define DMA_CH0_AL1_CTRL_MSB 31 +#define DMA_CH0_AL1_CTRL_LSB 0 +#define DMA_CH0_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL1_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL1_READ_ADDR_OFFSET 0x00000014 +#define DMA_CH0_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_READ_ADDR_RESET "-" +#define DMA_CH0_AL1_READ_ADDR_MSB 31 +#define DMA_CH0_AL1_READ_ADDR_LSB 0 +#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL1_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL1_WRITE_ADDR_OFFSET 0x00000018 +#define DMA_CH0_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH0_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 0 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000001c +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL2_CTRL_OFFSET 0x00000020 +#define DMA_CH0_AL2_CTRL_BITS 0xffffffff +#define DMA_CH0_AL2_CTRL_RESET "-" +#define DMA_CH0_AL2_CTRL_MSB 31 +#define DMA_CH0_AL2_CTRL_LSB 0 +#define DMA_CH0_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL2_TRANS_COUNT_OFFSET 0x00000024 +#define DMA_CH0_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH0_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL2_READ_ADDR_OFFSET 0x00000028 +#define DMA_CH0_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH0_AL2_READ_ADDR_RESET "-" +#define DMA_CH0_AL2_READ_ADDR_MSB 31 +#define DMA_CH0_AL2_READ_ADDR_LSB 0 +#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 0 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000002c +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL3_CTRL_OFFSET 0x00000030 +#define DMA_CH0_AL3_CTRL_BITS 0xffffffff +#define DMA_CH0_AL3_CTRL_RESET "-" +#define DMA_CH0_AL3_CTRL_MSB 31 +#define DMA_CH0_AL3_CTRL_LSB 0 +#define DMA_CH0_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL3_WRITE_ADDR_OFFSET 0x00000034 +#define DMA_CH0_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH0_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH0_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL3_TRANS_COUNT_OFFSET 0x00000038 +#define DMA_CH0_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH0_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH0_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_AL3_READ_ADDR_TRIG +// Description : Alias for channel 0 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET 0x0000003c +#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_READ_ADDR +// Description : DMA Channel 1 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH1_READ_ADDR_OFFSET 0x00000040 +#define DMA_CH1_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_READ_ADDR_RESET 0x00000000 +#define DMA_CH1_READ_ADDR_MSB 31 +#define DMA_CH1_READ_ADDR_LSB 0 +#define DMA_CH1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_WRITE_ADDR +// Description : DMA Channel 1 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH1_WRITE_ADDR_OFFSET 0x00000044 +#define DMA_CH1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH1_WRITE_ADDR_MSB 31 +#define DMA_CH1_WRITE_ADDR_LSB 0 +#define DMA_CH1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_TRANS_COUNT +// Description : DMA Channel 1 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH1_TRANS_COUNT_OFFSET 0x00000048 +#define DMA_CH1_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH1_TRANS_COUNT_MSB 31 +#define DMA_CH1_TRANS_COUNT_LSB 0 +#define DMA_CH1_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_CTRL_TRIG +// Description : DMA Channel 1 Control and Status +#define DMA_CH1_CTRL_TRIG_OFFSET 0x0000004c +#define DMA_CH1_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH1_CTRL_TRIG_RESET 0x00000800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH1_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH1_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH1_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH1_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH1_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH1_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (1). +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET 0x1 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH1_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH1_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH1_CTRL_TRIG_EN_MSB 0 +#define DMA_CH1_CTRL_TRIG_EN_LSB 0 +#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL1_CTRL_OFFSET 0x00000050 +#define DMA_CH1_AL1_CTRL_BITS 0xffffffff +#define DMA_CH1_AL1_CTRL_RESET "-" +#define DMA_CH1_AL1_CTRL_MSB 31 +#define DMA_CH1_AL1_CTRL_LSB 0 +#define DMA_CH1_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL1_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL1_READ_ADDR_OFFSET 0x00000054 +#define DMA_CH1_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_READ_ADDR_RESET "-" +#define DMA_CH1_AL1_READ_ADDR_MSB 31 +#define DMA_CH1_AL1_READ_ADDR_LSB 0 +#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL1_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL1_WRITE_ADDR_OFFSET 0x00000058 +#define DMA_CH1_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH1_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 1 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000005c +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL2_CTRL_OFFSET 0x00000060 +#define DMA_CH1_AL2_CTRL_BITS 0xffffffff +#define DMA_CH1_AL2_CTRL_RESET "-" +#define DMA_CH1_AL2_CTRL_MSB 31 +#define DMA_CH1_AL2_CTRL_LSB 0 +#define DMA_CH1_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL2_TRANS_COUNT_OFFSET 0x00000064 +#define DMA_CH1_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH1_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL2_READ_ADDR_OFFSET 0x00000068 +#define DMA_CH1_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH1_AL2_READ_ADDR_RESET "-" +#define DMA_CH1_AL2_READ_ADDR_MSB 31 +#define DMA_CH1_AL2_READ_ADDR_LSB 0 +#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 1 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000006c +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL3_CTRL_OFFSET 0x00000070 +#define DMA_CH1_AL3_CTRL_BITS 0xffffffff +#define DMA_CH1_AL3_CTRL_RESET "-" +#define DMA_CH1_AL3_CTRL_MSB 31 +#define DMA_CH1_AL3_CTRL_LSB 0 +#define DMA_CH1_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL3_WRITE_ADDR_OFFSET 0x00000074 +#define DMA_CH1_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH1_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH1_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL3_TRANS_COUNT_OFFSET 0x00000078 +#define DMA_CH1_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH1_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH1_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_AL3_READ_ADDR_TRIG +// Description : Alias for channel 1 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET 0x0000007c +#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_READ_ADDR +// Description : DMA Channel 2 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH2_READ_ADDR_OFFSET 0x00000080 +#define DMA_CH2_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_READ_ADDR_RESET 0x00000000 +#define DMA_CH2_READ_ADDR_MSB 31 +#define DMA_CH2_READ_ADDR_LSB 0 +#define DMA_CH2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_WRITE_ADDR +// Description : DMA Channel 2 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH2_WRITE_ADDR_OFFSET 0x00000084 +#define DMA_CH2_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH2_WRITE_ADDR_MSB 31 +#define DMA_CH2_WRITE_ADDR_LSB 0 +#define DMA_CH2_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_TRANS_COUNT +// Description : DMA Channel 2 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH2_TRANS_COUNT_OFFSET 0x00000088 +#define DMA_CH2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH2_TRANS_COUNT_MSB 31 +#define DMA_CH2_TRANS_COUNT_LSB 0 +#define DMA_CH2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_CTRL_TRIG +// Description : DMA Channel 2 Control and Status +#define DMA_CH2_CTRL_TRIG_OFFSET 0x0000008c +#define DMA_CH2_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH2_CTRL_TRIG_RESET 0x00001000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH2_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH2_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH2_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH2_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH2_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH2_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (2). +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET 0x2 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH2_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH2_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH2_CTRL_TRIG_EN_MSB 0 +#define DMA_CH2_CTRL_TRIG_EN_LSB 0 +#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL1_CTRL_OFFSET 0x00000090 +#define DMA_CH2_AL1_CTRL_BITS 0xffffffff +#define DMA_CH2_AL1_CTRL_RESET "-" +#define DMA_CH2_AL1_CTRL_MSB 31 +#define DMA_CH2_AL1_CTRL_LSB 0 +#define DMA_CH2_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL1_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL1_READ_ADDR_OFFSET 0x00000094 +#define DMA_CH2_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_READ_ADDR_RESET "-" +#define DMA_CH2_AL1_READ_ADDR_MSB 31 +#define DMA_CH2_AL1_READ_ADDR_LSB 0 +#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL1_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL1_WRITE_ADDR_OFFSET 0x00000098 +#define DMA_CH2_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH2_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 2 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000009c +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL2_CTRL_OFFSET 0x000000a0 +#define DMA_CH2_AL2_CTRL_BITS 0xffffffff +#define DMA_CH2_AL2_CTRL_RESET "-" +#define DMA_CH2_AL2_CTRL_MSB 31 +#define DMA_CH2_AL2_CTRL_LSB 0 +#define DMA_CH2_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL2_TRANS_COUNT_OFFSET 0x000000a4 +#define DMA_CH2_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH2_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL2_READ_ADDR_OFFSET 0x000000a8 +#define DMA_CH2_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH2_AL2_READ_ADDR_RESET "-" +#define DMA_CH2_AL2_READ_ADDR_MSB 31 +#define DMA_CH2_AL2_READ_ADDR_LSB 0 +#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 2 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ac +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL3_CTRL_OFFSET 0x000000b0 +#define DMA_CH2_AL3_CTRL_BITS 0xffffffff +#define DMA_CH2_AL3_CTRL_RESET "-" +#define DMA_CH2_AL3_CTRL_MSB 31 +#define DMA_CH2_AL3_CTRL_LSB 0 +#define DMA_CH2_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL3_WRITE_ADDR_OFFSET 0x000000b4 +#define DMA_CH2_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH2_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH2_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL3_TRANS_COUNT_OFFSET 0x000000b8 +#define DMA_CH2_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH2_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH2_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_AL3_READ_ADDR_TRIG +// Description : Alias for channel 2 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET 0x000000bc +#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_READ_ADDR +// Description : DMA Channel 3 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH3_READ_ADDR_OFFSET 0x000000c0 +#define DMA_CH3_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_READ_ADDR_RESET 0x00000000 +#define DMA_CH3_READ_ADDR_MSB 31 +#define DMA_CH3_READ_ADDR_LSB 0 +#define DMA_CH3_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_WRITE_ADDR +// Description : DMA Channel 3 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH3_WRITE_ADDR_OFFSET 0x000000c4 +#define DMA_CH3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH3_WRITE_ADDR_MSB 31 +#define DMA_CH3_WRITE_ADDR_LSB 0 +#define DMA_CH3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_TRANS_COUNT +// Description : DMA Channel 3 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH3_TRANS_COUNT_OFFSET 0x000000c8 +#define DMA_CH3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH3_TRANS_COUNT_MSB 31 +#define DMA_CH3_TRANS_COUNT_LSB 0 +#define DMA_CH3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_CTRL_TRIG +// Description : DMA Channel 3 Control and Status +#define DMA_CH3_CTRL_TRIG_OFFSET 0x000000cc +#define DMA_CH3_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH3_CTRL_TRIG_RESET 0x00001800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH3_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH3_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH3_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH3_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH3_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH3_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (3). +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET 0x3 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH3_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH3_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH3_CTRL_TRIG_EN_MSB 0 +#define DMA_CH3_CTRL_TRIG_EN_LSB 0 +#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL1_CTRL_OFFSET 0x000000d0 +#define DMA_CH3_AL1_CTRL_BITS 0xffffffff +#define DMA_CH3_AL1_CTRL_RESET "-" +#define DMA_CH3_AL1_CTRL_MSB 31 +#define DMA_CH3_AL1_CTRL_LSB 0 +#define DMA_CH3_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL1_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL1_READ_ADDR_OFFSET 0x000000d4 +#define DMA_CH3_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_READ_ADDR_RESET "-" +#define DMA_CH3_AL1_READ_ADDR_MSB 31 +#define DMA_CH3_AL1_READ_ADDR_LSB 0 +#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL1_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL1_WRITE_ADDR_OFFSET 0x000000d8 +#define DMA_CH3_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH3_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 3 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET 0x000000dc +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL2_CTRL_OFFSET 0x000000e0 +#define DMA_CH3_AL2_CTRL_BITS 0xffffffff +#define DMA_CH3_AL2_CTRL_RESET "-" +#define DMA_CH3_AL2_CTRL_MSB 31 +#define DMA_CH3_AL2_CTRL_LSB 0 +#define DMA_CH3_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL2_TRANS_COUNT_OFFSET 0x000000e4 +#define DMA_CH3_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH3_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL2_READ_ADDR_OFFSET 0x000000e8 +#define DMA_CH3_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH3_AL2_READ_ADDR_RESET "-" +#define DMA_CH3_AL2_READ_ADDR_MSB 31 +#define DMA_CH3_AL2_READ_ADDR_LSB 0 +#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 3 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET 0x000000ec +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL3_CTRL_OFFSET 0x000000f0 +#define DMA_CH3_AL3_CTRL_BITS 0xffffffff +#define DMA_CH3_AL3_CTRL_RESET "-" +#define DMA_CH3_AL3_CTRL_MSB 31 +#define DMA_CH3_AL3_CTRL_LSB 0 +#define DMA_CH3_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL3_WRITE_ADDR_OFFSET 0x000000f4 +#define DMA_CH3_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH3_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH3_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL3_TRANS_COUNT_OFFSET 0x000000f8 +#define DMA_CH3_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH3_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH3_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_AL3_READ_ADDR_TRIG +// Description : Alias for channel 3 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET 0x000000fc +#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_READ_ADDR +// Description : DMA Channel 4 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH4_READ_ADDR_OFFSET 0x00000100 +#define DMA_CH4_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_READ_ADDR_RESET 0x00000000 +#define DMA_CH4_READ_ADDR_MSB 31 +#define DMA_CH4_READ_ADDR_LSB 0 +#define DMA_CH4_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_WRITE_ADDR +// Description : DMA Channel 4 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH4_WRITE_ADDR_OFFSET 0x00000104 +#define DMA_CH4_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH4_WRITE_ADDR_MSB 31 +#define DMA_CH4_WRITE_ADDR_LSB 0 +#define DMA_CH4_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_TRANS_COUNT +// Description : DMA Channel 4 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH4_TRANS_COUNT_OFFSET 0x00000108 +#define DMA_CH4_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH4_TRANS_COUNT_MSB 31 +#define DMA_CH4_TRANS_COUNT_LSB 0 +#define DMA_CH4_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_CTRL_TRIG +// Description : DMA Channel 4 Control and Status +#define DMA_CH4_CTRL_TRIG_OFFSET 0x0000010c +#define DMA_CH4_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH4_CTRL_TRIG_RESET 0x00002000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH4_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH4_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH4_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH4_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH4_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH4_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (4). +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET 0x4 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH4_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH4_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH4_CTRL_TRIG_EN_MSB 0 +#define DMA_CH4_CTRL_TRIG_EN_LSB 0 +#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL1_CTRL_OFFSET 0x00000110 +#define DMA_CH4_AL1_CTRL_BITS 0xffffffff +#define DMA_CH4_AL1_CTRL_RESET "-" +#define DMA_CH4_AL1_CTRL_MSB 31 +#define DMA_CH4_AL1_CTRL_LSB 0 +#define DMA_CH4_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL1_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL1_READ_ADDR_OFFSET 0x00000114 +#define DMA_CH4_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_READ_ADDR_RESET "-" +#define DMA_CH4_AL1_READ_ADDR_MSB 31 +#define DMA_CH4_AL1_READ_ADDR_LSB 0 +#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL1_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL1_WRITE_ADDR_OFFSET 0x00000118 +#define DMA_CH4_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH4_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 4 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000011c +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL2_CTRL_OFFSET 0x00000120 +#define DMA_CH4_AL2_CTRL_BITS 0xffffffff +#define DMA_CH4_AL2_CTRL_RESET "-" +#define DMA_CH4_AL2_CTRL_MSB 31 +#define DMA_CH4_AL2_CTRL_LSB 0 +#define DMA_CH4_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL2_TRANS_COUNT_OFFSET 0x00000124 +#define DMA_CH4_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH4_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL2_READ_ADDR_OFFSET 0x00000128 +#define DMA_CH4_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH4_AL2_READ_ADDR_RESET "-" +#define DMA_CH4_AL2_READ_ADDR_MSB 31 +#define DMA_CH4_AL2_READ_ADDR_LSB 0 +#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 4 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000012c +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL3_CTRL_OFFSET 0x00000130 +#define DMA_CH4_AL3_CTRL_BITS 0xffffffff +#define DMA_CH4_AL3_CTRL_RESET "-" +#define DMA_CH4_AL3_CTRL_MSB 31 +#define DMA_CH4_AL3_CTRL_LSB 0 +#define DMA_CH4_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL3_WRITE_ADDR_OFFSET 0x00000134 +#define DMA_CH4_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH4_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH4_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL3_TRANS_COUNT_OFFSET 0x00000138 +#define DMA_CH4_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH4_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH4_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_AL3_READ_ADDR_TRIG +// Description : Alias for channel 4 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET 0x0000013c +#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_READ_ADDR +// Description : DMA Channel 5 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH5_READ_ADDR_OFFSET 0x00000140 +#define DMA_CH5_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_READ_ADDR_RESET 0x00000000 +#define DMA_CH5_READ_ADDR_MSB 31 +#define DMA_CH5_READ_ADDR_LSB 0 +#define DMA_CH5_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_WRITE_ADDR +// Description : DMA Channel 5 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH5_WRITE_ADDR_OFFSET 0x00000144 +#define DMA_CH5_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH5_WRITE_ADDR_MSB 31 +#define DMA_CH5_WRITE_ADDR_LSB 0 +#define DMA_CH5_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_TRANS_COUNT +// Description : DMA Channel 5 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH5_TRANS_COUNT_OFFSET 0x00000148 +#define DMA_CH5_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH5_TRANS_COUNT_MSB 31 +#define DMA_CH5_TRANS_COUNT_LSB 0 +#define DMA_CH5_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_CTRL_TRIG +// Description : DMA Channel 5 Control and Status +#define DMA_CH5_CTRL_TRIG_OFFSET 0x0000014c +#define DMA_CH5_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH5_CTRL_TRIG_RESET 0x00002800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH5_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH5_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH5_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH5_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH5_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH5_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (5). +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET 0x5 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH5_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH5_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH5_CTRL_TRIG_EN_MSB 0 +#define DMA_CH5_CTRL_TRIG_EN_LSB 0 +#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL1_CTRL_OFFSET 0x00000150 +#define DMA_CH5_AL1_CTRL_BITS 0xffffffff +#define DMA_CH5_AL1_CTRL_RESET "-" +#define DMA_CH5_AL1_CTRL_MSB 31 +#define DMA_CH5_AL1_CTRL_LSB 0 +#define DMA_CH5_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL1_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL1_READ_ADDR_OFFSET 0x00000154 +#define DMA_CH5_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_READ_ADDR_RESET "-" +#define DMA_CH5_AL1_READ_ADDR_MSB 31 +#define DMA_CH5_AL1_READ_ADDR_LSB 0 +#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL1_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL1_WRITE_ADDR_OFFSET 0x00000158 +#define DMA_CH5_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH5_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 5 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000015c +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL2_CTRL_OFFSET 0x00000160 +#define DMA_CH5_AL2_CTRL_BITS 0xffffffff +#define DMA_CH5_AL2_CTRL_RESET "-" +#define DMA_CH5_AL2_CTRL_MSB 31 +#define DMA_CH5_AL2_CTRL_LSB 0 +#define DMA_CH5_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL2_TRANS_COUNT_OFFSET 0x00000164 +#define DMA_CH5_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH5_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL2_READ_ADDR_OFFSET 0x00000168 +#define DMA_CH5_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH5_AL2_READ_ADDR_RESET "-" +#define DMA_CH5_AL2_READ_ADDR_MSB 31 +#define DMA_CH5_AL2_READ_ADDR_LSB 0 +#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 5 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000016c +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL3_CTRL_OFFSET 0x00000170 +#define DMA_CH5_AL3_CTRL_BITS 0xffffffff +#define DMA_CH5_AL3_CTRL_RESET "-" +#define DMA_CH5_AL3_CTRL_MSB 31 +#define DMA_CH5_AL3_CTRL_LSB 0 +#define DMA_CH5_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL3_WRITE_ADDR_OFFSET 0x00000174 +#define DMA_CH5_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH5_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH5_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL3_TRANS_COUNT_OFFSET 0x00000178 +#define DMA_CH5_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH5_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH5_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_AL3_READ_ADDR_TRIG +// Description : Alias for channel 5 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET 0x0000017c +#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_READ_ADDR +// Description : DMA Channel 6 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH6_READ_ADDR_OFFSET 0x00000180 +#define DMA_CH6_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_READ_ADDR_RESET 0x00000000 +#define DMA_CH6_READ_ADDR_MSB 31 +#define DMA_CH6_READ_ADDR_LSB 0 +#define DMA_CH6_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_WRITE_ADDR +// Description : DMA Channel 6 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH6_WRITE_ADDR_OFFSET 0x00000184 +#define DMA_CH6_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH6_WRITE_ADDR_MSB 31 +#define DMA_CH6_WRITE_ADDR_LSB 0 +#define DMA_CH6_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_TRANS_COUNT +// Description : DMA Channel 6 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH6_TRANS_COUNT_OFFSET 0x00000188 +#define DMA_CH6_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH6_TRANS_COUNT_MSB 31 +#define DMA_CH6_TRANS_COUNT_LSB 0 +#define DMA_CH6_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_CTRL_TRIG +// Description : DMA Channel 6 Control and Status +#define DMA_CH6_CTRL_TRIG_OFFSET 0x0000018c +#define DMA_CH6_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH6_CTRL_TRIG_RESET 0x00003000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH6_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH6_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH6_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH6_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH6_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH6_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (6). +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET 0x6 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH6_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH6_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH6_CTRL_TRIG_EN_MSB 0 +#define DMA_CH6_CTRL_TRIG_EN_LSB 0 +#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL1_CTRL_OFFSET 0x00000190 +#define DMA_CH6_AL1_CTRL_BITS 0xffffffff +#define DMA_CH6_AL1_CTRL_RESET "-" +#define DMA_CH6_AL1_CTRL_MSB 31 +#define DMA_CH6_AL1_CTRL_LSB 0 +#define DMA_CH6_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL1_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL1_READ_ADDR_OFFSET 0x00000194 +#define DMA_CH6_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_READ_ADDR_RESET "-" +#define DMA_CH6_AL1_READ_ADDR_MSB 31 +#define DMA_CH6_AL1_READ_ADDR_LSB 0 +#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL1_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL1_WRITE_ADDR_OFFSET 0x00000198 +#define DMA_CH6_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH6_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 6 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000019c +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL2_CTRL_OFFSET 0x000001a0 +#define DMA_CH6_AL2_CTRL_BITS 0xffffffff +#define DMA_CH6_AL2_CTRL_RESET "-" +#define DMA_CH6_AL2_CTRL_MSB 31 +#define DMA_CH6_AL2_CTRL_LSB 0 +#define DMA_CH6_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL2_TRANS_COUNT_OFFSET 0x000001a4 +#define DMA_CH6_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH6_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL2_READ_ADDR_OFFSET 0x000001a8 +#define DMA_CH6_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH6_AL2_READ_ADDR_RESET "-" +#define DMA_CH6_AL2_READ_ADDR_MSB 31 +#define DMA_CH6_AL2_READ_ADDR_LSB 0 +#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 6 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ac +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL3_CTRL_OFFSET 0x000001b0 +#define DMA_CH6_AL3_CTRL_BITS 0xffffffff +#define DMA_CH6_AL3_CTRL_RESET "-" +#define DMA_CH6_AL3_CTRL_MSB 31 +#define DMA_CH6_AL3_CTRL_LSB 0 +#define DMA_CH6_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL3_WRITE_ADDR_OFFSET 0x000001b4 +#define DMA_CH6_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH6_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH6_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL3_TRANS_COUNT_OFFSET 0x000001b8 +#define DMA_CH6_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH6_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH6_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_AL3_READ_ADDR_TRIG +// Description : Alias for channel 6 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET 0x000001bc +#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_READ_ADDR +// Description : DMA Channel 7 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH7_READ_ADDR_OFFSET 0x000001c0 +#define DMA_CH7_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_READ_ADDR_RESET 0x00000000 +#define DMA_CH7_READ_ADDR_MSB 31 +#define DMA_CH7_READ_ADDR_LSB 0 +#define DMA_CH7_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_WRITE_ADDR +// Description : DMA Channel 7 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH7_WRITE_ADDR_OFFSET 0x000001c4 +#define DMA_CH7_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH7_WRITE_ADDR_MSB 31 +#define DMA_CH7_WRITE_ADDR_LSB 0 +#define DMA_CH7_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_TRANS_COUNT +// Description : DMA Channel 7 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH7_TRANS_COUNT_OFFSET 0x000001c8 +#define DMA_CH7_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH7_TRANS_COUNT_MSB 31 +#define DMA_CH7_TRANS_COUNT_LSB 0 +#define DMA_CH7_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_CTRL_TRIG +// Description : DMA Channel 7 Control and Status +#define DMA_CH7_CTRL_TRIG_OFFSET 0x000001cc +#define DMA_CH7_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH7_CTRL_TRIG_RESET 0x00003800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH7_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH7_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH7_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH7_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH7_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH7_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (7). +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET 0x7 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH7_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH7_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH7_CTRL_TRIG_EN_MSB 0 +#define DMA_CH7_CTRL_TRIG_EN_LSB 0 +#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL1_CTRL_OFFSET 0x000001d0 +#define DMA_CH7_AL1_CTRL_BITS 0xffffffff +#define DMA_CH7_AL1_CTRL_RESET "-" +#define DMA_CH7_AL1_CTRL_MSB 31 +#define DMA_CH7_AL1_CTRL_LSB 0 +#define DMA_CH7_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL1_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL1_READ_ADDR_OFFSET 0x000001d4 +#define DMA_CH7_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_READ_ADDR_RESET "-" +#define DMA_CH7_AL1_READ_ADDR_MSB 31 +#define DMA_CH7_AL1_READ_ADDR_LSB 0 +#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL1_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL1_WRITE_ADDR_OFFSET 0x000001d8 +#define DMA_CH7_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH7_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 7 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET 0x000001dc +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL2_CTRL_OFFSET 0x000001e0 +#define DMA_CH7_AL2_CTRL_BITS 0xffffffff +#define DMA_CH7_AL2_CTRL_RESET "-" +#define DMA_CH7_AL2_CTRL_MSB 31 +#define DMA_CH7_AL2_CTRL_LSB 0 +#define DMA_CH7_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL2_TRANS_COUNT_OFFSET 0x000001e4 +#define DMA_CH7_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH7_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL2_READ_ADDR_OFFSET 0x000001e8 +#define DMA_CH7_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH7_AL2_READ_ADDR_RESET "-" +#define DMA_CH7_AL2_READ_ADDR_MSB 31 +#define DMA_CH7_AL2_READ_ADDR_LSB 0 +#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 7 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET 0x000001ec +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL3_CTRL_OFFSET 0x000001f0 +#define DMA_CH7_AL3_CTRL_BITS 0xffffffff +#define DMA_CH7_AL3_CTRL_RESET "-" +#define DMA_CH7_AL3_CTRL_MSB 31 +#define DMA_CH7_AL3_CTRL_LSB 0 +#define DMA_CH7_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL3_WRITE_ADDR_OFFSET 0x000001f4 +#define DMA_CH7_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH7_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH7_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL3_TRANS_COUNT_OFFSET 0x000001f8 +#define DMA_CH7_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH7_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH7_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_AL3_READ_ADDR_TRIG +// Description : Alias for channel 7 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET 0x000001fc +#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_READ_ADDR +// Description : DMA Channel 8 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH8_READ_ADDR_OFFSET 0x00000200 +#define DMA_CH8_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_READ_ADDR_RESET 0x00000000 +#define DMA_CH8_READ_ADDR_MSB 31 +#define DMA_CH8_READ_ADDR_LSB 0 +#define DMA_CH8_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_WRITE_ADDR +// Description : DMA Channel 8 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH8_WRITE_ADDR_OFFSET 0x00000204 +#define DMA_CH8_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH8_WRITE_ADDR_MSB 31 +#define DMA_CH8_WRITE_ADDR_LSB 0 +#define DMA_CH8_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_TRANS_COUNT +// Description : DMA Channel 8 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH8_TRANS_COUNT_OFFSET 0x00000208 +#define DMA_CH8_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH8_TRANS_COUNT_MSB 31 +#define DMA_CH8_TRANS_COUNT_LSB 0 +#define DMA_CH8_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_CTRL_TRIG +// Description : DMA Channel 8 Control and Status +#define DMA_CH8_CTRL_TRIG_OFFSET 0x0000020c +#define DMA_CH8_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH8_CTRL_TRIG_RESET 0x00004000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH8_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH8_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH8_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH8_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH8_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH8_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (8). +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET 0x8 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH8_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH8_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH8_CTRL_TRIG_EN_MSB 0 +#define DMA_CH8_CTRL_TRIG_EN_LSB 0 +#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL1_CTRL_OFFSET 0x00000210 +#define DMA_CH8_AL1_CTRL_BITS 0xffffffff +#define DMA_CH8_AL1_CTRL_RESET "-" +#define DMA_CH8_AL1_CTRL_MSB 31 +#define DMA_CH8_AL1_CTRL_LSB 0 +#define DMA_CH8_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL1_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL1_READ_ADDR_OFFSET 0x00000214 +#define DMA_CH8_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_READ_ADDR_RESET "-" +#define DMA_CH8_AL1_READ_ADDR_MSB 31 +#define DMA_CH8_AL1_READ_ADDR_LSB 0 +#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL1_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL1_WRITE_ADDR_OFFSET 0x00000218 +#define DMA_CH8_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH8_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 8 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000021c +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL2_CTRL_OFFSET 0x00000220 +#define DMA_CH8_AL2_CTRL_BITS 0xffffffff +#define DMA_CH8_AL2_CTRL_RESET "-" +#define DMA_CH8_AL2_CTRL_MSB 31 +#define DMA_CH8_AL2_CTRL_LSB 0 +#define DMA_CH8_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL2_TRANS_COUNT_OFFSET 0x00000224 +#define DMA_CH8_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH8_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL2_READ_ADDR_OFFSET 0x00000228 +#define DMA_CH8_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH8_AL2_READ_ADDR_RESET "-" +#define DMA_CH8_AL2_READ_ADDR_MSB 31 +#define DMA_CH8_AL2_READ_ADDR_LSB 0 +#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 8 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000022c +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL3_CTRL_OFFSET 0x00000230 +#define DMA_CH8_AL3_CTRL_BITS 0xffffffff +#define DMA_CH8_AL3_CTRL_RESET "-" +#define DMA_CH8_AL3_CTRL_MSB 31 +#define DMA_CH8_AL3_CTRL_LSB 0 +#define DMA_CH8_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL3_WRITE_ADDR_OFFSET 0x00000234 +#define DMA_CH8_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH8_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH8_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL3_TRANS_COUNT_OFFSET 0x00000238 +#define DMA_CH8_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH8_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH8_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_AL3_READ_ADDR_TRIG +// Description : Alias for channel 8 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET 0x0000023c +#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_READ_ADDR +// Description : DMA Channel 9 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH9_READ_ADDR_OFFSET 0x00000240 +#define DMA_CH9_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_READ_ADDR_RESET 0x00000000 +#define DMA_CH9_READ_ADDR_MSB 31 +#define DMA_CH9_READ_ADDR_LSB 0 +#define DMA_CH9_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_WRITE_ADDR +// Description : DMA Channel 9 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH9_WRITE_ADDR_OFFSET 0x00000244 +#define DMA_CH9_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH9_WRITE_ADDR_MSB 31 +#define DMA_CH9_WRITE_ADDR_LSB 0 +#define DMA_CH9_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_TRANS_COUNT +// Description : DMA Channel 9 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH9_TRANS_COUNT_OFFSET 0x00000248 +#define DMA_CH9_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH9_TRANS_COUNT_MSB 31 +#define DMA_CH9_TRANS_COUNT_LSB 0 +#define DMA_CH9_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_CTRL_TRIG +// Description : DMA Channel 9 Control and Status +#define DMA_CH9_CTRL_TRIG_OFFSET 0x0000024c +#define DMA_CH9_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH9_CTRL_TRIG_RESET 0x00004800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH9_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH9_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH9_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH9_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH9_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH9_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (9). +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET 0x9 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH9_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH9_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH9_CTRL_TRIG_EN_MSB 0 +#define DMA_CH9_CTRL_TRIG_EN_LSB 0 +#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL1_CTRL_OFFSET 0x00000250 +#define DMA_CH9_AL1_CTRL_BITS 0xffffffff +#define DMA_CH9_AL1_CTRL_RESET "-" +#define DMA_CH9_AL1_CTRL_MSB 31 +#define DMA_CH9_AL1_CTRL_LSB 0 +#define DMA_CH9_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL1_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL1_READ_ADDR_OFFSET 0x00000254 +#define DMA_CH9_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_READ_ADDR_RESET "-" +#define DMA_CH9_AL1_READ_ADDR_MSB 31 +#define DMA_CH9_AL1_READ_ADDR_LSB 0 +#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL1_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL1_WRITE_ADDR_OFFSET 0x00000258 +#define DMA_CH9_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH9_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 9 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000025c +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL2_CTRL_OFFSET 0x00000260 +#define DMA_CH9_AL2_CTRL_BITS 0xffffffff +#define DMA_CH9_AL2_CTRL_RESET "-" +#define DMA_CH9_AL2_CTRL_MSB 31 +#define DMA_CH9_AL2_CTRL_LSB 0 +#define DMA_CH9_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL2_TRANS_COUNT_OFFSET 0x00000264 +#define DMA_CH9_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH9_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL2_READ_ADDR_OFFSET 0x00000268 +#define DMA_CH9_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH9_AL2_READ_ADDR_RESET "-" +#define DMA_CH9_AL2_READ_ADDR_MSB 31 +#define DMA_CH9_AL2_READ_ADDR_LSB 0 +#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 9 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET 0x0000026c +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL3_CTRL_OFFSET 0x00000270 +#define DMA_CH9_AL3_CTRL_BITS 0xffffffff +#define DMA_CH9_AL3_CTRL_RESET "-" +#define DMA_CH9_AL3_CTRL_MSB 31 +#define DMA_CH9_AL3_CTRL_LSB 0 +#define DMA_CH9_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL3_WRITE_ADDR_OFFSET 0x00000274 +#define DMA_CH9_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH9_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH9_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL3_TRANS_COUNT_OFFSET 0x00000278 +#define DMA_CH9_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH9_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH9_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_AL3_READ_ADDR_TRIG +// Description : Alias for channel 9 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET 0x0000027c +#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_READ_ADDR +// Description : DMA Channel 10 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH10_READ_ADDR_OFFSET 0x00000280 +#define DMA_CH10_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_READ_ADDR_RESET 0x00000000 +#define DMA_CH10_READ_ADDR_MSB 31 +#define DMA_CH10_READ_ADDR_LSB 0 +#define DMA_CH10_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_WRITE_ADDR +// Description : DMA Channel 10 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH10_WRITE_ADDR_OFFSET 0x00000284 +#define DMA_CH10_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH10_WRITE_ADDR_MSB 31 +#define DMA_CH10_WRITE_ADDR_LSB 0 +#define DMA_CH10_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_TRANS_COUNT +// Description : DMA Channel 10 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH10_TRANS_COUNT_OFFSET 0x00000288 +#define DMA_CH10_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH10_TRANS_COUNT_MSB 31 +#define DMA_CH10_TRANS_COUNT_LSB 0 +#define DMA_CH10_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_CTRL_TRIG +// Description : DMA Channel 10 Control and Status +#define DMA_CH10_CTRL_TRIG_OFFSET 0x0000028c +#define DMA_CH10_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH10_CTRL_TRIG_RESET 0x00005000 +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH10_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH10_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH10_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH10_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH10_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH10_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (10). +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET 0xa +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH10_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH10_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH10_CTRL_TRIG_EN_MSB 0 +#define DMA_CH10_CTRL_TRIG_EN_LSB 0 +#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL1_CTRL_OFFSET 0x00000290 +#define DMA_CH10_AL1_CTRL_BITS 0xffffffff +#define DMA_CH10_AL1_CTRL_RESET "-" +#define DMA_CH10_AL1_CTRL_MSB 31 +#define DMA_CH10_AL1_CTRL_LSB 0 +#define DMA_CH10_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL1_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL1_READ_ADDR_OFFSET 0x00000294 +#define DMA_CH10_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_READ_ADDR_RESET "-" +#define DMA_CH10_AL1_READ_ADDR_MSB 31 +#define DMA_CH10_AL1_READ_ADDR_LSB 0 +#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL1_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL1_WRITE_ADDR_OFFSET 0x00000298 +#define DMA_CH10_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH10_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 10 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET 0x0000029c +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL2_CTRL_OFFSET 0x000002a0 +#define DMA_CH10_AL2_CTRL_BITS 0xffffffff +#define DMA_CH10_AL2_CTRL_RESET "-" +#define DMA_CH10_AL2_CTRL_MSB 31 +#define DMA_CH10_AL2_CTRL_LSB 0 +#define DMA_CH10_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL2_TRANS_COUNT_OFFSET 0x000002a4 +#define DMA_CH10_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH10_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL2_READ_ADDR_OFFSET 0x000002a8 +#define DMA_CH10_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH10_AL2_READ_ADDR_RESET "-" +#define DMA_CH10_AL2_READ_ADDR_MSB 31 +#define DMA_CH10_AL2_READ_ADDR_LSB 0 +#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 10 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ac +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL3_CTRL_OFFSET 0x000002b0 +#define DMA_CH10_AL3_CTRL_BITS 0xffffffff +#define DMA_CH10_AL3_CTRL_RESET "-" +#define DMA_CH10_AL3_CTRL_MSB 31 +#define DMA_CH10_AL3_CTRL_LSB 0 +#define DMA_CH10_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL3_WRITE_ADDR_OFFSET 0x000002b4 +#define DMA_CH10_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH10_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH10_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL3_TRANS_COUNT_OFFSET 0x000002b8 +#define DMA_CH10_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH10_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH10_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_AL3_READ_ADDR_TRIG +// Description : Alias for channel 10 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET 0x000002bc +#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_READ_ADDR +// Description : DMA Channel 11 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH11_READ_ADDR_OFFSET 0x000002c0 +#define DMA_CH11_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_READ_ADDR_RESET 0x00000000 +#define DMA_CH11_READ_ADDR_MSB 31 +#define DMA_CH11_READ_ADDR_LSB 0 +#define DMA_CH11_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_WRITE_ADDR +// Description : DMA Channel 11 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH11_WRITE_ADDR_OFFSET 0x000002c4 +#define DMA_CH11_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_WRITE_ADDR_RESET 0x00000000 +#define DMA_CH11_WRITE_ADDR_MSB 31 +#define DMA_CH11_WRITE_ADDR_LSB 0 +#define DMA_CH11_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_TRANS_COUNT +// Description : DMA Channel 11 Transfer Count +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH11_TRANS_COUNT_OFFSET 0x000002c8 +#define DMA_CH11_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_TRANS_COUNT_RESET 0x00000000 +#define DMA_CH11_TRANS_COUNT_MSB 31 +#define DMA_CH11_TRANS_COUNT_LSB 0 +#define DMA_CH11_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_CTRL_TRIG +// Description : DMA Channel 11 Control and Status +#define DMA_CH11_CTRL_TRIG_OFFSET 0x000002cc +#define DMA_CH11_CTRL_TRIG_BITS 0xe1ffffff +#define DMA_CH11_CTRL_TRIG_RESET 0x00005800 +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS 0x80000000 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB 31 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB 31 +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not to be earlier, or more than 3 transfers +// later) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS 0x40000000 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB 30 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB 30 +#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not to be earlier, or more than 5 +// transfers later) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS 0x20000000 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB 29 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB 29 +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH11_CTRL_TRIG_BUSY_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_BUSY_BITS 0x01000000 +#define DMA_CH11_CTRL_TRIG_BUSY_MSB 24 +#define DMA_CH11_CTRL_TRIG_BUSY_LSB 24 +#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a +// per-control- block basis. +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS 0x00800000 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB 23 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB 23 +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH11_CTRL_TRIG_BSWAP_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_BSWAP_BITS 0x00400000 +#define DMA_CH11_CTRL_TRIG_BSWAP_MSB 22 +#define DMA_CH11_CTRL_TRIG_BSWAP_LSB 22 +#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS 0x00200000 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB 21 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB 21 +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET 0x00 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS 0x001f8000 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB 20 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB 15 +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 0x3b +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 0x3c +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 0x3d +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 0x3e +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT 0x3f +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// Reset value is equal to channel number (11). +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET 0xb +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS 0x00007800 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB 14 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB 11 +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS 0x00000400 +#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB 10 +#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB 10 +#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS 0x000003c0 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB 9 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB 6 +#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE 0x0 +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS 0x00000020 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB 5 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB 5 +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS 0x00000010 +#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB 4 +#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB 4 +#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS 0x0000000c +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB 3 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB 2 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE 0x0 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD 0x1 +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD 0x2 +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS 0x00000002 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB 1 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB 1 +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH11_CTRL_TRIG_EN_RESET 0x0 +#define DMA_CH11_CTRL_TRIG_EN_BITS 0x00000001 +#define DMA_CH11_CTRL_TRIG_EN_MSB 0 +#define DMA_CH11_CTRL_TRIG_EN_LSB 0 +#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL1_CTRL_OFFSET 0x000002d0 +#define DMA_CH11_AL1_CTRL_BITS 0xffffffff +#define DMA_CH11_AL1_CTRL_RESET "-" +#define DMA_CH11_AL1_CTRL_MSB 31 +#define DMA_CH11_AL1_CTRL_LSB 0 +#define DMA_CH11_AL1_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL1_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL1_READ_ADDR_OFFSET 0x000002d4 +#define DMA_CH11_AL1_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_READ_ADDR_RESET "-" +#define DMA_CH11_AL1_READ_ADDR_MSB 31 +#define DMA_CH11_AL1_READ_ADDR_LSB 0 +#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL1_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL1_WRITE_ADDR_OFFSET 0x000002d8 +#define DMA_CH11_AL1_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL1_WRITE_ADDR_MSB 31 +#define DMA_CH11_AL1_WRITE_ADDR_LSB 0 +#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 11 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET 0x000002dc +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS 0xffffffff +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB 31 +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB 0 +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL2_CTRL_OFFSET 0x000002e0 +#define DMA_CH11_AL2_CTRL_BITS 0xffffffff +#define DMA_CH11_AL2_CTRL_RESET "-" +#define DMA_CH11_AL2_CTRL_MSB 31 +#define DMA_CH11_AL2_CTRL_LSB 0 +#define DMA_CH11_AL2_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL2_TRANS_COUNT_OFFSET 0x000002e4 +#define DMA_CH11_AL2_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL2_TRANS_COUNT_MSB 31 +#define DMA_CH11_AL2_TRANS_COUNT_LSB 0 +#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL2_READ_ADDR_OFFSET 0x000002e8 +#define DMA_CH11_AL2_READ_ADDR_BITS 0xffffffff +#define DMA_CH11_AL2_READ_ADDR_RESET "-" +#define DMA_CH11_AL2_READ_ADDR_MSB 31 +#define DMA_CH11_AL2_READ_ADDR_LSB 0 +#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 11 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET 0x000002ec +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB 31 +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB 0 +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL3_CTRL_OFFSET 0x000002f0 +#define DMA_CH11_AL3_CTRL_BITS 0xffffffff +#define DMA_CH11_AL3_CTRL_RESET "-" +#define DMA_CH11_AL3_CTRL_MSB 31 +#define DMA_CH11_AL3_CTRL_LSB 0 +#define DMA_CH11_AL3_CTRL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL3_WRITE_ADDR_OFFSET 0x000002f4 +#define DMA_CH11_AL3_WRITE_ADDR_BITS 0xffffffff +#define DMA_CH11_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL3_WRITE_ADDR_MSB 31 +#define DMA_CH11_AL3_WRITE_ADDR_LSB 0 +#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL3_TRANS_COUNT_OFFSET 0x000002f8 +#define DMA_CH11_AL3_TRANS_COUNT_BITS 0xffffffff +#define DMA_CH11_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL3_TRANS_COUNT_MSB 31 +#define DMA_CH11_AL3_TRANS_COUNT_LSB 0 +#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_AL3_READ_ADDR_TRIG +// Description : Alias for channel 11 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET 0x000002fc +#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS 0xffffffff +#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB 31 +#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB 0 +#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO" +// ============================================================================= +// Register : DMA_INTR +// Description : Interrupt Status (raw) +// Raw interrupt status for DMA Channels 0..15. Bit n corresponds +// to channel n. Ignores any masking or forcing. Channel +// interrupts can be cleared by writing a bit mask to INTR, INTS0 +// or INTS1. +// +// Channel interrupts can be routed to either of two system-level +// IRQs based on INTE0 and INTE1. +// +// This can be used vector different channel interrupts to +// different ISRs: this might be done to allow NVIC IRQ preemption +// for more time-critical channels, or to spread IRQ load across +// different cores. +// +// It is also valid to ignore this behaviour and just use +// INTE0/INTS0/IRQ 0. +#define DMA_INTR_OFFSET 0x00000400 +#define DMA_INTR_BITS 0x0000ffff +#define DMA_INTR_RESET 0x00000000 +#define DMA_INTR_MSB 15 +#define DMA_INTR_LSB 0 +#define DMA_INTR_ACCESS "RO" +// ============================================================================= +// Register : DMA_INTE0 +// Description : Interrupt Enables for IRQ 0 +// Set bit n to pass interrupts from channel n to DMA IRQ 0. +#define DMA_INTE0_OFFSET 0x00000404 +#define DMA_INTE0_BITS 0x0000ffff +#define DMA_INTE0_RESET 0x00000000 +#define DMA_INTE0_MSB 15 +#define DMA_INTE0_LSB 0 +#define DMA_INTE0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF0 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTE0. The +// interrupt remains asserted until INTF0 is cleared. +#define DMA_INTF0_OFFSET 0x00000408 +#define DMA_INTF0_BITS 0x0000ffff +#define DMA_INTF0_RESET 0x00000000 +#define DMA_INTF0_MSB 15 +#define DMA_INTF0_LSB 0 +#define DMA_INTF0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS0 +// Description : Interrupt Status for IRQ 0 +// Indicates active channel interrupt requests which are currently +// causing IRQ 0 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +#define DMA_INTS0_OFFSET 0x0000040c +#define DMA_INTS0_BITS 0x0000ffff +#define DMA_INTS0_RESET 0x00000000 +#define DMA_INTS0_MSB 15 +#define DMA_INTS0_LSB 0 +#define DMA_INTS0_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE1 +// Description : Interrupt Enables for IRQ 1 +// Set bit n to pass interrupts from channel n to DMA IRQ 1. +#define DMA_INTE1_OFFSET 0x00000414 +#define DMA_INTE1_BITS 0x0000ffff +#define DMA_INTE1_RESET 0x00000000 +#define DMA_INTE1_MSB 15 +#define DMA_INTE1_LSB 0 +#define DMA_INTE1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF1 +// Description : Force Interrupts for IRQ 1 +// Write 1s to force the corresponding bits in INTE0. The +// interrupt remains asserted until INTF0 is cleared. +#define DMA_INTF1_OFFSET 0x00000418 +#define DMA_INTF1_BITS 0x0000ffff +#define DMA_INTF1_RESET 0x00000000 +#define DMA_INTF1_MSB 15 +#define DMA_INTF1_LSB 0 +#define DMA_INTF1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS1 +// Description : Interrupt Status (masked) for IRQ 1 +// Indicates active channel interrupt requests which are currently +// causing IRQ 1 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +#define DMA_INTS1_OFFSET 0x0000041c +#define DMA_INTS1_BITS 0x0000ffff +#define DMA_INTS1_RESET 0x00000000 +#define DMA_INTS1_MSB 15 +#define DMA_INTS1_LSB 0 +#define DMA_INTS1_ACCESS "WC" +// ============================================================================= +// Register : DMA_TIMER0 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER0_OFFSET 0x00000420 +#define DMA_TIMER0_BITS 0xffffffff +#define DMA_TIMER0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_X_RESET 0x0000 +#define DMA_TIMER0_X_BITS 0xffff0000 +#define DMA_TIMER0_X_MSB 31 +#define DMA_TIMER0_X_LSB 16 +#define DMA_TIMER0_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_Y_RESET 0x0000 +#define DMA_TIMER0_Y_BITS 0x0000ffff +#define DMA_TIMER0_Y_MSB 15 +#define DMA_TIMER0_Y_LSB 0 +#define DMA_TIMER0_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER1 +// Description : Pacing (X/Y) Fractional Timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER1_OFFSET 0x00000424 +#define DMA_TIMER1_BITS 0xffffffff +#define DMA_TIMER1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_X_RESET 0x0000 +#define DMA_TIMER1_X_BITS 0xffff0000 +#define DMA_TIMER1_X_MSB 31 +#define DMA_TIMER1_X_LSB 16 +#define DMA_TIMER1_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_Y_RESET 0x0000 +#define DMA_TIMER1_Y_BITS 0x0000ffff +#define DMA_TIMER1_Y_MSB 15 +#define DMA_TIMER1_Y_LSB 0 +#define DMA_TIMER1_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_MULTI_CHAN_TRIGGER +// Description : Trigger one or more channels simultaneously +// Each bit in this register corresponds to a DMA channel. Writing +// a 1 to the relevant bit is the same as writing to that +// channel's trigger register; the channel will start if it is +// currently enabled and not already busy. +#define DMA_MULTI_CHAN_TRIGGER_OFFSET 0x00000430 +#define DMA_MULTI_CHAN_TRIGGER_BITS 0x0000ffff +#define DMA_MULTI_CHAN_TRIGGER_RESET 0x00000000 +#define DMA_MULTI_CHAN_TRIGGER_MSB 15 +#define DMA_MULTI_CHAN_TRIGGER_LSB 0 +#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" +// ============================================================================= +// Register : DMA_SNIFF_CTRL +// Description : Sniffer Control +#define DMA_SNIFF_CTRL_OFFSET 0x00000434 +#define DMA_SNIFF_CTRL_BITS 0x00000fff +#define DMA_SNIFF_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_INV +// Description : If set, the result appears inverted (bitwise complement) when +// read. This does not affect the way the checksum is calculated; +// the result is transformed on-the-fly between the result +// register and the bus. +#define DMA_SNIFF_CTRL_OUT_INV_RESET 0x0 +#define DMA_SNIFF_CTRL_OUT_INV_BITS 0x00000800 +#define DMA_SNIFF_CTRL_OUT_INV_MSB 11 +#define DMA_SNIFF_CTRL_OUT_INV_LSB 11 +#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_REV +// Description : If set, the result appears bit-reversed when read. This does +// not affect the way the checksum is calculated; the result is +// transformed on-the-fly between the result register and the bus. +#define DMA_SNIFF_CTRL_OUT_REV_RESET 0x0 +#define DMA_SNIFF_CTRL_OUT_REV_BITS 0x00000400 +#define DMA_SNIFF_CTRL_OUT_REV_MSB 10 +#define DMA_SNIFF_CTRL_OUT_REV_LSB 10 +#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_BSWAP +// Description : Locally perform a byte reverse on the sniffed data, before +// feeding into checksum. +// +// Note that the sniff hardware is downstream of the DMA channel +// byteswap performed in the read master: if channel CTRL_BSWAP +// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel +// from the sniffer's point of view. +#define DMA_SNIFF_CTRL_BSWAP_RESET 0x0 +#define DMA_SNIFF_CTRL_BSWAP_BITS 0x00000200 +#define DMA_SNIFF_CTRL_BSWAP_MSB 9 +#define DMA_SNIFF_CTRL_BSWAP_LSB 9 +#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_CALC +// Description : 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit +// reversed data +// 0x2 -> Calculate a CRC-16-CCITT +// 0x3 -> Calculate a CRC-16-CCITT with bit reversed data +// 0xe -> XOR reduction over all data. == 1 if the total 1 +// population count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 +// bit accumulator) +#define DMA_SNIFF_CTRL_CALC_RESET 0x0 +#define DMA_SNIFF_CTRL_CALC_BITS 0x000001e0 +#define DMA_SNIFF_CTRL_CALC_MSB 8 +#define DMA_SNIFF_CTRL_CALC_LSB 5 +#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 0x0 +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R 0x1 +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 0x2 +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R 0x3 +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN 0xe +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM 0xf +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_DMACH +// Description : DMA channel for Sniffer to observe +#define DMA_SNIFF_CTRL_DMACH_RESET 0x0 +#define DMA_SNIFF_CTRL_DMACH_BITS 0x0000001e +#define DMA_SNIFF_CTRL_DMACH_MSB 4 +#define DMA_SNIFF_CTRL_DMACH_LSB 1 +#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_EN +// Description : Enable sniffer +#define DMA_SNIFF_CTRL_EN_RESET 0x0 +#define DMA_SNIFF_CTRL_EN_BITS 0x00000001 +#define DMA_SNIFF_CTRL_EN_MSB 0 +#define DMA_SNIFF_CTRL_EN_LSB 0 +#define DMA_SNIFF_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_SNIFF_DATA +// Description : Data accumulator for sniff hardware +// Write an initial seed value here before starting a DMA transfer +// on the channel indicated by SNIFF_CTRL_DMACH. The hardware will +// update this register each time it observes a read from the +// indicated channel. Once the channel completes, the final result +// can be read from this register. +#define DMA_SNIFF_DATA_OFFSET 0x00000438 +#define DMA_SNIFF_DATA_BITS 0xffffffff +#define DMA_SNIFF_DATA_RESET 0x00000000 +#define DMA_SNIFF_DATA_MSB 31 +#define DMA_SNIFF_DATA_LSB 0 +#define DMA_SNIFF_DATA_ACCESS "RW" +// ============================================================================= +// Register : DMA_FIFO_LEVELS +// Description : Debug RAF, WAF, TDF levels +#define DMA_FIFO_LEVELS_OFFSET 0x00000440 +#define DMA_FIFO_LEVELS_BITS 0x00ffffff +#define DMA_FIFO_LEVELS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_RAF_LVL +// Description : Current Read-Address-FIFO fill level +#define DMA_FIFO_LEVELS_RAF_LVL_RESET 0x00 +#define DMA_FIFO_LEVELS_RAF_LVL_BITS 0x00ff0000 +#define DMA_FIFO_LEVELS_RAF_LVL_MSB 23 +#define DMA_FIFO_LEVELS_RAF_LVL_LSB 16 +#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_WAF_LVL +// Description : Current Write-Address-FIFO fill level +#define DMA_FIFO_LEVELS_WAF_LVL_RESET 0x00 +#define DMA_FIFO_LEVELS_WAF_LVL_BITS 0x0000ff00 +#define DMA_FIFO_LEVELS_WAF_LVL_MSB 15 +#define DMA_FIFO_LEVELS_WAF_LVL_LSB 8 +#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_TDF_LVL +// Description : Current Transfer-Data-FIFO fill level +#define DMA_FIFO_LEVELS_TDF_LVL_RESET 0x00 +#define DMA_FIFO_LEVELS_TDF_LVL_BITS 0x000000ff +#define DMA_FIFO_LEVELS_TDF_LVL_MSB 7 +#define DMA_FIFO_LEVELS_TDF_LVL_LSB 0 +#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CHAN_ABORT +// Description : Abort an in-progress transfer sequence on one or more channels +// Each bit corresponds to a channel. Writing a 1 aborts whatever +// transfer sequence is in progress on that channel. The bit will +// remain high until any in-flight transfers have been flushed +// through the address and data FIFOs. +// +// After writing, this register must be polled until it returns +// all-zero. Until this point, it is unsafe to restart the +// channel. +#define DMA_CHAN_ABORT_OFFSET 0x00000444 +#define DMA_CHAN_ABORT_BITS 0x0000ffff +#define DMA_CHAN_ABORT_RESET 0x00000000 +#define DMA_CHAN_ABORT_MSB 15 +#define DMA_CHAN_ABORT_LSB 0 +#define DMA_CHAN_ABORT_ACCESS "SC" +// ============================================================================= +// Register : DMA_N_CHANNELS +// Description : The number of channels this DMA instance is equipped with. This +// DMA supports up to 16 hardware channels, but can be configured +// with as few as one, to minimise silicon area. +#define DMA_N_CHANNELS_OFFSET 0x00000448 +#define DMA_N_CHANNELS_BITS 0x0000001f +#define DMA_N_CHANNELS_RESET "-" +#define DMA_N_CHANNELS_MSB 4 +#define DMA_N_CHANNELS_LSB 0 +#define DMA_N_CHANNELS_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH0_DBG_CTDREQ_OFFSET 0x00000800 +#define DMA_CH0_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH0_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH0_DBG_CTDREQ_MSB 5 +#define DMA_CH0_DBG_CTDREQ_LSB 0 +#define DMA_CH0_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH0_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH0_DBG_TCR_OFFSET 0x00000804 +#define DMA_CH0_DBG_TCR_BITS 0xffffffff +#define DMA_CH0_DBG_TCR_RESET 0x00000000 +#define DMA_CH0_DBG_TCR_MSB 31 +#define DMA_CH0_DBG_TCR_LSB 0 +#define DMA_CH0_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH1_DBG_CTDREQ_OFFSET 0x00000840 +#define DMA_CH1_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH1_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH1_DBG_CTDREQ_MSB 5 +#define DMA_CH1_DBG_CTDREQ_LSB 0 +#define DMA_CH1_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH1_DBG_TCR_OFFSET 0x00000844 +#define DMA_CH1_DBG_TCR_BITS 0xffffffff +#define DMA_CH1_DBG_TCR_RESET 0x00000000 +#define DMA_CH1_DBG_TCR_MSB 31 +#define DMA_CH1_DBG_TCR_LSB 0 +#define DMA_CH1_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH2_DBG_CTDREQ_OFFSET 0x00000880 +#define DMA_CH2_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH2_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH2_DBG_CTDREQ_MSB 5 +#define DMA_CH2_DBG_CTDREQ_LSB 0 +#define DMA_CH2_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH2_DBG_TCR_OFFSET 0x00000884 +#define DMA_CH2_DBG_TCR_BITS 0xffffffff +#define DMA_CH2_DBG_TCR_RESET 0x00000000 +#define DMA_CH2_DBG_TCR_MSB 31 +#define DMA_CH2_DBG_TCR_LSB 0 +#define DMA_CH2_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH3_DBG_CTDREQ_OFFSET 0x000008c0 +#define DMA_CH3_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH3_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH3_DBG_CTDREQ_MSB 5 +#define DMA_CH3_DBG_CTDREQ_LSB 0 +#define DMA_CH3_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH3_DBG_TCR_OFFSET 0x000008c4 +#define DMA_CH3_DBG_TCR_BITS 0xffffffff +#define DMA_CH3_DBG_TCR_RESET 0x00000000 +#define DMA_CH3_DBG_TCR_MSB 31 +#define DMA_CH3_DBG_TCR_LSB 0 +#define DMA_CH3_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH4_DBG_CTDREQ_OFFSET 0x00000900 +#define DMA_CH4_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH4_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH4_DBG_CTDREQ_MSB 5 +#define DMA_CH4_DBG_CTDREQ_LSB 0 +#define DMA_CH4_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH4_DBG_TCR_OFFSET 0x00000904 +#define DMA_CH4_DBG_TCR_BITS 0xffffffff +#define DMA_CH4_DBG_TCR_RESET 0x00000000 +#define DMA_CH4_DBG_TCR_MSB 31 +#define DMA_CH4_DBG_TCR_LSB 0 +#define DMA_CH4_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH5_DBG_CTDREQ_OFFSET 0x00000940 +#define DMA_CH5_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH5_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH5_DBG_CTDREQ_MSB 5 +#define DMA_CH5_DBG_CTDREQ_LSB 0 +#define DMA_CH5_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH5_DBG_TCR_OFFSET 0x00000944 +#define DMA_CH5_DBG_TCR_BITS 0xffffffff +#define DMA_CH5_DBG_TCR_RESET 0x00000000 +#define DMA_CH5_DBG_TCR_MSB 31 +#define DMA_CH5_DBG_TCR_LSB 0 +#define DMA_CH5_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH6_DBG_CTDREQ_OFFSET 0x00000980 +#define DMA_CH6_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH6_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH6_DBG_CTDREQ_MSB 5 +#define DMA_CH6_DBG_CTDREQ_LSB 0 +#define DMA_CH6_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH6_DBG_TCR_OFFSET 0x00000984 +#define DMA_CH6_DBG_TCR_BITS 0xffffffff +#define DMA_CH6_DBG_TCR_RESET 0x00000000 +#define DMA_CH6_DBG_TCR_MSB 31 +#define DMA_CH6_DBG_TCR_LSB 0 +#define DMA_CH6_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH7_DBG_CTDREQ_OFFSET 0x000009c0 +#define DMA_CH7_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH7_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH7_DBG_CTDREQ_MSB 5 +#define DMA_CH7_DBG_CTDREQ_LSB 0 +#define DMA_CH7_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH7_DBG_TCR_OFFSET 0x000009c4 +#define DMA_CH7_DBG_TCR_BITS 0xffffffff +#define DMA_CH7_DBG_TCR_RESET 0x00000000 +#define DMA_CH7_DBG_TCR_MSB 31 +#define DMA_CH7_DBG_TCR_LSB 0 +#define DMA_CH7_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH8_DBG_CTDREQ_OFFSET 0x00000a00 +#define DMA_CH8_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH8_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH8_DBG_CTDREQ_MSB 5 +#define DMA_CH8_DBG_CTDREQ_LSB 0 +#define DMA_CH8_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH8_DBG_TCR_OFFSET 0x00000a04 +#define DMA_CH8_DBG_TCR_BITS 0xffffffff +#define DMA_CH8_DBG_TCR_RESET 0x00000000 +#define DMA_CH8_DBG_TCR_MSB 31 +#define DMA_CH8_DBG_TCR_LSB 0 +#define DMA_CH8_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH9_DBG_CTDREQ_OFFSET 0x00000a40 +#define DMA_CH9_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH9_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH9_DBG_CTDREQ_MSB 5 +#define DMA_CH9_DBG_CTDREQ_LSB 0 +#define DMA_CH9_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH9_DBG_TCR_OFFSET 0x00000a44 +#define DMA_CH9_DBG_TCR_BITS 0xffffffff +#define DMA_CH9_DBG_TCR_RESET 0x00000000 +#define DMA_CH9_DBG_TCR_MSB 31 +#define DMA_CH9_DBG_TCR_LSB 0 +#define DMA_CH9_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH10_DBG_CTDREQ_OFFSET 0x00000a80 +#define DMA_CH10_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH10_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH10_DBG_CTDREQ_MSB 5 +#define DMA_CH10_DBG_CTDREQ_LSB 0 +#define DMA_CH10_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH10_DBG_TCR_OFFSET 0x00000a84 +#define DMA_CH10_DBG_TCR_BITS 0xffffffff +#define DMA_CH10_DBG_TCR_RESET 0x00000000 +#define DMA_CH10_DBG_TCR_MSB 31 +#define DMA_CH10_DBG_TCR_LSB 0 +#define DMA_CH10_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH11_DBG_CTDREQ_OFFSET 0x00000ac0 +#define DMA_CH11_DBG_CTDREQ_BITS 0x0000003f +#define DMA_CH11_DBG_CTDREQ_RESET 0x00000000 +#define DMA_CH11_DBG_CTDREQ_MSB 5 +#define DMA_CH11_DBG_CTDREQ_LSB 0 +#define DMA_CH11_DBG_CTDREQ_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH11_DBG_TCR_OFFSET 0x00000ac4 +#define DMA_CH11_DBG_TCR_BITS 0xffffffff +#define DMA_CH11_DBG_TCR_RESET 0x00000000 +#define DMA_CH11_DBG_TCR_MSB 31 +#define DMA_CH11_DBG_TCR_LSB 0 +#define DMA_CH11_DBG_TCR_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_DMA_DEFINED diff --git a/rp2040/hardware/regs/dreq.h b/rp2040/hardware/regs/dreq.h new file mode 100644 index 0000000..9de9dd5 --- /dev/null +++ b/rp2040/hardware/regs/dreq.h @@ -0,0 +1,50 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _DREQ_H_ +#define _DREQ_H_ + +#define DREQ_PIO0_TX0 0x0 +#define DREQ_PIO0_TX1 0x1 +#define DREQ_PIO0_TX2 0x2 +#define DREQ_PIO0_TX3 0x3 +#define DREQ_PIO0_RX0 0x4 +#define DREQ_PIO0_RX1 0x5 +#define DREQ_PIO0_RX2 0x6 +#define DREQ_PIO0_RX3 0x7 +#define DREQ_PIO1_TX0 0x8 +#define DREQ_PIO1_TX1 0x9 +#define DREQ_PIO1_TX2 0xa +#define DREQ_PIO1_TX3 0xb +#define DREQ_PIO1_RX0 0xc +#define DREQ_PIO1_RX1 0xd +#define DREQ_PIO1_RX2 0xe +#define DREQ_PIO1_RX3 0xf +#define DREQ_SPI0_TX 0x10 +#define DREQ_SPI0_RX 0x11 +#define DREQ_SPI1_TX 0x12 +#define DREQ_SPI1_RX 0x13 +#define DREQ_UART0_TX 0x14 +#define DREQ_UART0_RX 0x15 +#define DREQ_UART1_TX 0x16 +#define DREQ_UART1_RX 0x17 +#define DREQ_PWM_WRAP0 0x18 +#define DREQ_PWM_WRAP1 0x19 +#define DREQ_PWM_WRAP2 0x1a +#define DREQ_PWM_WRAP3 0x1b +#define DREQ_PWM_WRAP4 0x1c +#define DREQ_PWM_WRAP5 0x1d +#define DREQ_PWM_WRAP6 0x1e +#define DREQ_PWM_WRAP7 0x1f +#define DREQ_I2C0_TX 0x20 +#define DREQ_I2C0_RX 0x21 +#define DREQ_I2C1_TX 0x22 +#define DREQ_I2C1_RX 0x23 +#define DREQ_ADC 0x24 +#define DREQ_XIP_STREAM 0x25 +#define DREQ_XIP_SSITX 0x26 +#define DREQ_XIP_SSIRX 0x27 + +#endif // _DREQ_H_ diff --git a/rp2040/hardware/regs/i2c.h b/rp2040/hardware/regs/i2c.h new file mode 100644 index 0000000..c027119 --- /dev/null +++ b/rp2040/hardware/regs/i2c.h @@ -0,0 +1,2685 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : I2C +// Version : 1 +// Bus type : apb +// Description : DW_apb_i2c address block +// ============================================================================= +#ifndef HARDWARE_REGS_I2C_DEFINED +#define HARDWARE_REGS_I2C_DEFINED +// ============================================================================= +// Register : I2C_IC_CON +// Description : I2C Control Register. This register can be written only when +// the DW_apb_i2c is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// Read/Write Access: - bit 10 is read only. - bit 11 is read only +// - bit 16 is read only - bit 17 is read only - bits 18 and 19 +// are read only. +#define I2C_IC_CON_OFFSET 0x00000000 +#define I2C_IC_CON_BITS 0x000007ff +#define I2C_IC_CON_RESET 0x00000065 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE +// Description : Master issues the STOP_DET interrupt irrespective of whether +// master is active or not +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET 0x0 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS 0x00000400 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB 10 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB 10 +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL +// Description : This bit controls whether DW_apb_i2c should hold the bus when +// the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as +// described in the IC_RX_FULL_HLD_BUS_EN parameter. +// +// Reset value: 0x0. +// 0x0 -> Overflow when RX_FIFO is full +// 0x1 -> Hold bus when RX_FIFO is full +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET 0x0 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS 0x00000200 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB 9 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB 9 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED 0x0 +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_TX_EMPTY_CTRL +// Description : This bit controls the generation of the TX_EMPTY interrupt, as +// described in the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0. +// 0x0 -> Default behaviour of TX_EMPTY interrupt +// 0x1 -> Controlled generation of TX_EMPTY interrupt +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET 0x0 +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS 0x00000100 +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB 8 +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB 8 +#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED 0x0 +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IFADDRESSED +// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when +// it is addressed. - 1'b0: issues the STOP_DET irrespective of +// whether it's addressed or not. Reset value: 0x0 +// +// NOTE: During a general call address, this slave does not issue +// the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if +// the slave responds to the general call address by generating +// ACK. The STOP_DET interrupt is generated only when the +// transmitted address matches the slave address (SAR). +// 0x0 -> slave issues STOP_DET intr always +// 0x1 -> slave issues STOP_DET intr only if addressed +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET 0x0 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS 0x00000080 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB 7 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB 7 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED 0x0 +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_SLAVE_DISABLE +// Description : This bit controls whether I2C has its slave disabled, which +// means once the presetn signal is applied, then this bit is set +// and the slave is disabled. +// +// If this bit is set (slave is disabled), DW_apb_i2c functions +// only as a master and does not perform any action that requires +// a slave. +// +// NOTE: Software should ensure that if this bit is written with +// 0, then bit 0 should also be written with a 0. +// 0x0 -> Slave mode is enabled +// 0x1 -> Slave mode is disabled +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET 0x1 +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS 0x00000040 +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB 6 +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB 6 +#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED 0x0 +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_RESTART_EN +// Description : Determines whether RESTART conditions may be sent when acting +// as a master. Some older slaves do not support handling RESTART +// conditions; however, RESTART conditions are used in several +// DW_apb_i2c operations. When RESTART is disabled, the master is +// prohibited from performing the following functions: - Sending a +// START BYTE - Performing any high-speed mode operation - +// High-speed mode operation - Performing direction changes in +// combined format mode - Performing a read operation with a +// 10-bit address By replacing RESTART condition followed by a +// STOP and a subsequent START condition, split operations are +// broken down into multiple DW_apb_i2c transfers. If the above +// operations are performed, it will result in setting bit 6 +// (TX_ABRT) of the IC_RAW_INTR_STAT register. +// +// Reset value: ENABLED +// 0x0 -> Master restart disabled +// 0x1 -> Master restart enabled +#define I2C_IC_CON_IC_RESTART_EN_RESET 0x1 +#define I2C_IC_CON_IC_RESTART_EN_BITS 0x00000020 +#define I2C_IC_CON_IC_RESTART_EN_MSB 5 +#define I2C_IC_CON_IC_RESTART_EN_LSB 5 +#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" +#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED 0x0 +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_MASTER +// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or +// 10-bit addressing mode when acting as a master. - 0: 7-bit +// addressing - 1: 10-bit addressing +// 0x0 -> Master 7Bit addressing mode +// 0x1 -> Master 10Bit addressing mode +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET 0x0 +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS 0x00000010 +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB 4 +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB 4 +#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS 0x0 +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_SLAVE +// Description : When acting as a slave, this bit controls whether the +// DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit +// addressing. The DW_apb_i2c ignores transactions that involve +// 10-bit addressing; for 7-bit addressing, only the lower 7 bits +// of the IC_SAR register are compared. - 1: 10-bit addressing. +// The DW_apb_i2c responds to only 10-bit addressing transfers +// that match the full 10 bits of the IC_SAR register. +// 0x0 -> Slave 7Bit addressing +// 0x1 -> Slave 10Bit addressing +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET 0x0 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS 0x00000008 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB 3 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB 3 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS 0x0 +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_SPEED +// Description : These bits control at which speed the DW_apb_i2c operates; its +// setting is relevant only if one is operating the DW_apb_i2c in +// master mode. Hardware protects against illegal values being +// programmed by software. These bits must be programmed +// appropriately for slave mode also, as it is used to capture +// correct value of spike filter as per the speed mode. +// +// This register should be programmed only with a value in the +// range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates +// this register with the value of IC_MAX_SPEED_MODE. +// +// 1: standard mode (100 kbit/s) +// +// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) +// +// 3: high speed mode (3.4 Mbit/s) +// +// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 +// 0x1 -> Standard Speed mode of operation +// 0x2 -> Fast or Fast Plus mode of operation +// 0x3 -> High Speed mode of operation +#define I2C_IC_CON_SPEED_RESET 0x2 +#define I2C_IC_CON_SPEED_BITS 0x00000006 +#define I2C_IC_CON_SPEED_MSB 2 +#define I2C_IC_CON_SPEED_LSB 1 +#define I2C_IC_CON_SPEED_ACCESS "RW" +#define I2C_IC_CON_SPEED_VALUE_STANDARD 0x1 +#define I2C_IC_CON_SPEED_VALUE_FAST 0x2 +#define I2C_IC_CON_SPEED_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_MASTER_MODE +// Description : This bit controls whether the DW_apb_i2c master is enabled. +// +// NOTE: Software should ensure that if this bit is written with +// '1' then bit 6 should also be written with a '1'. +// 0x0 -> Master mode is disabled +// 0x1 -> Master mode is enabled +#define I2C_IC_CON_MASTER_MODE_RESET 0x1 +#define I2C_IC_CON_MASTER_MODE_BITS 0x00000001 +#define I2C_IC_CON_MASTER_MODE_MSB 0 +#define I2C_IC_CON_MASTER_MODE_LSB 0 +#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" +#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED 0x0 +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_TAR +// Description : I2C Target Address Register +// +// This register is 12 bits wide, and bits 31:12 are reserved. +// This register can be written to only when IC_ENABLE[0] is set +// to 0. +// +// Note: If the software or application is aware that the +// DW_apb_i2c is not using the TAR address for the pending +// commands in the Tx FIFO, then it is possible to update the TAR +// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - +// It is not necessary to perform any write to this register if +// DW_apb_i2c is enabled as an I2C slave only. +#define I2C_IC_TAR_OFFSET 0x00000004 +#define I2C_IC_TAR_BITS 0x00000fff +#define I2C_IC_TAR_RESET 0x00000055 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_SPECIAL +// Description : This bit indicates whether software performs a Device-ID or +// General Call or START BYTE command. - 0: ignore bit 10 +// GC_OR_START and use IC_TAR normally - 1: perform special I2C +// command as specified in Device_ID or GC_OR_START bit Reset +// value: 0x0 +// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE +// transmission +// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE +// transmission +#define I2C_IC_TAR_SPECIAL_RESET 0x0 +#define I2C_IC_TAR_SPECIAL_BITS 0x00000800 +#define I2C_IC_TAR_SPECIAL_MSB 11 +#define I2C_IC_TAR_SPECIAL_LSB 11 +#define I2C_IC_TAR_SPECIAL_ACCESS "RW" +#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED 0x0 +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_GC_OR_START +// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to +// 0, then this bit indicates whether a General Call or START byte +// command is to be performed by the DW_apb_i2c. - 0: General Call +// Address - after issuing a General Call, only writes may be +// performed. Attempting to issue a read command results in +// setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The +// DW_apb_i2c remains in General Call mode until the SPECIAL bit +// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 +// 0x0 -> GENERAL_CALL byte transmission +// 0x1 -> START byte transmission +#define I2C_IC_TAR_GC_OR_START_RESET 0x0 +#define I2C_IC_TAR_GC_OR_START_BITS 0x00000400 +#define I2C_IC_TAR_GC_OR_START_MSB 10 +#define I2C_IC_TAR_GC_OR_START_LSB 10 +#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" +#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL 0x0 +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_IC_TAR +// Description : This is the target address for any master transaction. When +// transmitting a General Call, these bits are ignored. To +// generate a START BYTE, the CPU needs to write only once into +// these bits. +// +// If the IC_TAR and IC_SAR are the same, loopback exists but the +// FIFOs are shared between master and slave, so full loopback is +// not feasible. Only one direction loopback mode is supported +// (simplex), not duplex. A master cannot transmit to itself; it +// can transmit to only a slave. +#define I2C_IC_TAR_IC_TAR_RESET 0x055 +#define I2C_IC_TAR_IC_TAR_BITS 0x000003ff +#define I2C_IC_TAR_IC_TAR_MSB 9 +#define I2C_IC_TAR_IC_TAR_LSB 0 +#define I2C_IC_TAR_IC_TAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SAR +// Description : I2C Slave Address Register +#define I2C_IC_SAR_OFFSET 0x00000008 +#define I2C_IC_SAR_BITS 0x000003ff +#define I2C_IC_SAR_RESET 0x00000055 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SAR_IC_SAR +// Description : The IC_SAR holds the slave address when the I2C is operating as +// a slave. For 7-bit addressing, only IC_SAR[6:0] is used. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// Note: The default values cannot be any of the reserved address +// locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct +// operation of the device is not guaranteed if you program the +// IC_SAR or IC_TAR to a reserved value. Refer to +// <> for a complete list of these +// reserved values. +#define I2C_IC_SAR_IC_SAR_RESET 0x055 +#define I2C_IC_SAR_IC_SAR_BITS 0x000003ff +#define I2C_IC_SAR_IC_SAR_MSB 9 +#define I2C_IC_SAR_IC_SAR_LSB 0 +#define I2C_IC_SAR_IC_SAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DATA_CMD +// Description : I2C Rx/Tx Data Buffer and Command Register; this is the +// register the CPU writes to when filling the TX FIFO and the CPU +// reads from when retrieving bytes from RX FIFO. +// +// The size of the register changes as follows: +// +// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits +// when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when +// IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when +// IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c +// to continue acknowledging reads, a read command should be +// written for every byte that is to be received; otherwise the +// DW_apb_i2c will stop acknowledging. +#define I2C_IC_DATA_CMD_OFFSET 0x00000010 +#define I2C_IC_DATA_CMD_BITS 0x00000fff +#define I2C_IC_DATA_CMD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE +// Description : Indicates the first data byte received after the address phase +// for receive transfer in Master receiver or Slave receiver mode. +// +// Reset value : 0x0 +// +// NOTE: In case of APB_DATA_WIDTH=8, +// +// 1. The user has to perform two APB Reads to IC_DATA_CMD in +// order to get status on 11 bit. +// +// 2. In order to read the 11 bit, the user has to perform the +// first data byte read [7:0] (offset 0x10) and then perform the +// second read [15:8] (offset 0x11) in order to know the status of +// 11 bit (whether the data received in previous read is a first +// data byte or not). +// +// 3. The 11th bit is an optional read field, user can ignore 2nd +// byte read [15:8] (offset 0x11) if not interested in +// FIRST_DATA_BYTE status. +// 0x0 -> Sequential data byte received +// 0x1 -> Non sequential data byte received +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET 0x0 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS 0x00000800 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB 11 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB 11 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE 0x0 +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_RESTART +// Description : This bit controls whether a RESTART is issued before the byte +// is sent or received. +// +// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data +// is sent/received (according to the value of CMD), regardless of +// whether or not the transfer direction is changing from the +// previous command; if IC_RESTART_EN is 0, a STOP followed by a +// START is issued instead. +// +// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the +// transfer direction is changing from the previous command; if +// IC_RESTART_EN is 0, a STOP followed by a START is issued +// instead. +// +// Reset value: 0x0 +// 0x0 -> Don't Issue RESTART before this command +// 0x1 -> Issue RESTART before this command +#define I2C_IC_DATA_CMD_RESTART_RESET 0x0 +#define I2C_IC_DATA_CMD_RESTART_BITS 0x00000400 +#define I2C_IC_DATA_CMD_RESTART_MSB 10 +#define I2C_IC_DATA_CMD_RESTART_LSB 10 +#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" +#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE 0x0 +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_STOP +// Description : This bit controls whether a STOP is issued after the byte is +// sent or received. +// +// - 1 - STOP is issued after this byte, regardless of whether or +// not the Tx FIFO is empty. If the Tx FIFO is not empty, the +// master immediately tries to start a new transfer by issuing a +// START and arbitrating for the bus. - 0 - STOP is not issued +// after this byte, regardless of whether or not the Tx FIFO is +// empty. If the Tx FIFO is not empty, the master continues the +// current transfer by sending/receiving data bytes according to +// the value of the CMD bit. If the Tx FIFO is empty, the master +// holds the SCL line low and stalls the bus until a new command +// is available in the Tx FIFO. Reset value: 0x0 +// 0x0 -> Don't Issue STOP after this command +// 0x1 -> Issue STOP after this command +#define I2C_IC_DATA_CMD_STOP_RESET 0x0 +#define I2C_IC_DATA_CMD_STOP_BITS 0x00000200 +#define I2C_IC_DATA_CMD_STOP_MSB 9 +#define I2C_IC_DATA_CMD_STOP_LSB 9 +#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" +#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE 0x0 +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_CMD +// Description : This bit controls whether a read or a write is performed. This +// bit does not control the direction when the DW_apb_i2con acts +// as a slave. It controls only the direction when it acts as a +// master. +// +// When a command is entered in the TX FIFO, this bit +// distinguishes the write and read commands. In slave-receiver +// mode, this bit is a 'don't care' because writes to this +// register are not required. In slave-transmitter mode, a '0' +// indicates that the data in IC_DATA_CMD is to be transmitted. +// +// When programming this bit, you should remember the following: +// attempting to perform a read operation after a General Call +// command has been sent results in a TX_ABRT interrupt (bit 6 of +// the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the +// IC_TAR register has been cleared. If a '1' is written to this +// bit after receiving a RD_REQ interrupt, then a TX_ABRT +// interrupt occurs. +// +// Reset value: 0x0 +// 0x0 -> Master Write Command +// 0x1 -> Master Read Command +#define I2C_IC_DATA_CMD_CMD_RESET 0x0 +#define I2C_IC_DATA_CMD_CMD_BITS 0x00000100 +#define I2C_IC_DATA_CMD_CMD_MSB 8 +#define I2C_IC_DATA_CMD_CMD_LSB 8 +#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" +#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE 0x0 +#define I2C_IC_DATA_CMD_CMD_VALUE_READ 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_DAT +// Description : This register contains the data to be transmitted or received +// on the I2C bus. If you are writing to this register and want to +// perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. +// However, when you read this register, these bits return the +// value of data received on the DW_apb_i2c interface. +// +// Reset value: 0x0 +#define I2C_IC_DATA_CMD_DAT_RESET 0x00 +#define I2C_IC_DATA_CMD_DAT_BITS 0x000000ff +#define I2C_IC_DATA_CMD_DAT_MSB 7 +#define I2C_IC_DATA_CMD_DAT_LSB 0 +#define I2C_IC_DATA_CMD_DAT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_HCNT +// Description : Standard Speed I2C Clock SCL High Count Register +#define I2C_IC_SS_SCL_HCNT_OFFSET 0x00000014 +#define I2C_IC_SS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_HCNT_RESET 0x00000028 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration'. +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +// +// NOTE: This register must not be programmed to a value higher +// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an +// I2C bus idle condition when this counter reaches a value of +// IC_SS_SCL_HCNT + 10. +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x0028 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0 +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_LCNT +// Description : Standard Speed I2C Clock SCL Low Count Register +#define I2C_IC_SS_SCL_LCNT_OFFSET 0x00000018 +#define I2C_IC_SS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_LCNT_RESET 0x0000002f +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration' +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted, results in 8 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of +// DW_apb_i2c. The lower byte must be programmed first, and then +// the upper byte is programmed. +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x002f +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15 +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0 +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_HCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register +#define I2C_IC_FS_SCL_HCNT_OFFSET 0x0000001c +#define I2C_IC_FS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_HCNT_RESET 0x00000006 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for fast mode or fast mode plus. It +// is used in high-speed mode to send the Master Code and START +// BYTE or General CALL. For more information, refer to 'IC_CLK +// Frequency Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. This register can be written only +// when the I2C interface is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH == 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x0006 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0 +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_LCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register +#define I2C_IC_FS_SCL_LCNT_OFFSET 0x00000020 +#define I2C_IC_FS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_LCNT_RESET 0x0000000d +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for fast speed. It is used in +// high-speed mode to send the Master Code and START BYTE or +// General CALL. For more information, refer to 'IC_CLK Frequency +// Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted results in 8 being +// set. For designs with APB_DATA_WIDTH = 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. If the value is less than 8 then the +// count value gets changed to 8. +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x000d +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS 0x0000ffff +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15 +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0 +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_INTR_STAT +// Description : I2C Interrupt Status Register +// +// Each bit in this register has a corresponding mask bit in the +// IC_INTR_MASK register. These bits are cleared by reading the +// matching interrupt clear register. The unmasked raw versions of +// these bits are available in the IC_RAW_INTR_STAT register. +#define I2C_IC_INTR_STAT_OFFSET 0x0000002c +#define I2C_IC_INTR_STAT_BITS 0x00003fff +#define I2C_IC_INTR_STAT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_MASTER_ON_HOLD +// Description : See IC_RAW_INTR_STAT for a detailed description of +// R_MASTER_ON_HOLD bit. +// +// Reset value: 0x0 +// 0x0 -> R_MASTER_ON_HOLD interrupt is inactive +// 0x1 -> R_MASTER_ON_HOLD interrupt is active +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_RESET 0x0 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_BITS 0x00002000 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_MSB 13 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_LSB 13 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RESTART_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of +// R_RESTART_DET bit. +// +// Reset value: 0x0 +// 0x0 -> R_RESTART_DET interrupt is inactive +// 0x1 -> R_RESTART_DET interrupt is active +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS 0x00001000 +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB 12 +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB 12 +#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_GEN_CALL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_GEN_CALL interrupt is inactive +// 0x1 -> R_GEN_CALL interrupt is active +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET 0x0 +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS 0x00000800 +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB 11 +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB 11 +#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_START_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_START_DET interrupt is inactive +// 0x1 -> R_START_DET interrupt is active +#define I2C_IC_INTR_STAT_R_START_DET_RESET 0x0 +#define I2C_IC_INTR_STAT_R_START_DET_BITS 0x00000400 +#define I2C_IC_INTR_STAT_R_START_DET_MSB 10 +#define I2C_IC_INTR_STAT_R_START_DET_LSB 10 +#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_STOP_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_STOP_DET interrupt is inactive +// 0x1 -> R_STOP_DET interrupt is active +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET 0x0 +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS 0x00000200 +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB 9 +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB 9 +#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_ACTIVITY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_ACTIVITY interrupt is inactive +// 0x1 -> R_ACTIVITY interrupt is active +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET 0x0 +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS 0x00000100 +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB 8 +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB 8 +#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_DONE +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_DONE interrupt is inactive +// 0x1 -> R_RX_DONE interrupt is active +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS 0x00000080 +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB 7 +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB 7 +#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_ABRT +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_ABRT interrupt is inactive +// 0x1 -> R_TX_ABRT interrupt is active +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET 0x0 +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS 0x00000040 +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB 6 +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB 6 +#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RD_REQ +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RD_REQ interrupt is inactive +// 0x1 -> R_RD_REQ interrupt is active +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS 0x00000020 +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB 5 +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB 5 +#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_EMPTY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_EMPTY interrupt is inactive +// 0x1 -> R_TX_EMPTY interrupt is active +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET 0x0 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS 0x00000010 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB 4 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_OVER interrupt is inactive +// 0x1 -> R_TX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET 0x0 +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS 0x00000008 +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB 3 +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB 3 +#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_FULL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_FULL interrupt is inactive +// 0x1 -> R_RX_FULL interrupt is active +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS 0x00000004 +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB 2 +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB 2 +#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_OVER interrupt is inactive +// 0x1 -> R_RX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS 0x00000002 +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB 1 +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB 1 +#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_UNDER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER +// bit. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET 0x0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS 0x00000001 +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB 0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB 0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE 0x0 +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_INTR_MASK +// Description : I2C Interrupt Mask Register. +// +// These bits mask their corresponding interrupt status bits. This +// register is active low; a value of 0 masks the interrupt, +// whereas a value of 1 unmasks the interrupt. +#define I2C_IC_INTR_MASK_OFFSET 0x00000030 +#define I2C_IC_INTR_MASK_BITS 0x00003fff +#define I2C_IC_INTR_MASK_RESET 0x000008ff +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY +// Description : This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD +// interrupt in IC_INTR_STAT register. +// +// Reset value: 0x0 +// 0x0 -> MASTER_ON_HOLD interrupt is masked +// 0x1 -> MASTER_ON_HOLD interrupt is unmasked +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_RESET 0x0 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_BITS 0x00002000 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_MSB 13 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_LSB 13 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ACCESS "RO" +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RESTART_DET +// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is masked +// 0x1 -> RESTART_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET 0x0 +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS 0x00001000 +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB 12 +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB 12 +#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_GEN_CALL +// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> GEN_CALL interrupt is masked +// 0x1 -> GEN_CALL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET 0x1 +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS 0x00000800 +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB 11 +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB 11 +#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_START_DET +// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is masked +// 0x1 -> START_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_START_DET_RESET 0x0 +#define I2C_IC_INTR_MASK_M_START_DET_BITS 0x00000400 +#define I2C_IC_INTR_MASK_M_START_DET_MSB 10 +#define I2C_IC_INTR_MASK_M_START_DET_LSB 10 +#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_STOP_DET +// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is masked +// 0x1 -> STOP_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET 0x0 +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS 0x00000200 +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB 9 +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB 9 +#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_ACTIVITY +// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> ACTIVITY interrupt is masked +// 0x1 -> ACTIVITY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET 0x0 +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS 0x00000100 +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB 8 +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB 8 +#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_DONE +// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_DONE interrupt is masked +// 0x1 -> RX_DONE interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS 0x00000080 +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB 7 +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB 7 +#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_ABRT +// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_ABORT interrupt is masked +// 0x1 -> TX_ABORT interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET 0x1 +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS 0x00000040 +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB 6 +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB 6 +#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RD_REQ +// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. +// +// Reset value: 0x1 +// 0x0 -> RD_REQ interrupt is masked +// 0x1 -> RD_REQ interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS 0x00000020 +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB 5 +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB 5 +#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_EMPTY +// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_EMPTY interrupt is masked +// 0x1 -> TX_EMPTY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET 0x1 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS 0x00000010 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB 4 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB 4 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_OVER +// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_OVER interrupt is masked +// 0x1 -> TX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET 0x1 +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS 0x00000008 +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB 3 +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB 3 +#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_FULL +// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_FULL interrupt is masked +// 0x1 -> RX_FULL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS 0x00000004 +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB 2 +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB 2 +#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_OVER +// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_OVER interrupt is masked +// 0x1 -> RX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS 0x00000002 +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB 1 +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB 1 +#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_UNDER +// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_UNDER interrupt is masked +// 0x1 -> RX_UNDER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET 0x1 +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS 0x00000001 +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB 0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB 0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED 0x0 +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED 0x1 +// ============================================================================= +// Register : I2C_IC_RAW_INTR_STAT +// Description : I2C Raw Interrupt Status Register +// +// Unlike the IC_INTR_STAT register, these bits are not masked so +// they always show the true status of the DW_apb_i2c. +#define I2C_IC_RAW_INTR_STAT_OFFSET 0x00000034 +#define I2C_IC_RAW_INTR_STAT_BITS 0x00003fff +#define I2C_IC_RAW_INTR_STAT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD +// Description : Indicates whether master is holding the bus and TX FIFO is +// empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and +// IC_EMPTYFIFO_HOLD_MASTER_EN=1. +// +// Reset value: 0x0 +// 0x0 -> MASTER_ON_HOLD interrupt is inactive +// 0x1 -> MASTER_ON_HOLD interrupt is active +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_BITS 0x00002000 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_MSB 13 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_LSB 13 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_MASTER_ON_HOLD_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET +// Description : Indicates whether a RESTART condition has occurred on the I2C +// interface when DW_apb_i2c is operating in Slave mode and the +// slave is being addressed. Enabled only when +// IC_SLV_RESTART_DET_EN=1. +// +// Note: However, in high-speed mode or during a START BYTE +// transfer, the RESTART comes before the address field as per the +// I2C protocol. In this case, the slave is not the addressed +// slave when the RESTART is issued, therefore DW_apb_i2c does not +// generate the RESTART_DET interrupt. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is inactive +// 0x1 -> RESTART_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS 0x00001000 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB 12 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB 12 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL +// Description : Set only when a General Call address is received and it is +// acknowledged. It stays set until it is cleared either by +// disabling DW_apb_i2c or when the CPU reads bit 0 of the +// IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data +// in the Rx buffer. +// +// Reset value: 0x0 +// 0x0 -> GEN_CALL interrupt is inactive +// 0x1 -> GEN_CALL interrupt is active +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS 0x00000800 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB 11 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB 11 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_START_DET +// Description : Indicates whether a START or RESTART condition has occurred on +// the I2C interface regardless of whether DW_apb_i2c is operating +// in slave or master mode. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is inactive +// 0x1 -> START_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS 0x00000400 +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB 10 +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB 10 +#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_STOP_DET +// Description : Indicates whether a STOP condition has occurred on the I2C +// interface regardless of whether DW_apb_i2c is operating in +// slave or master mode. +// +// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the +// STOP_DET interrupt will be issued only if slave is addressed. +// Note: During a general call address, this slave does not issue +// a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the +// slave responds to the general call address by generating ACK. +// The STOP_DET interrupt is generated only when the transmitted +// address matches the slave address (SAR). - If IC_CON[7]=1'b0 +// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued +// irrespective of whether it is being addressed. In Master Mode: +// - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET +// interrupt will be issued only if Master is active. - If +// IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt +// will be issued irrespective of whether master is active or not. +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is inactive +// 0x1 -> STOP_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS 0x00000200 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB 9 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB 9 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY +// Description : This bit captures DW_apb_i2c activity and stays set until it is +// cleared. There are four ways to clear it: - Disabling the +// DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the +// IC_CLR_INTR register - System reset Once this bit is set, it +// stays set unless one of the four methods is used to clear it. +// Even if the DW_apb_i2c module is idle, this bit remains set +// until cleared, indicating that there was activity on the bus. +// +// Reset value: 0x0 +// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive +// 0x1 -> RAW_INTR_ACTIVITY interrupt is active +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS 0x00000100 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB 8 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB 8 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_DONE +// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit +// is set to 1 if the master does not acknowledge a transmitted +// byte. This occurs on the last byte of the transmission, +// indicating that the transmission is done. +// +// Reset value: 0x0 +// 0x0 -> RX_DONE interrupt is inactive +// 0x1 -> RX_DONE interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS 0x00000080 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB 7 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB 7 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT +// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is +// unable to complete the intended actions on the contents of the +// transmit FIFO. This situation can occur both as an I2C master +// or an I2C slave, and is referred to as a 'transmit abort'. When +// this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates +// the reason why the transmit abort takes places. +// +// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and +// RX_FIFO whenever there is a transmit abort caused by any of the +// events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs +// remains in this flushed state until the register IC_CLR_TX_ABRT +// is read. Once this read is performed, the Tx FIFO is then ready +// to accept more data bytes from the APB interface. +// +// Reset value: 0x0 +// 0x0 -> TX_ABRT interrupt is inactive +// 0x1 -> TX_ABRT interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS 0x00000040 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB 6 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB 6 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RD_REQ +// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and +// another I2C master is attempting to read data from DW_apb_i2c. +// The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until +// this interrupt is serviced, which means that the slave has been +// addressed by a remote master that is asking for data to be +// transferred. The processor must respond to this interrupt and +// then write the requested data to the IC_DATA_CMD register. This +// bit is set to 0 just after the processor reads the +// IC_CLR_RD_REQ register. +// +// Reset value: 0x0 +// 0x0 -> RD_REQ interrupt is inactive +// 0x1 -> RD_REQ interrupt is active +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS 0x00000020 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB 5 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB 5 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY +// Description : The behavior of the TX_EMPTY interrupt status differs based on +// the TX_EMPTY_CTRL selection in the IC_CON register. - When +// TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit +// buffer is at or below the threshold value set in the IC_TX_TL +// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when +// the transmit buffer is at or below the threshold value set in +// the IC_TX_TL register and the transmission of the address/data +// from the internal shift register for the most recently popped +// command is completed. It is automatically cleared by hardware +// when the buffer level goes above the threshold. When +// IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in +// reset. There the TX FIFO looks like it has no data within it, +// so this bit is set to 1, provided there is activity in the +// master or slave state machines. When there is no longer any +// activity, then with ic_en=0, this bit is set to 0. +// +// Reset value: 0x0. +// 0x0 -> TX_EMPTY interrupt is inactive +// 0x1 -> TX_EMPTY interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS 0x00000010 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB 4 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB 4 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_OVER +// Description : Set during transmit if the transmit buffer is filled to +// IC_TX_BUFFER_DEPTH and the processor attempts to issue another +// I2C command by writing to the IC_DATA_CMD register. When the +// module is disabled, this bit keeps its level until the master +// or slave state machines go into idle, and when ic_en goes to 0, +// this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> TX_OVER interrupt is inactive +// 0x1 -> TX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS 0x00000008 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB 3 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB 3 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_FULL +// Description : Set when the receive buffer reaches or goes above the RX_TL +// threshold in the IC_RX_TL register. It is automatically cleared +// by hardware when buffer level goes below the threshold. If the +// module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and +// held in reset; therefore the RX FIFO is not full. So this bit +// is cleared once the IC_ENABLE bit 0 is programmed with a 0, +// regardless of the activity that continues. +// +// Reset value: 0x0 +// 0x0 -> RX_FULL interrupt is inactive +// 0x1 -> RX_FULL interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS 0x00000004 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB 2 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB 2 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_OVER +// Description : Set if the receive buffer is completely filled to +// IC_RX_BUFFER_DEPTH and an additional byte is received from an +// external I2C device. The DW_apb_i2c acknowledges this, but any +// data bytes received after the FIFO is full are lost. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) +// is programmed to HIGH, then the RX_OVER interrupt never occurs, +// because the Rx FIFO never overflows. +// +// Reset value: 0x0 +// 0x0 -> RX_OVER interrupt is inactive +// 0x1 -> RX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS 0x00000002 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB 1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB 1 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER +// Description : Set if the processor attempts to read the receive buffer when +// it is empty by reading from the IC_DATA_CMD register. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS 0x00000001 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB 0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB 0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE 0x0 +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_RX_TL +// Description : I2C Receive FIFO Threshold Register +#define I2C_IC_RX_TL_OFFSET 0x00000038 +#define I2C_IC_RX_TL_BITS 0x000000ff +#define I2C_IC_RX_TL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RX_TL_RX_TL +// Description : Receive FIFO Threshold Level. +// +// Controls the level of entries (or above) that triggers the +// RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that +// hardware does not allow this value to be set to a value larger +// than the depth of the buffer. If an attempt is made to do that, +// the actual value set will be the maximum depth of the buffer. A +// value of 0 sets the threshold for 1 entry, and a value of 255 +// sets the threshold for 256 entries. +#define I2C_IC_RX_TL_RX_TL_RESET 0x00 +#define I2C_IC_RX_TL_RX_TL_BITS 0x000000ff +#define I2C_IC_RX_TL_RX_TL_MSB 7 +#define I2C_IC_RX_TL_RX_TL_LSB 0 +#define I2C_IC_RX_TL_RX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_TL +// Description : I2C Transmit FIFO Threshold Register +#define I2C_IC_TX_TL_OFFSET 0x0000003c +#define I2C_IC_TX_TL_BITS 0x000000ff +#define I2C_IC_TX_TL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_TL_TX_TL +// Description : Transmit FIFO Threshold Level. +// +// Controls the level of entries (or below) that trigger the +// TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that it +// may not be set to value larger than the depth of the buffer. If +// an attempt is made to do that, the actual value set will be the +// maximum depth of the buffer. A value of 0 sets the threshold +// for 0 entries, and a value of 255 sets the threshold for 255 +// entries. +#define I2C_IC_TX_TL_TX_TL_RESET 0x00 +#define I2C_IC_TX_TL_TX_TL_BITS 0x000000ff +#define I2C_IC_TX_TL_TX_TL_MSB 7 +#define I2C_IC_TX_TL_TX_TL_LSB 0 +#define I2C_IC_TX_TL_TX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_INTR +// Description : Clear Combined and Individual Interrupt Register +#define I2C_IC_CLR_INTR_OFFSET 0x00000040 +#define I2C_IC_CLR_INTR_BITS 0x00000001 +#define I2C_IC_CLR_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_INTR_CLR_INTR +// Description : Read this register to clear the combined interrupt, all +// individual interrupts, and the IC_TX_ABRT_SOURCE register. This +// bit does not clear hardware clearable interrupts but software +// clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE +// register for an exception to clearing IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_INTR_CLR_INTR_RESET 0x0 +#define I2C_IC_CLR_INTR_CLR_INTR_BITS 0x00000001 +#define I2C_IC_CLR_INTR_CLR_INTR_MSB 0 +#define I2C_IC_CLR_INTR_CLR_INTR_LSB 0 +#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_UNDER +// Description : Clear RX_UNDER Interrupt Register +#define I2C_IC_CLR_RX_UNDER_OFFSET 0x00000044 +#define I2C_IC_CLR_RX_UNDER_BITS 0x00000001 +#define I2C_IC_CLR_RX_UNDER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER +// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS 0x00000001 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_OVER +// Description : Clear RX_OVER Interrupt Register +#define I2C_IC_CLR_RX_OVER_OFFSET 0x00000048 +#define I2C_IC_CLR_RX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_RX_OVER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER +// Description : Read this register to clear the RX_OVER interrupt (bit 1) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB 0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB 0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_OVER +// Description : Clear TX_OVER Interrupt Register +#define I2C_IC_CLR_TX_OVER_OFFSET 0x0000004c +#define I2C_IC_CLR_TX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_TX_OVER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER +// Description : Read this register to clear the TX_OVER interrupt (bit 3) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS 0x00000001 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB 0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB 0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RD_REQ +// Description : Clear RD_REQ Interrupt Register +#define I2C_IC_CLR_RD_REQ_OFFSET 0x00000050 +#define I2C_IC_CLR_RD_REQ_BITS 0x00000001 +#define I2C_IC_CLR_RD_REQ_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ +// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS 0x00000001 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB 0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB 0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_ABRT +// Description : Clear TX_ABRT Interrupt Register +#define I2C_IC_CLR_TX_ABRT_OFFSET 0x00000054 +#define I2C_IC_CLR_TX_ABRT_BITS 0x00000001 +#define I2C_IC_CLR_TX_ABRT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT +// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of +// the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE +// register. This also releases the TX FIFO from the flushed/reset +// state, allowing more writes to the TX FIFO. Refer to Bit 9 of +// the IC_TX_ABRT_SOURCE register for an exception to clearing +// IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET 0x0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS 0x00000001 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB 0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB 0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_DONE +// Description : Clear RX_DONE Interrupt Register +#define I2C_IC_CLR_RX_DONE_OFFSET 0x00000058 +#define I2C_IC_CLR_RX_DONE_BITS 0x00000001 +#define I2C_IC_CLR_RX_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE +// Description : Read this register to clear the RX_DONE interrupt (bit 7) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS 0x00000001 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB 0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB 0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_ACTIVITY +// Description : Clear ACTIVITY Interrupt Register +#define I2C_IC_CLR_ACTIVITY_OFFSET 0x0000005c +#define I2C_IC_CLR_ACTIVITY_BITS 0x00000001 +#define I2C_IC_CLR_ACTIVITY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY +// Description : Reading this register clears the ACTIVITY interrupt if the I2C +// is not active anymore. If the I2C module is still active on the +// bus, the ACTIVITY interrupt bit continues to be set. It is +// automatically cleared by hardware if the module is disabled and +// if there is no further activity on the bus. The value read from +// this register to get status of the ACTIVITY interrupt (bit 8) +// of the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS 0x00000001 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_STOP_DET +// Description : Clear STOP_DET Interrupt Register +#define I2C_IC_CLR_STOP_DET_OFFSET 0x00000060 +#define I2C_IC_CLR_STOP_DET_BITS 0x00000001 +#define I2C_IC_CLR_STOP_DET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET +// Description : Read this register to clear the STOP_DET interrupt (bit 9) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS 0x00000001 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB 0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB 0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_START_DET +// Description : Clear START_DET Interrupt Register +#define I2C_IC_CLR_START_DET_OFFSET 0x00000064 +#define I2C_IC_CLR_START_DET_BITS 0x00000001 +#define I2C_IC_CLR_START_DET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_START_DET_CLR_START_DET +// Description : Read this register to clear the START_DET interrupt (bit 10) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET 0x0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS 0x00000001 +#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB 0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB 0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_GEN_CALL +// Description : Clear GEN_CALL Interrupt Register +#define I2C_IC_CLR_GEN_CALL_OFFSET 0x00000068 +#define I2C_IC_CLR_GEN_CALL_BITS 0x00000001 +#define I2C_IC_CLR_GEN_CALL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL +// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS 0x00000001 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_ENABLE +// Description : I2C Enable Register +#define I2C_IC_ENABLE_OFFSET 0x0000006c +#define I2C_IC_ENABLE_BITS 0x00000007 +#define I2C_IC_ENABLE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_TX_CMD_BLOCK +// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C +// bus even if Tx FIFO has data to transmit. - 1'b0: The +// transmission of data starts on I2C bus automatically, as soon +// as the first data is available in the Tx FIFO. Note: To block +// the execution of Master commands, set the TX_CMD_BLOCK bit only +// when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle +// state (IC_STATUS[5] == 0). Any further commands put in the Tx +// FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset +// value: IC_TX_CMD_BLOCK_DEFAULT +// 0x0 -> Tx Command execution not blocked +// 0x1 -> Tx Command execution blocked +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET 0x0 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS 0x00000004 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB 2 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB 2 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED 0x0 +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ABORT +// Description : When set, the controller initiates the transfer abort. - 0: +// ABORT not initiated or ABORT done - 1: ABORT operation in +// progress The software can abort the I2C transfer in master mode +// by setting this bit. The software can set this bit only when +// ENABLE is already set; otherwise, the controller ignores any +// write to ABORT bit. The software cannot clear the ABORT bit +// once set. In response to an ABORT, the controller issues a STOP +// and flushes the Tx FIFO after completing the current transfer, +// then sets the TX_ABORT interrupt after the abort operation. The +// ABORT bit is cleared automatically after the abort operation. +// +// For a detailed description on how to abort I2C transfers, refer +// to 'Aborting I2C Transfers'. +// +// Reset value: 0x0 +// 0x0 -> ABORT operation not in progress +// 0x1 -> ABORT operation in progress +#define I2C_IC_ENABLE_ABORT_RESET 0x0 +#define I2C_IC_ENABLE_ABORT_BITS 0x00000002 +#define I2C_IC_ENABLE_ABORT_MSB 1 +#define I2C_IC_ENABLE_ABORT_LSB 1 +#define I2C_IC_ENABLE_ABORT_ACCESS "RW" +#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE 0x0 +#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ENABLE +// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables +// DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: +// Enables DW_apb_i2c Software can disable DW_apb_i2c while it is +// active. However, it is important that care be taken to ensure +// that DW_apb_i2c is disabled properly. A recommended procedure +// is described in 'Disabling DW_apb_i2c'. +// +// When DW_apb_i2c is disabled, the following occurs: - The TX +// FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT +// register are still active until DW_apb_i2c goes into IDLE +// state. If the module is transmitting, it stops as well as +// deletes the contents of the transmit buffer after the current +// transfer is complete. If the module is receiving, the +// DW_apb_i2c stops the current transfer at the end of the current +// byte and does not acknowledge the transfer. +// +// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE +// parameter set to asynchronous (1), there is a two ic_clk delay +// when enabling or disabling the DW_apb_i2c. For a detailed +// description on how to disable DW_apb_i2c, refer to 'Disabling +// DW_apb_i2c' +// +// Reset value: 0x0 +// 0x0 -> I2C is disabled +// 0x1 -> I2C is enabled +#define I2C_IC_ENABLE_ENABLE_RESET 0x0 +#define I2C_IC_ENABLE_ENABLE_BITS 0x00000001 +#define I2C_IC_ENABLE_ENABLE_MSB 0 +#define I2C_IC_ENABLE_ENABLE_LSB 0 +#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" +#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED 0x0 +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_STATUS +// Description : I2C Status Register +// +// This is a read-only register used to indicate the current +// transfer status and FIFO status. The status register may be +// read at any time. None of the bits in this register request an +// interrupt. +// +// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE +// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set +// to 0 When the master or slave state machines goes to idle and +// ic_en=0: - Bits 5 and 6 are set to 0 +#define I2C_IC_STATUS_OFFSET 0x00000070 +#define I2C_IC_STATUS_BITS 0x0000007f +#define I2C_IC_STATUS_RESET 0x00000006 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_SLV_ACTIVITY +// Description : Slave FSM Activity Status. When the Slave Finite State Machine +// (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM +// is in IDLE state so the Slave part of DW_apb_i2c is not Active +// - 1: Slave FSM is not in IDLE state so the Slave part of +// DW_apb_i2c is Active Reset value: 0x0 +// 0x0 -> Slave is idle +// 0x1 -> Slave not idle +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET 0x0 +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS 0x00000040 +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB 6 +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB 6 +#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE 0x0 +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_MST_ACTIVITY +// Description : Master FSM Activity Status. When the Master Finite State +// Machine (FSM) is not in the IDLE state, this bit is set. - 0: +// Master FSM is in IDLE state so the Master part of DW_apb_i2c is +// not Active - 1: Master FSM is not in IDLE state so the Master +// part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, +// ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. +// +// Reset value: 0x0 +// 0x0 -> Master is idle +// 0x1 -> Master not idle +#define I2C_IC_STATUS_MST_ACTIVITY_RESET 0x0 +#define I2C_IC_STATUS_MST_ACTIVITY_BITS 0x00000020 +#define I2C_IC_STATUS_MST_ACTIVITY_MSB 5 +#define I2C_IC_STATUS_MST_ACTIVITY_LSB 5 +#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE 0x0 +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFF +// Description : Receive FIFO Completely Full. When the receive FIFO is +// completely full, this bit is set. When the receive FIFO +// contains one or more empty location, this bit is cleared. - 0: +// Receive FIFO is not full - 1: Receive FIFO is full Reset value: +// 0x0 +// 0x0 -> Rx FIFO not full +// 0x1 -> Rx FIFO is full +#define I2C_IC_STATUS_RFF_RESET 0x0 +#define I2C_IC_STATUS_RFF_BITS 0x00000010 +#define I2C_IC_STATUS_RFF_MSB 4 +#define I2C_IC_STATUS_RFF_LSB 4 +#define I2C_IC_STATUS_RFF_ACCESS "RO" +#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL 0x0 +#define I2C_IC_STATUS_RFF_VALUE_FULL 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFNE +// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO +// contains one or more entries; it is cleared when the receive +// FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is +// not empty Reset value: 0x0 +// 0x0 -> Rx FIFO is empty +// 0x1 -> Rx FIFO not empty +#define I2C_IC_STATUS_RFNE_RESET 0x0 +#define I2C_IC_STATUS_RFNE_BITS 0x00000008 +#define I2C_IC_STATUS_RFNE_MSB 3 +#define I2C_IC_STATUS_RFNE_LSB 3 +#define I2C_IC_STATUS_RFNE_ACCESS "RO" +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY 0x0 +#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFE +// Description : Transmit FIFO Completely Empty. When the transmit FIFO is +// completely empty, this bit is set. When it contains one or more +// valid entries, this bit is cleared. This bit field does not +// request an interrupt. - 0: Transmit FIFO is not empty - 1: +// Transmit FIFO is empty Reset value: 0x1 +// 0x0 -> Tx FIFO not empty +// 0x1 -> Tx FIFO is empty +#define I2C_IC_STATUS_TFE_RESET 0x1 +#define I2C_IC_STATUS_TFE_BITS 0x00000004 +#define I2C_IC_STATUS_TFE_MSB 2 +#define I2C_IC_STATUS_TFE_LSB 2 +#define I2C_IC_STATUS_TFE_ACCESS "RO" +#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY 0x0 +#define I2C_IC_STATUS_TFE_VALUE_EMPTY 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFNF +// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one +// or more empty locations, and is cleared when the FIFO is full. +// - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset +// value: 0x1 +// 0x0 -> Tx FIFO is full +// 0x1 -> Tx FIFO not full +#define I2C_IC_STATUS_TFNF_RESET 0x1 +#define I2C_IC_STATUS_TFNF_BITS 0x00000002 +#define I2C_IC_STATUS_TFNF_MSB 1 +#define I2C_IC_STATUS_TFNF_LSB 1 +#define I2C_IC_STATUS_TFNF_ACCESS "RO" +#define I2C_IC_STATUS_TFNF_VALUE_FULL 0x0 +#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_ACTIVITY +// Description : I2C Activity Status. Reset value: 0x0 +// 0x0 -> I2C is idle +// 0x1 -> I2C is active +#define I2C_IC_STATUS_ACTIVITY_RESET 0x0 +#define I2C_IC_STATUS_ACTIVITY_BITS 0x00000001 +#define I2C_IC_STATUS_ACTIVITY_MSB 0 +#define I2C_IC_STATUS_ACTIVITY_LSB 0 +#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE 0x0 +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_TXFLR +// Description : I2C Transmit FIFO Level Register This register contains the +// number of valid data entries in the transmit FIFO buffer. It is +// cleared whenever: - The I2C is disabled - There is a transmit +// abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT +// register - The slave bulk transmit mode is aborted The register +// increments whenever data is placed into the transmit FIFO and +// decrements when data is taken from the transmit FIFO. +#define I2C_IC_TXFLR_OFFSET 0x00000074 +#define I2C_IC_TXFLR_BITS 0x0000001f +#define I2C_IC_TXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TXFLR_TXFLR +// Description : Transmit FIFO Level. Contains the number of valid data entries +// in the transmit FIFO. +// +// Reset value: 0x0 +#define I2C_IC_TXFLR_TXFLR_RESET 0x00 +#define I2C_IC_TXFLR_TXFLR_BITS 0x0000001f +#define I2C_IC_TXFLR_TXFLR_MSB 4 +#define I2C_IC_TXFLR_TXFLR_LSB 0 +#define I2C_IC_TXFLR_TXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_RXFLR +// Description : I2C Receive FIFO Level Register This register contains the +// number of valid data entries in the receive FIFO buffer. It is +// cleared whenever: - The I2C is disabled - Whenever there is a +// transmit abort caused by any of the events tracked in +// IC_TX_ABRT_SOURCE The register increments whenever data is +// placed into the receive FIFO and decrements when data is taken +// from the receive FIFO. +#define I2C_IC_RXFLR_OFFSET 0x00000078 +#define I2C_IC_RXFLR_BITS 0x0000001f +#define I2C_IC_RXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RXFLR_RXFLR +// Description : Receive FIFO Level. Contains the number of valid data entries +// in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_RXFLR_RXFLR_RESET 0x00 +#define I2C_IC_RXFLR_RXFLR_BITS 0x0000001f +#define I2C_IC_RXFLR_RXFLR_MSB 4 +#define I2C_IC_RXFLR_RXFLR_LSB 0 +#define I2C_IC_RXFLR_RXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_SDA_HOLD +// Description : I2C SDA Hold Time Length Register +// +// The bits [15:0] of this register are used to control the hold +// time of SDA during transmit in both slave and master mode +// (after SCL goes from HIGH to LOW). +// +// The bits [23:16] of this register are used to extend the SDA +// transition (if any) whenever SCL is HIGH in the receiver in +// either master or slave mode. +// +// Writes to this register succeed only when IC_ENABLE[0]=0. +// +// The values in this register are in units of ic_clk period. The +// value programmed in IC_SDA_TX_HOLD must be greater than the +// minimum hold time in each mode one cycle in master mode, seven +// cycles in slave mode for the value to be implemented. +// +// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) +// cannot exceed at any time the duration of the low part of scl. +// Therefore the programmed value cannot be larger than +// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of +// the scl period measured in ic_clk cycles. +#define I2C_IC_SDA_HOLD_OFFSET 0x0000007c +#define I2C_IC_SDA_HOLD_BITS 0x00ffffff +#define I2C_IC_SDA_HOLD_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a receiver. +// +// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x00 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS 0x00ff0000 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16 +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a transmitter. +// +// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x0001 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS 0x0000ffff +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0 +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_ABRT_SOURCE +// Description : I2C Transmit Abort Source Register +// +// This register has 32 bits that indicate the source of the +// TX_ABRT bit. Except for Bit 9, this register is cleared +// whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR +// register is read. To clear Bit 9, the source of the +// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled +// (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or +// the GC_OR_START bit must be cleared (IC_TAR[10]). +// +// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this +// bit can be cleared in the same manner as other bits in this +// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed +// before attempting to clear this bit, Bit 9 clears for one cycle +// and is then re-asserted. +#define I2C_IC_TX_ABRT_SOURCE_OFFSET 0x00000080 +#define I2C_IC_TX_ABRT_SOURCE_BITS 0xff81ffff +#define I2C_IC_TX_ABRT_SOURCE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT +// Description : This field indicates the number of Tx FIFO Data Commands which +// are flushed due to TX_ABRT interrupt. It is cleared whenever +// I2C is disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET 0x000 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS 0xff800000 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB 31 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB 23 +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT +// Description : This is a master-mode-only bit. Master has detected the +// transfer abort (IC_ENABLE[1]) +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transfer abort detected by master- scenario not present +// 0x1 -> Transfer abort detected by master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS 0x00010000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB 16 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB 16 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX +// Description : 1: When the processor side responds to a slave mode request for +// data to be transmitted to a remote master and user writes a 1 +// in CMD (bit 8) of IC_DATA_CMD register. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave trying to transmit to remote master in read mode- +// scenario not present +// 0x1 -> Slave trying to transmit to remote master in read mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS 0x00008000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB 15 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB 15 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST +// Description : This field indicates that a Slave has lost the bus while +// transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is +// set at the same time. Note: Even though the slave never 'owns' +// the bus, something could go wrong on the bus. This is a fail +// safe check. For instance, during a data transmission at the +// low-to-high transition of SCL, if what is on the data bus is +// not what is supposed to be transmitted, then DW_apb_i2c no +// longer own the bus. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave lost arbitration to remote master- scenario not +// present +// 0x1 -> Slave lost arbitration to remote master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS 0x00004000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB 14 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB 14 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO +// Description : This field specifies that the Slave has received a read command +// and some data exists in the TX FIFO, so the slave issues a +// TX_ABRT interrupt to flush old data in TX FIFO. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read +// command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read +// command +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS 0x00002000 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB 13 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB 13 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST +// Description : This field specifies that the Master has lost arbitration, or +// if IC_TX_ABRT_SOURCE[14] is also set, then the slave +// transmitter has lost arbitration. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario +// not present +// 0x1 -> Master or Slave-Transmitter lost arbitration +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS 0x00001000 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB 12 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB 12 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS +// Description : This field indicates that the User tries to initiate a Master +// operation with the Master mode disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User initiating master operation when MASTER disabled- +// scenario not present +// 0x1 -> User initiating master operation when MASTER disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS 0x00000800 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB 11 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB 11 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read +// command in 10-bit addressing mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Receiver +// 0x0 -> Master not trying to read in 10Bit addressing mode when +// RESTART disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when +// RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS 0x00000400 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB 10 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB 10 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT +// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be +// fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL +// bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must +// be cleared (IC_TAR[10]). Once the source of the +// ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in +// the same manner as other bits in this register. If the source +// of the ABRT_SBYTE_NORSTRT is not fixed before attempting to +// clear this bit, bit 9 clears for one cycle and then gets +// reasserted. When this field is set to 1, the restart is +// disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is +// trying to send a START Byte. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> User trying to send START byte when RESTART disabled- +// scenario not present +// 0x1 -> User trying to send START byte when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS 0x00000200 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB 9 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB 9 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to +// use the master to transfer data in High Speed mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User trying to switch Master to HS mode when RESTART +// disabled- scenario not present +// 0x1 -> User trying to switch Master to HS mode when RESTART +// disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS 0x00000100 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB 8 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB 8 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET +// Description : This field indicates that the Master has sent a START Byte and +// the START Byte was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> ACK detected for START byte- scenario not present +// 0x1 -> ACK detected for START byte +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS 0x00000080 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB 7 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB 7 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET +// Description : This field indicates that the Master is in High Speed mode and +// the High Speed Master code was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> HS Master code ACKed in HS Mode- scenario not present +// 0x1 -> HS Master code ACKed in HS Mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS 0x00000040 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB 6 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB 6 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ +// Description : This field indicates that DW_apb_i2c in the master mode has +// sent a General Call but the user programmed the byte following +// the General Call to be a read from the bus (IC_DATA_CMD[9] is +// set to 1). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL is followed by read from bus-scenario not present +// 0x1 -> GCALL is followed by read from bus +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS 0x00000020 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB 5 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB 5 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK +// Description : This field indicates that DW_apb_i2c in master mode has sent a +// General Call and no slave on the bus acknowledged the General +// Call. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL not ACKed by any slave-scenario not present +// 0x1 -> GCALL not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS 0x00000010 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB 4 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB 4 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK +// Description : This field indicates the master-mode only bit. When the master +// receives an acknowledgement for the address, but when it sends +// data byte(s) following the address, it did not receive an +// acknowledge from the remote slave(s). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario +// not present +// 0x1 -> Transmitted data not ACKed by addressed slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS 0x00000008 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB 3 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB 3 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and that the second address byte of the 10-bit address was not +// acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS 0x00000004 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB 2 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB 2 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and the first 10-bit address byte was not acknowledged by any +// slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS 0x00000002 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB 1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB 1 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK +// Description : This field indicates that the Master is in 7-bit addressing +// mode and the address sent was not acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> This abort is generated because of NOACK for 7-bit +// address +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS 0x00000001 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB 0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB 0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE 0x0 +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE 0x1 +// ============================================================================= +// Register : I2C_IC_SLV_DATA_NACK_ONLY +// Description : Generate Slave Data NACK Register +// +// The register is used to generate a NACK for the data part of a +// transfer when DW_apb_i2c is acting as a slave-receiver. This +// register only exists when the IC_SLV_DATA_NACK_ONLY parameter +// is set to 1. When this parameter disabled, this register does +// not exist and writing to the register's address has no effect. +// +// A write can occur on this register if both of the following +// conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) +// - Slave part is inactive (IC_STATUS[6] = 0) Note: The +// IC_STATUS[6] is a register read-back location for the internal +// slv_activity signal; the user should poll this before writing +// the ic_slv_data_nack_only bit. +#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET 0x00000084 +#define I2C_IC_SLV_DATA_NACK_ONLY_BITS 0x00000001 +#define I2C_IC_SLV_DATA_NACK_ONLY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK +// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c +// is a slave-receiver. If this register is set to a value of 1, +// it can only generate a NACK after a data byte is received; +// hence, the data transfer is aborted and the data received is +// not pushed to the receive buffer. +// +// When the register is set to a value of 0, it generates +// NACK/ACK, depending on normal criteria. - 1: generate NACK +// after data byte received - 0: generate NACK/ACK normally Reset +// value: 0x0 +// 0x0 -> Slave receiver generates NACK normally +// 0x1 -> Slave receiver generates NACK upon data reception only +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET 0x0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS 0x00000001 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB 0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB 0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED 0x0 +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_DMA_CR +// Description : DMA Control Register +// +// The register is used to enable the DMA Controller interface +// operation. There is a separate bit for transmit and receive. +// This can be programmed regardless of the state of IC_ENABLE. +#define I2C_IC_DMA_CR_OFFSET 0x00000088 +#define I2C_IC_DMA_CR_BITS 0x00000003 +#define I2C_IC_DMA_CR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_TDMAE +// Description : Transmit DMA Enable. This bit enables/disables the transmit +// FIFO DMA channel. Reset value: 0x0 +// 0x0 -> transmit FIFO DMA channel disabled +// 0x1 -> Transmit FIFO DMA channel enabled +#define I2C_IC_DMA_CR_TDMAE_RESET 0x0 +#define I2C_IC_DMA_CR_TDMAE_BITS 0x00000002 +#define I2C_IC_DMA_CR_TDMAE_MSB 1 +#define I2C_IC_DMA_CR_TDMAE_LSB 1 +#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED 0x0 +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_RDMAE +// Description : Receive DMA Enable. This bit enables/disables the receive FIFO +// DMA channel. Reset value: 0x0 +// 0x0 -> Receive FIFO DMA channel disabled +// 0x1 -> Receive FIFO DMA channel enabled +#define I2C_IC_DMA_CR_RDMAE_RESET 0x0 +#define I2C_IC_DMA_CR_RDMAE_BITS 0x00000001 +#define I2C_IC_DMA_CR_RDMAE_MSB 0 +#define I2C_IC_DMA_CR_RDMAE_LSB 0 +#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED 0x0 +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_DMA_TDLR +// Description : DMA Transmit Data Level Register +#define I2C_IC_DMA_TDLR_OFFSET 0x0000008c +#define I2C_IC_DMA_TDLR_BITS 0x0000000f +#define I2C_IC_DMA_TDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_TDLR_DMATDL +// Description : Transmit Data Level. This bit field controls the level at which +// a DMA request is made by the transmit logic. It is equal to the +// watermark level; that is, the dma_tx_req signal is generated +// when the number of valid data entries in the transmit FIFO is +// equal to or below this field value, and TDMAE = 1. +// +// Reset value: 0x0 +#define I2C_IC_DMA_TDLR_DMATDL_RESET 0x0 +#define I2C_IC_DMA_TDLR_DMATDL_BITS 0x0000000f +#define I2C_IC_DMA_TDLR_DMATDL_MSB 3 +#define I2C_IC_DMA_TDLR_DMATDL_LSB 0 +#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DMA_RDLR +// Description : I2C Receive Data Level Register +#define I2C_IC_DMA_RDLR_OFFSET 0x00000090 +#define I2C_IC_DMA_RDLR_BITS 0x0000000f +#define I2C_IC_DMA_RDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_RDLR_DMARDL +// Description : Receive Data Level. This bit field controls the level at which +// a DMA request is made by the receive logic. The watermark level +// = DMARDL+1; that is, dma_rx_req is generated when the number of +// valid data entries in the receive FIFO is equal to or more than +// this field value + 1, and RDMAE =1. For instance, when DMARDL +// is 0, then dma_rx_req is asserted when 1 or more data entries +// are present in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_DMA_RDLR_DMARDL_RESET 0x0 +#define I2C_IC_DMA_RDLR_DMARDL_BITS 0x0000000f +#define I2C_IC_DMA_RDLR_DMARDL_MSB 3 +#define I2C_IC_DMA_RDLR_DMARDL_LSB 0 +#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SDA_SETUP +// Description : I2C SDA Setup Register +// +// This register controls the amount of time delay (in terms of +// number of ic_clk clock periods) introduced in the rising edge +// of SCL - relative to SDA changing - when DW_apb_i2c services a +// read request in a slave-transmitter operation. The relevant I2C +// requirement is tSU:DAT (note 4) as detailed in the I2C Bus +// Specification. This register must be programmed with a value +// equal to or greater than 2. +// +// Writes to this register succeed only when IC_ENABLE[0] = 0. +// +// Note: The length of setup time is calculated using +// [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires +// 10 ic_clk periods of setup time, they should program a value of +// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c +// when operating as a slave transmitter. +#define I2C_IC_SDA_SETUP_OFFSET 0x00000094 +#define I2C_IC_SDA_SETUP_BITS 0x000000ff +#define I2C_IC_SDA_SETUP_RESET 0x00000064 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_SETUP_SDA_SETUP +// Description : SDA Setup. It is recommended that if the required delay is +// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP +// should be programmed to a value of 11. IC_SDA_SETUP must be +// programmed with a minimum value of 2. +#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET 0x64 +#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS 0x000000ff +#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB 7 +#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB 0 +#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_ACK_GENERAL_CALL +// Description : I2C ACK General Call Register +// +// The register controls whether DW_apb_i2c responds with a ACK or +// NACK when it receives an I2C General Call address. +// +// This register is applicable only when the DW_apb_i2c is in +// slave mode. +#define I2C_IC_ACK_GENERAL_CALL_OFFSET 0x00000098 +#define I2C_IC_ACK_GENERAL_CALL_BITS 0x00000001 +#define I2C_IC_ACK_GENERAL_CALL_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL +// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK +// (by asserting ic_data_oe) when it receives a General Call. +// Otherwise, DW_apb_i2c responds with a NACK (by negating +// ic_data_oe). +// 0x0 -> Generate NACK for a General Call +// 0x1 -> Generate ACK for a General Call +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS 0x00000001 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED 0x0 +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_ENABLE_STATUS +// Description : I2C Enable Status Register +// +// The register is used to report the DW_apb_i2c hardware status +// when the IC_ENABLE[0] register is set from 1 to 0; that is, +// when DW_apb_i2c is disabled. +// +// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, +// and bit 0 is forced to 1. +// +// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as +// soon as bit 0 is read as '0'. +// +// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for +// bit 0 to be read as 0 because disabling the DW_apb_i2c depends +// on I2C bus activities. +#define I2C_IC_ENABLE_STATUS_OFFSET 0x0000009c +#define I2C_IC_ENABLE_STATUS_BITS 0x00000007 +#define I2C_IC_ENABLE_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST +// Description : Slave Received Data Lost. This bit indicates if a +// Slave-Receiver operation has been aborted with at least one +// data byte received from an I2C transfer due to the setting bit +// 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is +// deemed to have been actively engaged in an aborted I2C transfer +// (with matching address) and the data phase of the I2C transfer +// has been entered, even though a data byte has been responded +// with a NACK. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit is +// also set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled +// without being actively involved in the data phase of a +// Slave-Receiver transfer. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave RX Data is not lost +// 0x1 -> Slave RX Data is lost +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS 0x00000004 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB 2 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB 2 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY +// Description : Slave Disabled While Busy (Transmit, Receive). This bit +// indicates if a potential or active Slave operation has been +// aborted due to the setting bit 0 of the IC_ENABLE register from +// 1 to 0. This bit is set when the CPU writes a 0 to the +// IC_ENABLE register while: +// +// (a) DW_apb_i2c is receiving the address byte of the +// Slave-Transmitter operation from a remote master; +// +// OR, +// +// (b) address and data bytes of the Slave-Receiver operation from +// a remote master. +// +// When read as 1, DW_apb_i2c is deemed to have forced a NACK +// during any part of an I2C transfer, irrespective of whether the +// I2C address matches the slave address set in DW_apb_i2c (IC_SAR +// register) OR if the transfer is completed before IC_ENABLE is +// set to 0 but has not taken effect. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit +// will also be set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled when +// there is master activity, or when the I2C bus is idle. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave is disabled when it is idle +// 0x1 -> Slave is disabled when it is active +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS 0x00000002 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB 1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB 1 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE 0x0 +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE 0x1 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_IC_EN +// Description : ic_en Status. This bit always reflects the value driven on the +// output port ic_en. - When read as 1, DW_apb_i2c is deemed to be +// in an enabled state. - When read as 0, DW_apb_i2c is deemed +// completely inactive. Note: The CPU can safely read this bit +// anytime. When this bit is read as 0, the CPU can safely read +// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). +// +// Reset value: 0x0 +// 0x0 -> I2C disabled +// 0x1 -> I2C enabled +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET 0x0 +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS 0x00000001 +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB 0 +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB 0 +#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED 0x0 +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED 0x1 +// ============================================================================= +// Register : I2C_IC_FS_SPKLEN +// Description : I2C SS, FS or FM+ spike suppression limit +// +// This register is used to store the duration, measured in ic_clk +// cycles, of the longest spike that is filtered out by the spike +// suppression logic when the component is operating in SS, FS or +// FM+ modes. The relevant I2C requirement is tSP (table 4) as +// detailed in the I2C Bus Specification. This register must be +// programmed with a minimum value of 1. +#define I2C_IC_FS_SPKLEN_OFFSET 0x000000a0 +#define I2C_IC_FS_SPKLEN_BITS 0x000000ff +#define I2C_IC_FS_SPKLEN_RESET 0x00000007 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN +// Description : This register must be set before any I2C bus transaction can +// take place to ensure stable operation. This register sets the +// duration, measured in ic_clk cycles, of the longest spike in +// the SCL or SDA lines that will be filtered out by the spike +// suppression logic. This register can be written only when the +// I2C interface is disabled which corresponds to the IC_ENABLE[0] +// register being set to 0. Writes at other times have no effect. +// The minimum valid value is 1; hardware prevents values less +// than this being written, and if attempted results in 1 being +// set. or more information, refer to 'Spike Suppression'. +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x07 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS 0x000000ff +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB 7 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB 0 +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_RESTART_DET +// Description : Clear RESTART_DET Interrupt Register +#define I2C_IC_CLR_RESTART_DET_OFFSET 0x000000a8 +#define I2C_IC_CLR_RESTART_DET_BITS 0x00000001 +#define I2C_IC_CLR_RESTART_DET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET +// Description : Read this register to clear the RESTART_DET interrupt (bit 12) +// of IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS 0x00000001 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_PARAM_1 +// Description : Component Parameter Register 1 +// +// Note This register is not implemented and therefore reads as 0. +// If it was implemented it would be a constant read-only register +// that contains encoded information about the component's +// parameter settings. Fields shown below are the settings for +// those parameters +#define I2C_IC_COMP_PARAM_1_OFFSET 0x000000f4 +#define I2C_IC_COMP_PARAM_1_BITS 0x00ffffff +#define I2C_IC_COMP_PARAM_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH +// Description : TX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET 0x00 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS 0x00ff0000 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB 23 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH +// Description : RX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET 0x00 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS 0x0000ff00 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB 15 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB 8 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS +// Description : Encoded parameters not visible +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS 0x00000080 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB 7 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB 7 +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HAS_DMA +// Description : DMA handshaking signals are enabled +#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS 0x00000040 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB 6 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB 6 +#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_INTR_IO +// Description : COMBINED Interrupt outputs +#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS 0x00000020 +#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB 5 +#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB 5 +#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES +// Description : Programmable count values for each mode. +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS 0x00000010 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4 +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE +// Description : MAX SPEED MODE = FAST MODE +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS 0x0000000c +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB 3 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB 2 +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH +// Description : APB data bus width is 32 bits +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x0 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS 0x00000003 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0 +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_VERSION +// Description : I2C Component Version Register +#define I2C_IC_COMP_VERSION_OFFSET 0x000000f8 +#define I2C_IC_COMP_VERSION_BITS 0xffffffff +#define I2C_IC_COMP_VERSION_RESET 0x3230312a +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION +// Description : None +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET 0x3230312a +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS 0xffffffff +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB 31 +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB 0 +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_TYPE +// Description : I2C Component Type Register +#define I2C_IC_COMP_TYPE_OFFSET 0x000000fc +#define I2C_IC_COMP_TYPE_BITS 0xffffffff +#define I2C_IC_COMP_TYPE_RESET 0x44570140 +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE +// Description : Designware Component Type number = 0x44_57_01_40. This assigned +// unique hex value is constant and is derived from the two ASCII +// letters 'DW' followed by a 16-bit unsigned number. +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS 0xffffffff +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB 31 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB 0 +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_I2C_DEFINED diff --git a/rp2040/hardware/regs/intctrl.h b/rp2040/hardware/regs/intctrl.h new file mode 100644 index 0000000..dec7e36 --- /dev/null +++ b/rp2040/hardware/regs/intctrl.h @@ -0,0 +1,63 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _INTCTRL_H_ +#define _INTCTRL_H_ + +#define TIMER_IRQ_0 0 +#define TIMER_IRQ_1 1 +#define TIMER_IRQ_2 2 +#define TIMER_IRQ_3 3 +#define PWM_IRQ_WRAP 4 +#define USBCTRL_IRQ 5 +#define XIP_IRQ 6 +#define PIO0_IRQ_0 7 +#define PIO0_IRQ_1 8 +#define PIO1_IRQ_0 9 +#define PIO1_IRQ_1 10 +#define DMA_IRQ_0 11 +#define DMA_IRQ_1 12 +#define IO_IRQ_BANK0 13 +#define IO_IRQ_QSPI 14 +#define SIO_IRQ_PROC0 15 +#define SIO_IRQ_PROC1 16 +#define CLOCKS_IRQ 17 +#define SPI0_IRQ 18 +#define SPI1_IRQ 19 +#define UART0_IRQ 20 +#define UART1_IRQ 21 +#define ADC_IRQ_FIFO 22 +#define I2C0_IRQ 23 +#define I2C1_IRQ 24 +#define RTC_IRQ 25 + +#define isr_timer_0 isr_irq0 +#define isr_timer_1 isr_irq1 +#define isr_timer_2 isr_irq2 +#define isr_timer_3 isr_irq3 +#define isr_pwm_wrap isr_irq4 +#define isr_usbctrl isr_irq5 +#define isr_xip isr_irq6 +#define isr_pio0_0 isr_irq7 +#define isr_pio0_1 isr_irq8 +#define isr_pio1_0 isr_irq9 +#define isr_pio1_1 isr_irq10 +#define isr_dma_0 isr_irq11 +#define isr_dma_1 isr_irq12 +#define isr_io_bank0 isr_irq13 +#define isr_io_qspi isr_irq14 +#define isr_sio_proc0 isr_irq15 +#define isr_sio_proc1 isr_irq16 +#define isr_clocks isr_irq17 +#define isr_spi0 isr_irq18 +#define isr_spi1 isr_irq19 +#define isr_uart0 isr_irq20 +#define isr_uart1 isr_irq21 +#define isr_adc_fifo isr_irq22 +#define isr_i2c0 isr_irq23 +#define isr_i2c1 isr_irq24 +#define isr_rtc isr_irq25 + +#endif // _INTCTRL_H_ diff --git a/rp2040/hardware/regs/io_bank0.h b/rp2040/hardware/regs/io_bank0.h new file mode 100644 index 0000000..f7b1561 --- /dev/null +++ b/rp2040/hardware/regs/io_bank0.h @@ -0,0 +1,14937 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_BANK0 +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_IO_BANK0_DEFINED +#define HARDWARE_REGS_IO_BANK0_DEFINED +// ============================================================================= +// Register : IO_BANK0_GPIO0_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO0_STATUS_OFFSET 0x00000000 +#define IO_BANK0_GPIO0_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO0_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO0_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO0_CTRL_OFFSET 0x00000004 +#define IO_BANK0_GPIO0_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO0_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tck +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> sio_0 +// 0x06 -> pio0_0 +// 0x07 -> pio1_0 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK 0x00 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 0x05 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 0x06 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 0x07 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO1_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO1_STATUS_OFFSET 0x00000008 +#define IO_BANK0_GPIO1_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO1_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO1_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO1_CTRL_OFFSET 0x0000000c +#define IO_BANK0_GPIO1_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO1_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tms +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> sio_1 +// 0x06 -> pio0_1 +// 0x07 -> pio1_1 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS 0x00 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 0x05 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 0x06 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 0x07 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO2_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO2_STATUS_OFFSET 0x00000010 +#define IO_BANK0_GPIO2_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO2_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO2_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO2_CTRL_OFFSET 0x00000014 +#define IO_BANK0_GPIO2_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO2_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdi +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> sio_2 +// 0x06 -> pio0_2 +// 0x07 -> pio1_2 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI 0x00 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 0x05 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 0x06 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 0x07 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO3_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO3_STATUS_OFFSET 0x00000018 +#define IO_BANK0_GPIO3_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO3_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO3_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO3_CTRL_OFFSET 0x0000001c +#define IO_BANK0_GPIO3_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO3_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdo +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> sio_3 +// 0x06 -> pio0_3 +// 0x07 -> pio1_3 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO 0x00 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 0x05 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 0x06 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 0x07 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO4_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO4_STATUS_OFFSET 0x00000020 +#define IO_BANK0_GPIO4_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO4_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO4_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO4_CTRL_OFFSET 0x00000024 +#define IO_BANK0_GPIO4_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO4_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> sio_4 +// 0x06 -> pio0_4 +// 0x07 -> pio1_4 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 0x05 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 0x06 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 0x07 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO5_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO5_STATUS_OFFSET 0x00000028 +#define IO_BANK0_GPIO5_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO5_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO5_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO5_CTRL_OFFSET 0x0000002c +#define IO_BANK0_GPIO5_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO5_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> sio_5 +// 0x06 -> pio0_5 +// 0x07 -> pio1_5 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 0x05 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 0x06 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 0x07 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO6_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO6_STATUS_OFFSET 0x00000030 +#define IO_BANK0_GPIO6_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO6_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO6_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO6_CTRL_OFFSET 0x00000034 +#define IO_BANK0_GPIO6_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO6_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> sio_6 +// 0x06 -> pio0_6 +// 0x07 -> pio1_6 +// 0x08 -> usb_muxing_extphy_softcon +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 0x05 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 0x06 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 0x07 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON 0x08 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO7_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO7_STATUS_OFFSET 0x00000038 +#define IO_BANK0_GPIO7_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO7_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO7_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO7_CTRL_OFFSET 0x0000003c +#define IO_BANK0_GPIO7_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO7_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> sio_7 +// 0x06 -> pio0_7 +// 0x07 -> pio1_7 +// 0x08 -> usb_muxing_extphy_oe_n +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 0x05 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 0x06 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 0x07 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N 0x08 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO8_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO8_STATUS_OFFSET 0x00000040 +#define IO_BANK0_GPIO8_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO8_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO8_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO8_CTRL_OFFSET 0x00000044 +#define IO_BANK0_GPIO8_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO8_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> sio_8 +// 0x06 -> pio0_8 +// 0x07 -> pio1_8 +// 0x08 -> usb_muxing_extphy_rcv +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 0x05 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 0x06 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 0x07 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV 0x08 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO9_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO9_STATUS_OFFSET 0x00000048 +#define IO_BANK0_GPIO9_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO9_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO9_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO9_CTRL_OFFSET 0x0000004c +#define IO_BANK0_GPIO9_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO9_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> sio_9 +// 0x06 -> pio0_9 +// 0x07 -> pio1_9 +// 0x08 -> usb_muxing_extphy_vp +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 0x05 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 0x06 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 0x07 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP 0x08 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO10_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO10_STATUS_OFFSET 0x00000050 +#define IO_BANK0_GPIO10_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO10_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO10_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO10_CTRL_OFFSET 0x00000054 +#define IO_BANK0_GPIO10_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO10_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> sio_10 +// 0x06 -> pio0_10 +// 0x07 -> pio1_10 +// 0x08 -> usb_muxing_extphy_vm +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 0x05 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 0x06 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 0x07 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM 0x08 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO11_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO11_STATUS_OFFSET 0x00000058 +#define IO_BANK0_GPIO11_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO11_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO11_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO11_CTRL_OFFSET 0x0000005c +#define IO_BANK0_GPIO11_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO11_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> sio_11 +// 0x06 -> pio0_11 +// 0x07 -> pio1_11 +// 0x08 -> usb_muxing_extphy_suspnd +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 0x05 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 0x06 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 0x07 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND 0x08 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO12_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO12_STATUS_OFFSET 0x00000060 +#define IO_BANK0_GPIO12_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO12_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO12_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO12_CTRL_OFFSET 0x00000064 +#define IO_BANK0_GPIO12_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO12_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> sio_12 +// 0x06 -> pio0_12 +// 0x07 -> pio1_12 +// 0x08 -> usb_muxing_extphy_speed +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 0x05 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 0x06 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 0x07 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED 0x08 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO13_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO13_STATUS_OFFSET 0x00000068 +#define IO_BANK0_GPIO13_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO13_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO13_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO13_CTRL_OFFSET 0x0000006c +#define IO_BANK0_GPIO13_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO13_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> sio_13 +// 0x06 -> pio0_13 +// 0x07 -> pio1_13 +// 0x08 -> usb_muxing_extphy_vpo +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 0x05 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 0x06 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 0x07 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO 0x08 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO14_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO14_STATUS_OFFSET 0x00000070 +#define IO_BANK0_GPIO14_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO14_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO14_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO14_CTRL_OFFSET 0x00000074 +#define IO_BANK0_GPIO14_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO14_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_7 +// 0x05 -> sio_14 +// 0x06 -> pio0_14 +// 0x07 -> pio1_14 +// 0x08 -> usb_muxing_extphy_vmo +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 0x04 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 0x05 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 0x06 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 0x07 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO 0x08 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO15_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO15_STATUS_OFFSET 0x00000078 +#define IO_BANK0_GPIO15_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO15_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO15_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO15_CTRL_OFFSET 0x0000007c +#define IO_BANK0_GPIO15_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO15_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_7 +// 0x05 -> sio_15 +// 0x06 -> pio0_15 +// 0x07 -> pio1_15 +// 0x08 -> usb_muxing_digital_dp +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 0x04 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 0x05 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 0x06 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 0x07 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP 0x08 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO16_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO16_STATUS_OFFSET 0x00000080 +#define IO_BANK0_GPIO16_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO16_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO16_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO16_CTRL_OFFSET 0x00000084 +#define IO_BANK0_GPIO16_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO16_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> sio_16 +// 0x06 -> pio0_16 +// 0x07 -> pio1_16 +// 0x08 -> usb_muxing_digital_dm +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 0x04 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 0x05 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 0x06 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 0x07 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM 0x08 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO17_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO17_STATUS_OFFSET 0x00000088 +#define IO_BANK0_GPIO17_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO17_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO17_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO17_CTRL_OFFSET 0x0000008c +#define IO_BANK0_GPIO17_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO17_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> sio_17 +// 0x06 -> pio0_17 +// 0x07 -> pio1_17 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 0x04 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 0x05 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 0x06 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 0x07 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO18_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO18_STATUS_OFFSET 0x00000090 +#define IO_BANK0_GPIO18_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO18_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO18_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO18_CTRL_OFFSET 0x00000094 +#define IO_BANK0_GPIO18_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO18_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> sio_18 +// 0x06 -> pio0_18 +// 0x07 -> pio1_18 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS 0x02 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 0x04 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 0x05 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 0x06 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 0x07 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO19_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO19_STATUS_OFFSET 0x00000098 +#define IO_BANK0_GPIO19_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO19_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO19_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO19_CTRL_OFFSET 0x0000009c +#define IO_BANK0_GPIO19_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO19_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> sio_19 +// 0x06 -> pio0_19 +// 0x07 -> pio1_19 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS 0x02 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 0x04 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 0x05 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 0x06 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 0x07 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO20_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO20_STATUS_OFFSET 0x000000a0 +#define IO_BANK0_GPIO20_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO20_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO20_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO20_CTRL_OFFSET 0x000000a4 +#define IO_BANK0_GPIO20_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO20_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> sio_20 +// 0x06 -> pio0_20 +// 0x07 -> pio1_20 +// 0x08 -> clocks_gpin_0 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX 0x01 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 0x04 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 0x05 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 0x06 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 0x07 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 0x08 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO21_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO21_STATUS_OFFSET 0x000000a8 +#define IO_BANK0_GPIO21_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO21_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO21_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO21_CTRL_OFFSET 0x000000ac +#define IO_BANK0_GPIO21_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO21_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> sio_21 +// 0x06 -> pio0_21 +// 0x07 -> pio1_21 +// 0x08 -> clocks_gpout_0 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N 0x01 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 0x04 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 0x05 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 0x06 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 0x07 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 0x08 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO22_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO22_STATUS_OFFSET 0x000000b0 +#define IO_BANK0_GPIO22_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO22_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO22_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO22_CTRL_OFFSET 0x000000b4 +#define IO_BANK0_GPIO22_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO22_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> sio_22 +// 0x06 -> pio0_22 +// 0x07 -> pio1_22 +// 0x08 -> clocks_gpin_1 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK 0x01 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 0x04 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 0x05 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 0x06 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 0x07 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 0x08 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO23_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO23_STATUS_OFFSET 0x000000b8 +#define IO_BANK0_GPIO23_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO23_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO23_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO23_CTRL_OFFSET 0x000000bc +#define IO_BANK0_GPIO23_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO23_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> sio_23 +// 0x06 -> pio0_23 +// 0x07 -> pio1_23 +// 0x08 -> clocks_gpout_1 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX 0x01 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 0x04 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 0x05 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 0x06 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 0x07 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 0x08 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO24_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO24_STATUS_OFFSET 0x000000c0 +#define IO_BANK0_GPIO24_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO24_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO24_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO24_CTRL_OFFSET 0x000000c4 +#define IO_BANK0_GPIO24_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO24_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> sio_24 +// 0x06 -> pio0_24 +// 0x07 -> pio1_24 +// 0x08 -> clocks_gpout_2 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX 0x02 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 0x04 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 0x05 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 0x06 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 0x07 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 0x08 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO25_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO25_STATUS_OFFSET 0x000000c8 +#define IO_BANK0_GPIO25_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO25_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO25_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO25_CTRL_OFFSET 0x000000cc +#define IO_BANK0_GPIO25_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO25_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> sio_25 +// 0x06 -> pio0_25 +// 0x07 -> pio1_25 +// 0x08 -> clocks_gpout_3 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX 0x02 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 0x04 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 0x05 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 0x06 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 0x07 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 0x08 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO26_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO26_STATUS_OFFSET 0x000000d0 +#define IO_BANK0_GPIO26_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO26_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO26_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO26_CTRL_OFFSET 0x000000d4 +#define IO_BANK0_GPIO26_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO26_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> sio_26 +// 0x06 -> pio0_26 +// 0x07 -> pio1_26 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK 0x01 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS 0x02 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA 0x03 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 0x04 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 0x05 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 0x06 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 0x07 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO27_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO27_STATUS_OFFSET 0x000000d8 +#define IO_BANK0_GPIO27_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO27_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO27_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO27_CTRL_OFFSET 0x000000dc +#define IO_BANK0_GPIO27_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO27_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> sio_27 +// 0x06 -> pio0_27 +// 0x07 -> pio1_27 +// 0x09 -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX 0x01 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS 0x02 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL 0x03 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 0x04 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 0x05 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 0x06 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 0x07 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT 0x09 +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO28_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO28_STATUS_OFFSET 0x000000e0 +#define IO_BANK0_GPIO28_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO28_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO28_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO28_CTRL_OFFSET 0x000000e4 +#define IO_BANK0_GPIO28_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO28_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> sio_28 +// 0x06 -> pio0_28 +// 0x07 -> pio1_28 +// 0x09 -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX 0x01 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX 0x02 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA 0x03 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 0x04 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 0x05 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 0x06 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 0x07 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT 0x09 +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_GPIO29_STATUS +// Description : GPIO status +#define IO_BANK0_GPIO29_STATUS_OFFSET 0x000000e8 +#define IO_BANK0_GPIO29_STATUS_BITS 0x050a3300 +#define IO_BANK0_GPIO29_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB 26 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB 26 +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB 24 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB 24 +#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS 0x00080000 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB 19 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB 19 +#define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB 17 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB 17 +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS 0x00002000 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB 13 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB 13 +#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB 12 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB 12 +#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB 9 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB 9 +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB 8 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB 8 +#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO29_CTRL +// Description : GPIO control including function select and overrides. +#define IO_BANK0_GPIO29_CTRL_OFFSET 0x000000ec +#define IO_BANK0_GPIO29_CTRL_BITS 0x3003331f +#define IO_BANK0_GPIO29_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS 0x30000000 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB 29 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB 28 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS 0x00030000 +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB 17 +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB 16 +#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS 0x00003000 +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB 13 +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB 12 +#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET 0x0 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS 0x00000300 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB 9 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB 8 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> sio_29 +// 0x06 -> pio0_29 +// 0x07 -> pio1_29 +// 0x09 -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET 0x1f +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB 4 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB 0 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N 0x01 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX 0x02 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL 0x03 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 0x04 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 0x05 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 0x06 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 0x07 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN 0x09 +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_BANK0_INTR0 +// Description : Raw Interrupts +#define IO_BANK0_INTR0_OFFSET 0x000000f0 +#define IO_BANK0_INTR0_BITS 0xffffffff +#define IO_BANK0_INTR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR1 +// Description : Raw Interrupts +#define IO_BANK0_INTR1_OFFSET 0x000000f4 +#define IO_BANK0_INTR1_BITS 0xffffffff +#define IO_BANK0_INTR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR2 +// Description : Raw Interrupts +#define IO_BANK0_INTR2_OFFSET 0x000000f8 +#define IO_BANK0_INTR2_BITS 0xffffffff +#define IO_BANK0_INTR2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR3 +// Description : Raw Interrupts +#define IO_BANK0_INTR3_OFFSET 0x000000fc +#define IO_BANK0_INTR3_BITS 0x00ffffff +#define IO_BANK0_INTR3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE0 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE0_OFFSET 0x00000100 +#define IO_BANK0_PROC0_INTE0_BITS 0xffffffff +#define IO_BANK0_PROC0_INTE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE1 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE1_OFFSET 0x00000104 +#define IO_BANK0_PROC0_INTE1_BITS 0xffffffff +#define IO_BANK0_PROC0_INTE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE2 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE2_OFFSET 0x00000108 +#define IO_BANK0_PROC0_INTE2_BITS 0xffffffff +#define IO_BANK0_PROC0_INTE2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE3 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE3_OFFSET 0x0000010c +#define IO_BANK0_PROC0_INTE3_BITS 0x00ffffff +#define IO_BANK0_PROC0_INTE3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF0 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF0_OFFSET 0x00000110 +#define IO_BANK0_PROC0_INTF0_BITS 0xffffffff +#define IO_BANK0_PROC0_INTF0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF1 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF1_OFFSET 0x00000114 +#define IO_BANK0_PROC0_INTF1_BITS 0xffffffff +#define IO_BANK0_PROC0_INTF1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF2 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF2_OFFSET 0x00000118 +#define IO_BANK0_PROC0_INTF2_BITS 0xffffffff +#define IO_BANK0_PROC0_INTF2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF3 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF3_OFFSET 0x0000011c +#define IO_BANK0_PROC0_INTF3_BITS 0x00ffffff +#define IO_BANK0_PROC0_INTF3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS0 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS0_OFFSET 0x00000120 +#define IO_BANK0_PROC0_INTS0_BITS 0xffffffff +#define IO_BANK0_PROC0_INTS0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS1 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS1_OFFSET 0x00000124 +#define IO_BANK0_PROC0_INTS1_BITS 0xffffffff +#define IO_BANK0_PROC0_INTS1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS2 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS2_OFFSET 0x00000128 +#define IO_BANK0_PROC0_INTS2_BITS 0xffffffff +#define IO_BANK0_PROC0_INTS2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS3 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS3_OFFSET 0x0000012c +#define IO_BANK0_PROC0_INTS3_BITS 0x00ffffff +#define IO_BANK0_PROC0_INTS3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE0 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE0_OFFSET 0x00000130 +#define IO_BANK0_PROC1_INTE0_BITS 0xffffffff +#define IO_BANK0_PROC1_INTE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE1 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE1_OFFSET 0x00000134 +#define IO_BANK0_PROC1_INTE1_BITS 0xffffffff +#define IO_BANK0_PROC1_INTE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE2 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE2_OFFSET 0x00000138 +#define IO_BANK0_PROC1_INTE2_BITS 0xffffffff +#define IO_BANK0_PROC1_INTE2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE3 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE3_OFFSET 0x0000013c +#define IO_BANK0_PROC1_INTE3_BITS 0x00ffffff +#define IO_BANK0_PROC1_INTE3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF0 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF0_OFFSET 0x00000140 +#define IO_BANK0_PROC1_INTF0_BITS 0xffffffff +#define IO_BANK0_PROC1_INTF0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF1 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF1_OFFSET 0x00000144 +#define IO_BANK0_PROC1_INTF1_BITS 0xffffffff +#define IO_BANK0_PROC1_INTF1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF2 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF2_OFFSET 0x00000148 +#define IO_BANK0_PROC1_INTF2_BITS 0xffffffff +#define IO_BANK0_PROC1_INTF2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF3 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF3_OFFSET 0x0000014c +#define IO_BANK0_PROC1_INTF3_BITS 0x00ffffff +#define IO_BANK0_PROC1_INTF3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS0 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS0_OFFSET 0x00000150 +#define IO_BANK0_PROC1_INTS0_BITS 0xffffffff +#define IO_BANK0_PROC1_INTS0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS1 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS1_OFFSET 0x00000154 +#define IO_BANK0_PROC1_INTS1_BITS 0xffffffff +#define IO_BANK0_PROC1_INTS1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS2 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS2_OFFSET 0x00000158 +#define IO_BANK0_PROC1_INTS2_BITS 0xffffffff +#define IO_BANK0_PROC1_INTS2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS3 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS3_OFFSET 0x0000015c +#define IO_BANK0_PROC1_INTS3_BITS 0x00ffffff +#define IO_BANK0_PROC1_INTS3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE0 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET 0x00000160 +#define IO_BANK0_DORMANT_WAKE_INTE0_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE1 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET 0x00000164 +#define IO_BANK0_DORMANT_WAKE_INTE1_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE2 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET 0x00000168 +#define IO_BANK0_DORMANT_WAKE_INTE2_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTE2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE3 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET 0x0000016c +#define IO_BANK0_DORMANT_WAKE_INTE3_BITS 0x00ffffff +#define IO_BANK0_DORMANT_WAKE_INTE3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF0 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET 0x00000170 +#define IO_BANK0_DORMANT_WAKE_INTF0_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTF0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF1 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET 0x00000174 +#define IO_BANK0_DORMANT_WAKE_INTF1_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTF1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF2 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET 0x00000178 +#define IO_BANK0_DORMANT_WAKE_INTF2_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTF2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF3 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET 0x0000017c +#define IO_BANK0_DORMANT_WAKE_INTF3_BITS 0x00ffffff +#define IO_BANK0_DORMANT_WAKE_INTF3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS0 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET 0x00000180 +#define IO_BANK0_DORMANT_WAKE_INTS0_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTS0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS1 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET 0x00000184 +#define IO_BANK0_DORMANT_WAKE_INTS1_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTS1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS2 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET 0x00000188 +#define IO_BANK0_DORMANT_WAKE_INTS2_BITS 0xffffffff +#define IO_BANK0_DORMANT_WAKE_INTS2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS 0x80000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB 31 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS 0x40000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB 30 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS 0x20000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB 29 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS 0x10000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB 28 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS 0x08000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB 27 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS 0x04000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB 26 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS 0x02000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB 25 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS 0x01000000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB 24 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS3 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET 0x0000018c +#define IO_BANK0_DORMANT_WAKE_INTS3_BITS 0x00ffffff +#define IO_BANK0_DORMANT_WAKE_INTS3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS 0x00800000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB 23 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS 0x00400000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB 22 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS 0x00200000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB 21 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS 0x00100000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB 20 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS 0x00080000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB 19 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS 0x00040000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB 18 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS 0x00020000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB 17 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS 0x00010000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB 16 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS 0x00008000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB 15 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS 0x00004000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB 14 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS 0x00002000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB 13 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS 0x00001000 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB 12 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS 0x00000800 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB 11 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS 0x00000400 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB 10 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS 0x00000200 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB 9 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS 0x00000100 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB 8 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS 0x00000080 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB 7 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS 0x00000040 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB 6 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS 0x00000020 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB 5 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS 0x00000010 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB 4 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS 0x00000008 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB 3 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS 0x00000004 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB 2 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS 0x00000002 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB 1 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW +// Description : None +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET 0x0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS 0x00000001 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB 0 +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_IO_BANK0_DEFINED diff --git a/rp2040/hardware/regs/io_qspi.h b/rp2040/hardware/regs/io_qspi.h new file mode 100644 index 0000000..0c7c88d --- /dev/null +++ b/rp2040/hardware/regs/io_qspi.h @@ -0,0 +1,2931 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_QSPI +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_IO_QSPI_DEFINED +#define HARDWARE_REGS_IO_QSPI_DEFINED +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET 0x00000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET 0x00000004 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sclk +// 0x05 -> sio_30 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK 0x00 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 0x05 +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET 0x00000008 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET 0x0000000c +#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_ss_n +// 0x05 -> sio_31 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N 0x00 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 0x05 +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET 0x00000010 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET 0x00000014 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd0 +// 0x05 -> sio_32 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 0x00 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 0x05 +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET 0x00000018 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET 0x0000001c +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd1 +// 0x05 -> sio_33 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 0x00 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 0x05 +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET 0x00000020 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET 0x00000024 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd2 +// 0x05 -> sio_34 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 0x00 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 0x05 +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS +// Description : GPIO status +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET 0x00000028 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS 0x050a3300 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS 0x04000000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB 26 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB 26 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD +// Description : interrupt from pad before override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS 0x01000000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB 24 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB 24 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI +// Description : input signal to peripheral, after override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS 0x00080000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB 19 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB 19 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD +// Description : input signal from pad, before override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS 0x00020000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS 0x00002000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI +// Description : output enable from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS 0x00001000 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS 0x00000200 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI +// Description : output signal from selected peripheral, before register +// override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS 0x00000100 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL +// Description : GPIO control including function select and overrides. +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET 0x0000002c +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS 0x3003331f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET 0x0000001f +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER +// Description : 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS 0x30000000 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB 29 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB 28 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER +// Description : 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS 0x00030000 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB 17 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB 16 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER +// Description : 0x0 -> drive output enable from peripheral signal selected by +// funcsel +// 0x1 -> drive output enable from inverse of peripheral signal +// selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS 0x00003000 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB 13 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB 12 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER +// Description : 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected +// by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS 0x00000300 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB 9 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB 8 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL 0x0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT 0x1 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW 0x2 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH 0x3 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd3 +// 0x05 -> sio_35 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET 0x1f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS 0x0000001f +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB 4 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB 0 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 0x00 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 0x05 +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL 0x1f +// ============================================================================= +// Register : IO_QSPI_INTR +// Description : Raw Interrupts +#define IO_QSPI_INTR_OFFSET 0x00000030 +#define IO_QSPI_INTR_BITS 0x00ffffff +#define IO_QSPI_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTE +// Description : Interrupt Enable for proc0 +#define IO_QSPI_PROC0_INTE_OFFSET 0x00000034 +#define IO_QSPI_PROC0_INTE_BITS 0x00ffffff +#define IO_QSPI_PROC0_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTF +// Description : Interrupt Force for proc0 +#define IO_QSPI_PROC0_INTF_OFFSET 0x00000038 +#define IO_QSPI_PROC0_INTF_BITS 0x00ffffff +#define IO_QSPI_PROC0_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTS +// Description : Interrupt status after masking & forcing for proc0 +#define IO_QSPI_PROC0_INTS_OFFSET 0x0000003c +#define IO_QSPI_PROC0_INTS_BITS 0x00ffffff +#define IO_QSPI_PROC0_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTE +// Description : Interrupt Enable for proc1 +#define IO_QSPI_PROC1_INTE_OFFSET 0x00000040 +#define IO_QSPI_PROC1_INTE_BITS 0x00ffffff +#define IO_QSPI_PROC1_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTF +// Description : Interrupt Force for proc1 +#define IO_QSPI_PROC1_INTF_OFFSET 0x00000044 +#define IO_QSPI_PROC1_INTF_BITS 0x00ffffff +#define IO_QSPI_PROC1_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTS +// Description : Interrupt status after masking & forcing for proc1 +#define IO_QSPI_PROC1_INTS_OFFSET 0x00000048 +#define IO_QSPI_PROC1_INTS_BITS 0x00ffffff +#define IO_QSPI_PROC1_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTE +// Description : Interrupt Enable for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET 0x0000004c +#define IO_QSPI_DORMANT_WAKE_INTE_BITS 0x00ffffff +#define IO_QSPI_DORMANT_WAKE_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTF +// Description : Interrupt Force for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET 0x00000050 +#define IO_QSPI_DORMANT_WAKE_INTF_BITS 0x00ffffff +#define IO_QSPI_DORMANT_WAKE_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTS +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET 0x00000054 +#define IO_QSPI_DORMANT_WAKE_INTS_BITS 0x00ffffff +#define IO_QSPI_DORMANT_WAKE_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS 0x00800000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB 23 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB 23 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS 0x00400000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB 22 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB 22 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS 0x00200000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB 21 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB 21 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS 0x00100000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB 20 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB 20 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS 0x00080000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB 19 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB 19 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS 0x00040000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB 18 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB 18 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS 0x00020000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB 17 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB 17 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS 0x00010000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB 16 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB 16 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS 0x00008000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB 15 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB 15 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS 0x00004000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB 14 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB 14 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS 0x00002000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB 13 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB 13 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS 0x00001000 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB 12 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB 12 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS 0x00000800 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB 11 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB 11 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS 0x00000400 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB 10 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB 10 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS 0x00000200 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB 9 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB 9 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS 0x00000100 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB 8 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB 8 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS 0x00000080 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB 7 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB 7 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS 0x00000040 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB 6 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB 6 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS 0x00000020 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB 5 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB 5 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS 0x00000010 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB 4 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB 4 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS 0x00000008 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB 3 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB 3 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS 0x00000004 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB 2 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB 2 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS 0x00000002 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB 1 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB 1 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +// Description : None +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET 0x0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS 0x00000001 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB 0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB 0 +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_IO_QSPI_DEFINED diff --git a/rp2040/hardware/regs/m0plus.h b/rp2040/hardware/regs/m0plus.h new file mode 100644 index 0000000..fac8e8b --- /dev/null +++ b/rp2040/hardware/regs/m0plus.h @@ -0,0 +1,1149 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : M0PLUS +// Version : 1 +// Bus type : ahbl +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_M0PLUS_DEFINED +#define HARDWARE_REGS_M0PLUS_DEFINED +// ============================================================================= +// Register : M0PLUS_SYST_CSR +// Description : Use the SysTick Control and Status Register to enable the +// SysTick features. +#define M0PLUS_SYST_CSR_OFFSET 0x0000e010 +#define M0PLUS_SYST_CSR_BITS 0x00010007 +#define M0PLUS_SYST_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_COUNTFLAG +// Description : Returns 1 if timer counted to 0 since last time this was read. +// Clears on read by application or debugger. +#define M0PLUS_SYST_CSR_COUNTFLAG_RESET 0x0 +#define M0PLUS_SYST_CSR_COUNTFLAG_BITS 0x00010000 +#define M0PLUS_SYST_CSR_COUNTFLAG_MSB 16 +#define M0PLUS_SYST_CSR_COUNTFLAG_LSB 16 +#define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_CLKSOURCE +// Description : SysTick clock source. Always reads as one if SYST_CALIB reports +// NOREF. +// Selects the SysTick timer clock source: +// 0 = External reference clock. +// 1 = Processor clock. +#define M0PLUS_SYST_CSR_CLKSOURCE_RESET 0x0 +#define M0PLUS_SYST_CSR_CLKSOURCE_BITS 0x00000004 +#define M0PLUS_SYST_CSR_CLKSOURCE_MSB 2 +#define M0PLUS_SYST_CSR_CLKSOURCE_LSB 2 +#define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_TICKINT +// Description : Enables SysTick exception request: +// 0 = Counting down to zero does not assert the SysTick exception +// request. +// 1 = Counting down to zero to asserts the SysTick exception +// request. +#define M0PLUS_SYST_CSR_TICKINT_RESET 0x0 +#define M0PLUS_SYST_CSR_TICKINT_BITS 0x00000002 +#define M0PLUS_SYST_CSR_TICKINT_MSB 1 +#define M0PLUS_SYST_CSR_TICKINT_LSB 1 +#define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CSR_ENABLE +// Description : Enable SysTick counter: +// 0 = Counter disabled. +// 1 = Counter enabled. +#define M0PLUS_SYST_CSR_ENABLE_RESET 0x0 +#define M0PLUS_SYST_CSR_ENABLE_BITS 0x00000001 +#define M0PLUS_SYST_CSR_ENABLE_MSB 0 +#define M0PLUS_SYST_CSR_ENABLE_LSB 0 +#define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SYST_RVR +// Description : Use the SysTick Reload Value Register to specify the start +// value to load into the current value register when the counter +// reaches 0. It can be any value between 0 and 0x00FFFFFF. A +// start value of 0 is possible, but has no effect because the +// SysTick interrupt and COUNTFLAG are activated when counting +// from 1 to 0. The reset value of this register is UNKNOWN. +// To generate a multi-shot timer with a period of N processor +// clock cycles, use a RELOAD value of N-1. For example, if the +// SysTick interrupt is required every 100 clock pulses, set +// RELOAD to 99. +#define M0PLUS_SYST_RVR_OFFSET 0x0000e014 +#define M0PLUS_SYST_RVR_BITS 0x00ffffff +#define M0PLUS_SYST_RVR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_RVR_RELOAD +// Description : Value to load into the SysTick Current Value Register when the +// counter reaches 0. +#define M0PLUS_SYST_RVR_RELOAD_RESET 0x000000 +#define M0PLUS_SYST_RVR_RELOAD_BITS 0x00ffffff +#define M0PLUS_SYST_RVR_RELOAD_MSB 23 +#define M0PLUS_SYST_RVR_RELOAD_LSB 0 +#define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SYST_CVR +// Description : Use the SysTick Current Value Register to find the current +// value in the register. The reset value of this register is +// UNKNOWN. +#define M0PLUS_SYST_CVR_OFFSET 0x0000e018 +#define M0PLUS_SYST_CVR_BITS 0x00ffffff +#define M0PLUS_SYST_CVR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CVR_CURRENT +// Description : Reads return the current value of the SysTick counter. This +// register is write-clear. Writing to it with any value clears +// the register to 0. Clearing this register also clears the +// COUNTFLAG bit of the SysTick Control and Status Register. +#define M0PLUS_SYST_CVR_CURRENT_RESET 0x000000 +#define M0PLUS_SYST_CVR_CURRENT_BITS 0x00ffffff +#define M0PLUS_SYST_CVR_CURRENT_MSB 23 +#define M0PLUS_SYST_CVR_CURRENT_LSB 0 +#define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SYST_CALIB +// Description : Use the SysTick Calibration Value Register to enable software +// to scale to any required speed using divide and multiply. +#define M0PLUS_SYST_CALIB_OFFSET 0x0000e01c +#define M0PLUS_SYST_CALIB_BITS 0xc0ffffff +#define M0PLUS_SYST_CALIB_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CALIB_NOREF +// Description : If reads as 1, the Reference clock is not provided - the +// CLKSOURCE bit of the SysTick Control and Status register will +// be forced to 1 and cannot be cleared to 0. +#define M0PLUS_SYST_CALIB_NOREF_RESET 0x0 +#define M0PLUS_SYST_CALIB_NOREF_BITS 0x80000000 +#define M0PLUS_SYST_CALIB_NOREF_MSB 31 +#define M0PLUS_SYST_CALIB_NOREF_LSB 31 +#define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CALIB_SKEW +// Description : If reads as 1, the calibration value for 10ms is inexact (due +// to clock frequency). +#define M0PLUS_SYST_CALIB_SKEW_RESET 0x0 +#define M0PLUS_SYST_CALIB_SKEW_BITS 0x40000000 +#define M0PLUS_SYST_CALIB_SKEW_MSB 30 +#define M0PLUS_SYST_CALIB_SKEW_LSB 30 +#define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SYST_CALIB_TENMS +// Description : An optional Reload value to be used for 10ms (100Hz) timing, +// subject to system clock skew errors. If the value reads as 0, +// the calibration value is not known. +#define M0PLUS_SYST_CALIB_TENMS_RESET 0x000000 +#define M0PLUS_SYST_CALIB_TENMS_BITS 0x00ffffff +#define M0PLUS_SYST_CALIB_TENMS_MSB 23 +#define M0PLUS_SYST_CALIB_TENMS_LSB 0 +#define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_NVIC_ISER +// Description : Use the Interrupt Set-Enable Register to enable interrupts and +// determine which interrupts are currently enabled. +// If a pending interrupt is enabled, the NVIC activates the +// interrupt based on its priority. If an interrupt is not +// enabled, asserting its interrupt signal changes the interrupt +// state to pending, but the NVIC never activates the interrupt, +// regardless of its priority. +#define M0PLUS_NVIC_ISER_OFFSET 0x0000e100 +#define M0PLUS_NVIC_ISER_BITS 0xffffffff +#define M0PLUS_NVIC_ISER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ISER_SETENA +// Description : Interrupt set-enable bits. +// Write: +// 0 = No effect. +// 1 = Enable interrupt. +// Read: +// 0 = Interrupt disabled. +// 1 = Interrupt enabled. +#define M0PLUS_NVIC_ISER_SETENA_RESET 0x00000000 +#define M0PLUS_NVIC_ISER_SETENA_BITS 0xffffffff +#define M0PLUS_NVIC_ISER_SETENA_MSB 31 +#define M0PLUS_NVIC_ISER_SETENA_LSB 0 +#define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_ICER +// Description : Use the Interrupt Clear-Enable Registers to disable interrupts +// and determine which interrupts are currently enabled. +#define M0PLUS_NVIC_ICER_OFFSET 0x0000e180 +#define M0PLUS_NVIC_ICER_BITS 0xffffffff +#define M0PLUS_NVIC_ICER_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ICER_CLRENA +// Description : Interrupt clear-enable bits. +// Write: +// 0 = No effect. +// 1 = Disable interrupt. +// Read: +// 0 = Interrupt disabled. +// 1 = Interrupt enabled. +#define M0PLUS_NVIC_ICER_CLRENA_RESET 0x00000000 +#define M0PLUS_NVIC_ICER_CLRENA_BITS 0xffffffff +#define M0PLUS_NVIC_ICER_CLRENA_MSB 31 +#define M0PLUS_NVIC_ICER_CLRENA_LSB 0 +#define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_ISPR +// Description : The NVIC_ISPR forces interrupts into the pending state, and +// shows which interrupts are pending. +#define M0PLUS_NVIC_ISPR_OFFSET 0x0000e200 +#define M0PLUS_NVIC_ISPR_BITS 0xffffffff +#define M0PLUS_NVIC_ISPR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ISPR_SETPEND +// Description : Interrupt set-pending bits. +// Write: +// 0 = No effect. +// 1 = Changes interrupt state to pending. +// Read: +// 0 = Interrupt is not pending. +// 1 = Interrupt is pending. +// Note: Writing 1 to the NVIC_ISPR bit corresponding to: +// An interrupt that is pending has no effect. +// A disabled interrupt sets the state of that interrupt to +// pending. +#define M0PLUS_NVIC_ISPR_SETPEND_RESET 0x00000000 +#define M0PLUS_NVIC_ISPR_SETPEND_BITS 0xffffffff +#define M0PLUS_NVIC_ISPR_SETPEND_MSB 31 +#define M0PLUS_NVIC_ISPR_SETPEND_LSB 0 +#define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_ICPR +// Description : Use the Interrupt Clear-Pending Register to clear pending +// interrupts and determine which interrupts are currently +// pending. +#define M0PLUS_NVIC_ICPR_OFFSET 0x0000e280 +#define M0PLUS_NVIC_ICPR_BITS 0xffffffff +#define M0PLUS_NVIC_ICPR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_ICPR_CLRPEND +// Description : Interrupt clear-pending bits. +// Write: +// 0 = No effect. +// 1 = Removes pending state and interrupt. +// Read: +// 0 = Interrupt is not pending. +// 1 = Interrupt is pending. +#define M0PLUS_NVIC_ICPR_CLRPEND_RESET 0x00000000 +#define M0PLUS_NVIC_ICPR_CLRPEND_BITS 0xffffffff +#define M0PLUS_NVIC_ICPR_CLRPEND_MSB 31 +#define M0PLUS_NVIC_ICPR_CLRPEND_LSB 0 +#define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR0 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +// Note: Writing 1 to an NVIC_ICPR bit does not affect the active +// state of the corresponding interrupt. +// These registers are only word-accessible +#define M0PLUS_NVIC_IPR0_OFFSET 0x0000e400 +#define M0PLUS_NVIC_IPR0_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_3 +// Description : Priority of interrupt 3 +#define M0PLUS_NVIC_IPR0_IP_3_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_3_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR0_IP_3_MSB 31 +#define M0PLUS_NVIC_IPR0_IP_3_LSB 30 +#define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_2 +// Description : Priority of interrupt 2 +#define M0PLUS_NVIC_IPR0_IP_2_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_2_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR0_IP_2_MSB 23 +#define M0PLUS_NVIC_IPR0_IP_2_LSB 22 +#define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_1 +// Description : Priority of interrupt 1 +#define M0PLUS_NVIC_IPR0_IP_1_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_1_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR0_IP_1_MSB 15 +#define M0PLUS_NVIC_IPR0_IP_1_LSB 14 +#define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR0_IP_0 +// Description : Priority of interrupt 0 +#define M0PLUS_NVIC_IPR0_IP_0_RESET 0x0 +#define M0PLUS_NVIC_IPR0_IP_0_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR0_IP_0_MSB 7 +#define M0PLUS_NVIC_IPR0_IP_0_LSB 6 +#define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR1 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR1_OFFSET 0x0000e404 +#define M0PLUS_NVIC_IPR1_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_7 +// Description : Priority of interrupt 7 +#define M0PLUS_NVIC_IPR1_IP_7_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_7_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR1_IP_7_MSB 31 +#define M0PLUS_NVIC_IPR1_IP_7_LSB 30 +#define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_6 +// Description : Priority of interrupt 6 +#define M0PLUS_NVIC_IPR1_IP_6_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_6_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR1_IP_6_MSB 23 +#define M0PLUS_NVIC_IPR1_IP_6_LSB 22 +#define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_5 +// Description : Priority of interrupt 5 +#define M0PLUS_NVIC_IPR1_IP_5_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_5_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR1_IP_5_MSB 15 +#define M0PLUS_NVIC_IPR1_IP_5_LSB 14 +#define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR1_IP_4 +// Description : Priority of interrupt 4 +#define M0PLUS_NVIC_IPR1_IP_4_RESET 0x0 +#define M0PLUS_NVIC_IPR1_IP_4_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR1_IP_4_MSB 7 +#define M0PLUS_NVIC_IPR1_IP_4_LSB 6 +#define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR2 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR2_OFFSET 0x0000e408 +#define M0PLUS_NVIC_IPR2_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_11 +// Description : Priority of interrupt 11 +#define M0PLUS_NVIC_IPR2_IP_11_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_11_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR2_IP_11_MSB 31 +#define M0PLUS_NVIC_IPR2_IP_11_LSB 30 +#define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_10 +// Description : Priority of interrupt 10 +#define M0PLUS_NVIC_IPR2_IP_10_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_10_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR2_IP_10_MSB 23 +#define M0PLUS_NVIC_IPR2_IP_10_LSB 22 +#define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_9 +// Description : Priority of interrupt 9 +#define M0PLUS_NVIC_IPR2_IP_9_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_9_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR2_IP_9_MSB 15 +#define M0PLUS_NVIC_IPR2_IP_9_LSB 14 +#define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR2_IP_8 +// Description : Priority of interrupt 8 +#define M0PLUS_NVIC_IPR2_IP_8_RESET 0x0 +#define M0PLUS_NVIC_IPR2_IP_8_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR2_IP_8_MSB 7 +#define M0PLUS_NVIC_IPR2_IP_8_LSB 6 +#define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR3 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR3_OFFSET 0x0000e40c +#define M0PLUS_NVIC_IPR3_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_15 +// Description : Priority of interrupt 15 +#define M0PLUS_NVIC_IPR3_IP_15_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_15_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR3_IP_15_MSB 31 +#define M0PLUS_NVIC_IPR3_IP_15_LSB 30 +#define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_14 +// Description : Priority of interrupt 14 +#define M0PLUS_NVIC_IPR3_IP_14_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_14_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR3_IP_14_MSB 23 +#define M0PLUS_NVIC_IPR3_IP_14_LSB 22 +#define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_13 +// Description : Priority of interrupt 13 +#define M0PLUS_NVIC_IPR3_IP_13_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_13_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR3_IP_13_MSB 15 +#define M0PLUS_NVIC_IPR3_IP_13_LSB 14 +#define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR3_IP_12 +// Description : Priority of interrupt 12 +#define M0PLUS_NVIC_IPR3_IP_12_RESET 0x0 +#define M0PLUS_NVIC_IPR3_IP_12_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR3_IP_12_MSB 7 +#define M0PLUS_NVIC_IPR3_IP_12_LSB 6 +#define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR4 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR4_OFFSET 0x0000e410 +#define M0PLUS_NVIC_IPR4_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_19 +// Description : Priority of interrupt 19 +#define M0PLUS_NVIC_IPR4_IP_19_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_19_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR4_IP_19_MSB 31 +#define M0PLUS_NVIC_IPR4_IP_19_LSB 30 +#define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_18 +// Description : Priority of interrupt 18 +#define M0PLUS_NVIC_IPR4_IP_18_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_18_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR4_IP_18_MSB 23 +#define M0PLUS_NVIC_IPR4_IP_18_LSB 22 +#define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_17 +// Description : Priority of interrupt 17 +#define M0PLUS_NVIC_IPR4_IP_17_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_17_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR4_IP_17_MSB 15 +#define M0PLUS_NVIC_IPR4_IP_17_LSB 14 +#define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR4_IP_16 +// Description : Priority of interrupt 16 +#define M0PLUS_NVIC_IPR4_IP_16_RESET 0x0 +#define M0PLUS_NVIC_IPR4_IP_16_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR4_IP_16_MSB 7 +#define M0PLUS_NVIC_IPR4_IP_16_LSB 6 +#define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR5 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR5_OFFSET 0x0000e414 +#define M0PLUS_NVIC_IPR5_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR5_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_23 +// Description : Priority of interrupt 23 +#define M0PLUS_NVIC_IPR5_IP_23_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_23_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR5_IP_23_MSB 31 +#define M0PLUS_NVIC_IPR5_IP_23_LSB 30 +#define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_22 +// Description : Priority of interrupt 22 +#define M0PLUS_NVIC_IPR5_IP_22_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_22_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR5_IP_22_MSB 23 +#define M0PLUS_NVIC_IPR5_IP_22_LSB 22 +#define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_21 +// Description : Priority of interrupt 21 +#define M0PLUS_NVIC_IPR5_IP_21_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_21_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR5_IP_21_MSB 15 +#define M0PLUS_NVIC_IPR5_IP_21_LSB 14 +#define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR5_IP_20 +// Description : Priority of interrupt 20 +#define M0PLUS_NVIC_IPR5_IP_20_RESET 0x0 +#define M0PLUS_NVIC_IPR5_IP_20_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR5_IP_20_MSB 7 +#define M0PLUS_NVIC_IPR5_IP_20_LSB 6 +#define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR6 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR6_OFFSET 0x0000e418 +#define M0PLUS_NVIC_IPR6_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR6_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_27 +// Description : Priority of interrupt 27 +#define M0PLUS_NVIC_IPR6_IP_27_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_27_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR6_IP_27_MSB 31 +#define M0PLUS_NVIC_IPR6_IP_27_LSB 30 +#define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_26 +// Description : Priority of interrupt 26 +#define M0PLUS_NVIC_IPR6_IP_26_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_26_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR6_IP_26_MSB 23 +#define M0PLUS_NVIC_IPR6_IP_26_LSB 22 +#define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_25 +// Description : Priority of interrupt 25 +#define M0PLUS_NVIC_IPR6_IP_25_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_25_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR6_IP_25_MSB 15 +#define M0PLUS_NVIC_IPR6_IP_25_LSB 14 +#define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR6_IP_24 +// Description : Priority of interrupt 24 +#define M0PLUS_NVIC_IPR6_IP_24_RESET 0x0 +#define M0PLUS_NVIC_IPR6_IP_24_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR6_IP_24_MSB 7 +#define M0PLUS_NVIC_IPR6_IP_24_LSB 6 +#define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_NVIC_IPR7 +// Description : Use the Interrupt Priority Registers to assign a priority from +// 0 to 3 to each of the available interrupts. 0 is the highest +// priority, and 3 is the lowest. +#define M0PLUS_NVIC_IPR7_OFFSET 0x0000e41c +#define M0PLUS_NVIC_IPR7_BITS 0xc0c0c0c0 +#define M0PLUS_NVIC_IPR7_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_31 +// Description : Priority of interrupt 31 +#define M0PLUS_NVIC_IPR7_IP_31_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_31_BITS 0xc0000000 +#define M0PLUS_NVIC_IPR7_IP_31_MSB 31 +#define M0PLUS_NVIC_IPR7_IP_31_LSB 30 +#define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_30 +// Description : Priority of interrupt 30 +#define M0PLUS_NVIC_IPR7_IP_30_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_30_BITS 0x00c00000 +#define M0PLUS_NVIC_IPR7_IP_30_MSB 23 +#define M0PLUS_NVIC_IPR7_IP_30_LSB 22 +#define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_29 +// Description : Priority of interrupt 29 +#define M0PLUS_NVIC_IPR7_IP_29_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_29_BITS 0x0000c000 +#define M0PLUS_NVIC_IPR7_IP_29_MSB 15 +#define M0PLUS_NVIC_IPR7_IP_29_LSB 14 +#define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_NVIC_IPR7_IP_28 +// Description : Priority of interrupt 28 +#define M0PLUS_NVIC_IPR7_IP_28_RESET 0x0 +#define M0PLUS_NVIC_IPR7_IP_28_BITS 0x000000c0 +#define M0PLUS_NVIC_IPR7_IP_28_MSB 7 +#define M0PLUS_NVIC_IPR7_IP_28_LSB 6 +#define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_CPUID +// Description : Read the CPU ID Base Register to determine: the ID number of +// the processor core, the version number of the processor core, +// the implementation details of the processor core. +#define M0PLUS_CPUID_OFFSET 0x0000ed00 +#define M0PLUS_CPUID_BITS 0xffffffff +#define M0PLUS_CPUID_RESET 0x410cc601 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_IMPLEMENTER +// Description : Implementor code: 0x41 = ARM +#define M0PLUS_CPUID_IMPLEMENTER_RESET 0x41 +#define M0PLUS_CPUID_IMPLEMENTER_BITS 0xff000000 +#define M0PLUS_CPUID_IMPLEMENTER_MSB 31 +#define M0PLUS_CPUID_IMPLEMENTER_LSB 24 +#define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_VARIANT +// Description : Major revision number n in the rnpm revision status: +// 0x0 = Revision 0. +#define M0PLUS_CPUID_VARIANT_RESET 0x0 +#define M0PLUS_CPUID_VARIANT_BITS 0x00f00000 +#define M0PLUS_CPUID_VARIANT_MSB 23 +#define M0PLUS_CPUID_VARIANT_LSB 20 +#define M0PLUS_CPUID_VARIANT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_ARCHITECTURE +// Description : Constant that defines the architecture of the processor: +// 0xC = ARMv6-M architecture. +#define M0PLUS_CPUID_ARCHITECTURE_RESET 0xc +#define M0PLUS_CPUID_ARCHITECTURE_BITS 0x000f0000 +#define M0PLUS_CPUID_ARCHITECTURE_MSB 19 +#define M0PLUS_CPUID_ARCHITECTURE_LSB 16 +#define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_PARTNO +// Description : Number of processor within family: 0xC60 = Cortex-M0+ +#define M0PLUS_CPUID_PARTNO_RESET 0xc60 +#define M0PLUS_CPUID_PARTNO_BITS 0x0000fff0 +#define M0PLUS_CPUID_PARTNO_MSB 15 +#define M0PLUS_CPUID_PARTNO_LSB 4 +#define M0PLUS_CPUID_PARTNO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CPUID_REVISION +// Description : Minor revision number m in the rnpm revision status: +// 0x1 = Patch 1. +#define M0PLUS_CPUID_REVISION_RESET 0x1 +#define M0PLUS_CPUID_REVISION_BITS 0x0000000f +#define M0PLUS_CPUID_REVISION_MSB 3 +#define M0PLUS_CPUID_REVISION_LSB 0 +#define M0PLUS_CPUID_REVISION_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_ICSR +// Description : Use the Interrupt Control State Register to set a pending +// Non-Maskable Interrupt (NMI), set or clear a pending PendSV, +// set or clear a pending SysTick, check for pending exceptions, +// check the vector number of the highest priority pended +// exception, check the vector number of the active exception. +#define M0PLUS_ICSR_OFFSET 0x0000ed04 +#define M0PLUS_ICSR_BITS 0x9edff1ff +#define M0PLUS_ICSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_NMIPENDSET +// Description : Setting this bit will activate an NMI. Since NMI is the highest +// priority exception, it will activate as soon as it is +// registered. +// NMI set-pending bit. +// Write: +// 0 = No effect. +// 1 = Changes NMI exception state to pending. +// Read: +// 0 = NMI exception is not pending. +// 1 = NMI exception is pending. +// Because NMI is the highest-priority exception, normally the +// processor enters the NMI +// exception handler as soon as it detects a write of 1 to this +// bit. Entering the handler then clears +// this bit to 0. This means a read of this bit by the NMI +// exception handler returns 1 only if the +// NMI signal is reasserted while the processor is executing that +// handler. +#define M0PLUS_ICSR_NMIPENDSET_RESET 0x0 +#define M0PLUS_ICSR_NMIPENDSET_BITS 0x80000000 +#define M0PLUS_ICSR_NMIPENDSET_MSB 31 +#define M0PLUS_ICSR_NMIPENDSET_LSB 31 +#define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSVSET +// Description : PendSV set-pending bit. +// Write: +// 0 = No effect. +// 1 = Changes PendSV exception state to pending. +// Read: +// 0 = PendSV exception is not pending. +// 1 = PendSV exception is pending. +// Writing 1 to this bit is the only way to set the PendSV +// exception state to pending. +#define M0PLUS_ICSR_PENDSVSET_RESET 0x0 +#define M0PLUS_ICSR_PENDSVSET_BITS 0x10000000 +#define M0PLUS_ICSR_PENDSVSET_MSB 28 +#define M0PLUS_ICSR_PENDSVSET_LSB 28 +#define M0PLUS_ICSR_PENDSVSET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSVCLR +// Description : PendSV clear-pending bit. +// Write: +// 0 = No effect. +// 1 = Removes the pending state from the PendSV exception. +#define M0PLUS_ICSR_PENDSVCLR_RESET 0x0 +#define M0PLUS_ICSR_PENDSVCLR_BITS 0x08000000 +#define M0PLUS_ICSR_PENDSVCLR_MSB 27 +#define M0PLUS_ICSR_PENDSVCLR_LSB 27 +#define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSTSET +// Description : SysTick exception set-pending bit. +// Write: +// 0 = No effect. +// 1 = Changes SysTick exception state to pending. +// Read: +// 0 = SysTick exception is not pending. +// 1 = SysTick exception is pending. +#define M0PLUS_ICSR_PENDSTSET_RESET 0x0 +#define M0PLUS_ICSR_PENDSTSET_BITS 0x04000000 +#define M0PLUS_ICSR_PENDSTSET_MSB 26 +#define M0PLUS_ICSR_PENDSTSET_LSB 26 +#define M0PLUS_ICSR_PENDSTSET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_PENDSTCLR +// Description : SysTick exception clear-pending bit. +// Write: +// 0 = No effect. +// 1 = Removes the pending state from the SysTick exception. +// This bit is WO. On a register read its value is Unknown. +#define M0PLUS_ICSR_PENDSTCLR_RESET 0x0 +#define M0PLUS_ICSR_PENDSTCLR_BITS 0x02000000 +#define M0PLUS_ICSR_PENDSTCLR_MSB 25 +#define M0PLUS_ICSR_PENDSTCLR_LSB 25 +#define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_ISRPREEMPT +// Description : The system can only access this bit when the core is halted. It +// indicates that a pending interrupt is to be taken in the next +// running cycle. If C_MASKINTS is clear in the Debug Halting +// Control and Status Register, the interrupt is serviced. +#define M0PLUS_ICSR_ISRPREEMPT_RESET 0x0 +#define M0PLUS_ICSR_ISRPREEMPT_BITS 0x00800000 +#define M0PLUS_ICSR_ISRPREEMPT_MSB 23 +#define M0PLUS_ICSR_ISRPREEMPT_LSB 23 +#define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_ISRPENDING +// Description : External interrupt pending flag +#define M0PLUS_ICSR_ISRPENDING_RESET 0x0 +#define M0PLUS_ICSR_ISRPENDING_BITS 0x00400000 +#define M0PLUS_ICSR_ISRPENDING_MSB 22 +#define M0PLUS_ICSR_ISRPENDING_LSB 22 +#define M0PLUS_ICSR_ISRPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_VECTPENDING +// Description : Indicates the exception number for the highest priority pending +// exception: 0 = no pending exceptions. Non zero = The pending +// state includes the effect of memory-mapped enable and mask +// registers. It does not include the PRIMASK special-purpose +// register qualifier. +#define M0PLUS_ICSR_VECTPENDING_RESET 0x000 +#define M0PLUS_ICSR_VECTPENDING_BITS 0x001ff000 +#define M0PLUS_ICSR_VECTPENDING_MSB 20 +#define M0PLUS_ICSR_VECTPENDING_LSB 12 +#define M0PLUS_ICSR_VECTPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_ICSR_VECTACTIVE +// Description : Active exception number field. Reset clears the VECTACTIVE +// field. +#define M0PLUS_ICSR_VECTACTIVE_RESET 0x000 +#define M0PLUS_ICSR_VECTACTIVE_BITS 0x000001ff +#define M0PLUS_ICSR_VECTACTIVE_MSB 8 +#define M0PLUS_ICSR_VECTACTIVE_LSB 0 +#define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_VTOR +// Description : The VTOR holds the vector table offset address. +#define M0PLUS_VTOR_OFFSET 0x0000ed08 +#define M0PLUS_VTOR_BITS 0xffffff00 +#define M0PLUS_VTOR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_VTOR_TBLOFF +// Description : Bits [31:8] of the indicate the vector table offset address. +#define M0PLUS_VTOR_TBLOFF_RESET 0x000000 +#define M0PLUS_VTOR_TBLOFF_BITS 0xffffff00 +#define M0PLUS_VTOR_TBLOFF_MSB 31 +#define M0PLUS_VTOR_TBLOFF_LSB 8 +#define M0PLUS_VTOR_TBLOFF_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_AIRCR +// Description : Use the Application Interrupt and Reset Control Register to: +// determine data endianness, clear all active state information +// from debug halt mode, request a system reset. +#define M0PLUS_AIRCR_OFFSET 0x0000ed0c +#define M0PLUS_AIRCR_BITS 0xffff8006 +#define M0PLUS_AIRCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_VECTKEY +// Description : Register key: +// Reads as Unknown +// On writes, write 0x05FA to VECTKEY, otherwise the write is +// ignored. +#define M0PLUS_AIRCR_VECTKEY_RESET 0x0000 +#define M0PLUS_AIRCR_VECTKEY_BITS 0xffff0000 +#define M0PLUS_AIRCR_VECTKEY_MSB 31 +#define M0PLUS_AIRCR_VECTKEY_LSB 16 +#define M0PLUS_AIRCR_VECTKEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_ENDIANESS +// Description : Data endianness implemented: +// 0 = Little-endian. +#define M0PLUS_AIRCR_ENDIANESS_RESET 0x0 +#define M0PLUS_AIRCR_ENDIANESS_BITS 0x00008000 +#define M0PLUS_AIRCR_ENDIANESS_MSB 15 +#define M0PLUS_AIRCR_ENDIANESS_LSB 15 +#define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_SYSRESETREQ +// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the +// outer system to be asserted to request a reset. The intention +// is to force a large system reset of all major components except +// for debug. The C_HALT bit in the DHCSR is cleared as a result +// of the system reset requested. The debugger does not lose +// contact with the device. +#define M0PLUS_AIRCR_SYSRESETREQ_RESET 0x0 +#define M0PLUS_AIRCR_SYSRESETREQ_BITS 0x00000004 +#define M0PLUS_AIRCR_SYSRESETREQ_MSB 2 +#define M0PLUS_AIRCR_SYSRESETREQ_LSB 2 +#define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_AIRCR_VECTCLRACTIVE +// Description : Clears all active state information for fixed and configurable +// exceptions. This bit: is self-clearing, can only be set by the +// DAP when the core is halted. When set: clears all active +// exception status of the processor, forces a return to Thread +// mode, forces an IPSR of 0. A debugger must re-initialize the +// stack. +#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET 0x0 +#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS 0x00000002 +#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB 1 +#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB 1 +#define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SCR +// Description : System Control Register. Use the System Control Register for +// power-management functions: signal to the system when the +// processor can enter a low power state, control how the +// processor enters and exits low power states. +#define M0PLUS_SCR_OFFSET 0x0000ed10 +#define M0PLUS_SCR_BITS 0x00000016 +#define M0PLUS_SCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SCR_SEVONPEND +// Description : Send Event on Pending bit: +// 0 = Only enabled interrupts or events can wakeup the processor, +// disabled interrupts are excluded. +// 1 = Enabled events and all interrupts, including disabled +// interrupts, can wakeup the processor. +// When an event or interrupt becomes pending, the event signal +// wakes up the processor from WFE. If the +// processor is not waiting for an event, the event is registered +// and affects the next WFE. +// The processor also wakes up on execution of an SEV instruction +// or an external event. +#define M0PLUS_SCR_SEVONPEND_RESET 0x0 +#define M0PLUS_SCR_SEVONPEND_BITS 0x00000010 +#define M0PLUS_SCR_SEVONPEND_MSB 4 +#define M0PLUS_SCR_SEVONPEND_LSB 4 +#define M0PLUS_SCR_SEVONPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SCR_SLEEPDEEP +// Description : Controls whether the processor uses sleep or deep sleep as its +// low power mode: +// 0 = Sleep. +// 1 = Deep sleep. +#define M0PLUS_SCR_SLEEPDEEP_RESET 0x0 +#define M0PLUS_SCR_SLEEPDEEP_BITS 0x00000004 +#define M0PLUS_SCR_SLEEPDEEP_MSB 2 +#define M0PLUS_SCR_SLEEPDEEP_LSB 2 +#define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SCR_SLEEPONEXIT +// Description : Indicates sleep-on-exit when returning from Handler mode to +// Thread mode: +// 0 = Do not sleep when returning to Thread mode. +// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread +// mode. +// Setting this bit to 1 enables an interrupt driven application +// to avoid returning to an empty main application. +#define M0PLUS_SCR_SLEEPONEXIT_RESET 0x0 +#define M0PLUS_SCR_SLEEPONEXIT_BITS 0x00000002 +#define M0PLUS_SCR_SLEEPONEXIT_MSB 1 +#define M0PLUS_SCR_SLEEPONEXIT_LSB 1 +#define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_CCR +// Description : The Configuration and Control Register permanently enables +// stack alignment and causes unaligned accesses to result in a +// Hard Fault. +#define M0PLUS_CCR_OFFSET 0x0000ed14 +#define M0PLUS_CCR_BITS 0x00000208 +#define M0PLUS_CCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CCR_STKALIGN +// Description : Always reads as one, indicates 8-byte stack alignment on +// exception entry. On exception entry, the processor uses bit[9] +// of the stacked PSR to indicate the stack alignment. On return +// from the exception it uses this stacked bit to restore the +// correct stack alignment. +#define M0PLUS_CCR_STKALIGN_RESET 0x0 +#define M0PLUS_CCR_STKALIGN_BITS 0x00000200 +#define M0PLUS_CCR_STKALIGN_MSB 9 +#define M0PLUS_CCR_STKALIGN_LSB 9 +#define M0PLUS_CCR_STKALIGN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_CCR_UNALIGN_TRP +// Description : Always reads as one, indicates that all unaligned accesses +// generate a HardFault. +#define M0PLUS_CCR_UNALIGN_TRP_RESET 0x0 +#define M0PLUS_CCR_UNALIGN_TRP_BITS 0x00000008 +#define M0PLUS_CCR_UNALIGN_TRP_MSB 3 +#define M0PLUS_CCR_UNALIGN_TRP_LSB 3 +#define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_SHPR2 +// Description : System handlers are a special class of exception handler that +// can have their priority set to any of the priority levels. Use +// the System Handler Priority Register 2 to set the priority of +// SVCall. +#define M0PLUS_SHPR2_OFFSET 0x0000ed1c +#define M0PLUS_SHPR2_BITS 0xc0000000 +#define M0PLUS_SHPR2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHPR2_PRI_11 +// Description : Priority of system handler 11, SVCall +#define M0PLUS_SHPR2_PRI_11_RESET 0x0 +#define M0PLUS_SHPR2_PRI_11_BITS 0xc0000000 +#define M0PLUS_SHPR2_PRI_11_MSB 31 +#define M0PLUS_SHPR2_PRI_11_LSB 30 +#define M0PLUS_SHPR2_PRI_11_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SHPR3 +// Description : System handlers are a special class of exception handler that +// can have their priority set to any of the priority levels. Use +// the System Handler Priority Register 3 to set the priority of +// PendSV and SysTick. +#define M0PLUS_SHPR3_OFFSET 0x0000ed20 +#define M0PLUS_SHPR3_BITS 0xc0c00000 +#define M0PLUS_SHPR3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHPR3_PRI_15 +// Description : Priority of system handler 15, SysTick +#define M0PLUS_SHPR3_PRI_15_RESET 0x0 +#define M0PLUS_SHPR3_PRI_15_BITS 0xc0000000 +#define M0PLUS_SHPR3_PRI_15_MSB 31 +#define M0PLUS_SHPR3_PRI_15_LSB 30 +#define M0PLUS_SHPR3_PRI_15_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHPR3_PRI_14 +// Description : Priority of system handler 14, PendSV +#define M0PLUS_SHPR3_PRI_14_RESET 0x0 +#define M0PLUS_SHPR3_PRI_14_BITS 0x00c00000 +#define M0PLUS_SHPR3_PRI_14_MSB 23 +#define M0PLUS_SHPR3_PRI_14_LSB 22 +#define M0PLUS_SHPR3_PRI_14_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_SHCSR +// Description : Use the System Handler Control and State Register to determine +// or clear the pending status of SVCall. +#define M0PLUS_SHCSR_OFFSET 0x0000ed24 +#define M0PLUS_SHCSR_BITS 0x00008000 +#define M0PLUS_SHCSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_SHCSR_SVCALLPENDED +// Description : Reads as 1 if SVCall is Pending. Write 1 to set pending +// SVCall, write 0 to clear pending SVCall. +#define M0PLUS_SHCSR_SVCALLPENDED_RESET 0x0 +#define M0PLUS_SHCSR_SVCALLPENDED_BITS 0x00008000 +#define M0PLUS_SHCSR_SVCALLPENDED_MSB 15 +#define M0PLUS_SHCSR_SVCALLPENDED_LSB 15 +#define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_TYPE +// Description : Read the MPU Type Register to determine if the processor +// implements an MPU, and how many regions the MPU supports. +#define M0PLUS_MPU_TYPE_OFFSET 0x0000ed90 +#define M0PLUS_MPU_TYPE_BITS 0x00ffff01 +#define M0PLUS_MPU_TYPE_RESET 0x00000800 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_TYPE_IREGION +// Description : Instruction region. Reads as zero as ARMv6-M only supports a +// unified MPU. +#define M0PLUS_MPU_TYPE_IREGION_RESET 0x00 +#define M0PLUS_MPU_TYPE_IREGION_BITS 0x00ff0000 +#define M0PLUS_MPU_TYPE_IREGION_MSB 23 +#define M0PLUS_MPU_TYPE_IREGION_LSB 16 +#define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_TYPE_DREGION +// Description : Number of regions supported by the MPU. +#define M0PLUS_MPU_TYPE_DREGION_RESET 0x08 +#define M0PLUS_MPU_TYPE_DREGION_BITS 0x0000ff00 +#define M0PLUS_MPU_TYPE_DREGION_MSB 15 +#define M0PLUS_MPU_TYPE_DREGION_LSB 8 +#define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_TYPE_SEPARATE +// Description : Indicates support for separate instruction and data address +// maps. Reads as 0 as ARMv6-M only supports a unified MPU. +#define M0PLUS_MPU_TYPE_SEPARATE_RESET 0x0 +#define M0PLUS_MPU_TYPE_SEPARATE_BITS 0x00000001 +#define M0PLUS_MPU_TYPE_SEPARATE_MSB 0 +#define M0PLUS_MPU_TYPE_SEPARATE_LSB 0 +#define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO" +// ============================================================================= +// Register : M0PLUS_MPU_CTRL +// Description : Use the MPU Control Register to enable and disable the MPU, and +// to control whether the default memory map is enabled as a +// background region for privileged accesses, and whether the MPU +// is enabled for HardFaults and NMIs. +#define M0PLUS_MPU_CTRL_OFFSET 0x0000ed94 +#define M0PLUS_MPU_CTRL_BITS 0x00000007 +#define M0PLUS_MPU_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_CTRL_PRIVDEFENA +// Description : Controls whether the default memory map is enabled as a +// background region for privileged accesses. This bit is ignored +// when ENABLE is clear. +// 0 = If the MPU is enabled, disables use of the default memory +// map. Any memory access to a location not +// covered by any enabled region causes a fault. +// 1 = If the MPU is enabled, enables use of the default memory +// map as a background region for privileged software accesses. +// When enabled, the background region acts as if it is region +// number -1. Any region that is defined and enabled has priority +// over this default map. +#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET 0x0 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS 0x00000004 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB 2 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB 2 +#define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_CTRL_HFNMIENA +// Description : Controls the use of the MPU for HardFaults and NMIs. Setting +// this bit when ENABLE is clear results in UNPREDICTABLE +// behaviour. +// When the MPU is enabled: +// 0 = MPU is disabled during HardFault and NMI handlers, +// regardless of the value of the ENABLE bit. +// 1 = the MPU is enabled during HardFault and NMI handlers. +#define M0PLUS_MPU_CTRL_HFNMIENA_RESET 0x0 +#define M0PLUS_MPU_CTRL_HFNMIENA_BITS 0x00000002 +#define M0PLUS_MPU_CTRL_HFNMIENA_MSB 1 +#define M0PLUS_MPU_CTRL_HFNMIENA_LSB 1 +#define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_CTRL_ENABLE +// Description : Enables the MPU. If the MPU is disabled, privileged and +// unprivileged accesses use the default memory map. +// 0 = MPU disabled. +// 1 = MPU enabled. +#define M0PLUS_MPU_CTRL_ENABLE_RESET 0x0 +#define M0PLUS_MPU_CTRL_ENABLE_BITS 0x00000001 +#define M0PLUS_MPU_CTRL_ENABLE_MSB 0 +#define M0PLUS_MPU_CTRL_ENABLE_LSB 0 +#define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_RNR +// Description : Use the MPU Region Number Register to select the region +// currently accessed by MPU_RBAR and MPU_RASR. +#define M0PLUS_MPU_RNR_OFFSET 0x0000ed98 +#define M0PLUS_MPU_RNR_BITS 0x0000000f +#define M0PLUS_MPU_RNR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RNR_REGION +// Description : Indicates the MPU region referenced by the MPU_RBAR and +// MPU_RASR registers. +// The MPU supports 8 memory regions, so the permitted values of +// this field are 0-7. +#define M0PLUS_MPU_RNR_REGION_RESET 0x0 +#define M0PLUS_MPU_RNR_REGION_BITS 0x0000000f +#define M0PLUS_MPU_RNR_REGION_MSB 3 +#define M0PLUS_MPU_RNR_REGION_LSB 0 +#define M0PLUS_MPU_RNR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_RBAR +// Description : Read the MPU Region Base Address Register to determine the base +// address of the region identified by MPU_RNR. Write to update +// the base address of said region or that of a specified region, +// with whose number MPU_RNR will also be updated. +#define M0PLUS_MPU_RBAR_OFFSET 0x0000ed9c +#define M0PLUS_MPU_RBAR_BITS 0xffffff1f +#define M0PLUS_MPU_RBAR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RBAR_ADDR +// Description : Base address of the region. +#define M0PLUS_MPU_RBAR_ADDR_RESET 0x000000 +#define M0PLUS_MPU_RBAR_ADDR_BITS 0xffffff00 +#define M0PLUS_MPU_RBAR_ADDR_MSB 31 +#define M0PLUS_MPU_RBAR_ADDR_LSB 8 +#define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RBAR_VALID +// Description : On writes, indicates whether the write must update the base +// address of the region identified by the REGION field, updating +// the MPU_RNR to indicate this new region. +// Write: +// 0 = MPU_RNR not changed, and the processor: +// Updates the base address for the region specified in the +// MPU_RNR. +// Ignores the value of the REGION field. +// 1 = The processor: +// Updates the value of the MPU_RNR to the value of the REGION +// field. +// Updates the base address for the region specified in the REGION +// field. +// Always reads as zero. +#define M0PLUS_MPU_RBAR_VALID_RESET 0x0 +#define M0PLUS_MPU_RBAR_VALID_BITS 0x00000010 +#define M0PLUS_MPU_RBAR_VALID_MSB 4 +#define M0PLUS_MPU_RBAR_VALID_LSB 4 +#define M0PLUS_MPU_RBAR_VALID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RBAR_REGION +// Description : On writes, specifies the number of the region whose base +// address to update provided VALID is set written as 1. On reads, +// returns bits [3:0] of MPU_RNR. +#define M0PLUS_MPU_RBAR_REGION_RESET 0x0 +#define M0PLUS_MPU_RBAR_REGION_BITS 0x0000000f +#define M0PLUS_MPU_RBAR_REGION_MSB 3 +#define M0PLUS_MPU_RBAR_REGION_LSB 0 +#define M0PLUS_MPU_RBAR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M0PLUS_MPU_RASR +// Description : Use the MPU Region Attribute and Size Register to define the +// size, access behaviour and memory type of the region identified +// by MPU_RNR, and enable that region. +#define M0PLUS_MPU_RASR_OFFSET 0x0000eda0 +#define M0PLUS_MPU_RASR_BITS 0xffffff3f +#define M0PLUS_MPU_RASR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_ATTRS +// Description : The MPU Region Attribute field. Use to define the region +// attribute control. +// 28 = XN: Instruction access disable bit: +// 0 = Instruction fetches enabled. +// 1 = Instruction fetches disabled. +// 26:24 = AP: Access permission field +// 18 = S: Shareable bit +// 17 = C: Cacheable bit +// 16 = B: Bufferable bit +#define M0PLUS_MPU_RASR_ATTRS_RESET 0x0000 +#define M0PLUS_MPU_RASR_ATTRS_BITS 0xffff0000 +#define M0PLUS_MPU_RASR_ATTRS_MSB 31 +#define M0PLUS_MPU_RASR_ATTRS_LSB 16 +#define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_SRD +// Description : Subregion Disable. For regions of 256 bytes or larger, each bit +// of this field controls whether one of the eight equal +// subregions is enabled. +#define M0PLUS_MPU_RASR_SRD_RESET 0x00 +#define M0PLUS_MPU_RASR_SRD_BITS 0x0000ff00 +#define M0PLUS_MPU_RASR_SRD_MSB 15 +#define M0PLUS_MPU_RASR_SRD_LSB 8 +#define M0PLUS_MPU_RASR_SRD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_SIZE +// Description : Indicates the region size. Region size in bytes = 2^(SIZE+1). +// The minimum permitted value is 7 (b00111) = 256Bytes +#define M0PLUS_MPU_RASR_SIZE_RESET 0x00 +#define M0PLUS_MPU_RASR_SIZE_BITS 0x0000003e +#define M0PLUS_MPU_RASR_SIZE_MSB 5 +#define M0PLUS_MPU_RASR_SIZE_LSB 1 +#define M0PLUS_MPU_RASR_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M0PLUS_MPU_RASR_ENABLE +// Description : Enables the region. +#define M0PLUS_MPU_RASR_ENABLE_RESET 0x0 +#define M0PLUS_MPU_RASR_ENABLE_BITS 0x00000001 +#define M0PLUS_MPU_RASR_ENABLE_MSB 0 +#define M0PLUS_MPU_RASR_ENABLE_LSB 0 +#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_M0PLUS_DEFINED diff --git a/rp2040/hardware/regs/pads_bank0.h b/rp2040/hardware/regs/pads_bank0.h new file mode 100644 index 0000000..92242bd --- /dev/null +++ b/rp2040/hardware/regs/pads_bank0.h @@ -0,0 +1,2300 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_BANK0 +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PADS_BANK0_DEFINED +#define HARDWARE_REGS_PADS_BANK0_DEFINED +// ============================================================================= +// Register : PADS_BANK0_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET 0x00000000 +#define PADS_BANK0_VOLTAGE_SELECT_BITS 0x00000001 +#define PADS_BANK0_VOLTAGE_SELECT_RESET 0x00000000 +#define PADS_BANK0_VOLTAGE_SELECT_MSB 0 +#define PADS_BANK0_VOLTAGE_SELECT_LSB 0 +#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 0x0 +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 0x1 +// ============================================================================= +// Register : PADS_BANK0_GPIO0 +// Description : Pad control register +#define PADS_BANK0_GPIO0_OFFSET 0x00000004 +#define PADS_BANK0_GPIO0_BITS 0x000000ff +#define PADS_BANK0_GPIO0_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO0_OD_RESET 0x0 +#define PADS_BANK0_GPIO0_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO0_OD_MSB 7 +#define PADS_BANK0_GPIO0_OD_LSB 7 +#define PADS_BANK0_GPIO0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_IE +// Description : Input enable +#define PADS_BANK0_GPIO0_IE_RESET 0x1 +#define PADS_BANK0_GPIO0_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO0_IE_MSB 6 +#define PADS_BANK0_GPIO0_IE_LSB 6 +#define PADS_BANK0_GPIO0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO0_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO0_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO0_DRIVE_MSB 5 +#define PADS_BANK0_GPIO0_DRIVE_LSB 4 +#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO0_PUE_RESET 0x0 +#define PADS_BANK0_GPIO0_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO0_PUE_MSB 3 +#define PADS_BANK0_GPIO0_PUE_LSB 3 +#define PADS_BANK0_GPIO0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO0_PDE_RESET 0x1 +#define PADS_BANK0_GPIO0_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO0_PDE_MSB 2 +#define PADS_BANK0_GPIO0_PDE_LSB 2 +#define PADS_BANK0_GPIO0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO0_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO0_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO0_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO0_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO0_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO0_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO0_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO0_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO1 +// Description : Pad control register +#define PADS_BANK0_GPIO1_OFFSET 0x00000008 +#define PADS_BANK0_GPIO1_BITS 0x000000ff +#define PADS_BANK0_GPIO1_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO1_OD_RESET 0x0 +#define PADS_BANK0_GPIO1_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO1_OD_MSB 7 +#define PADS_BANK0_GPIO1_OD_LSB 7 +#define PADS_BANK0_GPIO1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_IE +// Description : Input enable +#define PADS_BANK0_GPIO1_IE_RESET 0x1 +#define PADS_BANK0_GPIO1_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO1_IE_MSB 6 +#define PADS_BANK0_GPIO1_IE_LSB 6 +#define PADS_BANK0_GPIO1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO1_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO1_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO1_DRIVE_MSB 5 +#define PADS_BANK0_GPIO1_DRIVE_LSB 4 +#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO1_PUE_RESET 0x0 +#define PADS_BANK0_GPIO1_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO1_PUE_MSB 3 +#define PADS_BANK0_GPIO1_PUE_LSB 3 +#define PADS_BANK0_GPIO1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO1_PDE_RESET 0x1 +#define PADS_BANK0_GPIO1_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO1_PDE_MSB 2 +#define PADS_BANK0_GPIO1_PDE_LSB 2 +#define PADS_BANK0_GPIO1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO1_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO1_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO1_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO1_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO1_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO1_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO1_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO1_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO2 +// Description : Pad control register +#define PADS_BANK0_GPIO2_OFFSET 0x0000000c +#define PADS_BANK0_GPIO2_BITS 0x000000ff +#define PADS_BANK0_GPIO2_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO2_OD_RESET 0x0 +#define PADS_BANK0_GPIO2_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO2_OD_MSB 7 +#define PADS_BANK0_GPIO2_OD_LSB 7 +#define PADS_BANK0_GPIO2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_IE +// Description : Input enable +#define PADS_BANK0_GPIO2_IE_RESET 0x1 +#define PADS_BANK0_GPIO2_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO2_IE_MSB 6 +#define PADS_BANK0_GPIO2_IE_LSB 6 +#define PADS_BANK0_GPIO2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO2_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO2_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO2_DRIVE_MSB 5 +#define PADS_BANK0_GPIO2_DRIVE_LSB 4 +#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO2_PUE_RESET 0x0 +#define PADS_BANK0_GPIO2_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO2_PUE_MSB 3 +#define PADS_BANK0_GPIO2_PUE_LSB 3 +#define PADS_BANK0_GPIO2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO2_PDE_RESET 0x1 +#define PADS_BANK0_GPIO2_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO2_PDE_MSB 2 +#define PADS_BANK0_GPIO2_PDE_LSB 2 +#define PADS_BANK0_GPIO2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO2_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO2_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO2_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO2_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO2_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO2_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO2_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO2_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO3 +// Description : Pad control register +#define PADS_BANK0_GPIO3_OFFSET 0x00000010 +#define PADS_BANK0_GPIO3_BITS 0x000000ff +#define PADS_BANK0_GPIO3_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO3_OD_RESET 0x0 +#define PADS_BANK0_GPIO3_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO3_OD_MSB 7 +#define PADS_BANK0_GPIO3_OD_LSB 7 +#define PADS_BANK0_GPIO3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_IE +// Description : Input enable +#define PADS_BANK0_GPIO3_IE_RESET 0x1 +#define PADS_BANK0_GPIO3_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO3_IE_MSB 6 +#define PADS_BANK0_GPIO3_IE_LSB 6 +#define PADS_BANK0_GPIO3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO3_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO3_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO3_DRIVE_MSB 5 +#define PADS_BANK0_GPIO3_DRIVE_LSB 4 +#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO3_PUE_RESET 0x0 +#define PADS_BANK0_GPIO3_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO3_PUE_MSB 3 +#define PADS_BANK0_GPIO3_PUE_LSB 3 +#define PADS_BANK0_GPIO3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO3_PDE_RESET 0x1 +#define PADS_BANK0_GPIO3_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO3_PDE_MSB 2 +#define PADS_BANK0_GPIO3_PDE_LSB 2 +#define PADS_BANK0_GPIO3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO3_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO3_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO3_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO3_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO3_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO3_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO3_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO3_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO4 +// Description : Pad control register +#define PADS_BANK0_GPIO4_OFFSET 0x00000014 +#define PADS_BANK0_GPIO4_BITS 0x000000ff +#define PADS_BANK0_GPIO4_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO4_OD_RESET 0x0 +#define PADS_BANK0_GPIO4_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO4_OD_MSB 7 +#define PADS_BANK0_GPIO4_OD_LSB 7 +#define PADS_BANK0_GPIO4_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_IE +// Description : Input enable +#define PADS_BANK0_GPIO4_IE_RESET 0x1 +#define PADS_BANK0_GPIO4_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO4_IE_MSB 6 +#define PADS_BANK0_GPIO4_IE_LSB 6 +#define PADS_BANK0_GPIO4_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO4_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO4_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO4_DRIVE_MSB 5 +#define PADS_BANK0_GPIO4_DRIVE_LSB 4 +#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO4_PUE_RESET 0x0 +#define PADS_BANK0_GPIO4_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO4_PUE_MSB 3 +#define PADS_BANK0_GPIO4_PUE_LSB 3 +#define PADS_BANK0_GPIO4_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO4_PDE_RESET 0x1 +#define PADS_BANK0_GPIO4_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO4_PDE_MSB 2 +#define PADS_BANK0_GPIO4_PDE_LSB 2 +#define PADS_BANK0_GPIO4_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO4_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO4_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO4_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO4_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO4_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO4_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO4_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO4_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO5 +// Description : Pad control register +#define PADS_BANK0_GPIO5_OFFSET 0x00000018 +#define PADS_BANK0_GPIO5_BITS 0x000000ff +#define PADS_BANK0_GPIO5_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO5_OD_RESET 0x0 +#define PADS_BANK0_GPIO5_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO5_OD_MSB 7 +#define PADS_BANK0_GPIO5_OD_LSB 7 +#define PADS_BANK0_GPIO5_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_IE +// Description : Input enable +#define PADS_BANK0_GPIO5_IE_RESET 0x1 +#define PADS_BANK0_GPIO5_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO5_IE_MSB 6 +#define PADS_BANK0_GPIO5_IE_LSB 6 +#define PADS_BANK0_GPIO5_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO5_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO5_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO5_DRIVE_MSB 5 +#define PADS_BANK0_GPIO5_DRIVE_LSB 4 +#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO5_PUE_RESET 0x0 +#define PADS_BANK0_GPIO5_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO5_PUE_MSB 3 +#define PADS_BANK0_GPIO5_PUE_LSB 3 +#define PADS_BANK0_GPIO5_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO5_PDE_RESET 0x1 +#define PADS_BANK0_GPIO5_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO5_PDE_MSB 2 +#define PADS_BANK0_GPIO5_PDE_LSB 2 +#define PADS_BANK0_GPIO5_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO5_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO5_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO5_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO5_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO5_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO5_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO5_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO5_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO6 +// Description : Pad control register +#define PADS_BANK0_GPIO6_OFFSET 0x0000001c +#define PADS_BANK0_GPIO6_BITS 0x000000ff +#define PADS_BANK0_GPIO6_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO6_OD_RESET 0x0 +#define PADS_BANK0_GPIO6_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO6_OD_MSB 7 +#define PADS_BANK0_GPIO6_OD_LSB 7 +#define PADS_BANK0_GPIO6_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_IE +// Description : Input enable +#define PADS_BANK0_GPIO6_IE_RESET 0x1 +#define PADS_BANK0_GPIO6_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO6_IE_MSB 6 +#define PADS_BANK0_GPIO6_IE_LSB 6 +#define PADS_BANK0_GPIO6_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO6_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO6_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO6_DRIVE_MSB 5 +#define PADS_BANK0_GPIO6_DRIVE_LSB 4 +#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO6_PUE_RESET 0x0 +#define PADS_BANK0_GPIO6_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO6_PUE_MSB 3 +#define PADS_BANK0_GPIO6_PUE_LSB 3 +#define PADS_BANK0_GPIO6_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO6_PDE_RESET 0x1 +#define PADS_BANK0_GPIO6_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO6_PDE_MSB 2 +#define PADS_BANK0_GPIO6_PDE_LSB 2 +#define PADS_BANK0_GPIO6_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO6_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO6_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO6_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO6_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO6_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO6_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO6_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO6_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO7 +// Description : Pad control register +#define PADS_BANK0_GPIO7_OFFSET 0x00000020 +#define PADS_BANK0_GPIO7_BITS 0x000000ff +#define PADS_BANK0_GPIO7_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO7_OD_RESET 0x0 +#define PADS_BANK0_GPIO7_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO7_OD_MSB 7 +#define PADS_BANK0_GPIO7_OD_LSB 7 +#define PADS_BANK0_GPIO7_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_IE +// Description : Input enable +#define PADS_BANK0_GPIO7_IE_RESET 0x1 +#define PADS_BANK0_GPIO7_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO7_IE_MSB 6 +#define PADS_BANK0_GPIO7_IE_LSB 6 +#define PADS_BANK0_GPIO7_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO7_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO7_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO7_DRIVE_MSB 5 +#define PADS_BANK0_GPIO7_DRIVE_LSB 4 +#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO7_PUE_RESET 0x0 +#define PADS_BANK0_GPIO7_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO7_PUE_MSB 3 +#define PADS_BANK0_GPIO7_PUE_LSB 3 +#define PADS_BANK0_GPIO7_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO7_PDE_RESET 0x1 +#define PADS_BANK0_GPIO7_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO7_PDE_MSB 2 +#define PADS_BANK0_GPIO7_PDE_LSB 2 +#define PADS_BANK0_GPIO7_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO7_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO7_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO7_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO7_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO7_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO7_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO7_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO7_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO8 +// Description : Pad control register +#define PADS_BANK0_GPIO8_OFFSET 0x00000024 +#define PADS_BANK0_GPIO8_BITS 0x000000ff +#define PADS_BANK0_GPIO8_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO8_OD_RESET 0x0 +#define PADS_BANK0_GPIO8_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO8_OD_MSB 7 +#define PADS_BANK0_GPIO8_OD_LSB 7 +#define PADS_BANK0_GPIO8_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_IE +// Description : Input enable +#define PADS_BANK0_GPIO8_IE_RESET 0x1 +#define PADS_BANK0_GPIO8_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO8_IE_MSB 6 +#define PADS_BANK0_GPIO8_IE_LSB 6 +#define PADS_BANK0_GPIO8_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO8_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO8_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO8_DRIVE_MSB 5 +#define PADS_BANK0_GPIO8_DRIVE_LSB 4 +#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO8_PUE_RESET 0x0 +#define PADS_BANK0_GPIO8_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO8_PUE_MSB 3 +#define PADS_BANK0_GPIO8_PUE_LSB 3 +#define PADS_BANK0_GPIO8_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO8_PDE_RESET 0x1 +#define PADS_BANK0_GPIO8_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO8_PDE_MSB 2 +#define PADS_BANK0_GPIO8_PDE_LSB 2 +#define PADS_BANK0_GPIO8_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO8_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO8_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO8_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO8_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO8_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO8_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO8_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO8_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO9 +// Description : Pad control register +#define PADS_BANK0_GPIO9_OFFSET 0x00000028 +#define PADS_BANK0_GPIO9_BITS 0x000000ff +#define PADS_BANK0_GPIO9_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO9_OD_RESET 0x0 +#define PADS_BANK0_GPIO9_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO9_OD_MSB 7 +#define PADS_BANK0_GPIO9_OD_LSB 7 +#define PADS_BANK0_GPIO9_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_IE +// Description : Input enable +#define PADS_BANK0_GPIO9_IE_RESET 0x1 +#define PADS_BANK0_GPIO9_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO9_IE_MSB 6 +#define PADS_BANK0_GPIO9_IE_LSB 6 +#define PADS_BANK0_GPIO9_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO9_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO9_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO9_DRIVE_MSB 5 +#define PADS_BANK0_GPIO9_DRIVE_LSB 4 +#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO9_PUE_RESET 0x0 +#define PADS_BANK0_GPIO9_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO9_PUE_MSB 3 +#define PADS_BANK0_GPIO9_PUE_LSB 3 +#define PADS_BANK0_GPIO9_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO9_PDE_RESET 0x1 +#define PADS_BANK0_GPIO9_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO9_PDE_MSB 2 +#define PADS_BANK0_GPIO9_PDE_LSB 2 +#define PADS_BANK0_GPIO9_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO9_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO9_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO9_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO9_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO9_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO9_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO9_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO9_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO10 +// Description : Pad control register +#define PADS_BANK0_GPIO10_OFFSET 0x0000002c +#define PADS_BANK0_GPIO10_BITS 0x000000ff +#define PADS_BANK0_GPIO10_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO10_OD_RESET 0x0 +#define PADS_BANK0_GPIO10_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO10_OD_MSB 7 +#define PADS_BANK0_GPIO10_OD_LSB 7 +#define PADS_BANK0_GPIO10_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_IE +// Description : Input enable +#define PADS_BANK0_GPIO10_IE_RESET 0x1 +#define PADS_BANK0_GPIO10_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO10_IE_MSB 6 +#define PADS_BANK0_GPIO10_IE_LSB 6 +#define PADS_BANK0_GPIO10_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO10_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO10_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO10_DRIVE_MSB 5 +#define PADS_BANK0_GPIO10_DRIVE_LSB 4 +#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO10_PUE_RESET 0x0 +#define PADS_BANK0_GPIO10_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO10_PUE_MSB 3 +#define PADS_BANK0_GPIO10_PUE_LSB 3 +#define PADS_BANK0_GPIO10_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO10_PDE_RESET 0x1 +#define PADS_BANK0_GPIO10_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO10_PDE_MSB 2 +#define PADS_BANK0_GPIO10_PDE_LSB 2 +#define PADS_BANK0_GPIO10_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO10_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO10_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO10_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO10_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO10_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO10_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO10_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO10_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO11 +// Description : Pad control register +#define PADS_BANK0_GPIO11_OFFSET 0x00000030 +#define PADS_BANK0_GPIO11_BITS 0x000000ff +#define PADS_BANK0_GPIO11_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO11_OD_RESET 0x0 +#define PADS_BANK0_GPIO11_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO11_OD_MSB 7 +#define PADS_BANK0_GPIO11_OD_LSB 7 +#define PADS_BANK0_GPIO11_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_IE +// Description : Input enable +#define PADS_BANK0_GPIO11_IE_RESET 0x1 +#define PADS_BANK0_GPIO11_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO11_IE_MSB 6 +#define PADS_BANK0_GPIO11_IE_LSB 6 +#define PADS_BANK0_GPIO11_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO11_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO11_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO11_DRIVE_MSB 5 +#define PADS_BANK0_GPIO11_DRIVE_LSB 4 +#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO11_PUE_RESET 0x0 +#define PADS_BANK0_GPIO11_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO11_PUE_MSB 3 +#define PADS_BANK0_GPIO11_PUE_LSB 3 +#define PADS_BANK0_GPIO11_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO11_PDE_RESET 0x1 +#define PADS_BANK0_GPIO11_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO11_PDE_MSB 2 +#define PADS_BANK0_GPIO11_PDE_LSB 2 +#define PADS_BANK0_GPIO11_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO11_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO11_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO11_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO11_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO11_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO11_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO11_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO11_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO12 +// Description : Pad control register +#define PADS_BANK0_GPIO12_OFFSET 0x00000034 +#define PADS_BANK0_GPIO12_BITS 0x000000ff +#define PADS_BANK0_GPIO12_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO12_OD_RESET 0x0 +#define PADS_BANK0_GPIO12_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO12_OD_MSB 7 +#define PADS_BANK0_GPIO12_OD_LSB 7 +#define PADS_BANK0_GPIO12_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_IE +// Description : Input enable +#define PADS_BANK0_GPIO12_IE_RESET 0x1 +#define PADS_BANK0_GPIO12_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO12_IE_MSB 6 +#define PADS_BANK0_GPIO12_IE_LSB 6 +#define PADS_BANK0_GPIO12_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO12_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO12_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO12_DRIVE_MSB 5 +#define PADS_BANK0_GPIO12_DRIVE_LSB 4 +#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO12_PUE_RESET 0x0 +#define PADS_BANK0_GPIO12_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO12_PUE_MSB 3 +#define PADS_BANK0_GPIO12_PUE_LSB 3 +#define PADS_BANK0_GPIO12_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO12_PDE_RESET 0x1 +#define PADS_BANK0_GPIO12_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO12_PDE_MSB 2 +#define PADS_BANK0_GPIO12_PDE_LSB 2 +#define PADS_BANK0_GPIO12_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO12_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO12_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO12_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO12_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO12_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO12_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO12_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO12_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO13 +// Description : Pad control register +#define PADS_BANK0_GPIO13_OFFSET 0x00000038 +#define PADS_BANK0_GPIO13_BITS 0x000000ff +#define PADS_BANK0_GPIO13_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO13_OD_RESET 0x0 +#define PADS_BANK0_GPIO13_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO13_OD_MSB 7 +#define PADS_BANK0_GPIO13_OD_LSB 7 +#define PADS_BANK0_GPIO13_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_IE +// Description : Input enable +#define PADS_BANK0_GPIO13_IE_RESET 0x1 +#define PADS_BANK0_GPIO13_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO13_IE_MSB 6 +#define PADS_BANK0_GPIO13_IE_LSB 6 +#define PADS_BANK0_GPIO13_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO13_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO13_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO13_DRIVE_MSB 5 +#define PADS_BANK0_GPIO13_DRIVE_LSB 4 +#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO13_PUE_RESET 0x0 +#define PADS_BANK0_GPIO13_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO13_PUE_MSB 3 +#define PADS_BANK0_GPIO13_PUE_LSB 3 +#define PADS_BANK0_GPIO13_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO13_PDE_RESET 0x1 +#define PADS_BANK0_GPIO13_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO13_PDE_MSB 2 +#define PADS_BANK0_GPIO13_PDE_LSB 2 +#define PADS_BANK0_GPIO13_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO13_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO13_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO13_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO13_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO13_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO13_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO13_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO13_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO14 +// Description : Pad control register +#define PADS_BANK0_GPIO14_OFFSET 0x0000003c +#define PADS_BANK0_GPIO14_BITS 0x000000ff +#define PADS_BANK0_GPIO14_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO14_OD_RESET 0x0 +#define PADS_BANK0_GPIO14_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO14_OD_MSB 7 +#define PADS_BANK0_GPIO14_OD_LSB 7 +#define PADS_BANK0_GPIO14_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_IE +// Description : Input enable +#define PADS_BANK0_GPIO14_IE_RESET 0x1 +#define PADS_BANK0_GPIO14_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO14_IE_MSB 6 +#define PADS_BANK0_GPIO14_IE_LSB 6 +#define PADS_BANK0_GPIO14_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO14_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO14_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO14_DRIVE_MSB 5 +#define PADS_BANK0_GPIO14_DRIVE_LSB 4 +#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO14_PUE_RESET 0x0 +#define PADS_BANK0_GPIO14_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO14_PUE_MSB 3 +#define PADS_BANK0_GPIO14_PUE_LSB 3 +#define PADS_BANK0_GPIO14_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO14_PDE_RESET 0x1 +#define PADS_BANK0_GPIO14_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO14_PDE_MSB 2 +#define PADS_BANK0_GPIO14_PDE_LSB 2 +#define PADS_BANK0_GPIO14_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO14_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO14_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO14_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO14_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO14_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO14_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO14_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO14_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO15 +// Description : Pad control register +#define PADS_BANK0_GPIO15_OFFSET 0x00000040 +#define PADS_BANK0_GPIO15_BITS 0x000000ff +#define PADS_BANK0_GPIO15_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO15_OD_RESET 0x0 +#define PADS_BANK0_GPIO15_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO15_OD_MSB 7 +#define PADS_BANK0_GPIO15_OD_LSB 7 +#define PADS_BANK0_GPIO15_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_IE +// Description : Input enable +#define PADS_BANK0_GPIO15_IE_RESET 0x1 +#define PADS_BANK0_GPIO15_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO15_IE_MSB 6 +#define PADS_BANK0_GPIO15_IE_LSB 6 +#define PADS_BANK0_GPIO15_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO15_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO15_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO15_DRIVE_MSB 5 +#define PADS_BANK0_GPIO15_DRIVE_LSB 4 +#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO15_PUE_RESET 0x0 +#define PADS_BANK0_GPIO15_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO15_PUE_MSB 3 +#define PADS_BANK0_GPIO15_PUE_LSB 3 +#define PADS_BANK0_GPIO15_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO15_PDE_RESET 0x1 +#define PADS_BANK0_GPIO15_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO15_PDE_MSB 2 +#define PADS_BANK0_GPIO15_PDE_LSB 2 +#define PADS_BANK0_GPIO15_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO15_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO15_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO15_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO15_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO15_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO15_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO15_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO15_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO16 +// Description : Pad control register +#define PADS_BANK0_GPIO16_OFFSET 0x00000044 +#define PADS_BANK0_GPIO16_BITS 0x000000ff +#define PADS_BANK0_GPIO16_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO16_OD_RESET 0x0 +#define PADS_BANK0_GPIO16_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO16_OD_MSB 7 +#define PADS_BANK0_GPIO16_OD_LSB 7 +#define PADS_BANK0_GPIO16_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_IE +// Description : Input enable +#define PADS_BANK0_GPIO16_IE_RESET 0x1 +#define PADS_BANK0_GPIO16_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO16_IE_MSB 6 +#define PADS_BANK0_GPIO16_IE_LSB 6 +#define PADS_BANK0_GPIO16_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO16_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO16_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO16_DRIVE_MSB 5 +#define PADS_BANK0_GPIO16_DRIVE_LSB 4 +#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO16_PUE_RESET 0x0 +#define PADS_BANK0_GPIO16_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO16_PUE_MSB 3 +#define PADS_BANK0_GPIO16_PUE_LSB 3 +#define PADS_BANK0_GPIO16_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO16_PDE_RESET 0x1 +#define PADS_BANK0_GPIO16_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO16_PDE_MSB 2 +#define PADS_BANK0_GPIO16_PDE_LSB 2 +#define PADS_BANK0_GPIO16_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO16_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO16_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO16_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO16_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO16_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO16_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO16_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO16_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO17 +// Description : Pad control register +#define PADS_BANK0_GPIO17_OFFSET 0x00000048 +#define PADS_BANK0_GPIO17_BITS 0x000000ff +#define PADS_BANK0_GPIO17_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO17_OD_RESET 0x0 +#define PADS_BANK0_GPIO17_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO17_OD_MSB 7 +#define PADS_BANK0_GPIO17_OD_LSB 7 +#define PADS_BANK0_GPIO17_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_IE +// Description : Input enable +#define PADS_BANK0_GPIO17_IE_RESET 0x1 +#define PADS_BANK0_GPIO17_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO17_IE_MSB 6 +#define PADS_BANK0_GPIO17_IE_LSB 6 +#define PADS_BANK0_GPIO17_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO17_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO17_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO17_DRIVE_MSB 5 +#define PADS_BANK0_GPIO17_DRIVE_LSB 4 +#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO17_PUE_RESET 0x0 +#define PADS_BANK0_GPIO17_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO17_PUE_MSB 3 +#define PADS_BANK0_GPIO17_PUE_LSB 3 +#define PADS_BANK0_GPIO17_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO17_PDE_RESET 0x1 +#define PADS_BANK0_GPIO17_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO17_PDE_MSB 2 +#define PADS_BANK0_GPIO17_PDE_LSB 2 +#define PADS_BANK0_GPIO17_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO17_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO17_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO17_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO17_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO17_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO17_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO17_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO17_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO18 +// Description : Pad control register +#define PADS_BANK0_GPIO18_OFFSET 0x0000004c +#define PADS_BANK0_GPIO18_BITS 0x000000ff +#define PADS_BANK0_GPIO18_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO18_OD_RESET 0x0 +#define PADS_BANK0_GPIO18_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO18_OD_MSB 7 +#define PADS_BANK0_GPIO18_OD_LSB 7 +#define PADS_BANK0_GPIO18_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_IE +// Description : Input enable +#define PADS_BANK0_GPIO18_IE_RESET 0x1 +#define PADS_BANK0_GPIO18_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO18_IE_MSB 6 +#define PADS_BANK0_GPIO18_IE_LSB 6 +#define PADS_BANK0_GPIO18_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO18_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO18_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO18_DRIVE_MSB 5 +#define PADS_BANK0_GPIO18_DRIVE_LSB 4 +#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO18_PUE_RESET 0x0 +#define PADS_BANK0_GPIO18_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO18_PUE_MSB 3 +#define PADS_BANK0_GPIO18_PUE_LSB 3 +#define PADS_BANK0_GPIO18_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO18_PDE_RESET 0x1 +#define PADS_BANK0_GPIO18_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO18_PDE_MSB 2 +#define PADS_BANK0_GPIO18_PDE_LSB 2 +#define PADS_BANK0_GPIO18_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO18_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO18_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO18_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO18_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO18_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO18_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO18_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO18_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO19 +// Description : Pad control register +#define PADS_BANK0_GPIO19_OFFSET 0x00000050 +#define PADS_BANK0_GPIO19_BITS 0x000000ff +#define PADS_BANK0_GPIO19_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO19_OD_RESET 0x0 +#define PADS_BANK0_GPIO19_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO19_OD_MSB 7 +#define PADS_BANK0_GPIO19_OD_LSB 7 +#define PADS_BANK0_GPIO19_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_IE +// Description : Input enable +#define PADS_BANK0_GPIO19_IE_RESET 0x1 +#define PADS_BANK0_GPIO19_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO19_IE_MSB 6 +#define PADS_BANK0_GPIO19_IE_LSB 6 +#define PADS_BANK0_GPIO19_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO19_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO19_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO19_DRIVE_MSB 5 +#define PADS_BANK0_GPIO19_DRIVE_LSB 4 +#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO19_PUE_RESET 0x0 +#define PADS_BANK0_GPIO19_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO19_PUE_MSB 3 +#define PADS_BANK0_GPIO19_PUE_LSB 3 +#define PADS_BANK0_GPIO19_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO19_PDE_RESET 0x1 +#define PADS_BANK0_GPIO19_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO19_PDE_MSB 2 +#define PADS_BANK0_GPIO19_PDE_LSB 2 +#define PADS_BANK0_GPIO19_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO19_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO19_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO19_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO19_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO19_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO19_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO19_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO19_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO20 +// Description : Pad control register +#define PADS_BANK0_GPIO20_OFFSET 0x00000054 +#define PADS_BANK0_GPIO20_BITS 0x000000ff +#define PADS_BANK0_GPIO20_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO20_OD_RESET 0x0 +#define PADS_BANK0_GPIO20_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO20_OD_MSB 7 +#define PADS_BANK0_GPIO20_OD_LSB 7 +#define PADS_BANK0_GPIO20_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_IE +// Description : Input enable +#define PADS_BANK0_GPIO20_IE_RESET 0x1 +#define PADS_BANK0_GPIO20_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO20_IE_MSB 6 +#define PADS_BANK0_GPIO20_IE_LSB 6 +#define PADS_BANK0_GPIO20_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO20_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO20_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO20_DRIVE_MSB 5 +#define PADS_BANK0_GPIO20_DRIVE_LSB 4 +#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO20_PUE_RESET 0x0 +#define PADS_BANK0_GPIO20_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO20_PUE_MSB 3 +#define PADS_BANK0_GPIO20_PUE_LSB 3 +#define PADS_BANK0_GPIO20_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO20_PDE_RESET 0x1 +#define PADS_BANK0_GPIO20_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO20_PDE_MSB 2 +#define PADS_BANK0_GPIO20_PDE_LSB 2 +#define PADS_BANK0_GPIO20_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO20_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO20_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO20_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO20_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO20_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO20_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO20_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO20_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO21 +// Description : Pad control register +#define PADS_BANK0_GPIO21_OFFSET 0x00000058 +#define PADS_BANK0_GPIO21_BITS 0x000000ff +#define PADS_BANK0_GPIO21_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO21_OD_RESET 0x0 +#define PADS_BANK0_GPIO21_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO21_OD_MSB 7 +#define PADS_BANK0_GPIO21_OD_LSB 7 +#define PADS_BANK0_GPIO21_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_IE +// Description : Input enable +#define PADS_BANK0_GPIO21_IE_RESET 0x1 +#define PADS_BANK0_GPIO21_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO21_IE_MSB 6 +#define PADS_BANK0_GPIO21_IE_LSB 6 +#define PADS_BANK0_GPIO21_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO21_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO21_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO21_DRIVE_MSB 5 +#define PADS_BANK0_GPIO21_DRIVE_LSB 4 +#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO21_PUE_RESET 0x0 +#define PADS_BANK0_GPIO21_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO21_PUE_MSB 3 +#define PADS_BANK0_GPIO21_PUE_LSB 3 +#define PADS_BANK0_GPIO21_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO21_PDE_RESET 0x1 +#define PADS_BANK0_GPIO21_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO21_PDE_MSB 2 +#define PADS_BANK0_GPIO21_PDE_LSB 2 +#define PADS_BANK0_GPIO21_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO21_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO21_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO21_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO21_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO21_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO21_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO21_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO21_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO22 +// Description : Pad control register +#define PADS_BANK0_GPIO22_OFFSET 0x0000005c +#define PADS_BANK0_GPIO22_BITS 0x000000ff +#define PADS_BANK0_GPIO22_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO22_OD_RESET 0x0 +#define PADS_BANK0_GPIO22_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO22_OD_MSB 7 +#define PADS_BANK0_GPIO22_OD_LSB 7 +#define PADS_BANK0_GPIO22_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_IE +// Description : Input enable +#define PADS_BANK0_GPIO22_IE_RESET 0x1 +#define PADS_BANK0_GPIO22_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO22_IE_MSB 6 +#define PADS_BANK0_GPIO22_IE_LSB 6 +#define PADS_BANK0_GPIO22_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO22_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO22_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO22_DRIVE_MSB 5 +#define PADS_BANK0_GPIO22_DRIVE_LSB 4 +#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO22_PUE_RESET 0x0 +#define PADS_BANK0_GPIO22_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO22_PUE_MSB 3 +#define PADS_BANK0_GPIO22_PUE_LSB 3 +#define PADS_BANK0_GPIO22_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO22_PDE_RESET 0x1 +#define PADS_BANK0_GPIO22_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO22_PDE_MSB 2 +#define PADS_BANK0_GPIO22_PDE_LSB 2 +#define PADS_BANK0_GPIO22_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO22_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO22_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO22_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO22_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO22_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO22_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO22_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO22_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO23 +// Description : Pad control register +#define PADS_BANK0_GPIO23_OFFSET 0x00000060 +#define PADS_BANK0_GPIO23_BITS 0x000000ff +#define PADS_BANK0_GPIO23_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO23_OD_RESET 0x0 +#define PADS_BANK0_GPIO23_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO23_OD_MSB 7 +#define PADS_BANK0_GPIO23_OD_LSB 7 +#define PADS_BANK0_GPIO23_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_IE +// Description : Input enable +#define PADS_BANK0_GPIO23_IE_RESET 0x1 +#define PADS_BANK0_GPIO23_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO23_IE_MSB 6 +#define PADS_BANK0_GPIO23_IE_LSB 6 +#define PADS_BANK0_GPIO23_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO23_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO23_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO23_DRIVE_MSB 5 +#define PADS_BANK0_GPIO23_DRIVE_LSB 4 +#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO23_PUE_RESET 0x0 +#define PADS_BANK0_GPIO23_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO23_PUE_MSB 3 +#define PADS_BANK0_GPIO23_PUE_LSB 3 +#define PADS_BANK0_GPIO23_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO23_PDE_RESET 0x1 +#define PADS_BANK0_GPIO23_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO23_PDE_MSB 2 +#define PADS_BANK0_GPIO23_PDE_LSB 2 +#define PADS_BANK0_GPIO23_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO23_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO23_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO23_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO23_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO23_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO23_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO23_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO23_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO24 +// Description : Pad control register +#define PADS_BANK0_GPIO24_OFFSET 0x00000064 +#define PADS_BANK0_GPIO24_BITS 0x000000ff +#define PADS_BANK0_GPIO24_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO24_OD_RESET 0x0 +#define PADS_BANK0_GPIO24_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO24_OD_MSB 7 +#define PADS_BANK0_GPIO24_OD_LSB 7 +#define PADS_BANK0_GPIO24_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_IE +// Description : Input enable +#define PADS_BANK0_GPIO24_IE_RESET 0x1 +#define PADS_BANK0_GPIO24_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO24_IE_MSB 6 +#define PADS_BANK0_GPIO24_IE_LSB 6 +#define PADS_BANK0_GPIO24_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO24_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO24_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO24_DRIVE_MSB 5 +#define PADS_BANK0_GPIO24_DRIVE_LSB 4 +#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO24_PUE_RESET 0x0 +#define PADS_BANK0_GPIO24_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO24_PUE_MSB 3 +#define PADS_BANK0_GPIO24_PUE_LSB 3 +#define PADS_BANK0_GPIO24_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO24_PDE_RESET 0x1 +#define PADS_BANK0_GPIO24_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO24_PDE_MSB 2 +#define PADS_BANK0_GPIO24_PDE_LSB 2 +#define PADS_BANK0_GPIO24_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO24_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO24_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO24_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO24_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO24_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO24_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO24_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO24_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO25 +// Description : Pad control register +#define PADS_BANK0_GPIO25_OFFSET 0x00000068 +#define PADS_BANK0_GPIO25_BITS 0x000000ff +#define PADS_BANK0_GPIO25_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO25_OD_RESET 0x0 +#define PADS_BANK0_GPIO25_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO25_OD_MSB 7 +#define PADS_BANK0_GPIO25_OD_LSB 7 +#define PADS_BANK0_GPIO25_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_IE +// Description : Input enable +#define PADS_BANK0_GPIO25_IE_RESET 0x1 +#define PADS_BANK0_GPIO25_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO25_IE_MSB 6 +#define PADS_BANK0_GPIO25_IE_LSB 6 +#define PADS_BANK0_GPIO25_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO25_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO25_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO25_DRIVE_MSB 5 +#define PADS_BANK0_GPIO25_DRIVE_LSB 4 +#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO25_PUE_RESET 0x0 +#define PADS_BANK0_GPIO25_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO25_PUE_MSB 3 +#define PADS_BANK0_GPIO25_PUE_LSB 3 +#define PADS_BANK0_GPIO25_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO25_PDE_RESET 0x1 +#define PADS_BANK0_GPIO25_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO25_PDE_MSB 2 +#define PADS_BANK0_GPIO25_PDE_LSB 2 +#define PADS_BANK0_GPIO25_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO25_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO25_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO25_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO25_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO25_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO25_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO25_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO25_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO26 +// Description : Pad control register +#define PADS_BANK0_GPIO26_OFFSET 0x0000006c +#define PADS_BANK0_GPIO26_BITS 0x000000ff +#define PADS_BANK0_GPIO26_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO26_OD_RESET 0x0 +#define PADS_BANK0_GPIO26_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO26_OD_MSB 7 +#define PADS_BANK0_GPIO26_OD_LSB 7 +#define PADS_BANK0_GPIO26_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_IE +// Description : Input enable +#define PADS_BANK0_GPIO26_IE_RESET 0x1 +#define PADS_BANK0_GPIO26_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO26_IE_MSB 6 +#define PADS_BANK0_GPIO26_IE_LSB 6 +#define PADS_BANK0_GPIO26_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO26_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO26_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO26_DRIVE_MSB 5 +#define PADS_BANK0_GPIO26_DRIVE_LSB 4 +#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO26_PUE_RESET 0x0 +#define PADS_BANK0_GPIO26_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO26_PUE_MSB 3 +#define PADS_BANK0_GPIO26_PUE_LSB 3 +#define PADS_BANK0_GPIO26_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO26_PDE_RESET 0x1 +#define PADS_BANK0_GPIO26_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO26_PDE_MSB 2 +#define PADS_BANK0_GPIO26_PDE_LSB 2 +#define PADS_BANK0_GPIO26_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO26_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO26_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO26_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO26_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO26_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO26_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO26_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO26_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO27 +// Description : Pad control register +#define PADS_BANK0_GPIO27_OFFSET 0x00000070 +#define PADS_BANK0_GPIO27_BITS 0x000000ff +#define PADS_BANK0_GPIO27_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO27_OD_RESET 0x0 +#define PADS_BANK0_GPIO27_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO27_OD_MSB 7 +#define PADS_BANK0_GPIO27_OD_LSB 7 +#define PADS_BANK0_GPIO27_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_IE +// Description : Input enable +#define PADS_BANK0_GPIO27_IE_RESET 0x1 +#define PADS_BANK0_GPIO27_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO27_IE_MSB 6 +#define PADS_BANK0_GPIO27_IE_LSB 6 +#define PADS_BANK0_GPIO27_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO27_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO27_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO27_DRIVE_MSB 5 +#define PADS_BANK0_GPIO27_DRIVE_LSB 4 +#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO27_PUE_RESET 0x0 +#define PADS_BANK0_GPIO27_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO27_PUE_MSB 3 +#define PADS_BANK0_GPIO27_PUE_LSB 3 +#define PADS_BANK0_GPIO27_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO27_PDE_RESET 0x1 +#define PADS_BANK0_GPIO27_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO27_PDE_MSB 2 +#define PADS_BANK0_GPIO27_PDE_LSB 2 +#define PADS_BANK0_GPIO27_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO27_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO27_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO27_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO27_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO27_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO27_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO27_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO27_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO28 +// Description : Pad control register +#define PADS_BANK0_GPIO28_OFFSET 0x00000074 +#define PADS_BANK0_GPIO28_BITS 0x000000ff +#define PADS_BANK0_GPIO28_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO28_OD_RESET 0x0 +#define PADS_BANK0_GPIO28_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO28_OD_MSB 7 +#define PADS_BANK0_GPIO28_OD_LSB 7 +#define PADS_BANK0_GPIO28_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_IE +// Description : Input enable +#define PADS_BANK0_GPIO28_IE_RESET 0x1 +#define PADS_BANK0_GPIO28_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO28_IE_MSB 6 +#define PADS_BANK0_GPIO28_IE_LSB 6 +#define PADS_BANK0_GPIO28_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO28_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO28_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO28_DRIVE_MSB 5 +#define PADS_BANK0_GPIO28_DRIVE_LSB 4 +#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO28_PUE_RESET 0x0 +#define PADS_BANK0_GPIO28_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO28_PUE_MSB 3 +#define PADS_BANK0_GPIO28_PUE_LSB 3 +#define PADS_BANK0_GPIO28_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO28_PDE_RESET 0x1 +#define PADS_BANK0_GPIO28_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO28_PDE_MSB 2 +#define PADS_BANK0_GPIO28_PDE_LSB 2 +#define PADS_BANK0_GPIO28_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO28_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO28_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO28_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO28_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO28_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO28_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO28_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO28_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO29 +// Description : Pad control register +#define PADS_BANK0_GPIO29_OFFSET 0x00000078 +#define PADS_BANK0_GPIO29_BITS 0x000000ff +#define PADS_BANK0_GPIO29_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO29_OD_RESET 0x0 +#define PADS_BANK0_GPIO29_OD_BITS 0x00000080 +#define PADS_BANK0_GPIO29_OD_MSB 7 +#define PADS_BANK0_GPIO29_OD_LSB 7 +#define PADS_BANK0_GPIO29_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_IE +// Description : Input enable +#define PADS_BANK0_GPIO29_IE_RESET 0x1 +#define PADS_BANK0_GPIO29_IE_BITS 0x00000040 +#define PADS_BANK0_GPIO29_IE_MSB 6 +#define PADS_BANK0_GPIO29_IE_LSB 6 +#define PADS_BANK0_GPIO29_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO29_DRIVE_RESET 0x1 +#define PADS_BANK0_GPIO29_DRIVE_BITS 0x00000030 +#define PADS_BANK0_GPIO29_DRIVE_MSB 5 +#define PADS_BANK0_GPIO29_DRIVE_LSB 4 +#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO29_PUE_RESET 0x0 +#define PADS_BANK0_GPIO29_PUE_BITS 0x00000008 +#define PADS_BANK0_GPIO29_PUE_MSB 3 +#define PADS_BANK0_GPIO29_PUE_LSB 3 +#define PADS_BANK0_GPIO29_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO29_PDE_RESET 0x1 +#define PADS_BANK0_GPIO29_PDE_BITS 0x00000004 +#define PADS_BANK0_GPIO29_PDE_MSB 2 +#define PADS_BANK0_GPIO29_PDE_LSB 2 +#define PADS_BANK0_GPIO29_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO29_SCHMITT_RESET 0x1 +#define PADS_BANK0_GPIO29_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_GPIO29_SCHMITT_MSB 1 +#define PADS_BANK0_GPIO29_SCHMITT_LSB 1 +#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO29_SLEWFAST_RESET 0x0 +#define PADS_BANK0_GPIO29_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_GPIO29_SLEWFAST_MSB 0 +#define PADS_BANK0_GPIO29_SLEWFAST_LSB 0 +#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWCLK +// Description : Pad control register +#define PADS_BANK0_SWCLK_OFFSET 0x0000007c +#define PADS_BANK0_SWCLK_BITS 0x000000ff +#define PADS_BANK0_SWCLK_RESET 0x000000da +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWCLK_OD_RESET 0x1 +#define PADS_BANK0_SWCLK_OD_BITS 0x00000080 +#define PADS_BANK0_SWCLK_OD_MSB 7 +#define PADS_BANK0_SWCLK_OD_LSB 7 +#define PADS_BANK0_SWCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_IE +// Description : Input enable +#define PADS_BANK0_SWCLK_IE_RESET 0x1 +#define PADS_BANK0_SWCLK_IE_BITS 0x00000040 +#define PADS_BANK0_SWCLK_IE_MSB 6 +#define PADS_BANK0_SWCLK_IE_LSB 6 +#define PADS_BANK0_SWCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWCLK_DRIVE_RESET 0x1 +#define PADS_BANK0_SWCLK_DRIVE_BITS 0x00000030 +#define PADS_BANK0_SWCLK_DRIVE_MSB 5 +#define PADS_BANK0_SWCLK_DRIVE_LSB 4 +#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PUE +// Description : Pull up enable +#define PADS_BANK0_SWCLK_PUE_RESET 0x1 +#define PADS_BANK0_SWCLK_PUE_BITS 0x00000008 +#define PADS_BANK0_SWCLK_PUE_MSB 3 +#define PADS_BANK0_SWCLK_PUE_LSB 3 +#define PADS_BANK0_SWCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PDE +// Description : Pull down enable +#define PADS_BANK0_SWCLK_PDE_RESET 0x0 +#define PADS_BANK0_SWCLK_PDE_BITS 0x00000004 +#define PADS_BANK0_SWCLK_PDE_MSB 2 +#define PADS_BANK0_SWCLK_PDE_LSB 2 +#define PADS_BANK0_SWCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWCLK_SCHMITT_RESET 0x1 +#define PADS_BANK0_SWCLK_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_SWCLK_SCHMITT_MSB 1 +#define PADS_BANK0_SWCLK_SCHMITT_LSB 1 +#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWCLK_SLEWFAST_RESET 0x0 +#define PADS_BANK0_SWCLK_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_SWCLK_SLEWFAST_MSB 0 +#define PADS_BANK0_SWCLK_SLEWFAST_LSB 0 +#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWD +// Description : Pad control register +#define PADS_BANK0_SWD_OFFSET 0x00000080 +#define PADS_BANK0_SWD_BITS 0x000000ff +#define PADS_BANK0_SWD_RESET 0x0000005a +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWD_OD_RESET 0x0 +#define PADS_BANK0_SWD_OD_BITS 0x00000080 +#define PADS_BANK0_SWD_OD_MSB 7 +#define PADS_BANK0_SWD_OD_LSB 7 +#define PADS_BANK0_SWD_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_IE +// Description : Input enable +#define PADS_BANK0_SWD_IE_RESET 0x1 +#define PADS_BANK0_SWD_IE_BITS 0x00000040 +#define PADS_BANK0_SWD_IE_MSB 6 +#define PADS_BANK0_SWD_IE_LSB 6 +#define PADS_BANK0_SWD_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWD_DRIVE_RESET 0x1 +#define PADS_BANK0_SWD_DRIVE_BITS 0x00000030 +#define PADS_BANK0_SWD_DRIVE_MSB 5 +#define PADS_BANK0_SWD_DRIVE_LSB 4 +#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA 0x0 +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA 0x1 +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA 0x2 +#define PADS_BANK0_SWD_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PUE +// Description : Pull up enable +#define PADS_BANK0_SWD_PUE_RESET 0x1 +#define PADS_BANK0_SWD_PUE_BITS 0x00000008 +#define PADS_BANK0_SWD_PUE_MSB 3 +#define PADS_BANK0_SWD_PUE_LSB 3 +#define PADS_BANK0_SWD_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PDE +// Description : Pull down enable +#define PADS_BANK0_SWD_PDE_RESET 0x0 +#define PADS_BANK0_SWD_PDE_BITS 0x00000004 +#define PADS_BANK0_SWD_PDE_MSB 2 +#define PADS_BANK0_SWD_PDE_LSB 2 +#define PADS_BANK0_SWD_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWD_SCHMITT_RESET 0x1 +#define PADS_BANK0_SWD_SCHMITT_BITS 0x00000002 +#define PADS_BANK0_SWD_SCHMITT_MSB 1 +#define PADS_BANK0_SWD_SCHMITT_LSB 1 +#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWD_SLEWFAST_RESET 0x0 +#define PADS_BANK0_SWD_SLEWFAST_BITS 0x00000001 +#define PADS_BANK0_SWD_SLEWFAST_MSB 0 +#define PADS_BANK0_SWD_SLEWFAST_LSB 0 +#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_PADS_BANK0_DEFINED diff --git a/rp2040/hardware/regs/pads_qspi.h b/rp2040/hardware/regs/pads_qspi.h new file mode 100644 index 0000000..7aba5e8 --- /dev/null +++ b/rp2040/hardware/regs/pads_qspi.h @@ -0,0 +1,454 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_QSPI +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED +#define HARDWARE_REGS_PADS_QSPI_DEFINED +// ============================================================================= +// Register : PADS_QSPI_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET 0x00000000 +#define PADS_QSPI_VOLTAGE_SELECT_BITS 0x00000001 +#define PADS_QSPI_VOLTAGE_SELECT_RESET 0x00000000 +#define PADS_QSPI_VOLTAGE_SELECT_MSB 0 +#define PADS_QSPI_VOLTAGE_SELECT_LSB 0 +#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 0x0 +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 0x1 +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SCLK +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SCLK_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SCLK_RESET 0x00000056 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD0 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD0_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD0_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD1 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET 0x0000000c +#define PADS_QSPI_GPIO_QSPI_SD1_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD1_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD2 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET 0x00000010 +#define PADS_QSPI_GPIO_QSPI_SD2_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD2_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD3 +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET 0x00000014 +#define PADS_QSPI_GPIO_QSPI_SD3_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SD3_RESET 0x00000052 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SS +// Description : Pad control register +#define PADS_QSPI_GPIO_QSPI_SS_OFFSET 0x00000018 +#define PADS_QSPI_GPIO_QSPI_SS_BITS 0x000000ff +#define PADS_QSPI_GPIO_QSPI_SS_RESET 0x0000005a +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS 0x00000080 +#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB 7 +#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB 7 +#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS 0x00000040 +#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB 6 +#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB 6 +#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS 0x00000030 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB 5 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB 4 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA 0x2 +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA 0x3 +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS 0x00000008 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB 3 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB 3 +#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS 0x00000004 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB 2 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB 2 +#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET 0x1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS 0x00000002 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB 1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB 1 +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET 0x0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS 0x00000001 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB 0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB 0 +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_PADS_QSPI_DEFINED diff --git a/rp2040/hardware/regs/pio.h b/rp2040/hardware/regs/pio.h new file mode 100644 index 0000000..503aa09 --- /dev/null +++ b/rp2040/hardware/regs/pio.h @@ -0,0 +1,2591 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PIO +// Version : 1 +// Bus type : ahbl +// Description : Programmable IO block +// ============================================================================= +#ifndef HARDWARE_REGS_PIO_DEFINED +#define HARDWARE_REGS_PIO_DEFINED +// ============================================================================= +// Register : PIO_CTRL +// Description : PIO control register +#define PIO_CTRL_OFFSET 0x00000000 +#define PIO_CTRL_BITS 0x00000fff +#define PIO_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_CLKDIV_RESTART +// Description : Force clock dividers to restart their count and clear +// fractional +// accumulators. Restart multiple dividers to synchronise them. +#define PIO_CTRL_CLKDIV_RESTART_RESET 0x0 +#define PIO_CTRL_CLKDIV_RESTART_BITS 0x00000f00 +#define PIO_CTRL_CLKDIV_RESTART_MSB 11 +#define PIO_CTRL_CLKDIV_RESTART_LSB 8 +#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_RESTART +// Description : Clear internal SM state which is otherwise difficult to access +// (e.g. shift counters). Self-clearing. +#define PIO_CTRL_SM_RESTART_RESET 0x0 +#define PIO_CTRL_SM_RESTART_BITS 0x000000f0 +#define PIO_CTRL_SM_RESTART_MSB 7 +#define PIO_CTRL_SM_RESTART_LSB 4 +#define PIO_CTRL_SM_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_ENABLE +// Description : Enable state machine +#define PIO_CTRL_SM_ENABLE_RESET 0x0 +#define PIO_CTRL_SM_ENABLE_BITS 0x0000000f +#define PIO_CTRL_SM_ENABLE_MSB 3 +#define PIO_CTRL_SM_ENABLE_LSB 0 +#define PIO_CTRL_SM_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : PIO_FSTAT +// Description : FIFO status register +#define PIO_FSTAT_OFFSET 0x00000004 +#define PIO_FSTAT_BITS 0x0f0f0f0f +#define PIO_FSTAT_RESET 0x0f000f00 +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXEMPTY +// Description : State machine TX FIFO is empty +#define PIO_FSTAT_TXEMPTY_RESET 0xf +#define PIO_FSTAT_TXEMPTY_BITS 0x0f000000 +#define PIO_FSTAT_TXEMPTY_MSB 27 +#define PIO_FSTAT_TXEMPTY_LSB 24 +#define PIO_FSTAT_TXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXFULL +// Description : State machine TX FIFO is full +#define PIO_FSTAT_TXFULL_RESET 0x0 +#define PIO_FSTAT_TXFULL_BITS 0x000f0000 +#define PIO_FSTAT_TXFULL_MSB 19 +#define PIO_FSTAT_TXFULL_LSB 16 +#define PIO_FSTAT_TXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXEMPTY +// Description : State machine RX FIFO is empty +#define PIO_FSTAT_RXEMPTY_RESET 0xf +#define PIO_FSTAT_RXEMPTY_BITS 0x00000f00 +#define PIO_FSTAT_RXEMPTY_MSB 11 +#define PIO_FSTAT_RXEMPTY_LSB 8 +#define PIO_FSTAT_RXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXFULL +// Description : State machine RX FIFO is full +#define PIO_FSTAT_RXFULL_RESET 0x0 +#define PIO_FSTAT_RXFULL_BITS 0x0000000f +#define PIO_FSTAT_RXFULL_MSB 3 +#define PIO_FSTAT_RXFULL_LSB 0 +#define PIO_FSTAT_RXFULL_ACCESS "RO" +// ============================================================================= +// Register : PIO_FDEBUG +// Description : FIFO debug register +#define PIO_FDEBUG_OFFSET 0x00000008 +#define PIO_FDEBUG_BITS 0x0f0f0f0f +#define PIO_FDEBUG_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXSTALL +// Description : State machine has stalled on empty TX FIFO. Write 1 to clear. +#define PIO_FDEBUG_TXSTALL_RESET 0x0 +#define PIO_FDEBUG_TXSTALL_BITS 0x0f000000 +#define PIO_FDEBUG_TXSTALL_MSB 27 +#define PIO_FDEBUG_TXSTALL_LSB 24 +#define PIO_FDEBUG_TXSTALL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXOVER +// Description : TX FIFO overflow has occurred. Write 1 to clear. +#define PIO_FDEBUG_TXOVER_RESET 0x0 +#define PIO_FDEBUG_TXOVER_BITS 0x000f0000 +#define PIO_FDEBUG_TXOVER_MSB 19 +#define PIO_FDEBUG_TXOVER_LSB 16 +#define PIO_FDEBUG_TXOVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXUNDER +// Description : RX FIFO underflow has occurred. Write 1 to clear. +#define PIO_FDEBUG_RXUNDER_RESET 0x0 +#define PIO_FDEBUG_RXUNDER_BITS 0x00000f00 +#define PIO_FDEBUG_RXUNDER_MSB 11 +#define PIO_FDEBUG_RXUNDER_LSB 8 +#define PIO_FDEBUG_RXUNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXSTALL +// Description : State machine has stalled on full RX FIFO. Write 1 to clear. +#define PIO_FDEBUG_RXSTALL_RESET 0x0 +#define PIO_FDEBUG_RXSTALL_BITS 0x0000000f +#define PIO_FDEBUG_RXSTALL_MSB 3 +#define PIO_FDEBUG_RXSTALL_LSB 0 +#define PIO_FDEBUG_RXSTALL_ACCESS "WC" +// ============================================================================= +// Register : PIO_FLEVEL +// Description : FIFO levels +#define PIO_FLEVEL_OFFSET 0x0000000c +#define PIO_FLEVEL_BITS 0xffffffff +#define PIO_FLEVEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX3 +// Description : None +#define PIO_FLEVEL_RX3_RESET 0x0 +#define PIO_FLEVEL_RX3_BITS 0xf0000000 +#define PIO_FLEVEL_RX3_MSB 31 +#define PIO_FLEVEL_RX3_LSB 28 +#define PIO_FLEVEL_RX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX3 +// Description : None +#define PIO_FLEVEL_TX3_RESET 0x0 +#define PIO_FLEVEL_TX3_BITS 0x0f000000 +#define PIO_FLEVEL_TX3_MSB 27 +#define PIO_FLEVEL_TX3_LSB 24 +#define PIO_FLEVEL_TX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX2 +// Description : None +#define PIO_FLEVEL_RX2_RESET 0x0 +#define PIO_FLEVEL_RX2_BITS 0x00f00000 +#define PIO_FLEVEL_RX2_MSB 23 +#define PIO_FLEVEL_RX2_LSB 20 +#define PIO_FLEVEL_RX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX2 +// Description : None +#define PIO_FLEVEL_TX2_RESET 0x0 +#define PIO_FLEVEL_TX2_BITS 0x000f0000 +#define PIO_FLEVEL_TX2_MSB 19 +#define PIO_FLEVEL_TX2_LSB 16 +#define PIO_FLEVEL_TX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX1 +// Description : None +#define PIO_FLEVEL_RX1_RESET 0x0 +#define PIO_FLEVEL_RX1_BITS 0x0000f000 +#define PIO_FLEVEL_RX1_MSB 15 +#define PIO_FLEVEL_RX1_LSB 12 +#define PIO_FLEVEL_RX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX1 +// Description : None +#define PIO_FLEVEL_TX1_RESET 0x0 +#define PIO_FLEVEL_TX1_BITS 0x00000f00 +#define PIO_FLEVEL_TX1_MSB 11 +#define PIO_FLEVEL_TX1_LSB 8 +#define PIO_FLEVEL_TX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX0 +// Description : None +#define PIO_FLEVEL_RX0_RESET 0x0 +#define PIO_FLEVEL_RX0_BITS 0x000000f0 +#define PIO_FLEVEL_RX0_MSB 7 +#define PIO_FLEVEL_RX0_LSB 4 +#define PIO_FLEVEL_RX0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX0 +// Description : None +#define PIO_FLEVEL_TX0_RESET 0x0 +#define PIO_FLEVEL_TX0_BITS 0x0000000f +#define PIO_FLEVEL_TX0_MSB 3 +#define PIO_FLEVEL_TX0_LSB 0 +#define PIO_FLEVEL_TX0_ACCESS "RO" +// ============================================================================= +// Register : PIO_TXF0 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF0_OFFSET 0x00000010 +#define PIO_TXF0_BITS 0xffffffff +#define PIO_TXF0_RESET 0x00000000 +#define PIO_TXF0_MSB 31 +#define PIO_TXF0_LSB 0 +#define PIO_TXF0_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF1 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF1_OFFSET 0x00000014 +#define PIO_TXF1_BITS 0xffffffff +#define PIO_TXF1_RESET 0x00000000 +#define PIO_TXF1_MSB 31 +#define PIO_TXF1_LSB 0 +#define PIO_TXF1_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF2 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF2_OFFSET 0x00000018 +#define PIO_TXF2_BITS 0xffffffff +#define PIO_TXF2_RESET 0x00000000 +#define PIO_TXF2_MSB 31 +#define PIO_TXF2_LSB 0 +#define PIO_TXF2_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF3 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. +#define PIO_TXF3_OFFSET 0x0000001c +#define PIO_TXF3_BITS 0xffffffff +#define PIO_TXF3_RESET 0x00000000 +#define PIO_TXF3_MSB 31 +#define PIO_TXF3_LSB 0 +#define PIO_TXF3_ACCESS "WF" +// ============================================================================= +// Register : PIO_RXF0 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF0_OFFSET 0x00000020 +#define PIO_RXF0_BITS 0xffffffff +#define PIO_RXF0_RESET "-" +#define PIO_RXF0_MSB 31 +#define PIO_RXF0_LSB 0 +#define PIO_RXF0_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF1 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF1_OFFSET 0x00000024 +#define PIO_RXF1_BITS 0xffffffff +#define PIO_RXF1_RESET "-" +#define PIO_RXF1_MSB 31 +#define PIO_RXF1_LSB 0 +#define PIO_RXF1_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF2 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF2_OFFSET 0x00000028 +#define PIO_RXF2_BITS 0xffffffff +#define PIO_RXF2_RESET "-" +#define PIO_RXF2_MSB 31 +#define PIO_RXF2_LSB 0 +#define PIO_RXF2_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF3 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. +#define PIO_RXF3_OFFSET 0x0000002c +#define PIO_RXF3_BITS 0xffffffff +#define PIO_RXF3_RESET "-" +#define PIO_RXF3_MSB 31 +#define PIO_RXF3_LSB 0 +#define PIO_RXF3_ACCESS "RF" +// ============================================================================= +// Register : PIO_IRQ +// Description : Interrupt request register. Write 1 to clear +#define PIO_IRQ_OFFSET 0x00000030 +#define PIO_IRQ_BITS 0x000000ff +#define PIO_IRQ_RESET 0x00000000 +#define PIO_IRQ_MSB 7 +#define PIO_IRQ_LSB 0 +#define PIO_IRQ_ACCESS "WC" +// ============================================================================= +// Register : PIO_IRQ_FORCE +// Description : Writing a 1 to each of these bits will forcibly assert the +// corresponding IRQ. +// Note this is different to the INTF register: writing here +// affects PIO internal +// state. INTF just asserts the processor-facing IRQ signal for +// testing ISRs, +// and is not visible to the state machines. +#define PIO_IRQ_FORCE_OFFSET 0x00000034 +#define PIO_IRQ_FORCE_BITS 0x000000ff +#define PIO_IRQ_FORCE_RESET 0x00000000 +#define PIO_IRQ_FORCE_MSB 7 +#define PIO_IRQ_FORCE_LSB 0 +#define PIO_IRQ_FORCE_ACCESS "WF" +// ============================================================================= +// Register : PIO_INPUT_SYNC_BYPASS +// Description : There is a 2-flipflop synchronizer on each GPIO input, which +// protects +// PIO logic from metastabilities. This increases input delay, and +// for fast +// synchronous IO (e.g. SPI) these synchronizers may need to be +// bypassed. +// Each bit in this register corresponds to one GPIO. +// 0 -> input is synchronized (default) +// 1 -> synchronizer is bypassed +// If in doubt, leave this register as all zeroes. +#define PIO_INPUT_SYNC_BYPASS_OFFSET 0x00000038 +#define PIO_INPUT_SYNC_BYPASS_BITS 0xffffffff +#define PIO_INPUT_SYNC_BYPASS_RESET 0x00000000 +#define PIO_INPUT_SYNC_BYPASS_MSB 31 +#define PIO_INPUT_SYNC_BYPASS_LSB 0 +#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" +// ============================================================================= +// Register : PIO_DBG_PADOUT +// Description : Read to sample the pad output values PIO is currently driving +// to the GPIOs. +#define PIO_DBG_PADOUT_OFFSET 0x0000003c +#define PIO_DBG_PADOUT_BITS 0xffffffff +#define PIO_DBG_PADOUT_RESET 0x00000000 +#define PIO_DBG_PADOUT_MSB 31 +#define PIO_DBG_PADOUT_LSB 0 +#define PIO_DBG_PADOUT_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_PADOE +// Description : Read to sample the pad output enables (direction) PIO is +// currently driving to the GPIOs. +#define PIO_DBG_PADOE_OFFSET 0x00000040 +#define PIO_DBG_PADOE_BITS 0xffffffff +#define PIO_DBG_PADOE_RESET 0x00000000 +#define PIO_DBG_PADOE_MSB 31 +#define PIO_DBG_PADOE_LSB 0 +#define PIO_DBG_PADOE_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_CFGINFO +// Description : The PIO hardware has some free parameters that may vary between +// chip products. +// These should be provided in the chip datasheet, but are also +// exposed here. +#define PIO_DBG_CFGINFO_OFFSET 0x00000044 +#define PIO_DBG_CFGINFO_BITS 0x003f0f3f +#define PIO_DBG_CFGINFO_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_IMEM_SIZE +// Description : The size of the instruction memory, measured in units of one +// instruction +#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" +#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS 0x003f0000 +#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB 21 +#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB 16 +#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_SM_COUNT +// Description : The number of state machines this PIO instance is equipped +// with. +#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" +#define PIO_DBG_CFGINFO_SM_COUNT_BITS 0x00000f00 +#define PIO_DBG_CFGINFO_SM_COUNT_MSB 11 +#define PIO_DBG_CFGINFO_SM_COUNT_LSB 8 +#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_FIFO_DEPTH +// Description : The depth of the state machine TX/RX FIFOs, measured in words. +// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double +// this depth. +#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" +#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS 0x0000003f +#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB 5 +#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB 0 +#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" +// ============================================================================= +// Register : PIO_INSTR_MEM0 +// Description : Write-only access to instruction memory location 0 +#define PIO_INSTR_MEM0_OFFSET 0x00000048 +#define PIO_INSTR_MEM0_BITS 0x0000ffff +#define PIO_INSTR_MEM0_RESET 0x00000000 +#define PIO_INSTR_MEM0_MSB 15 +#define PIO_INSTR_MEM0_LSB 0 +#define PIO_INSTR_MEM0_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM1 +// Description : Write-only access to instruction memory location 1 +#define PIO_INSTR_MEM1_OFFSET 0x0000004c +#define PIO_INSTR_MEM1_BITS 0x0000ffff +#define PIO_INSTR_MEM1_RESET 0x00000000 +#define PIO_INSTR_MEM1_MSB 15 +#define PIO_INSTR_MEM1_LSB 0 +#define PIO_INSTR_MEM1_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM2 +// Description : Write-only access to instruction memory location 2 +#define PIO_INSTR_MEM2_OFFSET 0x00000050 +#define PIO_INSTR_MEM2_BITS 0x0000ffff +#define PIO_INSTR_MEM2_RESET 0x00000000 +#define PIO_INSTR_MEM2_MSB 15 +#define PIO_INSTR_MEM2_LSB 0 +#define PIO_INSTR_MEM2_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM3 +// Description : Write-only access to instruction memory location 3 +#define PIO_INSTR_MEM3_OFFSET 0x00000054 +#define PIO_INSTR_MEM3_BITS 0x0000ffff +#define PIO_INSTR_MEM3_RESET 0x00000000 +#define PIO_INSTR_MEM3_MSB 15 +#define PIO_INSTR_MEM3_LSB 0 +#define PIO_INSTR_MEM3_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM4 +// Description : Write-only access to instruction memory location 4 +#define PIO_INSTR_MEM4_OFFSET 0x00000058 +#define PIO_INSTR_MEM4_BITS 0x0000ffff +#define PIO_INSTR_MEM4_RESET 0x00000000 +#define PIO_INSTR_MEM4_MSB 15 +#define PIO_INSTR_MEM4_LSB 0 +#define PIO_INSTR_MEM4_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM5 +// Description : Write-only access to instruction memory location 5 +#define PIO_INSTR_MEM5_OFFSET 0x0000005c +#define PIO_INSTR_MEM5_BITS 0x0000ffff +#define PIO_INSTR_MEM5_RESET 0x00000000 +#define PIO_INSTR_MEM5_MSB 15 +#define PIO_INSTR_MEM5_LSB 0 +#define PIO_INSTR_MEM5_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM6 +// Description : Write-only access to instruction memory location 6 +#define PIO_INSTR_MEM6_OFFSET 0x00000060 +#define PIO_INSTR_MEM6_BITS 0x0000ffff +#define PIO_INSTR_MEM6_RESET 0x00000000 +#define PIO_INSTR_MEM6_MSB 15 +#define PIO_INSTR_MEM6_LSB 0 +#define PIO_INSTR_MEM6_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM7 +// Description : Write-only access to instruction memory location 7 +#define PIO_INSTR_MEM7_OFFSET 0x00000064 +#define PIO_INSTR_MEM7_BITS 0x0000ffff +#define PIO_INSTR_MEM7_RESET 0x00000000 +#define PIO_INSTR_MEM7_MSB 15 +#define PIO_INSTR_MEM7_LSB 0 +#define PIO_INSTR_MEM7_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM8 +// Description : Write-only access to instruction memory location 8 +#define PIO_INSTR_MEM8_OFFSET 0x00000068 +#define PIO_INSTR_MEM8_BITS 0x0000ffff +#define PIO_INSTR_MEM8_RESET 0x00000000 +#define PIO_INSTR_MEM8_MSB 15 +#define PIO_INSTR_MEM8_LSB 0 +#define PIO_INSTR_MEM8_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM9 +// Description : Write-only access to instruction memory location 9 +#define PIO_INSTR_MEM9_OFFSET 0x0000006c +#define PIO_INSTR_MEM9_BITS 0x0000ffff +#define PIO_INSTR_MEM9_RESET 0x00000000 +#define PIO_INSTR_MEM9_MSB 15 +#define PIO_INSTR_MEM9_LSB 0 +#define PIO_INSTR_MEM9_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM10 +// Description : Write-only access to instruction memory location 10 +#define PIO_INSTR_MEM10_OFFSET 0x00000070 +#define PIO_INSTR_MEM10_BITS 0x0000ffff +#define PIO_INSTR_MEM10_RESET 0x00000000 +#define PIO_INSTR_MEM10_MSB 15 +#define PIO_INSTR_MEM10_LSB 0 +#define PIO_INSTR_MEM10_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM11 +// Description : Write-only access to instruction memory location 11 +#define PIO_INSTR_MEM11_OFFSET 0x00000074 +#define PIO_INSTR_MEM11_BITS 0x0000ffff +#define PIO_INSTR_MEM11_RESET 0x00000000 +#define PIO_INSTR_MEM11_MSB 15 +#define PIO_INSTR_MEM11_LSB 0 +#define PIO_INSTR_MEM11_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM12 +// Description : Write-only access to instruction memory location 12 +#define PIO_INSTR_MEM12_OFFSET 0x00000078 +#define PIO_INSTR_MEM12_BITS 0x0000ffff +#define PIO_INSTR_MEM12_RESET 0x00000000 +#define PIO_INSTR_MEM12_MSB 15 +#define PIO_INSTR_MEM12_LSB 0 +#define PIO_INSTR_MEM12_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM13 +// Description : Write-only access to instruction memory location 13 +#define PIO_INSTR_MEM13_OFFSET 0x0000007c +#define PIO_INSTR_MEM13_BITS 0x0000ffff +#define PIO_INSTR_MEM13_RESET 0x00000000 +#define PIO_INSTR_MEM13_MSB 15 +#define PIO_INSTR_MEM13_LSB 0 +#define PIO_INSTR_MEM13_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM14 +// Description : Write-only access to instruction memory location 14 +#define PIO_INSTR_MEM14_OFFSET 0x00000080 +#define PIO_INSTR_MEM14_BITS 0x0000ffff +#define PIO_INSTR_MEM14_RESET 0x00000000 +#define PIO_INSTR_MEM14_MSB 15 +#define PIO_INSTR_MEM14_LSB 0 +#define PIO_INSTR_MEM14_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM15 +// Description : Write-only access to instruction memory location 15 +#define PIO_INSTR_MEM15_OFFSET 0x00000084 +#define PIO_INSTR_MEM15_BITS 0x0000ffff +#define PIO_INSTR_MEM15_RESET 0x00000000 +#define PIO_INSTR_MEM15_MSB 15 +#define PIO_INSTR_MEM15_LSB 0 +#define PIO_INSTR_MEM15_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM16 +// Description : Write-only access to instruction memory location 16 +#define PIO_INSTR_MEM16_OFFSET 0x00000088 +#define PIO_INSTR_MEM16_BITS 0x0000ffff +#define PIO_INSTR_MEM16_RESET 0x00000000 +#define PIO_INSTR_MEM16_MSB 15 +#define PIO_INSTR_MEM16_LSB 0 +#define PIO_INSTR_MEM16_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM17 +// Description : Write-only access to instruction memory location 17 +#define PIO_INSTR_MEM17_OFFSET 0x0000008c +#define PIO_INSTR_MEM17_BITS 0x0000ffff +#define PIO_INSTR_MEM17_RESET 0x00000000 +#define PIO_INSTR_MEM17_MSB 15 +#define PIO_INSTR_MEM17_LSB 0 +#define PIO_INSTR_MEM17_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM18 +// Description : Write-only access to instruction memory location 18 +#define PIO_INSTR_MEM18_OFFSET 0x00000090 +#define PIO_INSTR_MEM18_BITS 0x0000ffff +#define PIO_INSTR_MEM18_RESET 0x00000000 +#define PIO_INSTR_MEM18_MSB 15 +#define PIO_INSTR_MEM18_LSB 0 +#define PIO_INSTR_MEM18_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM19 +// Description : Write-only access to instruction memory location 19 +#define PIO_INSTR_MEM19_OFFSET 0x00000094 +#define PIO_INSTR_MEM19_BITS 0x0000ffff +#define PIO_INSTR_MEM19_RESET 0x00000000 +#define PIO_INSTR_MEM19_MSB 15 +#define PIO_INSTR_MEM19_LSB 0 +#define PIO_INSTR_MEM19_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM20 +// Description : Write-only access to instruction memory location 20 +#define PIO_INSTR_MEM20_OFFSET 0x00000098 +#define PIO_INSTR_MEM20_BITS 0x0000ffff +#define PIO_INSTR_MEM20_RESET 0x00000000 +#define PIO_INSTR_MEM20_MSB 15 +#define PIO_INSTR_MEM20_LSB 0 +#define PIO_INSTR_MEM20_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM21 +// Description : Write-only access to instruction memory location 21 +#define PIO_INSTR_MEM21_OFFSET 0x0000009c +#define PIO_INSTR_MEM21_BITS 0x0000ffff +#define PIO_INSTR_MEM21_RESET 0x00000000 +#define PIO_INSTR_MEM21_MSB 15 +#define PIO_INSTR_MEM21_LSB 0 +#define PIO_INSTR_MEM21_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM22 +// Description : Write-only access to instruction memory location 22 +#define PIO_INSTR_MEM22_OFFSET 0x000000a0 +#define PIO_INSTR_MEM22_BITS 0x0000ffff +#define PIO_INSTR_MEM22_RESET 0x00000000 +#define PIO_INSTR_MEM22_MSB 15 +#define PIO_INSTR_MEM22_LSB 0 +#define PIO_INSTR_MEM22_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM23 +// Description : Write-only access to instruction memory location 23 +#define PIO_INSTR_MEM23_OFFSET 0x000000a4 +#define PIO_INSTR_MEM23_BITS 0x0000ffff +#define PIO_INSTR_MEM23_RESET 0x00000000 +#define PIO_INSTR_MEM23_MSB 15 +#define PIO_INSTR_MEM23_LSB 0 +#define PIO_INSTR_MEM23_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM24 +// Description : Write-only access to instruction memory location 24 +#define PIO_INSTR_MEM24_OFFSET 0x000000a8 +#define PIO_INSTR_MEM24_BITS 0x0000ffff +#define PIO_INSTR_MEM24_RESET 0x00000000 +#define PIO_INSTR_MEM24_MSB 15 +#define PIO_INSTR_MEM24_LSB 0 +#define PIO_INSTR_MEM24_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM25 +// Description : Write-only access to instruction memory location 25 +#define PIO_INSTR_MEM25_OFFSET 0x000000ac +#define PIO_INSTR_MEM25_BITS 0x0000ffff +#define PIO_INSTR_MEM25_RESET 0x00000000 +#define PIO_INSTR_MEM25_MSB 15 +#define PIO_INSTR_MEM25_LSB 0 +#define PIO_INSTR_MEM25_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM26 +// Description : Write-only access to instruction memory location 26 +#define PIO_INSTR_MEM26_OFFSET 0x000000b0 +#define PIO_INSTR_MEM26_BITS 0x0000ffff +#define PIO_INSTR_MEM26_RESET 0x00000000 +#define PIO_INSTR_MEM26_MSB 15 +#define PIO_INSTR_MEM26_LSB 0 +#define PIO_INSTR_MEM26_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM27 +// Description : Write-only access to instruction memory location 27 +#define PIO_INSTR_MEM27_OFFSET 0x000000b4 +#define PIO_INSTR_MEM27_BITS 0x0000ffff +#define PIO_INSTR_MEM27_RESET 0x00000000 +#define PIO_INSTR_MEM27_MSB 15 +#define PIO_INSTR_MEM27_LSB 0 +#define PIO_INSTR_MEM27_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM28 +// Description : Write-only access to instruction memory location 28 +#define PIO_INSTR_MEM28_OFFSET 0x000000b8 +#define PIO_INSTR_MEM28_BITS 0x0000ffff +#define PIO_INSTR_MEM28_RESET 0x00000000 +#define PIO_INSTR_MEM28_MSB 15 +#define PIO_INSTR_MEM28_LSB 0 +#define PIO_INSTR_MEM28_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM29 +// Description : Write-only access to instruction memory location 29 +#define PIO_INSTR_MEM29_OFFSET 0x000000bc +#define PIO_INSTR_MEM29_BITS 0x0000ffff +#define PIO_INSTR_MEM29_RESET 0x00000000 +#define PIO_INSTR_MEM29_MSB 15 +#define PIO_INSTR_MEM29_LSB 0 +#define PIO_INSTR_MEM29_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM30 +// Description : Write-only access to instruction memory location 30 +#define PIO_INSTR_MEM30_OFFSET 0x000000c0 +#define PIO_INSTR_MEM30_BITS 0x0000ffff +#define PIO_INSTR_MEM30_RESET 0x00000000 +#define PIO_INSTR_MEM30_MSB 15 +#define PIO_INSTR_MEM30_LSB 0 +#define PIO_INSTR_MEM30_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM31 +// Description : Write-only access to instruction memory location 31 +#define PIO_INSTR_MEM31_OFFSET 0x000000c4 +#define PIO_INSTR_MEM31_BITS 0x0000ffff +#define PIO_INSTR_MEM31_RESET 0x00000000 +#define PIO_INSTR_MEM31_MSB 15 +#define PIO_INSTR_MEM31_LSB 0 +#define PIO_INSTR_MEM31_ACCESS "WO" +// ============================================================================= +// Register : PIO_SM0_CLKDIV +// Description : Clock divider register for state machine 0 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM0_CLKDIV_OFFSET 0x000000c8 +#define PIO_SM0_CLKDIV_BITS 0xffffff00 +#define PIO_SM0_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM0_CLKDIV_INT_RESET 0x0001 +#define PIO_SM0_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM0_CLKDIV_INT_MSB 31 +#define PIO_SM0_CLKDIV_INT_LSB 16 +#define PIO_SM0_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM0_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM0_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM0_CLKDIV_FRAC_MSB 15 +#define PIO_SM0_CLKDIV_FRAC_LSB 8 +#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_EXECCTRL +// Description : Execution/behavioural settings for state machine 0 +#define PIO_SM0_EXECCTRL_OFFSET 0x000000cc +#define PIO_SM0_EXECCTRL_BITS 0xffffff9f +#define PIO_SM0_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM0_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM0_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM0_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM0_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM0_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM0_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM0_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM0_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM0_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM0_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM0_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM0_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 0 +#define PIO_SM0_SHIFTCTRL_OFFSET 0x000000d0 +#define PIO_SM0_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM0_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_ADDR +// Description : Current instruction address of state machine 0 +#define PIO_SM0_ADDR_OFFSET 0x000000d4 +#define PIO_SM0_ADDR_BITS 0x0000001f +#define PIO_SM0_ADDR_RESET 0x00000000 +#define PIO_SM0_ADDR_MSB 4 +#define PIO_SM0_ADDR_LSB 0 +#define PIO_SM0_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM0_INSTR +// Description : Instruction currently being executed by state machine 0 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM0_INSTR_OFFSET 0x000000d8 +#define PIO_SM0_INSTR_BITS 0x0000ffff +#define PIO_SM0_INSTR_RESET "-" +#define PIO_SM0_INSTR_MSB 15 +#define PIO_SM0_INSTR_LSB 0 +#define PIO_SM0_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_PINCTRL +// Description : State machine pin control +#define PIO_SM0_PINCTRL_OFFSET 0x000000dc +#define PIO_SM0_PINCTRL_BITS 0xffffffff +#define PIO_SM0_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM0_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM0_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM0_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM0_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM0_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM0_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM0_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM0_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM0_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM0_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM0_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM0_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM0_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM0_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM0_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM0_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM0_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM0_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_CLKDIV +// Description : Clock divider register for state machine 1 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM1_CLKDIV_OFFSET 0x000000e0 +#define PIO_SM1_CLKDIV_BITS 0xffffff00 +#define PIO_SM1_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM1_CLKDIV_INT_RESET 0x0001 +#define PIO_SM1_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM1_CLKDIV_INT_MSB 31 +#define PIO_SM1_CLKDIV_INT_LSB 16 +#define PIO_SM1_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM1_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM1_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM1_CLKDIV_FRAC_MSB 15 +#define PIO_SM1_CLKDIV_FRAC_LSB 8 +#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_EXECCTRL +// Description : Execution/behavioural settings for state machine 1 +#define PIO_SM1_EXECCTRL_OFFSET 0x000000e4 +#define PIO_SM1_EXECCTRL_BITS 0xffffff9f +#define PIO_SM1_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM1_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM1_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM1_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM1_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM1_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM1_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM1_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM1_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM1_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM1_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM1_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM1_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 1 +#define PIO_SM1_SHIFTCTRL_OFFSET 0x000000e8 +#define PIO_SM1_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM1_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_ADDR +// Description : Current instruction address of state machine 1 +#define PIO_SM1_ADDR_OFFSET 0x000000ec +#define PIO_SM1_ADDR_BITS 0x0000001f +#define PIO_SM1_ADDR_RESET 0x00000000 +#define PIO_SM1_ADDR_MSB 4 +#define PIO_SM1_ADDR_LSB 0 +#define PIO_SM1_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM1_INSTR +// Description : Instruction currently being executed by state machine 1 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM1_INSTR_OFFSET 0x000000f0 +#define PIO_SM1_INSTR_BITS 0x0000ffff +#define PIO_SM1_INSTR_RESET "-" +#define PIO_SM1_INSTR_MSB 15 +#define PIO_SM1_INSTR_LSB 0 +#define PIO_SM1_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_PINCTRL +// Description : State machine pin control +#define PIO_SM1_PINCTRL_OFFSET 0x000000f4 +#define PIO_SM1_PINCTRL_BITS 0xffffffff +#define PIO_SM1_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM1_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM1_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM1_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM1_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM1_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM1_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM1_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM1_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM1_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM1_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM1_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM1_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM1_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM1_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM1_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM1_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM1_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM1_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_CLKDIV +// Description : Clock divider register for state machine 2 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM2_CLKDIV_OFFSET 0x000000f8 +#define PIO_SM2_CLKDIV_BITS 0xffffff00 +#define PIO_SM2_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM2_CLKDIV_INT_RESET 0x0001 +#define PIO_SM2_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM2_CLKDIV_INT_MSB 31 +#define PIO_SM2_CLKDIV_INT_LSB 16 +#define PIO_SM2_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM2_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM2_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM2_CLKDIV_FRAC_MSB 15 +#define PIO_SM2_CLKDIV_FRAC_LSB 8 +#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_EXECCTRL +// Description : Execution/behavioural settings for state machine 2 +#define PIO_SM2_EXECCTRL_OFFSET 0x000000fc +#define PIO_SM2_EXECCTRL_BITS 0xffffff9f +#define PIO_SM2_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM2_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM2_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM2_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM2_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM2_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM2_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM2_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM2_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM2_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM2_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM2_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM2_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 2 +#define PIO_SM2_SHIFTCTRL_OFFSET 0x00000100 +#define PIO_SM2_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM2_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_ADDR +// Description : Current instruction address of state machine 2 +#define PIO_SM2_ADDR_OFFSET 0x00000104 +#define PIO_SM2_ADDR_BITS 0x0000001f +#define PIO_SM2_ADDR_RESET 0x00000000 +#define PIO_SM2_ADDR_MSB 4 +#define PIO_SM2_ADDR_LSB 0 +#define PIO_SM2_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM2_INSTR +// Description : Instruction currently being executed by state machine 2 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM2_INSTR_OFFSET 0x00000108 +#define PIO_SM2_INSTR_BITS 0x0000ffff +#define PIO_SM2_INSTR_RESET "-" +#define PIO_SM2_INSTR_MSB 15 +#define PIO_SM2_INSTR_LSB 0 +#define PIO_SM2_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_PINCTRL +// Description : State machine pin control +#define PIO_SM2_PINCTRL_OFFSET 0x0000010c +#define PIO_SM2_PINCTRL_BITS 0xffffffff +#define PIO_SM2_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM2_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM2_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM2_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM2_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM2_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM2_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM2_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM2_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM2_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM2_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM2_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM2_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM2_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM2_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM2_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM2_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM2_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM2_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_CLKDIV +// Description : Clock divider register for state machine 3 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM3_CLKDIV_OFFSET 0x00000110 +#define PIO_SM3_CLKDIV_BITS 0xffffff00 +#define PIO_SM3_CLKDIV_RESET 0x00010000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_INT +// Description : Effective frequency is sysclk/int. +// Value of 0 is interpreted as max possible value +#define PIO_SM3_CLKDIV_INT_RESET 0x0001 +#define PIO_SM3_CLKDIV_INT_BITS 0xffff0000 +#define PIO_SM3_CLKDIV_INT_MSB 31 +#define PIO_SM3_CLKDIV_INT_LSB 16 +#define PIO_SM3_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_FRAC +// Description : Fractional part of clock divider +#define PIO_SM3_CLKDIV_FRAC_RESET 0x00 +#define PIO_SM3_CLKDIV_FRAC_BITS 0x0000ff00 +#define PIO_SM3_CLKDIV_FRAC_MSB 15 +#define PIO_SM3_CLKDIV_FRAC_LSB 8 +#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_EXECCTRL +// Description : Execution/behavioural settings for state machine 3 +#define PIO_SM3_EXECCTRL_OFFSET 0x00000114 +#define PIO_SM3_EXECCTRL_BITS 0xffffff9f +#define PIO_SM3_EXECCTRL_RESET 0x0001f000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_EXEC_STALLED +// Description : An instruction written to SMx_INSTR is stalled, and latched by +// the +// state machine. Will clear once the instruction completes. +#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET 0x0 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS 0x80000000 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB 31 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB 31 +#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_EN +// Description : If 1, the delay MSB is used as side-set enable, rather than a +// side-set data bit. This allows instructions to perform side-set +// optionally, +// rather than on every instruction. +#define PIO_SM3_EXECCTRL_SIDE_EN_RESET 0x0 +#define PIO_SM3_EXECCTRL_SIDE_EN_BITS 0x40000000 +#define PIO_SM3_EXECCTRL_SIDE_EN_MSB 30 +#define PIO_SM3_EXECCTRL_SIDE_EN_LSB 30 +#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR +// Description : Side-set data is asserted to pin OEs instead of pin values +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET 0x0 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS 0x20000000 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB 29 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB 29 +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM3_EXECCTRL_JMP_PIN_RESET 0x00 +#define PIO_SM3_EXECCTRL_JMP_PIN_BITS 0x1f000000 +#define PIO_SM3_EXECCTRL_JMP_PIN_MSB 28 +#define PIO_SM3_EXECCTRL_JMP_PIN_LSB 24 +#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET 0x00 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS 0x00f80000 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB 23 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB 19 +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET 0x0 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS 0x00040000 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB 18 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB 18 +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET 0x0 +#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS 0x00020000 +#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB 17 +#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB 17 +#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET 0x1f +#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS 0x0001f000 +#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB 16 +#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB 12 +#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET 0x00 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS 0x00000f80 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB 11 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB 7 +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET 0x0 +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS 0x00000010 +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB 4 +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB 4 +#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL 0x0 +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL 0x1 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_N +// Description : Comparison level for the MOV x, STATUS instruction +#define PIO_SM3_EXECCTRL_STATUS_N_RESET 0x0 +#define PIO_SM3_EXECCTRL_STATUS_N_BITS 0x0000000f +#define PIO_SM3_EXECCTRL_STATUS_N_MSB 3 +#define PIO_SM3_EXECCTRL_STATUS_N_LSB 0 +#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 3 +#define PIO_SM3_SHIFTCTRL_OFFSET 0x00000118 +#define PIO_SM3_SHIFTCTRL_BITS 0xffff0000 +#define PIO_SM3_SHIFTCTRL_RESET 0x000c0000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS 0x80000000 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB 31 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB 31 +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS 0x40000000 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB 30 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB 30 +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of TXSR before autopull or +// conditional pull. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET 0x00 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS 0x3e000000 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB 29 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB 25 +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into RXSR before autopush or conditional +// push. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET 0x00 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS 0x01f00000 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB 24 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB 20 +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET 0x1 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS 0x00080000 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB 19 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB 19 +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET 0x1 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS 0x00040000 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB 18 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB 18 +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied +#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS 0x00020000 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB 17 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB 17 +#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET 0x0 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS 0x00010000 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB 16 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB 16 +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_ADDR +// Description : Current instruction address of state machine 3 +#define PIO_SM3_ADDR_OFFSET 0x0000011c +#define PIO_SM3_ADDR_BITS 0x0000001f +#define PIO_SM3_ADDR_RESET 0x00000000 +#define PIO_SM3_ADDR_MSB 4 +#define PIO_SM3_ADDR_LSB 0 +#define PIO_SM3_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM3_INSTR +// Description : Instruction currently being executed by state machine 3 +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM3_INSTR_OFFSET 0x00000120 +#define PIO_SM3_INSTR_BITS 0x0000ffff +#define PIO_SM3_INSTR_RESET "-" +#define PIO_SM3_INSTR_MSB 15 +#define PIO_SM3_INSTR_LSB 0 +#define PIO_SM3_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_PINCTRL +// Description : State machine pin control +#define PIO_SM3_PINCTRL_OFFSET 0x00000124 +#define PIO_SM3_PINCTRL_BITS 0xffffffff +#define PIO_SM3_PINCTRL_RESET 0x14000000 +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_COUNT +// Description : The number of delay bits co-opted for side-set. Inclusive of +// the enable bit, if present. +#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET 0x0 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS 0xe0000000 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB 31 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB 29 +#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. Max of 5 +#define PIO_SM3_PINCTRL_SET_COUNT_RESET 0x5 +#define PIO_SM3_PINCTRL_SET_COUNT_BITS 0x1c000000 +#define PIO_SM3_PINCTRL_SET_COUNT_MSB 28 +#define PIO_SM3_PINCTRL_SET_COUNT_LSB 26 +#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins +#define PIO_SM3_PINCTRL_OUT_COUNT_RESET 0x00 +#define PIO_SM3_PINCTRL_OUT_COUNT_BITS 0x03f00000 +#define PIO_SM3_PINCTRL_OUT_COUNT_MSB 25 +#define PIO_SM3_PINCTRL_OUT_COUNT_LSB 20 +#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_IN_BASE +// Description : The virtual pin corresponding to IN bit 0 +#define PIO_SM3_PINCTRL_IN_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_IN_BASE_BITS 0x000f8000 +#define PIO_SM3_PINCTRL_IN_BASE_MSB 19 +#define PIO_SM3_PINCTRL_IN_BASE_LSB 15 +#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_BASE +// Description : The virtual pin corresponding to delay field bit 0 +#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS 0x00007c00 +#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB 14 +#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB 10 +#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_BASE +// Description : The virtual pin corresponding to SET bit 0 +#define PIO_SM3_PINCTRL_SET_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_SET_BASE_BITS 0x000003e0 +#define PIO_SM3_PINCTRL_SET_BASE_MSB 9 +#define PIO_SM3_PINCTRL_SET_BASE_LSB 5 +#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_BASE +// Description : The virtual pin corresponding to OUT bit 0 +#define PIO_SM3_PINCTRL_OUT_BASE_RESET 0x00 +#define PIO_SM3_PINCTRL_OUT_BASE_BITS 0x0000001f +#define PIO_SM3_PINCTRL_OUT_BASE_MSB 4 +#define PIO_SM3_PINCTRL_OUT_BASE_LSB 0 +#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_INTR +// Description : Raw Interrupts +#define PIO_INTR_OFFSET 0x00000128 +#define PIO_INTR_BITS 0x00000fff +#define PIO_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3 +// Description : None +#define PIO_INTR_SM3_RESET 0x0 +#define PIO_INTR_SM3_BITS 0x00000800 +#define PIO_INTR_SM3_MSB 11 +#define PIO_INTR_SM3_LSB 11 +#define PIO_INTR_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2 +// Description : None +#define PIO_INTR_SM2_RESET 0x0 +#define PIO_INTR_SM2_BITS 0x00000400 +#define PIO_INTR_SM2_MSB 10 +#define PIO_INTR_SM2_LSB 10 +#define PIO_INTR_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1 +// Description : None +#define PIO_INTR_SM1_RESET 0x0 +#define PIO_INTR_SM1_BITS 0x00000200 +#define PIO_INTR_SM1_MSB 9 +#define PIO_INTR_SM1_LSB 9 +#define PIO_INTR_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0 +// Description : None +#define PIO_INTR_SM0_RESET 0x0 +#define PIO_INTR_SM0_BITS 0x00000100 +#define PIO_INTR_SM0_MSB 8 +#define PIO_INTR_SM0_LSB 8 +#define PIO_INTR_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_TXNFULL +// Description : None +#define PIO_INTR_SM3_TXNFULL_RESET 0x0 +#define PIO_INTR_SM3_TXNFULL_BITS 0x00000080 +#define PIO_INTR_SM3_TXNFULL_MSB 7 +#define PIO_INTR_SM3_TXNFULL_LSB 7 +#define PIO_INTR_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_TXNFULL +// Description : None +#define PIO_INTR_SM2_TXNFULL_RESET 0x0 +#define PIO_INTR_SM2_TXNFULL_BITS 0x00000040 +#define PIO_INTR_SM2_TXNFULL_MSB 6 +#define PIO_INTR_SM2_TXNFULL_LSB 6 +#define PIO_INTR_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_TXNFULL +// Description : None +#define PIO_INTR_SM1_TXNFULL_RESET 0x0 +#define PIO_INTR_SM1_TXNFULL_BITS 0x00000020 +#define PIO_INTR_SM1_TXNFULL_MSB 5 +#define PIO_INTR_SM1_TXNFULL_LSB 5 +#define PIO_INTR_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_TXNFULL +// Description : None +#define PIO_INTR_SM0_TXNFULL_RESET 0x0 +#define PIO_INTR_SM0_TXNFULL_BITS 0x00000010 +#define PIO_INTR_SM0_TXNFULL_MSB 4 +#define PIO_INTR_SM0_TXNFULL_LSB 4 +#define PIO_INTR_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_RXNEMPTY +// Description : None +#define PIO_INTR_SM3_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_INTR_SM3_RXNEMPTY_MSB 3 +#define PIO_INTR_SM3_RXNEMPTY_LSB 3 +#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_RXNEMPTY +// Description : None +#define PIO_INTR_SM2_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_INTR_SM2_RXNEMPTY_MSB 2 +#define PIO_INTR_SM2_RXNEMPTY_LSB 2 +#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_RXNEMPTY +// Description : None +#define PIO_INTR_SM1_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_INTR_SM1_RXNEMPTY_MSB 1 +#define PIO_INTR_SM1_RXNEMPTY_LSB 1 +#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_RXNEMPTY +// Description : None +#define PIO_INTR_SM0_RXNEMPTY_RESET 0x0 +#define PIO_INTR_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_INTR_SM0_RXNEMPTY_MSB 0 +#define PIO_INTR_SM0_RXNEMPTY_LSB 0 +#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ0_INTE +// Description : Interrupt Enable for irq0 +#define PIO_IRQ0_INTE_OFFSET 0x0000012c +#define PIO_IRQ0_INTE_BITS 0x00000fff +#define PIO_IRQ0_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3 +// Description : None +#define PIO_IRQ0_INTE_SM3_RESET 0x0 +#define PIO_IRQ0_INTE_SM3_BITS 0x00000800 +#define PIO_IRQ0_INTE_SM3_MSB 11 +#define PIO_IRQ0_INTE_SM3_LSB 11 +#define PIO_IRQ0_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2 +// Description : None +#define PIO_IRQ0_INTE_SM2_RESET 0x0 +#define PIO_IRQ0_INTE_SM2_BITS 0x00000400 +#define PIO_IRQ0_INTE_SM2_MSB 10 +#define PIO_IRQ0_INTE_SM2_LSB 10 +#define PIO_IRQ0_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1 +// Description : None +#define PIO_IRQ0_INTE_SM1_RESET 0x0 +#define PIO_IRQ0_INTE_SM1_BITS 0x00000200 +#define PIO_IRQ0_INTE_SM1_MSB 9 +#define PIO_IRQ0_INTE_SM1_LSB 9 +#define PIO_IRQ0_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0 +// Description : None +#define PIO_IRQ0_INTE_SM0_RESET 0x0 +#define PIO_IRQ0_INTE_SM0_BITS 0x00000100 +#define PIO_IRQ0_INTE_SM0_MSB 8 +#define PIO_IRQ0_INTE_SM0_LSB 8 +#define PIO_IRQ0_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB 7 +#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB 6 +#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB 5 +#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_TXNFULL +// Description : None +#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB 4 +#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTF +// Description : Interrupt Force for irq0 +#define PIO_IRQ0_INTF_OFFSET 0x00000130 +#define PIO_IRQ0_INTF_BITS 0x00000fff +#define PIO_IRQ0_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3 +// Description : None +#define PIO_IRQ0_INTF_SM3_RESET 0x0 +#define PIO_IRQ0_INTF_SM3_BITS 0x00000800 +#define PIO_IRQ0_INTF_SM3_MSB 11 +#define PIO_IRQ0_INTF_SM3_LSB 11 +#define PIO_IRQ0_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2 +// Description : None +#define PIO_IRQ0_INTF_SM2_RESET 0x0 +#define PIO_IRQ0_INTF_SM2_BITS 0x00000400 +#define PIO_IRQ0_INTF_SM2_MSB 10 +#define PIO_IRQ0_INTF_SM2_LSB 10 +#define PIO_IRQ0_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1 +// Description : None +#define PIO_IRQ0_INTF_SM1_RESET 0x0 +#define PIO_IRQ0_INTF_SM1_BITS 0x00000200 +#define PIO_IRQ0_INTF_SM1_MSB 9 +#define PIO_IRQ0_INTF_SM1_LSB 9 +#define PIO_IRQ0_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0 +// Description : None +#define PIO_IRQ0_INTF_SM0_RESET 0x0 +#define PIO_IRQ0_INTF_SM0_BITS 0x00000100 +#define PIO_IRQ0_INTF_SM0_MSB 8 +#define PIO_IRQ0_INTF_SM0_LSB 8 +#define PIO_IRQ0_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB 7 +#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB 6 +#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB 5 +#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_TXNFULL +// Description : None +#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB 4 +#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTS +// Description : Interrupt status after masking & forcing for irq0 +#define PIO_IRQ0_INTS_OFFSET 0x00000134 +#define PIO_IRQ0_INTS_BITS 0x00000fff +#define PIO_IRQ0_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3 +// Description : None +#define PIO_IRQ0_INTS_SM3_RESET 0x0 +#define PIO_IRQ0_INTS_SM3_BITS 0x00000800 +#define PIO_IRQ0_INTS_SM3_MSB 11 +#define PIO_IRQ0_INTS_SM3_LSB 11 +#define PIO_IRQ0_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2 +// Description : None +#define PIO_IRQ0_INTS_SM2_RESET 0x0 +#define PIO_IRQ0_INTS_SM2_BITS 0x00000400 +#define PIO_IRQ0_INTS_SM2_MSB 10 +#define PIO_IRQ0_INTS_SM2_LSB 10 +#define PIO_IRQ0_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1 +// Description : None +#define PIO_IRQ0_INTS_SM1_RESET 0x0 +#define PIO_IRQ0_INTS_SM1_BITS 0x00000200 +#define PIO_IRQ0_INTS_SM1_MSB 9 +#define PIO_IRQ0_INTS_SM1_LSB 9 +#define PIO_IRQ0_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0 +// Description : None +#define PIO_IRQ0_INTS_SM0_RESET 0x0 +#define PIO_IRQ0_INTS_SM0_BITS 0x00000100 +#define PIO_IRQ0_INTS_SM0_MSB 8 +#define PIO_IRQ0_INTS_SM0_LSB 8 +#define PIO_IRQ0_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB 7 +#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB 6 +#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB 5 +#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_TXNFULL +// Description : None +#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB 4 +#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ1_INTE +// Description : Interrupt Enable for irq1 +#define PIO_IRQ1_INTE_OFFSET 0x00000138 +#define PIO_IRQ1_INTE_BITS 0x00000fff +#define PIO_IRQ1_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3 +// Description : None +#define PIO_IRQ1_INTE_SM3_RESET 0x0 +#define PIO_IRQ1_INTE_SM3_BITS 0x00000800 +#define PIO_IRQ1_INTE_SM3_MSB 11 +#define PIO_IRQ1_INTE_SM3_LSB 11 +#define PIO_IRQ1_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2 +// Description : None +#define PIO_IRQ1_INTE_SM2_RESET 0x0 +#define PIO_IRQ1_INTE_SM2_BITS 0x00000400 +#define PIO_IRQ1_INTE_SM2_MSB 10 +#define PIO_IRQ1_INTE_SM2_LSB 10 +#define PIO_IRQ1_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1 +// Description : None +#define PIO_IRQ1_INTE_SM1_RESET 0x0 +#define PIO_IRQ1_INTE_SM1_BITS 0x00000200 +#define PIO_IRQ1_INTE_SM1_MSB 9 +#define PIO_IRQ1_INTE_SM1_LSB 9 +#define PIO_IRQ1_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0 +// Description : None +#define PIO_IRQ1_INTE_SM0_RESET 0x0 +#define PIO_IRQ1_INTE_SM0_BITS 0x00000100 +#define PIO_IRQ1_INTE_SM0_MSB 8 +#define PIO_IRQ1_INTE_SM0_LSB 8 +#define PIO_IRQ1_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB 7 +#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB 6 +#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB 5 +#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_TXNFULL +// Description : None +#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB 4 +#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTF +// Description : Interrupt Force for irq1 +#define PIO_IRQ1_INTF_OFFSET 0x0000013c +#define PIO_IRQ1_INTF_BITS 0x00000fff +#define PIO_IRQ1_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3 +// Description : None +#define PIO_IRQ1_INTF_SM3_RESET 0x0 +#define PIO_IRQ1_INTF_SM3_BITS 0x00000800 +#define PIO_IRQ1_INTF_SM3_MSB 11 +#define PIO_IRQ1_INTF_SM3_LSB 11 +#define PIO_IRQ1_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2 +// Description : None +#define PIO_IRQ1_INTF_SM2_RESET 0x0 +#define PIO_IRQ1_INTF_SM2_BITS 0x00000400 +#define PIO_IRQ1_INTF_SM2_MSB 10 +#define PIO_IRQ1_INTF_SM2_LSB 10 +#define PIO_IRQ1_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1 +// Description : None +#define PIO_IRQ1_INTF_SM1_RESET 0x0 +#define PIO_IRQ1_INTF_SM1_BITS 0x00000200 +#define PIO_IRQ1_INTF_SM1_MSB 9 +#define PIO_IRQ1_INTF_SM1_LSB 9 +#define PIO_IRQ1_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0 +// Description : None +#define PIO_IRQ1_INTF_SM0_RESET 0x0 +#define PIO_IRQ1_INTF_SM0_BITS 0x00000100 +#define PIO_IRQ1_INTF_SM0_MSB 8 +#define PIO_IRQ1_INTF_SM0_LSB 8 +#define PIO_IRQ1_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB 7 +#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB 6 +#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB 5 +#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_TXNFULL +// Description : None +#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB 4 +#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTS +// Description : Interrupt status after masking & forcing for irq1 +#define PIO_IRQ1_INTS_OFFSET 0x00000140 +#define PIO_IRQ1_INTS_BITS 0x00000fff +#define PIO_IRQ1_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3 +// Description : None +#define PIO_IRQ1_INTS_SM3_RESET 0x0 +#define PIO_IRQ1_INTS_SM3_BITS 0x00000800 +#define PIO_IRQ1_INTS_SM3_MSB 11 +#define PIO_IRQ1_INTS_SM3_LSB 11 +#define PIO_IRQ1_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2 +// Description : None +#define PIO_IRQ1_INTS_SM2_RESET 0x0 +#define PIO_IRQ1_INTS_SM2_BITS 0x00000400 +#define PIO_IRQ1_INTS_SM2_MSB 10 +#define PIO_IRQ1_INTS_SM2_LSB 10 +#define PIO_IRQ1_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1 +// Description : None +#define PIO_IRQ1_INTS_SM1_RESET 0x0 +#define PIO_IRQ1_INTS_SM1_BITS 0x00000200 +#define PIO_IRQ1_INTS_SM1_MSB 9 +#define PIO_IRQ1_INTS_SM1_LSB 9 +#define PIO_IRQ1_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0 +// Description : None +#define PIO_IRQ1_INTS_SM0_RESET 0x0 +#define PIO_IRQ1_INTS_SM0_BITS 0x00000100 +#define PIO_IRQ1_INTS_SM0_MSB 8 +#define PIO_IRQ1_INTS_SM0_LSB 8 +#define PIO_IRQ1_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS 0x00000080 +#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB 7 +#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB 7 +#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS 0x00000040 +#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB 6 +#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB 6 +#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS 0x00000020 +#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB 5 +#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB 5 +#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_TXNFULL +// Description : None +#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET 0x0 +#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS 0x00000010 +#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB 4 +#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB 4 +#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS 0x00000008 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB 3 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB 3 +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS 0x00000004 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB 2 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB 2 +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS 0x00000002 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB 1 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB 1 +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY +// Description : None +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET 0x0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS 0x00000001 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB 0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB 0 +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_PIO_DEFINED diff --git a/rp2040/hardware/regs/pll.h b/rp2040/hardware/regs/pll.h new file mode 100644 index 0000000..6a21d56 --- /dev/null +++ b/rp2040/hardware/regs/pll.h @@ -0,0 +1,135 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PLL +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PLL_DEFINED +#define HARDWARE_REGS_PLL_DEFINED +// ============================================================================= +// Register : PLL_CS +// Description : Control and Status +// GENERAL CONSTRAINTS: +// Reference clock frequency min=5MHz, max=800MHz +// Feedback divider min=16, max=320 +// VCO frequency min=400MHz, max=1600MHz +#define PLL_CS_OFFSET 0x00000000 +#define PLL_CS_BITS 0x8000013f +#define PLL_CS_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : PLL_CS_LOCK +// Description : PLL is locked +#define PLL_CS_LOCK_RESET 0x0 +#define PLL_CS_LOCK_BITS 0x80000000 +#define PLL_CS_LOCK_MSB 31 +#define PLL_CS_LOCK_LSB 31 +#define PLL_CS_LOCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_BYPASS +// Description : Passes the reference clock to the output instead of the divided +// VCO. The VCO continues to run so the user can switch between +// the reference clock and the divided VCO but the output will +// glitch when doing so. +#define PLL_CS_BYPASS_RESET 0x0 +#define PLL_CS_BYPASS_BITS 0x00000100 +#define PLL_CS_BYPASS_MSB 8 +#define PLL_CS_BYPASS_LSB 8 +#define PLL_CS_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_REFDIV +// Description : Divides the PLL input reference clock. +// Behaviour is undefined for div=0. +// PLL output will be unpredictable during refdiv changes, wait +// for lock=1 before using it. +#define PLL_CS_REFDIV_RESET 0x01 +#define PLL_CS_REFDIV_BITS 0x0000003f +#define PLL_CS_REFDIV_MSB 5 +#define PLL_CS_REFDIV_LSB 0 +#define PLL_CS_REFDIV_ACCESS "RW" +// ============================================================================= +// Register : PLL_PWR +// Description : Controls the PLL power modes. +#define PLL_PWR_OFFSET 0x00000004 +#define PLL_PWR_BITS 0x0000002d +#define PLL_PWR_RESET 0x0000002d +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_VCOPD +// Description : PLL VCO powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_VCOPD_RESET 0x1 +#define PLL_PWR_VCOPD_BITS 0x00000020 +#define PLL_PWR_VCOPD_MSB 5 +#define PLL_PWR_VCOPD_LSB 5 +#define PLL_PWR_VCOPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_POSTDIVPD +// Description : PLL post divider powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_POSTDIVPD_RESET 0x1 +#define PLL_PWR_POSTDIVPD_BITS 0x00000008 +#define PLL_PWR_POSTDIVPD_MSB 3 +#define PLL_PWR_POSTDIVPD_LSB 3 +#define PLL_PWR_POSTDIVPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_DSMPD +// Description : PLL DSM powerdown +// Nothing is achieved by setting this low. +#define PLL_PWR_DSMPD_RESET 0x1 +#define PLL_PWR_DSMPD_BITS 0x00000004 +#define PLL_PWR_DSMPD_MSB 2 +#define PLL_PWR_DSMPD_LSB 2 +#define PLL_PWR_DSMPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_PD +// Description : PLL powerdown +// To save power set high when PLL output not required. +#define PLL_PWR_PD_RESET 0x1 +#define PLL_PWR_PD_BITS 0x00000001 +#define PLL_PWR_PD_MSB 0 +#define PLL_PWR_PD_LSB 0 +#define PLL_PWR_PD_ACCESS "RW" +// ============================================================================= +// Register : PLL_FBDIV_INT +// Description : Feedback divisor +// (note: this PLL does not support fractional division) +// see ctrl reg description for constraints +#define PLL_FBDIV_INT_OFFSET 0x00000008 +#define PLL_FBDIV_INT_BITS 0x00000fff +#define PLL_FBDIV_INT_RESET 0x00000000 +#define PLL_FBDIV_INT_MSB 11 +#define PLL_FBDIV_INT_LSB 0 +#define PLL_FBDIV_INT_ACCESS "RW" +// ============================================================================= +// Register : PLL_PRIM +// Description : Controls the PLL post dividers for the primary output +// (note: this PLL does not have a secondary output) +// the primary output is driven from VCO divided by +// postdiv1*postdiv2 +#define PLL_PRIM_OFFSET 0x0000000c +#define PLL_PRIM_BITS 0x00077000 +#define PLL_PRIM_RESET 0x00077000 +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV1 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV1_RESET 0x7 +#define PLL_PRIM_POSTDIV1_BITS 0x00070000 +#define PLL_PRIM_POSTDIV1_MSB 18 +#define PLL_PRIM_POSTDIV1_LSB 16 +#define PLL_PRIM_POSTDIV1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV2 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV2_RESET 0x7 +#define PLL_PRIM_POSTDIV2_BITS 0x00007000 +#define PLL_PRIM_POSTDIV2_MSB 14 +#define PLL_PRIM_POSTDIV2_LSB 12 +#define PLL_PRIM_POSTDIV2_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_PLL_DEFINED diff --git a/rp2040/hardware/regs/psm.h b/rp2040/hardware/regs/psm.h new file mode 100644 index 0000000..dacf363 --- /dev/null +++ b/rp2040/hardware/regs/psm.h @@ -0,0 +1,584 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PSM +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_PSM_DEFINED +#define HARDWARE_REGS_PSM_DEFINED +// ============================================================================= +// Register : PSM_FRCE_ON +// Description : Force block out of reset (i.e. power it on) +#define PSM_FRCE_ON_OFFSET 0x00000000 +#define PSM_FRCE_ON_BITS 0x0001ffff +#define PSM_FRCE_ON_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC1 +// Description : None +#define PSM_FRCE_ON_PROC1_RESET 0x0 +#define PSM_FRCE_ON_PROC1_BITS 0x00010000 +#define PSM_FRCE_ON_PROC1_MSB 16 +#define PSM_FRCE_ON_PROC1_LSB 16 +#define PSM_FRCE_ON_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC0 +// Description : None +#define PSM_FRCE_ON_PROC0_RESET 0x0 +#define PSM_FRCE_ON_PROC0_BITS 0x00008000 +#define PSM_FRCE_ON_PROC0_MSB 15 +#define PSM_FRCE_ON_PROC0_LSB 15 +#define PSM_FRCE_ON_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SIO +// Description : None +#define PSM_FRCE_ON_SIO_RESET 0x0 +#define PSM_FRCE_ON_SIO_BITS 0x00004000 +#define PSM_FRCE_ON_SIO_MSB 14 +#define PSM_FRCE_ON_SIO_LSB 14 +#define PSM_FRCE_ON_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET +// Description : None +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XIP +// Description : None +#define PSM_FRCE_ON_XIP_RESET 0x0 +#define PSM_FRCE_ON_XIP_BITS 0x00001000 +#define PSM_FRCE_ON_XIP_MSB 12 +#define PSM_FRCE_ON_XIP_LSB 12 +#define PSM_FRCE_ON_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM5 +// Description : None +#define PSM_FRCE_ON_SRAM5_RESET 0x0 +#define PSM_FRCE_ON_SRAM5_BITS 0x00000800 +#define PSM_FRCE_ON_SRAM5_MSB 11 +#define PSM_FRCE_ON_SRAM5_LSB 11 +#define PSM_FRCE_ON_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM4 +// Description : None +#define PSM_FRCE_ON_SRAM4_RESET 0x0 +#define PSM_FRCE_ON_SRAM4_BITS 0x00000400 +#define PSM_FRCE_ON_SRAM4_MSB 10 +#define PSM_FRCE_ON_SRAM4_LSB 10 +#define PSM_FRCE_ON_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM3 +// Description : None +#define PSM_FRCE_ON_SRAM3_RESET 0x0 +#define PSM_FRCE_ON_SRAM3_BITS 0x00000200 +#define PSM_FRCE_ON_SRAM3_MSB 9 +#define PSM_FRCE_ON_SRAM3_LSB 9 +#define PSM_FRCE_ON_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM2 +// Description : None +#define PSM_FRCE_ON_SRAM2_RESET 0x0 +#define PSM_FRCE_ON_SRAM2_BITS 0x00000100 +#define PSM_FRCE_ON_SRAM2_MSB 8 +#define PSM_FRCE_ON_SRAM2_LSB 8 +#define PSM_FRCE_ON_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM1 +// Description : None +#define PSM_FRCE_ON_SRAM1_RESET 0x0 +#define PSM_FRCE_ON_SRAM1_BITS 0x00000080 +#define PSM_FRCE_ON_SRAM1_MSB 7 +#define PSM_FRCE_ON_SRAM1_LSB 7 +#define PSM_FRCE_ON_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM0 +// Description : None +#define PSM_FRCE_ON_SRAM0_RESET 0x0 +#define PSM_FRCE_ON_SRAM0_BITS 0x00000040 +#define PSM_FRCE_ON_SRAM0_MSB 6 +#define PSM_FRCE_ON_SRAM0_LSB 6 +#define PSM_FRCE_ON_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROM +// Description : None +#define PSM_FRCE_ON_ROM_RESET 0x0 +#define PSM_FRCE_ON_ROM_BITS 0x00000020 +#define PSM_FRCE_ON_ROM_MSB 5 +#define PSM_FRCE_ON_ROM_LSB 5 +#define PSM_FRCE_ON_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_BUSFABRIC +// Description : None +#define PSM_FRCE_ON_BUSFABRIC_RESET 0x0 +#define PSM_FRCE_ON_BUSFABRIC_BITS 0x00000010 +#define PSM_FRCE_ON_BUSFABRIC_MSB 4 +#define PSM_FRCE_ON_BUSFABRIC_LSB 4 +#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_RESETS +// Description : None +#define PSM_FRCE_ON_RESETS_RESET 0x0 +#define PSM_FRCE_ON_RESETS_BITS 0x00000008 +#define PSM_FRCE_ON_RESETS_MSB 3 +#define PSM_FRCE_ON_RESETS_LSB 3 +#define PSM_FRCE_ON_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_CLOCKS +// Description : None +#define PSM_FRCE_ON_CLOCKS_RESET 0x0 +#define PSM_FRCE_ON_CLOCKS_BITS 0x00000004 +#define PSM_FRCE_ON_CLOCKS_MSB 2 +#define PSM_FRCE_ON_CLOCKS_LSB 2 +#define PSM_FRCE_ON_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XOSC +// Description : None +#define PSM_FRCE_ON_XOSC_RESET 0x0 +#define PSM_FRCE_ON_XOSC_BITS 0x00000002 +#define PSM_FRCE_ON_XOSC_MSB 1 +#define PSM_FRCE_ON_XOSC_LSB 1 +#define PSM_FRCE_ON_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROSC +// Description : None +#define PSM_FRCE_ON_ROSC_RESET 0x0 +#define PSM_FRCE_ON_ROSC_BITS 0x00000001 +#define PSM_FRCE_ON_ROSC_MSB 0 +#define PSM_FRCE_ON_ROSC_LSB 0 +#define PSM_FRCE_ON_ROSC_ACCESS "RW" +// ============================================================================= +// Register : PSM_FRCE_OFF +// Description : Force into reset (i.e. power it off) +#define PSM_FRCE_OFF_OFFSET 0x00000004 +#define PSM_FRCE_OFF_BITS 0x0001ffff +#define PSM_FRCE_OFF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC1 +// Description : None +#define PSM_FRCE_OFF_PROC1_RESET 0x0 +#define PSM_FRCE_OFF_PROC1_BITS 0x00010000 +#define PSM_FRCE_OFF_PROC1_MSB 16 +#define PSM_FRCE_OFF_PROC1_LSB 16 +#define PSM_FRCE_OFF_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC0 +// Description : None +#define PSM_FRCE_OFF_PROC0_RESET 0x0 +#define PSM_FRCE_OFF_PROC0_BITS 0x00008000 +#define PSM_FRCE_OFF_PROC0_MSB 15 +#define PSM_FRCE_OFF_PROC0_LSB 15 +#define PSM_FRCE_OFF_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SIO +// Description : None +#define PSM_FRCE_OFF_SIO_RESET 0x0 +#define PSM_FRCE_OFF_SIO_BITS 0x00004000 +#define PSM_FRCE_OFF_SIO_MSB 14 +#define PSM_FRCE_OFF_SIO_LSB 14 +#define PSM_FRCE_OFF_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET +// Description : None +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XIP +// Description : None +#define PSM_FRCE_OFF_XIP_RESET 0x0 +#define PSM_FRCE_OFF_XIP_BITS 0x00001000 +#define PSM_FRCE_OFF_XIP_MSB 12 +#define PSM_FRCE_OFF_XIP_LSB 12 +#define PSM_FRCE_OFF_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM5 +// Description : None +#define PSM_FRCE_OFF_SRAM5_RESET 0x0 +#define PSM_FRCE_OFF_SRAM5_BITS 0x00000800 +#define PSM_FRCE_OFF_SRAM5_MSB 11 +#define PSM_FRCE_OFF_SRAM5_LSB 11 +#define PSM_FRCE_OFF_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM4 +// Description : None +#define PSM_FRCE_OFF_SRAM4_RESET 0x0 +#define PSM_FRCE_OFF_SRAM4_BITS 0x00000400 +#define PSM_FRCE_OFF_SRAM4_MSB 10 +#define PSM_FRCE_OFF_SRAM4_LSB 10 +#define PSM_FRCE_OFF_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM3 +// Description : None +#define PSM_FRCE_OFF_SRAM3_RESET 0x0 +#define PSM_FRCE_OFF_SRAM3_BITS 0x00000200 +#define PSM_FRCE_OFF_SRAM3_MSB 9 +#define PSM_FRCE_OFF_SRAM3_LSB 9 +#define PSM_FRCE_OFF_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM2 +// Description : None +#define PSM_FRCE_OFF_SRAM2_RESET 0x0 +#define PSM_FRCE_OFF_SRAM2_BITS 0x00000100 +#define PSM_FRCE_OFF_SRAM2_MSB 8 +#define PSM_FRCE_OFF_SRAM2_LSB 8 +#define PSM_FRCE_OFF_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM1 +// Description : None +#define PSM_FRCE_OFF_SRAM1_RESET 0x0 +#define PSM_FRCE_OFF_SRAM1_BITS 0x00000080 +#define PSM_FRCE_OFF_SRAM1_MSB 7 +#define PSM_FRCE_OFF_SRAM1_LSB 7 +#define PSM_FRCE_OFF_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM0 +// Description : None +#define PSM_FRCE_OFF_SRAM0_RESET 0x0 +#define PSM_FRCE_OFF_SRAM0_BITS 0x00000040 +#define PSM_FRCE_OFF_SRAM0_MSB 6 +#define PSM_FRCE_OFF_SRAM0_LSB 6 +#define PSM_FRCE_OFF_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROM +// Description : None +#define PSM_FRCE_OFF_ROM_RESET 0x0 +#define PSM_FRCE_OFF_ROM_BITS 0x00000020 +#define PSM_FRCE_OFF_ROM_MSB 5 +#define PSM_FRCE_OFF_ROM_LSB 5 +#define PSM_FRCE_OFF_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_BUSFABRIC +// Description : None +#define PSM_FRCE_OFF_BUSFABRIC_RESET 0x0 +#define PSM_FRCE_OFF_BUSFABRIC_BITS 0x00000010 +#define PSM_FRCE_OFF_BUSFABRIC_MSB 4 +#define PSM_FRCE_OFF_BUSFABRIC_LSB 4 +#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_RESETS +// Description : None +#define PSM_FRCE_OFF_RESETS_RESET 0x0 +#define PSM_FRCE_OFF_RESETS_BITS 0x00000008 +#define PSM_FRCE_OFF_RESETS_MSB 3 +#define PSM_FRCE_OFF_RESETS_LSB 3 +#define PSM_FRCE_OFF_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_CLOCKS +// Description : None +#define PSM_FRCE_OFF_CLOCKS_RESET 0x0 +#define PSM_FRCE_OFF_CLOCKS_BITS 0x00000004 +#define PSM_FRCE_OFF_CLOCKS_MSB 2 +#define PSM_FRCE_OFF_CLOCKS_LSB 2 +#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XOSC +// Description : None +#define PSM_FRCE_OFF_XOSC_RESET 0x0 +#define PSM_FRCE_OFF_XOSC_BITS 0x00000002 +#define PSM_FRCE_OFF_XOSC_MSB 1 +#define PSM_FRCE_OFF_XOSC_LSB 1 +#define PSM_FRCE_OFF_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROSC +// Description : None +#define PSM_FRCE_OFF_ROSC_RESET 0x0 +#define PSM_FRCE_OFF_ROSC_BITS 0x00000001 +#define PSM_FRCE_OFF_ROSC_MSB 0 +#define PSM_FRCE_OFF_ROSC_LSB 0 +#define PSM_FRCE_OFF_ROSC_ACCESS "RW" +// ============================================================================= +// Register : PSM_WDSEL +// Description : Set to 1 if this peripheral should be reset when the watchdog +// fires. +#define PSM_WDSEL_OFFSET 0x00000008 +#define PSM_WDSEL_BITS 0x0001ffff +#define PSM_WDSEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC1 +// Description : None +#define PSM_WDSEL_PROC1_RESET 0x0 +#define PSM_WDSEL_PROC1_BITS 0x00010000 +#define PSM_WDSEL_PROC1_MSB 16 +#define PSM_WDSEL_PROC1_LSB 16 +#define PSM_WDSEL_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC0 +// Description : None +#define PSM_WDSEL_PROC0_RESET 0x0 +#define PSM_WDSEL_PROC0_BITS 0x00008000 +#define PSM_WDSEL_PROC0_MSB 15 +#define PSM_WDSEL_PROC0_LSB 15 +#define PSM_WDSEL_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SIO +// Description : None +#define PSM_WDSEL_SIO_RESET 0x0 +#define PSM_WDSEL_SIO_BITS 0x00004000 +#define PSM_WDSEL_SIO_MSB 14 +#define PSM_WDSEL_SIO_LSB 14 +#define PSM_WDSEL_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_VREG_AND_CHIP_RESET +// Description : None +#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XIP +// Description : None +#define PSM_WDSEL_XIP_RESET 0x0 +#define PSM_WDSEL_XIP_BITS 0x00001000 +#define PSM_WDSEL_XIP_MSB 12 +#define PSM_WDSEL_XIP_LSB 12 +#define PSM_WDSEL_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM5 +// Description : None +#define PSM_WDSEL_SRAM5_RESET 0x0 +#define PSM_WDSEL_SRAM5_BITS 0x00000800 +#define PSM_WDSEL_SRAM5_MSB 11 +#define PSM_WDSEL_SRAM5_LSB 11 +#define PSM_WDSEL_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM4 +// Description : None +#define PSM_WDSEL_SRAM4_RESET 0x0 +#define PSM_WDSEL_SRAM4_BITS 0x00000400 +#define PSM_WDSEL_SRAM4_MSB 10 +#define PSM_WDSEL_SRAM4_LSB 10 +#define PSM_WDSEL_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM3 +// Description : None +#define PSM_WDSEL_SRAM3_RESET 0x0 +#define PSM_WDSEL_SRAM3_BITS 0x00000200 +#define PSM_WDSEL_SRAM3_MSB 9 +#define PSM_WDSEL_SRAM3_LSB 9 +#define PSM_WDSEL_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM2 +// Description : None +#define PSM_WDSEL_SRAM2_RESET 0x0 +#define PSM_WDSEL_SRAM2_BITS 0x00000100 +#define PSM_WDSEL_SRAM2_MSB 8 +#define PSM_WDSEL_SRAM2_LSB 8 +#define PSM_WDSEL_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM1 +// Description : None +#define PSM_WDSEL_SRAM1_RESET 0x0 +#define PSM_WDSEL_SRAM1_BITS 0x00000080 +#define PSM_WDSEL_SRAM1_MSB 7 +#define PSM_WDSEL_SRAM1_LSB 7 +#define PSM_WDSEL_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM0 +// Description : None +#define PSM_WDSEL_SRAM0_RESET 0x0 +#define PSM_WDSEL_SRAM0_BITS 0x00000040 +#define PSM_WDSEL_SRAM0_MSB 6 +#define PSM_WDSEL_SRAM0_LSB 6 +#define PSM_WDSEL_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROM +// Description : None +#define PSM_WDSEL_ROM_RESET 0x0 +#define PSM_WDSEL_ROM_BITS 0x00000020 +#define PSM_WDSEL_ROM_MSB 5 +#define PSM_WDSEL_ROM_LSB 5 +#define PSM_WDSEL_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_BUSFABRIC +// Description : None +#define PSM_WDSEL_BUSFABRIC_RESET 0x0 +#define PSM_WDSEL_BUSFABRIC_BITS 0x00000010 +#define PSM_WDSEL_BUSFABRIC_MSB 4 +#define PSM_WDSEL_BUSFABRIC_LSB 4 +#define PSM_WDSEL_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_RESETS +// Description : None +#define PSM_WDSEL_RESETS_RESET 0x0 +#define PSM_WDSEL_RESETS_BITS 0x00000008 +#define PSM_WDSEL_RESETS_MSB 3 +#define PSM_WDSEL_RESETS_LSB 3 +#define PSM_WDSEL_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_CLOCKS +// Description : None +#define PSM_WDSEL_CLOCKS_RESET 0x0 +#define PSM_WDSEL_CLOCKS_BITS 0x00000004 +#define PSM_WDSEL_CLOCKS_MSB 2 +#define PSM_WDSEL_CLOCKS_LSB 2 +#define PSM_WDSEL_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XOSC +// Description : None +#define PSM_WDSEL_XOSC_RESET 0x0 +#define PSM_WDSEL_XOSC_BITS 0x00000002 +#define PSM_WDSEL_XOSC_MSB 1 +#define PSM_WDSEL_XOSC_LSB 1 +#define PSM_WDSEL_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROSC +// Description : None +#define PSM_WDSEL_ROSC_RESET 0x0 +#define PSM_WDSEL_ROSC_BITS 0x00000001 +#define PSM_WDSEL_ROSC_MSB 0 +#define PSM_WDSEL_ROSC_LSB 0 +#define PSM_WDSEL_ROSC_ACCESS "RW" +// ============================================================================= +// Register : PSM_DONE +// Description : Indicates the peripheral's registers are ready to access. +#define PSM_DONE_OFFSET 0x0000000c +#define PSM_DONE_BITS 0x0001ffff +#define PSM_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC1 +// Description : None +#define PSM_DONE_PROC1_RESET 0x0 +#define PSM_DONE_PROC1_BITS 0x00010000 +#define PSM_DONE_PROC1_MSB 16 +#define PSM_DONE_PROC1_LSB 16 +#define PSM_DONE_PROC1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC0 +// Description : None +#define PSM_DONE_PROC0_RESET 0x0 +#define PSM_DONE_PROC0_BITS 0x00008000 +#define PSM_DONE_PROC0_MSB 15 +#define PSM_DONE_PROC0_LSB 15 +#define PSM_DONE_PROC0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SIO +// Description : None +#define PSM_DONE_SIO_RESET 0x0 +#define PSM_DONE_SIO_BITS 0x00004000 +#define PSM_DONE_SIO_MSB 14 +#define PSM_DONE_SIO_LSB 14 +#define PSM_DONE_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_VREG_AND_CHIP_RESET +// Description : None +#define PSM_DONE_VREG_AND_CHIP_RESET_RESET 0x0 +#define PSM_DONE_VREG_AND_CHIP_RESET_BITS 0x00002000 +#define PSM_DONE_VREG_AND_CHIP_RESET_MSB 13 +#define PSM_DONE_VREG_AND_CHIP_RESET_LSB 13 +#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XIP +// Description : None +#define PSM_DONE_XIP_RESET 0x0 +#define PSM_DONE_XIP_BITS 0x00001000 +#define PSM_DONE_XIP_MSB 12 +#define PSM_DONE_XIP_LSB 12 +#define PSM_DONE_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM5 +// Description : None +#define PSM_DONE_SRAM5_RESET 0x0 +#define PSM_DONE_SRAM5_BITS 0x00000800 +#define PSM_DONE_SRAM5_MSB 11 +#define PSM_DONE_SRAM5_LSB 11 +#define PSM_DONE_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM4 +// Description : None +#define PSM_DONE_SRAM4_RESET 0x0 +#define PSM_DONE_SRAM4_BITS 0x00000400 +#define PSM_DONE_SRAM4_MSB 10 +#define PSM_DONE_SRAM4_LSB 10 +#define PSM_DONE_SRAM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM3 +// Description : None +#define PSM_DONE_SRAM3_RESET 0x0 +#define PSM_DONE_SRAM3_BITS 0x00000200 +#define PSM_DONE_SRAM3_MSB 9 +#define PSM_DONE_SRAM3_LSB 9 +#define PSM_DONE_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM2 +// Description : None +#define PSM_DONE_SRAM2_RESET 0x0 +#define PSM_DONE_SRAM2_BITS 0x00000100 +#define PSM_DONE_SRAM2_MSB 8 +#define PSM_DONE_SRAM2_LSB 8 +#define PSM_DONE_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM1 +// Description : None +#define PSM_DONE_SRAM1_RESET 0x0 +#define PSM_DONE_SRAM1_BITS 0x00000080 +#define PSM_DONE_SRAM1_MSB 7 +#define PSM_DONE_SRAM1_LSB 7 +#define PSM_DONE_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM0 +// Description : None +#define PSM_DONE_SRAM0_RESET 0x0 +#define PSM_DONE_SRAM0_BITS 0x00000040 +#define PSM_DONE_SRAM0_MSB 6 +#define PSM_DONE_SRAM0_LSB 6 +#define PSM_DONE_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROM +// Description : None +#define PSM_DONE_ROM_RESET 0x0 +#define PSM_DONE_ROM_BITS 0x00000020 +#define PSM_DONE_ROM_MSB 5 +#define PSM_DONE_ROM_LSB 5 +#define PSM_DONE_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_BUSFABRIC +// Description : None +#define PSM_DONE_BUSFABRIC_RESET 0x0 +#define PSM_DONE_BUSFABRIC_BITS 0x00000010 +#define PSM_DONE_BUSFABRIC_MSB 4 +#define PSM_DONE_BUSFABRIC_LSB 4 +#define PSM_DONE_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_RESETS +// Description : None +#define PSM_DONE_RESETS_RESET 0x0 +#define PSM_DONE_RESETS_BITS 0x00000008 +#define PSM_DONE_RESETS_MSB 3 +#define PSM_DONE_RESETS_LSB 3 +#define PSM_DONE_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_CLOCKS +// Description : None +#define PSM_DONE_CLOCKS_RESET 0x0 +#define PSM_DONE_CLOCKS_BITS 0x00000004 +#define PSM_DONE_CLOCKS_MSB 2 +#define PSM_DONE_CLOCKS_LSB 2 +#define PSM_DONE_CLOCKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XOSC +// Description : None +#define PSM_DONE_XOSC_RESET 0x0 +#define PSM_DONE_XOSC_BITS 0x00000002 +#define PSM_DONE_XOSC_MSB 1 +#define PSM_DONE_XOSC_LSB 1 +#define PSM_DONE_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROSC +// Description : None +#define PSM_DONE_ROSC_RESET 0x0 +#define PSM_DONE_ROSC_BITS 0x00000001 +#define PSM_DONE_ROSC_MSB 0 +#define PSM_DONE_ROSC_LSB 0 +#define PSM_DONE_ROSC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_PSM_DEFINED diff --git a/rp2040/hardware/regs/pwm.h b/rp2040/hardware/regs/pwm.h new file mode 100644 index 0000000..01e2e5c --- /dev/null +++ b/rp2040/hardware/regs/pwm.h @@ -0,0 +1,1505 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PWM +// Version : 1 +// Bus type : apb +// Description : Simple PWM +// ============================================================================= +#ifndef HARDWARE_REGS_PWM_DEFINED +#define HARDWARE_REGS_PWM_DEFINED +// ============================================================================= +// Register : PWM_CH0_CSR +// Description : Control and status register +#define PWM_CH0_CSR_OFFSET 0x00000000 +#define PWM_CH0_CSR_BITS 0x000000ff +#define PWM_CH0_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH0_CSR_PH_ADV_RESET 0x0 +#define PWM_CH0_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH0_CSR_PH_ADV_MSB 7 +#define PWM_CH0_CSR_PH_ADV_LSB 7 +#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH0_CSR_PH_RET_RESET 0x0 +#define PWM_CH0_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH0_CSR_PH_RET_MSB 6 +#define PWM_CH0_CSR_PH_RET_LSB 6 +#define PWM_CH0_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH0_CSR_DIVMODE_RESET 0x0 +#define PWM_CH0_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH0_CSR_DIVMODE_MSB 5 +#define PWM_CH0_CSR_DIVMODE_LSB 4 +#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_B_INV +// Description : Invert output B +#define PWM_CH0_CSR_B_INV_RESET 0x0 +#define PWM_CH0_CSR_B_INV_BITS 0x00000008 +#define PWM_CH0_CSR_B_INV_MSB 3 +#define PWM_CH0_CSR_B_INV_LSB 3 +#define PWM_CH0_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_A_INV +// Description : Invert output A +#define PWM_CH0_CSR_A_INV_RESET 0x0 +#define PWM_CH0_CSR_A_INV_BITS 0x00000004 +#define PWM_CH0_CSR_A_INV_MSB 2 +#define PWM_CH0_CSR_A_INV_LSB 2 +#define PWM_CH0_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH0_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH0_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH0_CSR_PH_CORRECT_MSB 1 +#define PWM_CH0_CSR_PH_CORRECT_LSB 1 +#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH0_CSR_EN_RESET 0x0 +#define PWM_CH0_CSR_EN_BITS 0x00000001 +#define PWM_CH0_CSR_EN_MSB 0 +#define PWM_CH0_CSR_EN_LSB 0 +#define PWM_CH0_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH0_DIV_OFFSET 0x00000004 +#define PWM_CH0_DIV_BITS 0x00000fff +#define PWM_CH0_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_INT +// Description : None +#define PWM_CH0_DIV_INT_RESET 0x01 +#define PWM_CH0_DIV_INT_BITS 0x00000ff0 +#define PWM_CH0_DIV_INT_MSB 11 +#define PWM_CH0_DIV_INT_LSB 4 +#define PWM_CH0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_FRAC +// Description : None +#define PWM_CH0_DIV_FRAC_RESET 0x0 +#define PWM_CH0_DIV_FRAC_BITS 0x0000000f +#define PWM_CH0_DIV_FRAC_MSB 3 +#define PWM_CH0_DIV_FRAC_LSB 0 +#define PWM_CH0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CTR +// Description : Direct access to the PWM counter +#define PWM_CH0_CTR_OFFSET 0x00000008 +#define PWM_CH0_CTR_BITS 0x0000ffff +#define PWM_CH0_CTR_RESET 0x00000000 +#define PWM_CH0_CTR_MSB 15 +#define PWM_CH0_CTR_LSB 0 +#define PWM_CH0_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CC +// Description : Counter compare values +#define PWM_CH0_CC_OFFSET 0x0000000c +#define PWM_CH0_CC_BITS 0xffffffff +#define PWM_CH0_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_B +// Description : None +#define PWM_CH0_CC_B_RESET 0x0000 +#define PWM_CH0_CC_B_BITS 0xffff0000 +#define PWM_CH0_CC_B_MSB 31 +#define PWM_CH0_CC_B_LSB 16 +#define PWM_CH0_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_A +// Description : None +#define PWM_CH0_CC_A_RESET 0x0000 +#define PWM_CH0_CC_A_BITS 0x0000ffff +#define PWM_CH0_CC_A_MSB 15 +#define PWM_CH0_CC_A_LSB 0 +#define PWM_CH0_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_TOP +// Description : Counter wrap value +#define PWM_CH0_TOP_OFFSET 0x00000010 +#define PWM_CH0_TOP_BITS 0x0000ffff +#define PWM_CH0_TOP_RESET 0x0000ffff +#define PWM_CH0_TOP_MSB 15 +#define PWM_CH0_TOP_LSB 0 +#define PWM_CH0_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CSR +// Description : Control and status register +#define PWM_CH1_CSR_OFFSET 0x00000014 +#define PWM_CH1_CSR_BITS 0x000000ff +#define PWM_CH1_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH1_CSR_PH_ADV_RESET 0x0 +#define PWM_CH1_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH1_CSR_PH_ADV_MSB 7 +#define PWM_CH1_CSR_PH_ADV_LSB 7 +#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH1_CSR_PH_RET_RESET 0x0 +#define PWM_CH1_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH1_CSR_PH_RET_MSB 6 +#define PWM_CH1_CSR_PH_RET_LSB 6 +#define PWM_CH1_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH1_CSR_DIVMODE_RESET 0x0 +#define PWM_CH1_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH1_CSR_DIVMODE_MSB 5 +#define PWM_CH1_CSR_DIVMODE_LSB 4 +#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_B_INV +// Description : Invert output B +#define PWM_CH1_CSR_B_INV_RESET 0x0 +#define PWM_CH1_CSR_B_INV_BITS 0x00000008 +#define PWM_CH1_CSR_B_INV_MSB 3 +#define PWM_CH1_CSR_B_INV_LSB 3 +#define PWM_CH1_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_A_INV +// Description : Invert output A +#define PWM_CH1_CSR_A_INV_RESET 0x0 +#define PWM_CH1_CSR_A_INV_BITS 0x00000004 +#define PWM_CH1_CSR_A_INV_MSB 2 +#define PWM_CH1_CSR_A_INV_LSB 2 +#define PWM_CH1_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH1_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH1_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH1_CSR_PH_CORRECT_MSB 1 +#define PWM_CH1_CSR_PH_CORRECT_LSB 1 +#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH1_CSR_EN_RESET 0x0 +#define PWM_CH1_CSR_EN_BITS 0x00000001 +#define PWM_CH1_CSR_EN_MSB 0 +#define PWM_CH1_CSR_EN_LSB 0 +#define PWM_CH1_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH1_DIV_OFFSET 0x00000018 +#define PWM_CH1_DIV_BITS 0x00000fff +#define PWM_CH1_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_INT +// Description : None +#define PWM_CH1_DIV_INT_RESET 0x01 +#define PWM_CH1_DIV_INT_BITS 0x00000ff0 +#define PWM_CH1_DIV_INT_MSB 11 +#define PWM_CH1_DIV_INT_LSB 4 +#define PWM_CH1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_FRAC +// Description : None +#define PWM_CH1_DIV_FRAC_RESET 0x0 +#define PWM_CH1_DIV_FRAC_BITS 0x0000000f +#define PWM_CH1_DIV_FRAC_MSB 3 +#define PWM_CH1_DIV_FRAC_LSB 0 +#define PWM_CH1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CTR +// Description : Direct access to the PWM counter +#define PWM_CH1_CTR_OFFSET 0x0000001c +#define PWM_CH1_CTR_BITS 0x0000ffff +#define PWM_CH1_CTR_RESET 0x00000000 +#define PWM_CH1_CTR_MSB 15 +#define PWM_CH1_CTR_LSB 0 +#define PWM_CH1_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CC +// Description : Counter compare values +#define PWM_CH1_CC_OFFSET 0x00000020 +#define PWM_CH1_CC_BITS 0xffffffff +#define PWM_CH1_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_B +// Description : None +#define PWM_CH1_CC_B_RESET 0x0000 +#define PWM_CH1_CC_B_BITS 0xffff0000 +#define PWM_CH1_CC_B_MSB 31 +#define PWM_CH1_CC_B_LSB 16 +#define PWM_CH1_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_A +// Description : None +#define PWM_CH1_CC_A_RESET 0x0000 +#define PWM_CH1_CC_A_BITS 0x0000ffff +#define PWM_CH1_CC_A_MSB 15 +#define PWM_CH1_CC_A_LSB 0 +#define PWM_CH1_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_TOP +// Description : Counter wrap value +#define PWM_CH1_TOP_OFFSET 0x00000024 +#define PWM_CH1_TOP_BITS 0x0000ffff +#define PWM_CH1_TOP_RESET 0x0000ffff +#define PWM_CH1_TOP_MSB 15 +#define PWM_CH1_TOP_LSB 0 +#define PWM_CH1_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CSR +// Description : Control and status register +#define PWM_CH2_CSR_OFFSET 0x00000028 +#define PWM_CH2_CSR_BITS 0x000000ff +#define PWM_CH2_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH2_CSR_PH_ADV_RESET 0x0 +#define PWM_CH2_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH2_CSR_PH_ADV_MSB 7 +#define PWM_CH2_CSR_PH_ADV_LSB 7 +#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH2_CSR_PH_RET_RESET 0x0 +#define PWM_CH2_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH2_CSR_PH_RET_MSB 6 +#define PWM_CH2_CSR_PH_RET_LSB 6 +#define PWM_CH2_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH2_CSR_DIVMODE_RESET 0x0 +#define PWM_CH2_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH2_CSR_DIVMODE_MSB 5 +#define PWM_CH2_CSR_DIVMODE_LSB 4 +#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_B_INV +// Description : Invert output B +#define PWM_CH2_CSR_B_INV_RESET 0x0 +#define PWM_CH2_CSR_B_INV_BITS 0x00000008 +#define PWM_CH2_CSR_B_INV_MSB 3 +#define PWM_CH2_CSR_B_INV_LSB 3 +#define PWM_CH2_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_A_INV +// Description : Invert output A +#define PWM_CH2_CSR_A_INV_RESET 0x0 +#define PWM_CH2_CSR_A_INV_BITS 0x00000004 +#define PWM_CH2_CSR_A_INV_MSB 2 +#define PWM_CH2_CSR_A_INV_LSB 2 +#define PWM_CH2_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH2_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH2_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH2_CSR_PH_CORRECT_MSB 1 +#define PWM_CH2_CSR_PH_CORRECT_LSB 1 +#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH2_CSR_EN_RESET 0x0 +#define PWM_CH2_CSR_EN_BITS 0x00000001 +#define PWM_CH2_CSR_EN_MSB 0 +#define PWM_CH2_CSR_EN_LSB 0 +#define PWM_CH2_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH2_DIV_OFFSET 0x0000002c +#define PWM_CH2_DIV_BITS 0x00000fff +#define PWM_CH2_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_INT +// Description : None +#define PWM_CH2_DIV_INT_RESET 0x01 +#define PWM_CH2_DIV_INT_BITS 0x00000ff0 +#define PWM_CH2_DIV_INT_MSB 11 +#define PWM_CH2_DIV_INT_LSB 4 +#define PWM_CH2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_FRAC +// Description : None +#define PWM_CH2_DIV_FRAC_RESET 0x0 +#define PWM_CH2_DIV_FRAC_BITS 0x0000000f +#define PWM_CH2_DIV_FRAC_MSB 3 +#define PWM_CH2_DIV_FRAC_LSB 0 +#define PWM_CH2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CTR +// Description : Direct access to the PWM counter +#define PWM_CH2_CTR_OFFSET 0x00000030 +#define PWM_CH2_CTR_BITS 0x0000ffff +#define PWM_CH2_CTR_RESET 0x00000000 +#define PWM_CH2_CTR_MSB 15 +#define PWM_CH2_CTR_LSB 0 +#define PWM_CH2_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CC +// Description : Counter compare values +#define PWM_CH2_CC_OFFSET 0x00000034 +#define PWM_CH2_CC_BITS 0xffffffff +#define PWM_CH2_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_B +// Description : None +#define PWM_CH2_CC_B_RESET 0x0000 +#define PWM_CH2_CC_B_BITS 0xffff0000 +#define PWM_CH2_CC_B_MSB 31 +#define PWM_CH2_CC_B_LSB 16 +#define PWM_CH2_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_A +// Description : None +#define PWM_CH2_CC_A_RESET 0x0000 +#define PWM_CH2_CC_A_BITS 0x0000ffff +#define PWM_CH2_CC_A_MSB 15 +#define PWM_CH2_CC_A_LSB 0 +#define PWM_CH2_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_TOP +// Description : Counter wrap value +#define PWM_CH2_TOP_OFFSET 0x00000038 +#define PWM_CH2_TOP_BITS 0x0000ffff +#define PWM_CH2_TOP_RESET 0x0000ffff +#define PWM_CH2_TOP_MSB 15 +#define PWM_CH2_TOP_LSB 0 +#define PWM_CH2_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CSR +// Description : Control and status register +#define PWM_CH3_CSR_OFFSET 0x0000003c +#define PWM_CH3_CSR_BITS 0x000000ff +#define PWM_CH3_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH3_CSR_PH_ADV_RESET 0x0 +#define PWM_CH3_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH3_CSR_PH_ADV_MSB 7 +#define PWM_CH3_CSR_PH_ADV_LSB 7 +#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH3_CSR_PH_RET_RESET 0x0 +#define PWM_CH3_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH3_CSR_PH_RET_MSB 6 +#define PWM_CH3_CSR_PH_RET_LSB 6 +#define PWM_CH3_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH3_CSR_DIVMODE_RESET 0x0 +#define PWM_CH3_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH3_CSR_DIVMODE_MSB 5 +#define PWM_CH3_CSR_DIVMODE_LSB 4 +#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_B_INV +// Description : Invert output B +#define PWM_CH3_CSR_B_INV_RESET 0x0 +#define PWM_CH3_CSR_B_INV_BITS 0x00000008 +#define PWM_CH3_CSR_B_INV_MSB 3 +#define PWM_CH3_CSR_B_INV_LSB 3 +#define PWM_CH3_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_A_INV +// Description : Invert output A +#define PWM_CH3_CSR_A_INV_RESET 0x0 +#define PWM_CH3_CSR_A_INV_BITS 0x00000004 +#define PWM_CH3_CSR_A_INV_MSB 2 +#define PWM_CH3_CSR_A_INV_LSB 2 +#define PWM_CH3_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH3_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH3_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH3_CSR_PH_CORRECT_MSB 1 +#define PWM_CH3_CSR_PH_CORRECT_LSB 1 +#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH3_CSR_EN_RESET 0x0 +#define PWM_CH3_CSR_EN_BITS 0x00000001 +#define PWM_CH3_CSR_EN_MSB 0 +#define PWM_CH3_CSR_EN_LSB 0 +#define PWM_CH3_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH3_DIV_OFFSET 0x00000040 +#define PWM_CH3_DIV_BITS 0x00000fff +#define PWM_CH3_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_INT +// Description : None +#define PWM_CH3_DIV_INT_RESET 0x01 +#define PWM_CH3_DIV_INT_BITS 0x00000ff0 +#define PWM_CH3_DIV_INT_MSB 11 +#define PWM_CH3_DIV_INT_LSB 4 +#define PWM_CH3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_FRAC +// Description : None +#define PWM_CH3_DIV_FRAC_RESET 0x0 +#define PWM_CH3_DIV_FRAC_BITS 0x0000000f +#define PWM_CH3_DIV_FRAC_MSB 3 +#define PWM_CH3_DIV_FRAC_LSB 0 +#define PWM_CH3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CTR +// Description : Direct access to the PWM counter +#define PWM_CH3_CTR_OFFSET 0x00000044 +#define PWM_CH3_CTR_BITS 0x0000ffff +#define PWM_CH3_CTR_RESET 0x00000000 +#define PWM_CH3_CTR_MSB 15 +#define PWM_CH3_CTR_LSB 0 +#define PWM_CH3_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CC +// Description : Counter compare values +#define PWM_CH3_CC_OFFSET 0x00000048 +#define PWM_CH3_CC_BITS 0xffffffff +#define PWM_CH3_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_B +// Description : None +#define PWM_CH3_CC_B_RESET 0x0000 +#define PWM_CH3_CC_B_BITS 0xffff0000 +#define PWM_CH3_CC_B_MSB 31 +#define PWM_CH3_CC_B_LSB 16 +#define PWM_CH3_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_A +// Description : None +#define PWM_CH3_CC_A_RESET 0x0000 +#define PWM_CH3_CC_A_BITS 0x0000ffff +#define PWM_CH3_CC_A_MSB 15 +#define PWM_CH3_CC_A_LSB 0 +#define PWM_CH3_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_TOP +// Description : Counter wrap value +#define PWM_CH3_TOP_OFFSET 0x0000004c +#define PWM_CH3_TOP_BITS 0x0000ffff +#define PWM_CH3_TOP_RESET 0x0000ffff +#define PWM_CH3_TOP_MSB 15 +#define PWM_CH3_TOP_LSB 0 +#define PWM_CH3_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CSR +// Description : Control and status register +#define PWM_CH4_CSR_OFFSET 0x00000050 +#define PWM_CH4_CSR_BITS 0x000000ff +#define PWM_CH4_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH4_CSR_PH_ADV_RESET 0x0 +#define PWM_CH4_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH4_CSR_PH_ADV_MSB 7 +#define PWM_CH4_CSR_PH_ADV_LSB 7 +#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH4_CSR_PH_RET_RESET 0x0 +#define PWM_CH4_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH4_CSR_PH_RET_MSB 6 +#define PWM_CH4_CSR_PH_RET_LSB 6 +#define PWM_CH4_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH4_CSR_DIVMODE_RESET 0x0 +#define PWM_CH4_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH4_CSR_DIVMODE_MSB 5 +#define PWM_CH4_CSR_DIVMODE_LSB 4 +#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_B_INV +// Description : Invert output B +#define PWM_CH4_CSR_B_INV_RESET 0x0 +#define PWM_CH4_CSR_B_INV_BITS 0x00000008 +#define PWM_CH4_CSR_B_INV_MSB 3 +#define PWM_CH4_CSR_B_INV_LSB 3 +#define PWM_CH4_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_A_INV +// Description : Invert output A +#define PWM_CH4_CSR_A_INV_RESET 0x0 +#define PWM_CH4_CSR_A_INV_BITS 0x00000004 +#define PWM_CH4_CSR_A_INV_MSB 2 +#define PWM_CH4_CSR_A_INV_LSB 2 +#define PWM_CH4_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH4_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH4_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH4_CSR_PH_CORRECT_MSB 1 +#define PWM_CH4_CSR_PH_CORRECT_LSB 1 +#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH4_CSR_EN_RESET 0x0 +#define PWM_CH4_CSR_EN_BITS 0x00000001 +#define PWM_CH4_CSR_EN_MSB 0 +#define PWM_CH4_CSR_EN_LSB 0 +#define PWM_CH4_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH4_DIV_OFFSET 0x00000054 +#define PWM_CH4_DIV_BITS 0x00000fff +#define PWM_CH4_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_INT +// Description : None +#define PWM_CH4_DIV_INT_RESET 0x01 +#define PWM_CH4_DIV_INT_BITS 0x00000ff0 +#define PWM_CH4_DIV_INT_MSB 11 +#define PWM_CH4_DIV_INT_LSB 4 +#define PWM_CH4_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_FRAC +// Description : None +#define PWM_CH4_DIV_FRAC_RESET 0x0 +#define PWM_CH4_DIV_FRAC_BITS 0x0000000f +#define PWM_CH4_DIV_FRAC_MSB 3 +#define PWM_CH4_DIV_FRAC_LSB 0 +#define PWM_CH4_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CTR +// Description : Direct access to the PWM counter +#define PWM_CH4_CTR_OFFSET 0x00000058 +#define PWM_CH4_CTR_BITS 0x0000ffff +#define PWM_CH4_CTR_RESET 0x00000000 +#define PWM_CH4_CTR_MSB 15 +#define PWM_CH4_CTR_LSB 0 +#define PWM_CH4_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CC +// Description : Counter compare values +#define PWM_CH4_CC_OFFSET 0x0000005c +#define PWM_CH4_CC_BITS 0xffffffff +#define PWM_CH4_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_B +// Description : None +#define PWM_CH4_CC_B_RESET 0x0000 +#define PWM_CH4_CC_B_BITS 0xffff0000 +#define PWM_CH4_CC_B_MSB 31 +#define PWM_CH4_CC_B_LSB 16 +#define PWM_CH4_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_A +// Description : None +#define PWM_CH4_CC_A_RESET 0x0000 +#define PWM_CH4_CC_A_BITS 0x0000ffff +#define PWM_CH4_CC_A_MSB 15 +#define PWM_CH4_CC_A_LSB 0 +#define PWM_CH4_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_TOP +// Description : Counter wrap value +#define PWM_CH4_TOP_OFFSET 0x00000060 +#define PWM_CH4_TOP_BITS 0x0000ffff +#define PWM_CH4_TOP_RESET 0x0000ffff +#define PWM_CH4_TOP_MSB 15 +#define PWM_CH4_TOP_LSB 0 +#define PWM_CH4_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CSR +// Description : Control and status register +#define PWM_CH5_CSR_OFFSET 0x00000064 +#define PWM_CH5_CSR_BITS 0x000000ff +#define PWM_CH5_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH5_CSR_PH_ADV_RESET 0x0 +#define PWM_CH5_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH5_CSR_PH_ADV_MSB 7 +#define PWM_CH5_CSR_PH_ADV_LSB 7 +#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH5_CSR_PH_RET_RESET 0x0 +#define PWM_CH5_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH5_CSR_PH_RET_MSB 6 +#define PWM_CH5_CSR_PH_RET_LSB 6 +#define PWM_CH5_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH5_CSR_DIVMODE_RESET 0x0 +#define PWM_CH5_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH5_CSR_DIVMODE_MSB 5 +#define PWM_CH5_CSR_DIVMODE_LSB 4 +#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_B_INV +// Description : Invert output B +#define PWM_CH5_CSR_B_INV_RESET 0x0 +#define PWM_CH5_CSR_B_INV_BITS 0x00000008 +#define PWM_CH5_CSR_B_INV_MSB 3 +#define PWM_CH5_CSR_B_INV_LSB 3 +#define PWM_CH5_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_A_INV +// Description : Invert output A +#define PWM_CH5_CSR_A_INV_RESET 0x0 +#define PWM_CH5_CSR_A_INV_BITS 0x00000004 +#define PWM_CH5_CSR_A_INV_MSB 2 +#define PWM_CH5_CSR_A_INV_LSB 2 +#define PWM_CH5_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH5_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH5_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH5_CSR_PH_CORRECT_MSB 1 +#define PWM_CH5_CSR_PH_CORRECT_LSB 1 +#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH5_CSR_EN_RESET 0x0 +#define PWM_CH5_CSR_EN_BITS 0x00000001 +#define PWM_CH5_CSR_EN_MSB 0 +#define PWM_CH5_CSR_EN_LSB 0 +#define PWM_CH5_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH5_DIV_OFFSET 0x00000068 +#define PWM_CH5_DIV_BITS 0x00000fff +#define PWM_CH5_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_INT +// Description : None +#define PWM_CH5_DIV_INT_RESET 0x01 +#define PWM_CH5_DIV_INT_BITS 0x00000ff0 +#define PWM_CH5_DIV_INT_MSB 11 +#define PWM_CH5_DIV_INT_LSB 4 +#define PWM_CH5_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_FRAC +// Description : None +#define PWM_CH5_DIV_FRAC_RESET 0x0 +#define PWM_CH5_DIV_FRAC_BITS 0x0000000f +#define PWM_CH5_DIV_FRAC_MSB 3 +#define PWM_CH5_DIV_FRAC_LSB 0 +#define PWM_CH5_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CTR +// Description : Direct access to the PWM counter +#define PWM_CH5_CTR_OFFSET 0x0000006c +#define PWM_CH5_CTR_BITS 0x0000ffff +#define PWM_CH5_CTR_RESET 0x00000000 +#define PWM_CH5_CTR_MSB 15 +#define PWM_CH5_CTR_LSB 0 +#define PWM_CH5_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CC +// Description : Counter compare values +#define PWM_CH5_CC_OFFSET 0x00000070 +#define PWM_CH5_CC_BITS 0xffffffff +#define PWM_CH5_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_B +// Description : None +#define PWM_CH5_CC_B_RESET 0x0000 +#define PWM_CH5_CC_B_BITS 0xffff0000 +#define PWM_CH5_CC_B_MSB 31 +#define PWM_CH5_CC_B_LSB 16 +#define PWM_CH5_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_A +// Description : None +#define PWM_CH5_CC_A_RESET 0x0000 +#define PWM_CH5_CC_A_BITS 0x0000ffff +#define PWM_CH5_CC_A_MSB 15 +#define PWM_CH5_CC_A_LSB 0 +#define PWM_CH5_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_TOP +// Description : Counter wrap value +#define PWM_CH5_TOP_OFFSET 0x00000074 +#define PWM_CH5_TOP_BITS 0x0000ffff +#define PWM_CH5_TOP_RESET 0x0000ffff +#define PWM_CH5_TOP_MSB 15 +#define PWM_CH5_TOP_LSB 0 +#define PWM_CH5_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CSR +// Description : Control and status register +#define PWM_CH6_CSR_OFFSET 0x00000078 +#define PWM_CH6_CSR_BITS 0x000000ff +#define PWM_CH6_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH6_CSR_PH_ADV_RESET 0x0 +#define PWM_CH6_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH6_CSR_PH_ADV_MSB 7 +#define PWM_CH6_CSR_PH_ADV_LSB 7 +#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH6_CSR_PH_RET_RESET 0x0 +#define PWM_CH6_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH6_CSR_PH_RET_MSB 6 +#define PWM_CH6_CSR_PH_RET_LSB 6 +#define PWM_CH6_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH6_CSR_DIVMODE_RESET 0x0 +#define PWM_CH6_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH6_CSR_DIVMODE_MSB 5 +#define PWM_CH6_CSR_DIVMODE_LSB 4 +#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_B_INV +// Description : Invert output B +#define PWM_CH6_CSR_B_INV_RESET 0x0 +#define PWM_CH6_CSR_B_INV_BITS 0x00000008 +#define PWM_CH6_CSR_B_INV_MSB 3 +#define PWM_CH6_CSR_B_INV_LSB 3 +#define PWM_CH6_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_A_INV +// Description : Invert output A +#define PWM_CH6_CSR_A_INV_RESET 0x0 +#define PWM_CH6_CSR_A_INV_BITS 0x00000004 +#define PWM_CH6_CSR_A_INV_MSB 2 +#define PWM_CH6_CSR_A_INV_LSB 2 +#define PWM_CH6_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH6_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH6_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH6_CSR_PH_CORRECT_MSB 1 +#define PWM_CH6_CSR_PH_CORRECT_LSB 1 +#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH6_CSR_EN_RESET 0x0 +#define PWM_CH6_CSR_EN_BITS 0x00000001 +#define PWM_CH6_CSR_EN_MSB 0 +#define PWM_CH6_CSR_EN_LSB 0 +#define PWM_CH6_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH6_DIV_OFFSET 0x0000007c +#define PWM_CH6_DIV_BITS 0x00000fff +#define PWM_CH6_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_INT +// Description : None +#define PWM_CH6_DIV_INT_RESET 0x01 +#define PWM_CH6_DIV_INT_BITS 0x00000ff0 +#define PWM_CH6_DIV_INT_MSB 11 +#define PWM_CH6_DIV_INT_LSB 4 +#define PWM_CH6_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_FRAC +// Description : None +#define PWM_CH6_DIV_FRAC_RESET 0x0 +#define PWM_CH6_DIV_FRAC_BITS 0x0000000f +#define PWM_CH6_DIV_FRAC_MSB 3 +#define PWM_CH6_DIV_FRAC_LSB 0 +#define PWM_CH6_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CTR +// Description : Direct access to the PWM counter +#define PWM_CH6_CTR_OFFSET 0x00000080 +#define PWM_CH6_CTR_BITS 0x0000ffff +#define PWM_CH6_CTR_RESET 0x00000000 +#define PWM_CH6_CTR_MSB 15 +#define PWM_CH6_CTR_LSB 0 +#define PWM_CH6_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CC +// Description : Counter compare values +#define PWM_CH6_CC_OFFSET 0x00000084 +#define PWM_CH6_CC_BITS 0xffffffff +#define PWM_CH6_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_B +// Description : None +#define PWM_CH6_CC_B_RESET 0x0000 +#define PWM_CH6_CC_B_BITS 0xffff0000 +#define PWM_CH6_CC_B_MSB 31 +#define PWM_CH6_CC_B_LSB 16 +#define PWM_CH6_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_A +// Description : None +#define PWM_CH6_CC_A_RESET 0x0000 +#define PWM_CH6_CC_A_BITS 0x0000ffff +#define PWM_CH6_CC_A_MSB 15 +#define PWM_CH6_CC_A_LSB 0 +#define PWM_CH6_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_TOP +// Description : Counter wrap value +#define PWM_CH6_TOP_OFFSET 0x00000088 +#define PWM_CH6_TOP_BITS 0x0000ffff +#define PWM_CH6_TOP_RESET 0x0000ffff +#define PWM_CH6_TOP_MSB 15 +#define PWM_CH6_TOP_LSB 0 +#define PWM_CH6_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CSR +// Description : Control and status register +#define PWM_CH7_CSR_OFFSET 0x0000008c +#define PWM_CH7_CSR_BITS 0x000000ff +#define PWM_CH7_CSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH7_CSR_PH_ADV_RESET 0x0 +#define PWM_CH7_CSR_PH_ADV_BITS 0x00000080 +#define PWM_CH7_CSR_PH_ADV_MSB 7 +#define PWM_CH7_CSR_PH_ADV_LSB 7 +#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH7_CSR_PH_RET_RESET 0x0 +#define PWM_CH7_CSR_PH_RET_BITS 0x00000040 +#define PWM_CH7_CSR_PH_RET_MSB 6 +#define PWM_CH7_CSR_PH_RET_LSB 6 +#define PWM_CH7_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_DIVMODE +// Description : 0x0 -> Free-running counting at rate dictated by fractional +// divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B +// pin. +#define PWM_CH7_CSR_DIVMODE_RESET 0x0 +#define PWM_CH7_CSR_DIVMODE_BITS 0x00000030 +#define PWM_CH7_CSR_DIVMODE_MSB 5 +#define PWM_CH7_CSR_DIVMODE_LSB 4 +#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV 0x0 +#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL 0x1 +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE 0x2 +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL 0x3 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_B_INV +// Description : Invert output B +#define PWM_CH7_CSR_B_INV_RESET 0x0 +#define PWM_CH7_CSR_B_INV_BITS 0x00000008 +#define PWM_CH7_CSR_B_INV_MSB 3 +#define PWM_CH7_CSR_B_INV_LSB 3 +#define PWM_CH7_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_A_INV +// Description : Invert output A +#define PWM_CH7_CSR_A_INV_RESET 0x0 +#define PWM_CH7_CSR_A_INV_BITS 0x00000004 +#define PWM_CH7_CSR_A_INV_MSB 2 +#define PWM_CH7_CSR_A_INV_LSB 2 +#define PWM_CH7_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH7_CSR_PH_CORRECT_RESET 0x0 +#define PWM_CH7_CSR_PH_CORRECT_BITS 0x00000002 +#define PWM_CH7_CSR_PH_CORRECT_MSB 1 +#define PWM_CH7_CSR_PH_CORRECT_LSB 1 +#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH7_CSR_EN_RESET 0x0 +#define PWM_CH7_CSR_EN_BITS 0x00000001 +#define PWM_CH7_CSR_EN_MSB 0 +#define PWM_CH7_CSR_EN_LSB 0 +#define PWM_CH7_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH7_DIV_OFFSET 0x00000090 +#define PWM_CH7_DIV_BITS 0x00000fff +#define PWM_CH7_DIV_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_INT +// Description : None +#define PWM_CH7_DIV_INT_RESET 0x01 +#define PWM_CH7_DIV_INT_BITS 0x00000ff0 +#define PWM_CH7_DIV_INT_MSB 11 +#define PWM_CH7_DIV_INT_LSB 4 +#define PWM_CH7_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_FRAC +// Description : None +#define PWM_CH7_DIV_FRAC_RESET 0x0 +#define PWM_CH7_DIV_FRAC_BITS 0x0000000f +#define PWM_CH7_DIV_FRAC_MSB 3 +#define PWM_CH7_DIV_FRAC_LSB 0 +#define PWM_CH7_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CTR +// Description : Direct access to the PWM counter +#define PWM_CH7_CTR_OFFSET 0x00000094 +#define PWM_CH7_CTR_BITS 0x0000ffff +#define PWM_CH7_CTR_RESET 0x00000000 +#define PWM_CH7_CTR_MSB 15 +#define PWM_CH7_CTR_LSB 0 +#define PWM_CH7_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CC +// Description : Counter compare values +#define PWM_CH7_CC_OFFSET 0x00000098 +#define PWM_CH7_CC_BITS 0xffffffff +#define PWM_CH7_CC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_B +// Description : None +#define PWM_CH7_CC_B_RESET 0x0000 +#define PWM_CH7_CC_B_BITS 0xffff0000 +#define PWM_CH7_CC_B_MSB 31 +#define PWM_CH7_CC_B_LSB 16 +#define PWM_CH7_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_A +// Description : None +#define PWM_CH7_CC_A_RESET 0x0000 +#define PWM_CH7_CC_A_BITS 0x0000ffff +#define PWM_CH7_CC_A_MSB 15 +#define PWM_CH7_CC_A_LSB 0 +#define PWM_CH7_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_TOP +// Description : Counter wrap value +#define PWM_CH7_TOP_OFFSET 0x0000009c +#define PWM_CH7_TOP_BITS 0x0000ffff +#define PWM_CH7_TOP_RESET 0x0000ffff +#define PWM_CH7_TOP_MSB 15 +#define PWM_CH7_TOP_LSB 0 +#define PWM_CH7_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_EN +// Description : This register aliases the CSR_EN bits for all channels. +// Writing to this register allows multiple channels to be enabled +// or disabled simultaneously, so they can run in perfect sync. +// For each channel, there is only one physical EN register bit, +// which can be accessed through here or CHx_CSR. +#define PWM_EN_OFFSET 0x000000a0 +#define PWM_EN_BITS 0x000000ff +#define PWM_EN_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH7 +// Description : None +#define PWM_EN_CH7_RESET 0x0 +#define PWM_EN_CH7_BITS 0x00000080 +#define PWM_EN_CH7_MSB 7 +#define PWM_EN_CH7_LSB 7 +#define PWM_EN_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH6 +// Description : None +#define PWM_EN_CH6_RESET 0x0 +#define PWM_EN_CH6_BITS 0x00000040 +#define PWM_EN_CH6_MSB 6 +#define PWM_EN_CH6_LSB 6 +#define PWM_EN_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH5 +// Description : None +#define PWM_EN_CH5_RESET 0x0 +#define PWM_EN_CH5_BITS 0x00000020 +#define PWM_EN_CH5_MSB 5 +#define PWM_EN_CH5_LSB 5 +#define PWM_EN_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH4 +// Description : None +#define PWM_EN_CH4_RESET 0x0 +#define PWM_EN_CH4_BITS 0x00000010 +#define PWM_EN_CH4_MSB 4 +#define PWM_EN_CH4_LSB 4 +#define PWM_EN_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH3 +// Description : None +#define PWM_EN_CH3_RESET 0x0 +#define PWM_EN_CH3_BITS 0x00000008 +#define PWM_EN_CH3_MSB 3 +#define PWM_EN_CH3_LSB 3 +#define PWM_EN_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH2 +// Description : None +#define PWM_EN_CH2_RESET 0x0 +#define PWM_EN_CH2_BITS 0x00000004 +#define PWM_EN_CH2_MSB 2 +#define PWM_EN_CH2_LSB 2 +#define PWM_EN_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH1 +// Description : None +#define PWM_EN_CH1_RESET 0x0 +#define PWM_EN_CH1_BITS 0x00000002 +#define PWM_EN_CH1_MSB 1 +#define PWM_EN_CH1_LSB 1 +#define PWM_EN_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH0 +// Description : None +#define PWM_EN_CH0_RESET 0x0 +#define PWM_EN_CH0_BITS 0x00000001 +#define PWM_EN_CH0_MSB 0 +#define PWM_EN_CH0_LSB 0 +#define PWM_EN_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTR +// Description : Raw Interrupts +#define PWM_INTR_OFFSET 0x000000a4 +#define PWM_INTR_BITS 0x000000ff +#define PWM_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH7 +// Description : None +#define PWM_INTR_CH7_RESET 0x0 +#define PWM_INTR_CH7_BITS 0x00000080 +#define PWM_INTR_CH7_MSB 7 +#define PWM_INTR_CH7_LSB 7 +#define PWM_INTR_CH7_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH6 +// Description : None +#define PWM_INTR_CH6_RESET 0x0 +#define PWM_INTR_CH6_BITS 0x00000040 +#define PWM_INTR_CH6_MSB 6 +#define PWM_INTR_CH6_LSB 6 +#define PWM_INTR_CH6_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH5 +// Description : None +#define PWM_INTR_CH5_RESET 0x0 +#define PWM_INTR_CH5_BITS 0x00000020 +#define PWM_INTR_CH5_MSB 5 +#define PWM_INTR_CH5_LSB 5 +#define PWM_INTR_CH5_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH4 +// Description : None +#define PWM_INTR_CH4_RESET 0x0 +#define PWM_INTR_CH4_BITS 0x00000010 +#define PWM_INTR_CH4_MSB 4 +#define PWM_INTR_CH4_LSB 4 +#define PWM_INTR_CH4_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH3 +// Description : None +#define PWM_INTR_CH3_RESET 0x0 +#define PWM_INTR_CH3_BITS 0x00000008 +#define PWM_INTR_CH3_MSB 3 +#define PWM_INTR_CH3_LSB 3 +#define PWM_INTR_CH3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH2 +// Description : None +#define PWM_INTR_CH2_RESET 0x0 +#define PWM_INTR_CH2_BITS 0x00000004 +#define PWM_INTR_CH2_MSB 2 +#define PWM_INTR_CH2_LSB 2 +#define PWM_INTR_CH2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH1 +// Description : None +#define PWM_INTR_CH1_RESET 0x0 +#define PWM_INTR_CH1_BITS 0x00000002 +#define PWM_INTR_CH1_MSB 1 +#define PWM_INTR_CH1_LSB 1 +#define PWM_INTR_CH1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH0 +// Description : None +#define PWM_INTR_CH0_RESET 0x0 +#define PWM_INTR_CH0_BITS 0x00000001 +#define PWM_INTR_CH0_MSB 0 +#define PWM_INTR_CH0_LSB 0 +#define PWM_INTR_CH0_ACCESS "WC" +// ============================================================================= +// Register : PWM_INTE +// Description : Interrupt Enable +#define PWM_INTE_OFFSET 0x000000a8 +#define PWM_INTE_BITS 0x000000ff +#define PWM_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH7 +// Description : None +#define PWM_INTE_CH7_RESET 0x0 +#define PWM_INTE_CH7_BITS 0x00000080 +#define PWM_INTE_CH7_MSB 7 +#define PWM_INTE_CH7_LSB 7 +#define PWM_INTE_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH6 +// Description : None +#define PWM_INTE_CH6_RESET 0x0 +#define PWM_INTE_CH6_BITS 0x00000040 +#define PWM_INTE_CH6_MSB 6 +#define PWM_INTE_CH6_LSB 6 +#define PWM_INTE_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH5 +// Description : None +#define PWM_INTE_CH5_RESET 0x0 +#define PWM_INTE_CH5_BITS 0x00000020 +#define PWM_INTE_CH5_MSB 5 +#define PWM_INTE_CH5_LSB 5 +#define PWM_INTE_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH4 +// Description : None +#define PWM_INTE_CH4_RESET 0x0 +#define PWM_INTE_CH4_BITS 0x00000010 +#define PWM_INTE_CH4_MSB 4 +#define PWM_INTE_CH4_LSB 4 +#define PWM_INTE_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH3 +// Description : None +#define PWM_INTE_CH3_RESET 0x0 +#define PWM_INTE_CH3_BITS 0x00000008 +#define PWM_INTE_CH3_MSB 3 +#define PWM_INTE_CH3_LSB 3 +#define PWM_INTE_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH2 +// Description : None +#define PWM_INTE_CH2_RESET 0x0 +#define PWM_INTE_CH2_BITS 0x00000004 +#define PWM_INTE_CH2_MSB 2 +#define PWM_INTE_CH2_LSB 2 +#define PWM_INTE_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH1 +// Description : None +#define PWM_INTE_CH1_RESET 0x0 +#define PWM_INTE_CH1_BITS 0x00000002 +#define PWM_INTE_CH1_MSB 1 +#define PWM_INTE_CH1_LSB 1 +#define PWM_INTE_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTE_CH0 +// Description : None +#define PWM_INTE_CH0_RESET 0x0 +#define PWM_INTE_CH0_BITS 0x00000001 +#define PWM_INTE_CH0_MSB 0 +#define PWM_INTE_CH0_LSB 0 +#define PWM_INTE_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTF +// Description : Interrupt Force +#define PWM_INTF_OFFSET 0x000000ac +#define PWM_INTF_BITS 0x000000ff +#define PWM_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH7 +// Description : None +#define PWM_INTF_CH7_RESET 0x0 +#define PWM_INTF_CH7_BITS 0x00000080 +#define PWM_INTF_CH7_MSB 7 +#define PWM_INTF_CH7_LSB 7 +#define PWM_INTF_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH6 +// Description : None +#define PWM_INTF_CH6_RESET 0x0 +#define PWM_INTF_CH6_BITS 0x00000040 +#define PWM_INTF_CH6_MSB 6 +#define PWM_INTF_CH6_LSB 6 +#define PWM_INTF_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH5 +// Description : None +#define PWM_INTF_CH5_RESET 0x0 +#define PWM_INTF_CH5_BITS 0x00000020 +#define PWM_INTF_CH5_MSB 5 +#define PWM_INTF_CH5_LSB 5 +#define PWM_INTF_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH4 +// Description : None +#define PWM_INTF_CH4_RESET 0x0 +#define PWM_INTF_CH4_BITS 0x00000010 +#define PWM_INTF_CH4_MSB 4 +#define PWM_INTF_CH4_LSB 4 +#define PWM_INTF_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH3 +// Description : None +#define PWM_INTF_CH3_RESET 0x0 +#define PWM_INTF_CH3_BITS 0x00000008 +#define PWM_INTF_CH3_MSB 3 +#define PWM_INTF_CH3_LSB 3 +#define PWM_INTF_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH2 +// Description : None +#define PWM_INTF_CH2_RESET 0x0 +#define PWM_INTF_CH2_BITS 0x00000004 +#define PWM_INTF_CH2_MSB 2 +#define PWM_INTF_CH2_LSB 2 +#define PWM_INTF_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH1 +// Description : None +#define PWM_INTF_CH1_RESET 0x0 +#define PWM_INTF_CH1_BITS 0x00000002 +#define PWM_INTF_CH1_MSB 1 +#define PWM_INTF_CH1_LSB 1 +#define PWM_INTF_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_INTF_CH0 +// Description : None +#define PWM_INTF_CH0_RESET 0x0 +#define PWM_INTF_CH0_BITS 0x00000001 +#define PWM_INTF_CH0_MSB 0 +#define PWM_INTF_CH0_LSB 0 +#define PWM_INTF_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTS +// Description : Interrupt status after masking & forcing +#define PWM_INTS_OFFSET 0x000000b0 +#define PWM_INTS_BITS 0x000000ff +#define PWM_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH7 +// Description : None +#define PWM_INTS_CH7_RESET 0x0 +#define PWM_INTS_CH7_BITS 0x00000080 +#define PWM_INTS_CH7_MSB 7 +#define PWM_INTS_CH7_LSB 7 +#define PWM_INTS_CH7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH6 +// Description : None +#define PWM_INTS_CH6_RESET 0x0 +#define PWM_INTS_CH6_BITS 0x00000040 +#define PWM_INTS_CH6_MSB 6 +#define PWM_INTS_CH6_LSB 6 +#define PWM_INTS_CH6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH5 +// Description : None +#define PWM_INTS_CH5_RESET 0x0 +#define PWM_INTS_CH5_BITS 0x00000020 +#define PWM_INTS_CH5_MSB 5 +#define PWM_INTS_CH5_LSB 5 +#define PWM_INTS_CH5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH4 +// Description : None +#define PWM_INTS_CH4_RESET 0x0 +#define PWM_INTS_CH4_BITS 0x00000010 +#define PWM_INTS_CH4_MSB 4 +#define PWM_INTS_CH4_LSB 4 +#define PWM_INTS_CH4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH3 +// Description : None +#define PWM_INTS_CH3_RESET 0x0 +#define PWM_INTS_CH3_BITS 0x00000008 +#define PWM_INTS_CH3_MSB 3 +#define PWM_INTS_CH3_LSB 3 +#define PWM_INTS_CH3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH2 +// Description : None +#define PWM_INTS_CH2_RESET 0x0 +#define PWM_INTS_CH2_BITS 0x00000004 +#define PWM_INTS_CH2_MSB 2 +#define PWM_INTS_CH2_LSB 2 +#define PWM_INTS_CH2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH1 +// Description : None +#define PWM_INTS_CH1_RESET 0x0 +#define PWM_INTS_CH1_BITS 0x00000002 +#define PWM_INTS_CH1_MSB 1 +#define PWM_INTS_CH1_LSB 1 +#define PWM_INTS_CH1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_INTS_CH0 +// Description : None +#define PWM_INTS_CH0_RESET 0x0 +#define PWM_INTS_CH0_BITS 0x00000001 +#define PWM_INTS_CH0_MSB 0 +#define PWM_INTS_CH0_LSB 0 +#define PWM_INTS_CH0_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_PWM_DEFINED diff --git a/rp2040/hardware/regs/resets.h b/rp2040/hardware/regs/resets.h new file mode 100644 index 0000000..b512350 --- /dev/null +++ b/rp2040/hardware/regs/resets.h @@ -0,0 +1,637 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RESETS +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_RESETS_DEFINED +#define HARDWARE_REGS_RESETS_DEFINED +// ============================================================================= +// Register : RESETS_RESET +// Description : Reset control. If a bit is set it means the peripheral is in +// reset. 0 means the peripheral's reset is deasserted. +#define RESETS_RESET_OFFSET 0x00000000 +#define RESETS_RESET_BITS 0x01ffffff +#define RESETS_RESET_RESET 0x01ffffff +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_USBCTRL +// Description : None +#define RESETS_RESET_USBCTRL_RESET 0x1 +#define RESETS_RESET_USBCTRL_BITS 0x01000000 +#define RESETS_RESET_USBCTRL_MSB 24 +#define RESETS_RESET_USBCTRL_LSB 24 +#define RESETS_RESET_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART1 +// Description : None +#define RESETS_RESET_UART1_RESET 0x1 +#define RESETS_RESET_UART1_BITS 0x00800000 +#define RESETS_RESET_UART1_MSB 23 +#define RESETS_RESET_UART1_LSB 23 +#define RESETS_RESET_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART0 +// Description : None +#define RESETS_RESET_UART0_RESET 0x1 +#define RESETS_RESET_UART0_BITS 0x00400000 +#define RESETS_RESET_UART0_MSB 22 +#define RESETS_RESET_UART0_LSB 22 +#define RESETS_RESET_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TIMER +// Description : None +#define RESETS_RESET_TIMER_RESET 0x1 +#define RESETS_RESET_TIMER_BITS 0x00200000 +#define RESETS_RESET_TIMER_MSB 21 +#define RESETS_RESET_TIMER_LSB 21 +#define RESETS_RESET_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TBMAN +// Description : None +#define RESETS_RESET_TBMAN_RESET 0x1 +#define RESETS_RESET_TBMAN_BITS 0x00100000 +#define RESETS_RESET_TBMAN_MSB 20 +#define RESETS_RESET_TBMAN_LSB 20 +#define RESETS_RESET_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSINFO +// Description : None +#define RESETS_RESET_SYSINFO_RESET 0x1 +#define RESETS_RESET_SYSINFO_BITS 0x00080000 +#define RESETS_RESET_SYSINFO_MSB 19 +#define RESETS_RESET_SYSINFO_LSB 19 +#define RESETS_RESET_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSCFG +// Description : None +#define RESETS_RESET_SYSCFG_RESET 0x1 +#define RESETS_RESET_SYSCFG_BITS 0x00040000 +#define RESETS_RESET_SYSCFG_MSB 18 +#define RESETS_RESET_SYSCFG_LSB 18 +#define RESETS_RESET_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI1 +// Description : None +#define RESETS_RESET_SPI1_RESET 0x1 +#define RESETS_RESET_SPI1_BITS 0x00020000 +#define RESETS_RESET_SPI1_MSB 17 +#define RESETS_RESET_SPI1_LSB 17 +#define RESETS_RESET_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI0 +// Description : None +#define RESETS_RESET_SPI0_RESET 0x1 +#define RESETS_RESET_SPI0_BITS 0x00010000 +#define RESETS_RESET_SPI0_MSB 16 +#define RESETS_RESET_SPI0_LSB 16 +#define RESETS_RESET_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_RTC +// Description : None +#define RESETS_RESET_RTC_RESET 0x1 +#define RESETS_RESET_RTC_BITS 0x00008000 +#define RESETS_RESET_RTC_MSB 15 +#define RESETS_RESET_RTC_LSB 15 +#define RESETS_RESET_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PWM +// Description : None +#define RESETS_RESET_PWM_RESET 0x1 +#define RESETS_RESET_PWM_BITS 0x00004000 +#define RESETS_RESET_PWM_MSB 14 +#define RESETS_RESET_PWM_LSB 14 +#define RESETS_RESET_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_USB +// Description : None +#define RESETS_RESET_PLL_USB_RESET 0x1 +#define RESETS_RESET_PLL_USB_BITS 0x00002000 +#define RESETS_RESET_PLL_USB_MSB 13 +#define RESETS_RESET_PLL_USB_LSB 13 +#define RESETS_RESET_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_SYS +// Description : None +#define RESETS_RESET_PLL_SYS_RESET 0x1 +#define RESETS_RESET_PLL_SYS_BITS 0x00001000 +#define RESETS_RESET_PLL_SYS_MSB 12 +#define RESETS_RESET_PLL_SYS_LSB 12 +#define RESETS_RESET_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO1 +// Description : None +#define RESETS_RESET_PIO1_RESET 0x1 +#define RESETS_RESET_PIO1_BITS 0x00000800 +#define RESETS_RESET_PIO1_MSB 11 +#define RESETS_RESET_PIO1_LSB 11 +#define RESETS_RESET_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO0 +// Description : None +#define RESETS_RESET_PIO0_RESET 0x1 +#define RESETS_RESET_PIO0_BITS 0x00000400 +#define RESETS_RESET_PIO0_MSB 10 +#define RESETS_RESET_PIO0_LSB 10 +#define RESETS_RESET_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_QSPI +// Description : None +#define RESETS_RESET_PADS_QSPI_RESET 0x1 +#define RESETS_RESET_PADS_QSPI_BITS 0x00000200 +#define RESETS_RESET_PADS_QSPI_MSB 9 +#define RESETS_RESET_PADS_QSPI_LSB 9 +#define RESETS_RESET_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_BANK0 +// Description : None +#define RESETS_RESET_PADS_BANK0_RESET 0x1 +#define RESETS_RESET_PADS_BANK0_BITS 0x00000100 +#define RESETS_RESET_PADS_BANK0_MSB 8 +#define RESETS_RESET_PADS_BANK0_LSB 8 +#define RESETS_RESET_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_JTAG +// Description : None +#define RESETS_RESET_JTAG_RESET 0x1 +#define RESETS_RESET_JTAG_BITS 0x00000080 +#define RESETS_RESET_JTAG_MSB 7 +#define RESETS_RESET_JTAG_LSB 7 +#define RESETS_RESET_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_QSPI +// Description : None +#define RESETS_RESET_IO_QSPI_RESET 0x1 +#define RESETS_RESET_IO_QSPI_BITS 0x00000040 +#define RESETS_RESET_IO_QSPI_MSB 6 +#define RESETS_RESET_IO_QSPI_LSB 6 +#define RESETS_RESET_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_BANK0 +// Description : None +#define RESETS_RESET_IO_BANK0_RESET 0x1 +#define RESETS_RESET_IO_BANK0_BITS 0x00000020 +#define RESETS_RESET_IO_BANK0_MSB 5 +#define RESETS_RESET_IO_BANK0_LSB 5 +#define RESETS_RESET_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C1 +// Description : None +#define RESETS_RESET_I2C1_RESET 0x1 +#define RESETS_RESET_I2C1_BITS 0x00000010 +#define RESETS_RESET_I2C1_MSB 4 +#define RESETS_RESET_I2C1_LSB 4 +#define RESETS_RESET_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C0 +// Description : None +#define RESETS_RESET_I2C0_RESET 0x1 +#define RESETS_RESET_I2C0_BITS 0x00000008 +#define RESETS_RESET_I2C0_MSB 3 +#define RESETS_RESET_I2C0_LSB 3 +#define RESETS_RESET_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DMA +// Description : None +#define RESETS_RESET_DMA_RESET 0x1 +#define RESETS_RESET_DMA_BITS 0x00000004 +#define RESETS_RESET_DMA_MSB 2 +#define RESETS_RESET_DMA_LSB 2 +#define RESETS_RESET_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_BUSCTRL +// Description : None +#define RESETS_RESET_BUSCTRL_RESET 0x1 +#define RESETS_RESET_BUSCTRL_BITS 0x00000002 +#define RESETS_RESET_BUSCTRL_MSB 1 +#define RESETS_RESET_BUSCTRL_LSB 1 +#define RESETS_RESET_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_ADC +// Description : None +#define RESETS_RESET_ADC_RESET 0x1 +#define RESETS_RESET_ADC_BITS 0x00000001 +#define RESETS_RESET_ADC_MSB 0 +#define RESETS_RESET_ADC_LSB 0 +#define RESETS_RESET_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_WDSEL +// Description : Watchdog select. If a bit is set then the watchdog will reset +// this peripheral when the watchdog fires. +#define RESETS_WDSEL_OFFSET 0x00000004 +#define RESETS_WDSEL_BITS 0x01ffffff +#define RESETS_WDSEL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_USBCTRL +// Description : None +#define RESETS_WDSEL_USBCTRL_RESET 0x0 +#define RESETS_WDSEL_USBCTRL_BITS 0x01000000 +#define RESETS_WDSEL_USBCTRL_MSB 24 +#define RESETS_WDSEL_USBCTRL_LSB 24 +#define RESETS_WDSEL_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART1 +// Description : None +#define RESETS_WDSEL_UART1_RESET 0x0 +#define RESETS_WDSEL_UART1_BITS 0x00800000 +#define RESETS_WDSEL_UART1_MSB 23 +#define RESETS_WDSEL_UART1_LSB 23 +#define RESETS_WDSEL_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART0 +// Description : None +#define RESETS_WDSEL_UART0_RESET 0x0 +#define RESETS_WDSEL_UART0_BITS 0x00400000 +#define RESETS_WDSEL_UART0_MSB 22 +#define RESETS_WDSEL_UART0_LSB 22 +#define RESETS_WDSEL_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TIMER +// Description : None +#define RESETS_WDSEL_TIMER_RESET 0x0 +#define RESETS_WDSEL_TIMER_BITS 0x00200000 +#define RESETS_WDSEL_TIMER_MSB 21 +#define RESETS_WDSEL_TIMER_LSB 21 +#define RESETS_WDSEL_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TBMAN +// Description : None +#define RESETS_WDSEL_TBMAN_RESET 0x0 +#define RESETS_WDSEL_TBMAN_BITS 0x00100000 +#define RESETS_WDSEL_TBMAN_MSB 20 +#define RESETS_WDSEL_TBMAN_LSB 20 +#define RESETS_WDSEL_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSINFO +// Description : None +#define RESETS_WDSEL_SYSINFO_RESET 0x0 +#define RESETS_WDSEL_SYSINFO_BITS 0x00080000 +#define RESETS_WDSEL_SYSINFO_MSB 19 +#define RESETS_WDSEL_SYSINFO_LSB 19 +#define RESETS_WDSEL_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSCFG +// Description : None +#define RESETS_WDSEL_SYSCFG_RESET 0x0 +#define RESETS_WDSEL_SYSCFG_BITS 0x00040000 +#define RESETS_WDSEL_SYSCFG_MSB 18 +#define RESETS_WDSEL_SYSCFG_LSB 18 +#define RESETS_WDSEL_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI1 +// Description : None +#define RESETS_WDSEL_SPI1_RESET 0x0 +#define RESETS_WDSEL_SPI1_BITS 0x00020000 +#define RESETS_WDSEL_SPI1_MSB 17 +#define RESETS_WDSEL_SPI1_LSB 17 +#define RESETS_WDSEL_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI0 +// Description : None +#define RESETS_WDSEL_SPI0_RESET 0x0 +#define RESETS_WDSEL_SPI0_BITS 0x00010000 +#define RESETS_WDSEL_SPI0_MSB 16 +#define RESETS_WDSEL_SPI0_LSB 16 +#define RESETS_WDSEL_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_RTC +// Description : None +#define RESETS_WDSEL_RTC_RESET 0x0 +#define RESETS_WDSEL_RTC_BITS 0x00008000 +#define RESETS_WDSEL_RTC_MSB 15 +#define RESETS_WDSEL_RTC_LSB 15 +#define RESETS_WDSEL_RTC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PWM +// Description : None +#define RESETS_WDSEL_PWM_RESET 0x0 +#define RESETS_WDSEL_PWM_BITS 0x00004000 +#define RESETS_WDSEL_PWM_MSB 14 +#define RESETS_WDSEL_PWM_LSB 14 +#define RESETS_WDSEL_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_USB +// Description : None +#define RESETS_WDSEL_PLL_USB_RESET 0x0 +#define RESETS_WDSEL_PLL_USB_BITS 0x00002000 +#define RESETS_WDSEL_PLL_USB_MSB 13 +#define RESETS_WDSEL_PLL_USB_LSB 13 +#define RESETS_WDSEL_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_SYS +// Description : None +#define RESETS_WDSEL_PLL_SYS_RESET 0x0 +#define RESETS_WDSEL_PLL_SYS_BITS 0x00001000 +#define RESETS_WDSEL_PLL_SYS_MSB 12 +#define RESETS_WDSEL_PLL_SYS_LSB 12 +#define RESETS_WDSEL_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO1 +// Description : None +#define RESETS_WDSEL_PIO1_RESET 0x0 +#define RESETS_WDSEL_PIO1_BITS 0x00000800 +#define RESETS_WDSEL_PIO1_MSB 11 +#define RESETS_WDSEL_PIO1_LSB 11 +#define RESETS_WDSEL_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO0 +// Description : None +#define RESETS_WDSEL_PIO0_RESET 0x0 +#define RESETS_WDSEL_PIO0_BITS 0x00000400 +#define RESETS_WDSEL_PIO0_MSB 10 +#define RESETS_WDSEL_PIO0_LSB 10 +#define RESETS_WDSEL_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_QSPI +// Description : None +#define RESETS_WDSEL_PADS_QSPI_RESET 0x0 +#define RESETS_WDSEL_PADS_QSPI_BITS 0x00000200 +#define RESETS_WDSEL_PADS_QSPI_MSB 9 +#define RESETS_WDSEL_PADS_QSPI_LSB 9 +#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_BANK0 +// Description : None +#define RESETS_WDSEL_PADS_BANK0_RESET 0x0 +#define RESETS_WDSEL_PADS_BANK0_BITS 0x00000100 +#define RESETS_WDSEL_PADS_BANK0_MSB 8 +#define RESETS_WDSEL_PADS_BANK0_LSB 8 +#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_JTAG +// Description : None +#define RESETS_WDSEL_JTAG_RESET 0x0 +#define RESETS_WDSEL_JTAG_BITS 0x00000080 +#define RESETS_WDSEL_JTAG_MSB 7 +#define RESETS_WDSEL_JTAG_LSB 7 +#define RESETS_WDSEL_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_QSPI +// Description : None +#define RESETS_WDSEL_IO_QSPI_RESET 0x0 +#define RESETS_WDSEL_IO_QSPI_BITS 0x00000040 +#define RESETS_WDSEL_IO_QSPI_MSB 6 +#define RESETS_WDSEL_IO_QSPI_LSB 6 +#define RESETS_WDSEL_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_BANK0 +// Description : None +#define RESETS_WDSEL_IO_BANK0_RESET 0x0 +#define RESETS_WDSEL_IO_BANK0_BITS 0x00000020 +#define RESETS_WDSEL_IO_BANK0_MSB 5 +#define RESETS_WDSEL_IO_BANK0_LSB 5 +#define RESETS_WDSEL_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C1 +// Description : None +#define RESETS_WDSEL_I2C1_RESET 0x0 +#define RESETS_WDSEL_I2C1_BITS 0x00000010 +#define RESETS_WDSEL_I2C1_MSB 4 +#define RESETS_WDSEL_I2C1_LSB 4 +#define RESETS_WDSEL_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C0 +// Description : None +#define RESETS_WDSEL_I2C0_RESET 0x0 +#define RESETS_WDSEL_I2C0_BITS 0x00000008 +#define RESETS_WDSEL_I2C0_MSB 3 +#define RESETS_WDSEL_I2C0_LSB 3 +#define RESETS_WDSEL_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_DMA +// Description : None +#define RESETS_WDSEL_DMA_RESET 0x0 +#define RESETS_WDSEL_DMA_BITS 0x00000004 +#define RESETS_WDSEL_DMA_MSB 2 +#define RESETS_WDSEL_DMA_LSB 2 +#define RESETS_WDSEL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_BUSCTRL +// Description : None +#define RESETS_WDSEL_BUSCTRL_RESET 0x0 +#define RESETS_WDSEL_BUSCTRL_BITS 0x00000002 +#define RESETS_WDSEL_BUSCTRL_MSB 1 +#define RESETS_WDSEL_BUSCTRL_LSB 1 +#define RESETS_WDSEL_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_ADC +// Description : None +#define RESETS_WDSEL_ADC_RESET 0x0 +#define RESETS_WDSEL_ADC_BITS 0x00000001 +#define RESETS_WDSEL_ADC_MSB 0 +#define RESETS_WDSEL_ADC_LSB 0 +#define RESETS_WDSEL_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_RESET_DONE +// Description : Reset done. If a bit is set then a reset done signal has been +// returned by the peripheral. This indicates that the +// peripheral's registers are ready to be accessed. +#define RESETS_RESET_DONE_OFFSET 0x00000008 +#define RESETS_RESET_DONE_BITS 0x01ffffff +#define RESETS_RESET_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_USBCTRL +// Description : None +#define RESETS_RESET_DONE_USBCTRL_RESET 0x0 +#define RESETS_RESET_DONE_USBCTRL_BITS 0x01000000 +#define RESETS_RESET_DONE_USBCTRL_MSB 24 +#define RESETS_RESET_DONE_USBCTRL_LSB 24 +#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART1 +// Description : None +#define RESETS_RESET_DONE_UART1_RESET 0x0 +#define RESETS_RESET_DONE_UART1_BITS 0x00800000 +#define RESETS_RESET_DONE_UART1_MSB 23 +#define RESETS_RESET_DONE_UART1_LSB 23 +#define RESETS_RESET_DONE_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART0 +// Description : None +#define RESETS_RESET_DONE_UART0_RESET 0x0 +#define RESETS_RESET_DONE_UART0_BITS 0x00400000 +#define RESETS_RESET_DONE_UART0_MSB 22 +#define RESETS_RESET_DONE_UART0_LSB 22 +#define RESETS_RESET_DONE_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TIMER +// Description : None +#define RESETS_RESET_DONE_TIMER_RESET 0x0 +#define RESETS_RESET_DONE_TIMER_BITS 0x00200000 +#define RESETS_RESET_DONE_TIMER_MSB 21 +#define RESETS_RESET_DONE_TIMER_LSB 21 +#define RESETS_RESET_DONE_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TBMAN +// Description : None +#define RESETS_RESET_DONE_TBMAN_RESET 0x0 +#define RESETS_RESET_DONE_TBMAN_BITS 0x00100000 +#define RESETS_RESET_DONE_TBMAN_MSB 20 +#define RESETS_RESET_DONE_TBMAN_LSB 20 +#define RESETS_RESET_DONE_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSINFO +// Description : None +#define RESETS_RESET_DONE_SYSINFO_RESET 0x0 +#define RESETS_RESET_DONE_SYSINFO_BITS 0x00080000 +#define RESETS_RESET_DONE_SYSINFO_MSB 19 +#define RESETS_RESET_DONE_SYSINFO_LSB 19 +#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSCFG +// Description : None +#define RESETS_RESET_DONE_SYSCFG_RESET 0x0 +#define RESETS_RESET_DONE_SYSCFG_BITS 0x00040000 +#define RESETS_RESET_DONE_SYSCFG_MSB 18 +#define RESETS_RESET_DONE_SYSCFG_LSB 18 +#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI1 +// Description : None +#define RESETS_RESET_DONE_SPI1_RESET 0x0 +#define RESETS_RESET_DONE_SPI1_BITS 0x00020000 +#define RESETS_RESET_DONE_SPI1_MSB 17 +#define RESETS_RESET_DONE_SPI1_LSB 17 +#define RESETS_RESET_DONE_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI0 +// Description : None +#define RESETS_RESET_DONE_SPI0_RESET 0x0 +#define RESETS_RESET_DONE_SPI0_BITS 0x00010000 +#define RESETS_RESET_DONE_SPI0_MSB 16 +#define RESETS_RESET_DONE_SPI0_LSB 16 +#define RESETS_RESET_DONE_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_RTC +// Description : None +#define RESETS_RESET_DONE_RTC_RESET 0x0 +#define RESETS_RESET_DONE_RTC_BITS 0x00008000 +#define RESETS_RESET_DONE_RTC_MSB 15 +#define RESETS_RESET_DONE_RTC_LSB 15 +#define RESETS_RESET_DONE_RTC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PWM +// Description : None +#define RESETS_RESET_DONE_PWM_RESET 0x0 +#define RESETS_RESET_DONE_PWM_BITS 0x00004000 +#define RESETS_RESET_DONE_PWM_MSB 14 +#define RESETS_RESET_DONE_PWM_LSB 14 +#define RESETS_RESET_DONE_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_USB +// Description : None +#define RESETS_RESET_DONE_PLL_USB_RESET 0x0 +#define RESETS_RESET_DONE_PLL_USB_BITS 0x00002000 +#define RESETS_RESET_DONE_PLL_USB_MSB 13 +#define RESETS_RESET_DONE_PLL_USB_LSB 13 +#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_SYS +// Description : None +#define RESETS_RESET_DONE_PLL_SYS_RESET 0x0 +#define RESETS_RESET_DONE_PLL_SYS_BITS 0x00001000 +#define RESETS_RESET_DONE_PLL_SYS_MSB 12 +#define RESETS_RESET_DONE_PLL_SYS_LSB 12 +#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO1 +// Description : None +#define RESETS_RESET_DONE_PIO1_RESET 0x0 +#define RESETS_RESET_DONE_PIO1_BITS 0x00000800 +#define RESETS_RESET_DONE_PIO1_MSB 11 +#define RESETS_RESET_DONE_PIO1_LSB 11 +#define RESETS_RESET_DONE_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO0 +// Description : None +#define RESETS_RESET_DONE_PIO0_RESET 0x0 +#define RESETS_RESET_DONE_PIO0_BITS 0x00000400 +#define RESETS_RESET_DONE_PIO0_MSB 10 +#define RESETS_RESET_DONE_PIO0_LSB 10 +#define RESETS_RESET_DONE_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_QSPI +// Description : None +#define RESETS_RESET_DONE_PADS_QSPI_RESET 0x0 +#define RESETS_RESET_DONE_PADS_QSPI_BITS 0x00000200 +#define RESETS_RESET_DONE_PADS_QSPI_MSB 9 +#define RESETS_RESET_DONE_PADS_QSPI_LSB 9 +#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_BANK0 +// Description : None +#define RESETS_RESET_DONE_PADS_BANK0_RESET 0x0 +#define RESETS_RESET_DONE_PADS_BANK0_BITS 0x00000100 +#define RESETS_RESET_DONE_PADS_BANK0_MSB 8 +#define RESETS_RESET_DONE_PADS_BANK0_LSB 8 +#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_JTAG +// Description : None +#define RESETS_RESET_DONE_JTAG_RESET 0x0 +#define RESETS_RESET_DONE_JTAG_BITS 0x00000080 +#define RESETS_RESET_DONE_JTAG_MSB 7 +#define RESETS_RESET_DONE_JTAG_LSB 7 +#define RESETS_RESET_DONE_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_QSPI +// Description : None +#define RESETS_RESET_DONE_IO_QSPI_RESET 0x0 +#define RESETS_RESET_DONE_IO_QSPI_BITS 0x00000040 +#define RESETS_RESET_DONE_IO_QSPI_MSB 6 +#define RESETS_RESET_DONE_IO_QSPI_LSB 6 +#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_BANK0 +// Description : None +#define RESETS_RESET_DONE_IO_BANK0_RESET 0x0 +#define RESETS_RESET_DONE_IO_BANK0_BITS 0x00000020 +#define RESETS_RESET_DONE_IO_BANK0_MSB 5 +#define RESETS_RESET_DONE_IO_BANK0_LSB 5 +#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C1 +// Description : None +#define RESETS_RESET_DONE_I2C1_RESET 0x0 +#define RESETS_RESET_DONE_I2C1_BITS 0x00000010 +#define RESETS_RESET_DONE_I2C1_MSB 4 +#define RESETS_RESET_DONE_I2C1_LSB 4 +#define RESETS_RESET_DONE_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C0 +// Description : None +#define RESETS_RESET_DONE_I2C0_RESET 0x0 +#define RESETS_RESET_DONE_I2C0_BITS 0x00000008 +#define RESETS_RESET_DONE_I2C0_MSB 3 +#define RESETS_RESET_DONE_I2C0_LSB 3 +#define RESETS_RESET_DONE_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_DMA +// Description : None +#define RESETS_RESET_DONE_DMA_RESET 0x0 +#define RESETS_RESET_DONE_DMA_BITS 0x00000004 +#define RESETS_RESET_DONE_DMA_MSB 2 +#define RESETS_RESET_DONE_DMA_LSB 2 +#define RESETS_RESET_DONE_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_BUSCTRL +// Description : None +#define RESETS_RESET_DONE_BUSCTRL_RESET 0x0 +#define RESETS_RESET_DONE_BUSCTRL_BITS 0x00000002 +#define RESETS_RESET_DONE_BUSCTRL_MSB 1 +#define RESETS_RESET_DONE_BUSCTRL_LSB 1 +#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_ADC +// Description : None +#define RESETS_RESET_DONE_ADC_RESET 0x0 +#define RESETS_RESET_DONE_ADC_BITS 0x00000001 +#define RESETS_RESET_DONE_ADC_MSB 0 +#define RESETS_RESET_DONE_ADC_LSB 0 +#define RESETS_RESET_DONE_ADC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_RESETS_DEFINED diff --git a/rp2040/hardware/regs/rosc.h b/rp2040/hardware/regs/rosc.h new file mode 100644 index 0000000..1f9e8cc --- /dev/null +++ b/rp2040/hardware/regs/rosc.h @@ -0,0 +1,312 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ROSC +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_ROSC_DEFINED +#define HARDWARE_REGS_ROSC_DEFINED +// ============================================================================= +// Register : ROSC_CTRL +// Description : Ring Oscillator control +#define ROSC_CTRL_OFFSET 0x00000000 +#define ROSC_CTRL_BITS 0x00ffffff +#define ROSC_CTRL_RESET 0x00000aa0 +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_ENABLE +// Description : On power-up this field is initialised to ENABLE +// The system clock must be switched to another source before +// setting this field to DISABLE otherwise the chip will lock up +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will enable the +// oscillator. +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define ROSC_CTRL_ENABLE_RESET "-" +#define ROSC_CTRL_ENABLE_BITS 0x00fff000 +#define ROSC_CTRL_ENABLE_MSB 23 +#define ROSC_CTRL_ENABLE_LSB 12 +#define ROSC_CTRL_ENABLE_ACCESS "RW" +#define ROSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e +#define ROSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_FREQ_RANGE +// Description : Controls the number of delay stages in the ROSC ring +// LOW uses stages 0 to 7 +// MEDIUM uses stages 0 to 5 +// HIGH uses stages 0 to 3 +// TOOHIGH uses stages 0 to 1 and should not be used because its +// frequency exceeds design specifications +// The clock output will not glitch when changing the range up one +// step at a time +// The clock output will glitch when changing the range down +// Note: the values here are gray coded which is why HIGH comes +// before TOOHIGH +// 0xfa4 -> LOW +// 0xfa5 -> MEDIUM +// 0xfa7 -> HIGH +// 0xfa6 -> TOOHIGH +#define ROSC_CTRL_FREQ_RANGE_RESET 0xaa0 +#define ROSC_CTRL_FREQ_RANGE_BITS 0x00000fff +#define ROSC_CTRL_FREQ_RANGE_MSB 11 +#define ROSC_CTRL_FREQ_RANGE_LSB 0 +#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW 0xfa4 +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM 0xfa5 +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH 0xfa7 +#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH 0xfa6 +// ============================================================================= +// Register : ROSC_FREQA +// Description : The FREQA & FREQB registers control the frequency by +// controlling the drive strength of each stage +// The drive strength has 4 levels determined by the number of +// bits set +// Increasing the number of bits set increases the drive strength +// and increases the oscillation frequency +// 0 bits set is the default drive strength +// 1 bit set doubles the drive strength +// 2 bits set triples drive strength +// 3 bits set quadruples drive strength +#define ROSC_FREQA_OFFSET 0x00000004 +#define ROSC_FREQA_BITS 0xffff7777 +#define ROSC_FREQA_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQA_PASSWD_RESET 0x0000 +#define ROSC_FREQA_PASSWD_BITS 0xffff0000 +#define ROSC_FREQA_PASSWD_MSB 31 +#define ROSC_FREQA_PASSWD_LSB 16 +#define ROSC_FREQA_PASSWD_ACCESS "RW" +#define ROSC_FREQA_PASSWD_VALUE_PASS 0x9696 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS3 +// Description : Stage 3 drive strength +#define ROSC_FREQA_DS3_RESET 0x0 +#define ROSC_FREQA_DS3_BITS 0x00007000 +#define ROSC_FREQA_DS3_MSB 14 +#define ROSC_FREQA_DS3_LSB 12 +#define ROSC_FREQA_DS3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS2 +// Description : Stage 2 drive strength +#define ROSC_FREQA_DS2_RESET 0x0 +#define ROSC_FREQA_DS2_BITS 0x00000700 +#define ROSC_FREQA_DS2_MSB 10 +#define ROSC_FREQA_DS2_LSB 8 +#define ROSC_FREQA_DS2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS1 +// Description : Stage 1 drive strength +#define ROSC_FREQA_DS1_RESET 0x0 +#define ROSC_FREQA_DS1_BITS 0x00000070 +#define ROSC_FREQA_DS1_MSB 6 +#define ROSC_FREQA_DS1_LSB 4 +#define ROSC_FREQA_DS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS0 +// Description : Stage 0 drive strength +#define ROSC_FREQA_DS0_RESET 0x0 +#define ROSC_FREQA_DS0_BITS 0x00000007 +#define ROSC_FREQA_DS0_MSB 2 +#define ROSC_FREQA_DS0_LSB 0 +#define ROSC_FREQA_DS0_ACCESS "RW" +// ============================================================================= +// Register : ROSC_FREQB +// Description : For a detailed description see freqa register +#define ROSC_FREQB_OFFSET 0x00000008 +#define ROSC_FREQB_BITS 0xffff7777 +#define ROSC_FREQB_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQB_PASSWD_RESET 0x0000 +#define ROSC_FREQB_PASSWD_BITS 0xffff0000 +#define ROSC_FREQB_PASSWD_MSB 31 +#define ROSC_FREQB_PASSWD_LSB 16 +#define ROSC_FREQB_PASSWD_ACCESS "RW" +#define ROSC_FREQB_PASSWD_VALUE_PASS 0x9696 +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS7 +// Description : Stage 7 drive strength +#define ROSC_FREQB_DS7_RESET 0x0 +#define ROSC_FREQB_DS7_BITS 0x00007000 +#define ROSC_FREQB_DS7_MSB 14 +#define ROSC_FREQB_DS7_LSB 12 +#define ROSC_FREQB_DS7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS6 +// Description : Stage 6 drive strength +#define ROSC_FREQB_DS6_RESET 0x0 +#define ROSC_FREQB_DS6_BITS 0x00000700 +#define ROSC_FREQB_DS6_MSB 10 +#define ROSC_FREQB_DS6_LSB 8 +#define ROSC_FREQB_DS6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS5 +// Description : Stage 5 drive strength +#define ROSC_FREQB_DS5_RESET 0x0 +#define ROSC_FREQB_DS5_BITS 0x00000070 +#define ROSC_FREQB_DS5_MSB 6 +#define ROSC_FREQB_DS5_LSB 4 +#define ROSC_FREQB_DS5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS4 +// Description : Stage 4 drive strength +#define ROSC_FREQB_DS4_RESET 0x0 +#define ROSC_FREQB_DS4_BITS 0x00000007 +#define ROSC_FREQB_DS4_MSB 2 +#define ROSC_FREQB_DS4_LSB 0 +#define ROSC_FREQB_DS4_ACCESS "RW" +// ============================================================================= +// Register : ROSC_DORMANT +// Description : Ring Oscillator pause control +// This is used to save power by pausing the ROSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> DORMANT +// 0x77616b65 -> WAKE +#define ROSC_DORMANT_OFFSET 0x0000000c +#define ROSC_DORMANT_BITS 0xffffffff +#define ROSC_DORMANT_RESET "-" +#define ROSC_DORMANT_MSB 31 +#define ROSC_DORMANT_LSB 0 +#define ROSC_DORMANT_ACCESS "RW" +#define ROSC_DORMANT_VALUE_DORMANT 0x636f6d61 +#define ROSC_DORMANT_VALUE_WAKE 0x77616b65 +// ============================================================================= +// Register : ROSC_DIV +// Description : Controls the output divider +// set to 0xaa0 + div where +// div = 0 divides by 32 +// div = 1-31 divides by div +// any other value sets div=0 and therefore divides by 32 +// this register resets to div=16 +// 0xaa0 -> PASS +#define ROSC_DIV_OFFSET 0x00000010 +#define ROSC_DIV_BITS 0x00000fff +#define ROSC_DIV_RESET "-" +#define ROSC_DIV_MSB 11 +#define ROSC_DIV_LSB 0 +#define ROSC_DIV_ACCESS "RW" +#define ROSC_DIV_VALUE_PASS 0xaa0 +// ============================================================================= +// Register : ROSC_PHASE +// Description : Controls the phase shifted output +#define ROSC_PHASE_OFFSET 0x00000014 +#define ROSC_PHASE_BITS 0x00000fff +#define ROSC_PHASE_RESET 0x00000008 +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_PASSWD +// Description : set to 0xaa0 +// any other value enables the output with shift=0 +#define ROSC_PHASE_PASSWD_RESET 0x00 +#define ROSC_PHASE_PASSWD_BITS 0x00000ff0 +#define ROSC_PHASE_PASSWD_MSB 11 +#define ROSC_PHASE_PASSWD_LSB 4 +#define ROSC_PHASE_PASSWD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_ENABLE +// Description : enable the phase-shifted output +// this can be changed on-the-fly +#define ROSC_PHASE_ENABLE_RESET 0x1 +#define ROSC_PHASE_ENABLE_BITS 0x00000008 +#define ROSC_PHASE_ENABLE_MSB 3 +#define ROSC_PHASE_ENABLE_LSB 3 +#define ROSC_PHASE_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_FLIP +// Description : invert the phase-shifted output +// this is ignored when div=1 +#define ROSC_PHASE_FLIP_RESET 0x0 +#define ROSC_PHASE_FLIP_BITS 0x00000004 +#define ROSC_PHASE_FLIP_MSB 2 +#define ROSC_PHASE_FLIP_LSB 2 +#define ROSC_PHASE_FLIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_SHIFT +// Description : phase shift the phase-shifted output by SHIFT input clocks +// this can be changed on-the-fly +// must be set to 0 before setting div=1 +#define ROSC_PHASE_SHIFT_RESET 0x0 +#define ROSC_PHASE_SHIFT_BITS 0x00000003 +#define ROSC_PHASE_SHIFT_MSB 1 +#define ROSC_PHASE_SHIFT_LSB 0 +#define ROSC_PHASE_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : ROSC_STATUS +// Description : Ring Oscillator Status +#define ROSC_STATUS_OFFSET 0x00000018 +#define ROSC_STATUS_BITS 0x81011000 +#define ROSC_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define ROSC_STATUS_STABLE_RESET 0x0 +#define ROSC_STATUS_STABLE_BITS 0x80000000 +#define ROSC_STATUS_STABLE_MSB 31 +#define ROSC_STATUS_STABLE_LSB 31 +#define ROSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT +#define ROSC_STATUS_BADWRITE_RESET 0x0 +#define ROSC_STATUS_BADWRITE_BITS 0x01000000 +#define ROSC_STATUS_BADWRITE_MSB 24 +#define ROSC_STATUS_BADWRITE_LSB 24 +#define ROSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_DIV_RUNNING +// Description : post-divider is running +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_DIV_RUNNING_RESET "-" +#define ROSC_STATUS_DIV_RUNNING_BITS 0x00010000 +#define ROSC_STATUS_DIV_RUNNING_MSB 16 +#define ROSC_STATUS_DIV_RUNNING_LSB 16 +#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_ENABLED_RESET "-" +#define ROSC_STATUS_ENABLED_BITS 0x00001000 +#define ROSC_STATUS_ENABLED_MSB 12 +#define ROSC_STATUS_ENABLED_LSB 12 +#define ROSC_STATUS_ENABLED_ACCESS "RO" +// ============================================================================= +// Register : ROSC_RANDOMBIT +// Description : This just reads the state of the oscillator output so +// randomness is compromised if the ring oscillator is stopped or +// run at a harmonic of the bus frequency +#define ROSC_RANDOMBIT_OFFSET 0x0000001c +#define ROSC_RANDOMBIT_BITS 0x00000001 +#define ROSC_RANDOMBIT_RESET 0x00000001 +#define ROSC_RANDOMBIT_MSB 0 +#define ROSC_RANDOMBIT_LSB 0 +#define ROSC_RANDOMBIT_ACCESS "RO" +// ============================================================================= +// Register : ROSC_COUNT +// Description : A down counter running at the ROSC frequency which counts to +// zero and stops. +// To start the counter write a non-zero value. +// Can be used for short software pauses when setting up time +// sensitive hardware. +#define ROSC_COUNT_OFFSET 0x00000020 +#define ROSC_COUNT_BITS 0x000000ff +#define ROSC_COUNT_RESET 0x00000000 +#define ROSC_COUNT_MSB 7 +#define ROSC_COUNT_LSB 0 +#define ROSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_ROSC_DEFINED diff --git a/rp2040/hardware/regs/rtc.h b/rp2040/hardware/regs/rtc.h new file mode 100644 index 0000000..1287d90 --- /dev/null +++ b/rp2040/hardware/regs/rtc.h @@ -0,0 +1,398 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RTC +// Version : 1 +// Bus type : apb +// Description : Register block to control RTC +// ============================================================================= +#ifndef HARDWARE_REGS_RTC_DEFINED +#define HARDWARE_REGS_RTC_DEFINED +// ============================================================================= +// Register : RTC_CLKDIV_M1 +// Description : Divider minus 1 for the 1 second counter. Safe to change the +// value when RTC is not enabled. +#define RTC_CLKDIV_M1_OFFSET 0x00000000 +#define RTC_CLKDIV_M1_BITS 0x0000ffff +#define RTC_CLKDIV_M1_RESET 0x00000000 +#define RTC_CLKDIV_M1_MSB 15 +#define RTC_CLKDIV_M1_LSB 0 +#define RTC_CLKDIV_M1_ACCESS "RW" +// ============================================================================= +// Register : RTC_SETUP_0 +// Description : RTC setup register 0 +#define RTC_SETUP_0_OFFSET 0x00000004 +#define RTC_SETUP_0_BITS 0x00ffff1f +#define RTC_SETUP_0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_0_YEAR +// Description : Year +#define RTC_SETUP_0_YEAR_RESET 0x000 +#define RTC_SETUP_0_YEAR_BITS 0x00fff000 +#define RTC_SETUP_0_YEAR_MSB 23 +#define RTC_SETUP_0_YEAR_LSB 12 +#define RTC_SETUP_0_YEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_0_MONTH +// Description : Month (1..12) +#define RTC_SETUP_0_MONTH_RESET 0x0 +#define RTC_SETUP_0_MONTH_BITS 0x00000f00 +#define RTC_SETUP_0_MONTH_MSB 11 +#define RTC_SETUP_0_MONTH_LSB 8 +#define RTC_SETUP_0_MONTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_0_DAY +// Description : Day of the month (1..31) +#define RTC_SETUP_0_DAY_RESET 0x00 +#define RTC_SETUP_0_DAY_BITS 0x0000001f +#define RTC_SETUP_0_DAY_MSB 4 +#define RTC_SETUP_0_DAY_LSB 0 +#define RTC_SETUP_0_DAY_ACCESS "RW" +// ============================================================================= +// Register : RTC_SETUP_1 +// Description : RTC setup register 1 +#define RTC_SETUP_1_OFFSET 0x00000008 +#define RTC_SETUP_1_BITS 0x071f3f3f +#define RTC_SETUP_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_DOTW +// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 +#define RTC_SETUP_1_DOTW_RESET 0x0 +#define RTC_SETUP_1_DOTW_BITS 0x07000000 +#define RTC_SETUP_1_DOTW_MSB 26 +#define RTC_SETUP_1_DOTW_LSB 24 +#define RTC_SETUP_1_DOTW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_HOUR +// Description : Hours +#define RTC_SETUP_1_HOUR_RESET 0x00 +#define RTC_SETUP_1_HOUR_BITS 0x001f0000 +#define RTC_SETUP_1_HOUR_MSB 20 +#define RTC_SETUP_1_HOUR_LSB 16 +#define RTC_SETUP_1_HOUR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_MIN +// Description : Minutes +#define RTC_SETUP_1_MIN_RESET 0x00 +#define RTC_SETUP_1_MIN_BITS 0x00003f00 +#define RTC_SETUP_1_MIN_MSB 13 +#define RTC_SETUP_1_MIN_LSB 8 +#define RTC_SETUP_1_MIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_SETUP_1_SEC +// Description : Seconds +#define RTC_SETUP_1_SEC_RESET 0x00 +#define RTC_SETUP_1_SEC_BITS 0x0000003f +#define RTC_SETUP_1_SEC_MSB 5 +#define RTC_SETUP_1_SEC_LSB 0 +#define RTC_SETUP_1_SEC_ACCESS "RW" +// ============================================================================= +// Register : RTC_CTRL +// Description : RTC Control and status +#define RTC_CTRL_OFFSET 0x0000000c +#define RTC_CTRL_BITS 0x00000113 +#define RTC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_FORCE_NOTLEAPYEAR +// Description : If set, leapyear is forced off. +// Useful for years divisible by 100 but not by 400 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET 0x0 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS 0x00000100 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB 8 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB 8 +#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_LOAD +// Description : Load RTC +#define RTC_CTRL_LOAD_RESET 0x0 +#define RTC_CTRL_LOAD_BITS 0x00000010 +#define RTC_CTRL_LOAD_MSB 4 +#define RTC_CTRL_LOAD_LSB 4 +#define RTC_CTRL_LOAD_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_RTC_ACTIVE +// Description : RTC enabled (running) +#define RTC_CTRL_RTC_ACTIVE_RESET "-" +#define RTC_CTRL_RTC_ACTIVE_BITS 0x00000002 +#define RTC_CTRL_RTC_ACTIVE_MSB 1 +#define RTC_CTRL_RTC_ACTIVE_LSB 1 +#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_CTRL_RTC_ENABLE +// Description : Enable RTC +#define RTC_CTRL_RTC_ENABLE_RESET 0x0 +#define RTC_CTRL_RTC_ENABLE_BITS 0x00000001 +#define RTC_CTRL_RTC_ENABLE_MSB 0 +#define RTC_CTRL_RTC_ENABLE_LSB 0 +#define RTC_CTRL_RTC_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : RTC_IRQ_SETUP_0 +// Description : Interrupt setup register 0 +#define RTC_IRQ_SETUP_0_OFFSET 0x00000010 +#define RTC_IRQ_SETUP_0_BITS 0x37ffff1f +#define RTC_IRQ_SETUP_0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE +// Description : None +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS 0x20000000 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB 29 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB 29 +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MATCH_ENA +// Description : Global match enable. Don't change any other value while this +// one is enabled +#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS 0x10000000 +#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB 28 +#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB 28 +#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_YEAR_ENA +// Description : Enable year matching +#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS 0x04000000 +#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB 26 +#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB 26 +#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MONTH_ENA +// Description : Enable month matching +#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS 0x02000000 +#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB 25 +#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB 25 +#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_DAY_ENA +// Description : Enable day matching +#define RTC_IRQ_SETUP_0_DAY_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_0_DAY_ENA_BITS 0x01000000 +#define RTC_IRQ_SETUP_0_DAY_ENA_MSB 24 +#define RTC_IRQ_SETUP_0_DAY_ENA_LSB 24 +#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_YEAR +// Description : Year +#define RTC_IRQ_SETUP_0_YEAR_RESET 0x000 +#define RTC_IRQ_SETUP_0_YEAR_BITS 0x00fff000 +#define RTC_IRQ_SETUP_0_YEAR_MSB 23 +#define RTC_IRQ_SETUP_0_YEAR_LSB 12 +#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_MONTH +// Description : Month (1..12) +#define RTC_IRQ_SETUP_0_MONTH_RESET 0x0 +#define RTC_IRQ_SETUP_0_MONTH_BITS 0x00000f00 +#define RTC_IRQ_SETUP_0_MONTH_MSB 11 +#define RTC_IRQ_SETUP_0_MONTH_LSB 8 +#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_0_DAY +// Description : Day of the month (1..31) +#define RTC_IRQ_SETUP_0_DAY_RESET 0x00 +#define RTC_IRQ_SETUP_0_DAY_BITS 0x0000001f +#define RTC_IRQ_SETUP_0_DAY_MSB 4 +#define RTC_IRQ_SETUP_0_DAY_LSB 0 +#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW" +// ============================================================================= +// Register : RTC_IRQ_SETUP_1 +// Description : Interrupt setup register 1 +#define RTC_IRQ_SETUP_1_OFFSET 0x00000014 +#define RTC_IRQ_SETUP_1_BITS 0xf71f3f3f +#define RTC_IRQ_SETUP_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_DOTW_ENA +// Description : Enable day of the week matching +#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS 0x80000000 +#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB 31 +#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB 31 +#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_HOUR_ENA +// Description : Enable hour matching +#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS 0x40000000 +#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB 30 +#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB 30 +#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_MIN_ENA +// Description : Enable minute matching +#define RTC_IRQ_SETUP_1_MIN_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_MIN_ENA_BITS 0x20000000 +#define RTC_IRQ_SETUP_1_MIN_ENA_MSB 29 +#define RTC_IRQ_SETUP_1_MIN_ENA_LSB 29 +#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_SEC_ENA +// Description : Enable second matching +#define RTC_IRQ_SETUP_1_SEC_ENA_RESET 0x0 +#define RTC_IRQ_SETUP_1_SEC_ENA_BITS 0x10000000 +#define RTC_IRQ_SETUP_1_SEC_ENA_MSB 28 +#define RTC_IRQ_SETUP_1_SEC_ENA_LSB 28 +#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_DOTW +// Description : Day of the week +#define RTC_IRQ_SETUP_1_DOTW_RESET 0x0 +#define RTC_IRQ_SETUP_1_DOTW_BITS 0x07000000 +#define RTC_IRQ_SETUP_1_DOTW_MSB 26 +#define RTC_IRQ_SETUP_1_DOTW_LSB 24 +#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_HOUR +// Description : Hours +#define RTC_IRQ_SETUP_1_HOUR_RESET 0x00 +#define RTC_IRQ_SETUP_1_HOUR_BITS 0x001f0000 +#define RTC_IRQ_SETUP_1_HOUR_MSB 20 +#define RTC_IRQ_SETUP_1_HOUR_LSB 16 +#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_MIN +// Description : Minutes +#define RTC_IRQ_SETUP_1_MIN_RESET 0x00 +#define RTC_IRQ_SETUP_1_MIN_BITS 0x00003f00 +#define RTC_IRQ_SETUP_1_MIN_MSB 13 +#define RTC_IRQ_SETUP_1_MIN_LSB 8 +#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RTC_IRQ_SETUP_1_SEC +// Description : Seconds +#define RTC_IRQ_SETUP_1_SEC_RESET 0x00 +#define RTC_IRQ_SETUP_1_SEC_BITS 0x0000003f +#define RTC_IRQ_SETUP_1_SEC_MSB 5 +#define RTC_IRQ_SETUP_1_SEC_LSB 0 +#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW" +// ============================================================================= +// Register : RTC_RTC_1 +// Description : RTC register 1. +#define RTC_RTC_1_OFFSET 0x00000018 +#define RTC_RTC_1_BITS 0x00ffff1f +#define RTC_RTC_1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_1_YEAR +// Description : Year +#define RTC_RTC_1_YEAR_RESET "-" +#define RTC_RTC_1_YEAR_BITS 0x00fff000 +#define RTC_RTC_1_YEAR_MSB 23 +#define RTC_RTC_1_YEAR_LSB 12 +#define RTC_RTC_1_YEAR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_1_MONTH +// Description : Month (1..12) +#define RTC_RTC_1_MONTH_RESET "-" +#define RTC_RTC_1_MONTH_BITS 0x00000f00 +#define RTC_RTC_1_MONTH_MSB 11 +#define RTC_RTC_1_MONTH_LSB 8 +#define RTC_RTC_1_MONTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_1_DAY +// Description : Day of the month (1..31) +#define RTC_RTC_1_DAY_RESET "-" +#define RTC_RTC_1_DAY_BITS 0x0000001f +#define RTC_RTC_1_DAY_MSB 4 +#define RTC_RTC_1_DAY_LSB 0 +#define RTC_RTC_1_DAY_ACCESS "RO" +// ============================================================================= +// Register : RTC_RTC_0 +// Description : RTC register 0 +// Read this before RTC 1! +#define RTC_RTC_0_OFFSET 0x0000001c +#define RTC_RTC_0_BITS 0x071f3f3f +#define RTC_RTC_0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_DOTW +// Description : Day of the week +#define RTC_RTC_0_DOTW_RESET "-" +#define RTC_RTC_0_DOTW_BITS 0x07000000 +#define RTC_RTC_0_DOTW_MSB 26 +#define RTC_RTC_0_DOTW_LSB 24 +#define RTC_RTC_0_DOTW_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_HOUR +// Description : Hours +#define RTC_RTC_0_HOUR_RESET "-" +#define RTC_RTC_0_HOUR_BITS 0x001f0000 +#define RTC_RTC_0_HOUR_MSB 20 +#define RTC_RTC_0_HOUR_LSB 16 +#define RTC_RTC_0_HOUR_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_MIN +// Description : Minutes +#define RTC_RTC_0_MIN_RESET "-" +#define RTC_RTC_0_MIN_BITS 0x00003f00 +#define RTC_RTC_0_MIN_MSB 13 +#define RTC_RTC_0_MIN_LSB 8 +#define RTC_RTC_0_MIN_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : RTC_RTC_0_SEC +// Description : Seconds +#define RTC_RTC_0_SEC_RESET "-" +#define RTC_RTC_0_SEC_BITS 0x0000003f +#define RTC_RTC_0_SEC_MSB 5 +#define RTC_RTC_0_SEC_LSB 0 +#define RTC_RTC_0_SEC_ACCESS "RF" +// ============================================================================= +// Register : RTC_INTR +// Description : Raw Interrupts +#define RTC_INTR_OFFSET 0x00000020 +#define RTC_INTR_BITS 0x00000001 +#define RTC_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTR_RTC +// Description : None +#define RTC_INTR_RTC_RESET 0x0 +#define RTC_INTR_RTC_BITS 0x00000001 +#define RTC_INTR_RTC_MSB 0 +#define RTC_INTR_RTC_LSB 0 +#define RTC_INTR_RTC_ACCESS "RO" +// ============================================================================= +// Register : RTC_INTE +// Description : Interrupt Enable +#define RTC_INTE_OFFSET 0x00000024 +#define RTC_INTE_BITS 0x00000001 +#define RTC_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTE_RTC +// Description : None +#define RTC_INTE_RTC_RESET 0x0 +#define RTC_INTE_RTC_BITS 0x00000001 +#define RTC_INTE_RTC_MSB 0 +#define RTC_INTE_RTC_LSB 0 +#define RTC_INTE_RTC_ACCESS "RW" +// ============================================================================= +// Register : RTC_INTF +// Description : Interrupt Force +#define RTC_INTF_OFFSET 0x00000028 +#define RTC_INTF_BITS 0x00000001 +#define RTC_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTF_RTC +// Description : None +#define RTC_INTF_RTC_RESET 0x0 +#define RTC_INTF_RTC_BITS 0x00000001 +#define RTC_INTF_RTC_MSB 0 +#define RTC_INTF_RTC_LSB 0 +#define RTC_INTF_RTC_ACCESS "RW" +// ============================================================================= +// Register : RTC_INTS +// Description : Interrupt status after masking & forcing +#define RTC_INTS_OFFSET 0x0000002c +#define RTC_INTS_BITS 0x00000001 +#define RTC_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : RTC_INTS_RTC +// Description : None +#define RTC_INTS_RTC_RESET 0x0 +#define RTC_INTS_RTC_BITS 0x00000001 +#define RTC_INTS_RTC_MSB 0 +#define RTC_INTS_RTC_LSB 0 +#define RTC_INTS_RTC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_RTC_DEFINED diff --git a/rp2040/hardware/regs/sio.h b/rp2040/hardware/regs/sio.h new file mode 100644 index 0000000..4480d76 --- /dev/null +++ b/rp2040/hardware/regs/sio.h @@ -0,0 +1,1656 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SIO +// Version : 1 +// Bus type : apb +// Description : Single-cycle IO block +// Provides core-local and inter-core hardware for the two +// processors, with single-cycle access. +// ============================================================================= +#ifndef HARDWARE_REGS_SIO_DEFINED +#define HARDWARE_REGS_SIO_DEFINED +// ============================================================================= +// Register : SIO_CPUID +// Description : Processor core identifier +// Value is 0 when read from processor core 0, and 1 when read +// from processor core 1. +#define SIO_CPUID_OFFSET 0x00000000 +#define SIO_CPUID_BITS 0xffffffff +#define SIO_CPUID_RESET "-" +#define SIO_CPUID_MSB 31 +#define SIO_CPUID_LSB 0 +#define SIO_CPUID_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_IN +// Description : Input value for GPIO pins +// Input value for GPIO0...29 +#define SIO_GPIO_IN_OFFSET 0x00000004 +#define SIO_GPIO_IN_BITS 0x3fffffff +#define SIO_GPIO_IN_RESET 0x00000000 +#define SIO_GPIO_IN_MSB 29 +#define SIO_GPIO_IN_LSB 0 +#define SIO_GPIO_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_HI_IN +// Description : Input value for QSPI pins +// Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, +// SD3 +#define SIO_GPIO_HI_IN_OFFSET 0x00000008 +#define SIO_GPIO_HI_IN_BITS 0x0000003f +#define SIO_GPIO_HI_IN_RESET 0x00000000 +#define SIO_GPIO_HI_IN_MSB 5 +#define SIO_GPIO_HI_IN_LSB 0 +#define SIO_GPIO_HI_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_OUT +// Description : GPIO output value +// Set output level (1/0 -> high/low) for GPIO0...29. +// Reading back gives the last value written, NOT the input value +// from the pins. +// If core 0 and core 1 both write to GPIO_OUT simultaneously (or +// to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_OUT_OFFSET 0x00000010 +#define SIO_GPIO_OUT_BITS 0x3fffffff +#define SIO_GPIO_OUT_RESET 0x00000000 +#define SIO_GPIO_OUT_MSB 29 +#define SIO_GPIO_OUT_LSB 0 +#define SIO_GPIO_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_SET +// Description : GPIO output value set +// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` +#define SIO_GPIO_OUT_SET_OFFSET 0x00000014 +#define SIO_GPIO_OUT_SET_BITS 0x3fffffff +#define SIO_GPIO_OUT_SET_RESET 0x00000000 +#define SIO_GPIO_OUT_SET_MSB 29 +#define SIO_GPIO_OUT_SET_LSB 0 +#define SIO_GPIO_OUT_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_CLR +// Description : GPIO output value clear +// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= +// ~wdata` +#define SIO_GPIO_OUT_CLR_OFFSET 0x00000018 +#define SIO_GPIO_OUT_CLR_BITS 0x3fffffff +#define SIO_GPIO_OUT_CLR_RESET 0x00000000 +#define SIO_GPIO_OUT_CLR_MSB 29 +#define SIO_GPIO_OUT_CLR_LSB 0 +#define SIO_GPIO_OUT_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_XOR +// Description : GPIO output value XOR +// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= +// wdata` +#define SIO_GPIO_OUT_XOR_OFFSET 0x0000001c +#define SIO_GPIO_OUT_XOR_BITS 0x3fffffff +#define SIO_GPIO_OUT_XOR_RESET 0x00000000 +#define SIO_GPIO_OUT_XOR_MSB 29 +#define SIO_GPIO_OUT_XOR_LSB 0 +#define SIO_GPIO_OUT_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE +// Description : GPIO output enable +// Set output enable (1/0 -> output/input) for GPIO0...29. +// Reading back gives the last value written. +// If core 0 and core 1 both write to GPIO_OE simultaneously (or +// to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_OE_OFFSET 0x00000020 +#define SIO_GPIO_OE_BITS 0x3fffffff +#define SIO_GPIO_OE_RESET 0x00000000 +#define SIO_GPIO_OE_MSB 29 +#define SIO_GPIO_OE_LSB 0 +#define SIO_GPIO_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_SET +// Description : GPIO output enable set +// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` +#define SIO_GPIO_OE_SET_OFFSET 0x00000024 +#define SIO_GPIO_OE_SET_BITS 0x3fffffff +#define SIO_GPIO_OE_SET_RESET 0x00000000 +#define SIO_GPIO_OE_SET_MSB 29 +#define SIO_GPIO_OE_SET_LSB 0 +#define SIO_GPIO_OE_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_CLR +// Description : GPIO output enable clear +// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= +// ~wdata` +#define SIO_GPIO_OE_CLR_OFFSET 0x00000028 +#define SIO_GPIO_OE_CLR_BITS 0x3fffffff +#define SIO_GPIO_OE_CLR_RESET 0x00000000 +#define SIO_GPIO_OE_CLR_MSB 29 +#define SIO_GPIO_OE_CLR_LSB 0 +#define SIO_GPIO_OE_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_XOR +// Description : GPIO output enable XOR +// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= +// wdata` +#define SIO_GPIO_OE_XOR_OFFSET 0x0000002c +#define SIO_GPIO_OE_XOR_BITS 0x3fffffff +#define SIO_GPIO_OE_XOR_RESET 0x00000000 +#define SIO_GPIO_OE_XOR_MSB 29 +#define SIO_GPIO_OE_XOR_LSB 0 +#define SIO_GPIO_OE_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT +// Description : QSPI output value +// Set output level (1/0 -> high/low) for QSPI IO0...5. +// Reading back gives the last value written, NOT the input value +// from the pins. +// If core 0 and core 1 both write to GPIO_HI_OUT simultaneously +// (or to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_HI_OUT_OFFSET 0x00000030 +#define SIO_GPIO_HI_OUT_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_MSB 5 +#define SIO_GPIO_HI_OUT_LSB 0 +#define SIO_GPIO_HI_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_SET +// Description : QSPI output value set +// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= +// wdata` +#define SIO_GPIO_HI_OUT_SET_OFFSET 0x00000034 +#define SIO_GPIO_HI_OUT_SET_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_SET_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_SET_MSB 5 +#define SIO_GPIO_HI_OUT_SET_LSB 0 +#define SIO_GPIO_HI_OUT_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_CLR +// Description : QSPI output value clear +// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// &= ~wdata` +#define SIO_GPIO_HI_OUT_CLR_OFFSET 0x00000038 +#define SIO_GPIO_HI_OUT_CLR_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_CLR_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_CLR_MSB 5 +#define SIO_GPIO_HI_OUT_CLR_LSB 0 +#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_XOR +// Description : QSPI output value XOR +// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// ^= wdata` +#define SIO_GPIO_HI_OUT_XOR_OFFSET 0x0000003c +#define SIO_GPIO_HI_OUT_XOR_BITS 0x0000003f +#define SIO_GPIO_HI_OUT_XOR_RESET 0x00000000 +#define SIO_GPIO_HI_OUT_XOR_MSB 5 +#define SIO_GPIO_HI_OUT_XOR_LSB 0 +#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE +// Description : QSPI output enable +// Set output enable (1/0 -> output/input) for QSPI IO0...5. +// Reading back gives the last value written. +// If core 0 and core 1 both write to GPIO_HI_OE simultaneously +// (or to a SET/CLR/XOR alias), +// the result is as though the write from core 0 took place first, +// and the write from core 1 was then applied to that intermediate +// result. +#define SIO_GPIO_HI_OE_OFFSET 0x00000040 +#define SIO_GPIO_HI_OE_BITS 0x0000003f +#define SIO_GPIO_HI_OE_RESET 0x00000000 +#define SIO_GPIO_HI_OE_MSB 5 +#define SIO_GPIO_HI_OE_LSB 0 +#define SIO_GPIO_HI_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_SET +// Description : QSPI output enable set +// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= +// wdata` +#define SIO_GPIO_HI_OE_SET_OFFSET 0x00000044 +#define SIO_GPIO_HI_OE_SET_BITS 0x0000003f +#define SIO_GPIO_HI_OE_SET_RESET 0x00000000 +#define SIO_GPIO_HI_OE_SET_MSB 5 +#define SIO_GPIO_HI_OE_SET_LSB 0 +#define SIO_GPIO_HI_OE_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_CLR +// Description : QSPI output enable clear +// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= +// ~wdata` +#define SIO_GPIO_HI_OE_CLR_OFFSET 0x00000048 +#define SIO_GPIO_HI_OE_CLR_BITS 0x0000003f +#define SIO_GPIO_HI_OE_CLR_RESET 0x00000000 +#define SIO_GPIO_HI_OE_CLR_MSB 5 +#define SIO_GPIO_HI_OE_CLR_LSB 0 +#define SIO_GPIO_HI_OE_CLR_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_XOR +// Description : QSPI output enable XOR +// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE +// ^= wdata` +#define SIO_GPIO_HI_OE_XOR_OFFSET 0x0000004c +#define SIO_GPIO_HI_OE_XOR_BITS 0x0000003f +#define SIO_GPIO_HI_OE_XOR_RESET 0x00000000 +#define SIO_GPIO_HI_OE_XOR_MSB 5 +#define SIO_GPIO_HI_OE_XOR_LSB 0 +#define SIO_GPIO_HI_OE_XOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_FIFO_ST +// Description : Status register for inter-core FIFOs (mailboxes). +// There is one FIFO in the core 0 -> core 1 direction, and one +// core 1 -> core 0. Both are 32 bits wide and 8 words deep. +// Core 0 can see the read side of the 1->0 FIFO (RX), and the +// write side of 0->1 FIFO (TX). +// Core 1 can see the read side of the 0->1 FIFO (RX), and the +// write side of 1->0 FIFO (TX). +// The SIO IRQ for each core is the logical OR of the VLD, WOF and +// ROE fields of its FIFO_ST register. +#define SIO_FIFO_ST_OFFSET 0x00000050 +#define SIO_FIFO_ST_BITS 0x0000000f +#define SIO_FIFO_ST_RESET 0x00000002 +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_ROE +// Description : Sticky flag indicating the RX FIFO was read when empty. This +// read was ignored by the FIFO. +#define SIO_FIFO_ST_ROE_RESET 0x0 +#define SIO_FIFO_ST_ROE_BITS 0x00000008 +#define SIO_FIFO_ST_ROE_MSB 3 +#define SIO_FIFO_ST_ROE_LSB 3 +#define SIO_FIFO_ST_ROE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_WOF +// Description : Sticky flag indicating the TX FIFO was written when full. This +// write was ignored by the FIFO. +#define SIO_FIFO_ST_WOF_RESET 0x0 +#define SIO_FIFO_ST_WOF_BITS 0x00000004 +#define SIO_FIFO_ST_WOF_MSB 2 +#define SIO_FIFO_ST_WOF_LSB 2 +#define SIO_FIFO_ST_WOF_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_RDY +// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR +// is ready for more data) +#define SIO_FIFO_ST_RDY_RESET 0x1 +#define SIO_FIFO_ST_RDY_BITS 0x00000002 +#define SIO_FIFO_ST_RDY_MSB 1 +#define SIO_FIFO_ST_RDY_LSB 1 +#define SIO_FIFO_ST_RDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_VLD +// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD +// is valid) +#define SIO_FIFO_ST_VLD_RESET 0x0 +#define SIO_FIFO_ST_VLD_BITS 0x00000001 +#define SIO_FIFO_ST_VLD_MSB 0 +#define SIO_FIFO_ST_VLD_LSB 0 +#define SIO_FIFO_ST_VLD_ACCESS "RO" +// ============================================================================= +// Register : SIO_FIFO_WR +// Description : Write access to this core's TX FIFO +#define SIO_FIFO_WR_OFFSET 0x00000054 +#define SIO_FIFO_WR_BITS 0xffffffff +#define SIO_FIFO_WR_RESET 0x00000000 +#define SIO_FIFO_WR_MSB 31 +#define SIO_FIFO_WR_LSB 0 +#define SIO_FIFO_WR_ACCESS "WF" +// ============================================================================= +// Register : SIO_FIFO_RD +// Description : Read access to this core's RX FIFO +#define SIO_FIFO_RD_OFFSET 0x00000058 +#define SIO_FIFO_RD_BITS 0xffffffff +#define SIO_FIFO_RD_RESET "-" +#define SIO_FIFO_RD_MSB 31 +#define SIO_FIFO_RD_LSB 0 +#define SIO_FIFO_RD_ACCESS "RF" +// ============================================================================= +// Register : SIO_SPINLOCK_ST +// Description : Spinlock state +// A bitmap containing the state of all 32 spinlocks (1=locked). +// Mainly intended for debugging. +#define SIO_SPINLOCK_ST_OFFSET 0x0000005c +#define SIO_SPINLOCK_ST_BITS 0xffffffff +#define SIO_SPINLOCK_ST_RESET 0x00000000 +#define SIO_SPINLOCK_ST_MSB 31 +#define SIO_SPINLOCK_ST_LSB 0 +#define SIO_SPINLOCK_ST_ACCESS "RO" +// ============================================================================= +// Register : SIO_DIV_UDIVIDEND +// Description : Divider unsigned dividend +// Write to the DIVIDEND operand of the divider, i.e. the p in `p +// / q`. +// Any operand write starts a new calculation. The results appear +// in QUOTIENT, REMAINDER. +// UDIVIDEND/SDIVIDEND are aliases of the same internal register. +// The U alias starts an +// unsigned calculation, and the S alias starts a signed +// calculation. +#define SIO_DIV_UDIVIDEND_OFFSET 0x00000060 +#define SIO_DIV_UDIVIDEND_BITS 0xffffffff +#define SIO_DIV_UDIVIDEND_RESET 0x00000000 +#define SIO_DIV_UDIVIDEND_MSB 31 +#define SIO_DIV_UDIVIDEND_LSB 0 +#define SIO_DIV_UDIVIDEND_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_UDIVISOR +// Description : Divider unsigned divisor +// Write to the DIVISOR operand of the divider, i.e. the q in `p / +// q`. +// Any operand write starts a new calculation. The results appear +// in QUOTIENT, REMAINDER. +// UDIVIDEND/SDIVIDEND are aliases of the same internal register. +// The U alias starts an +// unsigned calculation, and the S alias starts a signed +// calculation. +#define SIO_DIV_UDIVISOR_OFFSET 0x00000064 +#define SIO_DIV_UDIVISOR_BITS 0xffffffff +#define SIO_DIV_UDIVISOR_RESET 0x00000000 +#define SIO_DIV_UDIVISOR_MSB 31 +#define SIO_DIV_UDIVISOR_LSB 0 +#define SIO_DIV_UDIVISOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_SDIVIDEND +// Description : Divider signed dividend +// The same as UDIVIDEND, but starts a signed calculation, rather +// than unsigned. +#define SIO_DIV_SDIVIDEND_OFFSET 0x00000068 +#define SIO_DIV_SDIVIDEND_BITS 0xffffffff +#define SIO_DIV_SDIVIDEND_RESET 0x00000000 +#define SIO_DIV_SDIVIDEND_MSB 31 +#define SIO_DIV_SDIVIDEND_LSB 0 +#define SIO_DIV_SDIVIDEND_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_SDIVISOR +// Description : Divider signed divisor +// The same as UDIVISOR, but starts a signed calculation, rather +// than unsigned. +#define SIO_DIV_SDIVISOR_OFFSET 0x0000006c +#define SIO_DIV_SDIVISOR_BITS 0xffffffff +#define SIO_DIV_SDIVISOR_RESET 0x00000000 +#define SIO_DIV_SDIVISOR_MSB 31 +#define SIO_DIV_SDIVISOR_LSB 0 +#define SIO_DIV_SDIVISOR_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_QUOTIENT +// Description : Divider result quotient +// The result of `DIVIDEND / DIVISOR` (division). Contents +// undefined while CSR_READY is low. +// For signed calculations, QUOTIENT is negative when the signs of +// DIVIDEND and DIVISOR differ. +// This register can be written to directly, for context +// save/restore purposes. This halts any +// in-progress calculation and sets the CSR_READY and CSR_DIRTY +// flags. +// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read +// results in the order +// REMAINDER, QUOTIENT if CSR_DIRTY is used. +#define SIO_DIV_QUOTIENT_OFFSET 0x00000070 +#define SIO_DIV_QUOTIENT_BITS 0xffffffff +#define SIO_DIV_QUOTIENT_RESET 0x00000000 +#define SIO_DIV_QUOTIENT_MSB 31 +#define SIO_DIV_QUOTIENT_LSB 0 +#define SIO_DIV_QUOTIENT_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_REMAINDER +// Description : Divider result remainder +// The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined +// while CSR_READY is low. +// For signed calculations, REMAINDER is negative only when +// DIVIDEND is negative. +// This register can be written to directly, for context +// save/restore purposes. This halts any +// in-progress calculation and sets the CSR_READY and CSR_DIRTY +// flags. +#define SIO_DIV_REMAINDER_OFFSET 0x00000074 +#define SIO_DIV_REMAINDER_BITS 0xffffffff +#define SIO_DIV_REMAINDER_RESET 0x00000000 +#define SIO_DIV_REMAINDER_MSB 31 +#define SIO_DIV_REMAINDER_LSB 0 +#define SIO_DIV_REMAINDER_ACCESS "RW" +// ============================================================================= +// Register : SIO_DIV_CSR +// Description : Control and status register for divider. +#define SIO_DIV_CSR_OFFSET 0x00000078 +#define SIO_DIV_CSR_BITS 0x00000003 +#define SIO_DIV_CSR_RESET 0x00000001 +// ----------------------------------------------------------------------------- +// Field : SIO_DIV_CSR_DIRTY +// Description : Changes to 1 when any register is written, and back to 0 when +// QUOTIENT is read. +// Software can use this flag to make save/restore more efficient +// (skip if not DIRTY). +// If the flag is used in this way, it's recommended to either +// read QUOTIENT only, +// or REMAINDER and then QUOTIENT, to prevent data loss on context +// switch. +#define SIO_DIV_CSR_DIRTY_RESET 0x0 +#define SIO_DIV_CSR_DIRTY_BITS 0x00000002 +#define SIO_DIV_CSR_DIRTY_MSB 1 +#define SIO_DIV_CSR_DIRTY_LSB 1 +#define SIO_DIV_CSR_DIRTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_DIV_CSR_READY +// Description : Reads as 0 when a calculation is in progress, 1 otherwise. +// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start +// a new calculation, no +// matter if one is already in progress. +// Writing to a result register will immediately terminate any +// in-progress calculation +// and set the READY and DIRTY flags. +#define SIO_DIV_CSR_READY_RESET 0x1 +#define SIO_DIV_CSR_READY_BITS 0x00000001 +#define SIO_DIV_CSR_READY_MSB 0 +#define SIO_DIV_CSR_READY_LSB 0 +#define SIO_DIV_CSR_READY_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP0_ACCUM0_OFFSET 0x00000080 +#define SIO_INTERP0_ACCUM0_BITS 0xffffffff +#define SIO_INTERP0_ACCUM0_RESET 0x00000000 +#define SIO_INTERP0_ACCUM0_MSB 31 +#define SIO_INTERP0_ACCUM0_LSB 0 +#define SIO_INTERP0_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP0_ACCUM1_OFFSET 0x00000084 +#define SIO_INTERP0_ACCUM1_BITS 0xffffffff +#define SIO_INTERP0_ACCUM1_RESET 0x00000000 +#define SIO_INTERP0_ACCUM1_MSB 31 +#define SIO_INTERP0_ACCUM1_LSB 0 +#define SIO_INTERP0_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP0_BASE0_OFFSET 0x00000088 +#define SIO_INTERP0_BASE0_BITS 0xffffffff +#define SIO_INTERP0_BASE0_RESET 0x00000000 +#define SIO_INTERP0_BASE0_MSB 31 +#define SIO_INTERP0_BASE0_LSB 0 +#define SIO_INTERP0_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP0_BASE1_OFFSET 0x0000008c +#define SIO_INTERP0_BASE1_BITS 0xffffffff +#define SIO_INTERP0_BASE1_RESET 0x00000000 +#define SIO_INTERP0_BASE1_MSB 31 +#define SIO_INTERP0_BASE1_LSB 0 +#define SIO_INTERP0_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP0_BASE2_OFFSET 0x00000090 +#define SIO_INTERP0_BASE2_BITS 0xffffffff +#define SIO_INTERP0_BASE2_RESET 0x00000000 +#define SIO_INTERP0_BASE2_MSB 31 +#define SIO_INTERP0_BASE2_LSB 0 +#define SIO_INTERP0_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE0_OFFSET 0x00000094 +#define SIO_INTERP0_POP_LANE0_BITS 0xffffffff +#define SIO_INTERP0_POP_LANE0_RESET 0x00000000 +#define SIO_INTERP0_POP_LANE0_MSB 31 +#define SIO_INTERP0_POP_LANE0_LSB 0 +#define SIO_INTERP0_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE1_OFFSET 0x00000098 +#define SIO_INTERP0_POP_LANE1_BITS 0xffffffff +#define SIO_INTERP0_POP_LANE1_RESET 0x00000000 +#define SIO_INTERP0_POP_LANE1_MSB 31 +#define SIO_INTERP0_POP_LANE1_LSB 0 +#define SIO_INTERP0_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP0_POP_FULL_OFFSET 0x0000009c +#define SIO_INTERP0_POP_FULL_BITS 0xffffffff +#define SIO_INTERP0_POP_FULL_RESET 0x00000000 +#define SIO_INTERP0_POP_FULL_MSB 31 +#define SIO_INTERP0_POP_FULL_LSB 0 +#define SIO_INTERP0_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE0_OFFSET 0x000000a0 +#define SIO_INTERP0_PEEK_LANE0_BITS 0xffffffff +#define SIO_INTERP0_PEEK_LANE0_RESET 0x00000000 +#define SIO_INTERP0_PEEK_LANE0_MSB 31 +#define SIO_INTERP0_PEEK_LANE0_LSB 0 +#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE1_OFFSET 0x000000a4 +#define SIO_INTERP0_PEEK_LANE1_BITS 0xffffffff +#define SIO_INTERP0_PEEK_LANE1_RESET 0x00000000 +#define SIO_INTERP0_PEEK_LANE1_MSB 31 +#define SIO_INTERP0_PEEK_LANE1_LSB 0 +#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_FULL_OFFSET 0x000000a8 +#define SIO_INTERP0_PEEK_FULL_BITS 0xffffffff +#define SIO_INTERP0_PEEK_FULL_RESET 0x00000000 +#define SIO_INTERP0_PEEK_FULL_MSB 31 +#define SIO_INTERP0_PEEK_FULL_LSB 0 +#define SIO_INTERP0_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP0_CTRL_LANE0_OFFSET 0x000000ac +#define SIO_INTERP0_CTRL_LANE0_BITS 0x03bfffff +#define SIO_INTERP0_CTRL_LANE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS 0x02000000 +#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB 25 +#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS 0x01000000 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB 24 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS 0x00800000 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB 23 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_BLEND +// Description : Only present on INTERP0 on each core. If BLEND mode is enabled: +// - LANE1 result is a linear interpolation between BASE0 and +// BASE1, controlled +// by the 8 LSBs of lane 1 shift and mask value (a fractional +// number between +// 0 and 255/256ths) +// - LANE0 result does not have BASE0 added (yields only the 8 +// LSBs of lane 1 shift+mask value) +// - FULL result does not have lane 1 shift+mask value added +// (BASE2 + lane 0 shift+mask) +// LANE1 SIGNED flag controls whether the interpolation is signed +// or unsigned. +#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS 0x00200000 +#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB 21 +#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB 21 +#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB 20 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB 18 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB 17 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB 16 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS 0x00008000 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB 15 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB 14 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB 9 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS 0x0000001f +#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB 4 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP0_CTRL_LANE1_OFFSET 0x000000b0 +#define SIO_INTERP0_CTRL_LANE1_BITS 0x001fffff +#define SIO_INTERP0_CTRL_LANE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB 20 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB 18 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB 17 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB 16 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET 0x0 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS 0x00008000 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB 15 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB 14 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB 9 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET 0x00 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS 0x0000001f +#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB 4 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP0_ACCUM0_ADD_OFFSET 0x000000b4 +#define SIO_INTERP0_ACCUM0_ADD_BITS 0x00ffffff +#define SIO_INTERP0_ACCUM0_ADD_RESET 0x00000000 +#define SIO_INTERP0_ACCUM0_ADD_MSB 23 +#define SIO_INTERP0_ACCUM0_ADD_LSB 0 +#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP0_ACCUM1_ADD_OFFSET 0x000000b8 +#define SIO_INTERP0_ACCUM1_ADD_BITS 0x00ffffff +#define SIO_INTERP0_ACCUM1_ADD_RESET 0x00000000 +#define SIO_INTERP0_ACCUM1_ADD_MSB 23 +#define SIO_INTERP0_ACCUM1_ADD_LSB 0 +#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP0_BASE_1AND0_OFFSET 0x000000bc +#define SIO_INTERP0_BASE_1AND0_BITS 0xffffffff +#define SIO_INTERP0_BASE_1AND0_RESET 0x00000000 +#define SIO_INTERP0_BASE_1AND0_MSB 31 +#define SIO_INTERP0_BASE_1AND0_LSB 0 +#define SIO_INTERP0_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP1_ACCUM0_OFFSET 0x000000c0 +#define SIO_INTERP1_ACCUM0_BITS 0xffffffff +#define SIO_INTERP1_ACCUM0_RESET 0x00000000 +#define SIO_INTERP1_ACCUM0_MSB 31 +#define SIO_INTERP1_ACCUM0_LSB 0 +#define SIO_INTERP1_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP1_ACCUM1_OFFSET 0x000000c4 +#define SIO_INTERP1_ACCUM1_BITS 0xffffffff +#define SIO_INTERP1_ACCUM1_RESET 0x00000000 +#define SIO_INTERP1_ACCUM1_MSB 31 +#define SIO_INTERP1_ACCUM1_LSB 0 +#define SIO_INTERP1_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP1_BASE0_OFFSET 0x000000c8 +#define SIO_INTERP1_BASE0_BITS 0xffffffff +#define SIO_INTERP1_BASE0_RESET 0x00000000 +#define SIO_INTERP1_BASE0_MSB 31 +#define SIO_INTERP1_BASE0_LSB 0 +#define SIO_INTERP1_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP1_BASE1_OFFSET 0x000000cc +#define SIO_INTERP1_BASE1_BITS 0xffffffff +#define SIO_INTERP1_BASE1_RESET 0x00000000 +#define SIO_INTERP1_BASE1_MSB 31 +#define SIO_INTERP1_BASE1_LSB 0 +#define SIO_INTERP1_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP1_BASE2_OFFSET 0x000000d0 +#define SIO_INTERP1_BASE2_BITS 0xffffffff +#define SIO_INTERP1_BASE2_RESET 0x00000000 +#define SIO_INTERP1_BASE2_MSB 31 +#define SIO_INTERP1_BASE2_LSB 0 +#define SIO_INTERP1_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE0_OFFSET 0x000000d4 +#define SIO_INTERP1_POP_LANE0_BITS 0xffffffff +#define SIO_INTERP1_POP_LANE0_RESET 0x00000000 +#define SIO_INTERP1_POP_LANE0_MSB 31 +#define SIO_INTERP1_POP_LANE0_LSB 0 +#define SIO_INTERP1_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE1_OFFSET 0x000000d8 +#define SIO_INTERP1_POP_LANE1_BITS 0xffffffff +#define SIO_INTERP1_POP_LANE1_RESET 0x00000000 +#define SIO_INTERP1_POP_LANE1_MSB 31 +#define SIO_INTERP1_POP_LANE1_LSB 0 +#define SIO_INTERP1_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP1_POP_FULL_OFFSET 0x000000dc +#define SIO_INTERP1_POP_FULL_BITS 0xffffffff +#define SIO_INTERP1_POP_FULL_RESET 0x00000000 +#define SIO_INTERP1_POP_FULL_MSB 31 +#define SIO_INTERP1_POP_FULL_LSB 0 +#define SIO_INTERP1_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE0_OFFSET 0x000000e0 +#define SIO_INTERP1_PEEK_LANE0_BITS 0xffffffff +#define SIO_INTERP1_PEEK_LANE0_RESET 0x00000000 +#define SIO_INTERP1_PEEK_LANE0_MSB 31 +#define SIO_INTERP1_PEEK_LANE0_LSB 0 +#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE1_OFFSET 0x000000e4 +#define SIO_INTERP1_PEEK_LANE1_BITS 0xffffffff +#define SIO_INTERP1_PEEK_LANE1_RESET 0x00000000 +#define SIO_INTERP1_PEEK_LANE1_MSB 31 +#define SIO_INTERP1_PEEK_LANE1_LSB 0 +#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_FULL_OFFSET 0x000000e8 +#define SIO_INTERP1_PEEK_FULL_BITS 0xffffffff +#define SIO_INTERP1_PEEK_FULL_RESET 0x00000000 +#define SIO_INTERP1_PEEK_FULL_MSB 31 +#define SIO_INTERP1_PEEK_FULL_LSB 0 +#define SIO_INTERP1_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP1_CTRL_LANE0_OFFSET 0x000000ec +#define SIO_INTERP1_CTRL_LANE0_BITS 0x03dfffff +#define SIO_INTERP1_CTRL_LANE0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS 0x02000000 +#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB 25 +#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB 25 +#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS 0x01000000 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB 24 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB 24 +#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS 0x00800000 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB 23 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB 23 +#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CLAMP +// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: +// - LANE0 result is shifted and masked ACCUM0, clamped by a lower +// bound of +// BASE0 and an upper bound of BASE1. +// - Signedness of these comparisons is determined by +// LANE0_CTRL_SIGNED +#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS 0x00400000 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB 22 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB 22 +#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB 20 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB 18 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB 17 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB 16 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS 0x00008000 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB 15 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB 14 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB 9 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS 0x0000001f +#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB 4 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP1_CTRL_LANE1_OFFSET 0x000000f0 +#define SIO_INTERP1_CTRL_LANE1_BITS 0x001fffff +#define SIO_INTERP1_CTRL_LANE1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB 20 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB 19 +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS 0x00040000 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB 18 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB 18 +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB 17 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB 17 +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB 16 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB 16 +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET 0x0 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS 0x00008000 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB 15 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB 15 +#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB 14 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB 10 +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB 9 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB 5 +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SHIFT +// Description : Logical right-shift applied to accumulator before masking +#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET 0x00 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS 0x0000001f +#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB 4 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB 0 +#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP1_ACCUM0_ADD_OFFSET 0x000000f4 +#define SIO_INTERP1_ACCUM0_ADD_BITS 0x00ffffff +#define SIO_INTERP1_ACCUM0_ADD_RESET 0x00000000 +#define SIO_INTERP1_ACCUM0_ADD_MSB 23 +#define SIO_INTERP1_ACCUM0_ADD_LSB 0 +#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP1_ACCUM1_ADD_OFFSET 0x000000f8 +#define SIO_INTERP1_ACCUM1_ADD_BITS 0x00ffffff +#define SIO_INTERP1_ACCUM1_ADD_RESET 0x00000000 +#define SIO_INTERP1_ACCUM1_ADD_MSB 23 +#define SIO_INTERP1_ACCUM1_ADD_LSB 0 +#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP1_BASE_1AND0_OFFSET 0x000000fc +#define SIO_INTERP1_BASE_1AND0_BITS 0xffffffff +#define SIO_INTERP1_BASE_1AND0_RESET 0x00000000 +#define SIO_INTERP1_BASE_1AND0_MSB 31 +#define SIO_INTERP1_BASE_1AND0_LSB 0 +#define SIO_INTERP1_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_SPINLOCK0 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK0_OFFSET 0x00000100 +#define SIO_SPINLOCK0_BITS 0xffffffff +#define SIO_SPINLOCK0_RESET 0x00000000 +#define SIO_SPINLOCK0_MSB 31 +#define SIO_SPINLOCK0_LSB 0 +#define SIO_SPINLOCK0_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK1 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK1_OFFSET 0x00000104 +#define SIO_SPINLOCK1_BITS 0xffffffff +#define SIO_SPINLOCK1_RESET 0x00000000 +#define SIO_SPINLOCK1_MSB 31 +#define SIO_SPINLOCK1_LSB 0 +#define SIO_SPINLOCK1_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK2 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK2_OFFSET 0x00000108 +#define SIO_SPINLOCK2_BITS 0xffffffff +#define SIO_SPINLOCK2_RESET 0x00000000 +#define SIO_SPINLOCK2_MSB 31 +#define SIO_SPINLOCK2_LSB 0 +#define SIO_SPINLOCK2_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK3 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK3_OFFSET 0x0000010c +#define SIO_SPINLOCK3_BITS 0xffffffff +#define SIO_SPINLOCK3_RESET 0x00000000 +#define SIO_SPINLOCK3_MSB 31 +#define SIO_SPINLOCK3_LSB 0 +#define SIO_SPINLOCK3_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK4 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK4_OFFSET 0x00000110 +#define SIO_SPINLOCK4_BITS 0xffffffff +#define SIO_SPINLOCK4_RESET 0x00000000 +#define SIO_SPINLOCK4_MSB 31 +#define SIO_SPINLOCK4_LSB 0 +#define SIO_SPINLOCK4_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK5 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK5_OFFSET 0x00000114 +#define SIO_SPINLOCK5_BITS 0xffffffff +#define SIO_SPINLOCK5_RESET 0x00000000 +#define SIO_SPINLOCK5_MSB 31 +#define SIO_SPINLOCK5_LSB 0 +#define SIO_SPINLOCK5_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK6 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK6_OFFSET 0x00000118 +#define SIO_SPINLOCK6_BITS 0xffffffff +#define SIO_SPINLOCK6_RESET 0x00000000 +#define SIO_SPINLOCK6_MSB 31 +#define SIO_SPINLOCK6_LSB 0 +#define SIO_SPINLOCK6_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK7 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK7_OFFSET 0x0000011c +#define SIO_SPINLOCK7_BITS 0xffffffff +#define SIO_SPINLOCK7_RESET 0x00000000 +#define SIO_SPINLOCK7_MSB 31 +#define SIO_SPINLOCK7_LSB 0 +#define SIO_SPINLOCK7_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK8 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK8_OFFSET 0x00000120 +#define SIO_SPINLOCK8_BITS 0xffffffff +#define SIO_SPINLOCK8_RESET 0x00000000 +#define SIO_SPINLOCK8_MSB 31 +#define SIO_SPINLOCK8_LSB 0 +#define SIO_SPINLOCK8_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK9 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK9_OFFSET 0x00000124 +#define SIO_SPINLOCK9_BITS 0xffffffff +#define SIO_SPINLOCK9_RESET 0x00000000 +#define SIO_SPINLOCK9_MSB 31 +#define SIO_SPINLOCK9_LSB 0 +#define SIO_SPINLOCK9_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK10 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK10_OFFSET 0x00000128 +#define SIO_SPINLOCK10_BITS 0xffffffff +#define SIO_SPINLOCK10_RESET 0x00000000 +#define SIO_SPINLOCK10_MSB 31 +#define SIO_SPINLOCK10_LSB 0 +#define SIO_SPINLOCK10_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK11 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK11_OFFSET 0x0000012c +#define SIO_SPINLOCK11_BITS 0xffffffff +#define SIO_SPINLOCK11_RESET 0x00000000 +#define SIO_SPINLOCK11_MSB 31 +#define SIO_SPINLOCK11_LSB 0 +#define SIO_SPINLOCK11_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK12 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK12_OFFSET 0x00000130 +#define SIO_SPINLOCK12_BITS 0xffffffff +#define SIO_SPINLOCK12_RESET 0x00000000 +#define SIO_SPINLOCK12_MSB 31 +#define SIO_SPINLOCK12_LSB 0 +#define SIO_SPINLOCK12_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK13 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK13_OFFSET 0x00000134 +#define SIO_SPINLOCK13_BITS 0xffffffff +#define SIO_SPINLOCK13_RESET 0x00000000 +#define SIO_SPINLOCK13_MSB 31 +#define SIO_SPINLOCK13_LSB 0 +#define SIO_SPINLOCK13_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK14 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK14_OFFSET 0x00000138 +#define SIO_SPINLOCK14_BITS 0xffffffff +#define SIO_SPINLOCK14_RESET 0x00000000 +#define SIO_SPINLOCK14_MSB 31 +#define SIO_SPINLOCK14_LSB 0 +#define SIO_SPINLOCK14_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK15 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK15_OFFSET 0x0000013c +#define SIO_SPINLOCK15_BITS 0xffffffff +#define SIO_SPINLOCK15_RESET 0x00000000 +#define SIO_SPINLOCK15_MSB 31 +#define SIO_SPINLOCK15_LSB 0 +#define SIO_SPINLOCK15_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK16 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK16_OFFSET 0x00000140 +#define SIO_SPINLOCK16_BITS 0xffffffff +#define SIO_SPINLOCK16_RESET 0x00000000 +#define SIO_SPINLOCK16_MSB 31 +#define SIO_SPINLOCK16_LSB 0 +#define SIO_SPINLOCK16_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK17 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK17_OFFSET 0x00000144 +#define SIO_SPINLOCK17_BITS 0xffffffff +#define SIO_SPINLOCK17_RESET 0x00000000 +#define SIO_SPINLOCK17_MSB 31 +#define SIO_SPINLOCK17_LSB 0 +#define SIO_SPINLOCK17_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK18 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK18_OFFSET 0x00000148 +#define SIO_SPINLOCK18_BITS 0xffffffff +#define SIO_SPINLOCK18_RESET 0x00000000 +#define SIO_SPINLOCK18_MSB 31 +#define SIO_SPINLOCK18_LSB 0 +#define SIO_SPINLOCK18_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK19 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK19_OFFSET 0x0000014c +#define SIO_SPINLOCK19_BITS 0xffffffff +#define SIO_SPINLOCK19_RESET 0x00000000 +#define SIO_SPINLOCK19_MSB 31 +#define SIO_SPINLOCK19_LSB 0 +#define SIO_SPINLOCK19_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK20 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK20_OFFSET 0x00000150 +#define SIO_SPINLOCK20_BITS 0xffffffff +#define SIO_SPINLOCK20_RESET 0x00000000 +#define SIO_SPINLOCK20_MSB 31 +#define SIO_SPINLOCK20_LSB 0 +#define SIO_SPINLOCK20_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK21 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK21_OFFSET 0x00000154 +#define SIO_SPINLOCK21_BITS 0xffffffff +#define SIO_SPINLOCK21_RESET 0x00000000 +#define SIO_SPINLOCK21_MSB 31 +#define SIO_SPINLOCK21_LSB 0 +#define SIO_SPINLOCK21_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK22 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK22_OFFSET 0x00000158 +#define SIO_SPINLOCK22_BITS 0xffffffff +#define SIO_SPINLOCK22_RESET 0x00000000 +#define SIO_SPINLOCK22_MSB 31 +#define SIO_SPINLOCK22_LSB 0 +#define SIO_SPINLOCK22_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK23 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK23_OFFSET 0x0000015c +#define SIO_SPINLOCK23_BITS 0xffffffff +#define SIO_SPINLOCK23_RESET 0x00000000 +#define SIO_SPINLOCK23_MSB 31 +#define SIO_SPINLOCK23_LSB 0 +#define SIO_SPINLOCK23_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK24 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK24_OFFSET 0x00000160 +#define SIO_SPINLOCK24_BITS 0xffffffff +#define SIO_SPINLOCK24_RESET 0x00000000 +#define SIO_SPINLOCK24_MSB 31 +#define SIO_SPINLOCK24_LSB 0 +#define SIO_SPINLOCK24_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK25 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK25_OFFSET 0x00000164 +#define SIO_SPINLOCK25_BITS 0xffffffff +#define SIO_SPINLOCK25_RESET 0x00000000 +#define SIO_SPINLOCK25_MSB 31 +#define SIO_SPINLOCK25_LSB 0 +#define SIO_SPINLOCK25_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK26 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK26_OFFSET 0x00000168 +#define SIO_SPINLOCK26_BITS 0xffffffff +#define SIO_SPINLOCK26_RESET 0x00000000 +#define SIO_SPINLOCK26_MSB 31 +#define SIO_SPINLOCK26_LSB 0 +#define SIO_SPINLOCK26_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK27 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK27_OFFSET 0x0000016c +#define SIO_SPINLOCK27_BITS 0xffffffff +#define SIO_SPINLOCK27_RESET 0x00000000 +#define SIO_SPINLOCK27_MSB 31 +#define SIO_SPINLOCK27_LSB 0 +#define SIO_SPINLOCK27_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK28 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK28_OFFSET 0x00000170 +#define SIO_SPINLOCK28_BITS 0xffffffff +#define SIO_SPINLOCK28_RESET 0x00000000 +#define SIO_SPINLOCK28_MSB 31 +#define SIO_SPINLOCK28_LSB 0 +#define SIO_SPINLOCK28_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK29 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK29_OFFSET 0x00000174 +#define SIO_SPINLOCK29_BITS 0xffffffff +#define SIO_SPINLOCK29_RESET 0x00000000 +#define SIO_SPINLOCK29_MSB 31 +#define SIO_SPINLOCK29_LSB 0 +#define SIO_SPINLOCK29_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK30 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK30_OFFSET 0x00000178 +#define SIO_SPINLOCK30_BITS 0xffffffff +#define SIO_SPINLOCK30_RESET 0x00000000 +#define SIO_SPINLOCK30_MSB 31 +#define SIO_SPINLOCK30_LSB 0 +#define SIO_SPINLOCK30_ACCESS "RO" +// ============================================================================= +// Register : SIO_SPINLOCK31 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK31_OFFSET 0x0000017c +#define SIO_SPINLOCK31_BITS 0xffffffff +#define SIO_SPINLOCK31_RESET 0x00000000 +#define SIO_SPINLOCK31_MSB 31 +#define SIO_SPINLOCK31_LSB 0 +#define SIO_SPINLOCK31_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_SIO_DEFINED diff --git a/rp2040/hardware/regs/spi.h b/rp2040/hardware/regs/spi.h new file mode 100644 index 0000000..9670b83 --- /dev/null +++ b/rp2040/hardware/regs/spi.h @@ -0,0 +1,521 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SPI +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_SPI_DEFINED +#define HARDWARE_REGS_SPI_DEFINED +// ============================================================================= +// Register : SPI_SSPCR0 +// Description : Control register 0, SSPCR0 on page 3-4 +#define SPI_SSPCR0_OFFSET 0x00000000 +#define SPI_SSPCR0_BITS 0x0000ffff +#define SPI_SSPCR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SCR +// Description : Serial clock rate. The value SCR is used to generate the +// transmit and receive bit rate of the PrimeCell SSP. The bit +// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even +// value from 2-254, programmed through the SSPCPSR register and +// SCR is a value from 0-255. +#define SPI_SSPCR0_SCR_RESET 0x00 +#define SPI_SSPCR0_SCR_BITS 0x0000ff00 +#define SPI_SSPCR0_SCR_MSB 15 +#define SPI_SSPCR0_SCR_LSB 8 +#define SPI_SSPCR0_SCR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPH +// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. +// See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPH_RESET 0x0 +#define SPI_SSPCR0_SPH_BITS 0x00000080 +#define SPI_SSPCR0_SPH_MSB 7 +#define SPI_SSPCR0_SPH_LSB 7 +#define SPI_SSPCR0_SPH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPO +// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format +// only. See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPO_RESET 0x0 +#define SPI_SSPCR0_SPO_BITS 0x00000040 +#define SPI_SSPCR0_SPO_MSB 6 +#define SPI_SSPCR0_SPO_LSB 6 +#define SPI_SSPCR0_SPO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_FRF +// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous +// serial frame format. 10 National Microwire frame format. 11 +// Reserved, undefined operation. +#define SPI_SSPCR0_FRF_RESET 0x0 +#define SPI_SSPCR0_FRF_BITS 0x00000030 +#define SPI_SSPCR0_FRF_MSB 5 +#define SPI_SSPCR0_FRF_LSB 4 +#define SPI_SSPCR0_FRF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_DSS +// Description : Data Size Select: 0000 Reserved, undefined operation. 0001 +// Reserved, undefined operation. 0010 Reserved, undefined +// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. +// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit +// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. +// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. +#define SPI_SSPCR0_DSS_RESET 0x0 +#define SPI_SSPCR0_DSS_BITS 0x0000000f +#define SPI_SSPCR0_DSS_MSB 3 +#define SPI_SSPCR0_DSS_LSB 0 +#define SPI_SSPCR0_DSS_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPCR1 +// Description : Control register 1, SSPCR1 on page 3-5 +#define SPI_SSPCR1_OFFSET 0x00000004 +#define SPI_SSPCR1_BITS 0x0000000f +#define SPI_SSPCR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SOD +// Description : Slave-mode output disable. This bit is relevant only in the +// slave mode, MS=1. In multiple-slave systems, it is possible for +// an PrimeCell SSP master to broadcast a message to all slaves in +// the system while ensuring that only one slave drives data onto +// its serial output line. In such systems the RXD lines from +// multiple slaves could be tied together. To operate in such +// systems, the SOD bit can be set if the PrimeCell SSP slave is +// not supposed to drive the SSPTXD line: 0 SSP can drive the +// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD +// output in slave mode. +#define SPI_SSPCR1_SOD_RESET 0x0 +#define SPI_SSPCR1_SOD_BITS 0x00000008 +#define SPI_SSPCR1_SOD_MSB 3 +#define SPI_SSPCR1_SOD_LSB 3 +#define SPI_SSPCR1_SOD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_MS +// Description : Master or slave mode select. This bit can be modified only when +// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as +// master, default. 1 Device configured as slave. +#define SPI_SSPCR1_MS_RESET 0x0 +#define SPI_SSPCR1_MS_BITS 0x00000004 +#define SPI_SSPCR1_MS_MSB 2 +#define SPI_SSPCR1_MS_LSB 2 +#define SPI_SSPCR1_MS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SSE +// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP +// operation enabled. +#define SPI_SSPCR1_SSE_RESET 0x0 +#define SPI_SSPCR1_SSE_BITS 0x00000002 +#define SPI_SSPCR1_SSE_MSB 1 +#define SPI_SSPCR1_SSE_LSB 1 +#define SPI_SSPCR1_SSE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_LBM +// Description : Loop back mode: 0 Normal serial port operation enabled. 1 +// Output of transmit serial shifter is connected to input of +// receive serial shifter internally. +#define SPI_SSPCR1_LBM_RESET 0x0 +#define SPI_SSPCR1_LBM_BITS 0x00000001 +#define SPI_SSPCR1_LBM_MSB 0 +#define SPI_SSPCR1_LBM_LSB 0 +#define SPI_SSPCR1_LBM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPDR +// Description : Data register, SSPDR on page 3-6 +#define SPI_SSPDR_OFFSET 0x00000008 +#define SPI_SSPDR_BITS 0x0000ffff +#define SPI_SSPDR_RESET "-" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDR_DATA +// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. +// You must right-justify data when the PrimeCell SSP is +// programmed for a data size that is less than 16 bits. Unused +// bits at the top are ignored by transmit logic. The receive +// logic automatically right-justifies. +#define SPI_SSPDR_DATA_RESET "-" +#define SPI_SSPDR_DATA_BITS 0x0000ffff +#define SPI_SSPDR_DATA_MSB 15 +#define SPI_SSPDR_DATA_LSB 0 +#define SPI_SSPDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : SPI_SSPSR +// Description : Status register, SSPSR on page 3-7 +#define SPI_SSPSR_OFFSET 0x0000000c +#define SPI_SSPSR_BITS 0x0000001f +#define SPI_SSPSR_RESET 0x00000003 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_BSY +// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently +// transmitting and/or receiving a frame or the transmit FIFO is +// not empty. +#define SPI_SSPSR_BSY_RESET 0x0 +#define SPI_SSPSR_BSY_BITS 0x00000010 +#define SPI_SSPSR_BSY_MSB 4 +#define SPI_SSPSR_BSY_LSB 4 +#define SPI_SSPSR_BSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RFF +// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive +// FIFO is full. +#define SPI_SSPSR_RFF_RESET 0x0 +#define SPI_SSPSR_RFF_BITS 0x00000008 +#define SPI_SSPSR_RFF_MSB 3 +#define SPI_SSPSR_RFF_LSB 3 +#define SPI_SSPSR_RFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RNE +// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive +// FIFO is not empty. +#define SPI_SSPSR_RNE_RESET 0x0 +#define SPI_SSPSR_RNE_BITS 0x00000004 +#define SPI_SSPSR_RNE_MSB 2 +#define SPI_SSPSR_RNE_LSB 2 +#define SPI_SSPSR_RNE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TNF +// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit +// FIFO is not full. +#define SPI_SSPSR_TNF_RESET 0x1 +#define SPI_SSPSR_TNF_BITS 0x00000002 +#define SPI_SSPSR_TNF_MSB 1 +#define SPI_SSPSR_TNF_LSB 1 +#define SPI_SSPSR_TNF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TFE +// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 +// Transmit FIFO is empty. +#define SPI_SSPSR_TFE_RESET 0x1 +#define SPI_SSPSR_TFE_BITS 0x00000001 +#define SPI_SSPSR_TFE_MSB 0 +#define SPI_SSPSR_TFE_LSB 0 +#define SPI_SSPSR_TFE_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPCPSR +// Description : Clock prescale register, SSPCPSR on page 3-8 +#define SPI_SSPCPSR_OFFSET 0x00000010 +#define SPI_SSPCPSR_BITS 0x000000ff +#define SPI_SSPCPSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCPSR_CPSDVSR +// Description : Clock prescale divisor. Must be an even number from 2-254, +// depending on the frequency of SSPCLK. The least significant bit +// always returns zero on reads. +#define SPI_SSPCPSR_CPSDVSR_RESET 0x00 +#define SPI_SSPCPSR_CPSDVSR_BITS 0x000000ff +#define SPI_SSPCPSR_CPSDVSR_MSB 7 +#define SPI_SSPCPSR_CPSDVSR_LSB 0 +#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPIMSC +// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 +#define SPI_SSPIMSC_OFFSET 0x00000014 +#define SPI_SSPIMSC_BITS 0x0000000f +#define SPI_SSPIMSC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_TXIM +// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or +// less condition interrupt is masked. 1 Transmit FIFO half empty +// or less condition interrupt is not masked. +#define SPI_SSPIMSC_TXIM_RESET 0x0 +#define SPI_SSPIMSC_TXIM_BITS 0x00000008 +#define SPI_SSPIMSC_TXIM_MSB 3 +#define SPI_SSPIMSC_TXIM_LSB 3 +#define SPI_SSPIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RXIM +// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less +// condition interrupt is masked. 1 Receive FIFO half full or less +// condition interrupt is not masked. +#define SPI_SSPIMSC_RXIM_RESET 0x0 +#define SPI_SSPIMSC_RXIM_BITS 0x00000004 +#define SPI_SSPIMSC_RXIM_MSB 2 +#define SPI_SSPIMSC_RXIM_LSB 2 +#define SPI_SSPIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RTIM +// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no +// read prior to timeout period interrupt is masked. 1 Receive +// FIFO not empty and no read prior to timeout period interrupt is +// not masked. +#define SPI_SSPIMSC_RTIM_RESET 0x0 +#define SPI_SSPIMSC_RTIM_BITS 0x00000002 +#define SPI_SSPIMSC_RTIM_MSB 1 +#define SPI_SSPIMSC_RTIM_LSB 1 +#define SPI_SSPIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RORIM +// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while +// full condition interrupt is masked. 1 Receive FIFO written to +// while full condition interrupt is not masked. +#define SPI_SSPIMSC_RORIM_RESET 0x0 +#define SPI_SSPIMSC_RORIM_BITS 0x00000001 +#define SPI_SSPIMSC_RORIM_MSB 0 +#define SPI_SSPIMSC_RORIM_LSB 0 +#define SPI_SSPIMSC_RORIM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPRIS +// Description : Raw interrupt status register, SSPRIS on page 3-10 +#define SPI_SSPRIS_OFFSET 0x00000018 +#define SPI_SSPRIS_BITS 0x0000000f +#define SPI_SSPRIS_RESET 0x00000008 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_TXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPTXINTR interrupt +#define SPI_SSPRIS_TXRIS_RESET 0x1 +#define SPI_SSPRIS_TXRIS_BITS 0x00000008 +#define SPI_SSPRIS_TXRIS_MSB 3 +#define SPI_SSPRIS_TXRIS_LSB 3 +#define SPI_SSPRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRXINTR interrupt +#define SPI_SSPRIS_RXRIS_RESET 0x0 +#define SPI_SSPRIS_RXRIS_BITS 0x00000004 +#define SPI_SSPRIS_RXRIS_MSB 2 +#define SPI_SSPRIS_RXRIS_LSB 2 +#define SPI_SSPRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RTRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRTINTR interrupt +#define SPI_SSPRIS_RTRIS_RESET 0x0 +#define SPI_SSPRIS_RTRIS_BITS 0x00000002 +#define SPI_SSPRIS_RTRIS_MSB 1 +#define SPI_SSPRIS_RTRIS_LSB 1 +#define SPI_SSPRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RORRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRORINTR interrupt +#define SPI_SSPRIS_RORRIS_RESET 0x0 +#define SPI_SSPRIS_RORRIS_BITS 0x00000001 +#define SPI_SSPRIS_RORRIS_MSB 0 +#define SPI_SSPRIS_RORRIS_LSB 0 +#define SPI_SSPRIS_RORRIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPMIS +// Description : Masked interrupt status register, SSPMIS on page 3-11 +#define SPI_SSPMIS_OFFSET 0x0000001c +#define SPI_SSPMIS_BITS 0x0000000f +#define SPI_SSPMIS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_TXMIS +// Description : Gives the transmit FIFO masked interrupt state, after masking, +// of the SSPTXINTR interrupt +#define SPI_SSPMIS_TXMIS_RESET 0x0 +#define SPI_SSPMIS_TXMIS_BITS 0x00000008 +#define SPI_SSPMIS_TXMIS_MSB 3 +#define SPI_SSPMIS_TXMIS_LSB 3 +#define SPI_SSPMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RXMIS +// Description : Gives the receive FIFO masked interrupt state, after masking, +// of the SSPRXINTR interrupt +#define SPI_SSPMIS_RXMIS_RESET 0x0 +#define SPI_SSPMIS_RXMIS_BITS 0x00000004 +#define SPI_SSPMIS_RXMIS_MSB 2 +#define SPI_SSPMIS_RXMIS_LSB 2 +#define SPI_SSPMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RTMIS +// Description : Gives the receive timeout masked interrupt state, after +// masking, of the SSPRTINTR interrupt +#define SPI_SSPMIS_RTMIS_RESET 0x0 +#define SPI_SSPMIS_RTMIS_BITS 0x00000002 +#define SPI_SSPMIS_RTMIS_MSB 1 +#define SPI_SSPMIS_RTMIS_LSB 1 +#define SPI_SSPMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RORMIS +// Description : Gives the receive over run masked interrupt status, after +// masking, of the SSPRORINTR interrupt +#define SPI_SSPMIS_RORMIS_RESET 0x0 +#define SPI_SSPMIS_RORMIS_BITS 0x00000001 +#define SPI_SSPMIS_RORMIS_MSB 0 +#define SPI_SSPMIS_RORMIS_LSB 0 +#define SPI_SSPMIS_RORMIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPICR +// Description : Interrupt clear register, SSPICR on page 3-11 +#define SPI_SSPICR_OFFSET 0x00000020 +#define SPI_SSPICR_BITS 0x00000003 +#define SPI_SSPICR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RTIC +// Description : Clears the SSPRTINTR interrupt +#define SPI_SSPICR_RTIC_RESET 0x0 +#define SPI_SSPICR_RTIC_BITS 0x00000002 +#define SPI_SSPICR_RTIC_MSB 1 +#define SPI_SSPICR_RTIC_LSB 1 +#define SPI_SSPICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RORIC +// Description : Clears the SSPRORINTR interrupt +#define SPI_SSPICR_RORIC_RESET 0x0 +#define SPI_SSPICR_RORIC_BITS 0x00000001 +#define SPI_SSPICR_RORIC_MSB 0 +#define SPI_SSPICR_RORIC_LSB 0 +#define SPI_SSPICR_RORIC_ACCESS "WC" +// ============================================================================= +// Register : SPI_SSPDMACR +// Description : DMA control register, SSPDMACR on page 3-12 +#define SPI_SSPDMACR_OFFSET 0x00000024 +#define SPI_SSPDMACR_BITS 0x00000003 +#define SPI_SSPDMACR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_TXDMAE +// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define SPI_SSPDMACR_TXDMAE_RESET 0x0 +#define SPI_SSPDMACR_TXDMAE_BITS 0x00000002 +#define SPI_SSPDMACR_TXDMAE_MSB 1 +#define SPI_SSPDMACR_TXDMAE_LSB 1 +#define SPI_SSPDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_RXDMAE +// Description : Receive DMA Enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define SPI_SSPDMACR_RXDMAE_RESET 0x0 +#define SPI_SSPDMACR_RXDMAE_BITS 0x00000001 +#define SPI_SSPDMACR_RXDMAE_MSB 0 +#define SPI_SSPDMACR_RXDMAE_LSB 0 +#define SPI_SSPDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPPERIPHID0 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID0_OFFSET 0x00000fe0 +#define SPI_SSPPERIPHID0_BITS 0x000000ff +#define SPI_SSPPERIPHID0_RESET 0x00000022 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x22 +#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET 0x22 +#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS 0x000000ff +#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB 7 +#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB 0 +#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID1 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID1_OFFSET 0x00000fe4 +#define SPI_SSPPERIPHID1_BITS 0x000000ff +#define SPI_SSPPERIPHID1_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define SPI_SSPPERIPHID1_DESIGNER0_RESET 0x1 +#define SPI_SSPPERIPHID1_DESIGNER0_BITS 0x000000f0 +#define SPI_SSPPERIPHID1_DESIGNER0_MSB 7 +#define SPI_SSPPERIPHID1_DESIGNER0_LSB 4 +#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET 0x0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS 0x0000000f +#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB 3 +#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB 0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID2 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID2_OFFSET 0x00000fe8 +#define SPI_SSPPERIPHID2_BITS 0x000000ff +#define SPI_SSPPERIPHID2_RESET 0x00000034 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_REVISION +// Description : These bits return the peripheral revision +#define SPI_SSPPERIPHID2_REVISION_RESET 0x3 +#define SPI_SSPPERIPHID2_REVISION_BITS 0x000000f0 +#define SPI_SSPPERIPHID2_REVISION_MSB 7 +#define SPI_SSPPERIPHID2_REVISION_LSB 4 +#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define SPI_SSPPERIPHID2_DESIGNER1_RESET 0x4 +#define SPI_SSPPERIPHID2_DESIGNER1_BITS 0x0000000f +#define SPI_SSPPERIPHID2_DESIGNER1_MSB 3 +#define SPI_SSPPERIPHID2_DESIGNER1_LSB 0 +#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID3 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID3_OFFSET 0x00000fec +#define SPI_SSPPERIPHID3_BITS 0x000000ff +#define SPI_SSPPERIPHID3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define SPI_SSPPERIPHID3_CONFIGURATION_RESET 0x00 +#define SPI_SSPPERIPHID3_CONFIGURATION_BITS 0x000000ff +#define SPI_SSPPERIPHID3_CONFIGURATION_MSB 7 +#define SPI_SSPPERIPHID3_CONFIGURATION_LSB 0 +#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID0 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID0_OFFSET 0x00000ff0 +#define SPI_SSPPCELLID0_BITS 0x000000ff +#define SPI_SSPPCELLID0_RESET 0x0000000d +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID0_SSPPCELLID0 +// Description : These bits read back as 0x0D +#define SPI_SSPPCELLID0_SSPPCELLID0_RESET 0x0d +#define SPI_SSPPCELLID0_SSPPCELLID0_BITS 0x000000ff +#define SPI_SSPPCELLID0_SSPPCELLID0_MSB 7 +#define SPI_SSPPCELLID0_SSPPCELLID0_LSB 0 +#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID1 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID1_OFFSET 0x00000ff4 +#define SPI_SSPPCELLID1_BITS 0x000000ff +#define SPI_SSPPCELLID1_RESET 0x000000f0 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID1_SSPPCELLID1 +// Description : These bits read back as 0xF0 +#define SPI_SSPPCELLID1_SSPPCELLID1_RESET 0xf0 +#define SPI_SSPPCELLID1_SSPPCELLID1_BITS 0x000000ff +#define SPI_SSPPCELLID1_SSPPCELLID1_MSB 7 +#define SPI_SSPPCELLID1_SSPPCELLID1_LSB 0 +#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID2 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID2_OFFSET 0x00000ff8 +#define SPI_SSPPCELLID2_BITS 0x000000ff +#define SPI_SSPPCELLID2_RESET 0x00000005 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID2_SSPPCELLID2 +// Description : These bits read back as 0x05 +#define SPI_SSPPCELLID2_SSPPCELLID2_RESET 0x05 +#define SPI_SSPPCELLID2_SSPPCELLID2_BITS 0x000000ff +#define SPI_SSPPCELLID2_SSPPCELLID2_MSB 7 +#define SPI_SSPPCELLID2_SSPPCELLID2_LSB 0 +#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID3 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID3_OFFSET 0x00000ffc +#define SPI_SSPPCELLID3_BITS 0x000000ff +#define SPI_SSPPCELLID3_RESET 0x000000b1 +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID3_SSPPCELLID3 +// Description : These bits read back as 0xB1 +#define SPI_SSPPCELLID3_SSPPCELLID3_RESET 0xb1 +#define SPI_SSPPCELLID3_SSPPCELLID3_BITS 0x000000ff +#define SPI_SSPPCELLID3_SSPPCELLID3_MSB 7 +#define SPI_SSPPCELLID3_SSPPCELLID3_LSB 0 +#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_SPI_DEFINED diff --git a/rp2040/hardware/regs/ssi.h b/rp2040/hardware/regs/ssi.h new file mode 100644 index 0000000..04eecca --- /dev/null +++ b/rp2040/hardware/regs/ssi.h @@ -0,0 +1,809 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SSI +// Version : 1 +// Bus type : apb +// Description : DW_apb_ssi has the following features: +// * APB interface – Allows for easy integration into a +// DesignWare Synthesizable Components for AMBA 2 +// implementation. +// * APB3 and APB4 protocol support. +// * Scalable APB data bus width – Supports APB data bus widths +// of 8, 16, and 32 bits. +// * Serial-master or serial-slave operation – Enables serial +// communication with serial-master or serial-slave peripheral +// devices. +// * Programmable Dual/Quad/Octal SPI support in Master Mode. +// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - +// Enables the DW_apb_ssi master to perform operations with the +// device in DDR and RDS modes when working in Dual/Quad/Octal +// mode of operation. +// * Data Mask Support - Enables the DW_apb_ssi to selectively +// update the bytes in the device. This feature is applicable +// only in enhanced SPI modes. +// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi +// master to behave as a memory mapped I/O and fetches the data +// from the device based on the APB read request. This feature +// is applicable only in enhanced SPI modes. +// * DMA Controller Interface – Enables the DW_apb_ssi to +// interface to a DMA controller over the bus using a +// handshaking interface for transfer requests. +// * Independent masking of interrupts – Master collision, +// transmit FIFO overflow, transmit FIFO empty, receive FIFO +// full, receive FIFO underflow, and receive FIFO overflow +// interrupts can all be masked independently. +// * Multi-master contention detection – Informs the processor +// of multiple serial-master accesses on the serial bus. +// * Bypass of meta-stability flip-flops for synchronous clocks +// – When the APB clock (pclk) and the DW_apb_ssi serial clock +// (ssi_clk) are synchronous, meta-stable flip-flops are not +// used when transferring control signals across these clock +// domains. +// * Programmable delay on the sample time of the received +// serial data bit (rxd); enables programmable control of +// routing delays resulting in higher serial data-bit rates. +// * Programmable features: +// - Serial interface operation – Choice of Motorola SPI, Texas +// Instruments Synchronous Serial Protocol or National +// Semiconductor Microwire. +// - Clock bit-rate – Dynamic control of the serial bit rate of +// the data transfer; used in only serial-master mode of +// operation. +// - Data Item size (4 to 32 bits) – Item size of each data +// transfer under the control of the programmer. +// * Configured features: +// - FIFO depth – 16 words deep. The FIFO width is fixed at 32 +// bits. +// - 1 slave select output. +// - Hardware slave-select – Dedicated hardware slave-select +// line. +// - Combined interrupt line - one combined interrupt line from +// the DW_apb_ssi to the interrupt controller. +// - Interrupt polarity – active high interrupt lines. +// - Serial clock polarity – low serial-clock polarity directly +// after reset. +// - Serial clock phase – capture on first edge of serial-clock +// directly after reset. +// ============================================================================= +#ifndef HARDWARE_REGS_SSI_DEFINED +#define HARDWARE_REGS_SSI_DEFINED +// ============================================================================= +// Register : SSI_CTRLR0 +// Description : Control register 0 +#define SSI_CTRLR0_OFFSET 0x00000000 +#define SSI_CTRLR0_BITS 0x017fffff +#define SSI_CTRLR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SSTE +// Description : Slave select toggle enable +#define SSI_CTRLR0_SSTE_RESET 0x0 +#define SSI_CTRLR0_SSTE_BITS 0x01000000 +#define SSI_CTRLR0_SSTE_MSB 24 +#define SSI_CTRLR0_SSTE_LSB 24 +#define SSI_CTRLR0_SSTE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SPI_FRF +// Description : SPI frame format +// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, +// full-duplex +// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex +// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex +#define SSI_CTRLR0_SPI_FRF_RESET 0x0 +#define SSI_CTRLR0_SPI_FRF_BITS 0x00600000 +#define SSI_CTRLR0_SPI_FRF_MSB 22 +#define SSI_CTRLR0_SPI_FRF_LSB 21 +#define SSI_CTRLR0_SPI_FRF_ACCESS "RW" +#define SSI_CTRLR0_SPI_FRF_VALUE_STD 0x0 +#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL 0x1 +#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD 0x2 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_DFS_32 +// Description : Data frame size in 32b transfer mode +// Value of n -> n+1 clocks per frame. +#define SSI_CTRLR0_DFS_32_RESET 0x00 +#define SSI_CTRLR0_DFS_32_BITS 0x001f0000 +#define SSI_CTRLR0_DFS_32_MSB 20 +#define SSI_CTRLR0_DFS_32_LSB 16 +#define SSI_CTRLR0_DFS_32_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_CFS +// Description : Control frame size +// Value of n -> n+1 clocks per frame. +#define SSI_CTRLR0_CFS_RESET 0x0 +#define SSI_CTRLR0_CFS_BITS 0x0000f000 +#define SSI_CTRLR0_CFS_MSB 15 +#define SSI_CTRLR0_CFS_LSB 12 +#define SSI_CTRLR0_CFS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SRL +// Description : Shift register loop (test mode) +#define SSI_CTRLR0_SRL_RESET 0x0 +#define SSI_CTRLR0_SRL_BITS 0x00000800 +#define SSI_CTRLR0_SRL_MSB 11 +#define SSI_CTRLR0_SRL_LSB 11 +#define SSI_CTRLR0_SRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SLV_OE +// Description : Slave output enable +#define SSI_CTRLR0_SLV_OE_RESET 0x0 +#define SSI_CTRLR0_SLV_OE_BITS 0x00000400 +#define SSI_CTRLR0_SLV_OE_MSB 10 +#define SSI_CTRLR0_SLV_OE_LSB 10 +#define SSI_CTRLR0_SLV_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_TMOD +// Description : Transfer mode +// 0x0 -> Both transmit and receive +// 0x1 -> Transmit only (not for FRF == 0, standard SPI mode) +// 0x2 -> Receive only (not for FRF == 0, standard SPI mode) +// 0x3 -> EEPROM read mode (TX then RX; RX starts after control +// data TX'd) +#define SSI_CTRLR0_TMOD_RESET 0x0 +#define SSI_CTRLR0_TMOD_BITS 0x00000300 +#define SSI_CTRLR0_TMOD_MSB 9 +#define SSI_CTRLR0_TMOD_LSB 8 +#define SSI_CTRLR0_TMOD_ACCESS "RW" +#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX 0x0 +#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY 0x1 +#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY 0x2 +#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ 0x3 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SCPOL +// Description : Serial clock polarity +#define SSI_CTRLR0_SCPOL_RESET 0x0 +#define SSI_CTRLR0_SCPOL_BITS 0x00000080 +#define SSI_CTRLR0_SCPOL_MSB 7 +#define SSI_CTRLR0_SCPOL_LSB 7 +#define SSI_CTRLR0_SCPOL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_SCPH +// Description : Serial clock phase +#define SSI_CTRLR0_SCPH_RESET 0x0 +#define SSI_CTRLR0_SCPH_BITS 0x00000040 +#define SSI_CTRLR0_SCPH_MSB 6 +#define SSI_CTRLR0_SCPH_LSB 6 +#define SSI_CTRLR0_SCPH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_FRF +// Description : Frame format +#define SSI_CTRLR0_FRF_RESET 0x0 +#define SSI_CTRLR0_FRF_BITS 0x00000030 +#define SSI_CTRLR0_FRF_MSB 5 +#define SSI_CTRLR0_FRF_LSB 4 +#define SSI_CTRLR0_FRF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR0_DFS +// Description : Data frame size +#define SSI_CTRLR0_DFS_RESET 0x0 +#define SSI_CTRLR0_DFS_BITS 0x0000000f +#define SSI_CTRLR0_DFS_MSB 3 +#define SSI_CTRLR0_DFS_LSB 0 +#define SSI_CTRLR0_DFS_ACCESS "RW" +// ============================================================================= +// Register : SSI_CTRLR1 +// Description : Master Control register 1 +#define SSI_CTRLR1_OFFSET 0x00000004 +#define SSI_CTRLR1_BITS 0x0000ffff +#define SSI_CTRLR1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_CTRLR1_NDF +// Description : Number of data frames +#define SSI_CTRLR1_NDF_RESET 0x0000 +#define SSI_CTRLR1_NDF_BITS 0x0000ffff +#define SSI_CTRLR1_NDF_MSB 15 +#define SSI_CTRLR1_NDF_LSB 0 +#define SSI_CTRLR1_NDF_ACCESS "RW" +// ============================================================================= +// Register : SSI_SSIENR +// Description : SSI Enable +#define SSI_SSIENR_OFFSET 0x00000008 +#define SSI_SSIENR_BITS 0x00000001 +#define SSI_SSIENR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_SSIENR_SSI_EN +// Description : SSI enable +#define SSI_SSIENR_SSI_EN_RESET 0x0 +#define SSI_SSIENR_SSI_EN_BITS 0x00000001 +#define SSI_SSIENR_SSI_EN_MSB 0 +#define SSI_SSIENR_SSI_EN_LSB 0 +#define SSI_SSIENR_SSI_EN_ACCESS "RW" +// ============================================================================= +// Register : SSI_MWCR +// Description : Microwire Control +#define SSI_MWCR_OFFSET 0x0000000c +#define SSI_MWCR_BITS 0x00000007 +#define SSI_MWCR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_MWCR_MHS +// Description : Microwire handshaking +#define SSI_MWCR_MHS_RESET 0x0 +#define SSI_MWCR_MHS_BITS 0x00000004 +#define SSI_MWCR_MHS_MSB 2 +#define SSI_MWCR_MHS_LSB 2 +#define SSI_MWCR_MHS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_MWCR_MDD +// Description : Microwire control +#define SSI_MWCR_MDD_RESET 0x0 +#define SSI_MWCR_MDD_BITS 0x00000002 +#define SSI_MWCR_MDD_MSB 1 +#define SSI_MWCR_MDD_LSB 1 +#define SSI_MWCR_MDD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_MWCR_MWMOD +// Description : Microwire transfer mode +#define SSI_MWCR_MWMOD_RESET 0x0 +#define SSI_MWCR_MWMOD_BITS 0x00000001 +#define SSI_MWCR_MWMOD_MSB 0 +#define SSI_MWCR_MWMOD_LSB 0 +#define SSI_MWCR_MWMOD_ACCESS "RW" +// ============================================================================= +// Register : SSI_SER +// Description : Slave enable +// For each bit: +// 0 -> slave not selected +// 1 -> slave selected +#define SSI_SER_OFFSET 0x00000010 +#define SSI_SER_BITS 0x00000001 +#define SSI_SER_RESET 0x00000000 +#define SSI_SER_MSB 0 +#define SSI_SER_LSB 0 +#define SSI_SER_ACCESS "RW" +// ============================================================================= +// Register : SSI_BAUDR +// Description : Baud rate +#define SSI_BAUDR_OFFSET 0x00000014 +#define SSI_BAUDR_BITS 0x0000ffff +#define SSI_BAUDR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_BAUDR_SCKDV +// Description : SSI clock divider +#define SSI_BAUDR_SCKDV_RESET 0x0000 +#define SSI_BAUDR_SCKDV_BITS 0x0000ffff +#define SSI_BAUDR_SCKDV_MSB 15 +#define SSI_BAUDR_SCKDV_LSB 0 +#define SSI_BAUDR_SCKDV_ACCESS "RW" +// ============================================================================= +// Register : SSI_TXFTLR +// Description : TX FIFO threshold level +#define SSI_TXFTLR_OFFSET 0x00000018 +#define SSI_TXFTLR_BITS 0x000000ff +#define SSI_TXFTLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_TXFTLR_TFT +// Description : Transmit FIFO threshold +#define SSI_TXFTLR_TFT_RESET 0x00 +#define SSI_TXFTLR_TFT_BITS 0x000000ff +#define SSI_TXFTLR_TFT_MSB 7 +#define SSI_TXFTLR_TFT_LSB 0 +#define SSI_TXFTLR_TFT_ACCESS "RW" +// ============================================================================= +// Register : SSI_RXFTLR +// Description : RX FIFO threshold level +#define SSI_RXFTLR_OFFSET 0x0000001c +#define SSI_RXFTLR_BITS 0x000000ff +#define SSI_RXFTLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RXFTLR_RFT +// Description : Receive FIFO threshold +#define SSI_RXFTLR_RFT_RESET 0x00 +#define SSI_RXFTLR_RFT_BITS 0x000000ff +#define SSI_RXFTLR_RFT_MSB 7 +#define SSI_RXFTLR_RFT_LSB 0 +#define SSI_RXFTLR_RFT_ACCESS "RW" +// ============================================================================= +// Register : SSI_TXFLR +// Description : TX FIFO level +#define SSI_TXFLR_OFFSET 0x00000020 +#define SSI_TXFLR_BITS 0x000000ff +#define SSI_TXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_TXFLR_TFTFL +// Description : Transmit FIFO level +#define SSI_TXFLR_TFTFL_RESET 0x00 +#define SSI_TXFLR_TFTFL_BITS 0x000000ff +#define SSI_TXFLR_TFTFL_MSB 7 +#define SSI_TXFLR_TFTFL_LSB 0 +#define SSI_TXFLR_TFTFL_ACCESS "RO" +// ============================================================================= +// Register : SSI_RXFLR +// Description : RX FIFO level +#define SSI_RXFLR_OFFSET 0x00000024 +#define SSI_RXFLR_BITS 0x000000ff +#define SSI_RXFLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RXFLR_RXTFL +// Description : Receive FIFO level +#define SSI_RXFLR_RXTFL_RESET 0x00 +#define SSI_RXFLR_RXTFL_BITS 0x000000ff +#define SSI_RXFLR_RXTFL_MSB 7 +#define SSI_RXFLR_RXTFL_LSB 0 +#define SSI_RXFLR_RXTFL_ACCESS "RO" +// ============================================================================= +// Register : SSI_SR +// Description : Status register +#define SSI_SR_OFFSET 0x00000028 +#define SSI_SR_BITS 0x0000007f +#define SSI_SR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_SR_DCOL +// Description : Data collision error +#define SSI_SR_DCOL_RESET 0x0 +#define SSI_SR_DCOL_BITS 0x00000040 +#define SSI_SR_DCOL_MSB 6 +#define SSI_SR_DCOL_LSB 6 +#define SSI_SR_DCOL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_TXE +// Description : Transmission error +#define SSI_SR_TXE_RESET 0x0 +#define SSI_SR_TXE_BITS 0x00000020 +#define SSI_SR_TXE_MSB 5 +#define SSI_SR_TXE_LSB 5 +#define SSI_SR_TXE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_RFF +// Description : Receive FIFO full +#define SSI_SR_RFF_RESET 0x0 +#define SSI_SR_RFF_BITS 0x00000010 +#define SSI_SR_RFF_MSB 4 +#define SSI_SR_RFF_LSB 4 +#define SSI_SR_RFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_RFNE +// Description : Receive FIFO not empty +#define SSI_SR_RFNE_RESET 0x0 +#define SSI_SR_RFNE_BITS 0x00000008 +#define SSI_SR_RFNE_MSB 3 +#define SSI_SR_RFNE_LSB 3 +#define SSI_SR_RFNE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_TFE +// Description : Transmit FIFO empty +#define SSI_SR_TFE_RESET 0x0 +#define SSI_SR_TFE_BITS 0x00000004 +#define SSI_SR_TFE_MSB 2 +#define SSI_SR_TFE_LSB 2 +#define SSI_SR_TFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_TFNF +// Description : Transmit FIFO not full +#define SSI_SR_TFNF_RESET 0x0 +#define SSI_SR_TFNF_BITS 0x00000002 +#define SSI_SR_TFNF_MSB 1 +#define SSI_SR_TFNF_LSB 1 +#define SSI_SR_TFNF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_SR_BUSY +// Description : SSI busy flag +#define SSI_SR_BUSY_RESET 0x0 +#define SSI_SR_BUSY_BITS 0x00000001 +#define SSI_SR_BUSY_MSB 0 +#define SSI_SR_BUSY_LSB 0 +#define SSI_SR_BUSY_ACCESS "RO" +// ============================================================================= +// Register : SSI_IMR +// Description : Interrupt mask +#define SSI_IMR_OFFSET 0x0000002c +#define SSI_IMR_BITS 0x0000003f +#define SSI_IMR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_MSTIM +// Description : Multi-master contention interrupt mask +#define SSI_IMR_MSTIM_RESET 0x0 +#define SSI_IMR_MSTIM_BITS 0x00000020 +#define SSI_IMR_MSTIM_MSB 5 +#define SSI_IMR_MSTIM_LSB 5 +#define SSI_IMR_MSTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_RXFIM +// Description : Receive FIFO full interrupt mask +#define SSI_IMR_RXFIM_RESET 0x0 +#define SSI_IMR_RXFIM_BITS 0x00000010 +#define SSI_IMR_RXFIM_MSB 4 +#define SSI_IMR_RXFIM_LSB 4 +#define SSI_IMR_RXFIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_RXOIM +// Description : Receive FIFO overflow interrupt mask +#define SSI_IMR_RXOIM_RESET 0x0 +#define SSI_IMR_RXOIM_BITS 0x00000008 +#define SSI_IMR_RXOIM_MSB 3 +#define SSI_IMR_RXOIM_LSB 3 +#define SSI_IMR_RXOIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_RXUIM +// Description : Receive FIFO underflow interrupt mask +#define SSI_IMR_RXUIM_RESET 0x0 +#define SSI_IMR_RXUIM_BITS 0x00000004 +#define SSI_IMR_RXUIM_MSB 2 +#define SSI_IMR_RXUIM_LSB 2 +#define SSI_IMR_RXUIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_TXOIM +// Description : Transmit FIFO overflow interrupt mask +#define SSI_IMR_TXOIM_RESET 0x0 +#define SSI_IMR_TXOIM_BITS 0x00000002 +#define SSI_IMR_TXOIM_MSB 1 +#define SSI_IMR_TXOIM_LSB 1 +#define SSI_IMR_TXOIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_IMR_TXEIM +// Description : Transmit FIFO empty interrupt mask +#define SSI_IMR_TXEIM_RESET 0x0 +#define SSI_IMR_TXEIM_BITS 0x00000001 +#define SSI_IMR_TXEIM_MSB 0 +#define SSI_IMR_TXEIM_LSB 0 +#define SSI_IMR_TXEIM_ACCESS "RW" +// ============================================================================= +// Register : SSI_ISR +// Description : Interrupt status +#define SSI_ISR_OFFSET 0x00000030 +#define SSI_ISR_BITS 0x0000003f +#define SSI_ISR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_MSTIS +// Description : Multi-master contention interrupt status +#define SSI_ISR_MSTIS_RESET 0x0 +#define SSI_ISR_MSTIS_BITS 0x00000020 +#define SSI_ISR_MSTIS_MSB 5 +#define SSI_ISR_MSTIS_LSB 5 +#define SSI_ISR_MSTIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_RXFIS +// Description : Receive FIFO full interrupt status +#define SSI_ISR_RXFIS_RESET 0x0 +#define SSI_ISR_RXFIS_BITS 0x00000010 +#define SSI_ISR_RXFIS_MSB 4 +#define SSI_ISR_RXFIS_LSB 4 +#define SSI_ISR_RXFIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_RXOIS +// Description : Receive FIFO overflow interrupt status +#define SSI_ISR_RXOIS_RESET 0x0 +#define SSI_ISR_RXOIS_BITS 0x00000008 +#define SSI_ISR_RXOIS_MSB 3 +#define SSI_ISR_RXOIS_LSB 3 +#define SSI_ISR_RXOIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_RXUIS +// Description : Receive FIFO underflow interrupt status +#define SSI_ISR_RXUIS_RESET 0x0 +#define SSI_ISR_RXUIS_BITS 0x00000004 +#define SSI_ISR_RXUIS_MSB 2 +#define SSI_ISR_RXUIS_LSB 2 +#define SSI_ISR_RXUIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_TXOIS +// Description : Transmit FIFO overflow interrupt status +#define SSI_ISR_TXOIS_RESET 0x0 +#define SSI_ISR_TXOIS_BITS 0x00000002 +#define SSI_ISR_TXOIS_MSB 1 +#define SSI_ISR_TXOIS_LSB 1 +#define SSI_ISR_TXOIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_ISR_TXEIS +// Description : Transmit FIFO empty interrupt status +#define SSI_ISR_TXEIS_RESET 0x0 +#define SSI_ISR_TXEIS_BITS 0x00000001 +#define SSI_ISR_TXEIS_MSB 0 +#define SSI_ISR_TXEIS_LSB 0 +#define SSI_ISR_TXEIS_ACCESS "RO" +// ============================================================================= +// Register : SSI_RISR +// Description : Raw interrupt status +#define SSI_RISR_OFFSET 0x00000034 +#define SSI_RISR_BITS 0x0000003f +#define SSI_RISR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_MSTIR +// Description : Multi-master contention raw interrupt status +#define SSI_RISR_MSTIR_RESET 0x0 +#define SSI_RISR_MSTIR_BITS 0x00000020 +#define SSI_RISR_MSTIR_MSB 5 +#define SSI_RISR_MSTIR_LSB 5 +#define SSI_RISR_MSTIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_RXFIR +// Description : Receive FIFO full raw interrupt status +#define SSI_RISR_RXFIR_RESET 0x0 +#define SSI_RISR_RXFIR_BITS 0x00000010 +#define SSI_RISR_RXFIR_MSB 4 +#define SSI_RISR_RXFIR_LSB 4 +#define SSI_RISR_RXFIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_RXOIR +// Description : Receive FIFO overflow raw interrupt status +#define SSI_RISR_RXOIR_RESET 0x0 +#define SSI_RISR_RXOIR_BITS 0x00000008 +#define SSI_RISR_RXOIR_MSB 3 +#define SSI_RISR_RXOIR_LSB 3 +#define SSI_RISR_RXOIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_RXUIR +// Description : Receive FIFO underflow raw interrupt status +#define SSI_RISR_RXUIR_RESET 0x0 +#define SSI_RISR_RXUIR_BITS 0x00000004 +#define SSI_RISR_RXUIR_MSB 2 +#define SSI_RISR_RXUIR_LSB 2 +#define SSI_RISR_RXUIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_TXOIR +// Description : Transmit FIFO overflow raw interrupt status +#define SSI_RISR_TXOIR_RESET 0x0 +#define SSI_RISR_TXOIR_BITS 0x00000002 +#define SSI_RISR_TXOIR_MSB 1 +#define SSI_RISR_TXOIR_LSB 1 +#define SSI_RISR_TXOIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SSI_RISR_TXEIR +// Description : Transmit FIFO empty raw interrupt status +#define SSI_RISR_TXEIR_RESET 0x0 +#define SSI_RISR_TXEIR_BITS 0x00000001 +#define SSI_RISR_TXEIR_MSB 0 +#define SSI_RISR_TXEIR_LSB 0 +#define SSI_RISR_TXEIR_ACCESS "RO" +// ============================================================================= +// Register : SSI_TXOICR +// Description : TX FIFO overflow interrupt clear +// Clear-on-read transmit FIFO overflow interrupt +#define SSI_TXOICR_OFFSET 0x00000038 +#define SSI_TXOICR_BITS 0x00000001 +#define SSI_TXOICR_RESET 0x00000000 +#define SSI_TXOICR_MSB 0 +#define SSI_TXOICR_LSB 0 +#define SSI_TXOICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_RXOICR +// Description : RX FIFO overflow interrupt clear +// Clear-on-read receive FIFO overflow interrupt +#define SSI_RXOICR_OFFSET 0x0000003c +#define SSI_RXOICR_BITS 0x00000001 +#define SSI_RXOICR_RESET 0x00000000 +#define SSI_RXOICR_MSB 0 +#define SSI_RXOICR_LSB 0 +#define SSI_RXOICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_RXUICR +// Description : RX FIFO underflow interrupt clear +// Clear-on-read receive FIFO underflow interrupt +#define SSI_RXUICR_OFFSET 0x00000040 +#define SSI_RXUICR_BITS 0x00000001 +#define SSI_RXUICR_RESET 0x00000000 +#define SSI_RXUICR_MSB 0 +#define SSI_RXUICR_LSB 0 +#define SSI_RXUICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_MSTICR +// Description : Multi-master interrupt clear +// Clear-on-read multi-master contention interrupt +#define SSI_MSTICR_OFFSET 0x00000044 +#define SSI_MSTICR_BITS 0x00000001 +#define SSI_MSTICR_RESET 0x00000000 +#define SSI_MSTICR_MSB 0 +#define SSI_MSTICR_LSB 0 +#define SSI_MSTICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_ICR +// Description : Interrupt clear +// Clear-on-read all active interrupts +#define SSI_ICR_OFFSET 0x00000048 +#define SSI_ICR_BITS 0x00000001 +#define SSI_ICR_RESET 0x00000000 +#define SSI_ICR_MSB 0 +#define SSI_ICR_LSB 0 +#define SSI_ICR_ACCESS "RO" +// ============================================================================= +// Register : SSI_DMACR +// Description : DMA control +#define SSI_DMACR_OFFSET 0x0000004c +#define SSI_DMACR_BITS 0x00000003 +#define SSI_DMACR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DMACR_TDMAE +// Description : Transmit DMA enable +#define SSI_DMACR_TDMAE_RESET 0x0 +#define SSI_DMACR_TDMAE_BITS 0x00000002 +#define SSI_DMACR_TDMAE_MSB 1 +#define SSI_DMACR_TDMAE_LSB 1 +#define SSI_DMACR_TDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_DMACR_RDMAE +// Description : Receive DMA enable +#define SSI_DMACR_RDMAE_RESET 0x0 +#define SSI_DMACR_RDMAE_BITS 0x00000001 +#define SSI_DMACR_RDMAE_MSB 0 +#define SSI_DMACR_RDMAE_LSB 0 +#define SSI_DMACR_RDMAE_ACCESS "RW" +// ============================================================================= +// Register : SSI_DMATDLR +// Description : DMA TX data level +#define SSI_DMATDLR_OFFSET 0x00000050 +#define SSI_DMATDLR_BITS 0x000000ff +#define SSI_DMATDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DMATDLR_DMATDL +// Description : Transmit data watermark level +#define SSI_DMATDLR_DMATDL_RESET 0x00 +#define SSI_DMATDLR_DMATDL_BITS 0x000000ff +#define SSI_DMATDLR_DMATDL_MSB 7 +#define SSI_DMATDLR_DMATDL_LSB 0 +#define SSI_DMATDLR_DMATDL_ACCESS "RW" +// ============================================================================= +// Register : SSI_DMARDLR +// Description : DMA RX data level +#define SSI_DMARDLR_OFFSET 0x00000054 +#define SSI_DMARDLR_BITS 0x000000ff +#define SSI_DMARDLR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DMARDLR_DMARDL +// Description : Receive data watermark level (DMARDLR+1) +#define SSI_DMARDLR_DMARDL_RESET 0x00 +#define SSI_DMARDLR_DMARDL_BITS 0x000000ff +#define SSI_DMARDLR_DMARDL_MSB 7 +#define SSI_DMARDLR_DMARDL_LSB 0 +#define SSI_DMARDLR_DMARDL_ACCESS "RW" +// ============================================================================= +// Register : SSI_IDR +// Description : Identification register +#define SSI_IDR_OFFSET 0x00000058 +#define SSI_IDR_BITS 0xffffffff +#define SSI_IDR_RESET 0x51535049 +// ----------------------------------------------------------------------------- +// Field : SSI_IDR_IDCODE +// Description : Peripheral dentification code +#define SSI_IDR_IDCODE_RESET 0x51535049 +#define SSI_IDR_IDCODE_BITS 0xffffffff +#define SSI_IDR_IDCODE_MSB 31 +#define SSI_IDR_IDCODE_LSB 0 +#define SSI_IDR_IDCODE_ACCESS "RO" +// ============================================================================= +// Register : SSI_SSI_VERSION_ID +// Description : Version ID +#define SSI_SSI_VERSION_ID_OFFSET 0x0000005c +#define SSI_SSI_VERSION_ID_BITS 0xffffffff +#define SSI_SSI_VERSION_ID_RESET 0x3430312a +// ----------------------------------------------------------------------------- +// Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION +// Description : SNPS component version (format X.YY) +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET 0x3430312a +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS 0xffffffff +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB 31 +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB 0 +#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO" +// ============================================================================= +// Register : SSI_DR0 +// Description : Data Register 0 (of 36) +#define SSI_DR0_OFFSET 0x00000060 +#define SSI_DR0_BITS 0xffffffff +#define SSI_DR0_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_DR0_DR +// Description : First data register of 36 +#define SSI_DR0_DR_RESET 0x00000000 +#define SSI_DR0_DR_BITS 0xffffffff +#define SSI_DR0_DR_MSB 31 +#define SSI_DR0_DR_LSB 0 +#define SSI_DR0_DR_ACCESS "RW" +// ============================================================================= +// Register : SSI_RX_SAMPLE_DLY +// Description : RX sample delay +#define SSI_RX_SAMPLE_DLY_OFFSET 0x000000f0 +#define SSI_RX_SAMPLE_DLY_BITS 0x000000ff +#define SSI_RX_SAMPLE_DLY_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_RX_SAMPLE_DLY_RSD +// Description : RXD sample delay (in SCLK cycles) +#define SSI_RX_SAMPLE_DLY_RSD_RESET 0x00 +#define SSI_RX_SAMPLE_DLY_RSD_BITS 0x000000ff +#define SSI_RX_SAMPLE_DLY_RSD_MSB 7 +#define SSI_RX_SAMPLE_DLY_RSD_LSB 0 +#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW" +// ============================================================================= +// Register : SSI_SPI_CTRLR0 +// Description : SPI control +#define SSI_SPI_CTRLR0_OFFSET 0x000000f4 +#define SSI_SPI_CTRLR0_BITS 0xff07fb3f +#define SSI_SPI_CTRLR0_RESET 0x03000000 +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_XIP_CMD +// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append +// to Address (INST_L = 0-bit) +#define SSI_SPI_CTRLR0_XIP_CMD_RESET 0x03 +#define SSI_SPI_CTRLR0_XIP_CMD_BITS 0xff000000 +#define SSI_SPI_CTRLR0_XIP_CMD_MSB 31 +#define SSI_SPI_CTRLR0_XIP_CMD_LSB 24 +#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_SPI_RXDS_EN +// Description : Read data strobe enable +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET 0x0 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS 0x00040000 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB 18 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB 18 +#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_INST_DDR_EN +// Description : Instruction DDR transfer enable +#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET 0x0 +#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS 0x00020000 +#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB 17 +#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB 17 +#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_SPI_DDR_EN +// Description : SPI DDR transfer enable +#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET 0x0 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS 0x00010000 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB 16 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB 16 +#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_WAIT_CYCLES +// Description : Wait cycles between control frame transmit and data reception +// (in SCLK cycles) +#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET 0x00 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS 0x0000f800 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB 15 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB 11 +#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_INST_L +// Description : Instruction length (0/4/8/16b) +// 0x0 -> No instruction +// 0x1 -> 4-bit instruction +// 0x2 -> 8-bit instruction +// 0x3 -> 16-bit instruction +#define SSI_SPI_CTRLR0_INST_L_RESET 0x0 +#define SSI_SPI_CTRLR0_INST_L_BITS 0x00000300 +#define SSI_SPI_CTRLR0_INST_L_MSB 9 +#define SSI_SPI_CTRLR0_INST_L_LSB 8 +#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" +#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE 0x0 +#define SSI_SPI_CTRLR0_INST_L_VALUE_4B 0x1 +#define SSI_SPI_CTRLR0_INST_L_VALUE_8B 0x2 +#define SSI_SPI_CTRLR0_INST_L_VALUE_16B 0x3 +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_ADDR_L +// Description : Address length (0b-60b in 4b increments) +#define SSI_SPI_CTRLR0_ADDR_L_RESET 0x0 +#define SSI_SPI_CTRLR0_ADDR_L_BITS 0x0000003c +#define SSI_SPI_CTRLR0_ADDR_L_MSB 5 +#define SSI_SPI_CTRLR0_ADDR_L_LSB 2 +#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SSI_SPI_CTRLR0_TRANS_TYPE +// Description : Address and instruction transfer format +// 0x0 -> Command and address both in standard SPI frame format +// 0x1 -> Command in standard SPI format, address in format +// specified by FRF +// 0x2 -> Command and address both in format specified by FRF +// (e.g. Dual-SPI) +#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET 0x0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS 0x00000003 +#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB 1 +#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB 0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A 0x0 +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A 0x1 +#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A 0x2 +// ============================================================================= +// Register : SSI_TXD_DRIVE_EDGE +// Description : TX drive edge +#define SSI_TXD_DRIVE_EDGE_OFFSET 0x000000f8 +#define SSI_TXD_DRIVE_EDGE_BITS 0x000000ff +#define SSI_TXD_DRIVE_EDGE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SSI_TXD_DRIVE_EDGE_TDE +// Description : TXD drive edge +#define SSI_TXD_DRIVE_EDGE_TDE_RESET 0x00 +#define SSI_TXD_DRIVE_EDGE_TDE_BITS 0x000000ff +#define SSI_TXD_DRIVE_EDGE_TDE_MSB 7 +#define SSI_TXD_DRIVE_EDGE_TDE_LSB 0 +#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_SSI_DEFINED diff --git a/rp2040/hardware/regs/syscfg.h b/rp2040/hardware/regs/syscfg.h new file mode 100644 index 0000000..c1bcaf9 --- /dev/null +++ b/rp2040/hardware/regs/syscfg.h @@ -0,0 +1,257 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSCFG +// Version : 1 +// Bus type : apb +// Description : Register block for various chip control signals +// ============================================================================= +#ifndef HARDWARE_REGS_SYSCFG_DEFINED +#define HARDWARE_REGS_SYSCFG_DEFINED +// ============================================================================= +// Register : SYSCFG_PROC0_NMI_MASK +// Description : Processor core 0 NMI source mask +// Set a bit high to enable NMI from that IRQ +#define SYSCFG_PROC0_NMI_MASK_OFFSET 0x00000000 +#define SYSCFG_PROC0_NMI_MASK_BITS 0xffffffff +#define SYSCFG_PROC0_NMI_MASK_RESET 0x00000000 +#define SYSCFG_PROC0_NMI_MASK_MSB 31 +#define SYSCFG_PROC0_NMI_MASK_LSB 0 +#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC1_NMI_MASK +// Description : Processor core 1 NMI source mask +// Set a bit high to enable NMI from that IRQ +#define SYSCFG_PROC1_NMI_MASK_OFFSET 0x00000004 +#define SYSCFG_PROC1_NMI_MASK_BITS 0xffffffff +#define SYSCFG_PROC1_NMI_MASK_RESET 0x00000000 +#define SYSCFG_PROC1_NMI_MASK_MSB 31 +#define SYSCFG_PROC1_NMI_MASK_LSB 0 +#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC_CONFIG +// Description : Configuration for processors +#define SYSCFG_PROC_CONFIG_OFFSET 0x00000008 +#define SYSCFG_PROC_CONFIG_BITS 0xff000003 +#define SYSCFG_PROC_CONFIG_RESET 0x10000000 +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID +// Description : Configure proc1 DAP instance ID. +// Recommend that this is NOT changed until you require debug +// access in multi-chip environment +// WARNING: do not set to 15 as this is reserved for RescueDP +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET 0x1 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS 0xf0000000 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB 31 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB 28 +#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID +// Description : Configure proc0 DAP instance ID. +// Recommend that this is NOT changed until you require debug +// access in multi-chip environment +// WARNING: do not set to 15 as this is reserved for RescueDP +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET 0x0 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS 0x0f000000 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB 27 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB 24 +#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED +// Description : Indication that proc1 has halted +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET 0x0 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS 0x00000002 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB 1 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB 1 +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED +// Description : Indication that proc0 has halted +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET 0x0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS 0x00000001 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB 0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB 0 +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 0...29. +#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET 0x0000000c +#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS 0x3fffffff +#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET 0x00000000 +#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB 29 +#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 30...35 (the QSPI IOs). +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET 0x00000010 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS 0x0000003f +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET 0x00000000 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB 5 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB 0 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_DBGFORCE +// Description : Directly control the SWD debug port of either processor +#define SYSCFG_DBGFORCE_OFFSET 0x00000014 +#define SYSCFG_DBGFORCE_BITS 0x000000ff +#define SYSCFG_DBGFORCE_RESET 0x00000066 +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_ATTACH +// Description : Attach processor 1 debug port to syscfg controls, and +// disconnect it from external SWD pads. +#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET 0x0 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS 0x00000080 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB 7 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB 7 +#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_SWCLK +// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set +#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS 0x00000040 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB 6 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB 6 +#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_SWDI +// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set +#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS 0x00000020 +#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB 5 +#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB 5 +#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC1_SWDO +// Description : Observe the value of processor 1 SWDIO output. +#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-" +#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS 0x00000010 +#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB 4 +#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB 4 +#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_ATTACH +// Description : Attach processor 0 debug port to syscfg controls, and +// disconnect it from external SWD pads. +#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET 0x0 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS 0x00000008 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB 3 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB 3 +#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_SWCLK +// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set +#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS 0x00000004 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB 2 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB 2 +#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_SWDI +// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set +#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET 0x1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS 0x00000002 +#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB 1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB 1 +#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_PROC0_SWDO +// Description : Observe the value of processor 0 SWDIO output. +#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-" +#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS 0x00000001 +#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB 0 +#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB 0 +#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_MEMPOWERDOWN +// Description : Control power downs to memories. Set high to power down +// memories. +// Use with extreme caution +#define SYSCFG_MEMPOWERDOWN_OFFSET 0x00000018 +#define SYSCFG_MEMPOWERDOWN_BITS 0x000000ff +#define SYSCFG_MEMPOWERDOWN_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_ROM +// Description : None +#define SYSCFG_MEMPOWERDOWN_ROM_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_ROM_BITS 0x00000080 +#define SYSCFG_MEMPOWERDOWN_ROM_MSB 7 +#define SYSCFG_MEMPOWERDOWN_ROM_LSB 7 +#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_USB +// Description : None +#define SYSCFG_MEMPOWERDOWN_USB_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_USB_BITS 0x00000040 +#define SYSCFG_MEMPOWERDOWN_USB_MSB 6 +#define SYSCFG_MEMPOWERDOWN_USB_LSB 6 +#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM5 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS 0x00000020 +#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB 5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB 5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM4 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS 0x00000010 +#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB 4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB 4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM3 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS 0x00000008 +#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB 3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB 3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM2 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS 0x00000004 +#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB 2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB 2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM1 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS 0x00000002 +#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB 1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB 1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM0 +// Description : None +#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET 0x0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS 0x00000001 +#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB 0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB 0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_SYSCFG_DEFINED diff --git a/rp2040/hardware/regs/sysinfo.h b/rp2040/hardware/regs/sysinfo.h new file mode 100644 index 0000000..7a46037 --- /dev/null +++ b/rp2040/hardware/regs/sysinfo.h @@ -0,0 +1,77 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSINFO +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_SYSINFO_DEFINED +#define HARDWARE_REGS_SYSINFO_DEFINED +// ============================================================================= +// Register : SYSINFO_CHIP_ID +// Description : JEDEC JEP-106 compliant chip identifier. +#define SYSINFO_CHIP_ID_OFFSET 0x00000000 +#define SYSINFO_CHIP_ID_BITS 0xffffffff +#define SYSINFO_CHIP_ID_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_REVISION +// Description : None +#define SYSINFO_CHIP_ID_REVISION_RESET "-" +#define SYSINFO_CHIP_ID_REVISION_BITS 0xf0000000 +#define SYSINFO_CHIP_ID_REVISION_MSB 31 +#define SYSINFO_CHIP_ID_REVISION_LSB 28 +#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_PART +// Description : None +#define SYSINFO_CHIP_ID_PART_RESET "-" +#define SYSINFO_CHIP_ID_PART_BITS 0x0ffff000 +#define SYSINFO_CHIP_ID_PART_MSB 27 +#define SYSINFO_CHIP_ID_PART_LSB 12 +#define SYSINFO_CHIP_ID_PART_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_MANUFACTURER +// Description : None +#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" +#define SYSINFO_CHIP_ID_MANUFACTURER_BITS 0x00000fff +#define SYSINFO_CHIP_ID_MANUFACTURER_MSB 11 +#define SYSINFO_CHIP_ID_MANUFACTURER_LSB 0 +#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_PLATFORM +// Description : Platform register. Allows software to know what environment it +// is running in. +#define SYSINFO_PLATFORM_OFFSET 0x00000004 +#define SYSINFO_PLATFORM_BITS 0x00000003 +#define SYSINFO_PLATFORM_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_ASIC +// Description : None +#define SYSINFO_PLATFORM_ASIC_RESET 0x0 +#define SYSINFO_PLATFORM_ASIC_BITS 0x00000002 +#define SYSINFO_PLATFORM_ASIC_MSB 1 +#define SYSINFO_PLATFORM_ASIC_LSB 1 +#define SYSINFO_PLATFORM_ASIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_FPGA +// Description : None +#define SYSINFO_PLATFORM_FPGA_RESET 0x0 +#define SYSINFO_PLATFORM_FPGA_BITS 0x00000001 +#define SYSINFO_PLATFORM_FPGA_MSB 0 +#define SYSINFO_PLATFORM_FPGA_LSB 0 +#define SYSINFO_PLATFORM_FPGA_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_GITREF_RP2040 +// Description : Git hash of the chip source. Used to identify chip version. +#define SYSINFO_GITREF_RP2040_OFFSET 0x00000040 +#define SYSINFO_GITREF_RP2040_BITS 0xffffffff +#define SYSINFO_GITREF_RP2040_RESET "-" +#define SYSINFO_GITREF_RP2040_MSB 31 +#define SYSINFO_GITREF_RP2040_LSB 0 +#define SYSINFO_GITREF_RP2040_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_SYSINFO_DEFINED diff --git a/rp2040/hardware/regs/tbman.h b/rp2040/hardware/regs/tbman.h new file mode 100644 index 0000000..6bf9b29 --- /dev/null +++ b/rp2040/hardware/regs/tbman.h @@ -0,0 +1,38 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TBMAN +// Version : 1 +// Bus type : apb +// Description : Testbench manager. Allows the programmer to know what +// platform their software is running on. +// ============================================================================= +#ifndef HARDWARE_REGS_TBMAN_DEFINED +#define HARDWARE_REGS_TBMAN_DEFINED +// ============================================================================= +// Register : TBMAN_PLATFORM +// Description : Indicates the type of platform in use +#define TBMAN_PLATFORM_OFFSET 0x00000000 +#define TBMAN_PLATFORM_BITS 0x00000003 +#define TBMAN_PLATFORM_RESET 0x00000005 +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_FPGA +// Description : Indicates the platform is an FPGA +#define TBMAN_PLATFORM_FPGA_RESET 0x0 +#define TBMAN_PLATFORM_FPGA_BITS 0x00000002 +#define TBMAN_PLATFORM_FPGA_MSB 1 +#define TBMAN_PLATFORM_FPGA_LSB 1 +#define TBMAN_PLATFORM_FPGA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_ASIC +// Description : Indicates the platform is an ASIC +#define TBMAN_PLATFORM_ASIC_RESET 0x1 +#define TBMAN_PLATFORM_ASIC_BITS 0x00000001 +#define TBMAN_PLATFORM_ASIC_MSB 0 +#define TBMAN_PLATFORM_ASIC_LSB 0 +#define TBMAN_PLATFORM_ASIC_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_TBMAN_DEFINED diff --git a/rp2040/hardware/regs/timer.h b/rp2040/hardware/regs/timer.h new file mode 100644 index 0000000..a2209b6 --- /dev/null +++ b/rp2040/hardware/regs/timer.h @@ -0,0 +1,332 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TIMER +// Version : 1 +// Bus type : apb +// Description : Controls time and alarms +// time is a 64 bit value indicating the time in usec since +// power-on +// timeh is the top 32 bits of time & timel is the bottom 32 +// bits +// to change time write to timelw before timehw +// to read time read from timelr before timehr +// An alarm is set by setting alarm_enable and writing to the +// corresponding alarm register +// When an alarm is pending, the corresponding alarm_running +// signal will be high +// An alarm can be cancelled before it has finished by clearing +// the alarm_enable +// When an alarm fires, the corresponding alarm_irq is set and +// alarm_running is cleared +// To clear the interrupt write a 1 to the corresponding +// alarm_irq +// ============================================================================= +#ifndef HARDWARE_REGS_TIMER_DEFINED +#define HARDWARE_REGS_TIMER_DEFINED +// ============================================================================= +// Register : TIMER_TIMEHW +// Description : Write to bits 63:32 of time +// always write timelw before timehw +#define TIMER_TIMEHW_OFFSET 0x00000000 +#define TIMER_TIMEHW_BITS 0xffffffff +#define TIMER_TIMEHW_RESET 0x00000000 +#define TIMER_TIMEHW_MSB 31 +#define TIMER_TIMEHW_LSB 0 +#define TIMER_TIMEHW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMELW +// Description : Write to bits 31:0 of time +// writes do not get copied to time until timehw is written +#define TIMER_TIMELW_OFFSET 0x00000004 +#define TIMER_TIMELW_BITS 0xffffffff +#define TIMER_TIMELW_RESET 0x00000000 +#define TIMER_TIMELW_MSB 31 +#define TIMER_TIMELW_LSB 0 +#define TIMER_TIMELW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMEHR +// Description : Read from bits 63:32 of time +// always read timelr before timehr +#define TIMER_TIMEHR_OFFSET 0x00000008 +#define TIMER_TIMEHR_BITS 0xffffffff +#define TIMER_TIMEHR_RESET 0x00000000 +#define TIMER_TIMEHR_MSB 31 +#define TIMER_TIMEHR_LSB 0 +#define TIMER_TIMEHR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMELR +// Description : Read from bits 31:0 of time +#define TIMER_TIMELR_OFFSET 0x0000000c +#define TIMER_TIMELR_BITS 0xffffffff +#define TIMER_TIMELR_RESET 0x00000000 +#define TIMER_TIMELR_MSB 31 +#define TIMER_TIMELR_LSB 0 +#define TIMER_TIMELR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_ALARM0 +// Description : Arm alarm 0, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM0_OFFSET 0x00000010 +#define TIMER_ALARM0_BITS 0xffffffff +#define TIMER_ALARM0_RESET 0x00000000 +#define TIMER_ALARM0_MSB 31 +#define TIMER_ALARM0_LSB 0 +#define TIMER_ALARM0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM1 +// Description : Arm alarm 1, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM1_OFFSET 0x00000014 +#define TIMER_ALARM1_BITS 0xffffffff +#define TIMER_ALARM1_RESET 0x00000000 +#define TIMER_ALARM1_MSB 31 +#define TIMER_ALARM1_LSB 0 +#define TIMER_ALARM1_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM2 +// Description : Arm alarm 2, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM2_OFFSET 0x00000018 +#define TIMER_ALARM2_BITS 0xffffffff +#define TIMER_ALARM2_RESET 0x00000000 +#define TIMER_ALARM2_MSB 31 +#define TIMER_ALARM2_LSB 0 +#define TIMER_ALARM2_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM3 +// Description : Arm alarm 3, and configure the time it will fire. +// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. +// The alarm will disarm itself once it fires, and can +// be disarmed early using the ARMED status register. +#define TIMER_ALARM3_OFFSET 0x0000001c +#define TIMER_ALARM3_BITS 0xffffffff +#define TIMER_ALARM3_RESET 0x00000000 +#define TIMER_ALARM3_MSB 31 +#define TIMER_ALARM3_LSB 0 +#define TIMER_ALARM3_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ARMED +// Description : Indicates the armed/disarmed status of each alarm. +// A write to the corresponding ALARMx register arms the alarm. +// Alarms automatically disarm upon firing, but writing ones here +// will disarm immediately without waiting to fire. +#define TIMER_ARMED_OFFSET 0x00000020 +#define TIMER_ARMED_BITS 0x0000000f +#define TIMER_ARMED_RESET 0x00000000 +#define TIMER_ARMED_MSB 3 +#define TIMER_ARMED_LSB 0 +#define TIMER_ARMED_ACCESS "WC" +// ============================================================================= +// Register : TIMER_TIMERAWH +// Description : Raw read from bits 63:32 of time (no side effects) +#define TIMER_TIMERAWH_OFFSET 0x00000024 +#define TIMER_TIMERAWH_BITS 0xffffffff +#define TIMER_TIMERAWH_RESET 0x00000000 +#define TIMER_TIMERAWH_MSB 31 +#define TIMER_TIMERAWH_LSB 0 +#define TIMER_TIMERAWH_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMERAWL +// Description : Raw read from bits 31:0 of time (no side effects) +#define TIMER_TIMERAWL_OFFSET 0x00000028 +#define TIMER_TIMERAWL_BITS 0xffffffff +#define TIMER_TIMERAWL_RESET 0x00000000 +#define TIMER_TIMERAWL_MSB 31 +#define TIMER_TIMERAWL_LSB 0 +#define TIMER_TIMERAWL_ACCESS "RO" +// ============================================================================= +// Register : TIMER_DBGPAUSE +// Description : Set bits high to enable pause when the corresponding debug +// ports are active +#define TIMER_DBGPAUSE_OFFSET 0x0000002c +#define TIMER_DBGPAUSE_BITS 0x00000006 +#define TIMER_DBGPAUSE_RESET 0x00000007 +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG1 +// Description : Pause when processor 1 is in debug mode +#define TIMER_DBGPAUSE_DBG1_RESET 0x1 +#define TIMER_DBGPAUSE_DBG1_BITS 0x00000004 +#define TIMER_DBGPAUSE_DBG1_MSB 2 +#define TIMER_DBGPAUSE_DBG1_LSB 2 +#define TIMER_DBGPAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG0 +// Description : Pause when processor 0 is in debug mode +#define TIMER_DBGPAUSE_DBG0_RESET 0x1 +#define TIMER_DBGPAUSE_DBG0_BITS 0x00000002 +#define TIMER_DBGPAUSE_DBG0_MSB 1 +#define TIMER_DBGPAUSE_DBG0_LSB 1 +#define TIMER_DBGPAUSE_DBG0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_PAUSE +// Description : Set high to pause the timer +#define TIMER_PAUSE_OFFSET 0x00000030 +#define TIMER_PAUSE_BITS 0x00000001 +#define TIMER_PAUSE_RESET 0x00000000 +#define TIMER_PAUSE_MSB 0 +#define TIMER_PAUSE_LSB 0 +#define TIMER_PAUSE_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTR +// Description : Raw Interrupts +#define TIMER_INTR_OFFSET 0x00000034 +#define TIMER_INTR_BITS 0x0000000f +#define TIMER_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_3 +// Description : None +#define TIMER_INTR_ALARM_3_RESET 0x0 +#define TIMER_INTR_ALARM_3_BITS 0x00000008 +#define TIMER_INTR_ALARM_3_MSB 3 +#define TIMER_INTR_ALARM_3_LSB 3 +#define TIMER_INTR_ALARM_3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_2 +// Description : None +#define TIMER_INTR_ALARM_2_RESET 0x0 +#define TIMER_INTR_ALARM_2_BITS 0x00000004 +#define TIMER_INTR_ALARM_2_MSB 2 +#define TIMER_INTR_ALARM_2_LSB 2 +#define TIMER_INTR_ALARM_2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_1 +// Description : None +#define TIMER_INTR_ALARM_1_RESET 0x0 +#define TIMER_INTR_ALARM_1_BITS 0x00000002 +#define TIMER_INTR_ALARM_1_MSB 1 +#define TIMER_INTR_ALARM_1_LSB 1 +#define TIMER_INTR_ALARM_1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_0 +// Description : None +#define TIMER_INTR_ALARM_0_RESET 0x0 +#define TIMER_INTR_ALARM_0_BITS 0x00000001 +#define TIMER_INTR_ALARM_0_MSB 0 +#define TIMER_INTR_ALARM_0_LSB 0 +#define TIMER_INTR_ALARM_0_ACCESS "WC" +// ============================================================================= +// Register : TIMER_INTE +// Description : Interrupt Enable +#define TIMER_INTE_OFFSET 0x00000038 +#define TIMER_INTE_BITS 0x0000000f +#define TIMER_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_3 +// Description : None +#define TIMER_INTE_ALARM_3_RESET 0x0 +#define TIMER_INTE_ALARM_3_BITS 0x00000008 +#define TIMER_INTE_ALARM_3_MSB 3 +#define TIMER_INTE_ALARM_3_LSB 3 +#define TIMER_INTE_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_2 +// Description : None +#define TIMER_INTE_ALARM_2_RESET 0x0 +#define TIMER_INTE_ALARM_2_BITS 0x00000004 +#define TIMER_INTE_ALARM_2_MSB 2 +#define TIMER_INTE_ALARM_2_LSB 2 +#define TIMER_INTE_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_1 +// Description : None +#define TIMER_INTE_ALARM_1_RESET 0x0 +#define TIMER_INTE_ALARM_1_BITS 0x00000002 +#define TIMER_INTE_ALARM_1_MSB 1 +#define TIMER_INTE_ALARM_1_LSB 1 +#define TIMER_INTE_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_0 +// Description : None +#define TIMER_INTE_ALARM_0_RESET 0x0 +#define TIMER_INTE_ALARM_0_BITS 0x00000001 +#define TIMER_INTE_ALARM_0_MSB 0 +#define TIMER_INTE_ALARM_0_LSB 0 +#define TIMER_INTE_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTF +// Description : Interrupt Force +#define TIMER_INTF_OFFSET 0x0000003c +#define TIMER_INTF_BITS 0x0000000f +#define TIMER_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_3 +// Description : None +#define TIMER_INTF_ALARM_3_RESET 0x0 +#define TIMER_INTF_ALARM_3_BITS 0x00000008 +#define TIMER_INTF_ALARM_3_MSB 3 +#define TIMER_INTF_ALARM_3_LSB 3 +#define TIMER_INTF_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_2 +// Description : None +#define TIMER_INTF_ALARM_2_RESET 0x0 +#define TIMER_INTF_ALARM_2_BITS 0x00000004 +#define TIMER_INTF_ALARM_2_MSB 2 +#define TIMER_INTF_ALARM_2_LSB 2 +#define TIMER_INTF_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_1 +// Description : None +#define TIMER_INTF_ALARM_1_RESET 0x0 +#define TIMER_INTF_ALARM_1_BITS 0x00000002 +#define TIMER_INTF_ALARM_1_MSB 1 +#define TIMER_INTF_ALARM_1_LSB 1 +#define TIMER_INTF_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_0 +// Description : None +#define TIMER_INTF_ALARM_0_RESET 0x0 +#define TIMER_INTF_ALARM_0_BITS 0x00000001 +#define TIMER_INTF_ALARM_0_MSB 0 +#define TIMER_INTF_ALARM_0_LSB 0 +#define TIMER_INTF_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTS +// Description : Interrupt status after masking & forcing +#define TIMER_INTS_OFFSET 0x00000040 +#define TIMER_INTS_BITS 0x0000000f +#define TIMER_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_3 +// Description : None +#define TIMER_INTS_ALARM_3_RESET 0x0 +#define TIMER_INTS_ALARM_3_BITS 0x00000008 +#define TIMER_INTS_ALARM_3_MSB 3 +#define TIMER_INTS_ALARM_3_LSB 3 +#define TIMER_INTS_ALARM_3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_2 +// Description : None +#define TIMER_INTS_ALARM_2_RESET 0x0 +#define TIMER_INTS_ALARM_2_BITS 0x00000004 +#define TIMER_INTS_ALARM_2_MSB 2 +#define TIMER_INTS_ALARM_2_LSB 2 +#define TIMER_INTS_ALARM_2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_1 +// Description : None +#define TIMER_INTS_ALARM_1_RESET 0x0 +#define TIMER_INTS_ALARM_1_BITS 0x00000002 +#define TIMER_INTS_ALARM_1_MSB 1 +#define TIMER_INTS_ALARM_1_LSB 1 +#define TIMER_INTS_ALARM_1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_0 +// Description : None +#define TIMER_INTS_ALARM_0_RESET 0x0 +#define TIMER_INTS_ALARM_0_BITS 0x00000001 +#define TIMER_INTS_ALARM_0_MSB 0 +#define TIMER_INTS_ALARM_0_LSB 0 +#define TIMER_INTS_ALARM_0_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_TIMER_DEFINED diff --git a/rp2040/hardware/regs/uart.h b/rp2040/hardware/regs/uart.h new file mode 100644 index 0000000..8fde5d1 --- /dev/null +++ b/rp2040/hardware/regs/uart.h @@ -0,0 +1,1148 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : UART +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_UART_DEFINED +#define HARDWARE_REGS_UART_DEFINED +// ============================================================================= +// Register : UART_UARTDR +// Description : Data Register, UARTDR +#define UART_UARTDR_OFFSET 0x00000000 +#define UART_UARTDR_BITS 0x00000fff +#define UART_UARTDR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// receive FIFO is already full. This is cleared to 0 once there +// is an empty space in the FIFO and a new character can be +// written to it. +#define UART_UARTDR_OE_RESET "-" +#define UART_UARTDR_OE_BITS 0x00000800 +#define UART_UARTDR_OE_MSB 11 +#define UART_UARTDR_OE_LSB 11 +#define UART_UARTDR_OE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity and stop bits). In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state), and the next valid start bit is +// received. +#define UART_UARTDR_BE_RESET "-" +#define UART_UARTDR_BE_BITS 0x00000400 +#define UART_UARTDR_BE_MSB 10 +#define UART_UARTDR_BE_LSB 10 +#define UART_UARTDR_BE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. In +// FIFO mode, this error is associated with the character at the +// top of the FIFO. +#define UART_UARTDR_PE_RESET "-" +#define UART_UARTDR_PE_BITS 0x00000200 +#define UART_UARTDR_PE_MSB 9 +#define UART_UARTDR_PE_LSB 9 +#define UART_UARTDR_PE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). In FIFO mode, this error is associated with the character +// at the top of the FIFO. +#define UART_UARTDR_FE_RESET "-" +#define UART_UARTDR_FE_BITS 0x00000100 +#define UART_UARTDR_FE_MSB 8 +#define UART_UARTDR_FE_LSB 8 +#define UART_UARTDR_FE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_DATA +// Description : Receive (read) data character. Transmit (write) data character. +#define UART_UARTDR_DATA_RESET "-" +#define UART_UARTDR_DATA_BITS 0x000000ff +#define UART_UARTDR_DATA_MSB 7 +#define UART_UARTDR_DATA_LSB 0 +#define UART_UARTDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : UART_UARTRSR +// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR +#define UART_UARTRSR_OFFSET 0x00000004 +#define UART_UARTRSR_BITS 0x0000000f +#define UART_UARTRSR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// FIFO is already full. This bit is cleared to 0 by a write to +// UARTECR. The FIFO contents remain valid because no more data is +// written when the FIFO is full, only the contents of the shift +// register are overwritten. The CPU must now read the data, to +// empty the FIFO. +#define UART_UARTRSR_OE_RESET 0x0 +#define UART_UARTRSR_OE_BITS 0x00000008 +#define UART_UARTRSR_OE_MSB 3 +#define UART_UARTRSR_OE_LSB 3 +#define UART_UARTRSR_OE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity, and stop bits). This bit is cleared to 0 +// after a write to UARTECR. In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state) and the next valid start bit is +// received. +#define UART_UARTRSR_BE_RESET 0x0 +#define UART_UARTRSR_BE_BITS 0x00000004 +#define UART_UARTRSR_BE_MSB 2 +#define UART_UARTRSR_BE_LSB 2 +#define UART_UARTRSR_BE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. This +// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this +// error is associated with the character at the top of the FIFO. +#define UART_UARTRSR_PE_RESET 0x0 +#define UART_UARTRSR_PE_BITS 0x00000002 +#define UART_UARTRSR_PE_MSB 1 +#define UART_UARTRSR_PE_LSB 1 +#define UART_UARTRSR_PE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO +// mode, this error is associated with the character at the top of +// the FIFO. +#define UART_UARTRSR_FE_RESET 0x0 +#define UART_UARTRSR_FE_BITS 0x00000001 +#define UART_UARTRSR_FE_MSB 0 +#define UART_UARTRSR_FE_LSB 0 +#define UART_UARTRSR_FE_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTFR +// Description : Flag Register, UARTFR +#define UART_UARTFR_OFFSET 0x00000018 +#define UART_UARTFR_BITS 0x000001ff +#define UART_UARTFR_RESET 0x00000090 +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RI +// Description : Ring indicator. This bit is the complement of the UART ring +// indicator, nUARTRI, modem status input. That is, the bit is 1 +// when nUARTRI is LOW. +#define UART_UARTFR_RI_RESET "-" +#define UART_UARTFR_RI_BITS 0x00000100 +#define UART_UARTFR_RI_MSB 8 +#define UART_UARTFR_RI_LSB 8 +#define UART_UARTFR_RI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFE +// Description : Transmit FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the Line Control Register, UARTLCR_H. +// If the FIFO is disabled, this bit is set when the transmit +// holding register is empty. If the FIFO is enabled, the TXFE bit +// is set when the transmit FIFO is empty. This bit does not +// indicate if there is data in the transmit shift register. +#define UART_UARTFR_TXFE_RESET 0x1 +#define UART_UARTFR_TXFE_BITS 0x00000080 +#define UART_UARTFR_TXFE_MSB 7 +#define UART_UARTFR_TXFE_LSB 7 +#define UART_UARTFR_TXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFF +// Description : Receive FIFO full. The meaning of this bit depends on the state +// of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// full. If the FIFO is enabled, the RXFF bit is set when the +// receive FIFO is full. +#define UART_UARTFR_RXFF_RESET 0x0 +#define UART_UARTFR_RXFF_BITS 0x00000040 +#define UART_UARTFR_RXFF_MSB 6 +#define UART_UARTFR_RXFF_LSB 6 +#define UART_UARTFR_RXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFF +// Description : Transmit FIFO full. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the transmit holding register is +// full. If the FIFO is enabled, the TXFF bit is set when the +// transmit FIFO is full. +#define UART_UARTFR_TXFF_RESET 0x0 +#define UART_UARTFR_TXFF_BITS 0x00000020 +#define UART_UARTFR_TXFF_MSB 5 +#define UART_UARTFR_TXFF_LSB 5 +#define UART_UARTFR_TXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFE +// Description : Receive FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// empty. If the FIFO is enabled, the RXFE bit is set when the +// receive FIFO is empty. +#define UART_UARTFR_RXFE_RESET 0x1 +#define UART_UARTFR_RXFE_BITS 0x00000010 +#define UART_UARTFR_RXFE_MSB 4 +#define UART_UARTFR_RXFE_LSB 4 +#define UART_UARTFR_RXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_BUSY +// Description : UART busy. If this bit is set to 1, the UART is busy +// transmitting data. This bit remains set until the complete +// byte, including all the stop bits, has been sent from the shift +// register. This bit is set as soon as the transmit FIFO becomes +// non-empty, regardless of whether the UART is enabled or not. +#define UART_UARTFR_BUSY_RESET 0x0 +#define UART_UARTFR_BUSY_BITS 0x00000008 +#define UART_UARTFR_BUSY_MSB 3 +#define UART_UARTFR_BUSY_LSB 3 +#define UART_UARTFR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DCD +// Description : Data carrier detect. This bit is the complement of the UART +// data carrier detect, nUARTDCD, modem status input. That is, the +// bit is 1 when nUARTDCD is LOW. +#define UART_UARTFR_DCD_RESET "-" +#define UART_UARTFR_DCD_BITS 0x00000004 +#define UART_UARTFR_DCD_MSB 2 +#define UART_UARTFR_DCD_LSB 2 +#define UART_UARTFR_DCD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DSR +// Description : Data set ready. This bit is the complement of the UART data set +// ready, nUARTDSR, modem status input. That is, the bit is 1 when +// nUARTDSR is LOW. +#define UART_UARTFR_DSR_RESET "-" +#define UART_UARTFR_DSR_BITS 0x00000002 +#define UART_UARTFR_DSR_MSB 1 +#define UART_UARTFR_DSR_LSB 1 +#define UART_UARTFR_DSR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_CTS +// Description : Clear to send. This bit is the complement of the UART clear to +// send, nUARTCTS, modem status input. That is, the bit is 1 when +// nUARTCTS is LOW. +#define UART_UARTFR_CTS_RESET "-" +#define UART_UARTFR_CTS_BITS 0x00000001 +#define UART_UARTFR_CTS_MSB 0 +#define UART_UARTFR_CTS_LSB 0 +#define UART_UARTFR_CTS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTILPR +// Description : IrDA Low-Power Counter Register, UARTILPR +#define UART_UARTILPR_OFFSET 0x00000020 +#define UART_UARTILPR_BITS 0x000000ff +#define UART_UARTILPR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTILPR_ILPDVSR +// Description : 8-bit low-power divisor value. These bits are cleared to 0 at +// reset. +#define UART_UARTILPR_ILPDVSR_RESET 0x00 +#define UART_UARTILPR_ILPDVSR_BITS 0x000000ff +#define UART_UARTILPR_ILPDVSR_MSB 7 +#define UART_UARTILPR_ILPDVSR_LSB 0 +#define UART_UARTILPR_ILPDVSR_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIBRD +// Description : Integer Baud Rate Register, UARTIBRD +#define UART_UARTIBRD_OFFSET 0x00000024 +#define UART_UARTIBRD_BITS 0x0000ffff +#define UART_UARTIBRD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTIBRD_BAUD_DIVINT +// Description : The integer baud rate divisor. These bits are cleared to 0 on +// reset. +#define UART_UARTIBRD_BAUD_DIVINT_RESET 0x0000 +#define UART_UARTIBRD_BAUD_DIVINT_BITS 0x0000ffff +#define UART_UARTIBRD_BAUD_DIVINT_MSB 15 +#define UART_UARTIBRD_BAUD_DIVINT_LSB 0 +#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTFBRD +// Description : Fractional Baud Rate Register, UARTFBRD +#define UART_UARTFBRD_OFFSET 0x00000028 +#define UART_UARTFBRD_BITS 0x0000003f +#define UART_UARTFBRD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTFBRD_BAUD_DIVFRAC +// Description : The fractional baud rate divisor. These bits are cleared to 0 +// on reset. +#define UART_UARTFBRD_BAUD_DIVFRAC_RESET 0x00 +#define UART_UARTFBRD_BAUD_DIVFRAC_BITS 0x0000003f +#define UART_UARTFBRD_BAUD_DIVFRAC_MSB 5 +#define UART_UARTFBRD_BAUD_DIVFRAC_LSB 0 +#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTLCR_H +// Description : Line Control Register, UARTLCR_H +#define UART_UARTLCR_H_OFFSET 0x0000002c +#define UART_UARTLCR_H_BITS 0x000000ff +#define UART_UARTLCR_H_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_SPS +// Description : Stick parity select. 0 = stick parity is disabled 1 = either: * +// if the EPS bit is 0 then the parity bit is transmitted and +// checked as a 1 * if the EPS bit is 1 then the parity bit is +// transmitted and checked as a 0. This bit has no effect when the +// PEN bit disables parity checking and generation. +#define UART_UARTLCR_H_SPS_RESET 0x0 +#define UART_UARTLCR_H_SPS_BITS 0x00000080 +#define UART_UARTLCR_H_SPS_MSB 7 +#define UART_UARTLCR_H_SPS_LSB 7 +#define UART_UARTLCR_H_SPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_WLEN +// Description : Word length. These bits indicate the number of data bits +// transmitted or received in a frame as follows: b11 = 8 bits b10 +// = 7 bits b01 = 6 bits b00 = 5 bits. +#define UART_UARTLCR_H_WLEN_RESET 0x0 +#define UART_UARTLCR_H_WLEN_BITS 0x00000060 +#define UART_UARTLCR_H_WLEN_MSB 6 +#define UART_UARTLCR_H_WLEN_LSB 5 +#define UART_UARTLCR_H_WLEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_FEN +// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, +// the FIFOs become 1-byte-deep holding registers 1 = transmit and +// receive FIFO buffers are enabled (FIFO mode). +#define UART_UARTLCR_H_FEN_RESET 0x0 +#define UART_UARTLCR_H_FEN_BITS 0x00000010 +#define UART_UARTLCR_H_FEN_MSB 4 +#define UART_UARTLCR_H_FEN_LSB 4 +#define UART_UARTLCR_H_FEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_STP2 +// Description : Two stop bits select. If this bit is set to 1, two stop bits +// are transmitted at the end of the frame. The receive logic does +// not check for two stop bits being received. +#define UART_UARTLCR_H_STP2_RESET 0x0 +#define UART_UARTLCR_H_STP2_BITS 0x00000008 +#define UART_UARTLCR_H_STP2_MSB 3 +#define UART_UARTLCR_H_STP2_LSB 3 +#define UART_UARTLCR_H_STP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_EPS +// Description : Even parity select. Controls the type of parity the UART uses +// during transmission and reception: 0 = odd parity. The UART +// generates or checks for an odd number of 1s in the data and +// parity bits. 1 = even parity. The UART generates or checks for +// an even number of 1s in the data and parity bits. This bit has +// no effect when the PEN bit disables parity checking and +// generation. +#define UART_UARTLCR_H_EPS_RESET 0x0 +#define UART_UARTLCR_H_EPS_BITS 0x00000004 +#define UART_UARTLCR_H_EPS_MSB 2 +#define UART_UARTLCR_H_EPS_LSB 2 +#define UART_UARTLCR_H_EPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_PEN +// Description : Parity enable: 0 = parity is disabled and no parity bit added +// to the data frame 1 = parity checking and generation is +// enabled. +#define UART_UARTLCR_H_PEN_RESET 0x0 +#define UART_UARTLCR_H_PEN_BITS 0x00000002 +#define UART_UARTLCR_H_PEN_MSB 1 +#define UART_UARTLCR_H_PEN_LSB 1 +#define UART_UARTLCR_H_PEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_BRK +// Description : Send break. If this bit is set to 1, a low-level is continually +// output on the UARTTXD output, after completing transmission of +// the current character. For the proper execution of the break +// command, the software must set this bit for at least two +// complete frames. For normal use, this bit must be cleared to 0. +#define UART_UARTLCR_H_BRK_RESET 0x0 +#define UART_UARTLCR_H_BRK_BITS 0x00000001 +#define UART_UARTLCR_H_BRK_MSB 0 +#define UART_UARTLCR_H_BRK_LSB 0 +#define UART_UARTLCR_H_BRK_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTCR +// Description : Control Register, UARTCR +#define UART_UARTCR_OFFSET 0x00000030 +#define UART_UARTCR_BITS 0x0000ff87 +#define UART_UARTCR_RESET 0x00000300 +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_CTSEN +// Description : CTS hardware flow control enable. If this bit is set to 1, CTS +// hardware flow control is enabled. Data is only transmitted when +// the nUARTCTS signal is asserted. +#define UART_UARTCR_CTSEN_RESET 0x0 +#define UART_UARTCR_CTSEN_BITS 0x00008000 +#define UART_UARTCR_CTSEN_MSB 15 +#define UART_UARTCR_CTSEN_LSB 15 +#define UART_UARTCR_CTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTSEN +// Description : RTS hardware flow control enable. If this bit is set to 1, RTS +// hardware flow control is enabled. Data is only requested when +// there is space in the receive FIFO for it to be received. +#define UART_UARTCR_RTSEN_RESET 0x0 +#define UART_UARTCR_RTSEN_BITS 0x00004000 +#define UART_UARTCR_RTSEN_MSB 14 +#define UART_UARTCR_RTSEN_LSB 14 +#define UART_UARTCR_RTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT2 +// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem +// status output. That is, when the bit is programmed to a 1, the +// output is 0. For DTE this can be used as Ring Indicator (RI). +#define UART_UARTCR_OUT2_RESET 0x0 +#define UART_UARTCR_OUT2_BITS 0x00002000 +#define UART_UARTCR_OUT2_MSB 13 +#define UART_UARTCR_OUT2_LSB 13 +#define UART_UARTCR_OUT2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT1 +// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem +// status output. That is, when the bit is programmed to a 1 the +// output is 0. For DTE this can be used as Data Carrier Detect +// (DCD). +#define UART_UARTCR_OUT1_RESET 0x0 +#define UART_UARTCR_OUT1_BITS 0x00001000 +#define UART_UARTCR_OUT1_MSB 12 +#define UART_UARTCR_OUT1_LSB 12 +#define UART_UARTCR_OUT1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTS +// Description : Request to send. This bit is the complement of the UART request +// to send, nUARTRTS, modem status output. That is, when the bit +// is programmed to a 1 then nUARTRTS is LOW. +#define UART_UARTCR_RTS_RESET 0x0 +#define UART_UARTCR_RTS_BITS 0x00000800 +#define UART_UARTCR_RTS_MSB 11 +#define UART_UARTCR_RTS_LSB 11 +#define UART_UARTCR_RTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_DTR +// Description : Data transmit ready. This bit is the complement of the UART +// data transmit ready, nUARTDTR, modem status output. That is, +// when the bit is programmed to a 1 then nUARTDTR is LOW. +#define UART_UARTCR_DTR_RESET 0x0 +#define UART_UARTCR_DTR_BITS 0x00000400 +#define UART_UARTCR_DTR_MSB 10 +#define UART_UARTCR_DTR_LSB 10 +#define UART_UARTCR_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RXE +// Description : Receive enable. If this bit is set to 1, the receive section of +// the UART is enabled. Data reception occurs for either UART +// signals or SIR signals depending on the setting of the SIREN +// bit. When the UART is disabled in the middle of reception, it +// completes the current character before stopping. +#define UART_UARTCR_RXE_RESET 0x1 +#define UART_UARTCR_RXE_BITS 0x00000200 +#define UART_UARTCR_RXE_MSB 9 +#define UART_UARTCR_RXE_LSB 9 +#define UART_UARTCR_RXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_TXE +// Description : Transmit enable. If this bit is set to 1, the transmit section +// of the UART is enabled. Data transmission occurs for either +// UART signals, or SIR signals depending on the setting of the +// SIREN bit. When the UART is disabled in the middle of +// transmission, it completes the current character before +// stopping. +#define UART_UARTCR_TXE_RESET 0x1 +#define UART_UARTCR_TXE_BITS 0x00000100 +#define UART_UARTCR_TXE_MSB 8 +#define UART_UARTCR_TXE_LSB 8 +#define UART_UARTCR_TXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_LBE +// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is +// set to 1 and the SIRTEST bit in the Test Control Register, +// UARTTCR is set to 1, then the nSIROUT path is inverted, and fed +// through to the SIRIN path. The SIRTEST bit in the test register +// must be set to 1 to override the normal half-duplex SIR +// operation. This must be the requirement for accessing the test +// registers during normal operation, and SIRTEST must be cleared +// to 0 when loopback testing is finished. This feature reduces +// the amount of external coupling required during system test. If +// this bit is set to 1, and the SIRTEST bit is set to 0, the +// UARTTXD path is fed through to the UARTRXD path. In either SIR +// mode or UART mode, when this bit is set, the modem outputs are +// also fed through to the modem inputs. This bit is cleared to 0 +// on reset, to disable loopback. +#define UART_UARTCR_LBE_RESET 0x0 +#define UART_UARTCR_LBE_BITS 0x00000080 +#define UART_UARTCR_LBE_MSB 7 +#define UART_UARTCR_LBE_LSB 7 +#define UART_UARTCR_LBE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIRLP +// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding +// mode. If this bit is cleared to 0, low-level bits are +// transmitted as an active high pulse with a width of 3 / 16th of +// the bit period. If this bit is set to 1, low-level bits are +// transmitted with a pulse width that is 3 times the period of +// the IrLPBaud16 input signal, regardless of the selected bit +// rate. Setting this bit uses less power, but might reduce +// transmission distances. +#define UART_UARTCR_SIRLP_RESET 0x0 +#define UART_UARTCR_SIRLP_BITS 0x00000004 +#define UART_UARTCR_SIRLP_MSB 2 +#define UART_UARTCR_SIRLP_LSB 2 +#define UART_UARTCR_SIRLP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIREN +// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW +// (no light pulse generated), and signal transitions on SIRIN +// have no effect. 1 = IrDA SIR ENDEC is enabled. Data is +// transmitted and received on nSIROUT and SIRIN. UARTTXD remains +// HIGH, in the marking state. Signal transitions on UARTRXD or +// modem status inputs have no effect. This bit has no effect if +// the UARTEN bit disables the UART. +#define UART_UARTCR_SIREN_RESET 0x0 +#define UART_UARTCR_SIREN_BITS 0x00000002 +#define UART_UARTCR_SIREN_MSB 1 +#define UART_UARTCR_SIREN_LSB 1 +#define UART_UARTCR_SIREN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_UARTEN +// Description : UART enable: 0 = UART is disabled. If the UART is disabled in +// the middle of transmission or reception, it completes the +// current character before stopping. 1 = the UART is enabled. +// Data transmission and reception occurs for either UART signals +// or SIR signals depending on the setting of the SIREN bit. +#define UART_UARTCR_UARTEN_RESET 0x0 +#define UART_UARTCR_UARTEN_BITS 0x00000001 +#define UART_UARTCR_UARTEN_MSB 0 +#define UART_UARTCR_UARTEN_LSB 0 +#define UART_UARTCR_UARTEN_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIFLS +// Description : Interrupt FIFO Level Select Register, UARTIFLS +#define UART_UARTIFLS_OFFSET 0x00000034 +#define UART_UARTIFLS_BITS 0x0000003f +#define UART_UARTIFLS_RESET 0x00000012 +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_RXIFLSEL +// Description : Receive interrupt FIFO level select. The trigger points for the +// receive interrupt are as follows: b000 = Receive FIFO becomes +// >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = +// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes +// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full +// b101-b111 = reserved. +#define UART_UARTIFLS_RXIFLSEL_RESET 0x2 +#define UART_UARTIFLS_RXIFLSEL_BITS 0x00000038 +#define UART_UARTIFLS_RXIFLSEL_MSB 5 +#define UART_UARTIFLS_RXIFLSEL_LSB 3 +#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_TXIFLSEL +// Description : Transmit interrupt FIFO level select. The trigger points for +// the transmit interrupt are as follows: b000 = Transmit FIFO +// becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 +// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit +// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / +// 8 full b101-b111 = reserved. +#define UART_UARTIFLS_TXIFLSEL_RESET 0x2 +#define UART_UARTIFLS_TXIFLSEL_BITS 0x00000007 +#define UART_UARTIFLS_TXIFLSEL_MSB 2 +#define UART_UARTIFLS_TXIFLSEL_LSB 0 +#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIMSC +// Description : Interrupt Mask Set/Clear Register, UARTIMSC +#define UART_UARTIMSC_OFFSET 0x00000038 +#define UART_UARTIMSC_BITS 0x000007ff +#define UART_UARTIMSC_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_OEIM +// Description : Overrun error interrupt mask. A read returns the current mask +// for the UARTOEINTR interrupt. On a write of 1, the mask of the +// UARTOEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_OEIM_RESET 0x0 +#define UART_UARTIMSC_OEIM_BITS 0x00000400 +#define UART_UARTIMSC_OEIM_MSB 10 +#define UART_UARTIMSC_OEIM_LSB 10 +#define UART_UARTIMSC_OEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_BEIM +// Description : Break error interrupt mask. A read returns the current mask for +// the UARTBEINTR interrupt. On a write of 1, the mask of the +// UARTBEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_BEIM_RESET 0x0 +#define UART_UARTIMSC_BEIM_BITS 0x00000200 +#define UART_UARTIMSC_BEIM_MSB 9 +#define UART_UARTIMSC_BEIM_LSB 9 +#define UART_UARTIMSC_BEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_PEIM +// Description : Parity error interrupt mask. A read returns the current mask +// for the UARTPEINTR interrupt. On a write of 1, the mask of the +// UARTPEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_PEIM_RESET 0x0 +#define UART_UARTIMSC_PEIM_BITS 0x00000100 +#define UART_UARTIMSC_PEIM_MSB 8 +#define UART_UARTIMSC_PEIM_LSB 8 +#define UART_UARTIMSC_PEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_FEIM +// Description : Framing error interrupt mask. A read returns the current mask +// for the UARTFEINTR interrupt. On a write of 1, the mask of the +// UARTFEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_FEIM_RESET 0x0 +#define UART_UARTIMSC_FEIM_BITS 0x00000080 +#define UART_UARTIMSC_FEIM_MSB 7 +#define UART_UARTIMSC_FEIM_LSB 7 +#define UART_UARTIMSC_FEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RTIM +// Description : Receive timeout interrupt mask. A read returns the current mask +// for the UARTRTINTR interrupt. On a write of 1, the mask of the +// UARTRTINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RTIM_RESET 0x0 +#define UART_UARTIMSC_RTIM_BITS 0x00000040 +#define UART_UARTIMSC_RTIM_MSB 6 +#define UART_UARTIMSC_RTIM_LSB 6 +#define UART_UARTIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_TXIM +// Description : Transmit interrupt mask. A read returns the current mask for +// the UARTTXINTR interrupt. On a write of 1, the mask of the +// UARTTXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_TXIM_RESET 0x0 +#define UART_UARTIMSC_TXIM_BITS 0x00000020 +#define UART_UARTIMSC_TXIM_MSB 5 +#define UART_UARTIMSC_TXIM_LSB 5 +#define UART_UARTIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RXIM +// Description : Receive interrupt mask. A read returns the current mask for the +// UARTRXINTR interrupt. On a write of 1, the mask of the +// UARTRXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RXIM_RESET 0x0 +#define UART_UARTIMSC_RXIM_BITS 0x00000010 +#define UART_UARTIMSC_RXIM_MSB 4 +#define UART_UARTIMSC_RXIM_LSB 4 +#define UART_UARTIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DSRMIM +// Description : nUARTDSR modem interrupt mask. A read returns the current mask +// for the UARTDSRINTR interrupt. On a write of 1, the mask of the +// UARTDSRINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DSRMIM_RESET 0x0 +#define UART_UARTIMSC_DSRMIM_BITS 0x00000008 +#define UART_UARTIMSC_DSRMIM_MSB 3 +#define UART_UARTIMSC_DSRMIM_LSB 3 +#define UART_UARTIMSC_DSRMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DCDMIM +// Description : nUARTDCD modem interrupt mask. A read returns the current mask +// for the UARTDCDINTR interrupt. On a write of 1, the mask of the +// UARTDCDINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DCDMIM_RESET 0x0 +#define UART_UARTIMSC_DCDMIM_BITS 0x00000004 +#define UART_UARTIMSC_DCDMIM_MSB 2 +#define UART_UARTIMSC_DCDMIM_LSB 2 +#define UART_UARTIMSC_DCDMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_CTSMIM +// Description : nUARTCTS modem interrupt mask. A read returns the current mask +// for the UARTCTSINTR interrupt. On a write of 1, the mask of the +// UARTCTSINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_CTSMIM_RESET 0x0 +#define UART_UARTIMSC_CTSMIM_BITS 0x00000002 +#define UART_UARTIMSC_CTSMIM_MSB 1 +#define UART_UARTIMSC_CTSMIM_LSB 1 +#define UART_UARTIMSC_CTSMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RIMIM +// Description : nUARTRI modem interrupt mask. A read returns the current mask +// for the UARTRIINTR interrupt. On a write of 1, the mask of the +// UARTRIINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RIMIM_RESET 0x0 +#define UART_UARTIMSC_RIMIM_BITS 0x00000001 +#define UART_UARTIMSC_RIMIM_MSB 0 +#define UART_UARTIMSC_RIMIM_LSB 0 +#define UART_UARTIMSC_RIMIM_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTRIS +// Description : Raw Interrupt Status Register, UARTRIS +#define UART_UARTRIS_OFFSET 0x0000003c +#define UART_UARTRIS_BITS 0x000007ff +#define UART_UARTRIS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_OERIS +// Description : Overrun error interrupt status. Returns the raw interrupt state +// of the UARTOEINTR interrupt. +#define UART_UARTRIS_OERIS_RESET 0x0 +#define UART_UARTRIS_OERIS_BITS 0x00000400 +#define UART_UARTRIS_OERIS_MSB 10 +#define UART_UARTRIS_OERIS_LSB 10 +#define UART_UARTRIS_OERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_BERIS +// Description : Break error interrupt status. Returns the raw interrupt state +// of the UARTBEINTR interrupt. +#define UART_UARTRIS_BERIS_RESET 0x0 +#define UART_UARTRIS_BERIS_BITS 0x00000200 +#define UART_UARTRIS_BERIS_MSB 9 +#define UART_UARTRIS_BERIS_LSB 9 +#define UART_UARTRIS_BERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_PERIS +// Description : Parity error interrupt status. Returns the raw interrupt state +// of the UARTPEINTR interrupt. +#define UART_UARTRIS_PERIS_RESET 0x0 +#define UART_UARTRIS_PERIS_BITS 0x00000100 +#define UART_UARTRIS_PERIS_MSB 8 +#define UART_UARTRIS_PERIS_LSB 8 +#define UART_UARTRIS_PERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_FERIS +// Description : Framing error interrupt status. Returns the raw interrupt state +// of the UARTFEINTR interrupt. +#define UART_UARTRIS_FERIS_RESET 0x0 +#define UART_UARTRIS_FERIS_BITS 0x00000080 +#define UART_UARTRIS_FERIS_MSB 7 +#define UART_UARTRIS_FERIS_LSB 7 +#define UART_UARTRIS_FERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RTRIS +// Description : Receive timeout interrupt status. Returns the raw interrupt +// state of the UARTRTINTR interrupt. a +#define UART_UARTRIS_RTRIS_RESET 0x0 +#define UART_UARTRIS_RTRIS_BITS 0x00000040 +#define UART_UARTRIS_RTRIS_MSB 6 +#define UART_UARTRIS_RTRIS_LSB 6 +#define UART_UARTRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_TXRIS +// Description : Transmit interrupt status. Returns the raw interrupt state of +// the UARTTXINTR interrupt. +#define UART_UARTRIS_TXRIS_RESET 0x0 +#define UART_UARTRIS_TXRIS_BITS 0x00000020 +#define UART_UARTRIS_TXRIS_MSB 5 +#define UART_UARTRIS_TXRIS_LSB 5 +#define UART_UARTRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RXRIS +// Description : Receive interrupt status. Returns the raw interrupt state of +// the UARTRXINTR interrupt. +#define UART_UARTRIS_RXRIS_RESET 0x0 +#define UART_UARTRIS_RXRIS_BITS 0x00000010 +#define UART_UARTRIS_RXRIS_MSB 4 +#define UART_UARTRIS_RXRIS_LSB 4 +#define UART_UARTRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DSRRMIS +// Description : nUARTDSR modem interrupt status. Returns the raw interrupt +// state of the UARTDSRINTR interrupt. +#define UART_UARTRIS_DSRRMIS_RESET "-" +#define UART_UARTRIS_DSRRMIS_BITS 0x00000008 +#define UART_UARTRIS_DSRRMIS_MSB 3 +#define UART_UARTRIS_DSRRMIS_LSB 3 +#define UART_UARTRIS_DSRRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DCDRMIS +// Description : nUARTDCD modem interrupt status. Returns the raw interrupt +// state of the UARTDCDINTR interrupt. +#define UART_UARTRIS_DCDRMIS_RESET "-" +#define UART_UARTRIS_DCDRMIS_BITS 0x00000004 +#define UART_UARTRIS_DCDRMIS_MSB 2 +#define UART_UARTRIS_DCDRMIS_LSB 2 +#define UART_UARTRIS_DCDRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_CTSRMIS +// Description : nUARTCTS modem interrupt status. Returns the raw interrupt +// state of the UARTCTSINTR interrupt. +#define UART_UARTRIS_CTSRMIS_RESET "-" +#define UART_UARTRIS_CTSRMIS_BITS 0x00000002 +#define UART_UARTRIS_CTSRMIS_MSB 1 +#define UART_UARTRIS_CTSRMIS_LSB 1 +#define UART_UARTRIS_CTSRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RIRMIS +// Description : nUARTRI modem interrupt status. Returns the raw interrupt state +// of the UARTRIINTR interrupt. +#define UART_UARTRIS_RIRMIS_RESET "-" +#define UART_UARTRIS_RIRMIS_BITS 0x00000001 +#define UART_UARTRIS_RIRMIS_MSB 0 +#define UART_UARTRIS_RIRMIS_LSB 0 +#define UART_UARTRIS_RIRMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTMIS +// Description : Masked Interrupt Status Register, UARTMIS +#define UART_UARTMIS_OFFSET 0x00000040 +#define UART_UARTMIS_BITS 0x000007ff +#define UART_UARTMIS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_OEMIS +// Description : Overrun error masked interrupt status. Returns the masked +// interrupt state of the UARTOEINTR interrupt. +#define UART_UARTMIS_OEMIS_RESET 0x0 +#define UART_UARTMIS_OEMIS_BITS 0x00000400 +#define UART_UARTMIS_OEMIS_MSB 10 +#define UART_UARTMIS_OEMIS_LSB 10 +#define UART_UARTMIS_OEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_BEMIS +// Description : Break error masked interrupt status. Returns the masked +// interrupt state of the UARTBEINTR interrupt. +#define UART_UARTMIS_BEMIS_RESET 0x0 +#define UART_UARTMIS_BEMIS_BITS 0x00000200 +#define UART_UARTMIS_BEMIS_MSB 9 +#define UART_UARTMIS_BEMIS_LSB 9 +#define UART_UARTMIS_BEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_PEMIS +// Description : Parity error masked interrupt status. Returns the masked +// interrupt state of the UARTPEINTR interrupt. +#define UART_UARTMIS_PEMIS_RESET 0x0 +#define UART_UARTMIS_PEMIS_BITS 0x00000100 +#define UART_UARTMIS_PEMIS_MSB 8 +#define UART_UARTMIS_PEMIS_LSB 8 +#define UART_UARTMIS_PEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_FEMIS +// Description : Framing error masked interrupt status. Returns the masked +// interrupt state of the UARTFEINTR interrupt. +#define UART_UARTMIS_FEMIS_RESET 0x0 +#define UART_UARTMIS_FEMIS_BITS 0x00000080 +#define UART_UARTMIS_FEMIS_MSB 7 +#define UART_UARTMIS_FEMIS_LSB 7 +#define UART_UARTMIS_FEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RTMIS +// Description : Receive timeout masked interrupt status. Returns the masked +// interrupt state of the UARTRTINTR interrupt. +#define UART_UARTMIS_RTMIS_RESET 0x0 +#define UART_UARTMIS_RTMIS_BITS 0x00000040 +#define UART_UARTMIS_RTMIS_MSB 6 +#define UART_UARTMIS_RTMIS_LSB 6 +#define UART_UARTMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_TXMIS +// Description : Transmit masked interrupt status. Returns the masked interrupt +// state of the UARTTXINTR interrupt. +#define UART_UARTMIS_TXMIS_RESET 0x0 +#define UART_UARTMIS_TXMIS_BITS 0x00000020 +#define UART_UARTMIS_TXMIS_MSB 5 +#define UART_UARTMIS_TXMIS_LSB 5 +#define UART_UARTMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RXMIS +// Description : Receive masked interrupt status. Returns the masked interrupt +// state of the UARTRXINTR interrupt. +#define UART_UARTMIS_RXMIS_RESET 0x0 +#define UART_UARTMIS_RXMIS_BITS 0x00000010 +#define UART_UARTMIS_RXMIS_MSB 4 +#define UART_UARTMIS_RXMIS_LSB 4 +#define UART_UARTMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DSRMMIS +// Description : nUARTDSR modem masked interrupt status. Returns the masked +// interrupt state of the UARTDSRINTR interrupt. +#define UART_UARTMIS_DSRMMIS_RESET "-" +#define UART_UARTMIS_DSRMMIS_BITS 0x00000008 +#define UART_UARTMIS_DSRMMIS_MSB 3 +#define UART_UARTMIS_DSRMMIS_LSB 3 +#define UART_UARTMIS_DSRMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DCDMMIS +// Description : nUARTDCD modem masked interrupt status. Returns the masked +// interrupt state of the UARTDCDINTR interrupt. +#define UART_UARTMIS_DCDMMIS_RESET "-" +#define UART_UARTMIS_DCDMMIS_BITS 0x00000004 +#define UART_UARTMIS_DCDMMIS_MSB 2 +#define UART_UARTMIS_DCDMMIS_LSB 2 +#define UART_UARTMIS_DCDMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_CTSMMIS +// Description : nUARTCTS modem masked interrupt status. Returns the masked +// interrupt state of the UARTCTSINTR interrupt. +#define UART_UARTMIS_CTSMMIS_RESET "-" +#define UART_UARTMIS_CTSMMIS_BITS 0x00000002 +#define UART_UARTMIS_CTSMMIS_MSB 1 +#define UART_UARTMIS_CTSMMIS_LSB 1 +#define UART_UARTMIS_CTSMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RIMMIS +// Description : nUARTRI modem masked interrupt status. Returns the masked +// interrupt state of the UARTRIINTR interrupt. +#define UART_UARTMIS_RIMMIS_RESET "-" +#define UART_UARTMIS_RIMMIS_BITS 0x00000001 +#define UART_UARTMIS_RIMMIS_MSB 0 +#define UART_UARTMIS_RIMMIS_LSB 0 +#define UART_UARTMIS_RIMMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTICR +// Description : Interrupt Clear Register, UARTICR +#define UART_UARTICR_OFFSET 0x00000044 +#define UART_UARTICR_BITS 0x000007ff +#define UART_UARTICR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_OEIC +// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. +#define UART_UARTICR_OEIC_RESET "-" +#define UART_UARTICR_OEIC_BITS 0x00000400 +#define UART_UARTICR_OEIC_MSB 10 +#define UART_UARTICR_OEIC_LSB 10 +#define UART_UARTICR_OEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_BEIC +// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. +#define UART_UARTICR_BEIC_RESET "-" +#define UART_UARTICR_BEIC_BITS 0x00000200 +#define UART_UARTICR_BEIC_MSB 9 +#define UART_UARTICR_BEIC_LSB 9 +#define UART_UARTICR_BEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_PEIC +// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. +#define UART_UARTICR_PEIC_RESET "-" +#define UART_UARTICR_PEIC_BITS 0x00000100 +#define UART_UARTICR_PEIC_MSB 8 +#define UART_UARTICR_PEIC_LSB 8 +#define UART_UARTICR_PEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_FEIC +// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. +#define UART_UARTICR_FEIC_RESET "-" +#define UART_UARTICR_FEIC_BITS 0x00000080 +#define UART_UARTICR_FEIC_MSB 7 +#define UART_UARTICR_FEIC_LSB 7 +#define UART_UARTICR_FEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RTIC +// Description : Receive timeout interrupt clear. Clears the UARTRTINTR +// interrupt. +#define UART_UARTICR_RTIC_RESET "-" +#define UART_UARTICR_RTIC_BITS 0x00000040 +#define UART_UARTICR_RTIC_MSB 6 +#define UART_UARTICR_RTIC_LSB 6 +#define UART_UARTICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_TXIC +// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. +#define UART_UARTICR_TXIC_RESET "-" +#define UART_UARTICR_TXIC_BITS 0x00000020 +#define UART_UARTICR_TXIC_MSB 5 +#define UART_UARTICR_TXIC_LSB 5 +#define UART_UARTICR_TXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RXIC +// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. +#define UART_UARTICR_RXIC_RESET "-" +#define UART_UARTICR_RXIC_BITS 0x00000010 +#define UART_UARTICR_RXIC_MSB 4 +#define UART_UARTICR_RXIC_LSB 4 +#define UART_UARTICR_RXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DSRMIC +// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR +// interrupt. +#define UART_UARTICR_DSRMIC_RESET "-" +#define UART_UARTICR_DSRMIC_BITS 0x00000008 +#define UART_UARTICR_DSRMIC_MSB 3 +#define UART_UARTICR_DSRMIC_LSB 3 +#define UART_UARTICR_DSRMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DCDMIC +// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR +// interrupt. +#define UART_UARTICR_DCDMIC_RESET "-" +#define UART_UARTICR_DCDMIC_BITS 0x00000004 +#define UART_UARTICR_DCDMIC_MSB 2 +#define UART_UARTICR_DCDMIC_LSB 2 +#define UART_UARTICR_DCDMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_CTSMIC +// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR +// interrupt. +#define UART_UARTICR_CTSMIC_RESET "-" +#define UART_UARTICR_CTSMIC_BITS 0x00000002 +#define UART_UARTICR_CTSMIC_MSB 1 +#define UART_UARTICR_CTSMIC_LSB 1 +#define UART_UARTICR_CTSMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RIMIC +// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. +#define UART_UARTICR_RIMIC_RESET "-" +#define UART_UARTICR_RIMIC_BITS 0x00000001 +#define UART_UARTICR_RIMIC_MSB 0 +#define UART_UARTICR_RIMIC_LSB 0 +#define UART_UARTICR_RIMIC_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTDMACR +// Description : DMA Control Register, UARTDMACR +#define UART_UARTDMACR_OFFSET 0x00000048 +#define UART_UARTDMACR_BITS 0x00000007 +#define UART_UARTDMACR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_DMAONERR +// Description : DMA on error. If this bit is set to 1, the DMA receive request +// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the +// UART error interrupt is asserted. +#define UART_UARTDMACR_DMAONERR_RESET 0x0 +#define UART_UARTDMACR_DMAONERR_BITS 0x00000004 +#define UART_UARTDMACR_DMAONERR_MSB 2 +#define UART_UARTDMACR_DMAONERR_LSB 2 +#define UART_UARTDMACR_DMAONERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_TXDMAE +// Description : Transmit DMA enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define UART_UARTDMACR_TXDMAE_RESET 0x0 +#define UART_UARTDMACR_TXDMAE_BITS 0x00000002 +#define UART_UARTDMACR_TXDMAE_MSB 1 +#define UART_UARTDMACR_TXDMAE_LSB 1 +#define UART_UARTDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_RXDMAE +// Description : Receive DMA enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define UART_UARTDMACR_RXDMAE_RESET 0x0 +#define UART_UARTDMACR_RXDMAE_BITS 0x00000001 +#define UART_UARTDMACR_RXDMAE_MSB 0 +#define UART_UARTDMACR_RXDMAE_LSB 0 +#define UART_UARTDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTPERIPHID0 +// Description : UARTPeriphID0 Register +#define UART_UARTPERIPHID0_OFFSET 0x00000fe0 +#define UART_UARTPERIPHID0_BITS 0x000000ff +#define UART_UARTPERIPHID0_RESET 0x00000011 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x11 +#define UART_UARTPERIPHID0_PARTNUMBER0_RESET 0x11 +#define UART_UARTPERIPHID0_PARTNUMBER0_BITS 0x000000ff +#define UART_UARTPERIPHID0_PARTNUMBER0_MSB 7 +#define UART_UARTPERIPHID0_PARTNUMBER0_LSB 0 +#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID1 +// Description : UARTPeriphID1 Register +#define UART_UARTPERIPHID1_OFFSET 0x00000fe4 +#define UART_UARTPERIPHID1_BITS 0x000000ff +#define UART_UARTPERIPHID1_RESET 0x00000010 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define UART_UARTPERIPHID1_DESIGNER0_RESET 0x1 +#define UART_UARTPERIPHID1_DESIGNER0_BITS 0x000000f0 +#define UART_UARTPERIPHID1_DESIGNER0_MSB 7 +#define UART_UARTPERIPHID1_DESIGNER0_LSB 4 +#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define UART_UARTPERIPHID1_PARTNUMBER1_RESET 0x0 +#define UART_UARTPERIPHID1_PARTNUMBER1_BITS 0x0000000f +#define UART_UARTPERIPHID1_PARTNUMBER1_MSB 3 +#define UART_UARTPERIPHID1_PARTNUMBER1_LSB 0 +#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID2 +// Description : UARTPeriphID2 Register +#define UART_UARTPERIPHID2_OFFSET 0x00000fe8 +#define UART_UARTPERIPHID2_BITS 0x000000ff +#define UART_UARTPERIPHID2_RESET 0x00000034 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_REVISION +// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 +// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 +#define UART_UARTPERIPHID2_REVISION_RESET 0x3 +#define UART_UARTPERIPHID2_REVISION_BITS 0x000000f0 +#define UART_UARTPERIPHID2_REVISION_MSB 7 +#define UART_UARTPERIPHID2_REVISION_LSB 4 +#define UART_UARTPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define UART_UARTPERIPHID2_DESIGNER1_RESET 0x4 +#define UART_UARTPERIPHID2_DESIGNER1_BITS 0x0000000f +#define UART_UARTPERIPHID2_DESIGNER1_MSB 3 +#define UART_UARTPERIPHID2_DESIGNER1_LSB 0 +#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID3 +// Description : UARTPeriphID3 Register +#define UART_UARTPERIPHID3_OFFSET 0x00000fec +#define UART_UARTPERIPHID3_BITS 0x000000ff +#define UART_UARTPERIPHID3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define UART_UARTPERIPHID3_CONFIGURATION_RESET 0x00 +#define UART_UARTPERIPHID3_CONFIGURATION_BITS 0x000000ff +#define UART_UARTPERIPHID3_CONFIGURATION_MSB 7 +#define UART_UARTPERIPHID3_CONFIGURATION_LSB 0 +#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID0 +// Description : UARTPCellID0 Register +#define UART_UARTPCELLID0_OFFSET 0x00000ff0 +#define UART_UARTPCELLID0_BITS 0x000000ff +#define UART_UARTPCELLID0_RESET 0x0000000d +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID0_UARTPCELLID0 +// Description : These bits read back as 0x0D +#define UART_UARTPCELLID0_UARTPCELLID0_RESET 0x0d +#define UART_UARTPCELLID0_UARTPCELLID0_BITS 0x000000ff +#define UART_UARTPCELLID0_UARTPCELLID0_MSB 7 +#define UART_UARTPCELLID0_UARTPCELLID0_LSB 0 +#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID1 +// Description : UARTPCellID1 Register +#define UART_UARTPCELLID1_OFFSET 0x00000ff4 +#define UART_UARTPCELLID1_BITS 0x000000ff +#define UART_UARTPCELLID1_RESET 0x000000f0 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID1_UARTPCELLID1 +// Description : These bits read back as 0xF0 +#define UART_UARTPCELLID1_UARTPCELLID1_RESET 0xf0 +#define UART_UARTPCELLID1_UARTPCELLID1_BITS 0x000000ff +#define UART_UARTPCELLID1_UARTPCELLID1_MSB 7 +#define UART_UARTPCELLID1_UARTPCELLID1_LSB 0 +#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID2 +// Description : UARTPCellID2 Register +#define UART_UARTPCELLID2_OFFSET 0x00000ff8 +#define UART_UARTPCELLID2_BITS 0x000000ff +#define UART_UARTPCELLID2_RESET 0x00000005 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID2_UARTPCELLID2 +// Description : These bits read back as 0x05 +#define UART_UARTPCELLID2_UARTPCELLID2_RESET 0x05 +#define UART_UARTPCELLID2_UARTPCELLID2_BITS 0x000000ff +#define UART_UARTPCELLID2_UARTPCELLID2_MSB 7 +#define UART_UARTPCELLID2_UARTPCELLID2_LSB 0 +#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID3 +// Description : UARTPCellID3 Register +#define UART_UARTPCELLID3_OFFSET 0x00000ffc +#define UART_UARTPCELLID3_BITS 0x000000ff +#define UART_UARTPCELLID3_RESET 0x000000b1 +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID3_UARTPCELLID3 +// Description : These bits read back as 0xB1 +#define UART_UARTPCELLID3_UARTPCELLID3_RESET 0xb1 +#define UART_UARTPCELLID3_UARTPCELLID3_BITS 0x000000ff +#define UART_UARTPCELLID3_UARTPCELLID3_MSB 7 +#define UART_UARTPCELLID3_UARTPCELLID3_LSB 0 +#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_UART_DEFINED diff --git a/rp2040/hardware/regs/usb.h b/rp2040/hardware/regs/usb.h new file mode 100644 index 0000000..6693205 --- /dev/null +++ b/rp2040/hardware/regs/usb.h @@ -0,0 +1,3603 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB +// Version : 1 +// Bus type : ahbl +// Description : USB FS/LS controller device registers +// ============================================================================= +#ifndef HARDWARE_REGS_USB_DEFINED +#define HARDWARE_REGS_USB_DEFINED +// ============================================================================= +// Register : USB_ADDR_ENDP +// Description : Device address and endpoint control +#define USB_ADDR_ENDP_OFFSET 0x00000000 +#define USB_ADDR_ENDP_BITS 0x000f007f +#define USB_ADDR_ENDP_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ENDPOINT +// Description : Device endpoint to send data to. Only valid for HOST mode. +#define USB_ADDR_ENDP_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ADDRESS +// Description : In device mode, the address that the device should respond to. +// Set in response to a SET_ADDR setup packet from the host. In +// host mode set to the address of the device to communicate with. +#define USB_ADDR_ENDP_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP_ADDRESS_MSB 6 +#define USB_ADDR_ENDP_ADDRESS_LSB 0 +#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP1 +// Description : Interrupt endpoint 1. Only valid for HOST mode. +#define USB_ADDR_ENDP1_OFFSET 0x00000004 +#define USB_ADDR_ENDP1_BITS 0x060f007f +#define USB_ADDR_ENDP1_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP1_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP1_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP1_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP1_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP1_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP1_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP1_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP1_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP1_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP1_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP1_ADDRESS_MSB 6 +#define USB_ADDR_ENDP1_ADDRESS_LSB 0 +#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP2 +// Description : Interrupt endpoint 2. Only valid for HOST mode. +#define USB_ADDR_ENDP2_OFFSET 0x00000008 +#define USB_ADDR_ENDP2_BITS 0x060f007f +#define USB_ADDR_ENDP2_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP2_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP2_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP2_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP2_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP2_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP2_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP2_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP2_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP2_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP2_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP2_ADDRESS_MSB 6 +#define USB_ADDR_ENDP2_ADDRESS_LSB 0 +#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP3 +// Description : Interrupt endpoint 3. Only valid for HOST mode. +#define USB_ADDR_ENDP3_OFFSET 0x0000000c +#define USB_ADDR_ENDP3_BITS 0x060f007f +#define USB_ADDR_ENDP3_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP3_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP3_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP3_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP3_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP3_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP3_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP3_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP3_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP3_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP3_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP3_ADDRESS_MSB 6 +#define USB_ADDR_ENDP3_ADDRESS_LSB 0 +#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP4 +// Description : Interrupt endpoint 4. Only valid for HOST mode. +#define USB_ADDR_ENDP4_OFFSET 0x00000010 +#define USB_ADDR_ENDP4_BITS 0x060f007f +#define USB_ADDR_ENDP4_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP4_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP4_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP4_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP4_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP4_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP4_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP4_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP4_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP4_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP4_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP4_ADDRESS_MSB 6 +#define USB_ADDR_ENDP4_ADDRESS_LSB 0 +#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP5 +// Description : Interrupt endpoint 5. Only valid for HOST mode. +#define USB_ADDR_ENDP5_OFFSET 0x00000014 +#define USB_ADDR_ENDP5_BITS 0x060f007f +#define USB_ADDR_ENDP5_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP5_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP5_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP5_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP5_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP5_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP5_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP5_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP5_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP5_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP5_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP5_ADDRESS_MSB 6 +#define USB_ADDR_ENDP5_ADDRESS_LSB 0 +#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP6 +// Description : Interrupt endpoint 6. Only valid for HOST mode. +#define USB_ADDR_ENDP6_OFFSET 0x00000018 +#define USB_ADDR_ENDP6_BITS 0x060f007f +#define USB_ADDR_ENDP6_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP6_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP6_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP6_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP6_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP6_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP6_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP6_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP6_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP6_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP6_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP6_ADDRESS_MSB 6 +#define USB_ADDR_ENDP6_ADDRESS_LSB 0 +#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP7 +// Description : Interrupt endpoint 7. Only valid for HOST mode. +#define USB_ADDR_ENDP7_OFFSET 0x0000001c +#define USB_ADDR_ENDP7_BITS 0x060f007f +#define USB_ADDR_ENDP7_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP7_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP7_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP7_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP7_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP7_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP7_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP7_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP7_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP7_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP7_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP7_ADDRESS_MSB 6 +#define USB_ADDR_ENDP7_ADDRESS_LSB 0 +#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP8 +// Description : Interrupt endpoint 8. Only valid for HOST mode. +#define USB_ADDR_ENDP8_OFFSET 0x00000020 +#define USB_ADDR_ENDP8_BITS 0x060f007f +#define USB_ADDR_ENDP8_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP8_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP8_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP8_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP8_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP8_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP8_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP8_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP8_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP8_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP8_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP8_ADDRESS_MSB 6 +#define USB_ADDR_ENDP8_ADDRESS_LSB 0 +#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP9 +// Description : Interrupt endpoint 9. Only valid for HOST mode. +#define USB_ADDR_ENDP9_OFFSET 0x00000024 +#define USB_ADDR_ENDP9_BITS 0x060f007f +#define USB_ADDR_ENDP9_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP9_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP9_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP9_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP9_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP9_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP9_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP9_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP9_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP9_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP9_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP9_ADDRESS_MSB 6 +#define USB_ADDR_ENDP9_ADDRESS_LSB 0 +#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP10 +// Description : Interrupt endpoint 10. Only valid for HOST mode. +#define USB_ADDR_ENDP10_OFFSET 0x00000028 +#define USB_ADDR_ENDP10_BITS 0x060f007f +#define USB_ADDR_ENDP10_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP10_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP10_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP10_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP10_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP10_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP10_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP10_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP10_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP10_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP10_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP10_ADDRESS_MSB 6 +#define USB_ADDR_ENDP10_ADDRESS_LSB 0 +#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP11 +// Description : Interrupt endpoint 11. Only valid for HOST mode. +#define USB_ADDR_ENDP11_OFFSET 0x0000002c +#define USB_ADDR_ENDP11_BITS 0x060f007f +#define USB_ADDR_ENDP11_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP11_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP11_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP11_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP11_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP11_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP11_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP11_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP11_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP11_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP11_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP11_ADDRESS_MSB 6 +#define USB_ADDR_ENDP11_ADDRESS_LSB 0 +#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP12 +// Description : Interrupt endpoint 12. Only valid for HOST mode. +#define USB_ADDR_ENDP12_OFFSET 0x00000030 +#define USB_ADDR_ENDP12_BITS 0x060f007f +#define USB_ADDR_ENDP12_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP12_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP12_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP12_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP12_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP12_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP12_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP12_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP12_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP12_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP12_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP12_ADDRESS_MSB 6 +#define USB_ADDR_ENDP12_ADDRESS_LSB 0 +#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP13 +// Description : Interrupt endpoint 13. Only valid for HOST mode. +#define USB_ADDR_ENDP13_OFFSET 0x00000034 +#define USB_ADDR_ENDP13_BITS 0x060f007f +#define USB_ADDR_ENDP13_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP13_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP13_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP13_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP13_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP13_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP13_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP13_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP13_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP13_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP13_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP13_ADDRESS_MSB 6 +#define USB_ADDR_ENDP13_ADDRESS_LSB 0 +#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP14 +// Description : Interrupt endpoint 14. Only valid for HOST mode. +#define USB_ADDR_ENDP14_OFFSET 0x00000038 +#define USB_ADDR_ENDP14_BITS 0x060f007f +#define USB_ADDR_ENDP14_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP14_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP14_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP14_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP14_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP14_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP14_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP14_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP14_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP14_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP14_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP14_ADDRESS_MSB 6 +#define USB_ADDR_ENDP14_ADDRESS_LSB 0 +#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP15 +// Description : Interrupt endpoint 15. Only valid for HOST mode. +#define USB_ADDR_ENDP15_OFFSET 0x0000003c +#define USB_ADDR_ENDP15_BITS 0x060f007f +#define USB_ADDR_ENDP15_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET 0x0 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS 0x04000000 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB 26 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB 26 +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP15_INTEP_DIR_RESET 0x0 +#define USB_ADDR_ENDP15_INTEP_DIR_BITS 0x02000000 +#define USB_ADDR_ENDP15_INTEP_DIR_MSB 25 +#define USB_ADDR_ENDP15_INTEP_DIR_LSB 25 +#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP15_ENDPOINT_RESET 0x0 +#define USB_ADDR_ENDP15_ENDPOINT_BITS 0x000f0000 +#define USB_ADDR_ENDP15_ENDPOINT_MSB 19 +#define USB_ADDR_ENDP15_ENDPOINT_LSB 16 +#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP15_ADDRESS_RESET 0x00 +#define USB_ADDR_ENDP15_ADDRESS_BITS 0x0000007f +#define USB_ADDR_ENDP15_ADDRESS_MSB 6 +#define USB_ADDR_ENDP15_ADDRESS_LSB 0 +#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_MAIN_CTRL +// Description : Main control register +#define USB_MAIN_CTRL_OFFSET 0x00000040 +#define USB_MAIN_CTRL_BITS 0x80000003 +#define USB_MAIN_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_SIM_TIMING +// Description : Reduced timings for simulation +#define USB_MAIN_CTRL_SIM_TIMING_RESET 0x0 +#define USB_MAIN_CTRL_SIM_TIMING_BITS 0x80000000 +#define USB_MAIN_CTRL_SIM_TIMING_MSB 31 +#define USB_MAIN_CTRL_SIM_TIMING_LSB 31 +#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_HOST_NDEVICE +// Description : Device mode = 0, Host mode = 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_RESET 0x0 +#define USB_MAIN_CTRL_HOST_NDEVICE_BITS 0x00000002 +#define USB_MAIN_CTRL_HOST_NDEVICE_MSB 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_LSB 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_CONTROLLER_EN +// Description : Enable controller +#define USB_MAIN_CTRL_CONTROLLER_EN_RESET 0x0 +#define USB_MAIN_CTRL_CONTROLLER_EN_BITS 0x00000001 +#define USB_MAIN_CTRL_CONTROLLER_EN_MSB 0 +#define USB_MAIN_CTRL_CONTROLLER_EN_LSB 0 +#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_SOF_WR +// Description : Set the SOF (Start of Frame) frame number in the host +// controller. The SOF packet is sent every 1ms and the host will +// increment the frame number by 1 each time. +#define USB_SOF_WR_OFFSET 0x00000044 +#define USB_SOF_WR_BITS 0x000007ff +#define USB_SOF_WR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SOF_WR_COUNT +// Description : None +#define USB_SOF_WR_COUNT_RESET 0x000 +#define USB_SOF_WR_COUNT_BITS 0x000007ff +#define USB_SOF_WR_COUNT_MSB 10 +#define USB_SOF_WR_COUNT_LSB 0 +#define USB_SOF_WR_COUNT_ACCESS "WF" +// ============================================================================= +// Register : USB_SOF_RD +// Description : Read the last SOF (Start of Frame) frame number seen. In device +// mode the last SOF received from the host. In host mode the last +// SOF sent by the host. +#define USB_SOF_RD_OFFSET 0x00000048 +#define USB_SOF_RD_BITS 0x000007ff +#define USB_SOF_RD_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SOF_RD_COUNT +// Description : None +#define USB_SOF_RD_COUNT_RESET 0x000 +#define USB_SOF_RD_COUNT_BITS 0x000007ff +#define USB_SOF_RD_COUNT_MSB 10 +#define USB_SOF_RD_COUNT_LSB 0 +#define USB_SOF_RD_COUNT_ACCESS "RO" +// ============================================================================= +// Register : USB_SIE_CTRL +// Description : SIE control register +#define USB_SIE_CTRL_OFFSET 0x0000004c +#define USB_SIE_CTRL_BITS 0xff07bf5f +#define USB_SIE_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_STALL +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL +#define USB_SIE_CTRL_EP0_INT_STALL_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_STALL_BITS 0x80000000 +#define USB_SIE_CTRL_EP0_INT_STALL_MSB 31 +#define USB_SIE_CTRL_EP0_INT_STALL_LSB 31 +#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF +// Description : Device: EP0 single buffered = 0, double buffered = 1 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET 0x0 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS 0x40000000 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB 30 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB 30 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_1BUF +// Description : Device: Set bit in BUFF_STATUS for every buffer completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_1BUF_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_1BUF_BITS 0x20000000 +#define USB_SIE_CTRL_EP0_INT_1BUF_MSB 29 +#define USB_SIE_CTRL_EP0_INT_1BUF_LSB 29 +#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_2BUF +// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_2BUF_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_2BUF_BITS 0x10000000 +#define USB_SIE_CTRL_EP0_INT_2BUF_MSB 28 +#define USB_SIE_CTRL_EP0_INT_2BUF_LSB 28 +#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_NAK +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK +#define USB_SIE_CTRL_EP0_INT_NAK_RESET 0x0 +#define USB_SIE_CTRL_EP0_INT_NAK_BITS 0x08000000 +#define USB_SIE_CTRL_EP0_INT_NAK_MSB 27 +#define USB_SIE_CTRL_EP0_INT_NAK_LSB 27 +#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_EN +// Description : Direct bus drive enable +#define USB_SIE_CTRL_DIRECT_EN_RESET 0x0 +#define USB_SIE_CTRL_DIRECT_EN_BITS 0x04000000 +#define USB_SIE_CTRL_DIRECT_EN_MSB 26 +#define USB_SIE_CTRL_DIRECT_EN_LSB 26 +#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DP +// Description : Direct control of DP +#define USB_SIE_CTRL_DIRECT_DP_RESET 0x0 +#define USB_SIE_CTRL_DIRECT_DP_BITS 0x02000000 +#define USB_SIE_CTRL_DIRECT_DP_MSB 25 +#define USB_SIE_CTRL_DIRECT_DP_LSB 25 +#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DM +// Description : Direct control of DM +#define USB_SIE_CTRL_DIRECT_DM_RESET 0x0 +#define USB_SIE_CTRL_DIRECT_DM_BITS 0x01000000 +#define USB_SIE_CTRL_DIRECT_DM_MSB 24 +#define USB_SIE_CTRL_DIRECT_DM_LSB 24 +#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_TRANSCEIVER_PD +// Description : Power down bus transceiver +#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET 0x0 +#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS 0x00040000 +#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB 18 +#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB 18 +#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RPU_OPT +// Description : Device: Pull-up strength (0=1K2, 1=2k3) +#define USB_SIE_CTRL_RPU_OPT_RESET 0x0 +#define USB_SIE_CTRL_RPU_OPT_BITS 0x00020000 +#define USB_SIE_CTRL_RPU_OPT_MSB 17 +#define USB_SIE_CTRL_RPU_OPT_LSB 17 +#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLUP_EN +// Description : Device: Enable pull up resistor +#define USB_SIE_CTRL_PULLUP_EN_RESET 0x0 +#define USB_SIE_CTRL_PULLUP_EN_BITS 0x00010000 +#define USB_SIE_CTRL_PULLUP_EN_MSB 16 +#define USB_SIE_CTRL_PULLUP_EN_LSB 16 +#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLDOWN_EN +// Description : Host: Enable pull down resistors +#define USB_SIE_CTRL_PULLDOWN_EN_RESET 0x0 +#define USB_SIE_CTRL_PULLDOWN_EN_BITS 0x00008000 +#define USB_SIE_CTRL_PULLDOWN_EN_MSB 15 +#define USB_SIE_CTRL_PULLDOWN_EN_LSB 15 +#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESET_BUS +// Description : Host: Reset bus +#define USB_SIE_CTRL_RESET_BUS_RESET 0x0 +#define USB_SIE_CTRL_RESET_BUS_BITS 0x00002000 +#define USB_SIE_CTRL_RESET_BUS_MSB 13 +#define USB_SIE_CTRL_RESET_BUS_LSB 13 +#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESUME +// Description : Device: Remote wakeup. Device can initiate its own resume after +// suspend. +#define USB_SIE_CTRL_RESUME_RESET 0x0 +#define USB_SIE_CTRL_RESUME_BITS 0x00001000 +#define USB_SIE_CTRL_RESUME_MSB 12 +#define USB_SIE_CTRL_RESUME_LSB 12 +#define USB_SIE_CTRL_RESUME_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_VBUS_EN +// Description : Host: Enable VBUS +#define USB_SIE_CTRL_VBUS_EN_RESET 0x0 +#define USB_SIE_CTRL_VBUS_EN_BITS 0x00000800 +#define USB_SIE_CTRL_VBUS_EN_MSB 11 +#define USB_SIE_CTRL_VBUS_EN_LSB 11 +#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_KEEP_ALIVE_EN +// Description : Host: Enable keep alive packet (for low speed bus) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET 0x0 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS 0x00000400 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB 10 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB 10 +#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_EN +// Description : Host: Enable SOF generation (for full speed bus) +#define USB_SIE_CTRL_SOF_EN_RESET 0x0 +#define USB_SIE_CTRL_SOF_EN_BITS 0x00000200 +#define USB_SIE_CTRL_SOF_EN_MSB 9 +#define USB_SIE_CTRL_SOF_EN_LSB 9 +#define USB_SIE_CTRL_SOF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_SYNC +// Description : Host: Delay packet(s) until after SOF +#define USB_SIE_CTRL_SOF_SYNC_RESET 0x0 +#define USB_SIE_CTRL_SOF_SYNC_BITS 0x00000100 +#define USB_SIE_CTRL_SOF_SYNC_MSB 8 +#define USB_SIE_CTRL_SOF_SYNC_LSB 8 +#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PREAMBLE_EN +// Description : Host: Preable enable for LS device on FS hub +#define USB_SIE_CTRL_PREAMBLE_EN_RESET 0x0 +#define USB_SIE_CTRL_PREAMBLE_EN_BITS 0x00000040 +#define USB_SIE_CTRL_PREAMBLE_EN_MSB 6 +#define USB_SIE_CTRL_PREAMBLE_EN_LSB 6 +#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_STOP_TRANS +// Description : Host: Stop transaction +#define USB_SIE_CTRL_STOP_TRANS_RESET 0x0 +#define USB_SIE_CTRL_STOP_TRANS_BITS 0x00000010 +#define USB_SIE_CTRL_STOP_TRANS_MSB 4 +#define USB_SIE_CTRL_STOP_TRANS_LSB 4 +#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RECEIVE_DATA +// Description : Host: Receive transaction (IN to host) +#define USB_SIE_CTRL_RECEIVE_DATA_RESET 0x0 +#define USB_SIE_CTRL_RECEIVE_DATA_BITS 0x00000008 +#define USB_SIE_CTRL_RECEIVE_DATA_MSB 3 +#define USB_SIE_CTRL_RECEIVE_DATA_LSB 3 +#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_DATA +// Description : Host: Send transaction (OUT from host) +#define USB_SIE_CTRL_SEND_DATA_RESET 0x0 +#define USB_SIE_CTRL_SEND_DATA_BITS 0x00000004 +#define USB_SIE_CTRL_SEND_DATA_MSB 2 +#define USB_SIE_CTRL_SEND_DATA_LSB 2 +#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_SETUP +// Description : Host: Send Setup packet +#define USB_SIE_CTRL_SEND_SETUP_RESET 0x0 +#define USB_SIE_CTRL_SEND_SETUP_BITS 0x00000002 +#define USB_SIE_CTRL_SEND_SETUP_MSB 1 +#define USB_SIE_CTRL_SEND_SETUP_LSB 1 +#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_START_TRANS +// Description : Host: Start transaction +#define USB_SIE_CTRL_START_TRANS_RESET 0x0 +#define USB_SIE_CTRL_START_TRANS_BITS 0x00000001 +#define USB_SIE_CTRL_START_TRANS_MSB 0 +#define USB_SIE_CTRL_START_TRANS_LSB 0 +#define USB_SIE_CTRL_START_TRANS_ACCESS "SC" +// ============================================================================= +// Register : USB_SIE_STATUS +// Description : SIE status register +#define USB_SIE_STATUS_OFFSET 0x00000050 +#define USB_SIE_STATUS_BITS 0xff0f0f1d +#define USB_SIE_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_DATA_SEQ_ERROR +// Description : Data Sequence Error. +// +// The device can raise a sequence error in the following +// conditions: +// +// * A SETUP packet is received followed by a DATA1 packet (data +// phase should always be DATA0) * An OUT packet is received from +// the host but doesn't match the data pid in the buffer control +// register read from DPSRAM +// +// The host can raise a data sequence error in the following +// conditions: +// +// * An IN packet from the device has the wrong data PID +#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET 0x0 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS 0x80000000 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB 31 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB 31 +#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_ACK_REC +// Description : ACK received. Raised by both host and device. +#define USB_SIE_STATUS_ACK_REC_RESET 0x0 +#define USB_SIE_STATUS_ACK_REC_BITS 0x40000000 +#define USB_SIE_STATUS_ACK_REC_MSB 30 +#define USB_SIE_STATUS_ACK_REC_LSB 30 +#define USB_SIE_STATUS_ACK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_STALL_REC +// Description : Host: STALL received +#define USB_SIE_STATUS_STALL_REC_RESET 0x0 +#define USB_SIE_STATUS_STALL_REC_BITS 0x20000000 +#define USB_SIE_STATUS_STALL_REC_MSB 29 +#define USB_SIE_STATUS_STALL_REC_LSB 29 +#define USB_SIE_STATUS_STALL_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_NAK_REC +// Description : Host: NAK received +#define USB_SIE_STATUS_NAK_REC_RESET 0x0 +#define USB_SIE_STATUS_NAK_REC_BITS 0x10000000 +#define USB_SIE_STATUS_NAK_REC_MSB 28 +#define USB_SIE_STATUS_NAK_REC_LSB 28 +#define USB_SIE_STATUS_NAK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_TIMEOUT +// Description : RX timeout is raised by both the host and device if an ACK is +// not received in the maximum time specified by the USB spec. +#define USB_SIE_STATUS_RX_TIMEOUT_RESET 0x0 +#define USB_SIE_STATUS_RX_TIMEOUT_BITS 0x08000000 +#define USB_SIE_STATUS_RX_TIMEOUT_MSB 27 +#define USB_SIE_STATUS_RX_TIMEOUT_LSB 27 +#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_OVERFLOW +// Description : RX overflow is raised by the Serial RX engine if the incoming +// data is too fast. +#define USB_SIE_STATUS_RX_OVERFLOW_RESET 0x0 +#define USB_SIE_STATUS_RX_OVERFLOW_BITS 0x04000000 +#define USB_SIE_STATUS_RX_OVERFLOW_MSB 26 +#define USB_SIE_STATUS_RX_OVERFLOW_LSB 26 +#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BIT_STUFF_ERROR +// Description : Bit Stuff Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET 0x0 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS 0x02000000 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB 25 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB 25 +#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CRC_ERROR +// Description : CRC Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_CRC_ERROR_RESET 0x0 +#define USB_SIE_STATUS_CRC_ERROR_BITS 0x01000000 +#define USB_SIE_STATUS_CRC_ERROR_MSB 24 +#define USB_SIE_STATUS_CRC_ERROR_LSB 24 +#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BUS_RESET +// Description : Device: bus reset received +#define USB_SIE_STATUS_BUS_RESET_RESET 0x0 +#define USB_SIE_STATUS_BUS_RESET_BITS 0x00080000 +#define USB_SIE_STATUS_BUS_RESET_MSB 19 +#define USB_SIE_STATUS_BUS_RESET_LSB 19 +#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_TRANS_COMPLETE +// Description : Transaction complete. +// +// Raised by device if: +// +// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in +// the buffer control register +// +// Raised by host if: +// +// * A setup packet is sent when no data in or data out +// transaction follows * An IN packet is received and the +// `LAST_BUFF` bit is set in the buffer control register * An IN +// packet is received with zero length * An OUT packet is sent and +// the `LAST_BUFF` bit is set +#define USB_SIE_STATUS_TRANS_COMPLETE_RESET 0x0 +#define USB_SIE_STATUS_TRANS_COMPLETE_BITS 0x00040000 +#define USB_SIE_STATUS_TRANS_COMPLETE_MSB 18 +#define USB_SIE_STATUS_TRANS_COMPLETE_LSB 18 +#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SETUP_REC +// Description : Device: Setup packet received +#define USB_SIE_STATUS_SETUP_REC_RESET 0x0 +#define USB_SIE_STATUS_SETUP_REC_BITS 0x00020000 +#define USB_SIE_STATUS_SETUP_REC_MSB 17 +#define USB_SIE_STATUS_SETUP_REC_LSB 17 +#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CONNECTED +// Description : Device: connected +#define USB_SIE_STATUS_CONNECTED_RESET 0x0 +#define USB_SIE_STATUS_CONNECTED_BITS 0x00010000 +#define USB_SIE_STATUS_CONNECTED_MSB 16 +#define USB_SIE_STATUS_CONNECTED_LSB 16 +#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RESUME +// Description : Host: Device has initiated a remote resume. Device: host has +// initiated a resume. +#define USB_SIE_STATUS_RESUME_RESET 0x0 +#define USB_SIE_STATUS_RESUME_BITS 0x00000800 +#define USB_SIE_STATUS_RESUME_MSB 11 +#define USB_SIE_STATUS_RESUME_LSB 11 +#define USB_SIE_STATUS_RESUME_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_OVER_CURR +// Description : VBUS over current detected +#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET 0x0 +#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS 0x00000400 +#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB 10 +#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB 10 +#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SPEED +// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 +#define USB_SIE_STATUS_SPEED_RESET 0x0 +#define USB_SIE_STATUS_SPEED_BITS 0x00000300 +#define USB_SIE_STATUS_SPEED_MSB 9 +#define USB_SIE_STATUS_SPEED_LSB 8 +#define USB_SIE_STATUS_SPEED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SUSPENDED +// Description : Bus in suspended state. Valid for device and host. Host and +// device will go into suspend if neither Keep Alive / SOF frames +// are enabled. +#define USB_SIE_STATUS_SUSPENDED_RESET 0x0 +#define USB_SIE_STATUS_SUSPENDED_BITS 0x00000010 +#define USB_SIE_STATUS_SUSPENDED_MSB 4 +#define USB_SIE_STATUS_SUSPENDED_LSB 4 +#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_LINE_STATE +// Description : USB bus line state +#define USB_SIE_STATUS_LINE_STATE_RESET 0x0 +#define USB_SIE_STATUS_LINE_STATE_BITS 0x0000000c +#define USB_SIE_STATUS_LINE_STATE_MSB 3 +#define USB_SIE_STATUS_LINE_STATE_LSB 2 +#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_DETECTED +// Description : Device: VBUS Detected +#define USB_SIE_STATUS_VBUS_DETECTED_RESET 0x0 +#define USB_SIE_STATUS_VBUS_DETECTED_BITS 0x00000001 +#define USB_SIE_STATUS_VBUS_DETECTED_MSB 0 +#define USB_SIE_STATUS_VBUS_DETECTED_LSB 0 +#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" +// ============================================================================= +// Register : USB_INT_EP_CTRL +// Description : interrupt endpoint control register +#define USB_INT_EP_CTRL_OFFSET 0x00000054 +#define USB_INT_EP_CTRL_BITS 0x0000fffe +#define USB_INT_EP_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE +// Description : Host: Enable interrupt endpoint 1 -> 15 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET 0x0000 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS 0x0000fffe +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB 15 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB 1 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : USB_BUFF_STATUS +// Description : Buffer status register. A bit set here indicates that a buffer +// has completed on the endpoint (if the buffer interrupt is +// enabled). It is possible for 2 buffers to be completed, so +// clearing the buffer status bit may instantly re set it on the +// next clock cycle. +#define USB_BUFF_STATUS_OFFSET 0x00000058 +#define USB_BUFF_STATUS_BITS 0xffffffff +#define USB_BUFF_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_OUT +// Description : None +#define USB_BUFF_STATUS_EP15_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP15_OUT_BITS 0x80000000 +#define USB_BUFF_STATUS_EP15_OUT_MSB 31 +#define USB_BUFF_STATUS_EP15_OUT_LSB 31 +#define USB_BUFF_STATUS_EP15_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_IN +// Description : None +#define USB_BUFF_STATUS_EP15_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP15_IN_BITS 0x40000000 +#define USB_BUFF_STATUS_EP15_IN_MSB 30 +#define USB_BUFF_STATUS_EP15_IN_LSB 30 +#define USB_BUFF_STATUS_EP15_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_OUT +// Description : None +#define USB_BUFF_STATUS_EP14_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP14_OUT_BITS 0x20000000 +#define USB_BUFF_STATUS_EP14_OUT_MSB 29 +#define USB_BUFF_STATUS_EP14_OUT_LSB 29 +#define USB_BUFF_STATUS_EP14_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_IN +// Description : None +#define USB_BUFF_STATUS_EP14_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP14_IN_BITS 0x10000000 +#define USB_BUFF_STATUS_EP14_IN_MSB 28 +#define USB_BUFF_STATUS_EP14_IN_LSB 28 +#define USB_BUFF_STATUS_EP14_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_OUT +// Description : None +#define USB_BUFF_STATUS_EP13_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP13_OUT_BITS 0x08000000 +#define USB_BUFF_STATUS_EP13_OUT_MSB 27 +#define USB_BUFF_STATUS_EP13_OUT_LSB 27 +#define USB_BUFF_STATUS_EP13_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_IN +// Description : None +#define USB_BUFF_STATUS_EP13_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP13_IN_BITS 0x04000000 +#define USB_BUFF_STATUS_EP13_IN_MSB 26 +#define USB_BUFF_STATUS_EP13_IN_LSB 26 +#define USB_BUFF_STATUS_EP13_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_OUT +// Description : None +#define USB_BUFF_STATUS_EP12_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP12_OUT_BITS 0x02000000 +#define USB_BUFF_STATUS_EP12_OUT_MSB 25 +#define USB_BUFF_STATUS_EP12_OUT_LSB 25 +#define USB_BUFF_STATUS_EP12_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_IN +// Description : None +#define USB_BUFF_STATUS_EP12_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP12_IN_BITS 0x01000000 +#define USB_BUFF_STATUS_EP12_IN_MSB 24 +#define USB_BUFF_STATUS_EP12_IN_LSB 24 +#define USB_BUFF_STATUS_EP12_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_OUT +// Description : None +#define USB_BUFF_STATUS_EP11_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP11_OUT_BITS 0x00800000 +#define USB_BUFF_STATUS_EP11_OUT_MSB 23 +#define USB_BUFF_STATUS_EP11_OUT_LSB 23 +#define USB_BUFF_STATUS_EP11_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_IN +// Description : None +#define USB_BUFF_STATUS_EP11_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP11_IN_BITS 0x00400000 +#define USB_BUFF_STATUS_EP11_IN_MSB 22 +#define USB_BUFF_STATUS_EP11_IN_LSB 22 +#define USB_BUFF_STATUS_EP11_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_OUT +// Description : None +#define USB_BUFF_STATUS_EP10_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP10_OUT_BITS 0x00200000 +#define USB_BUFF_STATUS_EP10_OUT_MSB 21 +#define USB_BUFF_STATUS_EP10_OUT_LSB 21 +#define USB_BUFF_STATUS_EP10_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_IN +// Description : None +#define USB_BUFF_STATUS_EP10_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP10_IN_BITS 0x00100000 +#define USB_BUFF_STATUS_EP10_IN_MSB 20 +#define USB_BUFF_STATUS_EP10_IN_LSB 20 +#define USB_BUFF_STATUS_EP10_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_OUT +// Description : None +#define USB_BUFF_STATUS_EP9_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP9_OUT_BITS 0x00080000 +#define USB_BUFF_STATUS_EP9_OUT_MSB 19 +#define USB_BUFF_STATUS_EP9_OUT_LSB 19 +#define USB_BUFF_STATUS_EP9_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_IN +// Description : None +#define USB_BUFF_STATUS_EP9_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP9_IN_BITS 0x00040000 +#define USB_BUFF_STATUS_EP9_IN_MSB 18 +#define USB_BUFF_STATUS_EP9_IN_LSB 18 +#define USB_BUFF_STATUS_EP9_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_OUT +// Description : None +#define USB_BUFF_STATUS_EP8_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP8_OUT_BITS 0x00020000 +#define USB_BUFF_STATUS_EP8_OUT_MSB 17 +#define USB_BUFF_STATUS_EP8_OUT_LSB 17 +#define USB_BUFF_STATUS_EP8_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_IN +// Description : None +#define USB_BUFF_STATUS_EP8_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP8_IN_BITS 0x00010000 +#define USB_BUFF_STATUS_EP8_IN_MSB 16 +#define USB_BUFF_STATUS_EP8_IN_LSB 16 +#define USB_BUFF_STATUS_EP8_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_OUT +// Description : None +#define USB_BUFF_STATUS_EP7_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP7_OUT_BITS 0x00008000 +#define USB_BUFF_STATUS_EP7_OUT_MSB 15 +#define USB_BUFF_STATUS_EP7_OUT_LSB 15 +#define USB_BUFF_STATUS_EP7_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_IN +// Description : None +#define USB_BUFF_STATUS_EP7_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP7_IN_BITS 0x00004000 +#define USB_BUFF_STATUS_EP7_IN_MSB 14 +#define USB_BUFF_STATUS_EP7_IN_LSB 14 +#define USB_BUFF_STATUS_EP7_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_OUT +// Description : None +#define USB_BUFF_STATUS_EP6_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP6_OUT_BITS 0x00002000 +#define USB_BUFF_STATUS_EP6_OUT_MSB 13 +#define USB_BUFF_STATUS_EP6_OUT_LSB 13 +#define USB_BUFF_STATUS_EP6_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_IN +// Description : None +#define USB_BUFF_STATUS_EP6_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP6_IN_BITS 0x00001000 +#define USB_BUFF_STATUS_EP6_IN_MSB 12 +#define USB_BUFF_STATUS_EP6_IN_LSB 12 +#define USB_BUFF_STATUS_EP6_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_OUT +// Description : None +#define USB_BUFF_STATUS_EP5_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP5_OUT_BITS 0x00000800 +#define USB_BUFF_STATUS_EP5_OUT_MSB 11 +#define USB_BUFF_STATUS_EP5_OUT_LSB 11 +#define USB_BUFF_STATUS_EP5_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_IN +// Description : None +#define USB_BUFF_STATUS_EP5_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP5_IN_BITS 0x00000400 +#define USB_BUFF_STATUS_EP5_IN_MSB 10 +#define USB_BUFF_STATUS_EP5_IN_LSB 10 +#define USB_BUFF_STATUS_EP5_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_OUT +// Description : None +#define USB_BUFF_STATUS_EP4_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP4_OUT_BITS 0x00000200 +#define USB_BUFF_STATUS_EP4_OUT_MSB 9 +#define USB_BUFF_STATUS_EP4_OUT_LSB 9 +#define USB_BUFF_STATUS_EP4_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_IN +// Description : None +#define USB_BUFF_STATUS_EP4_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP4_IN_BITS 0x00000100 +#define USB_BUFF_STATUS_EP4_IN_MSB 8 +#define USB_BUFF_STATUS_EP4_IN_LSB 8 +#define USB_BUFF_STATUS_EP4_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_OUT +// Description : None +#define USB_BUFF_STATUS_EP3_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP3_OUT_BITS 0x00000080 +#define USB_BUFF_STATUS_EP3_OUT_MSB 7 +#define USB_BUFF_STATUS_EP3_OUT_LSB 7 +#define USB_BUFF_STATUS_EP3_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_IN +// Description : None +#define USB_BUFF_STATUS_EP3_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP3_IN_BITS 0x00000040 +#define USB_BUFF_STATUS_EP3_IN_MSB 6 +#define USB_BUFF_STATUS_EP3_IN_LSB 6 +#define USB_BUFF_STATUS_EP3_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_OUT +// Description : None +#define USB_BUFF_STATUS_EP2_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP2_OUT_BITS 0x00000020 +#define USB_BUFF_STATUS_EP2_OUT_MSB 5 +#define USB_BUFF_STATUS_EP2_OUT_LSB 5 +#define USB_BUFF_STATUS_EP2_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_IN +// Description : None +#define USB_BUFF_STATUS_EP2_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP2_IN_BITS 0x00000010 +#define USB_BUFF_STATUS_EP2_IN_MSB 4 +#define USB_BUFF_STATUS_EP2_IN_LSB 4 +#define USB_BUFF_STATUS_EP2_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_OUT +// Description : None +#define USB_BUFF_STATUS_EP1_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP1_OUT_BITS 0x00000008 +#define USB_BUFF_STATUS_EP1_OUT_MSB 3 +#define USB_BUFF_STATUS_EP1_OUT_LSB 3 +#define USB_BUFF_STATUS_EP1_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_IN +// Description : None +#define USB_BUFF_STATUS_EP1_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP1_IN_BITS 0x00000004 +#define USB_BUFF_STATUS_EP1_IN_MSB 2 +#define USB_BUFF_STATUS_EP1_IN_LSB 2 +#define USB_BUFF_STATUS_EP1_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_OUT +// Description : None +#define USB_BUFF_STATUS_EP0_OUT_RESET 0x0 +#define USB_BUFF_STATUS_EP0_OUT_BITS 0x00000002 +#define USB_BUFF_STATUS_EP0_OUT_MSB 1 +#define USB_BUFF_STATUS_EP0_OUT_LSB 1 +#define USB_BUFF_STATUS_EP0_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_IN +// Description : None +#define USB_BUFF_STATUS_EP0_IN_RESET 0x0 +#define USB_BUFF_STATUS_EP0_IN_BITS 0x00000001 +#define USB_BUFF_STATUS_EP0_IN_MSB 0 +#define USB_BUFF_STATUS_EP0_IN_LSB 0 +#define USB_BUFF_STATUS_EP0_IN_ACCESS "RO" +// ============================================================================= +// Register : USB_BUFF_CPU_SHOULD_HANDLE +// Description : Which of the double buffers should be handled. Only valid if +// using an interrupt per buffer (i.e. not per 2 buffers). Not +// valid for host interrupt endpoint polling because they are only +// single buffered. +#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET 0x0000005c +#define USB_BUFF_CPU_SHOULD_HANDLE_BITS 0xffffffff +#define USB_BUFF_CPU_SHOULD_HANDLE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS 0x80000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB 31 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB 31 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS 0x40000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB 30 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB 30 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS 0x20000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB 29 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB 29 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS 0x10000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB 28 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB 28 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS 0x08000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB 27 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB 27 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS 0x04000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB 26 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB 26 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS 0x02000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB 25 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB 25 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS 0x01000000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB 24 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB 24 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS 0x00800000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB 23 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB 23 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS 0x00400000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB 22 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB 22 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS 0x00200000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB 21 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB 21 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS 0x00100000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB 20 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB 20 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS 0x00080000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB 19 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB 19 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS 0x00040000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB 18 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB 18 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS 0x00020000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB 17 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB 17 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS 0x00010000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB 16 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB 16 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS 0x00008000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB 15 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB 15 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS 0x00004000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB 14 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB 14 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS 0x00002000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB 13 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB 13 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS 0x00001000 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB 12 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB 12 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS 0x00000800 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB 11 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB 11 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS 0x00000400 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB 10 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB 10 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS 0x00000200 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB 9 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB 9 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS 0x00000100 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB 8 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB 8 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS 0x00000080 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB 7 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB 7 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS 0x00000040 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB 6 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB 6 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS 0x00000020 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB 5 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB 5 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS 0x00000010 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB 4 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB 4 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS 0x00000008 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB 3 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB 3 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS 0x00000004 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB 2 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB 2 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS 0x00000002 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB 1 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB 1 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN +// Description : None +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET 0x0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS 0x00000001 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB 0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB 0 +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" +// ============================================================================= +// Register : USB_EP_ABORT +// Description : Device only: Can be set to ignore the buffer control register +// for this endpoint in case you would like to revoke a buffer. A +// NAK will be sent for every access to the endpoint until this +// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set +// when it is safe to modify the buffer control register. +#define USB_EP_ABORT_OFFSET 0x00000060 +#define USB_EP_ABORT_BITS 0xffffffff +#define USB_EP_ABORT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_OUT +// Description : None +#define USB_EP_ABORT_EP15_OUT_RESET 0x0 +#define USB_EP_ABORT_EP15_OUT_BITS 0x80000000 +#define USB_EP_ABORT_EP15_OUT_MSB 31 +#define USB_EP_ABORT_EP15_OUT_LSB 31 +#define USB_EP_ABORT_EP15_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_IN +// Description : None +#define USB_EP_ABORT_EP15_IN_RESET 0x0 +#define USB_EP_ABORT_EP15_IN_BITS 0x40000000 +#define USB_EP_ABORT_EP15_IN_MSB 30 +#define USB_EP_ABORT_EP15_IN_LSB 30 +#define USB_EP_ABORT_EP15_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_OUT +// Description : None +#define USB_EP_ABORT_EP14_OUT_RESET 0x0 +#define USB_EP_ABORT_EP14_OUT_BITS 0x20000000 +#define USB_EP_ABORT_EP14_OUT_MSB 29 +#define USB_EP_ABORT_EP14_OUT_LSB 29 +#define USB_EP_ABORT_EP14_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_IN +// Description : None +#define USB_EP_ABORT_EP14_IN_RESET 0x0 +#define USB_EP_ABORT_EP14_IN_BITS 0x10000000 +#define USB_EP_ABORT_EP14_IN_MSB 28 +#define USB_EP_ABORT_EP14_IN_LSB 28 +#define USB_EP_ABORT_EP14_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_OUT +// Description : None +#define USB_EP_ABORT_EP13_OUT_RESET 0x0 +#define USB_EP_ABORT_EP13_OUT_BITS 0x08000000 +#define USB_EP_ABORT_EP13_OUT_MSB 27 +#define USB_EP_ABORT_EP13_OUT_LSB 27 +#define USB_EP_ABORT_EP13_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_IN +// Description : None +#define USB_EP_ABORT_EP13_IN_RESET 0x0 +#define USB_EP_ABORT_EP13_IN_BITS 0x04000000 +#define USB_EP_ABORT_EP13_IN_MSB 26 +#define USB_EP_ABORT_EP13_IN_LSB 26 +#define USB_EP_ABORT_EP13_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_OUT +// Description : None +#define USB_EP_ABORT_EP12_OUT_RESET 0x0 +#define USB_EP_ABORT_EP12_OUT_BITS 0x02000000 +#define USB_EP_ABORT_EP12_OUT_MSB 25 +#define USB_EP_ABORT_EP12_OUT_LSB 25 +#define USB_EP_ABORT_EP12_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_IN +// Description : None +#define USB_EP_ABORT_EP12_IN_RESET 0x0 +#define USB_EP_ABORT_EP12_IN_BITS 0x01000000 +#define USB_EP_ABORT_EP12_IN_MSB 24 +#define USB_EP_ABORT_EP12_IN_LSB 24 +#define USB_EP_ABORT_EP12_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_OUT +// Description : None +#define USB_EP_ABORT_EP11_OUT_RESET 0x0 +#define USB_EP_ABORT_EP11_OUT_BITS 0x00800000 +#define USB_EP_ABORT_EP11_OUT_MSB 23 +#define USB_EP_ABORT_EP11_OUT_LSB 23 +#define USB_EP_ABORT_EP11_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_IN +// Description : None +#define USB_EP_ABORT_EP11_IN_RESET 0x0 +#define USB_EP_ABORT_EP11_IN_BITS 0x00400000 +#define USB_EP_ABORT_EP11_IN_MSB 22 +#define USB_EP_ABORT_EP11_IN_LSB 22 +#define USB_EP_ABORT_EP11_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_OUT +// Description : None +#define USB_EP_ABORT_EP10_OUT_RESET 0x0 +#define USB_EP_ABORT_EP10_OUT_BITS 0x00200000 +#define USB_EP_ABORT_EP10_OUT_MSB 21 +#define USB_EP_ABORT_EP10_OUT_LSB 21 +#define USB_EP_ABORT_EP10_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_IN +// Description : None +#define USB_EP_ABORT_EP10_IN_RESET 0x0 +#define USB_EP_ABORT_EP10_IN_BITS 0x00100000 +#define USB_EP_ABORT_EP10_IN_MSB 20 +#define USB_EP_ABORT_EP10_IN_LSB 20 +#define USB_EP_ABORT_EP10_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_OUT +// Description : None +#define USB_EP_ABORT_EP9_OUT_RESET 0x0 +#define USB_EP_ABORT_EP9_OUT_BITS 0x00080000 +#define USB_EP_ABORT_EP9_OUT_MSB 19 +#define USB_EP_ABORT_EP9_OUT_LSB 19 +#define USB_EP_ABORT_EP9_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_IN +// Description : None +#define USB_EP_ABORT_EP9_IN_RESET 0x0 +#define USB_EP_ABORT_EP9_IN_BITS 0x00040000 +#define USB_EP_ABORT_EP9_IN_MSB 18 +#define USB_EP_ABORT_EP9_IN_LSB 18 +#define USB_EP_ABORT_EP9_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_OUT +// Description : None +#define USB_EP_ABORT_EP8_OUT_RESET 0x0 +#define USB_EP_ABORT_EP8_OUT_BITS 0x00020000 +#define USB_EP_ABORT_EP8_OUT_MSB 17 +#define USB_EP_ABORT_EP8_OUT_LSB 17 +#define USB_EP_ABORT_EP8_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_IN +// Description : None +#define USB_EP_ABORT_EP8_IN_RESET 0x0 +#define USB_EP_ABORT_EP8_IN_BITS 0x00010000 +#define USB_EP_ABORT_EP8_IN_MSB 16 +#define USB_EP_ABORT_EP8_IN_LSB 16 +#define USB_EP_ABORT_EP8_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_OUT +// Description : None +#define USB_EP_ABORT_EP7_OUT_RESET 0x0 +#define USB_EP_ABORT_EP7_OUT_BITS 0x00008000 +#define USB_EP_ABORT_EP7_OUT_MSB 15 +#define USB_EP_ABORT_EP7_OUT_LSB 15 +#define USB_EP_ABORT_EP7_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_IN +// Description : None +#define USB_EP_ABORT_EP7_IN_RESET 0x0 +#define USB_EP_ABORT_EP7_IN_BITS 0x00004000 +#define USB_EP_ABORT_EP7_IN_MSB 14 +#define USB_EP_ABORT_EP7_IN_LSB 14 +#define USB_EP_ABORT_EP7_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_OUT +// Description : None +#define USB_EP_ABORT_EP6_OUT_RESET 0x0 +#define USB_EP_ABORT_EP6_OUT_BITS 0x00002000 +#define USB_EP_ABORT_EP6_OUT_MSB 13 +#define USB_EP_ABORT_EP6_OUT_LSB 13 +#define USB_EP_ABORT_EP6_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_IN +// Description : None +#define USB_EP_ABORT_EP6_IN_RESET 0x0 +#define USB_EP_ABORT_EP6_IN_BITS 0x00001000 +#define USB_EP_ABORT_EP6_IN_MSB 12 +#define USB_EP_ABORT_EP6_IN_LSB 12 +#define USB_EP_ABORT_EP6_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_OUT +// Description : None +#define USB_EP_ABORT_EP5_OUT_RESET 0x0 +#define USB_EP_ABORT_EP5_OUT_BITS 0x00000800 +#define USB_EP_ABORT_EP5_OUT_MSB 11 +#define USB_EP_ABORT_EP5_OUT_LSB 11 +#define USB_EP_ABORT_EP5_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_IN +// Description : None +#define USB_EP_ABORT_EP5_IN_RESET 0x0 +#define USB_EP_ABORT_EP5_IN_BITS 0x00000400 +#define USB_EP_ABORT_EP5_IN_MSB 10 +#define USB_EP_ABORT_EP5_IN_LSB 10 +#define USB_EP_ABORT_EP5_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_OUT +// Description : None +#define USB_EP_ABORT_EP4_OUT_RESET 0x0 +#define USB_EP_ABORT_EP4_OUT_BITS 0x00000200 +#define USB_EP_ABORT_EP4_OUT_MSB 9 +#define USB_EP_ABORT_EP4_OUT_LSB 9 +#define USB_EP_ABORT_EP4_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_IN +// Description : None +#define USB_EP_ABORT_EP4_IN_RESET 0x0 +#define USB_EP_ABORT_EP4_IN_BITS 0x00000100 +#define USB_EP_ABORT_EP4_IN_MSB 8 +#define USB_EP_ABORT_EP4_IN_LSB 8 +#define USB_EP_ABORT_EP4_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_OUT +// Description : None +#define USB_EP_ABORT_EP3_OUT_RESET 0x0 +#define USB_EP_ABORT_EP3_OUT_BITS 0x00000080 +#define USB_EP_ABORT_EP3_OUT_MSB 7 +#define USB_EP_ABORT_EP3_OUT_LSB 7 +#define USB_EP_ABORT_EP3_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_IN +// Description : None +#define USB_EP_ABORT_EP3_IN_RESET 0x0 +#define USB_EP_ABORT_EP3_IN_BITS 0x00000040 +#define USB_EP_ABORT_EP3_IN_MSB 6 +#define USB_EP_ABORT_EP3_IN_LSB 6 +#define USB_EP_ABORT_EP3_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_OUT +// Description : None +#define USB_EP_ABORT_EP2_OUT_RESET 0x0 +#define USB_EP_ABORT_EP2_OUT_BITS 0x00000020 +#define USB_EP_ABORT_EP2_OUT_MSB 5 +#define USB_EP_ABORT_EP2_OUT_LSB 5 +#define USB_EP_ABORT_EP2_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_IN +// Description : None +#define USB_EP_ABORT_EP2_IN_RESET 0x0 +#define USB_EP_ABORT_EP2_IN_BITS 0x00000010 +#define USB_EP_ABORT_EP2_IN_MSB 4 +#define USB_EP_ABORT_EP2_IN_LSB 4 +#define USB_EP_ABORT_EP2_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_OUT +// Description : None +#define USB_EP_ABORT_EP1_OUT_RESET 0x0 +#define USB_EP_ABORT_EP1_OUT_BITS 0x00000008 +#define USB_EP_ABORT_EP1_OUT_MSB 3 +#define USB_EP_ABORT_EP1_OUT_LSB 3 +#define USB_EP_ABORT_EP1_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_IN +// Description : None +#define USB_EP_ABORT_EP1_IN_RESET 0x0 +#define USB_EP_ABORT_EP1_IN_BITS 0x00000004 +#define USB_EP_ABORT_EP1_IN_MSB 2 +#define USB_EP_ABORT_EP1_IN_LSB 2 +#define USB_EP_ABORT_EP1_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_OUT +// Description : None +#define USB_EP_ABORT_EP0_OUT_RESET 0x0 +#define USB_EP_ABORT_EP0_OUT_BITS 0x00000002 +#define USB_EP_ABORT_EP0_OUT_MSB 1 +#define USB_EP_ABORT_EP0_OUT_LSB 1 +#define USB_EP_ABORT_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_IN +// Description : None +#define USB_EP_ABORT_EP0_IN_RESET 0x0 +#define USB_EP_ABORT_EP0_IN_BITS 0x00000001 +#define USB_EP_ABORT_EP0_IN_MSB 0 +#define USB_EP_ABORT_EP0_IN_LSB 0 +#define USB_EP_ABORT_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_ABORT_DONE +// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an +// endpoint is idle so the programmer knows it is safe to modify +// the buffer control register. +#define USB_EP_ABORT_DONE_OFFSET 0x00000064 +#define USB_EP_ABORT_DONE_BITS 0xffffffff +#define USB_EP_ABORT_DONE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP15_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP15_OUT_BITS 0x80000000 +#define USB_EP_ABORT_DONE_EP15_OUT_MSB 31 +#define USB_EP_ABORT_DONE_EP15_OUT_LSB 31 +#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_IN +// Description : None +#define USB_EP_ABORT_DONE_EP15_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP15_IN_BITS 0x40000000 +#define USB_EP_ABORT_DONE_EP15_IN_MSB 30 +#define USB_EP_ABORT_DONE_EP15_IN_LSB 30 +#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP14_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP14_OUT_BITS 0x20000000 +#define USB_EP_ABORT_DONE_EP14_OUT_MSB 29 +#define USB_EP_ABORT_DONE_EP14_OUT_LSB 29 +#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_IN +// Description : None +#define USB_EP_ABORT_DONE_EP14_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP14_IN_BITS 0x10000000 +#define USB_EP_ABORT_DONE_EP14_IN_MSB 28 +#define USB_EP_ABORT_DONE_EP14_IN_LSB 28 +#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP13_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP13_OUT_BITS 0x08000000 +#define USB_EP_ABORT_DONE_EP13_OUT_MSB 27 +#define USB_EP_ABORT_DONE_EP13_OUT_LSB 27 +#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_IN +// Description : None +#define USB_EP_ABORT_DONE_EP13_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP13_IN_BITS 0x04000000 +#define USB_EP_ABORT_DONE_EP13_IN_MSB 26 +#define USB_EP_ABORT_DONE_EP13_IN_LSB 26 +#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP12_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP12_OUT_BITS 0x02000000 +#define USB_EP_ABORT_DONE_EP12_OUT_MSB 25 +#define USB_EP_ABORT_DONE_EP12_OUT_LSB 25 +#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_IN +// Description : None +#define USB_EP_ABORT_DONE_EP12_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP12_IN_BITS 0x01000000 +#define USB_EP_ABORT_DONE_EP12_IN_MSB 24 +#define USB_EP_ABORT_DONE_EP12_IN_LSB 24 +#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP11_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP11_OUT_BITS 0x00800000 +#define USB_EP_ABORT_DONE_EP11_OUT_MSB 23 +#define USB_EP_ABORT_DONE_EP11_OUT_LSB 23 +#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_IN +// Description : None +#define USB_EP_ABORT_DONE_EP11_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP11_IN_BITS 0x00400000 +#define USB_EP_ABORT_DONE_EP11_IN_MSB 22 +#define USB_EP_ABORT_DONE_EP11_IN_LSB 22 +#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP10_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP10_OUT_BITS 0x00200000 +#define USB_EP_ABORT_DONE_EP10_OUT_MSB 21 +#define USB_EP_ABORT_DONE_EP10_OUT_LSB 21 +#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_IN +// Description : None +#define USB_EP_ABORT_DONE_EP10_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP10_IN_BITS 0x00100000 +#define USB_EP_ABORT_DONE_EP10_IN_MSB 20 +#define USB_EP_ABORT_DONE_EP10_IN_LSB 20 +#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP9_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP9_OUT_BITS 0x00080000 +#define USB_EP_ABORT_DONE_EP9_OUT_MSB 19 +#define USB_EP_ABORT_DONE_EP9_OUT_LSB 19 +#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_IN +// Description : None +#define USB_EP_ABORT_DONE_EP9_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP9_IN_BITS 0x00040000 +#define USB_EP_ABORT_DONE_EP9_IN_MSB 18 +#define USB_EP_ABORT_DONE_EP9_IN_LSB 18 +#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP8_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP8_OUT_BITS 0x00020000 +#define USB_EP_ABORT_DONE_EP8_OUT_MSB 17 +#define USB_EP_ABORT_DONE_EP8_OUT_LSB 17 +#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_IN +// Description : None +#define USB_EP_ABORT_DONE_EP8_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP8_IN_BITS 0x00010000 +#define USB_EP_ABORT_DONE_EP8_IN_MSB 16 +#define USB_EP_ABORT_DONE_EP8_IN_LSB 16 +#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP7_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP7_OUT_BITS 0x00008000 +#define USB_EP_ABORT_DONE_EP7_OUT_MSB 15 +#define USB_EP_ABORT_DONE_EP7_OUT_LSB 15 +#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_IN +// Description : None +#define USB_EP_ABORT_DONE_EP7_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP7_IN_BITS 0x00004000 +#define USB_EP_ABORT_DONE_EP7_IN_MSB 14 +#define USB_EP_ABORT_DONE_EP7_IN_LSB 14 +#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP6_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP6_OUT_BITS 0x00002000 +#define USB_EP_ABORT_DONE_EP6_OUT_MSB 13 +#define USB_EP_ABORT_DONE_EP6_OUT_LSB 13 +#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_IN +// Description : None +#define USB_EP_ABORT_DONE_EP6_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP6_IN_BITS 0x00001000 +#define USB_EP_ABORT_DONE_EP6_IN_MSB 12 +#define USB_EP_ABORT_DONE_EP6_IN_LSB 12 +#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP5_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP5_OUT_BITS 0x00000800 +#define USB_EP_ABORT_DONE_EP5_OUT_MSB 11 +#define USB_EP_ABORT_DONE_EP5_OUT_LSB 11 +#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_IN +// Description : None +#define USB_EP_ABORT_DONE_EP5_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP5_IN_BITS 0x00000400 +#define USB_EP_ABORT_DONE_EP5_IN_MSB 10 +#define USB_EP_ABORT_DONE_EP5_IN_LSB 10 +#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP4_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP4_OUT_BITS 0x00000200 +#define USB_EP_ABORT_DONE_EP4_OUT_MSB 9 +#define USB_EP_ABORT_DONE_EP4_OUT_LSB 9 +#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_IN +// Description : None +#define USB_EP_ABORT_DONE_EP4_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP4_IN_BITS 0x00000100 +#define USB_EP_ABORT_DONE_EP4_IN_MSB 8 +#define USB_EP_ABORT_DONE_EP4_IN_LSB 8 +#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP3_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP3_OUT_BITS 0x00000080 +#define USB_EP_ABORT_DONE_EP3_OUT_MSB 7 +#define USB_EP_ABORT_DONE_EP3_OUT_LSB 7 +#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_IN +// Description : None +#define USB_EP_ABORT_DONE_EP3_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP3_IN_BITS 0x00000040 +#define USB_EP_ABORT_DONE_EP3_IN_MSB 6 +#define USB_EP_ABORT_DONE_EP3_IN_LSB 6 +#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP2_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP2_OUT_BITS 0x00000020 +#define USB_EP_ABORT_DONE_EP2_OUT_MSB 5 +#define USB_EP_ABORT_DONE_EP2_OUT_LSB 5 +#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_IN +// Description : None +#define USB_EP_ABORT_DONE_EP2_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP2_IN_BITS 0x00000010 +#define USB_EP_ABORT_DONE_EP2_IN_MSB 4 +#define USB_EP_ABORT_DONE_EP2_IN_LSB 4 +#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP1_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP1_OUT_BITS 0x00000008 +#define USB_EP_ABORT_DONE_EP1_OUT_MSB 3 +#define USB_EP_ABORT_DONE_EP1_OUT_LSB 3 +#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_IN +// Description : None +#define USB_EP_ABORT_DONE_EP1_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP1_IN_BITS 0x00000004 +#define USB_EP_ABORT_DONE_EP1_IN_MSB 2 +#define USB_EP_ABORT_DONE_EP1_IN_LSB 2 +#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_OUT +// Description : None +#define USB_EP_ABORT_DONE_EP0_OUT_RESET 0x0 +#define USB_EP_ABORT_DONE_EP0_OUT_BITS 0x00000002 +#define USB_EP_ABORT_DONE_EP0_OUT_MSB 1 +#define USB_EP_ABORT_DONE_EP0_OUT_LSB 1 +#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_IN +// Description : None +#define USB_EP_ABORT_DONE_EP0_IN_RESET 0x0 +#define USB_EP_ABORT_DONE_EP0_IN_BITS 0x00000001 +#define USB_EP_ABORT_DONE_EP0_IN_MSB 0 +#define USB_EP_ABORT_DONE_EP0_IN_LSB 0 +#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_EP_STALL_ARM +// Description : Device: this bit must be set in conjunction with the `STALL` +// bit in the buffer control register to send a STALL on EP0. The +// device controller clears these bits when a SETUP packet is +// received because the USB spec requires that a STALL condition +// is cleared when a SETUP packet is received. +#define USB_EP_STALL_ARM_OFFSET 0x00000068 +#define USB_EP_STALL_ARM_BITS 0x00000003 +#define USB_EP_STALL_ARM_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_OUT +// Description : None +#define USB_EP_STALL_ARM_EP0_OUT_RESET 0x0 +#define USB_EP_STALL_ARM_EP0_OUT_BITS 0x00000002 +#define USB_EP_STALL_ARM_EP0_OUT_MSB 1 +#define USB_EP_STALL_ARM_EP0_OUT_LSB 1 +#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_IN +// Description : None +#define USB_EP_STALL_ARM_EP0_IN_RESET 0x0 +#define USB_EP_STALL_ARM_EP0_IN_BITS 0x00000001 +#define USB_EP_STALL_ARM_EP0_IN_MSB 0 +#define USB_EP_STALL_ARM_EP0_IN_LSB 0 +#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_NAK_POLL +// Description : Used by the host controller. Sets the wait time in microseconds +// before trying again if the device replies with a NAK. +#define USB_NAK_POLL_OFFSET 0x0000006c +#define USB_NAK_POLL_BITS 0x03ff03ff +#define USB_NAK_POLL_RESET 0x00100010 +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_FS +// Description : NAK polling interval for a full speed device +#define USB_NAK_POLL_DELAY_FS_RESET 0x010 +#define USB_NAK_POLL_DELAY_FS_BITS 0x03ff0000 +#define USB_NAK_POLL_DELAY_FS_MSB 25 +#define USB_NAK_POLL_DELAY_FS_LSB 16 +#define USB_NAK_POLL_DELAY_FS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_LS +// Description : NAK polling interval for a low speed device +#define USB_NAK_POLL_DELAY_LS_RESET 0x010 +#define USB_NAK_POLL_DELAY_LS_BITS 0x000003ff +#define USB_NAK_POLL_DELAY_LS_MSB 9 +#define USB_NAK_POLL_DELAY_LS_LSB 0 +#define USB_NAK_POLL_DELAY_LS_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_STATUS_STALL_NAK +// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` +// bits are set. For EP0 this comes from `SIE_CTRL`. For all other +// endpoints it comes from the endpoint control register. +#define USB_EP_STATUS_STALL_NAK_OFFSET 0x00000070 +#define USB_EP_STATUS_STALL_NAK_BITS 0xffffffff +#define USB_EP_STATUS_STALL_NAK_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS 0x80000000 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB 31 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB 31 +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS 0x40000000 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB 30 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB 30 +#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS 0x20000000 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB 29 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB 29 +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS 0x10000000 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB 28 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB 28 +#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS 0x08000000 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB 27 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB 27 +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS 0x04000000 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB 26 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB 26 +#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS 0x02000000 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB 25 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB 25 +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS 0x01000000 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB 24 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB 24 +#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS 0x00800000 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB 23 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB 23 +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS 0x00400000 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB 22 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB 22 +#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS 0x00200000 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB 21 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB 21 +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS 0x00100000 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB 20 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB 20 +#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS 0x00080000 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB 19 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB 19 +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS 0x00040000 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB 18 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB 18 +#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS 0x00020000 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB 17 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB 17 +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS 0x00010000 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB 16 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB 16 +#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS 0x00008000 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB 15 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB 15 +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS 0x00004000 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB 14 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB 14 +#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS 0x00002000 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB 13 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB 13 +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS 0x00001000 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB 12 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB 12 +#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS 0x00000800 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB 11 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB 11 +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS 0x00000400 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB 10 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB 10 +#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS 0x00000200 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB 9 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB 9 +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS 0x00000100 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB 8 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB 8 +#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS 0x00000080 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB 7 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB 7 +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS 0x00000040 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB 6 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB 6 +#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS 0x00000020 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB 5 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB 5 +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS 0x00000010 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB 4 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB 4 +#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS 0x00000008 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB 3 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB 3 +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS 0x00000004 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB 2 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB 2 +#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS 0x00000002 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB 1 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB 1 +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_IN +// Description : None +#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET 0x0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS 0x00000001 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB 0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB 0 +#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_USB_MUXING +// Description : Where to connect the USB controller. Should be to_phy by +// default. +#define USB_USB_MUXING_OFFSET 0x00000074 +#define USB_USB_MUXING_BITS 0x0000000f +#define USB_USB_MUXING_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_SOFTCON +// Description : None +#define USB_USB_MUXING_SOFTCON_RESET 0x0 +#define USB_USB_MUXING_SOFTCON_BITS 0x00000008 +#define USB_USB_MUXING_SOFTCON_MSB 3 +#define USB_USB_MUXING_SOFTCON_LSB 3 +#define USB_USB_MUXING_SOFTCON_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_DIGITAL_PAD +// Description : None +#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET 0x0 +#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS 0x00000004 +#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB 2 +#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB 2 +#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_EXTPHY +// Description : None +#define USB_USB_MUXING_TO_EXTPHY_RESET 0x0 +#define USB_USB_MUXING_TO_EXTPHY_BITS 0x00000002 +#define USB_USB_MUXING_TO_EXTPHY_MSB 1 +#define USB_USB_MUXING_TO_EXTPHY_LSB 1 +#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_PHY +// Description : None +#define USB_USB_MUXING_TO_PHY_RESET 0x0 +#define USB_USB_MUXING_TO_PHY_BITS 0x00000001 +#define USB_USB_MUXING_TO_PHY_MSB 0 +#define USB_USB_MUXING_TO_PHY_LSB 0 +#define USB_USB_MUXING_TO_PHY_ACCESS "RW" +// ============================================================================= +// Register : USB_USB_PWR +// Description : Overrides for the power signals in the event that the VBUS +// signals are not hooked up to GPIO. Set the value of the +// override and then the override enable to switch over to the +// override value. +#define USB_USB_PWR_OFFSET 0x00000078 +#define USB_USB_PWR_BITS 0x0000003f +#define USB_USB_PWR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT_EN +// Description : None +#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET 0x0 +#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS 0x00000020 +#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB 5 +#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB 5 +#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT +// Description : None +#define USB_USB_PWR_OVERCURR_DETECT_RESET 0x0 +#define USB_USB_PWR_OVERCURR_DETECT_BITS 0x00000010 +#define USB_USB_PWR_OVERCURR_DETECT_MSB 4 +#define USB_USB_PWR_OVERCURR_DETECT_LSB 4 +#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN +// Description : None +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET 0x0 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS 0x00000008 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB 3 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB 3 +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT +// Description : None +#define USB_USB_PWR_VBUS_DETECT_RESET 0x0 +#define USB_USB_PWR_VBUS_DETECT_BITS 0x00000004 +#define USB_USB_PWR_VBUS_DETECT_MSB 2 +#define USB_USB_PWR_VBUS_DETECT_LSB 2 +#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN +// Description : None +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS 0x00000002 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB 1 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB 1 +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN +// Description : None +#define USB_USB_PWR_VBUS_EN_RESET 0x0 +#define USB_USB_PWR_VBUS_EN_BITS 0x00000001 +#define USB_USB_PWR_VBUS_EN_MSB 0 +#define USB_USB_PWR_VBUS_EN_LSB 0 +#define USB_USB_PWR_VBUS_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT +// Description : This register allows for direct control of the USB phy. Use in +// conjunction with usbphy_direct_override register to enable each +// override bit. +#define USB_USBPHY_DIRECT_OFFSET 0x0000007c +#define USB_USBPHY_DIRECT_BITS 0x007fff77 +#define USB_USBPHY_DIRECT_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVV +// Description : DM over voltage +#define USB_USBPHY_DIRECT_DM_OVV_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_OVV_BITS 0x00400000 +#define USB_USBPHY_DIRECT_DM_OVV_MSB 22 +#define USB_USBPHY_DIRECT_DM_OVV_LSB 22 +#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVV +// Description : DP over voltage +#define USB_USBPHY_DIRECT_DP_OVV_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_OVV_BITS 0x00200000 +#define USB_USBPHY_DIRECT_DP_OVV_MSB 21 +#define USB_USBPHY_DIRECT_DP_OVV_LSB 21 +#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVCN +// Description : DM overcurrent +#define USB_USBPHY_DIRECT_DM_OVCN_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_OVCN_BITS 0x00100000 +#define USB_USBPHY_DIRECT_DM_OVCN_MSB 20 +#define USB_USBPHY_DIRECT_DM_OVCN_LSB 20 +#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVCN +// Description : DP overcurrent +#define USB_USBPHY_DIRECT_DP_OVCN_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_OVCN_BITS 0x00080000 +#define USB_USBPHY_DIRECT_DP_OVCN_MSB 19 +#define USB_USBPHY_DIRECT_DP_OVCN_LSB 19 +#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DM +// Description : DPM pin state +#define USB_USBPHY_DIRECT_RX_DM_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_DM_BITS 0x00040000 +#define USB_USBPHY_DIRECT_RX_DM_MSB 18 +#define USB_USBPHY_DIRECT_RX_DM_LSB 18 +#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DP +// Description : DPP pin state +#define USB_USBPHY_DIRECT_RX_DP_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_DP_BITS 0x00020000 +#define USB_USBPHY_DIRECT_RX_DP_MSB 17 +#define USB_USBPHY_DIRECT_RX_DP_LSB 17 +#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DD +// Description : Differential RX +#define USB_USBPHY_DIRECT_RX_DD_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_DD_BITS 0x00010000 +#define USB_USBPHY_DIRECT_RX_DD_MSB 16 +#define USB_USBPHY_DIRECT_RX_DD_LSB 16 +#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DIFFMODE +// Description : TX_DIFFMODE=0: Single ended mode +// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE +// ignored) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS 0x00008000 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB 15 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB 15 +#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_FSSLEW +// Description : TX_FSSLEW=0: Low speed slew rate +// TX_FSSLEW=1: Full speed slew rate +#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS 0x00004000 +#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB 14 +#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB 14 +#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_PD +// Description : TX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_TX_PD_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_PD_BITS 0x00002000 +#define USB_USBPHY_DIRECT_TX_PD_MSB 13 +#define USB_USBPHY_DIRECT_TX_PD_LSB 13 +#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_PD +// Description : RX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_RX_PD_RESET 0x0 +#define USB_USBPHY_DIRECT_RX_PD_BITS 0x00001000 +#define USB_USBPHY_DIRECT_RX_PD_MSB 12 +#define USB_USBPHY_DIRECT_RX_PD_LSB 12 +#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM +// Description : Output data. TX_DIFFMODE=1, Ignored +// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. +// DPM=TX_DM +#define USB_USBPHY_DIRECT_TX_DM_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DM_BITS 0x00000800 +#define USB_USBPHY_DIRECT_TX_DM_MSB 11 +#define USB_USBPHY_DIRECT_TX_DM_LSB 11 +#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP +// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. +// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP +// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. +// DPP=TX_DP +#define USB_USBPHY_DIRECT_TX_DP_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DP_BITS 0x00000400 +#define USB_USBPHY_DIRECT_TX_DP_MSB 10 +#define USB_USBPHY_DIRECT_TX_DP_LSB 10 +#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM_OE +// Description : Output enable. If TX_DIFFMODE=1, Ignored. +// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - +// DPM driving +#define USB_USBPHY_DIRECT_TX_DM_OE_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DM_OE_BITS 0x00000200 +#define USB_USBPHY_DIRECT_TX_DM_OE_MSB 9 +#define USB_USBPHY_DIRECT_TX_DM_OE_LSB 9 +#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP_OE +// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - +// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving +// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - +// DPP driving +#define USB_USBPHY_DIRECT_TX_DP_OE_RESET 0x0 +#define USB_USBPHY_DIRECT_TX_DP_OE_BITS 0x00000100 +#define USB_USBPHY_DIRECT_TX_DP_OE_MSB 8 +#define USB_USBPHY_DIRECT_TX_DP_OE_LSB 8 +#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN +// Description : DM pull down enable +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS 0x00000040 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB 6 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB 6 +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN +// Description : DM pull up enable +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS 0x00000020 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB 5 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB 5 +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL +// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET 0x0 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS 0x00000010 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB 4 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB 4 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN +// Description : DP pull down enable +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS 0x00000004 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB 2 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB 2 +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN +// Description : DP pull up enable +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS 0x00000002 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB 1 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB 1 +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL +// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET 0x0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS 0x00000001 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB 0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB 0 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT_OVERRIDE +// Description : Override enable for each control in usbphy_direct +#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET 0x00000080 +#define USB_USBPHY_DIRECT_OVERRIDE_BITS 0x00009fff +#define USB_USBPHY_DIRECT_OVERRIDE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS 0x00008000 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB 15 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB 15 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS 0x00001000 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB 12 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB 12 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS 0x00000800 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB 11 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB 11 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS 0x00000400 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB 10 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB 10 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS 0x00000200 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB 9 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB 9 +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS 0x00000100 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB 8 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB 8 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS 0x00000080 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB 7 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB 7 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS 0x00000040 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB 6 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB 6 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS 0x00000020 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB 5 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB 5 +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS 0x00000010 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB 4 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB 4 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS 0x00000008 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB 3 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB 3 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS 0x00000004 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB 2 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB 2 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000002 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB 1 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB 1 +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN +// Description : None +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET 0x0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS 0x00000001 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB 0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB 0 +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_TRIM +// Description : Used to adjust trim values of USB phy pull down resistors. +#define USB_USBPHY_TRIM_OFFSET 0x00000084 +#define USB_USBPHY_TRIM_BITS 0x00001f1f +#define USB_USBPHY_TRIM_RESET 0x00001f1f +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DM pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET 0x1f +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS 0x00001f00 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB 12 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB 8 +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DP pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET 0x1f +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS 0x0000001f +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB 4 +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB 0 +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" +// ============================================================================= +// Register : USB_INTR +// Description : Raw Interrupts +#define USB_INTR_OFFSET 0x0000008c +#define USB_INTR_BITS 0x000fffff +#define USB_INTR_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTR_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTR_EP_STALL_NAK_RESET 0x0 +#define USB_INTR_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTR_EP_STALL_NAK_MSB 19 +#define USB_INTR_EP_STALL_NAK_LSB 19 +#define USB_INTR_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTR_ABORT_DONE_RESET 0x0 +#define USB_INTR_ABORT_DONE_BITS 0x00040000 +#define USB_INTR_ABORT_DONE_MSB 18 +#define USB_INTR_ABORT_DONE_LSB 18 +#define USB_INTR_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTR_DEV_SOF_RESET 0x0 +#define USB_INTR_DEV_SOF_BITS 0x00020000 +#define USB_INTR_DEV_SOF_MSB 17 +#define USB_INTR_DEV_SOF_LSB 17 +#define USB_INTR_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTR_SETUP_REQ_RESET 0x0 +#define USB_INTR_SETUP_REQ_BITS 0x00010000 +#define USB_INTR_SETUP_REQ_MSB 16 +#define USB_INTR_SETUP_REQ_LSB 16 +#define USB_INTR_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTR_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTR_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTR_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTR_DEV_SUSPEND_RESET 0x0 +#define USB_INTR_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTR_DEV_SUSPEND_MSB 14 +#define USB_INTR_DEV_SUSPEND_LSB 14 +#define USB_INTR_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTR_DEV_CONN_DIS_RESET 0x0 +#define USB_INTR_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTR_DEV_CONN_DIS_MSB 13 +#define USB_INTR_DEV_CONN_DIS_LSB 13 +#define USB_INTR_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTR_BUS_RESET_RESET 0x0 +#define USB_INTR_BUS_RESET_BITS 0x00001000 +#define USB_INTR_BUS_RESET_MSB 12 +#define USB_INTR_BUS_RESET_LSB 12 +#define USB_INTR_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTR_VBUS_DETECT_RESET 0x0 +#define USB_INTR_VBUS_DETECT_BITS 0x00000800 +#define USB_INTR_VBUS_DETECT_MSB 11 +#define USB_INTR_VBUS_DETECT_LSB 11 +#define USB_INTR_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTR_STALL_RESET 0x0 +#define USB_INTR_STALL_BITS 0x00000400 +#define USB_INTR_STALL_MSB 10 +#define USB_INTR_STALL_LSB 10 +#define USB_INTR_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTR_ERROR_CRC_RESET 0x0 +#define USB_INTR_ERROR_CRC_BITS 0x00000200 +#define USB_INTR_ERROR_CRC_MSB 9 +#define USB_INTR_ERROR_CRC_LSB 9 +#define USB_INTR_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTR_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTR_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTR_ERROR_BIT_STUFF_MSB 8 +#define USB_INTR_ERROR_BIT_STUFF_LSB 8 +#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTR_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTR_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTR_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTR_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTR_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTR_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTR_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTR_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTR_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTR_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTR_ERROR_DATA_SEQ_MSB 5 +#define USB_INTR_ERROR_DATA_SEQ_LSB 5 +#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTR_BUFF_STATUS_RESET 0x0 +#define USB_INTR_BUFF_STATUS_BITS 0x00000010 +#define USB_INTR_BUFF_STATUS_MSB 4 +#define USB_INTR_BUFF_STATUS_LSB 4 +#define USB_INTR_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTR_TRANS_COMPLETE_RESET 0x0 +#define USB_INTR_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTR_TRANS_COMPLETE_MSB 3 +#define USB_INTR_TRANS_COMPLETE_LSB 3 +#define USB_INTR_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTR_HOST_SOF_RESET 0x0 +#define USB_INTR_HOST_SOF_BITS 0x00000004 +#define USB_INTR_HOST_SOF_MSB 2 +#define USB_INTR_HOST_SOF_LSB 2 +#define USB_INTR_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_HOST_RESUME_RESET 0x0 +#define USB_INTR_HOST_RESUME_BITS 0x00000002 +#define USB_INTR_HOST_RESUME_MSB 1 +#define USB_INTR_HOST_RESUME_LSB 1 +#define USB_INTR_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTR_HOST_CONN_DIS_RESET 0x0 +#define USB_INTR_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTR_HOST_CONN_DIS_MSB 0 +#define USB_INTR_HOST_CONN_DIS_LSB 0 +#define USB_INTR_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +// Register : USB_INTE +// Description : Interrupt Enable +#define USB_INTE_OFFSET 0x00000090 +#define USB_INTE_BITS 0x000fffff +#define USB_INTE_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTE_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTE_EP_STALL_NAK_RESET 0x0 +#define USB_INTE_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTE_EP_STALL_NAK_MSB 19 +#define USB_INTE_EP_STALL_NAK_LSB 19 +#define USB_INTE_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTE_ABORT_DONE_RESET 0x0 +#define USB_INTE_ABORT_DONE_BITS 0x00040000 +#define USB_INTE_ABORT_DONE_MSB 18 +#define USB_INTE_ABORT_DONE_LSB 18 +#define USB_INTE_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTE_DEV_SOF_RESET 0x0 +#define USB_INTE_DEV_SOF_BITS 0x00020000 +#define USB_INTE_DEV_SOF_MSB 17 +#define USB_INTE_DEV_SOF_LSB 17 +#define USB_INTE_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTE_SETUP_REQ_RESET 0x0 +#define USB_INTE_SETUP_REQ_BITS 0x00010000 +#define USB_INTE_SETUP_REQ_MSB 16 +#define USB_INTE_SETUP_REQ_LSB 16 +#define USB_INTE_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTE_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTE_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTE_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTE_DEV_SUSPEND_RESET 0x0 +#define USB_INTE_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTE_DEV_SUSPEND_MSB 14 +#define USB_INTE_DEV_SUSPEND_LSB 14 +#define USB_INTE_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTE_DEV_CONN_DIS_RESET 0x0 +#define USB_INTE_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTE_DEV_CONN_DIS_MSB 13 +#define USB_INTE_DEV_CONN_DIS_LSB 13 +#define USB_INTE_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTE_BUS_RESET_RESET 0x0 +#define USB_INTE_BUS_RESET_BITS 0x00001000 +#define USB_INTE_BUS_RESET_MSB 12 +#define USB_INTE_BUS_RESET_LSB 12 +#define USB_INTE_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTE_VBUS_DETECT_RESET 0x0 +#define USB_INTE_VBUS_DETECT_BITS 0x00000800 +#define USB_INTE_VBUS_DETECT_MSB 11 +#define USB_INTE_VBUS_DETECT_LSB 11 +#define USB_INTE_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTE_STALL_RESET 0x0 +#define USB_INTE_STALL_BITS 0x00000400 +#define USB_INTE_STALL_MSB 10 +#define USB_INTE_STALL_LSB 10 +#define USB_INTE_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTE_ERROR_CRC_RESET 0x0 +#define USB_INTE_ERROR_CRC_BITS 0x00000200 +#define USB_INTE_ERROR_CRC_MSB 9 +#define USB_INTE_ERROR_CRC_LSB 9 +#define USB_INTE_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTE_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTE_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTE_ERROR_BIT_STUFF_MSB 8 +#define USB_INTE_ERROR_BIT_STUFF_LSB 8 +#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTE_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTE_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTE_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTE_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTE_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTE_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTE_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTE_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTE_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTE_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTE_ERROR_DATA_SEQ_MSB 5 +#define USB_INTE_ERROR_DATA_SEQ_LSB 5 +#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTE_BUFF_STATUS_RESET 0x0 +#define USB_INTE_BUFF_STATUS_BITS 0x00000010 +#define USB_INTE_BUFF_STATUS_MSB 4 +#define USB_INTE_BUFF_STATUS_LSB 4 +#define USB_INTE_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTE_TRANS_COMPLETE_RESET 0x0 +#define USB_INTE_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTE_TRANS_COMPLETE_MSB 3 +#define USB_INTE_TRANS_COMPLETE_LSB 3 +#define USB_INTE_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTE_HOST_SOF_RESET 0x0 +#define USB_INTE_HOST_SOF_BITS 0x00000004 +#define USB_INTE_HOST_SOF_MSB 2 +#define USB_INTE_HOST_SOF_LSB 2 +#define USB_INTE_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_HOST_RESUME_RESET 0x0 +#define USB_INTE_HOST_RESUME_BITS 0x00000002 +#define USB_INTE_HOST_RESUME_MSB 1 +#define USB_INTE_HOST_RESUME_LSB 1 +#define USB_INTE_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTE_HOST_CONN_DIS_RESET 0x0 +#define USB_INTE_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTE_HOST_CONN_DIS_MSB 0 +#define USB_INTE_HOST_CONN_DIS_LSB 0 +#define USB_INTE_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTF +// Description : Interrupt Force +#define USB_INTF_OFFSET 0x00000094 +#define USB_INTF_BITS 0x000fffff +#define USB_INTF_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTF_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTF_EP_STALL_NAK_RESET 0x0 +#define USB_INTF_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTF_EP_STALL_NAK_MSB 19 +#define USB_INTF_EP_STALL_NAK_LSB 19 +#define USB_INTF_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTF_ABORT_DONE_RESET 0x0 +#define USB_INTF_ABORT_DONE_BITS 0x00040000 +#define USB_INTF_ABORT_DONE_MSB 18 +#define USB_INTF_ABORT_DONE_LSB 18 +#define USB_INTF_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTF_DEV_SOF_RESET 0x0 +#define USB_INTF_DEV_SOF_BITS 0x00020000 +#define USB_INTF_DEV_SOF_MSB 17 +#define USB_INTF_DEV_SOF_LSB 17 +#define USB_INTF_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTF_SETUP_REQ_RESET 0x0 +#define USB_INTF_SETUP_REQ_BITS 0x00010000 +#define USB_INTF_SETUP_REQ_MSB 16 +#define USB_INTF_SETUP_REQ_LSB 16 +#define USB_INTF_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTF_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTF_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTF_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTF_DEV_SUSPEND_RESET 0x0 +#define USB_INTF_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTF_DEV_SUSPEND_MSB 14 +#define USB_INTF_DEV_SUSPEND_LSB 14 +#define USB_INTF_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTF_DEV_CONN_DIS_RESET 0x0 +#define USB_INTF_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTF_DEV_CONN_DIS_MSB 13 +#define USB_INTF_DEV_CONN_DIS_LSB 13 +#define USB_INTF_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTF_BUS_RESET_RESET 0x0 +#define USB_INTF_BUS_RESET_BITS 0x00001000 +#define USB_INTF_BUS_RESET_MSB 12 +#define USB_INTF_BUS_RESET_LSB 12 +#define USB_INTF_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTF_VBUS_DETECT_RESET 0x0 +#define USB_INTF_VBUS_DETECT_BITS 0x00000800 +#define USB_INTF_VBUS_DETECT_MSB 11 +#define USB_INTF_VBUS_DETECT_LSB 11 +#define USB_INTF_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTF_STALL_RESET 0x0 +#define USB_INTF_STALL_BITS 0x00000400 +#define USB_INTF_STALL_MSB 10 +#define USB_INTF_STALL_LSB 10 +#define USB_INTF_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTF_ERROR_CRC_RESET 0x0 +#define USB_INTF_ERROR_CRC_BITS 0x00000200 +#define USB_INTF_ERROR_CRC_MSB 9 +#define USB_INTF_ERROR_CRC_LSB 9 +#define USB_INTF_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTF_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTF_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTF_ERROR_BIT_STUFF_MSB 8 +#define USB_INTF_ERROR_BIT_STUFF_LSB 8 +#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTF_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTF_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTF_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTF_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTF_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTF_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTF_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTF_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTF_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTF_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTF_ERROR_DATA_SEQ_MSB 5 +#define USB_INTF_ERROR_DATA_SEQ_LSB 5 +#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTF_BUFF_STATUS_RESET 0x0 +#define USB_INTF_BUFF_STATUS_BITS 0x00000010 +#define USB_INTF_BUFF_STATUS_MSB 4 +#define USB_INTF_BUFF_STATUS_LSB 4 +#define USB_INTF_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTF_TRANS_COMPLETE_RESET 0x0 +#define USB_INTF_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTF_TRANS_COMPLETE_MSB 3 +#define USB_INTF_TRANS_COMPLETE_LSB 3 +#define USB_INTF_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTF_HOST_SOF_RESET 0x0 +#define USB_INTF_HOST_SOF_BITS 0x00000004 +#define USB_INTF_HOST_SOF_MSB 2 +#define USB_INTF_HOST_SOF_LSB 2 +#define USB_INTF_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_HOST_RESUME_RESET 0x0 +#define USB_INTF_HOST_RESUME_BITS 0x00000002 +#define USB_INTF_HOST_RESUME_MSB 1 +#define USB_INTF_HOST_RESUME_LSB 1 +#define USB_INTF_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTF_HOST_CONN_DIS_RESET 0x0 +#define USB_INTF_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTF_HOST_CONN_DIS_MSB 0 +#define USB_INTF_HOST_CONN_DIS_LSB 0 +#define USB_INTF_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTS +// Description : Interrupt status after masking & forcing +#define USB_INTS_OFFSET 0x00000098 +#define USB_INTS_BITS 0x000fffff +#define USB_INTS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : USB_INTS_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTS_EP_STALL_NAK_RESET 0x0 +#define USB_INTS_EP_STALL_NAK_BITS 0x00080000 +#define USB_INTS_EP_STALL_NAK_MSB 19 +#define USB_INTS_EP_STALL_NAK_LSB 19 +#define USB_INTS_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTS_ABORT_DONE_RESET 0x0 +#define USB_INTS_ABORT_DONE_BITS 0x00040000 +#define USB_INTS_ABORT_DONE_MSB 18 +#define USB_INTS_ABORT_DONE_LSB 18 +#define USB_INTS_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTS_DEV_SOF_RESET 0x0 +#define USB_INTS_DEV_SOF_BITS 0x00020000 +#define USB_INTS_DEV_SOF_MSB 17 +#define USB_INTS_DEV_SOF_LSB 17 +#define USB_INTS_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTS_SETUP_REQ_RESET 0x0 +#define USB_INTS_SETUP_REQ_BITS 0x00010000 +#define USB_INTS_SETUP_REQ_MSB 16 +#define USB_INTS_SETUP_REQ_LSB 16 +#define USB_INTS_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_DEV_RESUME_FROM_HOST_RESET 0x0 +#define USB_INTS_DEV_RESUME_FROM_HOST_BITS 0x00008000 +#define USB_INTS_DEV_RESUME_FROM_HOST_MSB 15 +#define USB_INTS_DEV_RESUME_FROM_HOST_LSB 15 +#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTS_DEV_SUSPEND_RESET 0x0 +#define USB_INTS_DEV_SUSPEND_BITS 0x00004000 +#define USB_INTS_DEV_SUSPEND_MSB 14 +#define USB_INTS_DEV_SUSPEND_LSB 14 +#define USB_INTS_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTS_DEV_CONN_DIS_RESET 0x0 +#define USB_INTS_DEV_CONN_DIS_BITS 0x00002000 +#define USB_INTS_DEV_CONN_DIS_MSB 13 +#define USB_INTS_DEV_CONN_DIS_LSB 13 +#define USB_INTS_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTS_BUS_RESET_RESET 0x0 +#define USB_INTS_BUS_RESET_BITS 0x00001000 +#define USB_INTS_BUS_RESET_MSB 12 +#define USB_INTS_BUS_RESET_LSB 12 +#define USB_INTS_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECT +#define USB_INTS_VBUS_DETECT_RESET 0x0 +#define USB_INTS_VBUS_DETECT_BITS 0x00000800 +#define USB_INTS_VBUS_DETECT_MSB 11 +#define USB_INTS_VBUS_DETECT_LSB 11 +#define USB_INTS_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTS_STALL_RESET 0x0 +#define USB_INTS_STALL_BITS 0x00000400 +#define USB_INTS_STALL_MSB 10 +#define USB_INTS_STALL_LSB 10 +#define USB_INTS_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTS_ERROR_CRC_RESET 0x0 +#define USB_INTS_ERROR_CRC_BITS 0x00000200 +#define USB_INTS_ERROR_CRC_MSB 9 +#define USB_INTS_ERROR_CRC_LSB 9 +#define USB_INTS_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTS_ERROR_BIT_STUFF_RESET 0x0 +#define USB_INTS_ERROR_BIT_STUFF_BITS 0x00000100 +#define USB_INTS_ERROR_BIT_STUFF_MSB 8 +#define USB_INTS_ERROR_BIT_STUFF_LSB 8 +#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTS_ERROR_RX_OVERFLOW_RESET 0x0 +#define USB_INTS_ERROR_RX_OVERFLOW_BITS 0x00000080 +#define USB_INTS_ERROR_RX_OVERFLOW_MSB 7 +#define USB_INTS_ERROR_RX_OVERFLOW_LSB 7 +#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTS_ERROR_RX_TIMEOUT_RESET 0x0 +#define USB_INTS_ERROR_RX_TIMEOUT_BITS 0x00000040 +#define USB_INTS_ERROR_RX_TIMEOUT_MSB 6 +#define USB_INTS_ERROR_RX_TIMEOUT_LSB 6 +#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTS_ERROR_DATA_SEQ_RESET 0x0 +#define USB_INTS_ERROR_DATA_SEQ_BITS 0x00000020 +#define USB_INTS_ERROR_DATA_SEQ_MSB 5 +#define USB_INTS_ERROR_DATA_SEQ_LSB 5 +#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTS_BUFF_STATUS_RESET 0x0 +#define USB_INTS_BUFF_STATUS_BITS 0x00000010 +#define USB_INTS_BUFF_STATUS_MSB 4 +#define USB_INTS_BUFF_STATUS_LSB 4 +#define USB_INTS_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTS_TRANS_COMPLETE_RESET 0x0 +#define USB_INTS_TRANS_COMPLETE_BITS 0x00000008 +#define USB_INTS_TRANS_COMPLETE_MSB 3 +#define USB_INTS_TRANS_COMPLETE_LSB 3 +#define USB_INTS_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTS_HOST_SOF_RESET 0x0 +#define USB_INTS_HOST_SOF_BITS 0x00000004 +#define USB_INTS_HOST_SOF_MSB 2 +#define USB_INTS_HOST_SOF_LSB 2 +#define USB_INTS_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_HOST_RESUME_RESET 0x0 +#define USB_INTS_HOST_RESUME_BITS 0x00000002 +#define USB_INTS_HOST_RESUME_MSB 1 +#define USB_INTS_HOST_RESUME_LSB 1 +#define USB_INTS_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTS_HOST_CONN_DIS_RESET 0x0 +#define USB_INTS_HOST_CONN_DIS_BITS 0x00000001 +#define USB_INTS_HOST_CONN_DIS_MSB 0 +#define USB_INTS_HOST_CONN_DIS_LSB 0 +#define USB_INTS_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_USB_DEFINED diff --git a/rp2040/hardware/regs/vreg_and_chip_reset.h b/rp2040/hardware/regs/vreg_and_chip_reset.h new file mode 100644 index 0000000..34ca1ba --- /dev/null +++ b/rp2040/hardware/regs/vreg_and_chip_reset.h @@ -0,0 +1,151 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : VREG_AND_CHIP_RESET +// Version : 1 +// Bus type : apb +// Description : control and status for on-chip voltage regulator and chip +// level reset subsystem +// ============================================================================= +#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +// ============================================================================= +// Register : VREG_AND_CHIP_RESET_VREG +// Description : Voltage regulator control and status +#define VREG_AND_CHIP_RESET_VREG_OFFSET 0x00000000 +#define VREG_AND_CHIP_RESET_VREG_BITS 0x000010f3 +#define VREG_AND_CHIP_RESET_VREG_RESET 0x000000b1 +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_ROK +// Description : regulation status +// 0=not in regulation, 1=in regulation +#define VREG_AND_CHIP_RESET_VREG_ROK_RESET 0x0 +#define VREG_AND_CHIP_RESET_VREG_ROK_BITS 0x00001000 +#define VREG_AND_CHIP_RESET_VREG_ROK_MSB 12 +#define VREG_AND_CHIP_RESET_VREG_ROK_LSB 12 +#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_VSEL +// Description : output voltage select +// 0000 to 0101 - 0.80V +// 0110 - 0.85V +// 0111 - 0.90V +// 1000 - 0.95V +// 1001 - 1.00V +// 1010 - 1.05V +// 1011 - 1.10V (default) +// 1100 - 1.15V +// 1101 - 1.20V +// 1110 - 1.25V +// 1111 - 1.30V +#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET 0xb +#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS 0x000000f0 +#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB 7 +#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET 0x0 +#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS 0x00000002 +#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB 1 +#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB 1 +#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_VREG_EN +// Description : enable +// 0=not enabled, 1=enabled +#define VREG_AND_CHIP_RESET_VREG_EN_RESET 0x1 +#define VREG_AND_CHIP_RESET_VREG_EN_BITS 0x00000001 +#define VREG_AND_CHIP_RESET_VREG_EN_MSB 0 +#define VREG_AND_CHIP_RESET_VREG_EN_LSB 0 +#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW" +// ============================================================================= +// Register : VREG_AND_CHIP_RESET_BOD +// Description : brown-out detection control +#define VREG_AND_CHIP_RESET_BOD_OFFSET 0x00000004 +#define VREG_AND_CHIP_RESET_BOD_BITS 0x000000f1 +#define VREG_AND_CHIP_RESET_BOD_RESET 0x00000091 +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_BOD_VSEL +// Description : threshold select +// 0000 - 0.473V +// 0001 - 0.516V +// 0010 - 0.559V +// 0011 - 0.602V +// 0100 - 0.645V +// 0101 - 0.688V +// 0110 - 0.731V +// 0111 - 0.774V +// 1000 - 0.817V +// 1001 - 0.860V (default) +// 1010 - 0.903V +// 1011 - 0.946V +// 1100 - 0.989V +// 1101 - 1.032V +// 1110 - 1.075V +// 1111 - 1.118V +#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET 0x9 +#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS 0x000000f0 +#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB 7 +#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB 4 +#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_BOD_EN +// Description : enable +// 0=not enabled, 1=enabled +#define VREG_AND_CHIP_RESET_BOD_EN_RESET 0x1 +#define VREG_AND_CHIP_RESET_BOD_EN_BITS 0x00000001 +#define VREG_AND_CHIP_RESET_BOD_EN_MSB 0 +#define VREG_AND_CHIP_RESET_BOD_EN_LSB 0 +#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW" +// ============================================================================= +// Register : VREG_AND_CHIP_RESET_CHIP_RESET +// Description : Chip reset control and status +#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET 0x00000008 +#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS 0x01110100 +#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG +// Description : This is set by psm_restart from the debugger. +// Its purpose is to branch bootcode to a safe mode when the +// debugger has issued a psm_restart in order to recover from a +// boot lock-up. +// In the safe mode the debugger can repair the boot code, clear +// this flag then reboot the processor. +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS 0x01000000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB 24 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB 24 +#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART +// Description : Last reset was from the debug port +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS 0x00100000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB 20 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB 20 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN +// Description : Last reset was from the RUN pin +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS 0x00010000 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB 16 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB 16 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR +// Description : Last reset was from the power-on reset or brown-out detection +// blocks +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET 0x0 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS 0x00000100 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB 8 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB 8 +#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" +// ============================================================================= +#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED diff --git a/rp2040/hardware/regs/watchdog.h b/rp2040/hardware/regs/watchdog.h new file mode 100644 index 0000000..f415c9c --- /dev/null +++ b/rp2040/hardware/regs/watchdog.h @@ -0,0 +1,226 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : WATCHDOG +// Version : 1 +// Bus type : apb +// Description : None +// ============================================================================= +#ifndef HARDWARE_REGS_WATCHDOG_DEFINED +#define HARDWARE_REGS_WATCHDOG_DEFINED +// ============================================================================= +// Register : WATCHDOG_CTRL +// Description : Watchdog control +// The rst_wdsel register determines which subsystems are reset +// when the watchdog is triggered. +// The watchdog can be triggered in software. +#define WATCHDOG_CTRL_OFFSET 0x00000000 +#define WATCHDOG_CTRL_BITS 0xc7ffffff +#define WATCHDOG_CTRL_RESET 0x07000000 +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TRIGGER +// Description : Trigger a watchdog reset +#define WATCHDOG_CTRL_TRIGGER_RESET 0x0 +#define WATCHDOG_CTRL_TRIGGER_BITS 0x80000000 +#define WATCHDOG_CTRL_TRIGGER_MSB 31 +#define WATCHDOG_CTRL_TRIGGER_LSB 31 +#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_ENABLE +// Description : When not enabled the watchdog timer is paused +#define WATCHDOG_CTRL_ENABLE_RESET 0x0 +#define WATCHDOG_CTRL_ENABLE_BITS 0x40000000 +#define WATCHDOG_CTRL_ENABLE_MSB 30 +#define WATCHDOG_CTRL_ENABLE_LSB 30 +#define WATCHDOG_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG1 +// Description : Pause the watchdog timer when processor 1 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG1_RESET 0x1 +#define WATCHDOG_CTRL_PAUSE_DBG1_BITS 0x04000000 +#define WATCHDOG_CTRL_PAUSE_DBG1_MSB 26 +#define WATCHDOG_CTRL_PAUSE_DBG1_LSB 26 +#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG0 +// Description : Pause the watchdog timer when processor 0 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG0_RESET 0x1 +#define WATCHDOG_CTRL_PAUSE_DBG0_BITS 0x02000000 +#define WATCHDOG_CTRL_PAUSE_DBG0_MSB 25 +#define WATCHDOG_CTRL_PAUSE_DBG0_LSB 25 +#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_JTAG +// Description : Pause the watchdog timer when JTAG is accessing the bus fabric +#define WATCHDOG_CTRL_PAUSE_JTAG_RESET 0x1 +#define WATCHDOG_CTRL_PAUSE_JTAG_BITS 0x01000000 +#define WATCHDOG_CTRL_PAUSE_JTAG_MSB 24 +#define WATCHDOG_CTRL_PAUSE_JTAG_LSB 24 +#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TIME +// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before +// a watchdog reset will be triggered +#define WATCHDOG_CTRL_TIME_RESET 0x000000 +#define WATCHDOG_CTRL_TIME_BITS 0x00ffffff +#define WATCHDOG_CTRL_TIME_MSB 23 +#define WATCHDOG_CTRL_TIME_LSB 0 +#define WATCHDOG_CTRL_TIME_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_LOAD +// Description : Load the watchdog timer. The maximum setting is 0xffffff which +// corresponds to 0xffffff / 2 ticks before triggering a watchdog +// reset (see errata RP2040-E1). +#define WATCHDOG_LOAD_OFFSET 0x00000004 +#define WATCHDOG_LOAD_BITS 0x00ffffff +#define WATCHDOG_LOAD_RESET 0x00000000 +#define WATCHDOG_LOAD_MSB 23 +#define WATCHDOG_LOAD_LSB 0 +#define WATCHDOG_LOAD_ACCESS "WF" +// ============================================================================= +// Register : WATCHDOG_REASON +// Description : Logs the reason for the last reset. Both bits are zero for the +// case of a hardware reset. +#define WATCHDOG_REASON_OFFSET 0x00000008 +#define WATCHDOG_REASON_BITS 0x00000003 +#define WATCHDOG_REASON_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_FORCE +// Description : None +#define WATCHDOG_REASON_FORCE_RESET 0x0 +#define WATCHDOG_REASON_FORCE_BITS 0x00000002 +#define WATCHDOG_REASON_FORCE_MSB 1 +#define WATCHDOG_REASON_FORCE_LSB 1 +#define WATCHDOG_REASON_FORCE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_TIMER +// Description : None +#define WATCHDOG_REASON_TIMER_RESET 0x0 +#define WATCHDOG_REASON_TIMER_BITS 0x00000001 +#define WATCHDOG_REASON_TIMER_MSB 0 +#define WATCHDOG_REASON_TIMER_LSB 0 +#define WATCHDOG_REASON_TIMER_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_SCRATCH0 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH0_OFFSET 0x0000000c +#define WATCHDOG_SCRATCH0_BITS 0xffffffff +#define WATCHDOG_SCRATCH0_RESET 0x00000000 +#define WATCHDOG_SCRATCH0_MSB 31 +#define WATCHDOG_SCRATCH0_LSB 0 +#define WATCHDOG_SCRATCH0_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH1 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH1_OFFSET 0x00000010 +#define WATCHDOG_SCRATCH1_BITS 0xffffffff +#define WATCHDOG_SCRATCH1_RESET 0x00000000 +#define WATCHDOG_SCRATCH1_MSB 31 +#define WATCHDOG_SCRATCH1_LSB 0 +#define WATCHDOG_SCRATCH1_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH2 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH2_OFFSET 0x00000014 +#define WATCHDOG_SCRATCH2_BITS 0xffffffff +#define WATCHDOG_SCRATCH2_RESET 0x00000000 +#define WATCHDOG_SCRATCH2_MSB 31 +#define WATCHDOG_SCRATCH2_LSB 0 +#define WATCHDOG_SCRATCH2_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH3 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH3_OFFSET 0x00000018 +#define WATCHDOG_SCRATCH3_BITS 0xffffffff +#define WATCHDOG_SCRATCH3_RESET 0x00000000 +#define WATCHDOG_SCRATCH3_MSB 31 +#define WATCHDOG_SCRATCH3_LSB 0 +#define WATCHDOG_SCRATCH3_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH4 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH4_OFFSET 0x0000001c +#define WATCHDOG_SCRATCH4_BITS 0xffffffff +#define WATCHDOG_SCRATCH4_RESET 0x00000000 +#define WATCHDOG_SCRATCH4_MSB 31 +#define WATCHDOG_SCRATCH4_LSB 0 +#define WATCHDOG_SCRATCH4_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH5 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH5_OFFSET 0x00000020 +#define WATCHDOG_SCRATCH5_BITS 0xffffffff +#define WATCHDOG_SCRATCH5_RESET 0x00000000 +#define WATCHDOG_SCRATCH5_MSB 31 +#define WATCHDOG_SCRATCH5_LSB 0 +#define WATCHDOG_SCRATCH5_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH6 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH6_OFFSET 0x00000024 +#define WATCHDOG_SCRATCH6_BITS 0xffffffff +#define WATCHDOG_SCRATCH6_RESET 0x00000000 +#define WATCHDOG_SCRATCH6_MSB 31 +#define WATCHDOG_SCRATCH6_LSB 0 +#define WATCHDOG_SCRATCH6_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH7 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH7_OFFSET 0x00000028 +#define WATCHDOG_SCRATCH7_BITS 0xffffffff +#define WATCHDOG_SCRATCH7_RESET 0x00000000 +#define WATCHDOG_SCRATCH7_MSB 31 +#define WATCHDOG_SCRATCH7_LSB 0 +#define WATCHDOG_SCRATCH7_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_TICK +// Description : Controls the tick generator +#define WATCHDOG_TICK_OFFSET 0x0000002c +#define WATCHDOG_TICK_BITS 0x000fffff +#define WATCHDOG_TICK_RESET 0x00000200 +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_COUNT +// Description : Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define WATCHDOG_TICK_COUNT_RESET "-" +#define WATCHDOG_TICK_COUNT_BITS 0x000ff800 +#define WATCHDOG_TICK_COUNT_MSB 19 +#define WATCHDOG_TICK_COUNT_LSB 11 +#define WATCHDOG_TICK_COUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_RUNNING +// Description : Is the tick generator running? +#define WATCHDOG_TICK_RUNNING_RESET "-" +#define WATCHDOG_TICK_RUNNING_BITS 0x00000400 +#define WATCHDOG_TICK_RUNNING_MSB 10 +#define WATCHDOG_TICK_RUNNING_LSB 10 +#define WATCHDOG_TICK_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_ENABLE +// Description : start / stop tick generation +#define WATCHDOG_TICK_ENABLE_RESET 0x1 +#define WATCHDOG_TICK_ENABLE_BITS 0x00000200 +#define WATCHDOG_TICK_ENABLE_MSB 9 +#define WATCHDOG_TICK_ENABLE_LSB 9 +#define WATCHDOG_TICK_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_TICK_CYCLES +// Description : Total number of clk_tick cycles before the next tick. +#define WATCHDOG_TICK_CYCLES_RESET 0x000 +#define WATCHDOG_TICK_CYCLES_BITS 0x000001ff +#define WATCHDOG_TICK_CYCLES_MSB 8 +#define WATCHDOG_TICK_CYCLES_LSB 0 +#define WATCHDOG_TICK_CYCLES_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_WATCHDOG_DEFINED diff --git a/rp2040/hardware/regs/xip.h b/rp2040/hardware/regs/xip.h new file mode 100644 index 0000000..59487e4 --- /dev/null +++ b/rp2040/hardware/regs/xip.h @@ -0,0 +1,187 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XIP +// Version : 1 +// Bus type : ahb +// Description : QSPI flash execute-in-place block +// ============================================================================= +#ifndef HARDWARE_REGS_XIP_DEFINED +#define HARDWARE_REGS_XIP_DEFINED +// ============================================================================= +// Register : XIP_CTRL +// Description : Cache control +#define XIP_CTRL_OFFSET 0x00000000 +#define XIP_CTRL_BITS 0x0000000b +#define XIP_CTRL_RESET 0x00000003 +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_POWER_DOWN +// Description : When 1, the cache memories are powered down. They retain state, +// but can not be accessed. This reduces static power dissipation. +// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache +// cannot +// be enabled when powered down. +// Cache-as-SRAM accesses will produce a bus error response when +// the cache is powered down. +#define XIP_CTRL_POWER_DOWN_RESET 0x0 +#define XIP_CTRL_POWER_DOWN_BITS 0x00000008 +#define XIP_CTRL_POWER_DOWN_MSB 3 +#define XIP_CTRL_POWER_DOWN_LSB 3 +#define XIP_CTRL_POWER_DOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_ERR_BADWRITE +// Description : When 1, writes to any alias other than 0x0 (caching, +// allocating) +// will produce a bus fault. When 0, these writes are silently +// ignored. +// In either case, writes to the 0x0 alias will deallocate on tag +// match, +// as usual. +#define XIP_CTRL_ERR_BADWRITE_RESET 0x1 +#define XIP_CTRL_ERR_BADWRITE_BITS 0x00000002 +#define XIP_CTRL_ERR_BADWRITE_MSB 1 +#define XIP_CTRL_ERR_BADWRITE_LSB 1 +#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_EN +// Description : When 1, enable the cache. When the cache is disabled, all XIP +// accesses +// will go straight to the flash, without querying the cache. When +// enabled, +// cacheable XIP accesses will query the cache, and the flash will +// not be accessed if the tag matches and the valid bit is set. +// +// If the cache is enabled, cache-as-SRAM accesses have no effect +// on the +// cache data RAM, and will produce a bus error response. +#define XIP_CTRL_EN_RESET 0x1 +#define XIP_CTRL_EN_BITS 0x00000001 +#define XIP_CTRL_EN_MSB 0 +#define XIP_CTRL_EN_LSB 0 +#define XIP_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : XIP_FLUSH +// Description : Cache Flush control +// Write 1 to flush the cache. This clears the tag memory, but +// the data memory retains its contents. (This means cache-as-SRAM +// contents is not affected by flush or reset.) +// Reading will hold the bus (stall the processor) until the flush +// completes. Alternatively STAT can be polled until completion. +#define XIP_FLUSH_OFFSET 0x00000004 +#define XIP_FLUSH_BITS 0x00000001 +#define XIP_FLUSH_RESET 0x00000000 +#define XIP_FLUSH_MSB 0 +#define XIP_FLUSH_LSB 0 +#define XIP_FLUSH_ACCESS "SC" +// ============================================================================= +// Register : XIP_STAT +// Description : Cache Status +#define XIP_STAT_OFFSET 0x00000008 +#define XIP_STAT_BITS 0x00000007 +#define XIP_STAT_RESET 0x00000002 +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_FULL +// Description : When 1, indicates the XIP streaming FIFO is completely full. +// The streaming FIFO is 2 entries deep, so the full and empty +// flag allow its level to be ascertained. +#define XIP_STAT_FIFO_FULL_RESET 0x0 +#define XIP_STAT_FIFO_FULL_BITS 0x00000004 +#define XIP_STAT_FIFO_FULL_MSB 2 +#define XIP_STAT_FIFO_FULL_LSB 2 +#define XIP_STAT_FIFO_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_EMPTY +// Description : When 1, indicates the XIP streaming FIFO is completely empty. +#define XIP_STAT_FIFO_EMPTY_RESET 0x1 +#define XIP_STAT_FIFO_EMPTY_BITS 0x00000002 +#define XIP_STAT_FIFO_EMPTY_MSB 1 +#define XIP_STAT_FIFO_EMPTY_LSB 1 +#define XIP_STAT_FIFO_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FLUSH_READY +// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise. +// The cache is flushed whenever the XIP block is reset, and also +// when requested via the FLUSH register. +#define XIP_STAT_FLUSH_READY_RESET 0x0 +#define XIP_STAT_FLUSH_READY_BITS 0x00000001 +#define XIP_STAT_FLUSH_READY_MSB 0 +#define XIP_STAT_FLUSH_READY_LSB 0 +#define XIP_STAT_FLUSH_READY_ACCESS "RO" +// ============================================================================= +// Register : XIP_CTR_HIT +// Description : Cache Hit counter +// A 32 bit saturating counter that increments upon each cache +// hit, +// i.e. when an XIP access is serviced directly from cached data. +// Write any value to clear. +#define XIP_CTR_HIT_OFFSET 0x0000000c +#define XIP_CTR_HIT_BITS 0xffffffff +#define XIP_CTR_HIT_RESET 0x00000000 +#define XIP_CTR_HIT_MSB 31 +#define XIP_CTR_HIT_LSB 0 +#define XIP_CTR_HIT_ACCESS "WC" +// ============================================================================= +// Register : XIP_CTR_ACC +// Description : Cache Access counter +// A 32 bit saturating counter that increments upon each XIP +// access, +// whether the cache is hit or not. This includes noncacheable +// accesses. +// Write any value to clear. +#define XIP_CTR_ACC_OFFSET 0x00000010 +#define XIP_CTR_ACC_BITS 0xffffffff +#define XIP_CTR_ACC_RESET 0x00000000 +#define XIP_CTR_ACC_MSB 31 +#define XIP_CTR_ACC_LSB 0 +#define XIP_CTR_ACC_ACCESS "WC" +// ============================================================================= +// Register : XIP_STREAM_ADDR +// Description : FIFO stream address +// The address of the next word to be streamed from flash to the +// streaming FIFO. +// Increments automatically after each flash access. +// Write the initial access address here before starting a +// streaming read. +#define XIP_STREAM_ADDR_OFFSET 0x00000014 +#define XIP_STREAM_ADDR_BITS 0xfffffffc +#define XIP_STREAM_ADDR_RESET 0x00000000 +#define XIP_STREAM_ADDR_MSB 31 +#define XIP_STREAM_ADDR_LSB 2 +#define XIP_STREAM_ADDR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_CTR +// Description : FIFO stream control +// Write a nonzero value to start a streaming read. This will then +// progress in the background, using flash idle cycles to transfer +// a linear data block from flash to the streaming FIFO. +// Decrements automatically (1 at a time) as the stream +// progresses, and halts on reaching 0. +// Write 0 to halt an in-progress stream, and discard any +// in-flight +// read, so that a new stream can immediately be started (after +// draining the FIFO and reinitialising STREAM_ADDR) +#define XIP_STREAM_CTR_OFFSET 0x00000018 +#define XIP_STREAM_CTR_BITS 0x003fffff +#define XIP_STREAM_CTR_RESET 0x00000000 +#define XIP_STREAM_CTR_MSB 21 +#define XIP_STREAM_CTR_LSB 0 +#define XIP_STREAM_CTR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_FIFO +// Description : FIFO stream data +// Streamed data is buffered here, for retrieval by the system +// DMA. +// This FIFO can also be accessed via the XIP_AUX slave, to avoid +// exposing +// the DMA to bus stalls caused by other XIP traffic. +#define XIP_STREAM_FIFO_OFFSET 0x0000001c +#define XIP_STREAM_FIFO_BITS 0xffffffff +#define XIP_STREAM_FIFO_RESET 0x00000000 +#define XIP_STREAM_FIFO_MSB 31 +#define XIP_STREAM_FIFO_LSB 0 +#define XIP_STREAM_FIFO_ACCESS "RF" +// ============================================================================= +#endif // HARDWARE_REGS_XIP_DEFINED diff --git a/rp2040/hardware/regs/xosc.h b/rp2040/hardware/regs/xosc.h new file mode 100644 index 0000000..89d036b --- /dev/null +++ b/rp2040/hardware/regs/xosc.h @@ -0,0 +1,159 @@ +/** + * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XOSC +// Version : 1 +// Bus type : apb +// Description : Controls the crystal oscillator +// ============================================================================= +#ifndef HARDWARE_REGS_XOSC_DEFINED +#define HARDWARE_REGS_XOSC_DEFINED +// ============================================================================= +// Register : XOSC_CTRL +// Description : Crystal Oscillator Control +#define XOSC_CTRL_OFFSET 0x00000000 +#define XOSC_CTRL_BITS 0x00ffffff +#define XOSC_CTRL_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_ENABLE +// Description : On power-up this field is initialised to DISABLE and the chip +// runs from the ROSC. +// If the chip has subsequently been programmed to run from the +// XOSC then setting this field to DISABLE may lock-up the chip. +// If this is a concern then run the clk_ref from the ROSC and +// enable the clk_sys RESUS feature. +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will enable the +// oscillator. +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define XOSC_CTRL_ENABLE_RESET "-" +#define XOSC_CTRL_ENABLE_BITS 0x00fff000 +#define XOSC_CTRL_ENABLE_MSB 23 +#define XOSC_CTRL_ENABLE_LSB 12 +#define XOSC_CTRL_ENABLE_ACCESS "RW" +#define XOSC_CTRL_ENABLE_VALUE_DISABLE 0xd1e +#define XOSC_CTRL_ENABLE_VALUE_ENABLE 0xfab +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_FREQ_RANGE +// Description : Frequency range. This resets to 0xAA0 and cannot be changed. +// 0xaa0 -> 1_15MHZ +// 0xaa1 -> RESERVED_1 +// 0xaa2 -> RESERVED_2 +// 0xaa3 -> RESERVED_3 +#define XOSC_CTRL_FREQ_RANGE_RESET "-" +#define XOSC_CTRL_FREQ_RANGE_BITS 0x00000fff +#define XOSC_CTRL_FREQ_RANGE_MSB 11 +#define XOSC_CTRL_FREQ_RANGE_LSB 0 +#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ 0xaa0 +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 0xaa1 +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 0xaa2 +#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 0xaa3 +// ============================================================================= +// Register : XOSC_STATUS +// Description : Crystal Oscillator Status +#define XOSC_STATUS_OFFSET 0x00000004 +#define XOSC_STATUS_BITS 0x81001003 +#define XOSC_STATUS_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define XOSC_STATUS_STABLE_RESET 0x0 +#define XOSC_STATUS_STABLE_BITS 0x80000000 +#define XOSC_STATUS_STABLE_MSB 31 +#define XOSC_STATUS_STABLE_LSB 31 +#define XOSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or DORMANT +#define XOSC_STATUS_BADWRITE_RESET 0x0 +#define XOSC_STATUS_BADWRITE_BITS 0x01000000 +#define XOSC_STATUS_BADWRITE_MSB 24 +#define XOSC_STATUS_BADWRITE_LSB 24 +#define XOSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable, +// resets to 0 +#define XOSC_STATUS_ENABLED_RESET "-" +#define XOSC_STATUS_ENABLED_BITS 0x00001000 +#define XOSC_STATUS_ENABLED_MSB 12 +#define XOSC_STATUS_ENABLED_LSB 12 +#define XOSC_STATUS_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_FREQ_RANGE +// Description : The current frequency range setting, always reads 0 +// 0x0 -> 1_15MHZ +// 0x1 -> RESERVED_1 +// 0x2 -> RESERVED_2 +// 0x3 -> RESERVED_3 +#define XOSC_STATUS_FREQ_RANGE_RESET "-" +#define XOSC_STATUS_FREQ_RANGE_BITS 0x00000003 +#define XOSC_STATUS_FREQ_RANGE_MSB 1 +#define XOSC_STATUS_FREQ_RANGE_LSB 0 +#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ 0x0 +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 0x1 +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 0x2 +#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 0x3 +// ============================================================================= +// Register : XOSC_DORMANT +// Description : Crystal Oscillator pause control +// This is used to save power by pausing the XOSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// WARNING: stop the PLLs before selecting dormant mode +// WARNING: setup the irq before selecting dormant mode +// 0x636f6d61 -> DORMANT +// 0x77616b65 -> WAKE +#define XOSC_DORMANT_OFFSET 0x00000008 +#define XOSC_DORMANT_BITS 0xffffffff +#define XOSC_DORMANT_RESET "-" +#define XOSC_DORMANT_MSB 31 +#define XOSC_DORMANT_LSB 0 +#define XOSC_DORMANT_ACCESS "RW" +#define XOSC_DORMANT_VALUE_DORMANT 0x636f6d61 +#define XOSC_DORMANT_VALUE_WAKE 0x77616b65 +// ============================================================================= +// Register : XOSC_STARTUP +// Description : Controls the startup delay +#define XOSC_STARTUP_OFFSET 0x0000000c +#define XOSC_STARTUP_BITS 0x00103fff +#define XOSC_STARTUP_RESET 0x00000000 +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_X4 +// Description : Multiplies the startup_delay by 4. This is of little value to +// the user given that the delay can be programmed directly +#define XOSC_STARTUP_X4_RESET "-" +#define XOSC_STARTUP_X4_BITS 0x00100000 +#define XOSC_STARTUP_X4_MSB 20 +#define XOSC_STARTUP_X4_LSB 20 +#define XOSC_STARTUP_X4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_DELAY +// Description : in multiples of 256*xtal_period +#define XOSC_STARTUP_DELAY_RESET "-" +#define XOSC_STARTUP_DELAY_BITS 0x00003fff +#define XOSC_STARTUP_DELAY_MSB 13 +#define XOSC_STARTUP_DELAY_LSB 0 +#define XOSC_STARTUP_DELAY_ACCESS "RW" +// ============================================================================= +// Register : XOSC_COUNT +// Description : A down counter running at the xosc frequency which counts to +// zero and stops. +// To start the counter write a non-zero value. +// Can be used for short software pauses when setting up time +// sensitive hardware. +#define XOSC_COUNT_OFFSET 0x0000001c +#define XOSC_COUNT_BITS 0x000000ff +#define XOSC_COUNT_RESET 0x00000000 +#define XOSC_COUNT_MSB 7 +#define XOSC_COUNT_LSB 0 +#define XOSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // HARDWARE_REGS_XOSC_DEFINED diff --git a/rp2040/hardware/structs/adc.h b/rp2040/hardware/structs/adc.h new file mode 100644 index 0000000..559b5f1 --- /dev/null +++ b/rp2040/hardware/structs/adc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ADC_H +#define _HARDWARE_STRUCTS_ADC_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/adc.h" + +typedef struct { + io_rw_32 cs; + io_rw_32 result; + io_rw_32 fcs; + io_rw_32 fifo; + io_rw_32 div; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} adc_hw_t; + +check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET); + +#define adc_hw ((adc_hw_t *const)ADC_BASE) + +#endif diff --git a/rp2040/hardware/structs/bus_ctrl.h b/rp2040/hardware/structs/bus_ctrl.h new file mode 100644 index 0000000..ce95a7c --- /dev/null +++ b/rp2040/hardware/structs/bus_ctrl.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H +#define _HARDWARE_STRUCTS_BUS_CTRL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +enum bus_ctrl_perf_counter { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +}; + +typedef struct { + io_rw_32 priority; + io_ro_32 priority_ack; + struct { + io_rw_32 value; + io_rw_32 sel; + } counter[4]; +} bus_ctrl_hw_t; + +check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET); + +#define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE) + +#endif diff --git a/rp2040/hardware/structs/clocks.h b/rp2040/hardware/structs/clocks.h new file mode 100644 index 0000000..489876d --- /dev/null +++ b/rp2040/hardware/structs/clocks.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/clocks.h" + +/*! \brief Enumeration identifying a hardware clock + * \ingroup hardware_clocks + */ +/// \tag::clkenum[] +enum clock_index { + clk_gpout0 = 0, ///< GPIO Muxing 0 + clk_gpout1, ///< GPIO Muxing 1 + clk_gpout2, ///< GPIO Muxing 2 + clk_gpout3, ///< GPIO Muxing 3 + clk_ref, ///< Watchdog and timers reference clock + clk_sys, ///< Processors, bus fabric, memory, memory mapped registers + clk_peri, ///< Peripheral clock for UART and SPI + clk_usb, ///< USB clock + clk_adc, ///< ADC clock + clk_rtc, ///< Real time clock + CLK_COUNT +}; +/// \end::clkenum[] + +/// \tag::clock_hw[] +typedef struct { + io_rw_32 ctrl; + io_rw_32 div; + io_rw_32 selected; +} clock_hw_t; +/// \end::clock_hw[] + +typedef struct { + io_rw_32 ref_khz; + io_rw_32 min_khz; + io_rw_32 max_khz; + io_rw_32 delay; + io_rw_32 interval; + io_rw_32 src; + io_ro_32 status; + io_ro_32 result; +} fc_hw_t; + +typedef struct { + clock_hw_t clk[CLK_COUNT]; + struct { + io_rw_32 ctrl; + io_rw_32 status; + } resus; + fc_hw_t fc0; + io_rw_32 wake_en0; + io_rw_32 wake_en1; + io_rw_32 sleep_en0; + io_rw_32 sleep_en1; + io_rw_32 enabled0; + io_rw_32 enabled1; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} clocks_hw_t; + +#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) +#endif diff --git a/rp2040/hardware/structs/dma.h b/rp2040/hardware/structs/dma.h new file mode 100644 index 0000000..fd96167 --- /dev/null +++ b/rp2040/hardware/structs/dma.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/dma.h" + +typedef struct { + io_rw_32 read_addr; + io_rw_32 write_addr; + io_rw_32 transfer_count; + io_rw_32 ctrl_trig; + io_rw_32 al1_ctrl; + io_rw_32 al1_read_addr; + io_rw_32 al1_write_addr; + io_rw_32 al1_transfer_count_trig; + io_rw_32 al2_ctrl; + io_rw_32 al2_transfer_count; + io_rw_32 al2_read_addr; + io_rw_32 al2_write_addr_trig; + io_rw_32 al3_ctrl; + io_rw_32 al3_write_addr; + io_rw_32 al3_transfer_count; + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + dma_channel_hw_t ch[NUM_DMA_CHANNELS]; + uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)]; + io_ro_32 intr; + io_rw_32 inte0; + io_rw_32 intf0; + io_rw_32 ints0; + uint32_t _pad1[1]; + io_rw_32 inte1; + io_rw_32 intf1; + io_rw_32 ints1; + io_rw_32 timer[2]; + uint32_t _pad2[2]; + io_wo_32 multi_channel_trigger; + io_rw_32 sniff_ctrl; + io_rw_32 sniff_data; + uint32_t _pad3[1]; + io_ro_32 fifo_levels; + io_wo_32 abort; +} dma_hw_t; + +typedef struct { + struct dma_debug_hw_channel { + io_ro_32 ctrdeq; + io_ro_32 tcr; + uint32_t pad[14]; + } ch[NUM_DMA_CHANNELS]; +} dma_debug_hw_t; + +#define dma_hw ((dma_hw_t *const)DMA_BASE) +#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif diff --git a/rp2040/hardware/structs/i2c.h b/rp2040/hardware/structs/i2c.h new file mode 100644 index 0000000..4bc501f --- /dev/null +++ b/rp2040/hardware/structs/i2c.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_I2C_H +#define _HARDWARE_STRUCTS_I2C_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/i2c.h" + +typedef struct { + io_rw_32 con; + io_rw_32 tar; + io_rw_32 sar; + uint32_t _pad0; + io_rw_32 data_cmd; + io_rw_32 ss_scl_hcnt; + io_rw_32 ss_scl_lcnt; + io_rw_32 fs_scl_hcnt; + io_rw_32 fs_scl_lcnt; + uint32_t _pad1[2]; + io_rw_32 intr_stat; + io_rw_32 intr_mask; + io_rw_32 raw_intr_stat; + io_rw_32 rx_tl; + io_rw_32 tx_tl; + io_rw_32 clr_intr; + io_rw_32 clr_rx_under; + io_rw_32 clr_rx_over; + io_rw_32 clr_tx_over; + io_rw_32 clr_rd_req; + io_rw_32 clr_tx_abrt; + io_rw_32 clr_rx_done; + io_rw_32 clr_activity; + io_rw_32 clr_stop_det; + io_rw_32 clr_start_det; + io_rw_32 clr_gen_call; + io_rw_32 enable; + io_rw_32 status; + io_rw_32 txflr; + io_rw_32 rxflr; + io_rw_32 sda_hold; + io_rw_32 tx_abrt_source; + io_rw_32 slv_data_nack_only; + io_rw_32 dma_cr; + io_rw_32 dma_tdlr; + io_rw_32 dma_rdlr; + io_rw_32 sda_setup; + io_rw_32 ack_general_call; + io_rw_32 enable_status; + io_rw_32 fs_spklen; + uint32_t _pad2; + io_rw_32 clr_restart_det; +} i2c_hw_t; + +#define i2c0_hw ((i2c_hw_t *const)I2C0_BASE) +#define i2c1_hw ((i2c_hw_t *const)I2C1_BASE) + +// List of configuration constants for the Synopsys I2C hardware (you may see +// references to these in I2C register header; these are *fixed* values, +// set at hardware design time): + +// SLAVE_INTERFACE_TYPE .............. 0 +// REG_TIMEOUT_WIDTH ................. 4 +// REG_TIMEOUT_VALUE ................. 8 +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_SS_SCL_LOW_COUNT ............... 0x01d6 +// IC_HAS_DMA ........................ 0x1 +// IC_RX_FULL_GEN_NACK ............... 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x0 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x003c +// IC_HS_SCL_LOW_COUNT ............... 0x0010 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0xf +// IC_ADD_ENCODED_PARAMS ............. 0x1 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// SLVERR_RESP_EN .................... 0 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK ................... 0x1 +// HC_REG_TIMEOUT_VALUE .............. 0 +// IC_BUS_CLEAR_FEATURE .............. 0x1 +// IC_CAP_LOADING .................... 100 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_FS_SCL_LOW_COUNT ............... 0x0082 +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_TX_BUFFER_DEPTH ................ 32 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_CLK_TYPE ....................... 0x0 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x1 +// IC_STAT_FOR_CLK_STRETCH ........... 0x1 +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x1 +// IC_RX_BUFFER_DEPTH ................ 32 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 1 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_SMBUS_UDID_HC .................. 0x1 +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0190 + +#endif diff --git a/rp2040/hardware/structs/interp.h b/rp2040/hardware/structs/interp.h new file mode 100644 index 0000000..6837507 --- /dev/null +++ b/rp2040/hardware/structs/interp.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/sio.h" + +typedef struct { + io_rw_32 accum[2]; + io_rw_32 base[3]; + io_ro_32 pop[3]; + io_ro_32 peek[3]; + io_rw_32 ctrl[2]; + io_rw_32 add_raw[2]; + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif diff --git a/rp2040/hardware/structs/iobank0.h b/rp2040/hardware/structs/iobank0.h new file mode 100644 index 0000000..b19800f --- /dev/null +++ b/rp2040/hardware/structs/iobank0.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_IOBANK0_H +#define _HARDWARE_STRUCTS_IOBANK0_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/io_bank0.h" + +typedef struct { + io_rw_32 inte[4]; + io_rw_32 intf[4]; + io_rw_32 ints[4]; +} io_irq_ctrl_hw_t; + +/// \tag::iobank0_hw[] +typedef struct { + struct { + io_rw_32 status; + io_rw_32 ctrl; + } io[30]; + io_rw_32 intr[4]; + io_irq_ctrl_hw_t proc0_irq_ctrl; + io_irq_ctrl_hw_t proc1_irq_ctrl; + io_irq_ctrl_hw_t dormant_wake_irq_ctrl; +} iobank0_hw_t; +/// \end::iobank0_hw[] + +#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) + +#endif diff --git a/rp2040/hardware/structs/ioqspi.h b/rp2040/hardware/structs/ioqspi.h new file mode 100644 index 0000000..48d08a7 --- /dev/null +++ b/rp2040/hardware/structs/ioqspi.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_IOQSPI_H +#define _HARDWARE_STRUCTS_IOQSPI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/io_qspi.h" + +typedef struct { + struct { + io_rw_32 status; + io_rw_32 ctrl; + } io[6]; +} ioqspi_hw_t; + +#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) + +#endif diff --git a/rp2040/hardware/structs/mpu.h b/rp2040/hardware/structs/mpu.h new file mode 100644 index 0000000..34e5c39 --- /dev/null +++ b/rp2040/hardware/structs/mpu.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_MPU_H +#define _HARDWARE_STRUCTS_MPU_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +typedef struct { + io_ro_32 type; + io_rw_32 ctrl; + io_rw_32 rnr; + io_rw_32 rbar; + io_rw_32 rasr; +} mpu_hw_t; + +#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) + +#endif diff --git a/rp2040/hardware/structs/pads_qspi.h b/rp2040/hardware/structs/pads_qspi.h new file mode 100644 index 0000000..451d7eb --- /dev/null +++ b/rp2040/hardware/structs/pads_qspi.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H +#define _HARDWARE_STRUCTS_PADS_QSPI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pads_qspi.h" + +typedef struct { + io_rw_32 voltage_select; + io_rw_32 io[6]; +} pads_qspi_hw_t; + +#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) + +#endif diff --git a/rp2040/hardware/structs/padsbank0.h b/rp2040/hardware/structs/padsbank0.h new file mode 100644 index 0000000..f56dc40 --- /dev/null +++ b/rp2040/hardware/structs/padsbank0.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PADSBANK0_H +#define _HARDWARE_STRUCTS_PADSBANK0_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pads_bank0.h" + +typedef struct { + io_rw_32 voltage_select; + io_rw_32 io[30]; +} padsbank0_hw_t; + +#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE) + +#endif diff --git a/rp2040/hardware/structs/pio.h b/rp2040/hardware/structs/pio.h new file mode 100644 index 0000000..176863b --- /dev/null +++ b/rp2040/hardware/structs/pio.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PIO_H +#define _HARDWARE_STRUCTS_PIO_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pio.h" + +typedef struct { + io_rw_32 ctrl; + io_ro_32 fstat; + io_rw_32 fdebug; + io_ro_32 flevel; + io_wo_32 txf[NUM_PIO_STATE_MACHINES]; + io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; + io_rw_32 irq; + io_wo_32 irq_force; + io_rw_32 input_sync_bypass; + io_rw_32 dbg_padout; + io_rw_32 dbg_padoe; + io_rw_32 dbg_cfginfo; + io_wo_32 instr_mem[32]; + struct pio_sm_hw { + io_rw_32 clkdiv; + io_rw_32 execctrl; + io_rw_32 shiftctrl; + io_ro_32 addr; + io_rw_32 instr; + io_rw_32 pinctrl; + } sm[NUM_PIO_STATE_MACHINES]; + io_rw_32 intr; + io_rw_32 inte0; + io_rw_32 intf0; + io_ro_32 ints0; + io_rw_32 inte1; + io_rw_32 intf1; + io_ro_32 ints1; +} pio_hw_t; + +#define pio0_hw ((pio_hw_t *const)PIO0_BASE) +#define pio1_hw ((pio_hw_t *const)PIO1_BASE) + +#endif diff --git a/rp2040/hardware/structs/pll.h b/rp2040/hardware/structs/pll.h new file mode 100644 index 0000000..4d5b5b7 --- /dev/null +++ b/rp2040/hardware/structs/pll.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PLL_H +#define _HARDWARE_STRUCTS_PLL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/pll.h" + +/// \tag::pll_hw[] +typedef struct { + io_rw_32 cs; + io_rw_32 pwr; + io_rw_32 fbdiv_int; + io_rw_32 prim; +} pll_hw_t; + +#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE) +#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE) +/// \end::pll_hw[] + +#endif diff --git a/rp2040/hardware/structs/psm.h b/rp2040/hardware/structs/psm.h new file mode 100644 index 0000000..cc9fb97 --- /dev/null +++ b/rp2040/hardware/structs/psm.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PSM_H +#define _HARDWARE_STRUCTS_PSM_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/psm.h" + +typedef struct { + io_rw_32 frce_on; + io_rw_32 frce_off; + io_rw_32 wdsel; + io_rw_32 done; +} psm_hw_t; + +#define psm_hw ((psm_hw_t *const)PSM_BASE) + +#endif diff --git a/rp2040/hardware/structs/pwm.h b/rp2040/hardware/structs/pwm.h new file mode 100644 index 0000000..5499561 --- /dev/null +++ b/rp2040/hardware/structs/pwm.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_PWM_H +#define _HARDWARE_STRUCTS_PWM_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/pwm.h" + +typedef struct pwm_slice_hw { + io_rw_32 csr; + io_rw_32 div; + io_rw_32 ctr; + io_rw_32 cc; + io_rw_32 top; +} pwm_slice_hw_t; + +typedef struct { + pwm_slice_hw_t slice[NUM_PWM_SLICES]; + io_rw_32 en; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} pwm_hw_t; + +#define pwm_hw ((pwm_hw_t *const)PWM_BASE) + +#endif diff --git a/rp2040/hardware/structs/resets.h b/rp2040/hardware/structs/resets.h new file mode 100644 index 0000000..a96ddeb --- /dev/null +++ b/rp2040/hardware/structs/resets.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RESETS_H +#define _HARDWARE_STRUCTS_RESETS_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/resets.h" + +/// \tag::resets_hw[] +typedef struct { + io_rw_32 reset; + io_rw_32 wdsel; + io_rw_32 reset_done; +} resets_hw_t; + +#define resets_hw ((resets_hw_t *const)RESETS_BASE) +/// \end::resets_hw[] + +#endif diff --git a/rp2040/hardware/structs/rosc.h b/rp2040/hardware/structs/rosc.h new file mode 100644 index 0000000..1054393 --- /dev/null +++ b/rp2040/hardware/structs/rosc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_ROSC_H +#define _HARDWARE_STRUCTS_ROSC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/rosc.h" + +typedef struct { + io_rw_32 ctrl; + io_rw_32 freqa; + io_rw_32 freqb; + io_rw_32 dormant; + io_rw_32 div; + io_rw_32 phase; + io_rw_32 status; + io_rw_32 randombit; + io_rw_32 count; + io_rw_32 dftx; +} rosc_hw_t; + +#define rosc_hw ((rosc_hw_t *const)ROSC_BASE) + +#endif diff --git a/rp2040/hardware/structs/rtc.h b/rp2040/hardware/structs/rtc.h new file mode 100644 index 0000000..276bd7a --- /dev/null +++ b/rp2040/hardware/structs/rtc.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_RTC_H +#define _HARDWARE_STRUCTS_RTC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/rtc.h" + +typedef struct { + io_rw_32 clkdiv_m1; + io_rw_32 setup_0; + io_rw_32 setup_1; + io_rw_32 ctrl; + io_rw_32 irq_setup_0; + io_rw_32 irq_setup_1; + io_rw_32 rtc_1; + io_rw_32 rtc_0; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} rtc_hw_t; + +#define rtc_hw ((rtc_hw_t *const)RTC_BASE) + +#endif diff --git a/rp2040/hardware/structs/scb.h b/rp2040/hardware/structs/scb.h new file mode 100644 index 0000000..b48a872 --- /dev/null +++ b/rp2040/hardware/structs/scb.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SCB_H +#define _HARDWARE_STRUCTS_SCB_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// SCB == System Control Block +typedef struct { + io_ro_32 cpuid; + io_rw_32 icsr; + io_rw_32 vtor; + io_rw_32 aircr; + io_rw_32 scr; + // ... +} armv6m_scb_t; + +#define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET)) + +#endif diff --git a/rp2040/hardware/structs/sio.h b/rp2040/hardware/structs/sio.h new file mode 100644 index 0000000..400083f --- /dev/null +++ b/rp2040/hardware/structs/sio.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +typedef struct { + io_ro_32 cpuid; + io_ro_32 gpio_in; + io_ro_32 gpio_hi_in; + uint32_t _pad; + + io_wo_32 gpio_out; + io_wo_32 gpio_set; + io_wo_32 gpio_clr; + io_wo_32 gpio_togl; + + io_wo_32 gpio_oe; + io_wo_32 gpio_oe_set; + io_wo_32 gpio_oe_clr; + io_wo_32 gpio_oe_togl; + + io_wo_32 gpio_hi_out; + io_wo_32 gpio_hi_set; + io_wo_32 gpio_hi_clr; + io_wo_32 gpio_hi_togl; + + io_wo_32 gpio_hi_oe; + io_wo_32 gpio_hi_oe_set; + io_wo_32 gpio_hi_oe_clr; + io_wo_32 gpio_hi_oe_togl; + + io_rw_32 fifo_st; + io_wo_32 fifo_wr; + io_ro_32 fifo_rd; + io_ro_32 spinlock_st; + + io_rw_32 div_udividend; + io_rw_32 div_udivisor; + io_rw_32 div_sdividend; + io_rw_32 div_sdivisor; + + io_rw_32 div_quotient; + io_rw_32 div_remainder; + io_rw_32 div_csr; + + uint32_t _pad2; + + interp_hw_t interp[2]; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) + +#endif diff --git a/rp2040/hardware/structs/spi.h b/rp2040/hardware/structs/spi.h new file mode 100644 index 0000000..5b3b2ba --- /dev/null +++ b/rp2040/hardware/structs/spi.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SPI_H +#define _HARDWARE_STRUCTS_SPI_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/spi.h" + +typedef struct { + io_rw_32 cr0; + io_rw_32 cr1; + io_rw_32 dr; + io_rw_32 sr; + io_rw_32 cpsr; + io_rw_32 imsc; + io_rw_32 ris; + io_rw_32 mis; + io_rw_32 icr; + io_rw_32 dmacr; +} spi_hw_t; + +#define spi0_hw ((spi_hw_t *const)SPI0_BASE) +#define spi1_hw ((spi_hw_t *const)SPI1_BASE) + +#endif diff --git a/rp2040/hardware/structs/ssi.h b/rp2040/hardware/structs/ssi.h new file mode 100644 index 0000000..80779fe --- /dev/null +++ b/rp2040/hardware/structs/ssi.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SSI_H +#define _HARDWARE_STRUCTS_SSI_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/ssi.h" + +typedef struct { + io_rw_32 ctrlr0; + io_rw_32 ctrlr1; + io_rw_32 ssienr; + io_rw_32 mwcr; + io_rw_32 ser; + io_rw_32 baudr; + io_rw_32 txftlr; + io_rw_32 rxftlr; + io_rw_32 txflr; + io_rw_32 rxflr; + io_rw_32 sr; + io_rw_32 imr; + io_rw_32 isr; + io_rw_32 risr; + io_rw_32 txoicr; + io_rw_32 rxoicr; + io_rw_32 rxuicr; + io_rw_32 msticr; + io_rw_32 icr; + io_rw_32 dmacr; + io_rw_32 dmatdlr; + io_rw_32 dmardlr; + io_rw_32 idr; + io_rw_32 ssi_version_id; + io_rw_32 dr0; + uint32_t _pad[(0xf0 - 0x60) / 4 - 1]; + io_rw_32 rx_sample_dly; + io_rw_32 spi_ctrlr0; + io_rw_32 txd_drive_edge; +} ssi_hw_t; + +#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE) +#endif diff --git a/rp2040/hardware/structs/syscfg.h b/rp2040/hardware/structs/syscfg.h new file mode 100644 index 0000000..0bfc729 --- /dev/null +++ b/rp2040/hardware/structs/syscfg.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SYSCFG_H +#define _HARDWARE_STRUCTS_SYSCFG_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/syscfg.h" + +typedef struct { + io_rw_32 proc0_nmi_mask; + io_rw_32 proc1_nmi_mask; + io_rw_32 proc_config; + io_rw_32 proc_in_sync_bypass; + io_rw_32 proc_in_sync_bypass_hi; + io_rw_32 dbgforce; + io_rw_32 mempowerdown; +} syscfg_hw_t; + +#define syscfg_hw ((syscfg_hw_t *const)SYSCFG_BASE) + +#endif diff --git a/rp2040/hardware/structs/systick.h b/rp2040/hardware/structs/systick.h new file mode 100644 index 0000000..3c99971 --- /dev/null +++ b/rp2040/hardware/structs/systick.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_SYSTICK_H +#define _HARDWARE_STRUCTS_SYSTICK_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +typedef struct { + io_rw_32 csr; + io_rw_32 rvr; + io_ro_32 cvr; + io_ro_32 calib; +} systick_hw_t; + +#define systick_hw ((systick_hw_t *const)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET)) + +#endif diff --git a/rp2040/hardware/structs/timer.h b/rp2040/hardware/structs/timer.h new file mode 100644 index 0000000..e051a06 --- /dev/null +++ b/rp2040/hardware/structs/timer.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_TIMER_H +#define _HARDWARE_STRUCTS_TIMER_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/timer.h" + +#define NUM_TIMERS 4 + +typedef struct { + io_wo_32 timehw; + io_wo_32 timelw; + io_ro_32 timehr; + io_ro_32 timelr; + io_rw_32 alarm[NUM_TIMERS]; + io_rw_32 armed; + io_ro_32 timerawh; + io_ro_32 timerawl; + io_rw_32 dbgpause; + io_rw_32 pause; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_ro_32 ints; +} timer_hw_t; + +#define timer_hw ((timer_hw_t *const)TIMER_BASE) + +#endif diff --git a/rp2040/hardware/structs/uart.h b/rp2040/hardware/structs/uart.h new file mode 100644 index 0000000..42fe8e8 --- /dev/null +++ b/rp2040/hardware/structs/uart.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_UART_H +#define _HARDWARE_STRUCTS_UART_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/uart.h" + +typedef struct { + io_rw_32 dr; + io_rw_32 rsr; + uint32_t _pad0[4]; + io_rw_32 fr; + uint32_t _pad1; + io_rw_32 ilpr; + io_rw_32 ibrd; + io_rw_32 fbrd; + io_rw_32 lcr_h; + io_rw_32 cr; + io_rw_32 ifls; + io_rw_32 imsc; + io_rw_32 ris; + io_rw_32 mis; + io_rw_32 icr; + io_rw_32 dmacr; +} uart_hw_t; + +#define uart0_hw ((uart_hw_t *const)UART0_BASE) +#define uart1_hw ((uart_hw_t *const)UART1_BASE) + +#endif diff --git a/rp2040/hardware/structs/usb.h b/rp2040/hardware/structs/usb.h new file mode 100644 index 0000000..5c3c453 --- /dev/null +++ b/rp2040/hardware/structs/usb.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_USB_H +#define _HARDWARE_STRUCTS_USB_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" + +// 0-15 +#define USB_NUM_ENDPOINTS 16 + +// allow user to restrict number of endpoints available to save RAN +#ifndef USB_MAX_ENDPOINTS +#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS +#endif + +// 1-15 +#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) + +// Endpoint buffer control bits +#define USB_BUF_CTRL_FULL 0x00008000u +#define USB_BUF_CTRL_LAST 0x00004000u +#define USB_BUF_CTRL_DATA0_PID 0x00000000u +#define USB_BUF_CTRL_DATA1_PID 0x00002000u +#define USB_BUF_CTRL_SEL 0x00001000u +#define USB_BUF_CTRL_STALL 0x00000800u +#define USB_BUF_CTRL_AVAIL 0x00000400u +#define USB_BUF_CTRL_LEN_MASK 0x000003FFu +#define USB_BUF_CTRL_LEN_LSB 0 + +// ep_inout_ctrl bits +#define EP_CTRL_ENABLE_BITS (1u << 31u) +#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) +#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) +#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) +#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) +#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) +#define EP_CTRL_BUFFER_TYPE_LSB 26 +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16 + +#define USB_DPRAM_SIZE 4096 + +// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb +// Allow user to claim some of the USB RAM for themselves +#ifndef USB_DPRAM_MAX +#define USB_DPRAM_MAX USB_DPRAM_SIZE +#endif + +// Define maximum packet sizes +#define USB_MAX_ISO_PACKET_SIZE 1023 +#define USB_MAX_PACKET_SIZE 64 + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Starts at ep1 + struct usb_device_dpram_ep_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_ctrl[USB_NUM_ENDPOINTS - 1]; + + // Starts at ep0 + struct usb_device_dpram_ep_buf_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_buf_ctrl[USB_NUM_ENDPOINTS]; + + // EP0 buffers are fixed. Assumes single buffered mode for EP0 + uint8_t ep0_buf_a[0x40]; + uint8_t ep0_buf_b[0x40]; + + // Rest of DPRAM can be carved up as needed + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_device_dpram_t; + +static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Interrupt endpoint control 1 -> 15 + struct usb_host_dpram_ep_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_buf_ctrl; + io_rw_32 _spare0; + + // Interrupt endpoint buffer control + struct usb_host_dpram_ep_buf_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_ctrl; + + uint8_t _spare1[124]; + + // Should start at 0x180 + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_host_dpram_t; + +static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); + +typedef struct { + io_rw_32 dev_addr_ctrl; + io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + io_rw_32 main_ctrl; + io_rw_32 sof_rw; + io_ro_32 sof_rd; + io_rw_32 sie_ctrl; + io_rw_32 sie_status; + io_rw_32 int_ep_ctrl; + io_rw_32 buf_status; + io_rw_32 buf_cpu_should_handle; // for double buff + io_rw_32 abort; + io_rw_32 abort_done; + io_rw_32 ep_stall_arm; + io_rw_32 nak_poll; + io_rw_32 ep_nak_stall_status; + io_rw_32 muxing; + io_rw_32 pwr; + io_rw_32 phy_direct; + io_rw_32 phy_direct_override; + io_rw_32 phy_trim; + io_rw_32 linestate_tuning; + io_rw_32 intr; + io_rw_32 inte; + io_rw_32 intf; + io_rw_32 ints; +} usb_hw_t; + +check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET); + +#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) + +#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) +#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) + +#endif diff --git a/rp2040/hardware/structs/vreg_and_chip_reset.h b/rp2040/hardware/structs/vreg_and_chip_reset.h new file mode 100644 index 0000000..9956d68 --- /dev/null +++ b/rp2040/hardware/structs/vreg_and_chip_reset.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H +#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/vreg_and_chip_reset.h" + +typedef struct { + io_rw_32 vreg; + io_rw_32 bod; + io_rw_32 chip_reset; +} vreg_and_chip_reset_hw_t; + +#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *const)VREG_AND_CHIP_RESET_BASE) + +#endif diff --git a/rp2040/hardware/structs/watchdog.h b/rp2040/hardware/structs/watchdog.h new file mode 100644 index 0000000..2cf05f1 --- /dev/null +++ b/rp2040/hardware/structs/watchdog.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_WATCHDOG_H +#define _HARDWARE_STRUCTS_WATCHDOG_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/watchdog.h" + +typedef struct { + io_rw_32 ctrl; + io_wo_32 load; + io_ro_32 reason; + io_rw_32 scratch[8]; + io_rw_32 tick; +} watchdog_hw_t; + +#define watchdog_hw ((watchdog_hw_t *const)WATCHDOG_BASE) + +#endif diff --git a/rp2040/hardware/structs/xip_ctrl.h b/rp2040/hardware/structs/xip_ctrl.h new file mode 100644 index 0000000..bfa5b1c --- /dev/null +++ b/rp2040/hardware/structs/xip_ctrl.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H +#define _HARDWARE_STRUCTS_XIP_CTRL_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +typedef struct { + io_rw_32 ctrl; + io_rw_32 flush; + io_rw_32 stat; + io_rw_32 ctr_hit; + io_rw_32 ctr_acc; + io_rw_32 stream_addr; + io_rw_32 stream_ctr; + io_rw_32 stream_fifo; +} xip_ctrl_hw_t; + +#define XIP_STAT_FIFO_FULL 0x4u +#define XIP_STAT_FIFO_EMPTY 0x2u +#define XIP_STAT_FLUSH_RDY 0x1u + +#define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE) + +#endif diff --git a/rp2040/hardware/structs/xosc.h b/rp2040/hardware/structs/xosc.h new file mode 100644 index 0000000..698e6a2 --- /dev/null +++ b/rp2040/hardware/structs/xosc.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_XOSC_H +#define _HARDWARE_STRUCTS_XOSC_H + +#include "hardware/address_mapped.h" +#include "hardware/platform_defs.h" +#include "hardware/regs/xosc.h" + +/// \tag::xosc_hw[] +typedef struct { + io_rw_32 ctrl; + io_rw_32 status; + io_rw_32 dormant; + io_rw_32 startup; + io_rw_32 _reserved[3]; + io_rw_32 count; +} xosc_hw_t; + +#define xosc_hw ((xosc_hw_t *const)XOSC_BASE) +/// \end::xosc_hw[] + +#endif diff --git a/rp2040/pico.h b/rp2040/pico.h new file mode 100644 index 0000000..e23ab36 --- /dev/null +++ b/rp2040/pico.h @@ -0,0 +1,12 @@ +#ifndef _PICO_H +#define _PICO_H + +#include +#include + +typedef unsigned int uint; + +#include +#define static_assert _Static_assert + +#endif diff --git a/rp2040/rp2040.h b/rp2040/rp2040.h new file mode 100644 index 0000000..214d92e --- /dev/null +++ b/rp2040/rp2040.h @@ -0,0 +1,111 @@ +#ifndef _RP2040_H +#define _RP2040_H + +#define __NVIC_PRIO_BITS 2 + +typedef enum +{ + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + SVC_IRQn = -5, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + TIMER0_IRQn = 0, + TIMER1_IRQn = 1, + TIMER2_IRQn = 2, + TIMER3_IRQn = 3, + PWM_IRQn = 4, + USB_IRQn = 5, + XIP_IRQn = 6, + PIO0_0_IRQn = 7, + PIO0_1_IRQn = 8, + PIO1_0_IRQn = 9, + PIO1_1_IRQn = 10, + DMA0_IRQn = 11, + DMA1_IRQn = 12, + IO_IRQn = 13, + QSPI_IRQn = 14, + SIO0_IRQn = 15, + SIO1_IRQn = 16, + CLOCKS_IRQn = 17, + SPI0_IRQn = 18, + SPI1_IRQn = 19, + UART0_IRQn = 20, + UART1_IRQn = 21, + ADC_IRQn = 22, + I2C0_IRQn = 23, + I2C1_IRQn = 24, + RTC_IRQn = 25, +} IRQn_Type; + +#include "core_cm0.h" + +#include "hardware/regs/addressmap.h" + +#include "hardware/regs/adc.h" +#include "hardware/regs/busctrl.h" +#include "hardware/regs/clocks.h" +#include "hardware/regs/dma.h" +#include "hardware/regs/dreq.h" +#include "hardware/regs/i2c.h" +#include "hardware/regs/intctrl.h" +#include "hardware/regs/io_bank0.h" +#include "hardware/regs/io_qspi.h" +#include "hardware/regs/m0plus.h" +#include "hardware/regs/pads_bank0.h" +#include "hardware/regs/pads_qspi.h" +#include "hardware/regs/pio.h" +#include "hardware/regs/pll.h" +#include "hardware/regs/psm.h" +#include "hardware/regs/pwm.h" +#include "hardware/regs/resets.h" +#include "hardware/regs/rosc.h" +#include "hardware/regs/rtc.h" +#include "hardware/regs/sio.h" +#include "hardware/regs/spi.h" +#include "hardware/regs/ssi.h" +#include "hardware/regs/syscfg.h" +#include "hardware/regs/sysinfo.h" +#include "hardware/regs/tbman.h" +#include "hardware/regs/timer.h" +#include "hardware/regs/uart.h" +#include "hardware/regs/usb.h" +#include "hardware/regs/vreg_and_chip_reset.h" +#include "hardware/regs/watchdog.h" +#include "hardware/regs/xip.h" +#include "hardware/regs/xosc.h" + +#include "hardware/structs/adc.h" +#include "hardware/structs/bus_ctrl.h" +#include "hardware/structs/clocks.h" +#include "hardware/structs/dma.h" +#include "hardware/structs/i2c.h" +#include "hardware/structs/interp.h" +#include "hardware/structs/iobank0.h" +#include "hardware/structs/ioqspi.h" +#include "hardware/structs/mpu.h" +#include "hardware/structs/padsbank0.h" +#include "hardware/structs/pads_qspi.h" +#include "hardware/structs/pio.h" +#include "hardware/structs/pll.h" +#include "hardware/structs/psm.h" +#include "hardware/structs/pwm.h" +#include "hardware/structs/resets.h" +#include "hardware/structs/rosc.h" +#include "hardware/structs/rtc.h" +#include "hardware/structs/scb.h" +#include "hardware/structs/sio.h" +#include "hardware/structs/spi.h" +#include "hardware/structs/ssi.h" +#include "hardware/structs/syscfg.h" +#include "hardware/structs/systick.h" +#include "hardware/structs/timer.h" +#include "hardware/structs/uart.h" +#include "hardware/structs/usb.h" +#include "hardware/structs/vreg_and_chip_reset.h" +#include "hardware/structs/watchdog.h" +#include "hardware/structs/xip_ctrl.h" +#include "hardware/structs/xosc.h" + +#endif diff --git a/tinyusb b/tinyusb new file mode 160000 index 0000000..42dad78 --- /dev/null +++ b/tinyusb @@ -0,0 +1 @@ +Subproject commit 42dad78dbc9e906eddc560f9584ed4551f145240 diff --git a/tusb_config.h b/tusb_config.h new file mode 100644 index 0000000..11ad349 --- /dev/null +++ b/tusb_config.h @@ -0,0 +1,110 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by board.mk +#ifndef CFG_TUSB_MCU + #error CFG_TUSB_MCU must be defined +#endif + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_DEVICE_RHPORT_NUM + #define BOARD_DEVICE_RHPORT_NUM 0 +#endif + +// RHPort max operational speed can defined by board.mk +// Default to Highspeed for MCU with internal HighSpeed PHY (can be port specific), otherwise FullSpeed +#ifndef BOARD_DEVICE_RHPORT_SPEED + #if (CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX || \ + CFG_TUSB_MCU == OPT_MCU_NUC505 || CFG_TUSB_MCU == OPT_MCU_CXD56) + #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_HIGH_SPEED + #else + #define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED + #endif +#endif + +// Device mode with rhport and speed defined by board.mk +#if BOARD_DEVICE_RHPORT_NUM == 0 + #define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED) +#elif BOARD_DEVICE_RHPORT_NUM == 1 + #define CFG_TUSB_RHPORT1_MODE (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED) +#else + #error "Incorrect RHPort configuration" +#endif + +// This example doesn't use an RTOS +#define CFG_TUSB_OS OPT_OS_NONE + +// CFG_TUSB_DEBUG is defined by compiler in DEBUG build +// #define CFG_TUSB_DEBUG 0 + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_CDC 0 +#define CFG_TUD_MSC 0 +#define CFG_TUD_HID 1 +#define CFG_TUD_MIDI 0 +#define CFG_TUD_VENDOR 0 +#define CFG_TUD_NET 0 + +#define CFG_TUD_HID_EP_BUFSIZE 64 + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/usb_descriptors.c b/usb_descriptors.c new file mode 100644 index 0000000..e769d5c --- /dev/null +++ b/usb_descriptors.c @@ -0,0 +1,140 @@ +#include "tusb.h" + +// String Descriptor Index +enum +{ + STRID_LANGID = 0, + STRID_PRODUCT, +}; + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = +{ + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + /* using Dapper Miser CMSIS-DAP VID:PID */ + .idVendor = 0x1209, + .idProduct = 0x2488, + .bcdDevice = 0x1000, + + .iManufacturer = 0, + .iProduct = STRID_PRODUCT, + .iSerialNumber = 0, + + .bNumConfigurations = 0x01 +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const * tud_descriptor_device_cb(void) +{ + return (uint8_t const *) &desc_device; +} + +//--------------------------------------------------------------------+ +// HID Report Descriptor +//--------------------------------------------------------------------+ + +static uint8_t const desc_hid_report[] = +{ + TUD_HID_REPORT_DESC_GENERIC_INOUT(CFG_TUD_HID_EP_BUFSIZE) +}; + +// Invoked when received GET HID REPORT DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const * tud_hid_descriptor_report_cb(void) +{ + return desc_hid_report; +} + +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ + +enum +{ + ITF_NUM_HID, + ITF_NUM_TOTAL +}; + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_HID_INOUT_DESC_LEN) + +#define EPNUM_HID 0x01 + +uint8_t const desc_configuration[] = +{ + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP, 100), + + // Interface number, string index, protocol, report descriptor len, EP In & Out address, size & polling interval + TUD_HID_INOUT_DESCRIPTOR(ITF_NUM_HID, 0, HID_PROTOCOL_NONE, sizeof(desc_hid_report), EPNUM_HID, 0x80 | EPNUM_HID, CFG_TUD_HID_EP_BUFSIZE, 1) +}; + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const * tud_descriptor_configuration_cb(uint8_t index) +{ + (void) index; // for multiple configurations + return desc_configuration; +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// array of pointer to string descriptors +char const* string_desc_arr [] = +{ + [STRID_LANGID] = (const char[]) { 0x09, 0x04 }, // supported language is English (0x0409) + [STRID_PRODUCT] = "CMSIS-DAP", // Product +}; + +static uint16_t _desc_str[32]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) +{ + (void) langid; + + uint8_t chr_count; + + if ( index == 0) + { + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + }else + { + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if ( !(index < sizeof(string_desc_arr)/sizeof(string_desc_arr[0])) ) return NULL; + + const char* str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + if ( chr_count > 31 ) chr_count = 31; + + // Convert ASCII string into UTF-16 + for(uint8_t i=0; i