kopia lustrzana https://github.com/DL7AD/pecanpico9
Increased image sampling speed
rodzic
a4087588fa
commit
423f88a671
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@ -31,7 +31,7 @@ static const struct regval_list OV5640YUV_Sensor_Dvp_Init[] =
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{ 0x3017, 0x7f },
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{ 0x3018, 0xff },
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{ 0x302c, 0x02 },
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{ 0x3108, 0x31 },
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{ 0x3108, 0x21 },
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{ 0x3630, 0x2e },//2e
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{ 0x3632, 0xe2 },
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{ 0x3633, 0x23 },//23
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@ -757,7 +757,7 @@ static const struct regval_list OV5640_QSXGA2XGA[] =
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static ssdv_conf_t *ov5640_conf;
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/* TODO: Implement a state machine instead of multiple flags. */
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static bool LptimRdy;
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static bool LptimRdy = false;
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static bool capture_finished;
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static bool vsync;
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static bool dma_error;
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@ -1083,7 +1083,7 @@ CH_IRQ_HANDLER(Vector5C) {
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*/
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dma_stop();
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TIM1->DIER &= ~TIM_DIER_TDE;
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LPTIM1->CR &= ~LPTIM_CR_CNTSTRT;
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//LPTIM1->CR &= ~LPTIM_CR_CNTSTRT;
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/*
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* Disable VSYNC edge interrupts.
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@ -1183,45 +1183,48 @@ bool OV5640_Capture(void)
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dma_flags = 0;
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// Setup timer for PCLK
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rccResetLPTIM1();
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rccEnableLPTIM1(FALSE);
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if(!LptimRdy)
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{
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rccResetLPTIM1();
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rccEnableLPTIM1(FALSE);
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/*
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* LPTIM1 is run in external count mode (CKSEL = 0, COUNTMODE = 1).
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* CKPOL is set so leading and trailing edge of PCLK increment the counter.
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* The internal clocking (checking edges of LPTIM1_IN) is set to use APB.
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* The internal clock must be >4 times the frequency of the input (PCLK).
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* NOTE: This does not guarantee that LPTIM1_OUT is coincident with PCLK.
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* Depending on PCLK state when LPTIM1 is enabled OUT may get inverted.
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*
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* LPTIM1 is enabled on the VSYNC edge interrupt.
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* After enabling LPTIM1 wait for the first interrupt (ARRIF).
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* The interrupt must be disabled on the first interrupt (else flood).
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*
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* LPTIM1_OUT is gated to TIM1 internal trigger input 2.
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*/
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LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1 | LPTIM_CFGR_WAVPOL);
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LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP;
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LPTIM1->CR |= LPTIM_CR_ENABLE;
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LPTIM1->IER |= LPTIM_IER_ARRMIE;
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/*
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* LPTIM1 is run in external count mode (CKSEL = 0, COUNTMODE = 1).
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* CKPOL is set so leading and trailing edge of PCLK increment the counter.
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* The internal clocking (checking edges of LPTIM1_IN) is set to use APB.
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* The internal clock must be >4 times the frequency of the input (PCLK).
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* NOTE: This does not guarantee that LPTIM1_OUT is coincident with PCLK.
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* Depending on PCLK state when LPTIM1 is enabled OUT may get inverted.
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*
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* LPTIM1 is enabled on the VSYNC edge interrupt.
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* After enabling LPTIM1 wait for the first interrupt (ARRIF).
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* The interrupt must be disabled on the first interrupt (else flood).
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*
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* LPTIM1_OUT is gated to TIM1 internal trigger input 2.
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*/
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LPTIM1->CFGR = (LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKPOL_1 | LPTIM_CFGR_WAVPOL);
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LPTIM1->OR |= LPTIM_OR_TIM1_ITR2_RMP;
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LPTIM1->CR |= LPTIM_CR_ENABLE;
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LPTIM1->IER |= LPTIM_IER_ARRMIE;
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/*
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* When LPTIM1 is enabled and ready LPTIM1_OUT will be not set.
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* WAVPOL inverts LPTIM1_OUT so it is not set.
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* On the next PCLK edge LPTIM1 will count and match ARR.
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* LPTIM1_OUT will set briefly and then clear again due ARR match.
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* This triggers TIM1 with the short pulse from LPTIM1_OUT.
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* TODO:
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* This use of LPTIM1 works probably by good luck for now.
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* Switch to direct triggering of TIM using Capture input is better.
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* Requires a PCB change.
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*/
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LPTIM1->CMP = 0;
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LPTIM1->ARR = 1;
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/*
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* When LPTIM1 is enabled and ready LPTIM1_OUT will be not set.
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* WAVPOL inverts LPTIM1_OUT so it is not set.
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* On the next PCLK edge LPTIM1 will count and match ARR.
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* LPTIM1_OUT will set briefly and then clear again due ARR match.
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* This triggers TIM1 with the short pulse from LPTIM1_OUT.
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* TODO:
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* This use of LPTIM1 works probably by good luck for now.
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* Switch to direct triggering of TIM using Capture input is better.
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* Requires a PCB change.
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*/
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LPTIM1->CMP = 0;
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LPTIM1->ARR = 1;
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}
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/* Set vector and clear flag. */
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nvicEnableVector(LPTIM1_IRQn, 7); // Enable interrupt
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LptimRdy = false;
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//LptimRdy = false;
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/*
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* Setup slave timer to trigger DMA.
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