diff --git a/README.md b/README.md
index 6fe891c..59c2d2b 100644
--- a/README.md
+++ b/README.md
@@ -89,11 +89,17 @@ for compatibility.
 ### 1.4.1 Chips tested by users
 
 If you have success with other chips please raise an issue and I will update
-this doc.
+this doc. Please note the `cmd5` arg. It is essential to know whether a chip
+uses 4 or 5 byte commands and to set this correctly otherise very confusing
+behaviour results.
 
 CAT24C256LI-G I2C EEPROM 32KiB tested by
 [Julien Phalip](https://github.com/peterhinch/micropython_eeprom/issues/6#issuecomment-825801065).
 
+Winbond W25Q128JV Flash 128MiB tested by
+[mweber-bg](https://github.com/peterhinch/micropython_eeprom/issues/8#issuecomment-917603913).  
+This requires setting `cmd5=False`.
+
 ## 1.5 Performance
 
 FRAM is truly byte-addressable: its speed is limited only by the speed of the
diff --git a/bdevice.py b/bdevice.py
index 5ea4bf0..e3e00e4 100644
--- a/bdevice.py
+++ b/bdevice.py
@@ -68,6 +68,7 @@ class BlockDevice:
     def writeblocks(self, blocknum, buf, offset=0):
         self.readwrite(offset + (blocknum << self._nbits), buf, False)
 
+    # https://docs.micropython.org/en/latest/library/os.html#os.AbstractBlockDev.ioctl
     def ioctl(self, op, arg):  # ioctl calls: see extmod/vfs.h
         if op == 3:  # SYNCHRONISE
             self.sync()
@@ -76,7 +77,7 @@ class BlockDevice:
             return self._a_bytes >> self._nbits
         if op == 5:  # BP_IOCTL_SEC_SIZE
             return self._block_size
-        if op == 6:  # ERASE
+        if op == 6:  # Ignore ERASE because handled by driver.
             return 0
 
 # Hardware agnostic base class for flash memory.