kopia lustrzana https://github.com/peterhinch/micropython_eeprom
Tested with 256KiB STM chip. SPI bug fixed.
rodzic
4624fb41c6
commit
07def0505c
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@ -59,8 +59,6 @@ In the table below the Interface column includes page size in bytes.
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| Microchip | 24xx64 | I2C 128 | 8KiB | EEPROM | [I2C.md](./i2c/I2C.md) |
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| Microchip | 24xx64 | I2C 128 | 8KiB | EEPROM | [I2C.md](./i2c/I2C.md) |
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| Adafruit | 1895 | I2C n/a | 32KiB | FRAM | [FRAM.md](./fram/FRAM.md) |
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| Adafruit | 1895 | I2C n/a | 32KiB | FRAM | [FRAM.md](./fram/FRAM.md) |
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**STM chip support under development**
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Documentation:
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Documentation:
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[SPI.md](./spi/SPI.md)
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[SPI.md](./spi/SPI.md)
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[I2C.md](./i2c/I2C.md)
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[I2C.md](./i2c/I2C.md)
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@ -82,3 +82,4 @@ class EEPROM(BlockDevice):
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nbytes -= npage
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nbytes -= npage
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start += npage
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start += npage
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addr += npage
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addr += npage
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return buf
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@ -4,8 +4,6 @@ This driver supports the Microchip 25xx1024 series of 128KiB SPI EEPROMs and
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the STM M95M02-DR 256KiB device. These have 1M and 4M cycles of write endurance
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the STM M95M02-DR 256KiB device. These have 1M and 4M cycles of write endurance
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respectively (compared to 10K for Pyboard Flash memory).
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respectively (compared to 10K for Pyboard Flash memory).
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**NOTE: STM chip not yet tested**
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Multiple chips may be used to construct a single logical nonvolatile memory
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Multiple chips may be used to construct a single logical nonvolatile memory
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module. The driver allows the memory either to be mounted in the target
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module. The driver allows the memory either to be mounted in the target
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filesystem as a disk device or to be addressed as an array of bytes.
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filesystem as a disk device or to be addressed as an array of bytes.
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@ -9,19 +9,21 @@ import time
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from micropython import const
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from micropython import const
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from bdevice import BlockDevice
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from bdevice import BlockDevice
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# Supported instruction set
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# Supported instruction set - common to both chips:
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_READ = const(3)
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_READ = const(3)
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_WRITE = const(2)
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_WRITE = const(2)
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_WREN = const(6) # Write enable
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_WREN = const(6) # Write enable
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_RDSR = const(5) # Read status register
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_RDSR = const(5) # Read status register
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# Microchip only:
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_RDID = const(0xab) # Read chip ID
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_RDID = const(0xab) # Read chip ID
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_CE = const(0xc7) # Chip erase (Microchip only)
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_CE = const(0xc7) # Chip erase
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# STM only:
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_RDID_STM = const(0x83) # Read ID page
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_WRID_STM = const(0x82)
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_STM_ID = const(0x30) # Arbitrary ID for STM chip
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# Not implemented: Write disable and Write status register
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# Not implemented: Write disable and Write status register
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# _WRDI = const(4)
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# _WRDI = const(4)
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# _WRSR = const(1)
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# _WRSR = const(1)
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#_RDID_STM = const(0x83) # STM only read ID page
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#_WRID_STM = const(0x82)
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#_STM_ID = const(0x30) # Arbitrary ID for STM chip
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# Logical EEPROM device comprising one or more physical chips sharing an SPI bus.
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# Logical EEPROM device comprising one or more physical chips sharing an SPI bus.
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class EEPROM(BlockDevice):
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class EEPROM(BlockDevice):
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@ -39,37 +41,41 @@ class EEPROM(BlockDevice):
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self._mvp = memoryview(self._bufp) # cost-free slicing
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self._mvp = memoryview(self._bufp) # cost-free slicing
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self.scan(verbose)
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self.scan(verbose)
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# STM Datasheet too vague about the ID block. Do we need _WREN? Do we need to poll ready?
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# Read ID block ID[0]
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#def _stm_rdid(self):
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def _stm_rdid(self, n):
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#mvp = self._mvp
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cs = self._cspins[n]
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#mvp[:] = b'\0\0\0\0\0'
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mvp = self._mvp
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#mvp[0] = _RDID_STM
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mvp[:] = b'\0\0\0\0\0'
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#cs(0)
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mvp[0] = _RDID_STM
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#self._spi.write_readinto(mvp, mvp)
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cs(0)
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#cs(1)
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self._spi.write_readinto(mvp, mvp)
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#return mvp[4]
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cs(1)
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return mvp[4]
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#def _stm_wrid(self):
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# Write a fixed value to ID[0]
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#mvp = self._mvp
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def _stm_wrid(self, n):
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#mvp[:] = b'\0\0\0\0\0'
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cs = self._ccs
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#mvp[0] = _WRID_STM
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mvp = self._mvp
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#mvp[5] = _STM_ID
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mvp[0] = _WREN
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#cs(0)
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cs(0)
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#self._spi.write(mvp)
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self._spi.write(mvp[:1]) # Enable write
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#cs(1)
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cs(1)
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mvp[:] = b'\0\0\0\0\0'
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mvp[0] = _WRID_STM
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mvp[4] = _STM_ID
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cs(0)
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self._spi.write(mvp)
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cs(1)
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self._wait_rdy()
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# Check for a valid hardware configuration: just see if we can write to offset 0
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# Check for valid hardware on each CS pin: use ID block
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# Tested (on Microchip), but probably better to use ID block
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def _stm_scan(self):
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def _stm_scan(self):
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for n in range(len(self._cspins)):
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for n, cs in enumerate(self._cspins):
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ta = n * self._c_bytes
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self._ccs = cs
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v = self[ta]
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if self._stm_rdid(n) != _STM_ID:
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vx = v^0xff
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self._stm_wrid(n)
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self[ta] = vx
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if self._stm_rdid(n) != _STM_ID:
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if self[ta] == vx: # Wrote OK, put back
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raise RuntimeError('M95M02 chip not found at cs[{}].'.format(n))
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self[ta] = v
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else:
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raise RuntimeError('EEPROM not found at cs[{}].'.format(n))
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return n
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return n
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# Scan for Microchip devices: read manf ID
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# Scan for Microchip devices: read manf ID
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@ -82,7 +88,7 @@ class EEPROM(BlockDevice):
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self._spi.write_readinto(mvp, mvp)
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self._spi.write_readinto(mvp, mvp)
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cs(1)
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cs(1)
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if mvp[4] != 0x29:
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if mvp[4] != 0x29:
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raise RuntimeError('EEPROM not found at cs[{}].'.format(n))
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raise RuntimeError('25xx1024 chip not found at cs[{}].'.format(n))
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return n
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return n
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# Check for a valid hardware configuration
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# Check for a valid hardware configuration
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@ -163,3 +169,4 @@ class EEPROM(BlockDevice):
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nbytes -= npage
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nbytes -= npage
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start += npage
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start += npage
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addr += npage
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addr += npage
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return buf
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