kopia lustrzana https://github.com/micropython/micropython
490 wiersze
18 KiB
C
490 wiersze
18 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Philipp Ebensberger
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* Copyright (c) 2022 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// This file is never compiled standalone, it's included directly from
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// extmod/machine_adc.c via MICROPY_PY_MACHINE_ADC_INCLUDEFILE.
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#include <stdint.h>
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#include "py/obj.h"
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#include "py/mperrno.h"
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#include "mphalport.h"
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#include "sam.h"
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#include "pin_af.h"
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#include "samd_soc.h"
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#include "dma_manager.h"
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#include "tc_manager.h"
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typedef struct _machine_adc_obj_t {
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mp_obj_base_t base;
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adc_config_t adc_config;
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uint8_t id;
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uint8_t avg;
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uint8_t bits;
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uint8_t vref;
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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int8_t dma_channel;
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int8_t tc_index;
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#endif
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} machine_adc_obj_t;
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#define DEFAULT_ADC_BITS 12
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#define DEFAULT_ADC_AVG 16
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#if defined(MCU_SAMD21)
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static uint8_t adc_vref_table[] = {
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ADC_REFCTRL_REFSEL_INT1V_Val, ADC_REFCTRL_REFSEL_INTVCC0_Val,
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ADC_REFCTRL_REFSEL_INTVCC1_Val, ADC_REFCTRL_REFSEL_AREFA_Val, ADC_REFCTRL_REFSEL_AREFB_Val
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};
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#if MICROPY_HW_ADC_VREF
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#define DEFAULT_ADC_VREF MICROPY_HW_ADC_VREF
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#else
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#define DEFAULT_ADC_VREF (3)
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#endif
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#define MAX_ADC_VREF (4)
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#define ADC_EVSYS_CHANNEL 0
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typedef struct _device_mgmt_t {
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bool init;
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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bool busy;
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mp_obj_t callback;
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mp_obj_t self;
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#endif
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} device_mgmt_t;
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device_mgmt_t device_mgmt[ADC_INST_NUM];
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#elif defined(MCU_SAMD51)
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static uint8_t adc_vref_table[] = {
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ADC_REFCTRL_REFSEL_INTREF_Val, ADC_REFCTRL_REFSEL_INTVCC1_Val,
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ADC_REFCTRL_REFSEL_INTVCC0_Val, ADC_REFCTRL_REFSEL_AREFA_Val,
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ADC_REFCTRL_REFSEL_AREFB_Val, ADC_REFCTRL_REFSEL_AREFC_Val
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};
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#if MICROPY_HW_ADC_VREF
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#define DEFAULT_ADC_VREF MICROPY_HW_ADC_VREF
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#else
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#define DEFAULT_ADC_VREF (3)
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#endif
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#define MAX_ADC_VREF (5)
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typedef struct _device_mgmt_t {
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bool init;
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bool busy;
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int8_t dma_channel;
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mp_obj_t callback;
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mp_obj_t self;
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} device_mgmt_t;
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device_mgmt_t device_mgmt[ADC_INST_NUM];
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#endif // defined(MCU_SAMD21)
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// The ADC class doesn't have any constants for this port.
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#define MICROPY_PY_MACHINE_ADC_CLASS_CONSTANTS
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Adc *const adc_bases[] = ADC_INSTS;
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uint32_t ch_busy_flags = 0;
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static uint8_t resolution[] = {
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ADC_CTRLB_RESSEL_8BIT_Val, ADC_CTRLB_RESSEL_10BIT_Val, ADC_CTRLB_RESSEL_12BIT_Val
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};
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static void adc_init(machine_adc_obj_t *self);
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extern mp_int_t log2i(mp_int_t num);
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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// Active just for SAMD21, stops the freerun mode
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// For SAMD51, just the INT flag is reset.
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void adc_irq_handler(int dma_channel) {
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#if defined(MCU_SAMD21)
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DMAC->CHID.reg = dma_channel;
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DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL | DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_SUSP;
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ADC->EVCTRL.bit.STARTEI = 0;
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device_mgmt[0].busy = 0;
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if (device_mgmt[0].callback != MP_OBJ_NULL) {
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mp_sched_schedule(device_mgmt[0].callback, device_mgmt[0].self);
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}
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#elif defined(MCU_SAMD51)
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DMAC->Channel[dma_channel].CHINTFLAG.reg =
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DMAC_CHINTFLAG_TCMPL | DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_SUSP;
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if (device_mgmt[0].dma_channel == dma_channel) {
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device_mgmt[0].busy = 0;
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if (device_mgmt[0].callback != MP_OBJ_NULL) {
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mp_sched_schedule(device_mgmt[0].callback, device_mgmt[0].self);
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}
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} else if (device_mgmt[1].dma_channel == dma_channel) {
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device_mgmt[1].busy = 0;
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if (device_mgmt[1].callback != MP_OBJ_NULL) {
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mp_sched_schedule(device_mgmt[1].callback, device_mgmt[1].self);
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}
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}
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#endif
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}
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#endif
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static void mp_machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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(void)kind;
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machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "ADC(%q, device=%u, channel=%u, bits=%u, average=%u, vref=%d)",
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pin_find_by_id(self->id)->name, self->adc_config.device,
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self->adc_config.channel, self->bits, 1 << self->avg, self->vref);
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}
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static mp_obj_t mp_machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
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enum { ARG_id, ARG_bits, ARG_average, ARG_vref, ARG_callback };
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ },
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{ MP_QSTR_bits, MP_ARG_INT, {.u_int = DEFAULT_ADC_BITS} },
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{ MP_QSTR_average, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_AVG} },
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{ MP_QSTR_vref, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_ADC_VREF} },
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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{ MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
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#endif
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};
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// Parse the arguments.
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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// Unpack and check, whether the pin has ADC capability
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int id = mp_hal_get_pin_obj(args[ARG_id].u_obj);
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adc_config_t adc_config = get_adc_config(id, ch_busy_flags);
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// Now that we have a valid device and channel, create and populate the ADC instance
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machine_adc_obj_t *self = mp_obj_malloc(machine_adc_obj_t, &machine_adc_type);
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self->id = id;
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self->adc_config = adc_config;
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self->bits = DEFAULT_ADC_BITS;
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uint16_t bits = args[ARG_bits].u_int;
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if (8 <= bits && bits <= 12) {
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self->bits = bits;
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}
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uint32_t avg = log2i(args[ARG_average].u_int);
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self->avg = (avg <= 10 ? avg : 10);
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uint8_t vref = args[ARG_vref].u_int;
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if (0 <= vref && vref <= MAX_ADC_VREF) {
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self->vref = vref;
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}
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// flag the device/channel as being in use.
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ch_busy_flags |= (1 << (self->adc_config.device * 16 + self->adc_config.channel));
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device_mgmt[self->adc_config.device].init = false;
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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device_mgmt[adc_config.device].callback = args[ARG_callback].u_obj;
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if (device_mgmt[adc_config.device].callback == mp_const_none) {
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device_mgmt[adc_config.device].callback = MP_OBJ_NULL;
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} else {
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device_mgmt[adc_config.device].self = self;
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}
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self->dma_channel = -1;
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self->tc_index = -1;
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#endif
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adc_init(self);
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return MP_OBJ_FROM_PTR(self);
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}
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// read_u16()
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static mp_int_t mp_machine_adc_read_u16(machine_adc_obj_t *self) {
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Adc *adc = adc_bases[self->adc_config.device];
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// Set the reference voltage. Default: external AREFA.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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if (device_mgmt[self->adc_config.device].busy != 0) {
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mp_raise_OSError(MP_EBUSY);
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}
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#endif
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// Set the reference voltage. Default: external AREFA.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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// Set Input channel and resolution
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// Select the pin as positive input and gnd as negative input reference, non-diff mode by default
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adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel;
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// set resolution. Scale 8-16 to 0 - 4 for table access.
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adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2];
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#if defined(MCU_SAMD21)
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// Stop the ADC sampling by timer
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adc->EVCTRL.bit.STARTEI = 0;
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#elif defined(MCU_SAMD51)
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// Do not restart ADC after data has bee read
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adc->DSEQCTRL.reg = 0;
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#endif
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// Measure input voltage
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adc->SWTRIG.bit.START = 1;
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while (adc->INTFLAG.bit.RESRDY == 0) {
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}
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// Get and return the result
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return adc->RESULT.reg * (65536 / (1 << self->bits));
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}
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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static void mp_machine_adc_read_timed(machine_adc_obj_t *self, mp_obj_t values, mp_int_t freq) {
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Adc *adc = adc_bases[self->adc_config.device];
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mp_buffer_info_t src;
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mp_get_buffer_raise(values, &src, MP_BUFFER_READ);
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if (src.len >= 2) {
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if (self->tc_index == -1) {
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self->tc_index = allocate_tc_instance();
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}
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if (self->dma_channel == -1) {
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self->dma_channel = allocate_dma_channel();
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dma_init();
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dma_register_irq(self->dma_channel, adc_irq_handler);
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}
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// Set the reference voltage. Default: external AREFA.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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// Set Input channel and resolution
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// Select the pin as positive input and gnd as negative input reference, non-diff mode by default
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adc->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND | self->adc_config.channel;
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// set resolution. Scale 8-16 to 0 - 4 for table access.
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adc->CTRLB.bit.RESSEL = resolution[(self->bits - 8) / 2];
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// Configure DMA for halfword output to the DAC
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#if defined(MCU_SAMD21)
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configure_tc(self->tc_index, freq, TC_EVCTRL_OVFEO);
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// Enable APBC clock
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PM->APBCMASK.reg |= PM_APBCMASK_EVSYS;
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// Set up the EVSYS channel
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EVSYS->CTRL.bit.SWRST = 1;
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EVSYS->USER.reg = EVSYS_USER_CHANNEL(ADC_EVSYS_CHANNEL + 1) |
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EVSYS_USER_USER(EVSYS_ID_USER_ADC_START);
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EVSYS->CHANNEL.reg = EVSYS_CHANNEL_CHANNEL(ADC_EVSYS_CHANNEL) |
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EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_TC3_OVF + 3 * self->tc_index) |
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EVSYS_CHANNEL_PATH_ASYNCHRONOUS;
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dma_desc[self->dma_channel].BTCTRL.reg =
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DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_STEPSEL |
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DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
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dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
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dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(&adc->RESULT.reg);
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dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(src.buf) + src.len;
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dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
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DMAC->CHID.reg = self->dma_channel;
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DMAC->CHCTRLA.reg = 0;
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while (DMAC->CHCTRLA.bit.ENABLE) {
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}
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DMAC->CHCTRLB.reg =
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DMAC_CHCTRLB_LVL(0) |
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DMAC_CHCTRLB_TRIGACT_BEAT |
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DMAC_CHCTRLB_TRIGSRC(ADC_DMAC_ID_RESRDY);
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DMAC->CHINTENSET.reg = DMAC_CHINTFLAG_TCMPL;
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DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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NVIC_EnableIRQ(DMAC_IRQn);
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adc->EVCTRL.bit.STARTEI = 1;
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device_mgmt[0].busy = 1;
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#elif defined(MCU_SAMD51)
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configure_tc(self->tc_index, freq, 0);
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device_mgmt[self->adc_config.device].dma_channel = self->dma_channel;
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// Restart ADC after data has bee read
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adc->DSEQCTRL.reg = ADC_DSEQCTRL_AUTOSTART;
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// Start the first sampling to ensure we get a proper first value.
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adc->SWTRIG.bit.START = 1;
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while (adc->INTFLAG.bit.RESRDY == 0) {
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}
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// Wait a little bit allowing the ADC to settle.
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mp_hal_delay_us(15);
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dma_desc[self->dma_channel].BTCTRL.reg =
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DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_DSTINC | DMAC_BTCTRL_STEPSEL |
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DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
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dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
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dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(&adc->RESULT.reg);
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dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(src.buf) + src.len;
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dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
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DMAC->Channel[self->dma_channel].CHCTRLA.reg =
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DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) |
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DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) |
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DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index);
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DMAC->Channel[self->dma_channel].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
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DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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if (self->dma_channel < 4) {
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NVIC_EnableIRQ(DMAC_0_IRQn + self->dma_channel);
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} else {
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NVIC_EnableIRQ(DMAC_4_IRQn);
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}
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device_mgmt[self->adc_config.device].busy = 1;
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#endif // defined SAMD21 or SAMD51
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}
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}
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// busy() : Report, if the ADC device is busy
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static mp_obj_t mp_machine_adc_busy(machine_adc_obj_t *self) {
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return device_mgmt[self->adc_config.device].busy ? mp_const_true : mp_const_false;
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}
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#endif
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// deinit() : release the ADC channel
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static void mp_machine_adc_deinit(machine_adc_obj_t *self) {
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ch_busy_flags &= ~((1 << (self->adc_config.device * 16 + self->adc_config.channel)));
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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if (self->dma_channel >= 0) {
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#if defined(MCU_SAMD51)
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if (self->dma_channel == device_mgmt[self->adc_config.device].dma_channel) {
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device_mgmt[self->adc_config.device].dma_channel = -1;
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device_mgmt[self->adc_config.device].busy = 0;
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}
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#endif
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dac_stop_dma(self->dma_channel, true);
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free_dma_channel(self->dma_channel);
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self->dma_channel = -1;
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}
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if (self->tc_index >= 0) {
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free_tc_instance(self->tc_index);
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self->tc_index = -1;
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}
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#endif
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}
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#if MICROPY_PY_MACHINE_ADC_READ_TIMED
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void adc_deinit_all(void) {
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ch_busy_flags = 0;
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device_mgmt[0].init = 0;
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#if defined(MCU_SAMD51)
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device_mgmt[0].dma_channel = -1;
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device_mgmt[1].init = 0;
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device_mgmt[1].dma_channel = -1;
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#endif
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}
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#else
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void adc_deinit_all(void) {
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ch_busy_flags = 0;
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device_mgmt[0].init = 0;
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#if defined(MCU_SAMD51)
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device_mgmt[1].init = 0;
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#endif
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}
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#endif
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static void adc_init(machine_adc_obj_t *self) {
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// ADC & clock init is done only once per ADC
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if (device_mgmt[self->adc_config.device].init == false) {
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Adc *adc = adc_bases[self->adc_config.device];
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device_mgmt[self->adc_config.device].init = true;
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#if defined(MCU_SAMD21)
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// Configuration SAMD21
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// Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz
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PM->APBCMASK.reg |= PM_APBCMASK_ADC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK5 | GCLK_CLKCTRL_ID_ADC;
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Reset ADC registers
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adc->CTRLA.bit.SWRST = 1;
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while (adc->CTRLA.bit.SWRST) {
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}
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// Get the calibration data
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uint32_t bias = (*((uint32_t *)ADC_FUSES_BIASCAL_ADDR) & ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;
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uint32_t linearity = (*((uint32_t *)ADC_FUSES_LINEARITY_0_ADDR) & ADC_FUSES_LINEARITY_0_Msk) >> ADC_FUSES_LINEARITY_0_Pos;
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linearity |= ((*((uint32_t *)ADC_FUSES_LINEARITY_1_ADDR) & ADC_FUSES_LINEARITY_1_Msk) >> ADC_FUSES_LINEARITY_1_Pos) << 5;
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/* Write the calibration data. */
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ADC->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) | ADC_CALIB_LINEARITY_CAL(linearity);
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// Divide a 48MHz clock by 32 to obtain 1.5 MHz clock to adc
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adc->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV32;
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// Select external AREFA as reference voltage.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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// Average: Accumulate samples and scale them down accordingly
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adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg);
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// Enable ADC and wait to be ready
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adc->CTRLA.bit.ENABLE = 1;
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while (adc->STATUS.bit.SYNCBUSY) {
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}
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#elif defined(MCU_SAMD51)
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// Configuration SAMD51
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// Enable APBD clocks and PCHCTRL clocks; GCLK5 at 48 MHz
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if (self->adc_config.device == 0) {
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GCLK->PCHCTRL[ADC0_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN;
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MCLK->APBDMASK.bit.ADC0_ = 1;
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} else {
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GCLK->PCHCTRL[ADC1_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK5 | GCLK_PCHCTRL_CHEN;
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MCLK->APBDMASK.bit.ADC1_ = 1;
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}
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// Reset ADC registers
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adc->CTRLA.bit.SWRST = 1;
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while (adc->CTRLA.bit.SWRST) {
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}
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// Get the calibration data
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uint32_t biascomp;
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uint32_t biasr2r;
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uint32_t biasrefbuf;
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if (self->adc_config.device == 0) {
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biascomp = (*((uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos;
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biasr2r = (*((uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos;
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biasrefbuf = (*((uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR) & ADC0_FUSES_BIASREFBUF_Msk) >> ADC0_FUSES_BIASREFBUF_Pos;
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} else {
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biascomp = (*((uint32_t *)ADC1_FUSES_BIASCOMP_ADDR) & ADC1_FUSES_BIASCOMP_Msk) >> ADC1_FUSES_BIASCOMP_Pos;
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biasr2r = (*((uint32_t *)ADC1_FUSES_BIASR2R_ADDR) & ADC1_FUSES_BIASR2R_Msk) >> ADC1_FUSES_BIASR2R_Pos;
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biasrefbuf = (*((uint32_t *)ADC1_FUSES_BIASREFBUF_ADDR) & ADC1_FUSES_BIASREFBUF_Msk) >> ADC1_FUSES_BIASREFBUF_Pos;
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}
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/* Write the calibration data. */
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adc->CALIB.reg = ADC_CALIB_BIASCOMP(biascomp) | ADC_CALIB_BIASR2R(biasr2r) | ADC_CALIB_BIASREFBUF(biasrefbuf);
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// Divide 48MHz clock by 4 to obtain 12 MHz clock to adc
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adc->CTRLA.reg = ADC_CTRLA_PRESCALER_DIV4;
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// Enable the offset compensation
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adc->SAMPCTRL.reg = ADC_SAMPCTRL_OFFCOMP;
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// Set the reference voltage. Default: external AREFA.
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adc->REFCTRL.reg = adc_vref_table[self->vref];
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// Average: Accumulate samples and scale them down accordingly
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adc->AVGCTRL.reg = self->avg | ADC_AVGCTRL_ADJRES(self->avg);
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// Enable ADC and wait to be ready
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adc->CTRLA.bit.ENABLE = 1;
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while (adc->SYNCBUSY.bit.ENABLE) {
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}
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#endif
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}
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// Set the port as given in self->id as ADC
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mp_hal_set_pin_mux(self->id, ALT_FCT_ADC);
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}
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