kopia lustrzana https://github.com/micropython/micropython
754 wiersze
23 KiB
Python
754 wiersze
23 KiB
Python
#
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# Driver class for the WM8960 Codec to be used e.g. with MIMXRT_1xxx Boards.
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# Derived from the NXP SDK drivers.
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#
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# Copyright (c) 2015, Freescale Semiconductor, Inc., (C-Code)
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# Copyright 2016-2021 NXP, (C-Code)
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# All rights reserved.
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#
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# Translated to MicroPython by Robert Hammelrath, 2022
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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import array
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from micropython import const
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# Define the register addresses of WM8960.
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_LINVOL = const(0x0)
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_RINVOL = const(0x1)
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_LOUT1 = const(0x2)
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_ROUT1 = const(0x3)
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_CLOCK1 = const(0x4)
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_DACCTL1 = const(0x5)
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_DACCTL2 = const(0x6)
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_IFACE1 = const(0x7)
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_CLOCK2 = const(0x8)
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_IFACE2 = const(0x9)
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_LDAC = const(0xA)
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_RDAC = const(0xB)
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_RESET = const(0xF)
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_3D = const(0x10)
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_ALC1 = const(0x11)
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_ALC2 = const(0x12)
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_ALC3 = const(0x13)
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_NOISEG = const(0x14)
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_LADC = const(0x15)
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_RADC = const(0x16)
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_ADDCTL1 = const(0x17)
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# Register _ADDCTL2 = const(0x18)
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_POWER1 = const(0x19)
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_POWER2 = const(0x1A)
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_ADDCTL3 = const(0x1B)
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# Register _APOP1 = const(0x1C)
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# Register _APOP2 = const(0x1D)
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_LINPATH = const(0x20)
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_RINPATH = const(0x21)
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_LOUTMIX = const(0x22)
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_ROUTMIX = const(0x25)
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_MONOMIX1 = const(0x26)
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_MONOMIX2 = const(0x27)
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_LOUT2 = const(0x28)
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_ROUT2 = const(0x29)
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_MONO = const(0x2A)
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_INBMIX1 = const(0x2B)
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_INBMIX2 = const(0x2C)
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_BYPASS1 = const(0x2D)
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_BYPASS2 = const(0x2E)
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_POWER3 = const(0x2F)
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_ADDCTL4 = const(0x30)
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_CLASSD1 = const(0x31)
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# Register _CLASSD3 = const(0x33)
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_PLL1 = const(0x34)
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_PLL2 = const(0x35)
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_PLL3 = const(0x36)
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_PLL4 = const(0x37)
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# WM8960 PLLN range */
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_PLL_N_MIN_VALUE = const(6)
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_PLL_N_MAX_VALUE = const(12)
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# WM8960 CLOCK2 bits
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_CLOCK2_BCLK_DIV_MASK = const(0x0F)
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_CLOCK2_DCLK_DIV_MASK = const(0x1C0)
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_CLOCK2_DCLK_DIV_SHIFT = const(0x06)
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# Register _IFACE1
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_IFACE1_FORMAT_MASK = const(0x03)
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_IFACE1_WL_MASK = const(0x0C)
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_IFACE1_WL_SHIFT = const(0x02)
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_IFACE1_LRP_MASK = const(0x10)
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_IFACE1_MS_MASK = const(0x40)
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_IFACE1_DLRSWAP_MASK = const(0x20)
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_IFACE1_ALRSWAP_MASK = const(0x100)
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# Register _POWER1
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_POWER1_VREF_MASK = const(0x40)
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_POWER1_VREF_SHIFT = const(0x06)
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_POWER1_AINL_MASK = const(0x20)
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_POWER1_AINR_MASK = const(0x10)
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_POWER1_ADCL_MASK = const(0x08)
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_POWER1_ADCR_MASK = const(0x0)
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_POWER1_MICB_MASK = const(0x02)
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_POWER1_MICB_SHIFT = const(0x01)
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# Register _POWER2
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_POWER2_DACL_MASK = const(0x100)
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_POWER2_DACR_MASK = const(0x80)
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_POWER2_LOUT1_MASK = const(0x40)
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_POWER2_ROUT1_MASK = const(0x20)
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_POWER2_SPKL_MASK = const(0x10)
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_POWER2_SPKR_MASK = const(0x08)
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_POWER3_LMIC_MASK = const(0x20)
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_POWER3_RMIC_MASK = const(0x10)
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_POWER3_LOMIX_MASK = const(0x08)
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_POWER3_ROMIX_MASK = const(0x04)
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# Register _DACCTL1 .. 3
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_DACCTL1_MONOMIX_MASK = const(0x10)
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_DACCTL1_MONOMIX_SHIFT = const(0x4)
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_DACCTL1_DACMU_MASK = const(0x08)
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_DACCTL1_DEEM_MASK = const(0x06)
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_DACCTL1_DEEM_SHIFT = const(0x01)
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_DACCTL2_DACSMM_MASK = const(0x08)
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_DACCTL2_DACMR_MASK = const(0x04)
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_DACCTL3_ALCSR_MASK = const(0x07)
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# _WM8060_ALC1 .. 3
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_ALC_CHANNEL_MASK = const(0x180)
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_ALC_CHANNEL_SHIFT = const(0x7)
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_ALC_MODE_MASK = const(0x100)
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_ALC_MODE_SHIFT = const(0x8)
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_ALC_GAIN_MASK = const(0x70)
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_ALC_GAIN_SHIFT = const(0x4)
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_ALC_TARGET_MASK = const(0x0F)
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_ALC_ATTACK_MASK = const(0x0F)
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_ALC_DECAY_MASK = const(0xF0)
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_ALC_DECAY_SHIFT = const(4)
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_ALC_HOLD_MASK = const(0xF)
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# Register _NOISEG
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_NOISEG_LEVEL_SHIFT = const(3)
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_I2C_ADDR = const(0x1A)
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# WM8960 maximum volume values
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_MAX_VOLUME_ADC = const(0xFF)
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_MAX_VOLUME_DAC = const(0xFF)
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_MAX_VOLUME_HEADPHONE = const(0x7F)
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_MAX_VOLUME_LINEIN = const(0x3F)
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_MAX_VOLUME_SPEAKER = const(0x7F)
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# Config symbol names
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# Modules
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MODULE_ADC = const(0) # ADC module in WM8960
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MODULE_DAC = const(1) # DAC module in WM8960
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MODULE_VREF = const(2) # VREF module
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MODULE_HEADPHONE = const(3) # Headphone
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MODULE_MIC_BIAS = const(4) # Mic bias
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MODULE_MIC = const(5) # Input Mic
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MODULE_LINE_IN = const(6) # Analog in PGA
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MODULE_LINE_OUT = const(7) # Line out module
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MODULE_SPEAKER = const(8) # Speaker module
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MODULE_OMIX = const(9) # Output mixer
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MODULE_MONO_OUT = const(10) # Mono mix
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# Route
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ROUTE_BYPASS = const(0) # LINEIN->Headphone.
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ROUTE_PLAYBACK = const(1) # I2SIN->DAC->Headphone.
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ROUTE_PLAYBACK_RECORD = const(2) # I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT.
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ROUTE_RECORD = const(5) # LINEIN->ADC->I2SOUT.
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# Input
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INPUT_CLOSED = const(0) # Input device is closed
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INPUT_MIC1 = const(1) # Input as single ended mic, only use L/RINPUT1
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INPUT_MIC2 = const(2) # Input as diff. mic, use L/RINPUT1 and L/RINPUT2
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INPUT_MIC3 = const(3) # Input as diff. mic, use L/RINPUT1 and L/RINPUT3
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INPUT_LINE2 = const(4) # Input as line input, only use L/RINPUT2
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INPUT_LINE3 = const(5) # Input as line input, only use L/RINPUT3
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# ADC sync input
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SYNC_ADC = const(0) # Use ADCLRC pin for ADC sync
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SYNC_DAC = const(1) # used DACLRC pin for ADC sync
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# Protocol type
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BUS_I2S = const(2) # I2S type
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BUS_LEFT_JUSTIFIED = const(1) # Left justified mode
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BUS_RIGHT_JUSTIFIED = const(0) # Right justified mode
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BUS_PCMA = const(3) # PCM A mode
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BUS_PCMB = const(3 | (1 << 4)) # PCM B mode
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# Channel swap
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SWAP_NONE = const(0)
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SWAP_INPUT = const(1)
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SWAP_OUTPUT = const(2)
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# Mute settings
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MUTE_FAST = const(0)
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MUTE_SLOW = const(1)
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# ALC settings
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ALC_OFF = const(0)
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ALC_RIGHT = const(1)
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ALC_LEFT = const(2)
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ALC_STEREO = const(3)
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ALC_MODE = const(0) # ALC mode
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ALC_LIMITER = const(1) # Limiter mode
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# Clock Source
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SYSCLK_MCLK = const(0) # sysclk source from external MCLK
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SYSCLK_PLL = const(1) # sysclk source from internal PLL
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class Regs:
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# register cache of 56 register. Since registers cannot be read back, they are
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# kept in the table for modification
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# fmt: off
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cache = array.array("H", (
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0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000,
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0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000,
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0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000,
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0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000,
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0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050,
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0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000,
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0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002,
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0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9
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))
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# fmt: on
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def __init__(self, i2c, i2c_address=_I2C_ADDR):
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self.value_buffer = bytearray(2)
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self.i2c = i2c
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self.i2c_address = i2c_address
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def __getitem__(self, reg):
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return self.cache[reg]
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def __setitem__(self, reg, value):
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if type(reg) is tuple:
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if type(value) is tuple:
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self[reg[0]] = value[0]
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self[reg[1]] = value[1]
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else:
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self[reg[0]] = value
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self[reg[1]] = value
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else:
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if type(value) is tuple:
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val = (self.cache[reg] & (~value[0] & 0xFFFF)) | value[1]
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else:
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val = value
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self.cache[reg] = val
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self.value_buffer[0] = (reg << 1) | ((val >> 8) & 0x01)
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self.value_buffer[1] = val & 0xFF
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self.i2c.writeto(self.i2c_address, self.value_buffer)
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class WM8960:
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_bit_clock_divider_table = {
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2: 0,
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3: 1,
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4: 2,
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6: 3,
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8: 4,
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11: 5,
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12: 6,
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16: 7,
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22: 8,
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24: 9,
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32: 10,
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44: 11,
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48: 12,
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}
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_dac_divider_table = {
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1.0 * 256: 0b000,
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1.5 * 256: 0b001,
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2 * 256: 0b010,
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3 * 256: 0b011,
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4 * 256: 0b100,
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5.5 * 256: 0b101,
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6 * 256: 0b110,
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}
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_audio_word_length_table = {
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16: 0b00,
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20: 0b01,
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24: 0b10,
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32: 0b11,
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}
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_alc_sample_rate_table = {
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48000: 0,
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44100: 0,
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32000: 1,
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24000: 2,
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22050: 2,
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16000: 3,
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12000: 4,
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11025: 4,
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8000: 5,
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}
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_volume_config_table = {
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MODULE_ADC: (_MAX_VOLUME_ADC, _LADC, 0x100),
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MODULE_DAC: (_MAX_VOLUME_DAC, _LDAC, 0x100),
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MODULE_HEADPHONE: (_MAX_VOLUME_HEADPHONE, _LOUT1, 0x180),
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MODULE_LINE_IN: (_MAX_VOLUME_LINEIN, _LINVOL, 0x140),
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MODULE_SPEAKER: (_MAX_VOLUME_SPEAKER, _LOUT2, 0x180),
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}
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_input_config_table = {
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INPUT_CLOSED: None,
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INPUT_MIC1: (0x138, 0x117),
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INPUT_MIC2: (0x178, 0x117),
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INPUT_MIC3: (0x1B8, 0x117),
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INPUT_LINE2: (0, 0xE),
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INPUT_LINE3: (0, 0x70),
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}
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def __init__(
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self,
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i2c,
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sample_rate=16000,
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bits=16,
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swap=SWAP_NONE,
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route=ROUTE_PLAYBACK_RECORD,
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left_input=INPUT_MIC3,
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right_input=INPUT_MIC2,
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sysclk_source=SYSCLK_MCLK,
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mclk_freq=None,
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primary=False,
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adc_sync=SYNC_DAC,
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protocol=BUS_I2S,
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i2c_address=_I2C_ADDR,
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):
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self.regs = regs = Regs(i2c, i2c_address)
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self.sample_rate = sample_rate
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# check parameter consistency and set the sysclk value
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if sysclk_source == SYSCLK_PLL:
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if sample_rate in (11025, 22050, 44100):
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sysclk = 11289600
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else:
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sysclk = 12288000
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if sysclk < sample_rate * 256:
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sysclk = sample_rate * 256
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if mclk_freq is None:
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mclk_freq = sysclk
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else: # sysclk_source == SYSCLK_MCLK
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if mclk_freq is None:
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mclk_freq = sample_rate * 256
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sysclk = mclk_freq
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regs[_RESET] = 0x00
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# VMID=50K, Enable VREF, AINL, AINR, ADCL and ADCR
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# I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5), ADC (bit 6) are powered on
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regs[_POWER1] = 0xFE
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# Enable DACL, DACR, LOUT1, ROUT1, PLL down, SPKL, SPKR
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regs[_POWER2] = 0x1F8
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# Enable left and right channel input PGA, left and right output mixer
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regs[_POWER3] = 0x3C
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if adc_sync == SYNC_ADC:
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# ADC and DAC use different Frame Clock Pins
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regs[_IFACE2] = 0x00 # ADCLRC 0x00:Input 0x40:output.
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else:
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# ADC and DAC use the same Frame Clock Pin
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regs[_IFACE2] = 0x40 # ADCLRC 0x00:Input 0x40:output.
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self.set_data_route(route)
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self.set_protocol(protocol)
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if sysclk_source == SYSCLK_PLL:
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self.set_internal_pll_config(mclk_freq, sysclk)
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if primary:
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self.set_master_clock(sysclk, sample_rate, bits)
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# set master bit.
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self.regs[_IFACE1] = (0, _IFACE1_MS_MASK)
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self.set_speaker_clock(sysclk)
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# swap channels
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if swap & SWAP_INPUT:
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regs[_IFACE1] = (0, _IFACE1_ALRSWAP_MASK)
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if swap & SWAP_OUTPUT:
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regs[_IFACE1] = (0, _IFACE1_DLRSWAP_MASK)
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self.set_left_input(left_input)
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self.set_right_input(right_input)
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regs[_ADDCTL1] = 0x0C0
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regs[_ADDCTL4] = 0x60 # Set GPIO1 to 0.
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regs[_BYPASS1] = regs[_BYPASS2] = 0x0
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# ADC volume, 0dB
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regs[_LADC, _RADC] = 0x1C3
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# Digital DAC volume, 0dB
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regs[_LDAC, _RDAC] = 0x1FF
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# Headphone volume, LOUT1 and ROUT1, 0dB
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regs[_LOUT1, _ROUT1] = 0x16F
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# speaker volume 6dB
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regs[_LOUT2, _ROUT2] = 0x1FF
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# enable class D output
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regs[_CLASSD1] = 0xF7
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# Unmute DAC.
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regs[_DACCTL1] = 0x0000
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# Input PGA volume 0 dB
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regs[_LINVOL, _RINVOL] = 0x117
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self.config_data_format(sysclk, sample_rate, bits)
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def deinit(self):
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self.set_module(MODULE_ADC, False)
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self.set_module(MODULE_DAC, False)
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self.set_module(MODULE_VREF, False)
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self.set_module(MODULE_LINE_IN, False)
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self.set_module(MODULE_LINE_OUT, False)
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self.set_module(MODULE_SPEAKER, False)
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def set_internal_pll_config(self, input_mclk, output_clk):
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regs = self.regs
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pllF2 = output_clk * 4
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pll_prescale = 0
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sysclk_div = 1
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frac_mode = 0
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# disable PLL power
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regs[_POWER2] = (1, 0)
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regs[_CLOCK1] = (7, 0)
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pllN = pllF2 // input_mclk
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if pllN < _PLL_N_MIN_VALUE:
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input_mclk //= 2
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pll_prescale = 1
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pllN = pllF2 // input_mclk
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if pllN < _PLL_N_MIN_VALUE:
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sysclk_div = 2
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pllF2 *= 2
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pllN = pllF2 // input_mclk
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if (pllN < _PLL_N_MIN_VALUE) or (pllN > _PLL_N_MAX_VALUE):
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raise ValueError("Invalid MCLK vs. sysclk ratio")
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pllK = ((pllF2 % input_mclk) * (1 << 24)) // input_mclk
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if pllK != 0:
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frac_mode = 1
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regs[_PLL1] = (frac_mode << 5) | (pll_prescale << 4) | (pllN & 0x0F)
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regs[_PLL2] = (pllK >> 16) & 0xFF
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regs[_PLL3] = (pllK >> 8) & 0xFF
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regs[_PLL4] = pllK & 0xFF
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# enable PLL power
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regs[_POWER2] = (1, 1)
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regs[_CLOCK1] = (7, ((0 if sysclk_div == 1 else sysclk_div) << 1) | 1)
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def set_master_clock(self, sysclk, sample_rate, bit_width):
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bit_clock_divider = (sysclk * 2) // (sample_rate * bit_width * 2)
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try:
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reg_divider = self._bit_clock_divider_table[bit_clock_divider]
|
|
except:
|
|
raise ValueError("Invalid ratio of sysclk sample rate and bits")
|
|
# configure the master bit clock divider
|
|
self.regs[_CLOCK2] = (_CLOCK2_BCLK_DIV_MASK, reg_divider)
|
|
|
|
def set_speaker_clock(self, sysclk):
|
|
speaker_divider_table = (1.5, 2, 3, 4, 6, 8, 12, 16)
|
|
for val in range(8):
|
|
divider = speaker_divider_table[val]
|
|
f = sysclk / divider
|
|
if 500_000 < f < 1_000_000:
|
|
break
|
|
else:
|
|
val = 7
|
|
self.regs[_CLOCK2] = (
|
|
_CLOCK2_DCLK_DIV_MASK,
|
|
val << _CLOCK2_DCLK_DIV_SHIFT,
|
|
)
|
|
|
|
def set_module(self, module, is_enabled):
|
|
|
|
is_enabled = 1 if is_enabled else 0
|
|
regs = self.regs
|
|
|
|
if module == MODULE_ADC:
|
|
|
|
regs[_POWER1] = (
|
|
_POWER1_ADCL_MASK | _POWER1_ADCR_MASK,
|
|
(_POWER1_ADCL_MASK | _POWER1_ADCR_MASK) * is_enabled,
|
|
)
|
|
|
|
elif module == MODULE_DAC:
|
|
|
|
regs[_POWER2] = (
|
|
_POWER2_DACL_MASK | _POWER2_DACR_MASK,
|
|
(_POWER2_DACL_MASK | _POWER2_DACR_MASK) * is_enabled,
|
|
)
|
|
|
|
elif module == MODULE_VREF:
|
|
|
|
regs[_POWER1] = (
|
|
_POWER1_VREF_MASK,
|
|
(is_enabled << _POWER1_VREF_SHIFT),
|
|
)
|
|
|
|
elif module == MODULE_LINE_IN:
|
|
|
|
regs[_POWER1] = (
|
|
_POWER1_AINL_MASK | _POWER1_AINR_MASK,
|
|
(_POWER1_AINL_MASK | _POWER1_AINR_MASK) * is_enabled,
|
|
)
|
|
regs[_POWER3] = (
|
|
_POWER3_LMIC_MASK | _POWER3_RMIC_MASK,
|
|
(_POWER3_LMIC_MASK | _POWER3_RMIC_MASK) * is_enabled,
|
|
)
|
|
|
|
elif module == MODULE_LINE_OUT:
|
|
|
|
regs[_POWER2] = (
|
|
_POWER2_LOUT1_MASK | _POWER2_ROUT1_MASK,
|
|
(_POWER2_LOUT1_MASK | _POWER2_ROUT1_MASK) * is_enabled,
|
|
)
|
|
|
|
elif module == MODULE_MIC_BIAS:
|
|
|
|
regs[_POWER1] = (
|
|
_POWER1_MICB_MASK,
|
|
(is_enabled << _POWER1_MICB_SHIFT),
|
|
)
|
|
|
|
elif module == MODULE_SPEAKER:
|
|
|
|
regs[_POWER2] = (
|
|
_POWER2_SPKL_MASK | _POWER2_SPKR_MASK,
|
|
(_POWER2_SPKL_MASK | _POWER2_SPKR_MASK) * is_enabled,
|
|
)
|
|
regs[_CLASSD1] = 0xF7
|
|
|
|
elif module == MODULE_OMIX:
|
|
|
|
regs[_POWER3] = (
|
|
_POWER3_LOMIX_MASK | _POWER3_ROMIX_MASK,
|
|
(_POWER3_LOMIX_MASK | _POWER3_ROMIX_MASK) * is_enabled,
|
|
)
|
|
|
|
elif module == MODULE_MONO_OUT:
|
|
|
|
regs[_MONOMIX1] = regs[_MONOMIX2] = is_enabled << 7
|
|
regs[_MONO] = is_enabled << 6
|
|
|
|
else:
|
|
raise ValueError("Invalid module")
|
|
|
|
def enable_module(self, module):
|
|
self.set_module(module, True)
|
|
|
|
def disable_module(self, module):
|
|
self.set_module(module, False)
|
|
|
|
def set_data_route(self, route):
|
|
regs = self.regs
|
|
if route == ROUTE_BYPASS:
|
|
# Bypass means from line-in to HP
|
|
# Left LINPUT3 to left output mixer, LINPUT3 left output mixer volume = 0dB
|
|
# Right RINPUT3 to right output mixer, RINPUT3 right output mixer volume = 0dB
|
|
regs[_LOUTMIX, _ROUTMIX] = 0x80
|
|
|
|
elif route == ROUTE_PLAYBACK:
|
|
# Data route I2S_IN-> DAC-> HP
|
|
#
|
|
# Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB
|
|
# Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB
|
|
regs[_LOUTMIX, _ROUTMIX] = 0x100
|
|
regs[_POWER3] = 0x0C
|
|
# Set power for DAC
|
|
self.set_module(MODULE_DAC, True)
|
|
self.set_module(MODULE_OMIX, True)
|
|
self.set_module(MODULE_LINE_OUT, True)
|
|
|
|
elif route == ROUTE_PLAYBACK_RECORD:
|
|
#
|
|
# Left DAC to left output mixer, LINPUT3 left output mixer volume = 0dB
|
|
# Right DAC to right output mixer, RINPUT3 right output mixer volume = 0dB
|
|
regs[_LOUTMIX, _ROUTMIX] = 0x100
|
|
regs[_POWER3] = 0x3C
|
|
self.set_module(MODULE_DAC, True)
|
|
self.set_module(MODULE_ADC, True)
|
|
self.set_module(MODULE_LINE_IN, True)
|
|
self.set_module(MODULE_OMIX, True)
|
|
self.set_module(MODULE_LINE_OUT, True)
|
|
|
|
elif route == ROUTE_RECORD:
|
|
# LINE_IN->ADC->I2S_OUT
|
|
# Left and right input boost, LIN3BOOST and RIN3BOOST = 0dB
|
|
regs[_POWER3] = 0x30
|
|
# Power up ADC and AIN
|
|
self.set_module(MODULE_LINE_IN, True)
|
|
self.set_module(MODULE_ADC, True)
|
|
|
|
else:
|
|
raise ValueError("Invalid route")
|
|
|
|
def set_left_input(self, input):
|
|
if not input in self._input_config_table.keys():
|
|
raise ValueError("Invalid input")
|
|
|
|
input = self._input_config_table[input]
|
|
|
|
regs = self.regs
|
|
if input is None:
|
|
regs[_POWER1] = (_POWER1_AINL_MASK | _POWER1_ADCL_MASK, 0)
|
|
elif input[0] == 0:
|
|
regs[_POWER1] = (0, _POWER1_AINL_MASK | _POWER1_ADCL_MASK)
|
|
regs[_INBMIX1] = input
|
|
else:
|
|
regs[_POWER1] = (0, _POWER1_AINL_MASK | _POWER1_ADCL_MASK | _POWER1_MICB_MASK)
|
|
regs[_LINPATH] = input[0]
|
|
regs[_LINVOL] = input[1]
|
|
|
|
def set_right_input(self, input):
|
|
if not input in self._input_config_table.keys():
|
|
raise ValueError("Invalid input name")
|
|
|
|
input = self._input_config_table[input]
|
|
|
|
regs = self.regs
|
|
if input is None:
|
|
regs[_POWER1] = (_POWER1_AINR_MASK | _POWER1_ADCR_MASK, 0)
|
|
elif input[0] == 0:
|
|
regs[_POWER1] = (0, _POWER1_AINL_MASK | _POWER1_ADCR_MASK)
|
|
regs[_INBMIX2] = input
|
|
else:
|
|
regs[_POWER1] = (0, _POWER1_AINR_MASK | _POWER1_ADCR_MASK | _POWER1_MICB_MASK)
|
|
regs[_RINPATH] = input[0]
|
|
regs[_RINVOL] = input[1]
|
|
|
|
def set_protocol(self, protocol):
|
|
self.regs[_IFACE1] = (
|
|
_IFACE1_FORMAT_MASK | _IFACE1_LRP_MASK,
|
|
protocol,
|
|
)
|
|
|
|
def config_data_format(self, sysclk, sample_rate, bits):
|
|
# Compute sample rate divider, dac and adc are the same sample rate
|
|
try:
|
|
divider = self._dac_divider_table[sysclk // sample_rate]
|
|
wl = self._audio_word_length_table[bits]
|
|
except:
|
|
raise ValueError("Invalid ratio sysclk/sample_rate or invalid bit length")
|
|
|
|
self.regs[_CLOCK1] = (0x1F8, divider << 6 | divider << 3)
|
|
self.regs[_IFACE1] = (_IFACE1_WL_MASK, wl << _IFACE1_WL_SHIFT)
|
|
|
|
def volume(self, module, volume_l=None, volume_r=None):
|
|
if not module in self._volume_config_table.keys():
|
|
raise ValueError("Invalid module")
|
|
|
|
if volume_l is None: # get volume
|
|
vol_max, regnum, _ = self._volume_config_table[module]
|
|
return (
|
|
int((self.regs[regnum] & vol_max) * 100 / vol_max + 0.5),
|
|
int((self.regs[regnum + 1] & vol_max) * 100 / vol_max + 0.5),
|
|
)
|
|
else: # set volume
|
|
if volume_r is None:
|
|
volume_r = volume_l
|
|
|
|
if not ((0 <= volume_l <= 100) and (0 <= volume_r <= 100)):
|
|
raise ValueError("Invalid value for volume")
|
|
elif not module in self._volume_config_table.keys():
|
|
raise ValueError("Invalid module")
|
|
|
|
vol_max, regnum, flags = self._volume_config_table[module]
|
|
self.regs[regnum] = int(volume_l * vol_max / 100 + 0.5) | flags
|
|
self.regs[regnum + 1] = int(volume_r * vol_max / 100 + 0.5) | flags
|
|
|
|
def mute(self, enable, soft=True, ramp=MUTE_FAST):
|
|
enable = _DACCTL1_DACMU_MASK if enable else 0
|
|
soft = _DACCTL2_DACSMM_MASK if soft else 0
|
|
ramp = _DACCTL2_DACMR_MASK if ramp == MUTE_SLOW else 0
|
|
self.regs[_DACCTL1] = (_DACCTL1_DACMU_MASK, enable)
|
|
self.regs[_DACCTL2] = (
|
|
_DACCTL2_DACSMM_MASK | _DACCTL2_DACMR_MASK,
|
|
soft | ramp,
|
|
)
|
|
|
|
def expand_3d(self, depth=0):
|
|
depth &= 0x0F
|
|
cutoff = 0 if self.sample_rate >= 32000 else 0b1100000
|
|
self.regs[_3D] = cutoff | depth << 1 | (1 if depth > 0 else 0)
|
|
|
|
def mono(self, enable):
|
|
enable = 1 if enable else 0
|
|
self.regs[_DACCTL1] = (
|
|
_DACCTL1_MONOMIX_MASK,
|
|
enable << _DACCTL1_MONOMIX_SHIFT,
|
|
)
|
|
|
|
def alc_mode(self, channel, mode=ALC_MODE):
|
|
if mode != ALC_MODE:
|
|
mode = ALC_LIMITER
|
|
channel &= 3
|
|
self.regs[_ALC1] = (
|
|
_ALC_CHANNEL_MASK,
|
|
channel << _ALC_CHANNEL_SHIFT,
|
|
)
|
|
self.regs[_ALC3] = (_ALC_MODE_MASK, mode << _ALC_MODE_SHIFT)
|
|
try:
|
|
rate = _alc_sample_rate_table[self.sample_rate]
|
|
except:
|
|
rate = 0
|
|
self.regs[_ADDCTL3] = (_DACCTL3_ALCSR_MASK, rate)
|
|
|
|
def alc_gain(self, target=-12, max_gain=30, min_gain=-17.25, noise_gate=-78):
|
|
def limit(value, minval, maxval):
|
|
value = int(value)
|
|
if value < minval:
|
|
value = minval
|
|
if value > maxval:
|
|
value = maxval
|
|
return value
|
|
|
|
target = limit((16 + (target * 2) // 3), 0, 15)
|
|
max_gain = limit((max_gain + 12) // 6, 0, 7)
|
|
min_gain = limit((min_gain * 4 + 69) // 24, 0, 7)
|
|
noise_gate = limit((noise_gate * 2 + 153) // 3, -1, 31)
|
|
self.regs[_ALC1] = (
|
|
_ALC_GAIN_MASK | _ALC_TARGET_MASK,
|
|
(max_gain << _ALC_GAIN_SHIFT) | target,
|
|
)
|
|
self.regs[_ALC2] = (_ALC_GAIN_MASK, (min_gain << _ALC_GAIN_SHIFT))
|
|
if noise_gate >= 0:
|
|
self.regs[_NOISEG] = noise_gate << _NOISEG_LEVEL_SHIFT | 1
|
|
else:
|
|
self.regs[_NOISEG] = 0
|
|
|
|
def alc_time(self, attack=24, decay=192, hold=0):
|
|
def logb(value, limit):
|
|
value = int(value)
|
|
lb = 0
|
|
while value > 1:
|
|
value >>= 1
|
|
lb += 1
|
|
if lb > limit:
|
|
lb = limit
|
|
return lb
|
|
|
|
attack = logb(attack / 6, 7)
|
|
decay = logb(decay / 24, 7)
|
|
hold = logb((hold * 3) / 8, 15)
|
|
self.regs[_ALC2] = (_ALC_HOLD_MASK, hold)
|
|
self.regs[_ALC3] = (
|
|
_ALC_DECAY_MASK | _ALC_ATTACK_MASK,
|
|
(decay << _ALC_DECAY_SHIFT) | attack,
|
|
)
|
|
|
|
def deemphasis(self, enable):
|
|
deem_table = (32000, 44100, 48000)
|
|
enable = not not enable
|
|
if enable and self.sample_rate in deem_table:
|
|
val = deem_table.index(self.sample_rate) + 1
|
|
else:
|
|
val = 0
|
|
self.regs[_DACCTL1] = (_DACCTL1_DEEM_MASK, val << _DACCTL1_DEEM_SHIFT)
|