kopia lustrzana https://github.com/micropython/micropython
308 wiersze
9.3 KiB
C
308 wiersze
9.3 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 NXP
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "board.h"
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/* SDK drivers */
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#include "fsl_ctimer.h"
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#include "drv_pwm.h"
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static int drv_pwm_current_period_channel(drv_pwm_t *pwm) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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uint32_t mcr = ct->MCR;
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for (uint8_t i = 0; i < 4; i++) {
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if (mcr & (1U << (3 * i + CTIMER_MCR_MR0R_SHIFT))) {
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return i;
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}
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}
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return -1;
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}
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static int drv_pwm_first_free_channel(drv_pwm_t *pwm) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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int pc = drv_pwm_current_period_channel(pwm);
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uint32_t pwmc = ct->PWMC;
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for (uint8_t i = 0; i < 4; i++) {
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if (pwmc & (1U << i)) {
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/* Skip this channel if there's an active PWM output */
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continue;
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}
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if (i == pc) {
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/* Skip this channel if this channel is the current period channel */
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continue;
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}
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return i;
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}
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/* There are no free channels left. */
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return -1;
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}
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int drv_pwm_init(drv_pwm_t *pwm, uint8_t id, uint8_t channel, uint32_t freq, bool inverted) {
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pwm->id = id;
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pwm->channel = channel;
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pwm->instance = MCX_BoardGetCT32Instance(id);
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if (pwm->instance == NULL) {
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return -EINVAL;
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}
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pwm->input_freq = MCX_BoardConfigureCT32Clock(id);
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pwm->inverted = inverted;
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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if ((ct->TCR & CTIMER_TCR_CEN_MASK) == 0U) {
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/* There's two conditions for a all-zero TCR: either a reset condition or timer is stopped. */
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/* In either case, we need to initialize the timer instance (AHB RST CTRL). */
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/* TODO: Do not use SDK functions */
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ctimer_config_t ct_cfg = {
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.mode = kCTIMER_TimerMode,
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.prescale = 1U,
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};
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/* Frequency: 150MHz max., we got 32bit counters, we can take that. */
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/* Approx. maximum period: 28.6 seconds. */
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CTIMER_Init(ct, &ct_cfg);
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/* Current timer is not running, we are the first channel being configured. */
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ct->TC = 0U; /* Reset counter */
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ct->PC = 0U; /* Reset prescaler counter */
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ct->PR = 0U; /* Prescaler, divide by 1 to get best resolution */
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ct->MCR = 0U; /* Reset interrupt and reset condition */
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ct->EMR = 0U; /* Do nothing on match event and output 0 as default state */
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ct->PWMC = 0U; /* Disable all PWM channels, outputs will be controlled by EMn */
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/* Here, we have a favoritism of using channel 3 as period channel, unless channel 3 is used for output */
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if (channel != 3) {
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ct->MR[3] = pwm->input_freq / freq;
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ct->MCR |= CTIMER_MCR_MR3R_MASK;
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} else {
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/* Use channel 2 as period channel. */
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ct->MR[2] = pwm->input_freq / freq;
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ct->MCR |= CTIMER_MCR_MR2R_MASK;
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}
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/* Start counter */
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ct->TCR |= CTIMER_TCR_CEN_MASK;
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} else {
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/*
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* Due to the nature of the CTimer, one of the 4 match channels is needed for period control (frequency)
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* To find out which one is the current period channel, check the MRxR bit for each match output.
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* If we are configuring the same match being used as periodic channel, configure the next free match as period
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* then current channel can be re-used. If all 4 channels are in use then the function will fail with an errno.
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*/
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/* The timer is running, check whether we need to re-locate the period channel */
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int p_channel = drv_pwm_current_period_channel(pwm);
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if (p_channel < 0) {
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return -EINVAL;
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}
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if (p_channel == channel) {
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/* We need to re-locate the period channel */
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int f_channel = drv_pwm_first_free_channel(pwm);
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if (f_channel < 0) {
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/* There's no free channel, bail out. */
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return -EBUSY;
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}
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/* Transfer the period channel to first free channel */
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/* Step 1: Copy current period to first free channel */
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ct->MR[f_channel] = ct->MR[p_channel];
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/* Step 2: Enable reset for new period channel */
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/* Note: it's safe doing it here since both old and new channel MRs contains same value */
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ct->MCR |= (CTIMER_MCR_MR0R_MASK << (3 * f_channel));
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/* Step 3: Disable reset for old period channel */
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ct->MCR &= ~(CTIMER_MCR_MR0R_MASK << (3 * p_channel));
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/* The old period channel is now available for PWM output */
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p_channel = f_channel;
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}
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if (drv_pwm_freq_set(pwm, freq) < 0) {
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return -EINVAL;
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}
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}
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return 0;
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}
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int drv_pwm_deinit(drv_pwm_t *pwm) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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/* Disable PWM output for channel, now the output is controlled by EMR */
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ct->PWMC &= ~(CTIMER_PWMC_PWMEN0_MASK << pwm->channel);
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/* Check whether there's still enabled channels */
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if ((ct->PWMC & 0x0FU) == 0) {
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/* Stop counter if this is the last. */
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ct->TCR &= ~CTIMER_TCR_CEN_MASK;
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}
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return 0;
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}
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int drv_pwm_start(drv_pwm_t *pwm) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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ct->PWMC |= (1U << pwm->channel);
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return 0;
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}
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int drv_pwm_stop(drv_pwm_t *pwm) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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ct->PWMC &= ~(1U << pwm->channel);
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return 0;
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}
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int drv_pwm_freq_set(drv_pwm_t *pwm, uint32_t freq) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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int p_channel = drv_pwm_current_period_channel(pwm);
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if (p_channel < 0) {
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return -EINVAL;
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}
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/* Store new values in shadow registers */
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ct->MSR[p_channel] = pwm->input_freq / freq;
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/* Enable period channel interrupt to check a reload event occurs.
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* Since interrupts are not configured from NVIC, so no ISR will occur.
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* Check IR[MRnINT] for reload point.
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*/
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uint32_t mcr_mask = (CTIMER_MCR_MR0RL_MASK << p_channel) | (CTIMER_MCR_MR0I_MASK << (3 * p_channel));
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for (uint8_t i = 0; i < 4; i++) {
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if (ct->PWMC & (1U << i)) {
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/* Channel PWM output is enabled, calculate new values and store into shadow registers */
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uint32_t new_mr = ct->MR[i] * ct->MSR[p_channel] / ct->MR[p_channel];
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ct->MSR[i] = new_mr;
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/* Update MRnRL map */
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mcr_mask |= CTIMER_MCR_MR0RL_MASK << i;
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}
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}
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/* Reload MRs on next counter reset, enable reload MR interrupt */
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ct->MCR |= mcr_mask;
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while ((ct->IR & (CTIMER_IR_MR0INT_MASK << p_channel)) == 0U) {
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/* -- */
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}
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/* Disable reload channel interrupt and MSR synchronization */
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ct->MCR &= ~mcr_mask;
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/* Clear interrupt flags. */
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ct->IR |= (CTIMER_IR_MR0INT_MASK << p_channel);
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return 0;
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}
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int drv_pwm_freq_get(drv_pwm_t *pwm, uint32_t *freq) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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int p_channel = drv_pwm_current_period_channel(pwm);
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if (p_channel < 0) {
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return -1;
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}
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*freq = pwm->input_freq / ct->MR[p_channel];
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return 0;
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}
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int drv_pwm_duty_set(drv_pwm_t *pwm, uint16_t duty_u16) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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int p_channel = drv_pwm_current_period_channel(pwm);
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if (p_channel < 0) {
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return -1;
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}
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/* To avoid overflow, use 64bit values here. */
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uint64_t period = ct->MR[p_channel];
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if (pwm->inverted) {
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ct->MSR[pwm->channel] = period * duty_u16 / 65535;
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} else {
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ct->MSR[pwm->channel] = period - (period * duty_u16 / 65535);
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}
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/* Reload MRn on the next cycle */
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ct->MCR |= (CTIMER_MCR_MR0RL_MASK << pwm->channel);
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/* Wait for new duty cycle loaded into the MRn */
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while (ct->MR[pwm->channel] != ct->MSR[pwm->channel]) {
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/* -- */
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}
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/* Disable shadow register updates */
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ct->MCR &= ~(CTIMER_MCR_MR0RL_MASK << pwm->channel);
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return 0;
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}
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int drv_pwm_duty_get(drv_pwm_t *pwm, uint16_t *duty_u16) {
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CTIMER_Type *ct = (CTIMER_Type *)pwm->instance;
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int p_channel = drv_pwm_current_period_channel(pwm);
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if (p_channel < 0) {
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return -1;
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}
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uint32_t period = ct->MR[p_channel];
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/* To avoid overflow, use 64bit values here. */
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uint64_t duty = ct->MR[pwm->channel];
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*duty_u16 = duty * 65535 / period;
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return 0;
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}
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