kopia lustrzana https://github.com/micropython/micropython
645 wiersze
20 KiB
C
645 wiersze
20 KiB
C
/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2016-2018 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "drivers/memory/spiflash.h"
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#include "drivers/memory/external_flash_device.h"
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#define USE_WR_DELAY (1)
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#define CMD_WRSR (0x01)
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#define CMD_WRCR (0x31)
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#define CMD_WRITE (0x02)
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#define CMD_READ (0x03)
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#define CMD_RDSR (0x05)
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#define CMD_WREN (0x06)
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#define CMD_SEC_ERASE (0x20)
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#define CMD_RDCR (0x35)
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#define CMD_RD_DEVID (0x9f)
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#define CMD_CHIP_ERASE (0xc7)
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#define CMD_C4READ (0xeb)
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// 32 bit addressing commands
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#define CMD_WRITE_32 (0x12)
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#define CMD_READ_32 (0x13)
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#define CMD_SEC_ERASE_32 (0x21)
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#define CMD_C4READ_32 (0xec)
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#define WAIT_SR_TIMEOUT (1000000)
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#define PAGE_SIZE (256) // maximum bytes we can write in one SPI transfer
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#define SECTOR_SIZE MP_SPIFLASH_ERASE_BLOCK_SIZE
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#if MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES
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#ifndef MICROPY_HW_SPIFLASH_DEVICES
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#if !MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES
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#warning SPIFLASH size undefined, should set MICROPY_HW_SPIFLASH_DEVICES or MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES
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#endif
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#define MICROPY_HW_SPIFLASH_DEVICES
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#endif
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#endif
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#if !BUILDING_MBOOT
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#define diag_printf(...) mp_printf(MICROPY_ERROR_PRINTER, __VA_ARGS__)
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#else
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#define diag_printf(...)
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#endif
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// List of all possible flash devices used by device.
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// MICROPY_HW_SPIFLASH_DEVICES can be set to a comma separated list in mpconfigboard.h
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static const external_flash_device possible_devices[] = {
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MICROPY_HW_SPIFLASH_DEVICES
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};
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#define EXTERNAL_FLASH_DEVICE_COUNT MP_ARRAY_SIZE(possible_devices)
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static external_flash_device generic_config = GENERIC;
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static void mp_spiflash_acquire_bus(mp_spiflash_t *self) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
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c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_ACQUIRE);
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}
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}
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static void mp_spiflash_release_bus(mp_spiflash_t *self) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_QSPI) {
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c->bus.u_qspi.proto->ioctl(c->bus.u_qspi.data, MP_QSPI_IOCTL_BUS_RELEASE);
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}
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}
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static int mp_spiflash_write_cmd_data(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t data) {
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int ret = 0;
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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// Note: len/data are unused for standard SPI
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mp_hal_pin_write(c->bus.u_spi.cs, 0);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
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mp_hal_pin_write(c->bus.u_spi.cs, 1);
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} else {
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ret = c->bus.u_qspi.proto->write_cmd_data(c->bus.u_qspi.data, cmd, len, data);
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}
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return ret;
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}
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static int mp_spiflash_transfer_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src, uint8_t *dest, uint8_t mode) {
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int ret = 0;
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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uint8_t buf[5] = {cmd, 0};
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uint8_t buff_len = 1 + mp_spi_set_addr_buff(&buf[1], addr);
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mp_hal_pin_write(c->bus.u_spi.cs, 0);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, buff_len, buf, NULL);
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if (len && (src != NULL)) {
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, src, NULL);
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} else if (len && (dest != NULL)) {
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, dest, dest);
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}
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mp_hal_pin_write(c->bus.u_spi.cs, 1);
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} else {
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if (dest != NULL) {
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ret = c->bus.u_qspi.proto->read_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, dest, mode);
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} else {
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ret = c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src);
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}
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}
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return ret;
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}
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static int mp_spiflash_read_cmd(mp_spiflash_t *self, uint8_t cmd, size_t len, uint32_t *dest) {
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const mp_spiflash_config_t *c = self->config;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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mp_hal_pin_write(c->bus.u_spi.cs, 0);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, 1, &cmd, NULL);
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c->bus.u_spi.proto->transfer(c->bus.u_spi.data, len, (void *)dest, (void *)dest);
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mp_hal_pin_write(c->bus.u_spi.cs, 1);
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return 0;
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} else {
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return c->bus.u_qspi.proto->read_cmd(c->bus.u_qspi.data, cmd, len, dest);
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}
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}
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static int mp_spiflash_read_data(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
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const mp_spiflash_config_t *c = self->config;
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uint8_t cmd;
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uint8_t mode;
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if (c->bus_kind == MP_SPIFLASH_BUS_SPI) {
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cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_READ_32 : CMD_READ;
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mode = MP_QSPI_TRANSFER_CMD_ADDR_DATA;
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} else {
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cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_C4READ_32 : CMD_C4READ;
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mode = MP_QSPI_TRANSFER_CMD_QADDR_QDATA;
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}
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return mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, NULL, dest, mode);
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}
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static int mp_spiflash_write_cmd(mp_spiflash_t *self, uint8_t cmd) {
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return mp_spiflash_write_cmd_data(self, cmd, 0, 0);
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}
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static int mp_spiflash_wait_sr(mp_spiflash_t *self, uint8_t mask, uint8_t val, uint32_t timeout) {
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do {
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uint32_t sr;
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int ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
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if (ret != 0) {
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return ret;
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}
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if ((sr & mask) == val) {
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return 0; // success
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}
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} while (timeout--);
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return -MP_ETIMEDOUT;
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}
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static int mp_spiflash_wait_wel1(mp_spiflash_t *self) {
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return mp_spiflash_wait_sr(self, 2, 2, WAIT_SR_TIMEOUT);
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}
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static int mp_spiflash_wait_wip0(mp_spiflash_t *self) {
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return mp_spiflash_wait_sr(self, 1, 0, WAIT_SR_TIMEOUT);
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}
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static inline void mp_spiflash_deepsleep_internal(mp_spiflash_t *self, int value) {
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mp_spiflash_write_cmd(self, value ? 0xb9 : 0xab); // sleep/wake
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}
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int mp_spiflash_init(mp_spiflash_t *self) {
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int ret = 0;
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self->flags = 0;
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if (self->config->bus_kind == MP_SPIFLASH_BUS_SPI) {
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mp_hal_pin_write(self->config->bus.u_spi.cs, 1);
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mp_hal_pin_output(self->config->bus.u_spi.cs);
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self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT);
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} else {
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self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT);
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}
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mp_spiflash_acquire_bus(self);
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// Ensure SPI flash is out of sleep mode
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mp_spiflash_deepsleep_internal(self, 0);
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#if defined(CHECK_DEVID)
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// Validate device id
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uint32_t devid;
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ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid);
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if (ret != 0 || devid != CHECK_DEVID) {
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mp_spiflash_release_bus(self);
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return -2;
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}
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#endif
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// Start with generic configuration, update with exact if found.
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self->device = &generic_config;
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uint8_t jedec_ids[3];
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ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, (uint32_t *)jedec_ids);
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if (ret != 0) {
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mp_spiflash_release_bus(self);
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return -2;
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}
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for (uint8_t i = 0; i < EXTERNAL_FLASH_DEVICE_COUNT; i++) {
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const external_flash_device *possible_device = &possible_devices[i];
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if (jedec_ids[0] == possible_device->manufacturer_id &&
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jedec_ids[1] == possible_device->memory_type &&
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jedec_ids[2] == possible_device->capacity) {
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self->device = possible_device;
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break;
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}
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}
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// If the flash device is not known, try to autodetect suitable settings.
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if (self->device == &generic_config) {
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if (jedec_ids[0] == 0xc2) { // Macronix devices
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generic_config.quad_enable_bit_mask = 0x04;
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generic_config.single_status_byte = true;
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}
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#if MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES
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generic_config.total_size = MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES;
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#else
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diag_printf("Set MICROPY_HW_SPIFLASH_DEVICES or MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES");
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diag_printf("jedec ids: 0x%x 0x%x 0x%x\n", jedec_ids[0], jedec_ids[1], jedec_ids[2]);
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#endif
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}
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if (self->config->bus_kind == MP_SPIFLASH_BUS_QSPI) {
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// Set quad enable (QE) bit.
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uint32_t sr = 0, cr = 0;
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ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
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if (ret == 0 && self->device->single_status_byte) {
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// QE bit is in status byte 1
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if ((sr & self->device->quad_enable_bit_mask) == 0) {
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mp_spiflash_write_cmd(self, CMD_WREN);
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sr |= self->device->quad_enable_bit_mask;
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mp_spiflash_write_cmd_data(self, CMD_WRSR, 1, sr);
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}
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// Verify it's written correctly
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ret = mp_spiflash_read_cmd(self, CMD_RDSR, 1, &sr);
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if (ret == 0 && (sr & self->device->quad_enable_bit_mask) == 0) {
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// QE bit could not be set
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ret = -1;
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}
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}
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if (ret == 0 && (!self->device->single_status_byte)) {
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// QE bit is in command register / status byte 2
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ret = mp_spiflash_read_cmd(self, CMD_RDCR, 1, &cr);
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if ((cr & self->device->quad_enable_bit_mask) == 0) {
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mp_spiflash_write_cmd(self, CMD_WREN);
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cr |= self->device->quad_enable_bit_mask;
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if (self->device->write_status_register_split) {
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// Some devices have a separate command to write CR
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mp_spiflash_write_cmd_data(self, CMD_WRCR, 1, cr);
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} else {
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// Other devices expect both SR and CR to be written in one operation
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uint32_t data = (sr & 0xff) | (cr & 0xff) << 8;
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mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data);
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}
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}
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// Verify it's written correctly
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ret = mp_spiflash_read_cmd(self, CMD_RDCR, 1, &cr);
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if (ret == 0 && (cr & self->device->quad_enable_bit_mask) == 0) {
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// QE bit could not be set
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ret = -1;
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}
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}
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}
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mp_spiflash_release_bus(self);
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return ret;
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}
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void mp_spiflash_deepsleep(mp_spiflash_t *self, int value) {
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if (value) {
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mp_spiflash_acquire_bus(self);
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}
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mp_spiflash_deepsleep_internal(self, value);
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if (!value) {
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mp_spiflash_release_bus(self);
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}
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}
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static int mp_spiflash_erase_block_internal(mp_spiflash_t *self, uint32_t addr) {
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int ret = 0;
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// enable writes
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ret = mp_spiflash_write_cmd(self, CMD_WREN);
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if (ret != 0) {
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return ret;
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}
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// wait WEL=1
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ret = mp_spiflash_wait_wel1(self);
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if (ret != 0) {
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return ret;
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}
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// erase the sector
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uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_SEC_ERASE_32 : CMD_SEC_ERASE;
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ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, 0, NULL, NULL, 0);
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if (ret != 0) {
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return ret;
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}
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// wait WIP=0
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return mp_spiflash_wait_wip0(self);
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}
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static int mp_spiflash_write_page(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
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int ret = 0;
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// enable writes
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ret = mp_spiflash_write_cmd(self, CMD_WREN);
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if (ret != 0) {
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return ret;
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}
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// wait WEL=1
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ret = mp_spiflash_wait_wel1(self);
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if (ret != 0) {
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return ret;
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}
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// write the page
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uint8_t cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? CMD_WRITE_32 : CMD_WRITE;
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ret = mp_spiflash_transfer_cmd_addr_data(self, cmd, addr, len, src, NULL, 0);
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if (ret != 0) {
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return ret;
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}
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// wait WIP=0
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return mp_spiflash_wait_wip0(self);
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}
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/******************************************************************************/
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// Interface functions that go direct to the SPI flash device
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int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr) {
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mp_spiflash_acquire_bus(self);
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int ret = mp_spiflash_erase_block_internal(self, addr);
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mp_spiflash_release_bus(self);
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return ret;
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}
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int mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
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if (len == 0) {
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return 0;
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}
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mp_spiflash_acquire_bus(self);
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int ret = mp_spiflash_read_data(self, addr, len, dest);
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mp_spiflash_release_bus(self);
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return ret;
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}
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int mp_spiflash_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
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mp_spiflash_acquire_bus(self);
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int ret = 0;
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uint32_t offset = addr & (PAGE_SIZE - 1);
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while (len) {
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size_t rest = PAGE_SIZE - offset;
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if (rest > len) {
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rest = len;
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}
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ret = mp_spiflash_write_page(self, addr, rest, src);
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if (ret != 0) {
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break;
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}
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len -= rest;
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addr += rest;
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src += rest;
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offset = 0;
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}
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mp_spiflash_release_bus(self);
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return ret;
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}
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/******************************************************************************/
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// Interface functions that use the cache
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#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
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int mp_spiflash_cached_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest) {
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if (len == 0) {
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return 0;
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}
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mp_spiflash_acquire_bus(self);
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mp_spiflash_cache_t *cache = self->config->cache;
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if (cache->user == self && cache->block != 0xffffffff) {
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uint32_t bis = addr / SECTOR_SIZE;
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uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
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if (bis <= cache->block && cache->block <= bie) {
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// Read straddles current buffer
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size_t rest = 0;
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if (bis < cache->block) {
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// Read direct from flash for first part
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rest = cache->block * SECTOR_SIZE - addr;
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int ret = mp_spiflash_read_data(self, addr, rest, dest);
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if (ret != 0) {
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mp_spiflash_release_bus(self);
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return ret;
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}
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len -= rest;
|
|
dest += rest;
|
|
addr += rest;
|
|
}
|
|
uint32_t offset = addr & (SECTOR_SIZE - 1);
|
|
rest = SECTOR_SIZE - offset;
|
|
if (rest > len) {
|
|
rest = len;
|
|
}
|
|
memcpy(dest, &cache->buf[offset], rest);
|
|
len -= rest;
|
|
if (len == 0) {
|
|
mp_spiflash_release_bus(self);
|
|
return 0;
|
|
}
|
|
dest += rest;
|
|
addr += rest;
|
|
}
|
|
}
|
|
// Read rest direct from flash
|
|
int ret = mp_spiflash_read_data(self, addr, len, dest);
|
|
mp_spiflash_release_bus(self);
|
|
return ret;
|
|
}
|
|
|
|
static int mp_spiflash_cache_flush_internal(mp_spiflash_t *self) {
|
|
#if USE_WR_DELAY
|
|
if (!(self->flags & 1)) {
|
|
return 0;
|
|
}
|
|
|
|
self->flags &= ~1;
|
|
|
|
mp_spiflash_cache_t *cache = self->config->cache;
|
|
|
|
// Erase sector
|
|
int ret = mp_spiflash_erase_block_internal(self, cache->block * SECTOR_SIZE);
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
|
|
// Write
|
|
for (int i = 0; i < 16; i += 1) {
|
|
uint32_t addr = cache->block * SECTOR_SIZE + i * PAGE_SIZE;
|
|
int ret = mp_spiflash_write_page(self, addr, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
int mp_spiflash_cache_flush(mp_spiflash_t *self) {
|
|
mp_spiflash_acquire_bus(self);
|
|
int ret = mp_spiflash_cache_flush_internal(self);
|
|
mp_spiflash_release_bus(self);
|
|
return ret;
|
|
}
|
|
|
|
static int mp_spiflash_cached_write_part(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
|
|
// Align to 4096 sector
|
|
uint32_t offset = addr & 0xfff;
|
|
uint32_t sec = addr >> 12;
|
|
addr = sec << 12;
|
|
|
|
// Restriction for now, so we don't need to erase multiple pages
|
|
if (offset + len > SECTOR_SIZE) {
|
|
diag_printf("mp_spiflash_cached_write_part: len is too large\n");
|
|
return -MP_EIO;
|
|
}
|
|
|
|
mp_spiflash_cache_t *cache = self->config->cache;
|
|
|
|
// Acquire the sector buffer
|
|
if (cache->user != self) {
|
|
if (cache->user != NULL) {
|
|
mp_spiflash_cache_flush(cache->user);
|
|
}
|
|
cache->user = self;
|
|
cache->block = 0xffffffff;
|
|
}
|
|
|
|
if (cache->block != sec) {
|
|
// Read sector
|
|
#if USE_WR_DELAY
|
|
if (cache->block != 0xffffffff) {
|
|
int ret = mp_spiflash_cache_flush_internal(self);
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
}
|
|
#endif
|
|
int ret = mp_spiflash_read_data(self, addr, SECTOR_SIZE, cache->buf);
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
#if USE_WR_DELAY
|
|
|
|
cache->block = sec;
|
|
// Just copy to buffer
|
|
memcpy(cache->buf + offset, src, len);
|
|
// And mark dirty
|
|
self->flags |= 1;
|
|
|
|
#else
|
|
|
|
uint32_t dirty = 0;
|
|
for (size_t i = 0; i < len; ++i) {
|
|
if (cache->buf[offset + i] != src[i]) {
|
|
if (cache->buf[offset + i] != 0xff) {
|
|
// Erase sector
|
|
int ret = mp_spiflash_erase_block_internal(self, addr);
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
dirty = 0xffff;
|
|
break;
|
|
} else {
|
|
dirty |= (1 << ((offset + i) >> 8));
|
|
}
|
|
}
|
|
}
|
|
|
|
cache->block = sec;
|
|
// Copy new block into buffer
|
|
memcpy(cache->buf + offset, src, len);
|
|
|
|
// Write sector in pages of 256 bytes
|
|
for (size_t i = 0; i < 16; ++i) {
|
|
if (dirty & (1 << i)) {
|
|
int ret = mp_spiflash_write_page(self, addr + i * PAGE_SIZE, PAGE_SIZE, cache->buf + i * PAGE_SIZE);
|
|
if (ret != 0) {
|
|
return ret;
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
return 0; // success
|
|
}
|
|
|
|
int mp_spiflash_cached_write(mp_spiflash_t *self, uint32_t addr, size_t len, const uint8_t *src) {
|
|
uint32_t bis = addr / SECTOR_SIZE;
|
|
uint32_t bie = (addr + len - 1) / SECTOR_SIZE;
|
|
|
|
mp_spiflash_acquire_bus(self);
|
|
|
|
mp_spiflash_cache_t *cache = self->config->cache;
|
|
if (cache->user == self && bis <= cache->block && bie >= cache->block) {
|
|
// Write straddles current buffer
|
|
uint32_t pre;
|
|
uint32_t offset;
|
|
if (cache->block * SECTOR_SIZE >= addr) {
|
|
pre = cache->block * SECTOR_SIZE - addr;
|
|
offset = 0;
|
|
} else {
|
|
pre = 0;
|
|
offset = addr - cache->block * SECTOR_SIZE;
|
|
}
|
|
|
|
// Write buffered part first
|
|
uint32_t len_in_buf = len - pre;
|
|
len = 0;
|
|
if (len_in_buf > SECTOR_SIZE - offset) {
|
|
len = len_in_buf - (SECTOR_SIZE - offset);
|
|
len_in_buf = SECTOR_SIZE - offset;
|
|
}
|
|
memcpy(&cache->buf[offset], &src[pre], len_in_buf);
|
|
self->flags |= 1; // Mark dirty
|
|
|
|
// Write part before buffer sector
|
|
while (pre) {
|
|
int rest = pre & (SECTOR_SIZE - 1);
|
|
if (rest == 0) {
|
|
rest = SECTOR_SIZE;
|
|
}
|
|
int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
|
|
if (ret != 0) {
|
|
mp_spiflash_release_bus(self);
|
|
return ret;
|
|
}
|
|
src += rest;
|
|
addr += rest;
|
|
pre -= rest;
|
|
}
|
|
src += len_in_buf;
|
|
addr += len_in_buf;
|
|
|
|
// Fall through to write remaining part
|
|
}
|
|
|
|
uint32_t offset = addr & (SECTOR_SIZE - 1);
|
|
while (len) {
|
|
int rest = SECTOR_SIZE - offset;
|
|
if (rest > len) {
|
|
rest = len;
|
|
}
|
|
int ret = mp_spiflash_cached_write_part(self, addr, rest, src);
|
|
if (ret != 0) {
|
|
mp_spiflash_release_bus(self);
|
|
return ret;
|
|
}
|
|
len -= rest;
|
|
addr += rest;
|
|
src += rest;
|
|
offset = 0;
|
|
}
|
|
|
|
mp_spiflash_release_bus(self);
|
|
return 0;
|
|
}
|
|
|
|
#endif // MICROPY_HW_SPIFLASH_ENABLE_CACHE
|