micropython/ports/renesas-ra/fsp_cfg/r_iic_master_cfg.h

15 wiersze
324 B
C

#ifndef R_IIC_MASTER_CFG_H_
#define R_IIC_MASTER_CFG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
#define IIC_MASTER_CFG_DTC_ENABLE (0)
#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
#ifdef __cplusplus
}
#endif
#endif /* R_IIC_MASTER_CFG_H_ */