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10 Commity (bc4f8b438b56cf1b4f6b44febcd0d83599cbbd68)

Autor SHA1 Wiadomość Data
Yonatan Goldschmidt bc4f8b438b extmod/moduwebsocket: Refactor `websocket` to `uwebsocket`.
As mentioned in #4450, `websocket` was experimental with a single intended
user, `webrepl`. Therefore, we'll make this change without a weak
link `websocket` -> `uwebsocket`.
2019-02-14 00:35:45 +11:00
Damien George 36808d4e6a esp8266/main: Activate UART(0) on dupterm for REPL before boot.py runs.
So that the user can explicitly deactivate UART(0) if needed.  See
issue #4314.

This introduces some risk to "brick" the device, if the user disables the
REPL without providing an alternative REPL (eg WebREPL), or any way to
reenable it.  In such a case the device needs to be erased and
reprogrammed.  This seems unavoidable, given the desire to have the option
to use the UART for something other than the REPL.
2019-01-16 17:24:23 +11:00
Damien George aace60a75e esp8266/modules/ntptime.py: Remove print of newly-set time.
It should be up to the user if they want to print the new time out or not.

Fixes issue #3766.
2018-06-05 14:30:35 +10:00
Damien George afd0701bf7 esp8266: Change UART(0) to attach to REPL via uos.dupterm interface.
This patch makes it so that UART(0) can by dynamically attached to and
detached from the REPL by using the uos.dupterm function.  Since WebREPL
uses dupterm slot 0 the UART uses dupterm slot 1 (a slot which is newly
introduced by this patch).  UART(0) must now be attached manually in
boot.py (or otherwise) and inisetup.py is changed to provide code to do
this.  For example, to attach use:

    import uos, machine
    uart = machine.UART(0, 115200)
    uos.dupterm(uart, 1)

and to detach use:

    uos.dupterm(None, 1)

When attached, all incoming chars on UART(0) go straight to stdin so
uart.read() will always return None.  Use sys.stdin.read() if it's needed
to read characters from the UART(0) while it's also used for the REPL (or
detach, read, then reattach).  When detached the UART(0) can be used for
other purposes.

If there are no objects in any of the dupterm slots when the REPL is
started (on hard or soft reset) then UART(0) is automatically attached.
Without this, the only way to recover a board without a REPL would be to
completely erase and reflash (which would install the default boot.py which
attaches the REPL).
2018-05-21 11:31:59 +10:00
Damien George a40ce1d829 esp8266/modules: Move dht.py driver to drivers/dht directory. 2018-01-31 18:11:06 +11:00
Damien George 4e056d82cc esp8266/modules/webrepl_setup: Fix first-time enable of WebREPL.
Prior to this fix, enabling WebREPL for the first time via webrepl_setup
did not work at all because "boot.py" did not contain any lines with
"webrepl" in them that could be uncommented.
2017-11-30 10:54:33 +11:00
Damien George 37282f8fc1 extmod/uos_dupterm: Update uos.dupterm() and helper funcs to have index.
The uos.dupterm() signature and behaviour is updated to reflect the latest
enhancements in the docs.  It has minor backwards incompatibility in that
it no longer accepts zero arguments.

The dupterm_rx helper function is moved from esp8266 to extmod and
generalised to support multiple dupterm slots.

A port can specify multiple slots by defining the MICROPY_PY_OS_DUPTERM
config macro to an integer, being the number of slots it wants to have;
0 means to disable the dupterm feature altogether.

The unix and esp8266 ports are updated to work with the new interface and
are otherwise unchanged with respect to functionality.
2017-10-13 20:01:57 +11:00
Vitor Massaru Iha 1b7d6a7951 esp8266/modules/webrepl_setup: Add info about allowed password length.
This patch also makes the code more concise by combining the checks for the
password length.
2017-10-11 11:37:01 +11:00
Damien George 4a93801c12 all: Update Makefiles and others to build with new ports/ dir layout.
Also renames "stmhal" to "stm32" in documentation and everywhere else.
2017-09-06 14:09:13 +10:00
Damien George 01dd7804b8 ports: Make new ports/ sub-directory and move all ports there.
This is to keep the top-level directory clean, to make it clear what is
core and what is a port, and to allow the repository to grow with new ports
in a sustainable way.
2017-09-06 13:40:51 +10:00