kopia lustrzana https://github.com/micropython/micropython
stm32/qspi: Support read in 1 and 4 line modes.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>pull/12722/head
rodzic
55ca924bea
commit
fd2833e95c
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@ -350,11 +350,29 @@ static int qspi_read_cmd(void *self_in, uint8_t cmd, size_t len, uint32_t *dest)
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return 0;
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return 0;
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}
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}
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static int qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) {
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static int qspi_read_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest, uint8_t mode) {
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(void)self_in;
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(void)self_in;
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uint8_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2;
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uint8_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2;
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uint32_t dmode = 0;
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uint32_t admode = 0;
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uint32_t dcyc = 0;
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uint32_t abmode = 0;
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if (mode == MP_QSPI_TRANSFER_CMD_QADDR_QDATA) {
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dmode = 3; // 4 data lines used
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admode = 3; // 4 address lines used
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dcyc = 4; // 4 dummy cycles (2 bytes)
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abmode = 3; // alternate-byte bytes sent on 4 lines
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} else if (mode == MP_QSPI_TRANSFER_CMD_ADDR_DATA) {
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dmode = 1; // 1 data lines used
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admode = 1; // 1 address lines used
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dcyc = 8; // 8 dummy cycles (1 byte)
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abmode = 0; // No alternate-byte bytes sent
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} else {
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return -1;
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}
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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QUADSPI->FCR = QUADSPI_FCR_CTCF; // clear TC flag
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QUADSPI->DLR = len - 1; // number of bytes to read
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QUADSPI->DLR = len - 1; // number of bytes to read
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@ -363,12 +381,12 @@ static int qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr,
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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0 << QUADSPI_CCR_DDRM_Pos // DDR mode disabled
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction
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| 1 << QUADSPI_CCR_FMODE_Pos // indirect read mode
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| 1 << QUADSPI_CCR_FMODE_Pos // indirect read mode
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| 3 << QUADSPI_CCR_DMODE_Pos // data on 4 lines
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| dmode << QUADSPI_CCR_DMODE_Pos // data lines
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| 4 << QUADSPI_CCR_DCYC_Pos // 4 dummy cycles
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| dcyc << QUADSPI_CCR_DCYC_Pos // dummy cycles
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| 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte
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| 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte
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| 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines
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| abmode << QUADSPI_CCR_ABMODE_Pos // alternate byte count / lines
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| adsize << QUADSPI_CCR_ADSIZE_Pos // 32 or 24-bit address size
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| adsize << QUADSPI_CCR_ADSIZE_Pos // 32 or 24-bit address size
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| 3 << QUADSPI_CCR_ADMODE_Pos // address on 4 lines
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| admode << QUADSPI_CCR_ADMODE_Pos // address lines
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // quad read opcode
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| cmd << QUADSPI_CCR_INSTRUCTION_Pos // quad read opcode
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;
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;
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@ -419,7 +437,7 @@ const mp_qspi_proto_t qspi_proto = {
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.write_cmd_data = qspi_write_cmd_data,
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.write_cmd_data = qspi_write_cmd_data,
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.write_cmd_addr_data = qspi_write_cmd_addr_data,
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.write_cmd_addr_data = qspi_write_cmd_addr_data,
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.read_cmd = qspi_read_cmd,
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.read_cmd = qspi_read_cmd,
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.read_cmd_qaddr_qdata = qspi_read_cmd_qaddr_qdata,
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.read_cmd_addr_data = qspi_read_cmd_addr_data,
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};
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};
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#endif // defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2)
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#endif // defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2)
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