diff --git a/ports/renesas-ra/Makefile b/ports/renesas-ra/Makefile
index 7ffb3b1d0e..71d0a2d667 100644
--- a/ports/renesas-ra/Makefile
+++ b/ports/renesas-ra/Makefile
@@ -16,41 +16,6 @@ endif
 # If the build directory is not given, make it reflect the board name.
 BUILD ?= build-$(BOARD)
 
-ifeq ($(BOARD),RA4M1_CLICKER)
-BOARD_LOW = ra4m1_ek
-CMSIS_MCU_LOW = ra4m1
-CMSIS_MCU_CAP = RA4M1
-USE_FSP_LPM = 0
-endif
-
-ifeq ($(BOARD),EK_RA4M1)
-BOARD_LOW = ra4m1_ek
-CMSIS_MCU_LOW = ra4m1
-CMSIS_MCU_CAP = RA4M1
-USE_FSP_LPM = 0
-endif
-
-ifeq ($(BOARD),EK_RA4W1)
-BOARD_LOW = ra4w1_ek
-CMSIS_MCU_LOW = ra4w1
-CMSIS_MCU_CAP = RA4W1
-USE_FSP_LPM = 1
-endif
-
-ifeq ($(BOARD),EK_RA6M1)
-BOARD_LOW = ra6m1_ek
-CMSIS_MCU_LOW = ra6m1
-CMSIS_MCU_CAP = RA6M1
-USE_FSP_LPM = 1
-endif
-
-ifeq ($(BOARD),EK_RA6M2)
-BOARD_LOW = ra6m2_ek
-CMSIS_MCU_LOW = ra6m2
-CMSIS_MCU_CAP = RA6M2
-USE_FSP_LPM = 1
-endif
-
 # select use wrapper function of FSP library
 USE_FSP_FLASH = 1
 
@@ -58,6 +23,10 @@ include ../../py/mkenv.mk
 -include mpconfigport.mk
 include $(BOARD_DIR)/mpconfigboard.mk
 
+USE_FSP_LPM ?= 1
+USE_FSP_QSPI ?= 0
+FSP_BOARD_NAME ?= $(shell echo $(BOARD) | tr '[:upper:]' '[:lower:]')
+
 # Files that are generated and needed before the QSTR build.
 #QSTR_GENERATED_HEADERS = $(BUILD)/pins_qstr.h $(BUILD)/modstm_qstr.h
 QSTR_GENERATED_HEADERS = $(BUILD)/pins_qstr.h
@@ -101,16 +70,18 @@ INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc/api
 INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc/instances
 INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include
 #INC += -Ilwip_inc
-ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2))
+ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2 RA6M5))
 INC += -Ira
 endif
 INC += -I$(BOARD_DIR)/ra_gen
+INC += -I$(BOARD_DIR)/ra_cfg/driver
 INC += -I$(BOARD_DIR)/ra_cfg/fsp_cfg
 INC += -I$(BOARD_DIR)/ra_cfg/fsp_cfg/bsp
 INC += -Idebug
 
 CFLAGS += -D$(CMSIS_MCU)
 CFLAGS += -DRA_HAL_H='<$(CMSIS_MCU)_hal.h>'
+CFLAGS += -DRA_CFG_H='<$(FSP_BOARD_NAME)_conf.h>'
 
 # Basic Cortex-M flags
 CFLAGS_CORTEX_M = -mthumb
@@ -123,12 +94,19 @@ CFLAGS_CORTEX_M += -mfpu=fpv4-sp-d16 -mfloat-abi=hard
 SUPPORTS_HARDWARE_FP_SINGLE = 1
 endif
 
+ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),m33))
+CFLAGS_CORTEX_M += -mfpu=fpv5-sp-d16 -mfloat-abi=hard 
+SUPPORTS_HARDWARE_FP_SINGLE = 1
+endif
+
 # Options for particular MCU series
 CFLAGS_MCU_RA4M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
 CFLAGS_MCU_RA4W1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
 CFLAGS_MCU_RA6M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
 CFLAGS_MCU_RA6M2 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
+CFLAGS_MCU_RA6M5 = $(CFLAGS_CORTEX_M) -mtune=cortex-m33 -mcpu=cortex-m33
 
+ASFLAGS += $(CFLAGS_CORTEX_M) -mcpu=cortex-$(MCU_SERIES)
 CFLAGS += $(INC) -Wall -Wpointer-arith -Werror -Wdouble-promotion -Wfloat-conversion -std=gnu99 -nostdlib $(CFLAGS_EXTRA)
 #CFLAGS += -D$(CMSIS_MCU)
 CFLAGS += $(CFLAGS_MCU_$(CMSIS_MCU))
@@ -315,11 +293,13 @@ SRC_C += \
 	gccollect.c \
 	help.c \
 	machine_adc.c \
+	machine_dac.c \
 	machine_i2c.c \
 	machine_spi.c \
 	machine_uart.c \
 	machine_pin.c \
 	machine_rtc.c \
+	machine_sdcard.c \
 	modmachine.c \
 	extint.c \
 	usrsw.c \
@@ -365,6 +345,17 @@ HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/,\
 CFLAGS_FSP = -Wno-unused-variable -Wno-unused-function
 $(BUILD)/lib/fsp/ra/fsp/src/r_sci_uart/r_sci_uart.o: CFLAGS += $(CFLAGS_FSP)
 
+ifeq ($(USE_FSP_QSPI), 1)
+CFLAGS += -DUSE_FSP_QSPI
+HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_qspi/r_qspi.c
+endif
+
+ifeq ($(USE_FSP_SDHI), 1)
+CFLAGS += -DUSE_FSP_SDHI
+HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_sdhi/r_sdhi.c \
+	$(HAL_DIR)/ra/fsp/src/r_dtc/r_dtc.c
+endif
+
 ifeq ($(USE_FSP_LPM), 1)
 CFLAGS += -DUSE_FSP_LPM
 HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_lpm/r_lpm.c
@@ -377,16 +368,17 @@ HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_lp/r_flash_lp.c
 endif
 endif
 
-ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1 RA6M2))
+ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1 RA6M2 RA6M5))
 ifeq ($(USE_FSP_FLASH), 1)
 CFLAGS += -DUSE_FSP_FLASH
 HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_hp/r_flash_hp.c
 endif
 endif
 
-ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2))
+ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2 RA6M5))
 HAL_SRC_C += $(addprefix ra/,\
 	ra_adc.c \
+	ra_dac.c \
 	ra_flash.c \
 	ra_gpio.c \
 	ra_i2c.c \
@@ -397,6 +389,7 @@ HAL_SRC_C += $(addprefix ra/,\
 	ra_sci.c \
 	ra_spi.c \
 	ra_timer.c \
+	ra_gpt.c \
 	ra_utils.c \
 	)
 
@@ -413,6 +406,12 @@ OBJ += $(addprefix $(BUILD)/, $(SRC_CXX:.cpp=.o))
 OBJ += $(addprefix $(BUILD)/, $(SRC_O))
 OBJ += $(BUILD)/pins_$(BOARD).o
 
+ifeq ($(CMSIS_MCU),RA6M5)
+$(BUILD)/shared/runtime/gchelper_thumb2.o: $(TOP)/shared/runtime/gchelper_thumb2.s
+	$(ECHO) "AS $<"
+	$(Q)$(AS) $(ASFLAGS) -o $@ $<
+endif
+
 # This file contains performance critical functions so turn up the optimisation
 # level.  It doesn't add much to the code size and improves performance a bit.
 # Don't use -O3 with this file because gcc tries to optimise memset in terms of itself.
@@ -486,6 +485,9 @@ endif
 ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M2))
 AF_FILE = boards/ra6m2_af.csv
 endif
+ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M5))
+AF_FILE = boards/ra6m5_af.csv
+endif
 GEN_PINS_SRC = $(BUILD)/pins_$(BOARD).c
 GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
 GEN_PINS_QSTR = $(BUILD)/pins_qstr.h
diff --git a/ports/renesas-ra/RA4M1_hal.h b/ports/renesas-ra/RA4M1_hal.h
index 7f0ad9666f..bdfa8cc75c 100644
--- a/ports/renesas-ra/RA4M1_hal.h
+++ b/ports/renesas-ra/RA4M1_hal.h
@@ -31,8 +31,11 @@
 // #include "hal_data.h"
 #include "bsp_api.h"
 #include "common_data.h"
+#if defined(USE_DBG_PRINT)
+#include RA_CFG_H
+#endif
 
-#define SCI_CH      0
+#define SCI_CH      DEFAULT_DBG_CH
 #define SCI_BAUD    115200
 #define UART_CH     SCI_CH
 #define UART_TxStr  sci_tx_str
@@ -56,8 +59,10 @@
 
 #include "ra_config.h"
 #include "ra_adc.h"
+#include "ra_dac.h"
 #include "ra_flash.h"
 #include "ra_gpio.h"
+#include "ra_gpt.h"
 #include "ra_i2c.h"
 #include "ra_icu.h"
 #include "ra_init.h"
diff --git a/ports/renesas-ra/RA4W1_hal.h b/ports/renesas-ra/RA4W1_hal.h
index 774ec46b38..930127c459 100644
--- a/ports/renesas-ra/RA4W1_hal.h
+++ b/ports/renesas-ra/RA4W1_hal.h
@@ -31,8 +31,11 @@
 // #include "hal_data.h"
 #include "bsp_api.h"
 #include "common_data.h"
+#if defined(USE_DBG_PRINT)
+#include RA_CFG_H
+#endif
 
-#define SCI_CH      0
+#define SCI_CH      DEFAULT_DBG_CH
 #define SCI_BAUD    115200
 #define UART_CH     SCI_CH
 #define UART_TxStr  sci_tx_str
@@ -56,8 +59,10 @@
 
 #include "ra_config.h"
 #include "ra_adc.h"
+#include "ra_dac.h"
 #include "ra_flash.h"
 #include "ra_gpio.h"
+#include "ra_gpt.h"
 #include "ra_i2c.h"
 #include "ra_icu.h"
 #include "ra_init.h"
diff --git a/ports/renesas-ra/RA6M1_hal.h b/ports/renesas-ra/RA6M1_hal.h
index 9929d29b54..6721a6fdb2 100644
--- a/ports/renesas-ra/RA6M1_hal.h
+++ b/ports/renesas-ra/RA6M1_hal.h
@@ -31,8 +31,11 @@
 // #include "hal_data.h"
 #include "bsp_api.h"
 #include "common_data.h"
+#if defined(USE_DBG_PRINT)
+#include RA_CFG_H
+#endif
 
-#define SCI_CH      0
+#define SCI_CH      DEFAULT_DBG_CH
 #define SCI_BAUD    115200
 #define UART_CH     SCI_CH
 #define UART_TxStr  sci_tx_str
@@ -56,8 +59,10 @@
 
 #include "ra_config.h"
 #include "ra_adc.h"
+#include "ra_dac.h"
 #include "ra_flash.h"
 #include "ra_gpio.h"
+#include "ra_gpt.h"
 #include "ra_i2c.h"
 #include "ra_icu.h"
 #include "ra_init.h"
diff --git a/ports/renesas-ra/RA6M2_hal.h b/ports/renesas-ra/RA6M2_hal.h
index 75877cc0f6..ffecacd2ba 100644
--- a/ports/renesas-ra/RA6M2_hal.h
+++ b/ports/renesas-ra/RA6M2_hal.h
@@ -31,8 +31,11 @@
 // #include "hal_data.h"
 #include "bsp_api.h"
 #include "common_data.h"
+#if defined(USE_DBG_PRINT)
+#include RA_CFG_H
+#endif
 
-#define SCI_CH      0
+#define SCI_CH      DEFAULT_DBG_CH
 #define SCI_BAUD    115200
 #define UART_CH     SCI_CH
 #define UART_TxStr  sci_tx_str
@@ -56,8 +59,10 @@
 
 #include "ra_config.h"
 #include "ra_adc.h"
+#include "ra_dac.h"
 #include "ra_flash.h"
 #include "ra_gpio.h"
+#include "ra_gpt.h"
 #include "ra_i2c.h"
 #include "ra_icu.h"
 #include "ra_init.h"
diff --git a/ports/renesas-ra/RA6M5_hal.h b/ports/renesas-ra/RA6M5_hal.h
new file mode 100644
index 0000000000..2e58dcb41d
--- /dev/null
+++ b/ports/renesas-ra/RA6M5_hal.h
@@ -0,0 +1,109 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021 Renesas Electronics Corporation
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef PORTS_RA_RA6M5_HAL_H_
+#define PORTS_RA_RA6M5_HAL_H_
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdbool.h>
+// #include "hal_data.h"
+#include "bsp_api.h"
+#include "common_data.h"
+#if defined(USE_DBG_PRINT)
+#include RA_CFG_H
+#endif
+
+#define SCI_CH      DEFAULT_DBG_CH
+#define SCI_BAUD    115200
+#define UART_CH     SCI_CH
+#define UART_TxStr  sci_tx_str
+#define PCLK        100000000
+
+#define RA_PRI_SYSTICK  (0)
+#define RA_PRI_UART     (1)
+#define RA_PRI_SDIO     (4)
+#define RA_PRI_DMA      (5)
+#define RA_PRI_FLASH    (6)
+#define RA_PRI_OTG_FS   (6)
+#define RA_PRI_OTG_HS   (6)
+#define RA_PRI_TIM5     (6)
+#define RA_PRI_CAN      (7)
+#define RA_PRI_SPI      (8)
+#define RA_PRI_I2C      (8)
+#define RA_PRI_TIMX     (13)
+#define RA_PRI_EXTINT   (14)
+#define RA_PRI_PENDSV   (15)
+#define RA_PRI_RTC_WKUP (15)
+
+#include "ra_config.h"
+#include "ra_adc.h"
+#include "ra_dac.h"
+#include "ra_flash.h"
+#include "ra_gpio.h"
+#include "ra_gpt.h"
+#include "ra_i2c.h"
+#include "ra_icu.h"
+#include "ra_init.h"
+#include "ra_int.h"
+#include "ra_rtc.h"
+#include "ra_sci.h"
+#include "ra_spi.h"
+#include "ra_timer.h"
+#include "ra_utils.h"
+
+typedef enum {
+    HAL_OK       = 0x00,
+    HAL_ERROR    = 0x01,
+    HAL_BUSY     = 0x02,
+    HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+#define __IO    volatile
+
+#if defined(USE_DBG_PRINT)
+#if !defined(DEBUG_CH)
+#define DEBUG_CH SCI_CH
+#endif
+#if (DEBUG_CH == 6)
+#define DEBUG_TX_PIN    P506
+#define DEBUG_RX_PIN    P505
+#endif
+#if (DEBUG_CH == 7)
+#define DEBUG_TX_PIN    P613
+#define DEBUG_RX_PIN    P614
+#endif
+#if (DEBUG_CH == 9)
+#define DEBUG_TX_PIN    P109
+#define DEBUG_RX_PIN    P110
+#endif
+#define DEBUG_TXSTR(s)  ra_sci_tx_str(DEBUG_CH, (unsigned char *)s)
+#define DEBUG_TXCH(c)   ra_sci_tx_ch(DEBUG_CH, c)
+#else
+#define DEBUG_TXSTR(s)
+#define DEBUG_TXCH(c)
+#endif
+
+#endif /* PORTS_RA_RA6M5_HAL_H_ */
diff --git a/ports/renesas-ra/README.md b/ports/renesas-ra/README.md
index 1e5e2ed0cf..4cd116a37f 100644
--- a/ports/renesas-ra/README.md
+++ b/ports/renesas-ra/README.md
@@ -6,9 +6,9 @@ Currently supported features are:
 - Filesystem on the internal flash using FatFs.
 - `time` module with sleep, time, and ticks functions.
 - `os` module with VFS support.
-- `machine` module with the following classes: `Pin`, `ADC`, `I2C`, `SPI`,
-   `SoftI2C`, `SoftSPI`, `UART`, `RTC`
-- sdcard driver if frozen driver is installed.
+- `machine` module with the following classes: `Pin`, `ADC`, `PWM`, `DAC`, `I2C`,
+  `SPI`, `SoftI2C`, `SoftSPI`, `UART`, `RTC`, `SDCard`.
+- `sdcard` module for MCUs without native `machine.SDCard` support.
 
 Currently supported board product names are:
 
diff --git a/ports/renesas-ra/boards/EK_RA4M1/mpconfigboard.mk b/ports/renesas-ra/boards/EK_RA4M1/mpconfigboard.mk
index abc111d16e..71c004df81 100644
--- a/ports/renesas-ra/boards/EK_RA4M1/mpconfigboard.mk
+++ b/ports/renesas-ra/boards/EK_RA4M1/mpconfigboard.mk
@@ -4,6 +4,9 @@ LD_FILES = boards/EK_RA4M1/ra4m1_ek.ld
 
 # MicroPython settings
 MICROPY_VFS_FAT = 1
+USE_FSP_LPM = 0
+
+CFLAGS+=-DDEFAULT_DBG_CH=0
 
 # Don't include default frozen modules because MCU is tight on flash space
 FROZEN_MANIFEST ?= boards/EK_RA4M1/manifest.py
diff --git a/ports/renesas-ra/boards/EK_RA4W1/mpconfigboard.mk b/ports/renesas-ra/boards/EK_RA4W1/mpconfigboard.mk
index c4f95f79f4..3a064e0e35 100644
--- a/ports/renesas-ra/boards/EK_RA4W1/mpconfigboard.mk
+++ b/ports/renesas-ra/boards/EK_RA4W1/mpconfigboard.mk
@@ -4,3 +4,5 @@ LD_FILES = boards/EK_RA4W1/ra4w1_ek.ld
 
 # MicroPython settings
 MICROPY_VFS_FAT = 1
+
+CFLAGS+=-DDEFAULT_DBG_CH=0
diff --git a/ports/renesas-ra/boards/EK_RA6M1/mpconfigboard.mk b/ports/renesas-ra/boards/EK_RA6M1/mpconfigboard.mk
index 3f916eb8e3..645daedc7b 100644
--- a/ports/renesas-ra/boards/EK_RA6M1/mpconfigboard.mk
+++ b/ports/renesas-ra/boards/EK_RA6M1/mpconfigboard.mk
@@ -4,3 +4,5 @@ LD_FILES = boards/EK_RA6M1/ra6m1_ek.ld
 
 # MicroPython settings
 MICROPY_VFS_FAT = 1
+
+CFLAGS+=-DDEFAULT_DBG_CH=0
diff --git a/ports/renesas-ra/boards/EK_RA6M2/mpconfigboard.mk b/ports/renesas-ra/boards/EK_RA6M2/mpconfigboard.mk
index a48ec6e50a..983cbed119 100644
--- a/ports/renesas-ra/boards/EK_RA6M2/mpconfigboard.mk
+++ b/ports/renesas-ra/boards/EK_RA6M2/mpconfigboard.mk
@@ -4,3 +4,5 @@ LD_FILES = boards/EK_RA6M2/ra6m2_ek.ld
 
 # MicroPython settings
 MICROPY_VFS_FAT = 1
+
+CFLAGS+=-DDEFAULT_DBG_CH=0
diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk b/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk
index 1758ce6738..5d845d93c5 100644
--- a/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk
+++ b/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk
@@ -4,6 +4,9 @@ LD_FILES = boards/RA4M1_CLICKER/ra4m1_clicker.ld
 
 # MicroPython settings
 MICROPY_VFS_FAT = 1
+USE_FSP_LPM = 0
+
+CFLAGS+=-DDEFAULT_DBG_CH=0
 
 # Don't include default frozen modules because MCU is tight on flash space
 FROZEN_MANIFEST ?= boards/RA4M1_CLICKER/manifest.py
diff --git a/ports/renesas-ra/boards/manifest.py b/ports/renesas-ra/boards/manifest.py
index c650136f66..94457a4696 100644
--- a/ports/renesas-ra/boards/manifest.py
+++ b/ports/renesas-ra/boards/manifest.py
@@ -1,4 +1,3 @@
 include("$(MPY_DIR)/extmod/asyncio")
 require("dht")
 require("onewire")
-require("sdcard")
diff --git a/ports/renesas-ra/boards/ra6m5_af.csv b/ports/renesas-ra/boards/ra6m5_af.csv
new file mode 100644
index 0000000000..816a0c5001
--- /dev/null
+++ b/ports/renesas-ra/boards/ra6m5_af.csv
@@ -0,0 +1,193 @@
+CPU_PIN,PORT_IDX,PORT_BIT,Analog,IRQ,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,AF16,AF17,AF18,AF19,AF20,AF21,AF22,AF23,AF24,AF25,AF26,AF27,AF28,AF29,
+P000,0,0,AN000,IRQ6-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P001,0,1,AN001,IRQ7-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P002,0,2,AN002,IRQ8-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P003,0,3,AN003,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P004,0,4,AN004,IRQ9-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P005,0,5,AN005,IRQ10-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P006,0,6,AN006,IRQ11-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P007,0,7,AN007,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P008,0,8,AN008,IRQ12-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P009,0,9,AN009,IRQ13-DS,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P010,0,10,AN010,IRQ14,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,0,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,0,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,0,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P014,0,14,AN012,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P015,0,15,AN013,IRQ13,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P100,1,0,,IRQ2,Hi-Z,AGTIO0,GTETRGA,GTIOC5B,RXD0/MISO0/SCL0,SCK1,MISOB_A,,,,,D00[A00/D00],,,,,,QSPCLK,,,,,,,,,,,OM_SCLK,,
+P101,1,1,,IRQ1,Hi-Z,AGTEE0,GTETRGB,GTIOC5A,TXD0/MOSI0/SDA0,CTS1_RTS1/SS1,MOSIB_A,,,,,D01[A01/D01],,,,,,QIO1,,,,,,,,,,,OM_SIO7,,
+P102,1,2,,,Hi-Z,AGTO0,GTOWLO,GTIOC2B,SCK0,,RSPCKB_A,,,,ADTRG0,D02[A02/D02],,,,,CRX0,QIO0,,,,,,,,,,,OM_SIO1,,
+P103,1,3,,,Hi-Z,AGTIO2,GTOWUP,GTIOC2A,CTS0_RTS0/SS0,,SSLB0_A,,,,,D03[A03/D03],,,,,CTX0,QIO3,,,,,,,,,,,OM_SIO6,,
+P104,1,4,,IRQ1,Hi-Z,AGTEE2,GTETRGB,GTIOC1B,RXD8/MISO8/SCL8,,SSLB1_A,,,,,D04[A04/D04],,,,,,QIO2,,,,,,,,,,,OM_DQS,,
+P105,1,5,,IRQ0,Hi-Z,AGTO2,GTETRGA,GTIOC1A,TXD8/MOSI8/SDA8,,SSLB2_A,,,,,D05[A05/D05],,,,,,,,,,,,,,,,,OM_SIO5,,
+P106,1,6,,,Hi-Z,AGTOB0,,GTIOC8B,SCK8,,SSLB3_A,,,,,D06[A06/D06],,,,,,,,,,,,,,,,,OM_SIO0,,
+P107,1,7,,,Hi-Z,AGTOA0,,GTIOC8A,CTS8_RTS8/SS8,,,,,,,D07[A07/D07],,,,,,,,,,,,,,,,,OM_SIO3,,
+P108,1,8,,,TMS/SWDIO,AGTOA3,GTOULO,GTIOC0B,,CTS9_RTS9/SS9,SSLA0_B,,,,,,,,,,,,,,,,,,,,,,,,
+P109,1,9,,,TDO/SWO,AGTOB3,GTOVUP,GTIOC1A,,TXD9/MOSI9/SDA9,MOSIA_B,,,CLKOUT,,,,,,,CTX1,,,,,,,,,,,,,,
+P110,1,10,,IRQ3,TDI,AGTEE3,GTOVLO,GTIOC1B,CTS2_RTS2/SS2,RXD9/MISO9/SCL9,MISOA_B,,,,,,,,,,CRX1,,,,,,,,,,,,,,
+P111,1,11,,IRQ4,Hi-Z,AGTOA5,,GTIOC3A,SCK2,SCK9,RSPCKA_B,,,,,A05,,,,,,,,,,,,,,,,,,,
+P112,1,12,,,Hi-Z,AGTOB5,,GTIOC3B,TXD2/MOSI2/SDA2/TXDX2/SIOX2,SCK1,SSLA0_B,,,,,A04,,,,,,QSSL,SSIBCK0_B,,,,,,,,,,OM_CS1,,
+P113,1,13,,,Hi-Z,AGTEE5,,GTIOC2A,RXD2/MISO2/SCL2/RXDX2,,,,,,,A03,,,,,,,SSILRCK0/SSIFS0_B,,,,,,,,,,,,
+P114,1,14,,,Hi-Z,AGTIO5,,GTIOC2B,,CTS9,,,,,,A02,,,,,,,SSIRXD0_B,,,,,,,,,,,,
+P115,1,15,,,Hi-Z,,,GTIOC4A,,,,,,,,A01,,,,,,,SSITXD0_B,,,,,,,,,,,,
+P200,2,0,,NMI,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P201,2,1,,,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P202,2,2,,IRQ3-DS,Hi-Z,AGTOB3,,GTIOC5B,SCK2,RXD9/MISO9/SCL9,MISOA_A,,,,,WR1/BC1,TS19,,,,CRX0,,,,,SD0DAT6_A,ET0_ERXD2,,,,,,,,
+P203,2,3,,IRQ2-DS,Hi-Z,AGTOA3,,GTIOC5A,CTS2_RTS2/SS2,TXD9/MOSI9/SDA9,MOSIA_A,,,,,A19,TS18,,,,CTX0,,,,,SD0DAT5_A,ET0_COL,,,,,,,,
+P204,2,4,,,Hi-Z,AGTIO1,GTIW,GTIOC4B,SCK4,SCK9,RSPCKA_A,,,,CACREF,A18,TS00,,,,,,SSIBCK0_C,USB_OVRCURB-DS,,SD0DAT4_A,ET0_RX_DV,,,,,,,,
+P205,2,5,,IRQ1-DS,Hi-Z,AGTO1,GTIV,GTIOC4A,TXD4/MOSI4/SDA4,CTS9_RTS9/SS9,SSLA0_A,SCL1_B,,CLKOUT,,A16,TS01,,,,,,SSILRCK0/SSIFS0_C,USB_OVRCURA-DS,,SD0DAT3_A,ET0_WOL,ET0_WOL,,,,,,,
+P206,2,6,,IRQ0-DS,Hi-Z,,GTIU,,RXD4/MISO4/SCL4,CTS9,SSLA1_A,SDA1_B,,,,WAIT,TS02,,,,,,SSIDATA0_C,USB_VBUSEN,,SD0DAT2_A,ET0_LINKSTA,ET0_LINKSTA,,,,,,CECIO_B,
+P207,2,7,,,Hi-Z,,,,TXD4/MOSI4/SDA4,,SSLA2_A,,,,,A17,TSCAP,,,,,QSSL,,,,,,,,,,,,,
+P208,2,8,,,Hi-Z,,GTOVLO,,,,,,,,,CS4,,,,,,QIO3,,,,SD0DAT0_B,ET0_LINKSTA,ET0_LINKSTA,,,TDATA3,,,,
+P209,2,9,,,Hi-Z,AGTEE5,GTOVUP,,,,,,,,,CS5,,,,,,QIO2,,,,SD0WP,ET0_EXOUT,ET0_EXOUT,,,TDATA2,,,,
+P210,2,10,,,Hi-Z,AGTOB5,GTIW,,,,,,,,,CS6,,,,,,QIO1,,,,SD0CD,ET0_WOL,ET0_WOL,,,TDATA1,,,,
+P211,2,11,,,Hi-Z,AGTOA5,GTIV,,,,,,,,,CS7,,,,,,QIO0,,,,SD0CMD_B,ET0_MDIO,ET0_MDIO,,,TDATA0,,,,
+P212,2,12,,IRQ3,Hi-Z,AGTEE1,GTETRGD,GTIOC0B,,RXD1/MISO1/SCL1/RXDX1,,,,,,,,,,,,,,,,,,,,,,,,,
+P213,2,13,,IRQ2,Hi-Z,AGTEE2,GTETRGC,GTIOC0A,,TXD1/MOSI1/SDA1/TXDX1/SIOX1,,,,,ADTRG1,,,,,,,,,,,,,,,,,,,,
+P214,2,14,,,Hi-Z,AGTO5,GTIU,,,,,,,,,,,,,,,QSPCLK,,,,SD0CLK_B,ET0_MDC,ET0_MDC,,,TCLK,,,,
+-,2,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P300,3,0,,,TCK/SWCLK,,GTOUUP,GTIOC0A,,,SSLA1_B,,,,,,,,,,,,,,,,,,,,,,,,
+P301,3,1,,IRQ6,Hi-Z,AGTIO0,GTOULO,GTIOC4B,RXD2/MISO2/SCL2/RXDX2,CTS9_RTS9/SS9,SSLA2_B,,,,,A06,,,,,,,,,,,,,,,,,,,
+P302,3,2,,IRQ5,Hi-Z,,GTOUUP,GTIOC4A,TXD2/MOSI2/SDA2/TXDX2/SIOX2,,SSLA3_B,,,,,A07,,,,,,,,,,,,,,,,,,,
+P303,3,3,,,Hi-Z,,,GTIOC7B,,CTS9,,,,,,A08,,,,,,,,,,,,,,,,,,,
+P304,3,4,,IRQ9,Hi-Z,AGTEE2,GTOWLO,GTIOC7A,RXD6/MISO6/SCL6,,,,,,,A09,,,,,,,,,,,,,,,,,,,
+P305,3,5,,IRQ8,Hi-Z,AGTOB2,GTOWUP,,TXD6/MOSI6/SDA6,,,,,,,A10,,,,,,QSPCLK,,,,,,,,,,,,,
+P306,3,6,,,Hi-Z,AGTOA2,GTOULO,,SCK6,,,,,,,A11,,,,,,QSSL,,,,,,,,,,,,,
+P307,3,7,,,Hi-Z,AGTEE4,GTOUUP,,CTS6_RTS6/SS6,,,,,,,A12,,,,,,QIO0,,,,,,,,,,,,,
+P308,3,8,,,Hi-Z,AGTOB4,,,CTS6,CTS3,,,,,,A13,,,,,,QIO1,,,,,,,,,,,,,
+P309,3,9,,,Hi-Z,AGTOA4,,,,RXD3/MISO3/SCL3,,,,,,A14,,,,,,QIO2,,,,,,,,,,,,,
+P310,3,10,,,Hi-Z,AGTEE1,,,,TXD3/MOSI3/SDA3,,,,,,A15,,,,,,QIO3,,,,,,,,,,,,,
+P311,3,11,,,Hi-Z,AGTOB1,,,,SCK3,,,,,,CS2,,,,,,,,,,,,,,,,,,,
+P312,3,12,,,Hi-Z,AGTOA1,,,,CTS3_RTS3/SS3,,,,,,CS3,,,,,,,,,,,,,,,,,,,
+P313,3,13,,,Hi-Z,,,,,,,,,,,A20,,,,,,,,,,SD0DAT7_A,ET0_ERXD3,,,,,,,,
+P314,3,14,,,Hi-Z,,,,,,ADTRG0,,,,,A21,,,,,,,,,,,,,,,,,,,
+P315,3,15,,,Hi-Z,,,,RXD4,,,,,,,A22,,,,,,,,,,,,,,,,,,,
+P400,4,0,,IRQ0,Hi-Z,AGTIO1,,GTIOC6A,SCK4,SCK7,,SCL0_A,,,ADTRG1,,,,,,,,AUDIO_CLK,,,,ET0_WOL,ET0_WOL,,,,,,,
+P401,4,1,,IRQ5-DS,Hi-Z,,GTETRGA,GTIOC6B,CTS4_RTS4/SS4,TXD7/MOSI7/SDA7,,SDA0_A,,,,,,,,,CTX0,,,,,,ET0_MDC,ET0_MDC,,,,,,,
+P402,4,2,,IRQ4-DS,Hi-Z,,,,CTS4,RXD7/MISO7/SCL7,,,,,CACREF,,,,,,CRX0,,AUDIO_CLK,,,,ET0_MDIO,ET0_MDIO,,,,,,,
+P403,4,3,,IRQ14-DS,Hi-Z,,,GTIOC3A,,CTS7_RTS7/SS7,,,,,,,,,,,,,SSIBCK0_A,,,,ET0_LINKSTA,ET0_LINKSTA,,,,,,,
+P404,4,4,,IRQ15-DS,Hi-Z,,,GTIOC3B,,CTS7,,,,,,,,,,,,,SSILRCK0/SSIFS0_A,,,,ET0_EXOUT,ET0_EXOUT,,,,,,,
+P405,4,5,,,Hi-Z,,,GTIOC1A,,,,,,,,,,,,,,,SSITXD0_A,,,,ET0_TX_EN,RMII0_TXD_EN_B,,,,,,,
+P406,4,6,,,Hi-Z,AGTO5,,GTIOC1B,,,SSLA3_C,,,,,,,,,,,,SSIRXD0_A,,,,ET0_RX_ER,RMII0_TXD1_B,,,,,,,
+P407,4,7,,,Hi-Z,AGTIO0,,GTIOC6A,CTS4_RTS4/SS4,,SSLA3_A,SDA0_B,,RTCOUT,ADTRG0,,TS03,,,,,,,USB_VBUS,,,ET0_EXOUT,ET0_EXOUT,,,,,,,
+P408,4,8,,IRQ7,Hi-Z,AGTOB2,GTOWLO,GTIOC6B,CTS4,RXD3/MISO3/SCL3,,SCL0_B,,,,,TS04,,,,,,,USB_ID,USBHS_ID,,ET0_CRS,RMII0_CRS_DV_A,,,,,,,
+P409,4,9,,IRQ6,Hi-Z,AGTOA2,GTOWUP,,,TXD3/MOSI3/SDA3,,SDA2_A,,,,,TS05,,,,,,,USB_EXICEN,USBHS_EXICEN,,ET0_RX_CLK,RMII0_RX_ER_A,,,,,,,
+P410,4,10,,IRQ5,Hi-Z,AGTOB1,GTOVLO,GTIOC9B,RXD0/MISO0/SCL0,SCK3,MISOB_B,SCL2_A,,,,,TS06,,,,,,,,,SD0DAT1_A,ET0_ERXD0,RMII0_RXD1_A,,,,,,,
+P411,4,11,,IRQ4,Hi-Z,AGTOA1,GTOVUP,GTIOC9A,TXD0/MOSI0/SDA0,CTS3_RTS3/SS3,MOSIB_B,,,,,,TS07,,,,,,,,,SD0DAT0_A,ET0_ERXD1,RMII0_RXD0_A,,,,,,,
+P412,4,12,,,Hi-Z,AGTEE1,GTOULO,,SCK0,CTS3,RSPCKB_B,,,,,,TS08,,,,,,,,,SD0CMD_A,ET0_ETXD0,REF50CK0_A,,,,,,,
+P413,4,13,,,Hi-Z,AGTEE3,GTOUUP,,CTS0_RTS0/SS0,,SSLB0_B,,,,,,TS09,,,,,,,,,SD0CLK_A,ET0_ETXD1,RMII0_TXD0_A,,,,,,,
+P414,4,14,,IRQ9,Hi-Z,AGTIO5,,GTIOC0B,CTS0,,SSLB1_B,SDA2_B,,,,,TS10,,,,,,,,,SD0WP,ET0_RX_ER,RMII0_TXD1_A,,,,,,,
+P415,4,15,,IRQ8,Hi-Z,AGTIO4,,GTIOC0A,,,SSLB2_B,SCL2_B,,,,,TS11,,,,,,,USB_VBUSEN,,SD0CD,ET0_TX_EN,RMII0_TXD_EN_A,,,,,,,
+P500,5,0,AN116,,Hi-Z,AGTOA0,GTIU,,,CTS5,,,,,CACREF,,,,,,,QSPCLK,,USB_VBUSEN,,,,,,,,,,,
+P501,5,1,AN117,IRQ11,Hi-Z,AGTOB0,GTIV,,,TXD5/MISO5/SDA5,,,,,,,,,,,,QSSL,,USB_OVRCURA,,,,,,,,,,,
+P502,5,2,AN118,IRQ12,Hi-Z,AGTOA2,GTIW,,CTS6,RXD5/MISO5/SCL5,,,,,,,,,,,,QIO0,,USB_OVRCURB,,,,,,,,,,,
+P503,5,3,AN119,,Hi-Z,AGTOB2,GTETRGC,,CTS6_RTS6/SS6,SCK5,,,,,,,,,,,,QIO1,,USB_EXICEN,,,,,,,,,,,
+P504,5,4,AN120,,Hi-Z,AGTOA3,GTETRGD,,SCK6,CTS5_RTS5/SS5,,,,,,ALE,,,,,,QIO2,,USB_ID,,,,,,,,,,,
+P505,5,5,AN121,IRQ14,Hi-Z,AGTOB3,,,RXD6/MISO6/SCL6,,,,,,,,,,,,,QIO3,,,,,,,,,,,,,
+P506,5,6,AN122,IRQ15,Hi-Z,,,,TXD6/MOSI6/SDA6,,,,,,,,,,,,,,,,,,,,,,,,,,
+P507,5,7,AN123,,Hi-Z,,,,SCK6,SCK5,,,,,,,,,,,,,,,,,,,,,,,,,
+P508,5,8,AN124,,Hi-Z,,,,,CTS5_RTS5,,,,,,,,,,,,,,,,,,,,,,,,,
+-,5,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,5,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P511,5,11,,IRQ15,Hi-Z,,,GTIOC0B,RXD4/MISO4/SCL4,,,SDA1_A,,,,,,,,,CRX1,,,,,,,,,,,,,,
+P512,5,12,,IRQ14,Hi-Z,,,GTIOC0A,TXD4/MOSI4/SDA4,,,SCL1_A,,,,,,,,,CTX1,,,,,,,,,,,,,,
+P513,5,13,,,Hi-Z,,,,,RXD5,,,,,,,,,,,,,,,,,,,,,,,,,
+-,5,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,5,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P600,6,0,,,Hi-Z,AGTIO3,,GTIOC6B,,SCK9,,,,CLKOUT,CACREF,RD,,,,,,,,,,,,,,,,,OM_SIO4,,
+P601,6,1,,,Hi-Z,AGTEE3,,GTIOC6A,,RXD9/MISO9/SCL9,,,,,,WR/WR0,,,,,,,,,,,,,,,,,OM_SIO2,,
+P602,6,2,,,Hi-Z,AGTO3,,GTIOC7B,,TXD9/MOSI9/SDA9,,,,,,EBCLK,,,,,,,,,,,,,,,,,OM_CS1,,
+P603,6,3,,,Hi-Z,AGTIO4,,GTIOC7A,,CTS9_RTS9/SS9,,,,,,D13[A13/D13],,,,,,,,,,,,,,,,,,,
+P604,6,4,,,Hi-Z,AGTEE4,,GTIOC8B,,CTS9,,,,,,D12[A12/D12],,,,,,,,,,,,,,,,,,,
+P605,6,5,,,Hi-Z,AGTO4,,GTIOC8A,CTS8,,,,,,,D11[A11/D11],,,,,,,,,,,,,,,,,,,
+P606,6,6,,,Hi-Z,,,,CTS8_RTS8,,,,,RTCOUT,,,,,,,,,,,,,,,,,,,,,
+P607,6,7,,,Hi-Z,,,,RXD8,,,,,,,,,,,,,,,,,,,,,,,,,,
+P608,6,8,,,Hi-Z,,,GTIOC4B,,,,,,,,A00/BC0,,,,,,,,,,,,,,,,,,,
+P609,6,9,,,Hi-Z,AGTO5,,GTIOC5A,,,,,,,,CS1,,,,,CTX1,,,,,,,,,,,,OM_ECS,,
+P610,6,10,,,Hi-Z,AGTO4,,GTIOC5B,,CTS7,,,,,,CS0,,,,,CRX1,,,,,,,,,,,,OM_CS0,,
+P611,6,11,,,Hi-Z,AGTO3,,,,CTS7_RTS7/SS7,,,,CLKOUT,CACREF,,,,,,,,,,,,,,,,,,,,
+P612,6,12,,,Hi-Z,AGTO2,,,,SCK7,,,,,,D08[A08/D08],,,,,,,,,,,,,,,,,,,
+P613,6,13,,,Hi-Z,AGTO1,,,,TXD7,,,,,,D09[A09/D09],,,,,,,,,,,,,,,,,,,
+P614,6,14,,,Hi-Z,AGTO0,,,,RXD7,,,,,,D10[A10/D10],,,,,,,,,,,,,,,,,,,
+P615,6,15,,IRQ7,Hi-Z,,,,,,,,,,,,,,,,,,,USB_VBUSEN,,,,,,,,,,,
+P700,7,0,,,Hi-Z,AGTO4,,GTIOC5A,,,MISOA_C,,,,,,,,,,,,,,,,ET0_ETXD1,RMII0_TXD0_B,,,,,,,
+P701,7,1,,,Hi-Z,AGTO3,,GTIOC5B,,,MOSIA_C,,,,,,,,,,,,,,,,ET0_ETXD0,REF50CK0_B,,,,,,,
+P702,7,2,,,Hi-Z,AGTO2,,GTIOC6A,,,RSPCKA_C,,,,,,,,,,,,,,,,ET0_ERXD1,RMII0_RXD0_B,,,,,,,
+P703,7,3,,,Hi-Z,AGTO1,,GTIOC6B,,,SSLA0_C,,,,,,,,,,,,,,,,ET0_ERXD0,RMII0_RXD1_B,,,,,,,
+P704,7,4,,,Hi-Z,AGTO0,,,,,SSLA1_C,,,,,,,,,,CTX0,,,,,,ET0_RX_CLK,RMII0_RX_ER_B,,,,,,,
+P705,7,5,,,Hi-Z,AGTIO0,,,,CTS3,SSLA2_C,,,,,,,,,,CRX0,,,,,,ET0_CRS,RMII0_CRS_DV_B,,,,,,,
+P706,7,6,,IRQ7,Hi-Z,,,,,RXD3,,,,,,,,,,,,,,,USBHS_OVRCURB,,,,,,,,,,
+P707,7,7,,IRQ8,Hi-Z,,,,,TXD3,,,,,,,,,,,,,,,USBHS_OVRCURA,,,,,,,,,,
+P708,7,8,,IRQ11,Hi-Z,,,,,RXD1/MISO1/SCL1/RXDX1/SCL1,SSLB3_B,,,,CACREF,,TS12,,,,,,AUDIO_CLK,,,,ET0_ETXD3,,,,,,,CECIO_A,
+P709,7,9,,IRQ10,Hi-Z,,,,,TXD1/MOSI1/SDA1/TXDX1/SIOX1/SDA1,,,,,,,TS13,,,,,,,,,,ET0_ETXD2,,,,,,,,
+P710,7,10,,,Hi-Z,,,,,SCK1,,,,,,,TS14,,,,,,,,,,ET0_TX_ER,,,,,,,,
+P711,7,11,,,Hi-Z,AGTEE0,,,,CTS1_RTS1/SS1,,,,,,,TS15,,,,,,,,,,ET0_TX_CLK,,,,,,,,
+P712,7,12,,,Hi-Z,AGTOB0,,GTIOC2B,,,,,,,,,TS16,,,,,,,,,,,,,,,,,,
+P713,7,13,,,Hi-Z,AGTOA0,,GTIOC2A,,,,,,,,,TS17,,,,,,,,,,,,,,,,,,
+-,7,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,7,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P800,8,0,AN125,,Hi-Z,AGTOA4,,,CTS0,,,,,,,D14[A14/D14],,,,,,,,,,,,,,,,,,,
+P801,8,1,AN126,,Hi-Z,AGTOB4,,,CTS8,,,,,,,D15[A15/D15],,,,,,,,,,,,,,,,,,,
+P802,8,2,AN127,IRQ3,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P803,8,3,AN128,IRQ2,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P804,8,4,,IRQ1,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P805,8,5,,,Hi-Z,,,,,TXD5,,,,,,,,,,,,,,,,,,,,,,,,,
+P806,8,6,,IRQ0,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,8,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,8,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P900,9,0,,,Hi-Z,,,,TXD4,,,,,,,A23,,,,,,,,,,,,,,,,,,,
+P901,9,1,,,Hi-Z,AGTIO,,,SCK4,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+P905,9,5,,IRQ8,Hi-Z,,,,,,,,,,,,,,,,,,,USB_ID,,,,,,,,,,,
+P906,9,6,,IRQ9,Hi-Z,,,,,,,,,,,,,,,,,,,USB_EXICEN,,,,,,,,,,,
+P907,9,7,,IRQ10,Hi-Z,,,,,,,,,,,,,,,,,,,,USBHS_ID,,,,,,,,,,
+P908,9,8,,IRQ11,Hi-Z,,,,,,,,,,,,,,,,,,,,USBHS_EXICEN,,,,,,,,,,
+-,9,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,9,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+PA00,A,0,,,Hi-Z,,,,TXD8,,,,,,,,,,,,,,,,,,,,,,,,,,
+PA01,A,1,,,Hi-Z,,,,SCK8,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,6,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+PA08,A,8,,IRQ6,Hi-Z,,,,,,,,,,,,,,,,,,,USB_OVRCURA,,,,,,,,,,,
+PA09,A,9,,IRQ5,Hi-Z,,,,,,,,,,,,,,,,,,,USB_OVRCURB,,,,,,,,,,,
+PA10,A,10,,IRQ4,Hi-Z,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,A,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+PB00,B,0,,,Hi-Z,,,,,SCK3,,,,,,,,,,,,,,,USBHS_VBUSEN,,,,,,,,,,
+PB01,B,1,,,Hi-Z,,,,,CTS3_RTS3,,,,,,,,,,,,,,,USBHS_VBUS,,,,,,,,,,
+-,B,2,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,3,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,4,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,5,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,6,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,7,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,8,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,9,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,10,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,11,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,12,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,13,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,14,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+-,B,15,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
diff --git a/ports/renesas-ra/flashbdev.c b/ports/renesas-ra/flashbdev.c
index 3e890d31d9..c213ed8f9b 100644
--- a/ports/renesas-ra/flashbdev.c
+++ b/ports/renesas-ra/flashbdev.c
@@ -38,6 +38,16 @@
 
 #if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE
 
+#if MICROPY_HW_HAS_QSPI_FLASH
+// The linker script specifies flash storage locations.
+extern uint8_t _micropy_hw_external_flash_storage_start;
+extern uint8_t _micropy_hw_external_flash_storage_end;
+
+#define FLASH_MEM_SEG1_START_ADDR \
+    ((long)&_micropy_hw_external_flash_storage_start)
+#define FLASH_MEM_SEG1_NUM_BLOCKS \
+    ((&_micropy_hw_external_flash_storage_end - &_micropy_hw_external_flash_storage_start) / 512)
+#else
 // The linker script specifies flash storage locations.
 extern uint8_t _micropy_hw_internal_flash_storage_start;
 extern uint8_t _micropy_hw_internal_flash_storage_end;
@@ -46,10 +56,11 @@ extern uint8_t _micropy_hw_internal_flash_storage_end;
     ((long)&_micropy_hw_internal_flash_storage_start)
 #define FLASH_MEM_SEG1_NUM_BLOCKS \
     ((&_micropy_hw_internal_flash_storage_end - &_micropy_hw_internal_flash_storage_start) / 512)
+#endif
 
 #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1)
 #define FLASH_SECTOR_SIZE_MAX (0x800)           // 2k max
-#elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3)
+#elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
 #define FLASH_SECTOR_SIZE_MAX (0x8000)          // 32k max
 #else
 #error "no internal flash storage support for this MCU"
diff --git a/ports/renesas-ra/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/fsp_cfg/r_agt_cfg.h
new file mode 100644
index 0000000000..216b6a21d7
--- /dev/null
+++ b/ports/renesas-ra/fsp_cfg/r_agt_cfg.h
@@ -0,0 +1,14 @@
+#ifndef R_AGT_CFG_H_
+#define R_AGT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0)
+#define AGT_CFG_INPUT_SUPPORT_ENABLE (0)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_AGT_CFG_H_ */
diff --git a/ports/renesas-ra/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/fsp_cfg/r_dtc_cfg.h
new file mode 100644
index 0000000000..c4237e7073
--- /dev/null
+++ b/ports/renesas-ra/fsp_cfg/r_dtc_cfg.h
@@ -0,0 +1,13 @@
+#ifndef R_DTC_CFG_H_
+#define R_DTC_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table"
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_DTC_CFG_H_ */
diff --git a/ports/renesas-ra/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/fsp_cfg/r_icu_cfg.h
new file mode 100644
index 0000000000..999692ed3c
--- /dev/null
+++ b/ports/renesas-ra/fsp_cfg/r_icu_cfg.h
@@ -0,0 +1,12 @@
+#ifndef R_ICU_CFG_H_
+#define R_ICU_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_ICU_CFG_H_ */
diff --git a/ports/renesas-ra/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/fsp_cfg/r_iic_master_cfg.h
new file mode 100644
index 0000000000..20f1445862
--- /dev/null
+++ b/ports/renesas-ra/fsp_cfg/r_iic_master_cfg.h
@@ -0,0 +1,14 @@
+#ifndef R_IIC_MASTER_CFG_H_
+#define R_IIC_MASTER_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define IIC_MASTER_CFG_DTC_ENABLE (0)
+#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IIC_MASTER_CFG_H_ */
diff --git a/ports/renesas-ra/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/fsp_cfg/r_rtc_cfg.h
new file mode 100644
index 0000000000..1f8ba25cda
--- /dev/null
+++ b/ports/renesas-ra/fsp_cfg/r_rtc_cfg.h
@@ -0,0 +1,13 @@
+#ifndef R_RTC_CFG_H_
+#define R_RTC_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define RTC_CFG_OPEN_SET_CLOCK_SOURCE (1)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_RTC_CFG_H_ */
diff --git a/ports/renesas-ra/fsp_cfg/r_sdhi_cfg.h b/ports/renesas-ra/fsp_cfg/r_sdhi_cfg.h
new file mode 100644
index 0000000000..62049ed445
--- /dev/null
+++ b/ports/renesas-ra/fsp_cfg/r_sdhi_cfg.h
@@ -0,0 +1,19 @@
+#ifndef R_SDHI_CFG_H_
+#define R_SDHI_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SDHI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define SDMMC_CFG_UNALIGNED_ACCESS_ENABLE (1)
+#ifndef SDHI_CFG_SD_SUPPORT_ENABLE
+#define SDHI_CFG_SD_SUPPORT_ENABLE ((1))
+#endif
+#ifndef SDHI_CFG_EMMC_SUPPORT_ENABLE
+#define SDHI_CFG_EMMC_SUPPORT_ENABLE ((0))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_SDHI_CFG_H_ */
diff --git a/ports/renesas-ra/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/fsp_cfg/r_spi_cfg.h
new file mode 100644
index 0000000000..e228e1036a
--- /dev/null
+++ b/ports/renesas-ra/fsp_cfg/r_spi_cfg.h
@@ -0,0 +1,17 @@
+#ifndef R_SPI_CFG_H_
+#define R_SPI_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#define SPI_DMA_SUPPORT_ENABLE (1)
+#define SPI_TRANSMIT_FROM_RXI_ISR (0)
+
+/* DEPRECATED: Use SPI_DMA_SUPPORT_ENABLE instead. */
+#define SPI_DTC_SUPPORT_ENABLE (SPI_DMA_SUPPORT_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_SPI_CFG_H_ */
diff --git a/ports/renesas-ra/machine_dac.c b/ports/renesas-ra/machine_dac.c
new file mode 100644
index 0000000000..6fd23c2388
--- /dev/null
+++ b/ports/renesas-ra/machine_dac.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2017 Nick Moore
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "py/mperrno.h"
+#include "pin.h"
+#include "ra/ra_dac.h"
+#include "modmachine.h"
+
+#if MICROPY_PY_MACHINE_DAC
+
+typedef struct _machine_dac_obj_t {
+    mp_obj_base_t base;
+    uint8_t active;
+    uint8_t ch;
+    uint16_t mv;
+    mp_hal_pin_obj_t dac;
+} machine_dac_obj_t;
+
+STATIC machine_dac_obj_t machine_dac_obj[] = {
+    #if defined(MICROPY_HW_DAC0)
+    {{&machine_dac_type}, 0, 0, 0, MICROPY_HW_DAC0},
+    #endif
+    #if defined(MICROPY_HW_DAC1)
+    {{&machine_dac_type}, 0, 1, 0, MICROPY_HW_DAC1}
+    #endif
+};
+
+STATIC void machine_dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    machine_dac_obj_t *self = MP_OBJ_TO_PTR(self_in);     // const char *qstr_str(qstr q);
+    mp_printf(print, "DAC(DA%d [#%d], runing=%u, out=%u mV)", self->ch, self->dac->pin, self->active, self->mv);
+}
+
+STATIC mp_obj_t machine_dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
+    mp_hal_pin_obj_t pin_id = MP_OBJ_NULL;
+    machine_dac_obj_t *self = MP_OBJ_NULL;
+
+    enum { ARG_pin };
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_pin,  MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }
+    };
+
+    mp_arg_check_num(n_args, n_kw, 1, 1, true);
+    mp_arg_val_t init_args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, args, MP_ARRAY_SIZE(allowed_args), allowed_args, init_args);
+
+    // Get GPIO and optional device to connect to DAC.
+    pin_id = mp_hal_get_pin_obj(init_args[ARG_pin].u_obj);
+
+    if (pin_id) {
+        for (int i = 0; i < MP_ARRAY_SIZE(machine_dac_obj); i++) {
+            if (pin_id->pin == machine_dac_obj[i].dac->pin) {
+                self = &machine_dac_obj[i];
+                break;
+            }
+        }
+
+        if (self) {
+            if (ra_dac_is_dac_pin(self->dac->pin)) {
+                ra_dac_init(self->dac->pin, self->ch);
+                self->active = ra_dac_is_running(self->ch);
+            } else {
+                mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%d) has no DAC output"), self->dac->pin);
+            }
+        } else {
+            mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%d) is used with other peripheral"), pin_id->pin);
+        }
+    } else {
+        mp_raise_ValueError(MP_ERROR_TEXT("Pin doesn't exist"));
+    }
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+// DAC.deinit()
+STATIC mp_obj_t machine_dac_deinit(mp_obj_t self_in) {
+    machine_dac_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    ra_dac_deinit(self->dac->pin, self->ch);
+    self->active = ra_dac_is_running(self->ch);
+    self->ch = 0;
+    self->mv = 0;
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_dac_deinit_obj, machine_dac_deinit);
+
+// DAC.write(value)
+STATIC mp_obj_t machine_dac_write(mp_obj_t self_in, mp_obj_t data) { // mp_obj_t value_in
+    machine_dac_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    mp_int_t value = mp_obj_get_int(data);
+
+    if (value < 0 || value > 4095) {
+        mp_raise_ValueError(MP_ERROR_TEXT("value should be 0-4095"));
+    } else
+    if (self->active) {
+        ra_dac_write(self->ch, value);
+        self->mv = (value * 3300) / 4095;
+    }
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_dac_write_obj, machine_dac_write);
+
+// DAC.read()
+STATIC mp_obj_t machine_dac_read(mp_obj_t self_in) {
+    machine_dac_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    return MP_OBJ_NEW_SMALL_INT(ra_dac_read(self->ch));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_dac_read_obj, machine_dac_read);
+
+// DAC.write_mv(Vout)
+STATIC mp_obj_t machine_dac_write_mv(mp_obj_t self_in, mp_obj_t data) {  // mp_obj_t self_in, mp_obj_t value_in
+    machine_dac_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    mp_int_t Vout = mp_obj_get_int(data);
+
+    if (Vout < 0 || Vout > 3300) {
+        mp_raise_ValueError(MP_ERROR_TEXT("value should be 0-3300"));
+    } else
+    if (self->active) {
+        uint16_t Dout = (Vout * 4095) / 3300;
+        ra_dac_write(self->ch, Dout);
+        self->mv = Vout;
+    }
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(machine_dac_write_mv_obj, machine_dac_write_mv);
+
+// DAC.read_mv()
+STATIC mp_obj_t machine_dac_read_mv(mp_obj_t self_in) {
+    machine_dac_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    return MP_OBJ_NEW_SMALL_INT(self->mv);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_dac_read_mv_obj, machine_dac_read_mv);
+
+// MP_DEFINE_CONST_FUN_OBJ_2(mp_machine_dac_write_obj, mp_machine_dac_write);
+
+STATIC const mp_rom_map_elem_t machine_dac_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_dac_deinit_obj) },
+    { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&machine_dac_read_obj) },
+    { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&machine_dac_write_obj) },
+    { MP_ROM_QSTR(MP_QSTR_read_mv), MP_ROM_PTR(&machine_dac_read_mv_obj) },
+    { MP_ROM_QSTR(MP_QSTR_write_mv), MP_ROM_PTR(&machine_dac_write_mv_obj) }
+};
+
+STATIC MP_DEFINE_CONST_DICT(machine_dac_locals_dict, machine_dac_locals_dict_table);
+
+MP_DEFINE_CONST_OBJ_TYPE(
+    machine_dac_type,
+    MP_QSTR_DAC,
+    MP_TYPE_FLAG_NONE,
+    make_new, machine_dac_make_new,
+    print, machine_dac_print,
+    locals_dict, &machine_dac_locals_dict
+    );
+
+#endif // MICROPY_PY_MACHINE_DAC
diff --git a/ports/renesas-ra/machine_pwm.c b/ports/renesas-ra/machine_pwm.c
new file mode 100644
index 0000000000..f2199805a1
--- /dev/null
+++ b/ports/renesas-ra/machine_pwm.c
@@ -0,0 +1,357 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2016 Damien P. George
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "py/mperrno.h"
+#include "extmod/machine_pwm.h"
+#include "pin.h"
+#include "ra/ra_gpt.h"
+#include "modmachine.h"
+
+#if MICROPY_HW_ENABLE_HW_PWM
+
+typedef struct _machine_pwm_obj_t {
+    mp_obj_base_t base;
+    R_GPT0_Type *pwm_inst;
+    uint8_t active;
+    uint8_t ch;
+    uint8_t id;
+    uint8_t duty;
+    uint32_t freq;
+    mp_hal_pin_obj_t pwm;
+} machine_pwm_obj_t;
+
+STATIC machine_pwm_obj_t machine_pwm_obj[] = {
+    #if defined(MICROPY_HW_PWM_0A)
+    {{&machine_pwm_type}, R_GPT0, 0, 0, 'A', 0, 0ul, MICROPY_HW_PWM_0A},
+    #endif
+    #if defined(MICROPY_HW_PWM_0B)
+    {{&machine_pwm_type}, R_GPT0, 0, 0, 'B', 0, 0ul, MICROPY_HW_PWM_0B},
+    #endif
+    #if defined(MICROPY_HW_PWM_1A)
+    {{&machine_pwm_type}, R_GPT1, 0, 1, 'A', 0, 0ul, MICROPY_HW_PWM_1A},
+    #endif
+    #if defined(MICROPY_HW_PWM_1B)
+    {{&machine_pwm_type}, R_GPT1, 0, 1, 'B', 0, 0ul, MICROPY_HW_PWM_1B},
+    #endif
+    #if defined(MICROPY_HW_PWM_2A)
+    {{&machine_pwm_type}, R_GPT2, 0, 2, 'A', 0, 0ul, MICROPY_HW_PWM_2A},
+    #endif
+    #if defined(MICROPY_HW_PWM_2B)
+    {{&machine_pwm_type}, R_GPT2, 0, 2, 'B', 0, 0ul, MICROPY_HW_PWM_2B},
+    #endif
+    #if defined(MICROPY_HW_PWM_3A)
+    {{&machine_pwm_type}, R_GPT3, 0, 3, 'A', 0, 0ul, MICROPY_HW_PWM_3A},
+    #endif
+    #if defined(MICROPY_HW_PWM_3B)
+    {{&machine_pwm_type}, R_GPT3, 0, 3, 'B', 0, 0ul, MICROPY_HW_PWM_3B},
+    #endif
+    #if defined(MICROPY_HW_PWM_4A)
+    {{&machine_pwm_type}, R_GPT4, 0, 4, 'A', 0, 0ul, MICROPY_HW_PWM_4A},
+    #endif
+    #if defined(MICROPY_HW_PWM_4B)
+    {{&machine_pwm_type}, R_GPT4, 0, 4, 'B', 0, 0ul, MICROPY_HW_PWM_4B},
+    #endif
+    #if defined(MICROPY_HW_PWM_5A)
+    {{&machine_pwm_type}, R_GPT5, 0, 5, 'A', 0, 0ul, MICROPY_HW_PWM_5A},
+    #endif
+    #if defined(MICROPY_HW_PWM_5B)
+    {{&machine_pwm_type}, R_GPT5, 0, 5, 'B', 0, 0ul, MICROPY_HW_PWM_5B},
+    #endif
+    #if defined(MICROPY_HW_PWM_6A)
+    {{&machine_pwm_type}, R_GPT6, 0, 6, 'A', 0, 0ul, MICROPY_HW_PWM_6A},
+    #endif
+    #if defined(MICROPY_HW_PWM_6B)
+    {{&machine_pwm_type}, R_GPT6, 0, 6, 'B', 0, 0ul, MICROPY_HW_PWM_6B},
+    #endif
+    #if defined(MICROPY_HW_PWM_7A)
+    {{&machine_pwm_type}, R_GPT7, 0, 7, 'A', 0, 0ul, MICROPY_HW_PWM_7A},
+    #endif
+    #if defined(MICROPY_HW_PWM_7B)
+    {{&machine_pwm_type}, R_GPT7, 0, 7, 'B', 0, 0ul, MICROPY_HW_PWM_7B},
+    #endif
+    #if defined(MICROPY_HW_PWM_8A)
+    {{&machine_pwm_type}, R_GPT8, 0, 8, 'A', 0, 0ul, MICROPY_HW_PWM_8A},
+    #endif
+    #if defined(MICROPY_HW_PWM_8B)
+    {{&machine_pwm_type}, R_GPT8, 0, 8, 'B', 0, 0ul, MICROPY_HW_PWM_8B},
+    #endif
+    #if defined(MICROPY_HW_PWM_9A)
+    {{&machine_pwm_type}, R_GPT9, 0, 9, 'A', 0, 0ul, MICROPY_HW_PWM_9A},
+    #endif
+    #if defined(MICROPY_HW_PWM_9B)
+    {{&machine_pwm_type}, R_GPT9, 0, 9, 'B', 0, 0ul, MICROPY_HW_PWM_9B},
+    #endif
+    #if defined(MICROPY_HW_PWM_10A)
+    {{&machine_pwm_type}, R_GPT10, 0, 10, 'A', 0, 0ul, MICROPY_HW_PWM_10A},
+    #endif
+    #if defined(MICROPY_HW_PWM_10B)
+    {{&machine_pwm_type}, R_GPT10, 0, 10, 'B', 0, 0ul, MICROPY_HW_PWM_10B},
+    #endif
+    #if defined(MICROPY_HW_PWM_11A)
+    {{&machine_pwm_type}, R_GPT11, 0, 11, 'A', 0, 0ul, MICROPY_HW_PWM_11A},
+    #endif
+    #if defined(MICROPY_HW_PWM_11B)
+    {{&machine_pwm_type}, R_GPT11, 0, 11, 'B', 0, 0ul, MICROPY_HW_PWM_11B},
+    #endif
+    #if defined(MICROPY_HW_PWM_12A)
+    {{&machine_pwm_type}, R_GPT12, 0, 12, 'A', 0, 0ul, MICROPY_HW_PWM_12A},
+    #endif
+    #if defined(MICROPY_HW_PWM_12B)
+    {{&machine_pwm_type}, R_GPT12, 0, 12, 'B', 0, 0ul, MICROPY_HW_PWM_12B},
+    #endif
+    #if defined(MICROPY_HW_PWM_13A)
+    {{&machine_pwm_type}, R_GPT13, 0, 13, 'A', 0, 0ul, MICROPY_HW_PWM_13A},
+    #endif
+    #if defined(MICROPY_HW_PWM_13B)
+    {{&machine_pwm_type}, R_GPT13, 0, 13, 'B', 0, 0ul, MICROPY_HW_PWM_13B}
+    #endif
+};
+
+/******************************************************************************/
+// MicroPython bindings for PWM
+
+STATIC void mp_machine_pwm_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
+    machine_pwm_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    mp_printf(print, "PWM(GTIOC %d%c[#%d], runing=%u, freq=%u, duty=%u)", self->ch, self->id, self->pwm->pin, self->active, self->freq, self->duty);
+}
+
+STATIC void mp_machine_pwm_init_helper(machine_pwm_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    uint32_t D = 0ul;
+
+    enum { ARG_freq, ARG_duty };
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_freq, MP_ARG_INT, {.u_int = -1} },
+        { MP_QSTR_duty, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }
+    };
+
+    mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+    if (args[ARG_freq].u_int != -1) {
+        if ((args[ARG_freq].u_int < 0) || (args[ARG_freq].u_int > 24000000)) {
+            mp_raise_ValueError(MP_ERROR_TEXT("freq should be 0-24000000"));
+        } else {
+            self->freq = args[ARG_freq].u_int;
+        }
+    }
+
+    ra_gpt_timer_init(self->pwm->pin, self->ch, self->id, 0, (float)self->freq);
+
+    if (args[ARG_duty].u_int != -1) {
+        if ((args[ARG_duty].u_int < 0) || (args[ARG_duty].u_int > 100)) {
+            mp_raise_ValueError(MP_ERROR_TEXT("duty should be 0-100"));
+        } else {
+            self->duty = args[ARG_duty].u_int;
+        }
+    }
+
+    D = self->duty * ra_gpt_timer_get_period(self->ch);
+    ra_gpt_timer_set_duty(self->ch, self->id, (uint32_t)(D / 100));
+
+    if (self->duty && self->freq) {
+        ra_gpt_timer_start(self->ch);
+        self->active = 1;
+    }
+}
+
+STATIC mp_obj_t mp_machine_pwm_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
+    mp_hal_pin_obj_t pin_id = MP_OBJ_NULL;
+    machine_pwm_obj_t *self = MP_OBJ_NULL;
+
+    enum { ARG_pin, ARG_freq, ARG_duty };
+    static const mp_arg_t allowed_args[] = {
+        { MP_QSTR_pin,  MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+        { MP_QSTR_freq, MP_ARG_INT, {.u_int = -1} },
+        { MP_QSTR_duty, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }
+    };
+
+    mp_arg_check_num(n_args, n_kw, 1, 3, true);
+    mp_arg_val_t init_args[MP_ARRAY_SIZE(allowed_args)];
+    mp_arg_parse_all_kw_array(n_args, n_kw, args, MP_ARRAY_SIZE(allowed_args), allowed_args, init_args);
+
+    // Get GPIO and optional device to connect to PWM.
+    pin_id = mp_hal_get_pin_obj(init_args[ARG_pin].u_obj);
+
+    if (pin_id) {
+        for (int i = 0; i < MP_ARRAY_SIZE(machine_pwm_obj); i++) {
+            if (pin_id->pin == machine_pwm_obj[i].pwm->pin) {
+                self = &machine_pwm_obj[i];
+                break;
+            }
+        }
+
+        if (self) {
+            if (ra_gpt_timer_is_pwm_pin(self->pwm->pin)) {
+                // start the PWM running for this channel
+                mp_map_t kw_args;
+                mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
+                mp_machine_pwm_init_helper(self, n_args - 1, args + 1, &kw_args);
+            } else {
+                mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%d) has no timer output"), self->pwm->pin);
+            }
+        } else {
+            mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%d) is used with other peripheral"), pin_id->pin);
+        }
+    } else {
+        mp_raise_ValueError(MP_ERROR_TEXT("Pin doesn't exist"));
+    }
+
+    return MP_OBJ_FROM_PTR(self);
+}
+
+STATIC void mp_machine_pwm_deinit(machine_pwm_obj_t *self) {
+    ra_gpt_timer_deinit(self->pwm->pin, self->ch, self->id);
+    self->active = 0;
+    self->ch = 0;
+    self->id = ' ';
+    self->duty = 0;
+    self->freq = 0;
+}
+
+STATIC mp_obj_t mp_machine_pwm_freq_get(machine_pwm_obj_t *self) {
+    return MP_OBJ_NEW_SMALL_INT((uint32_t)ra_gpt_timer_get_freq(self->ch));
+}
+
+STATIC void mp_machine_pwm_freq_set(machine_pwm_obj_t *self, mp_int_t freq) {
+    if (freq) {
+        ra_gpt_timer_set_freq(self->ch, (float)freq);
+        self->freq = (uint32_t)ra_gpt_timer_get_freq(self->ch);
+        if (!self->freq) {
+            mp_raise_ValueError(MP_ERROR_TEXT("freq should be 0-24000000"));
+        } else
+        if (!self->active) {
+            ra_gpt_timer_start(self->ch);
+            self->active = 1;
+        }
+    } else {
+        ra_gpt_timer_stop(self->ch);
+        ra_gpt_timer_set_freq(self->ch, (float)freq);
+        self->freq = 0;
+        self->active = 0;
+    }
+}
+
+STATIC mp_obj_t mp_machine_pwm_duty_get(machine_pwm_obj_t *self) {
+    // give the result in %
+    uint64_t Dc = ra_gpt_timer_get_duty(self->ch, self->id) * 100;
+    return MP_OBJ_NEW_SMALL_INT(Dc / ra_gpt_timer_get_period(self->ch));
+}
+
+STATIC void mp_machine_pwm_duty_set(machine_pwm_obj_t *self, mp_int_t duty) {
+    // assume duty is in %
+    if (duty < 0 || duty > 100) {
+        mp_raise_ValueError(MP_ERROR_TEXT("duty should be 0-100"));
+    } else {
+        if (duty) {
+            uint64_t D = (uint8_t)(duty) * ra_gpt_timer_get_period(self->ch);
+            ra_gpt_timer_set_duty(self->ch, self->id, (uint32_t)(D / 100));
+            self->duty = (uint8_t)duty;
+
+            if (!self->active && self->freq) {
+                ra_gpt_timer_start(self->ch);
+                self->active = 1;
+            }
+        } else {
+            if (self->active) {
+                ra_gpt_timer_stop(self->ch);
+                ra_gpt_timer_set_duty(self->ch, self->id, 0);
+                self->duty = 0;
+                self->active = 0;
+            }
+        }
+    }
+}
+
+STATIC mp_obj_t mp_machine_pwm_duty_get_u16(machine_pwm_obj_t *self) {
+    // give the result in ratio (u16 / 65535)
+    uint64_t Dc = ra_gpt_timer_get_duty(self->ch, self->id) * 65535;
+    return MP_OBJ_NEW_SMALL_INT(Dc / ra_gpt_timer_get_period(self->ch));
+}
+
+STATIC void mp_machine_pwm_duty_set_u16(machine_pwm_obj_t *self, mp_int_t duty_u16) {
+    // assume duty is a ratio (u16 / 65535)
+    if (duty_u16 < 0 || duty_u16 > 65535) {
+        mp_raise_ValueError(MP_ERROR_TEXT("duty should be 0-65535"));
+    } else {
+        if (duty_u16) {
+            uint64_t D = duty_u16 * ra_gpt_timer_get_period(self->ch);
+            ra_gpt_timer_set_duty(self->ch, self->id, (uint32_t)(D / 65535));
+            self->duty = (uint8_t)((duty_u16 * 100) / 65535);
+
+            if (!self->active && self->freq) {
+                ra_gpt_timer_start(self->ch);
+                self->active = 1;
+            }
+        } else {
+            if (self->active) {
+                ra_gpt_timer_stop(self->ch);
+                ra_gpt_timer_set_duty(self->ch, self->id, 0);
+                self->duty = 0;
+                self->active = 0;
+            }
+        }
+    }
+}
+
+STATIC mp_obj_t mp_machine_pwm_duty_get_ns(machine_pwm_obj_t *self) {
+    // give the result in ns
+    float ns = ra_gpt_timer_tick_time(self->ch);
+    ns *= (float)ra_gpt_timer_get_duty(self->ch, self->id);
+    return MP_OBJ_NEW_SMALL_INT(ns);
+}
+
+STATIC void mp_machine_pwm_duty_set_ns(machine_pwm_obj_t *self, mp_int_t duty_ns) {
+    // assume duty is ns
+    uint32_t ns_min = (uint32_t)ra_gpt_timer_tick_time(self->ch);
+    uint32_t ns_max = ns_min * ra_gpt_timer_get_period(self->ch);
+    if (duty_ns) {
+        if (duty_ns < ns_min || duty_ns > ns_max) {
+            mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("duty should be in period range %d-%d"), ns_min, ns_max);
+        } else {
+            uint32_t D = (uint32_t)duty_ns / ns_min;
+            ra_gpt_timer_set_duty(self->ch, self->id, D);
+            D *= ns_min * 100;
+            self->duty = D / ns_max;
+
+            if (!self->active && self->freq) {
+                ra_gpt_timer_start(self->ch);
+                self->active = 1;
+            }
+        }
+    } else {
+        if (self->active) {
+            ra_gpt_timer_stop(self->ch);
+            ra_gpt_timer_set_duty(self->ch, self->id, 0);
+            self->duty = 0;
+            self->active = 0;
+        }
+    }
+}
+
+#endif // MICROPY_HW_ENABLE_HW_PWM
diff --git a/ports/renesas-ra/machine_sdcard.c b/ports/renesas-ra/machine_sdcard.c
new file mode 100644
index 0000000000..2ed0d66535
--- /dev/null
+++ b/ports/renesas-ra/machine_sdcard.c
@@ -0,0 +1,338 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/mpconfig.h"
+#include "py/runtime.h"
+#include "py/mphal.h"
+#include "py/mperrno.h"
+#include "modmachine.h"
+#include "extmod/vfs.h"
+#include "hal_data.h"
+#include "led.h"
+
+#if MICROPY_HW_HAS_SDHI_CARD
+
+#define CARD_HOLDER    1000  // 500 ms
+#define CARD_OPERATION  200  // 100 ms
+
+static volatile uint8_t OP_complete = 0;
+
+typedef struct _machine_sdcard_obj_t {
+    mp_obj_base_t base;
+    sdmmc_status_t status;
+    uint16_t block_len;
+    uint32_t block_count;
+} machine_sdcard_obj_t;
+
+STATIC machine_sdcard_obj_t machine_sdcard_objs[] = {
+    {{&machine_sdcard_type}, {false, false, false}, 0, 0}
+};
+
+void sdhi_ISR(sdmmc_callback_args_t *p_args) {
+    switch (p_args->event)
+    {
+        case SDMMC_EVENT_CARD_INSERTED:
+            machine_sdcard_objs[0].status.card_inserted = true;
+            OP_complete = 0;
+            break;
+
+        case SDMMC_EVENT_CARD_REMOVED:
+            machine_sdcard_objs[0].status.card_inserted = false;
+            machine_sdcard_objs[0].status.initialized = false;
+            machine_sdcard_objs[0].block_count = 0;
+            break;
+
+        case SDMMC_EVENT_ERASE_COMPLETE:
+        case SDMMC_EVENT_TRANSFER_COMPLETE:
+            OP_complete = 0;
+            break;
+
+        // case SDMMC_EVENT_ERASE_BUSY:
+        // case SDMMC_EVENT_TRANSFER_ERROR:
+
+        default:
+            break;
+    }
+}
+
+STATIC mp_obj_t machine_sdcard_init(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+    fsp_err_t err = FSP_SUCCESS;
+    machine_sdcard_obj_t *self = mp_const_none;
+
+    if (g_sdmmc0_ctrl.open) {
+    check:
+        if ((err = R_SDHI_StatusGet(&g_sdmmc0_ctrl, &self->status)) == FSP_SUCCESS) {
+            self = &machine_sdcard_objs[0];
+            if (!self->status.initialized && self->status.card_inserted) {
+                if ((err = R_SDHI_MediaInit(&g_sdmmc0_ctrl, NULL)) == FSP_SUCCESS) {
+                    self->status.initialized = true;
+                    self->block_len = g_sdmmc0_ctrl.device.sector_size_bytes;
+                    self->block_count = g_sdmmc0_ctrl.device.sector_count;
+                } else {
+                    mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("can't init SDHI card, %d"), err);
+                }
+            }
+        } else {
+            mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("can't get SDHI Status, %d"), err);
+        }
+    } else {
+        if ((err = R_SDHI_Open(&g_sdmmc0_ctrl, &g_sdmmc0_cfg)) == FSP_SUCCESS) {
+            uint32_t Istamp = mp_hal_ticks_ms();
+            OP_complete = 1;
+            while (OP_complete) {
+                if ((mp_hal_ticks_ms() - Istamp) > CARD_HOLDER) {
+                    OP_complete = 0;
+                    Istamp = 0;
+                }
+            }
+
+            goto check;
+        } else {
+            mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("can't open SDHI controller, %d"), err);
+        }
+    }
+
+    return MP_OBJ_FROM_PTR(self);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_sdcard_init_obj, 1, machine_sdcard_init);
+
+STATIC mp_obj_t sdcard_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
+    mp_map_t kw_args;
+
+    mp_arg_check_num(n_args, n_kw, 0, 0, true);
+    mp_map_init_fixed_table(&kw_args, n_kw, all_args + n_args);
+    return machine_sdcard_init(n_args, all_args, &kw_args);
+}
+
+// deinit()
+STATIC mp_obj_t machine_sdcard_deinit(mp_obj_t self_in) {
+    machine_sdcard_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    R_SDHI_Close(&g_sdmmc0_ctrl);
+    self->block_count = self->block_len = 0;
+    self->status.card_inserted = self->status.initialized = self->status.transfer_in_progress = false;
+    return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_sdcard_deinit_obj, machine_sdcard_deinit);
+
+// present()
+STATIC mp_obj_t machine_sdcard_present(mp_obj_t self_in) {
+    fsp_err_t err = FSP_SUCCESS;
+    machine_sdcard_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    if ((err = R_SDHI_StatusGet(&g_sdmmc0_ctrl, &self->status)) == FSP_SUCCESS) {
+        return mp_obj_new_bool(self->status.card_inserted);
+    } else {
+        mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("can't get SDHI Status, %d"), err);
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_sdcard_present_obj, machine_sdcard_present);
+
+STATIC mp_obj_t machine_sdcard_info(mp_obj_t self_in) {
+    machine_sdcard_obj_t *self = MP_OBJ_TO_PTR(self_in);
+
+    if (self->status.card_inserted && self->status.initialized) {
+        uint32_t log_block_nbr = self->block_count;
+        uint32_t log_block_size = self->block_len;
+
+        mp_obj_t tuple[2] = {
+            mp_obj_new_int_from_ull((uint64_t)log_block_nbr * (uint64_t)log_block_size),
+            mp_obj_new_int_from_uint(log_block_size),
+        };
+        return mp_obj_new_tuple(2, tuple);
+    } else {
+        return mp_const_none;
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_sdcard_info_obj, machine_sdcard_info);
+
+// readblocks(block_num, buf)
+STATIC mp_obj_t machine_sdcard_readblocks(mp_obj_t self_in, mp_obj_t block_num, mp_obj_t buf) {
+    mp_buffer_info_t bufinfo;
+    machine_sdcard_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    mp_get_buffer_raise(buf, &bufinfo, MP_BUFFER_WRITE);
+
+    if ((self->status.initialized) && (FSP_SUCCESS == R_SDHI_Read(&g_sdmmc0_ctrl, bufinfo.buf, mp_obj_get_int(block_num), bufinfo.len / g_sdmmc0_cfg.block_size))) {
+        uint32_t Rstamp = mp_hal_ticks_ms();
+        OP_complete = 1;
+        while (OP_complete) {
+            if ((mp_hal_ticks_ms() - Rstamp) > CARD_OPERATION) {
+                OP_complete = 0;
+                Rstamp = 0;
+            }
+        }
+
+        return Rstamp? MP_OBJ_NEW_SMALL_INT(0) : MP_OBJ_NEW_SMALL_INT(-MP_EIO);
+    } else {
+        return MP_OBJ_NEW_SMALL_INT(-MP_EIO);
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_3(machine_sdcard_readblocks_obj, machine_sdcard_readblocks);
+
+// writeblocks(block_num, buf)
+STATIC mp_obj_t machine_sdcard_writeblocks(mp_obj_t self_in, mp_obj_t block_num, mp_obj_t buf) {
+    mp_buffer_info_t bufinfo;
+    machine_sdcard_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    mp_get_buffer_raise(buf, &bufinfo, MP_BUFFER_WRITE);
+
+    if ((self->status.initialized) && (FSP_SUCCESS == R_SDHI_Write(&g_sdmmc0_ctrl, bufinfo.buf, mp_obj_get_int(block_num), bufinfo.len / g_sdmmc0_cfg.block_size))) {
+        uint32_t Wstamp = mp_hal_ticks_ms();
+        OP_complete = 1;
+        while (OP_complete) {
+            if ((mp_hal_ticks_ms() - Wstamp) > CARD_OPERATION) {
+                OP_complete = 0;
+                Wstamp = 0;
+            }
+        }
+
+        return Wstamp? MP_OBJ_NEW_SMALL_INT(0) : MP_OBJ_NEW_SMALL_INT(-MP_EIO);
+    } else {
+        return MP_OBJ_NEW_SMALL_INT(-MP_EIO);
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_3(machine_sdcard_writeblocks_obj, machine_sdcard_writeblocks);
+
+// ioctl(op, arg)
+STATIC mp_obj_t machine_sdcard_ioctl(mp_obj_t self_in, mp_obj_t cmd_in, mp_obj_t arg_in) {
+    machine_sdcard_obj_t *self = MP_OBJ_TO_PTR(self_in);
+    mp_int_t cmd = mp_obj_get_int(cmd_in);
+
+    switch (cmd) {
+        case MP_BLOCKDEV_IOCTL_INIT: {
+            if (!g_sdmmc0_ctrl.open) {
+                if (FSP_SUCCESS == R_SDHI_Open(&g_sdmmc0_ctrl, &g_sdmmc0_cfg)) {
+                    uint32_t Istamp = mp_hal_ticks_ms();
+                    OP_complete = 1;
+                    while (OP_complete) {
+                        if ((mp_hal_ticks_ms() - Istamp) > CARD_OPERATION) {
+                            OP_complete = 0;
+                            Istamp = 0;
+                        }
+                    }
+                } else {
+                    return MP_OBJ_NEW_SMALL_INT(-MP_EIO);
+                }
+            }
+
+            R_SDHI_StatusGet(&g_sdmmc0_ctrl, &self->status);
+
+            if (self->status.card_inserted) {
+                if (!self->status.initialized) {
+                    if (FSP_SUCCESS == R_SDHI_MediaInit(&g_sdmmc0_ctrl, NULL)) {
+                        self->status.initialized = true;
+                        self->block_len = g_sdmmc0_ctrl.device.sector_size_bytes;
+                        self->block_count = g_sdmmc0_ctrl.device.sector_count;
+                        return MP_OBJ_NEW_SMALL_INT(0);
+                    } else {
+                        return MP_OBJ_NEW_SMALL_INT(-MP_EIO); // Initialization failed
+                    }
+                } else {
+                    return MP_OBJ_NEW_SMALL_INT(0);
+                }
+            } else {
+                return MP_OBJ_NEW_SMALL_INT(-MP_EIO);  // Initialization failed
+            }
+        }
+        break;
+
+        case MP_BLOCKDEV_IOCTL_DEINIT: {
+            if (g_sdmmc0_ctrl.open) {
+                R_SDHI_Close(&g_sdmmc0_ctrl);
+                self->block_count = self->block_len = 0;
+                self->status.card_inserted = self->status.initialized = self->status.transfer_in_progress = false;
+                return MP_OBJ_NEW_SMALL_INT(0);
+            } else {
+                return MP_OBJ_NEW_SMALL_INT(-MP_EIO);  // Deinitialization failed
+            }
+        }
+        break;
+
+        case MP_BLOCKDEV_IOCTL_SYNC: {
+            return MP_OBJ_NEW_SMALL_INT(0);
+        }
+        break;
+
+        case MP_BLOCKDEV_IOCTL_BLOCK_COUNT: {
+            if (self->status.initialized) {
+                return MP_OBJ_NEW_SMALL_INT(self->block_count);
+            } else {
+                return MP_OBJ_NEW_SMALL_INT(-MP_EIO);  // Card not initialized
+            }
+        }
+        break;
+
+        case MP_BLOCKDEV_IOCTL_BLOCK_SIZE: {
+            if (self->status.initialized) {
+                return MP_OBJ_NEW_SMALL_INT(self->block_len);
+            } else {
+                return MP_OBJ_NEW_SMALL_INT(-MP_EIO);  // Card not initialized
+            }
+        }
+        break;
+
+        case MP_BLOCKDEV_IOCTL_BLOCK_ERASE: {
+            if (self->status.initialized) {
+                uint32_t Estamp = mp_hal_ticks_ms();
+                OP_complete = 1;
+                while (OP_complete) {
+                    if ((mp_hal_ticks_ms() - Estamp) > CARD_OPERATION) {
+                        OP_complete = 0;
+                        Estamp = 0;
+                    }
+                }
+
+                return Estamp? MP_OBJ_NEW_SMALL_INT(0) : MP_OBJ_NEW_SMALL_INT(-MP_EIO);
+            } else {
+                return MP_OBJ_NEW_SMALL_INT(-MP_EIO);  // Card not initialized
+            }
+        }
+
+        default: // unknown command
+            return mp_const_none;
+            break;
+    }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_3(machine_sdcard_ioctl_obj, machine_sdcard_ioctl);
+
+STATIC const mp_rom_map_elem_t sdcard_locals_dict_table[] = {
+    { MP_ROM_QSTR(MP_QSTR_init),        MP_ROM_PTR(&machine_sdcard_init_obj) },
+    { MP_ROM_QSTR(MP_QSTR_deinit),      MP_ROM_PTR(&machine_sdcard_deinit_obj) },
+    { MP_ROM_QSTR(MP_QSTR_present),     MP_ROM_PTR(&machine_sdcard_present_obj) },
+    { MP_ROM_QSTR(MP_QSTR_info),        MP_ROM_PTR(&machine_sdcard_info_obj) },
+    // block device protocol
+    { MP_ROM_QSTR(MP_QSTR_readblocks),  MP_ROM_PTR(&machine_sdcard_readblocks_obj) },
+    { MP_ROM_QSTR(MP_QSTR_writeblocks), MP_ROM_PTR(&machine_sdcard_writeblocks_obj) },
+    { MP_ROM_QSTR(MP_QSTR_ioctl),       MP_ROM_PTR(&machine_sdcard_ioctl_obj) },
+};
+STATIC MP_DEFINE_CONST_DICT(sdcard_locals_dict, sdcard_locals_dict_table);
+
+MP_DEFINE_CONST_OBJ_TYPE(
+    machine_sdcard_type,
+    MP_QSTR_SDCard,
+    MP_TYPE_FLAG_NONE,
+    make_new, sdcard_obj_make_new,
+    locals_dict, &sdcard_locals_dict
+    );
+
+#endif // MICROPY_PY_MACHINE_SDCARD
diff --git a/ports/renesas-ra/machine_spi.c b/ports/renesas-ra/machine_spi.c
index 2c71c83b66..8c0c026d9a 100644
--- a/ports/renesas-ra/machine_spi.c
+++ b/ports/renesas-ra/machine_spi.c
@@ -86,6 +86,47 @@ STATIC machine_hard_spi_obj_t machine_hard_spi_obj[] = {
     #endif
 };
 
+STATIC void spi_init(machine_hard_spi_obj_t *self) {
+    const machine_pin_obj_t *pins[4] = { NULL, NULL, NULL, NULL };
+
+    if (0) {
+    #if defined(MICROPY_HW_SPI0_RSPCK)
+    } else if (self->spi_id == 0) {
+        #if defined(MICROPY_HW_SPI0_SSL)
+        pins[0] = MICROPY_HW_SPI0_SSL;
+        #endif
+        #if defined(MICROPY_HW_SPI0_RSPCK)
+        pins[1] = MICROPY_HW_SPI0_RSPCK;
+        #endif
+        #if defined(MICROPY_HW_SPI0_MISO)
+        pins[2] = MICROPY_HW_SPI0_MISO;
+        #endif
+        #if defined(MICROPY_HW_SPI0_MOSI)
+        pins[3] = MICROPY_HW_SPI0_MOSI;
+        #endif
+    #endif
+    #if defined(MICROPY_HW_SPI1_RSPCK)
+    } else if (self->spi_id == 1) {
+        #if defined(MICROPY_HW_SPI1_SSL)
+        pins[0] = MICROPY_HW_SPI1_SSL;
+        #endif
+        #if defined(MICROPY_HW_SPI1_RSPCK)
+        pins[1] = MICROPY_HW_SPI1_RSPCK;
+        #endif
+        #if defined(MICROPY_HW_SPI1_MISO)
+        pins[2] = MICROPY_HW_SPI1_MISO;
+        #endif
+        #if defined(MICROPY_HW_SPI1_MOSI)
+        pins[3] = MICROPY_HW_SPI1_MOSI;
+        #endif
+    #endif
+    } else {
+        // SPI does not exist for this board (shouldn't get here, should be checked by caller)
+        return;
+    }
+    ra_spi_init(self->spi_id, pins[3]->pin, pins[2]->pin, pins[1]->pin, pins[0]->pin, self->baudrate, self->bits, self->polarity, self->phase, self->firstbit);
+}
+
 STATIC void machine_hard_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
     machine_hard_spi_obj_t *self = MP_OBJ_TO_PTR(self_in);
     mp_printf(print, "SPI(%u, baudrate=%u, polarity=%u, phase=%u, bits=%u, firstbit=%u, sck=%q, mosi=%q, miso=%q)",
@@ -189,10 +230,7 @@ mp_obj_t machine_hard_spi_make_new(const mp_obj_type_t *type, size_t n_args, siz
         }
     }
     // init the SPI bus
-    spi_init(self->spi_id);
-    // set configurable paramaters
-    spi_set_params(self->spi_id, self->baudrate, self->polarity,
-        self->phase, self->bits, self->firstbit);
+    spi_init(self);
     return MP_OBJ_FROM_PTR(self);
 }
 
@@ -275,10 +313,7 @@ STATIC void machine_hard_spi_init(mp_obj_base_t *self_in, size_t n_args, const m
     }
 
     // init the SPI bus
-    spi_init(self->spi_id);
-    // set configurable paramaters
-    spi_set_params(self->spi_id, self->baudrate, self->polarity,
-        self->phase, self->bits, self->firstbit);
+    spi_init(self);
 }
 
 STATIC void machine_hard_spi_deinit(mp_obj_base_t *self_in) {
@@ -310,58 +345,6 @@ MP_DEFINE_CONST_OBJ_TYPE(
 void spi_init0(void) {
 }
 
-// sets the parameters in the SPI_InitTypeDef struct
-// if an argument is -1 then the corresponding parameter is not changed
-void spi_set_params(uint32_t ch, int32_t baudrate,
-    int32_t polarity, int32_t phase, int32_t bits, int32_t firstbit) {
-    ra_spi_set_mode(ch, polarity, phase);
-    ra_spi_set_clk(ch, baudrate);
-    ra_spi_set_bits(ch, bits);
-    ra_spi_set_lsb_first(ch, firstbit);
-}
-
-void spi_init(uint32_t ch) {
-    const machine_pin_obj_t *pins[4] = { NULL, NULL, NULL, NULL };
-
-    if (0) {
-    #if defined(MICROPY_HW_SPI0_RSPCK)
-    } else if (ch == 0) {
-        #if defined(MICROPY_HW_SPI0_SSL)
-        pins[0] = MICROPY_HW_SPI0_SSL;
-        #endif
-        #if defined(MICROPY_HW_SPI0_RSPCK)
-        pins[1] = MICROPY_HW_SPI0_RSPCK;
-        #endif
-        #if defined(MICROPY_HW_SPI0_MISO)
-        pins[2] = MICROPY_HW_SPI0_MISO;
-        #endif
-        #if defined(MICROPY_HW_SPI0_MOSI)
-        pins[3] = MICROPY_HW_SPI0_MOSI;
-        #endif
-        ra_spi_init(ch, pins[3]->pin, pins[2]->pin, pins[1]->pin, pins[0]->pin, DEFAULT_SPI_BAUDRATE, DEFAULT_SPI_BITS, DEFAULT_SPI_POLARITY, DEFAULT_SPI_PHASE);
-    #endif
-    #if defined(MICROPY_HW_SPI1_RSPCK)
-    } else if (ch == 1) {
-        #if defined(MICROPY_HW_SPI1_SSL)
-        pins[0] = MICROPY_HW_SPI1_SSL;
-        #endif
-        #if defined(MICROPY_HW_SPI1_RSPCK)
-        pins[1] = MICROPY_HW_SPI1_RSPCK;
-        #endif
-        #if defined(MICROPY_HW_SPI1_MISO)
-        pins[2] = MICROPY_HW_SPI1_MISO;
-        #endif
-        #if defined(MICROPY_HW_SPI1_MOSI)
-        pins[3] = MICROPY_HW_SPI1_MOSI;
-        #endif
-        ra_spi_init(ch, pins[3]->pin, pins[2]->pin, pins[1]->pin, pins[0]->pin, DEFAULT_SPI_BAUDRATE, DEFAULT_SPI_BITS, DEFAULT_SPI_POLARITY, DEFAULT_SPI_PHASE);
-    #endif
-    } else {
-        // SPI does not exist for this board (shouldn't get here, should be checked by caller)
-        return;
-    }
-}
-
 void spi_deinit(uint32_t ch) {
     if (0) {
     #if defined(MICROPY_HW_SPI0_RSPCK)
diff --git a/ports/renesas-ra/modmachine.c b/ports/renesas-ra/modmachine.c
index 47f7e8c805..bc85d9b7f8 100644
--- a/ports/renesas-ra/modmachine.c
+++ b/ports/renesas-ra/modmachine.c
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2013-2015 Damien P. George
  * Copyright (c) 2021,2022 Renesas Electronics Corporation
+ * Copyright (c) 2023 Vekatech Ltd.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -39,6 +40,7 @@
 #include "extmod/machine_pulse.h"
 #include "extmod/machine_i2c.h"
 #include "extmod/machine_spi.h"
+#include "extmod/machine_pwm.h"
 #include "shared/runtime/pyexec.h"
 #include "lib/oofatfs/ff.h"
 #include "extmod/vfs.h"
@@ -279,6 +281,9 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = {
 
     { MP_ROM_QSTR(MP_QSTR_RTC),                 MP_ROM_PTR(&machine_rtc_type) },
     { MP_ROM_QSTR(MP_QSTR_ADC),                 MP_ROM_PTR(&machine_adc_type) },
+    #if MICROPY_PY_MACHINE_DAC
+    { MP_ROM_QSTR(MP_QSTR_DAC),                 MP_ROM_PTR(&machine_dac_type) },
+    #endif
     #if MICROPY_PY_MACHINE_I2C
     #if MICROPY_HW_ENABLE_HW_I2C
     { MP_ROM_QSTR(MP_QSTR_I2C),                 MP_ROM_PTR(&machine_i2c_type) },
@@ -291,6 +296,14 @@ STATIC const mp_rom_map_elem_t machine_module_globals_table[] = {
     #endif
     { MP_ROM_QSTR(MP_QSTR_UART),                MP_ROM_PTR(&machine_uart_type) },
     { MP_ROM_QSTR(MP_QSTR_Timer),               MP_ROM_PTR(&machine_timer_type) },
+    #if MICROPY_PY_MACHINE_PWM
+    #if MICROPY_HW_ENABLE_HW_PWM
+    { MP_ROM_QSTR(MP_QSTR_PWM),                 MP_ROM_PTR(&machine_pwm_type) },
+    #endif
+    #endif
+    #if MICROPY_HW_HAS_SDHI_CARD
+    { MP_ROM_QSTR(MP_QSTR_SDCard),              MP_ROM_PTR(&machine_sdcard_type) },
+    #endif
     { MP_ROM_QSTR(MP_QSTR_PWRON_RESET),         MP_ROM_INT(PYB_RESET_POWER_ON) },
     { MP_ROM_QSTR(MP_QSTR_HARD_RESET),          MP_ROM_INT(PYB_RESET_HARD) },
     { MP_ROM_QSTR(MP_QSTR_WDT_RESET),           MP_ROM_INT(PYB_RESET_WDT) },
diff --git a/ports/renesas-ra/mpconfigboard_common.h b/ports/renesas-ra/mpconfigboard_common.h
index f63a924ad8..f8990f489e 100644
--- a/ports/renesas-ra/mpconfigboard_common.h
+++ b/ports/renesas-ra/mpconfigboard_common.h
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2018 Damien P. George
  * Copyright (c) 2021,2022 Renesas Electronics Corporation
+ * Copyright (c) 2023 Vekatech Ltd.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -63,6 +64,16 @@
 #define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE_SEGMENT2 (0)
 #endif
 
+// Whether to enable storage on the external QSPI flash of the MCU, instead of the internal flash
+#ifndef MICROPY_HW_HAS_QSPI_FLASH
+#define MICROPY_HW_HAS_QSPI_FLASH (0)
+#endif
+
+// Whether to enable access to SDCARD, through SDHI controller
+#ifndef MICROPY_HW_HAS_SDHI_CARD
+#define MICROPY_HW_HAS_SDHI_CARD (0)
+#endif
+
 // Whether to enable the RTC, exposed as pyb.RTC
 #ifndef MICROPY_HW_ENABLE_RTC
 #define MICROPY_HW_ENABLE_RTC (0)
@@ -209,6 +220,16 @@
 #define MICROPY_HW_MAX_UART (10)
 #define MICROPY_HW_MAX_LPUART (0)
 
+#elif defined(RA6M5)
+
+#define MP_HAL_UNIQUE_ID_ADDRESS (0x1ffff7ac)   /* To be fixed */
+// 16 IRQ + 1 EXTI_RTC_WAKEUP defined in exti.h
+#define PYB_EXTI_NUM_VECTORS (17)
+#define MICROPY_HW_MAX_TIMER (2)
+#define MICROPY_HW_MAX_UART (10)
+#define MICROPY_HW_MAX_LPUART (0)
+
+#else
 #error Unsupported MCU series
 #endif
 
@@ -240,5 +261,30 @@
 #define MICROPY_HW_ENABLE_HW_I2C (0)
 #endif
 
+#if defined(MICROPY_HW_PWM_0A) || defined(MICROPY_HW_PWM_0B) \
+    || defined(MICROPY_HW_PWM_1A) || defined(MICROPY_HW_PWM_1B) \
+    || defined(MICROPY_HW_PWM_2A) || defined(MICROPY_HW_PWM_2B) \
+    || defined(MICROPY_HW_PWM_3A) || defined(MICROPY_HW_PWM_3B) \
+    || defined(MICROPY_HW_PWM_4A) || defined(MICROPY_HW_PWM_4B) \
+    || defined(MICROPY_HW_PWM_5A) || defined(MICROPY_HW_PWM_5B) \
+    || defined(MICROPY_HW_PWM_6A) || defined(MICROPY_HW_PWM_6B) \
+    || defined(MICROPY_HW_PWM_7A) || defined(MICROPY_HW_PWM_7B) \
+    || defined(MICROPY_HW_PWM_8A) || defined(MICROPY_HW_PWM_8B) \
+    || defined(MICROPY_HW_PWM_9A) || defined(MICROPY_HW_PWM_9B) \
+    || defined(MICROPY_HW_PWM_10A) || defined(MICROPY_HW_PWM_10B) \
+    || defined(MICROPY_HW_PWM_11A) || defined(MICROPY_HW_PWM_11B) \
+    || defined(MICROPY_HW_PWM_12A) || defined(MICROPY_HW_PWM_12B) \
+    || defined(MICROPY_HW_PWM_13A) || defined(MICROPY_HW_PWM_13B)
+#define MICROPY_HW_ENABLE_HW_PWM (1)
+#else
+#define MICROPY_HW_ENABLE_HW_PWM (0)
+#endif
+
+#if defined(MICROPY_HW_DAC0) || defined(MICROPY_HW_DAC1)
+#define MICROPY_HW_ENABLE_HW_DAC (1)
+#else
+#define MICROPY_HW_ENABLE_HW_DAC (0)
+#endif
+
 // Pin definition header file
 #define MICROPY_PIN_DEFS_PORT_H "pin_defs_ra.h"
diff --git a/ports/renesas-ra/mpconfigport.h b/ports/renesas-ra/mpconfigport.h
index 434bc00f11..a4a0caa373 100644
--- a/ports/renesas-ra/mpconfigport.h
+++ b/ports/renesas-ra/mpconfigport.h
@@ -5,6 +5,7 @@
  *
  * Copyright (c) 2013-2017 Damien P. George
  * Copyright (c) 2021,2022 Renesas Electronics Corporation
+ * Copyright (c) 2023 Vekatech Ltd.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -117,6 +118,14 @@
 #define MICROPY_PY_MACHINE_SOFTSPI  (1)
 #define MICROPY_PY_MACHINE_TIMER    (1)
 #define MICROPY_SOFT_TIMER_TICKS_MS uwTick
+#if MICROPY_HW_ENABLE_HW_PWM
+#define MICROPY_PY_MACHINE_PWM      (1)
+#define MICROPY_PY_MACHINE_PWM_DUTY (1)
+#define MICROPY_PY_MACHINE_PWM_INCLUDEFILE  "ports/renesas-ra/machine_pwm.c"
+#endif
+#if MICROPY_HW_ENABLE_HW_DAC
+#define MICROPY_PY_MACHINE_DAC      (1)
+#endif
 #endif
 #define MICROPY_HW_SOFTSPI_MIN_DELAY (0)
 #define MICROPY_HW_SOFTSPI_MAX_BAUDRATE (48000000 / 48)
diff --git a/ports/renesas-ra/powerctrl.c b/ports/renesas-ra/powerctrl.c
index 8f9e25b724..26dc1cbe3a 100644
--- a/ports/renesas-ra/powerctrl.c
+++ b/ports/renesas-ra/powerctrl.c
@@ -175,7 +175,7 @@ const lpm_instance_t g_lpm_standby = {
 #endif
 
 NORETURN void powerctrl_mcu_reset(void) {
-    #if BSP_FEATURE_TZ_HAS_TRUSTZONE
+    #if BSP_TZ_SECURE_BUILD
     R_BSP_NonSecureEnter();
     #else
     NVIC_SystemReset();
diff --git a/ports/renesas-ra/ra/ra_adc.c b/ports/renesas-ra/ra/ra_adc.c
index e7a270a194..fc6583e80e 100644
--- a/ports/renesas-ra/ra/ra_adc.c
+++ b/ports/renesas-ra/ra/ra_adc.c
@@ -31,13 +31,13 @@
 #include "ra_utils.h"
 #include "ra_adc.h"
 
-static R_ADC0_Type *adc_reg = (R_ADC0_Type *)0x4005c000;
+static R_ADC0_Type *adc_reg = R_ADC0;
 #if defined(RA4M1) | defined(RA4W1)
 static R_TSN_Type *tsn_reg = (R_TSN_Type *)0x407ec000;
 #endif
-#if defined(RA6M1) | defined(RA6M2)
-static R_TSN_CTRL_Type *tsn_ctrl_reg = (R_TSN_CTRL_Type *)0x4005D000;
-static R_TSN_CAL_Type *tsn_cal_reg = (R_TSN_CAL_Type *)0x407FB17C;
+#if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
+static R_TSN_CTRL_Type *tsn_ctrl_reg = R_TSN_CTRL;
+static R_TSN_CAL_Type *tsn_cal_reg = R_TSN_CAL;
 #endif
 static uint8_t resolution = RA_ADC_DEF_RESOLUTION;
 
@@ -110,6 +110,63 @@ static const adc_pin_to_ch_t pin_to_ch[] = {
     { P506, AN019 },
     { P509, AN020 },
 
+    #elif defined(RA6M3)
+    { P000, AN000 },
+    { P001, AN001 },
+    { P002, AN002 },
+    { P003, AN007 },
+    { P004, AN100 },
+    { P005, AN101 },
+    { P006, AN102 },
+    { P007, AN107 },
+    { P008, AN003 },
+    { P009, AN004 },
+    { P010, AN103 },
+    { P014, AN005 },
+    { P014, AN105 },
+    { P015, AN006 },
+    { P015, AN106 },
+    { P500, AN016 },
+    { P501, AN116 },
+    { P502, AN017 },
+    { P503, AN117 },
+    { P504, AN018 },
+    { P505, AN118 },
+    { P506, AN019 },
+    { P507, AN119 },
+    { P508, AN020 },
+
+    #elif defined(RA6M5)
+    { P000, AN000 },
+    { P001, AN001 },
+    { P002, AN002 },
+    { P003, AN003 },
+    { P004, AN004 },
+    { P005, AN005 },
+    { P006, AN006 },
+    { P007, AN007 },
+    { P008, AN008 },
+    { P009, AN009 },
+    { P010, AN010 },
+    { P014, AN012 },
+    { P015, AN013 },
+    { P000, AN100 },
+    { P001, AN101 },
+    { P002, AN002 },
+    { P500, AN116 },
+    { P501, AN117 },
+    { P502, AN118 },
+    { P503, AN119 },
+    { P504, AN120 },
+    { P505, AN121 },
+    { P506, AN122 },
+    { P507, AN123 },
+    { P508, AN124 },
+    { P800, AN125 },
+    { P801, AN126 },
+    { P802, AN127 },
+    { P803, AN128 },
+
     #elif defined(RA6M1)
     { P000, AN000 },
     { P001, AN001 },
@@ -191,7 +248,7 @@ static void ra_adc0_module_stop(void) {
     ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD16_Msk);
 }
 
-#if defined(RA6M1) | defined(RA6M2)
+#if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
 static void ra_adc1_module_start(void) {
     ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD15_Msk);
 }
@@ -202,7 +259,7 @@ static void ra_adc1_module_stop(void) {
 #endif
 
 // For RA4M1 and RA4W1, there is no TSN configuration
-#if defined(RA6M1) | defined(RA6M2)
+#if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
 static void ra_tsn_module_start(void) {
     ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD22_Msk);
 }
@@ -324,7 +381,7 @@ uint8_t ra_adc_get_resolution(void) {
 uint16_t ra_adc_read_ch(uint8_t ch) {
     uint16_t value16 = 0;
     if ((ch == ADC_TEMP) | (ch == ADC_REF)) {
-        #if defined(RA6M1) | defined(RA6M2)
+        #if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
         if (ch == ADC_TEMP) {
             adc_reg->ADEXICR_b.TSSA = 1;
             tsn_ctrl_reg->TSCR_b.TSEN = 1;
@@ -360,7 +417,7 @@ uint16_t ra_adc_read_ch(uint8_t ch) {
     } else {
         value16 = (uint16_t)adc_reg->ADDR[ch];
     }
-    #if defined(RA6M1) | defined(RA6M2)
+    #if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     if (ch == ADC_TEMP) {
         tsn_ctrl_reg->TSCR_b.TSOE = 0;
         while (tsn_ctrl_reg->TSCR_b.TSOE) {
@@ -394,7 +451,7 @@ int16_t ra_adc_read_itemp(void) {
     int16_t v125 = (int16_t)(33 * cal125 / vmax / 10);
     int16_t vtemp = (int16_t)(33 * val / vmax / 10);
     temp = (int16_t)(125 + ((vtemp - v125) * 1000000 / (int16_t)BSP_FEATURE_ADC_TSN_SLOPE));
-    #elif defined(RA6M1) | defined(RA6M2)
+    #elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     uint16_t cal127 = (uint16_t)tsn_cal_reg->TSCDR;
     uint16_t val = ra_adc_read_ch(ADC_TEMP);
     int16_t v127 = (int16_t)(33 * cal127 / vmax / 10);
@@ -416,7 +473,7 @@ float ra_adc_read_ftemp(void) {
     float vtemp = (float)(3.3f * (float)val / vmax);
     temp = (float)(125.0f + ((vtemp - v125) * 1000000.0f / (float)BSP_FEATURE_ADC_TSN_SLOPE));
     #endif
-    #if defined(RA6M1) | defined(RA6M2)
+    #if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     uint16_t cal127 = (uint16_t)tsn_cal_reg->TSCDR;
     uint16_t val = ra_adc_read_ch(ADC_TEMP);
     float v127 = (float)(3.3f * (float)cal127 / vmax);
@@ -487,7 +544,7 @@ void ra_adc_all(__attribute__((unused)) uint32_t resolution, uint32_t mask) {
         adc_reg->ADANSA[0] = 0;
         adc_reg->ADANSA[1] = 0;
         adc_reg->ADEXICR_b.TSSA = 1;
-        #if defined(RA6M1) | defined(RA6M2)
+        #if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
         tsn_ctrl_reg->TSCR_b.TSEN = 1;
         while (!tsn_ctrl_reg->TSCR_b.TSEN) {
             ;
@@ -505,7 +562,7 @@ void ra_adc_all(__attribute__((unused)) uint32_t resolution, uint32_t mask) {
         }
         value16 = (uint16_t)adc_reg->ADTSDR;
         adc_values[ADC_TEMP] = value16;
-        #if defined(RA6M1) | defined(RA6M2)
+        #if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
         tsn_ctrl_reg->TSCR_b.TSOE = 0;
         while (tsn_ctrl_reg->TSCR_b.TSOE) {
             ;
@@ -533,7 +590,7 @@ void ra_adc_all(__attribute__((unused)) uint32_t resolution, uint32_t mask) {
 
 bool ra_adc_init(void) {
     ra_adc0_module_start();
-    #if defined(RA6M1) | defined(RA6M2)
+    #if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     ra_adc1_module_start();
     ra_tsn_module_start();
     #endif
@@ -544,7 +601,7 @@ bool ra_adc_init(void) {
 
 bool ra_adc_deinit(void) {
     ra_adc0_module_stop();
-    #if defined(RA6M1) | defined(RA6M2)
+    #if defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     ra_adc1_module_stop();
     ra_tsn_module_stop();
     #endif
diff --git a/ports/renesas-ra/ra/ra_adc.h b/ports/renesas-ra/ra/ra_adc.h
index 4d56243d1e..c6befa9f27 100644
--- a/ports/renesas-ra/ra/ra_adc.h
+++ b/ports/renesas-ra/ra/ra_adc.h
@@ -148,6 +148,67 @@ enum ADC14_PIN
     AN117 = 49,
     AN118 = 50,
 
+    #elif defined(RA6M3)
+    // Unit 0
+    AN000 = 0,
+    AN001 = 1,
+    AN002 = 2,
+    AN003 = 3,
+    AN004 = 4,
+    AN005 = 5,
+    AN006 = 6,
+    AN007 = 7,
+    AN016 = 16,
+    AN017 = 17,
+    AN018 = 18,
+    AN019 = 19,
+    AN020 = 20,
+    // Unit 1
+    AN100 = 32,
+    AN101 = 33,
+    AN102 = 34,
+    AN103 = 35,
+    AN105 = 37,
+    AN106 = 38,
+    AN107 = 39,
+    AN116 = 48,
+    AN117 = 49,
+    AN118 = 50,
+    AN119 = 51,
+
+    #elif defined(RA6M5)
+    // Unit 0
+    AN000 = 0,
+    AN001 = 1,
+    AN002 = 2,
+    AN003 = 3,
+    AN004 = 4,
+    AN005 = 5,
+    AN006 = 6,
+    AN007 = 7,
+    AN008 = 8,
+    AN009 = 9,
+    AN010 = 10,
+    AN012 = 12,
+    AN013 = 13,
+    // Unit 1
+    AN100 = 32,
+    AN101 = 33,
+    AN102 = 34,
+    AN116 = 35,
+    AN117 = 37,
+    AN118 = 38,
+    AN119 = 39,
+    AN120 = 48,
+    AN121 = 49,
+    AN122 = 50,
+    AN123 = 51,
+    AN124 = 52,
+    AN125 = 53,
+    AN126 = 54,
+    AN127 = 55,
+    AN128 = 56,
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
diff --git a/ports/renesas-ra/ra/ra_config.h b/ports/renesas-ra/ra/ra_config.h
index c02947a47b..a2df775c89 100644
--- a/ports/renesas-ra/ra/ra_config.h
+++ b/ports/renesas-ra/ra/ra_config.h
@@ -39,6 +39,12 @@
 #define SCI_TX_BUF_SIZE 128
 #define SCI_RX_BUF_SIZE 256
 #define PCLK         120000000
+#elif defined(RA6M5)
+#define SCI_CH_MAX   10
+#define SCI_CH_NUM   4
+#define SCI_TX_BUF_SIZE 128
+#define SCI_RX_BUF_SIZE 256
+#define PCLK         100000000
 #else
 #error "CMSIS MCU Series is not specified."
 #endif
diff --git a/ports/renesas-ra/ra/ra_dac.c b/ports/renesas-ra/ra/ra_dac.c
new file mode 100644
index 0000000000..e1b2008f72
--- /dev/null
+++ b/ports/renesas-ra/ra/ra_dac.c
@@ -0,0 +1,168 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* FSP has available API for DAC (r_dac)
+
+R_DAC_Open ( ... )
+R_DAC_Stop ( ... )
+R_DAC_Start ( ... )
+R_DAC_Write ( ... )
+R_DAC_Close ( ... )
+
+and this is (The Lazy way)
+
+   ... but looking to other drivers implementation (for example AGT [ra_timer.c/h]), Renesas want to be hard, so ...
+
+   (The Hard way it is)
+*/
+
+#include "hal_data.h"
+#include "ra_config.h"
+#include "ra_gpio.h"
+#include "ra_sci.h"
+// #include "ra_int.h"
+#include "ra_utils.h"
+#include "ra_dac.h"
+
+
+
+#if defined(RA4M1) || defined(RA4W1)
+#define DAC_CH_SIZE 1
+#elif defined(RA6M1) || defined(RA6M2) || defined(RA6M3) || defined(RA6M5)
+#define DAC_CH_SIZE 2
+#else
+#error "CMSIS MCU Series is not specified."
+#endif
+
+#define DAC_PINS_SIZE sizeof(ra_dac_pins) / sizeof(ra_af_pin_t)
+
+static const ra_af_pin_t ra_dac_pins[] = {
+    #if defined(RA4M1) || defined(RA4W1)
+    { AF_GPIO, 0, P014 }, // (A3)
+    #elif defined(RA6M1) || defined(RA6M2) || defined(RA6M3) || defined(RA6M5)
+    { AF_GPIO, 0, P014 }, // (A4)
+    { AF_GPIO, 1, P015 }, // (A5)
+    #else
+    #error "CMSIS MCU Series is not specified."
+    #endif
+};
+
+static void ra_dac_set_pin(uint32_t pin) {
+    bool find = false;
+    uint32_t ch;
+    uint32_t af;
+    find = ra_af_find_ch_af((ra_af_pin_t *)&ra_dac_pins, DAC_PINS_SIZE, pin, &ch, &af);
+    if (find) {
+        ra_gpio_config(pin, GPIO_MODE_ANALOG, GPIO_NOPULL, GPIO_LOW_POWER, af);
+        // pwpr_unprotect();
+        // _PXXPFS(GPIO_PORT(pin), GPIO_BIT(pin)) &= ~(PDR_MASK);
+        // _PXXPFS(GPIO_PORT(pin), GPIO_BIT(pin)) |= PDR_MASK;    // output
+        // pwpr_protect();
+    }
+}
+
+static void ra_dac_release_pin(uint32_t pin) {
+    bool find = false;
+    uint32_t ch;
+    uint32_t af;
+    find = ra_af_find_ch_af((ra_af_pin_t *)&ra_dac_pins, DAC_PINS_SIZE, pin, &ch, &af);
+    if (find) {
+        ra_gpio_config(pin, GPIO_MODE_ANALOG, GPIO_NOPULL, GPIO_LOW_POWER, AF_GPIO);
+        // pwpr_unprotect();
+        // _PXXPFS(GPIO_PORT(pin), GPIO_BIT(pin)) &= ~(PDR_MASK);
+        // pwpr_protect();
+    }
+}
+
+bool ra_dac_is_dac_pin(uint32_t pin) {
+    uint32_t ch;
+    uint32_t af;
+    return ra_af_find_ch_af((ra_af_pin_t *)&ra_dac_pins, DAC_PINS_SIZE, pin, &ch, &af);
+}
+
+uint8_t ra_dac_is_running(uint8_t ch) {
+    if (ch < DAC_CH_SIZE) {
+        return ch? R_DAC->DACR_b.DAOE1 : R_DAC->DACR_b.DAOE0;
+    } else {
+        return 0;
+    }
+}
+
+void ra_dac_start(uint8_t ch) {
+    if (ch < DAC_CH_SIZE) {
+        if (ch) {
+            R_DAC->DACR_b.DAOE1 = 1U;
+        } else {
+            R_DAC->DACR_b.DAOE0 = 1U;
+        }
+    }
+}
+
+void ra_dac_stop(uint8_t ch) {
+    if (ch < DAC_CH_SIZE) {
+        if (ch) {
+            R_DAC->DACR_b.DAOE1 = 0U;
+        } else {
+            R_DAC->DACR_b.DAOE0 = 0U;
+        }
+    }
+}
+
+void ra_dac_write(uint8_t ch, uint16_t val) {
+    if ((ch < DAC_CH_SIZE) || (val < 4096)) {
+        R_DAC->DADR[ch] = val;
+    }
+}
+
+uint16_t ra_dac_read(uint8_t ch) {
+    if (ch < DAC_CH_SIZE) {
+        return R_DAC->DADR[ch];
+    } else {
+        return 0;
+    }
+}
+
+void ra_dac_init(uint32_t dac_pin, uint8_t ch) {
+    if (ch < DAC_CH_SIZE) {
+        ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD20_Msk);
+
+        R_DAC->DADPR_b.DPSEL = 0;    // Right-justified format
+        R_DAC->DAADSCR_b.DAADST = 0;  // Do not synchronize with ADC14
+        R_DAC->DAVREFCR_b.REF = 1;   // AVCC0/AVSS0 selected
+        R_DAC->DADR[ch] = 0;         // Output 0 Volts
+
+        ra_dac_set_pin(dac_pin);
+        ra_dac_start(ch);
+    }
+}
+
+void ra_dac_deinit(uint32_t dac_pin, uint8_t ch) {
+    if (ch < DAC_CH_SIZE) {
+        ra_dac_stop(ch);
+        R_DAC->DAVREFCR_b.REF = 0;   // No reference voltage selected
+        ra_dac_release_pin(dac_pin);
+
+        ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD20_Msk);
+    }
+}
diff --git a/ports/renesas-ra/ra/ra_dac.h b/ports/renesas-ra/ra/ra_dac.h
new file mode 100644
index 0000000000..5afa11d973
--- /dev/null
+++ b/ports/renesas-ra/ra/ra_dac.h
@@ -0,0 +1,41 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+
+#ifndef RA_RA_DAC_H_
+#define RA_RA_DAC_H_
+
+#include <stdint.h>
+
+void ra_dac_start(uint8_t ch);
+void ra_dac_stop(uint8_t ch);
+uint8_t ra_dac_is_running(uint8_t ch);
+uint16_t ra_dac_read(uint8_t ch);
+void ra_dac_write(uint8_t ch, uint16_t val);
+void ra_dac_init(uint32_t dac_pin, uint8_t ch);
+void ra_dac_deinit(uint32_t dac_pin, uint8_t ch);
+bool ra_dac_is_dac_pin(uint32_t pin);
+
+#endif /* RA_RA_DAC_H_ */
diff --git a/ports/renesas-ra/ra/ra_flash.c b/ports/renesas-ra/ra/ra_flash.c
index e289f5f924..933e3fef9e 100644
--- a/ports/renesas-ra/ra/ra_flash.c
+++ b/ports/renesas-ra/ra/ra_flash.c
@@ -2,6 +2,7 @@
  * The MIT License (MIT)
  *
  * Copyright (c) 2021 Renesas Electronics Corporation
+ * Copyright (c) 2023 Vekatech Ltd.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -23,6 +24,7 @@
  */
 
 #include <stdbool.h>
+#include "py/mpconfig.h"
 #include "hal_data.h"
 #include "ra_config.h"
 #include "ra_utils.h"
@@ -47,6 +49,115 @@ static volatile _Bool g_b_flash_event_write_complete = false;
 
 static uint8_t flash_buf[FLASH_BUF_SIZE] __attribute__((aligned(2)));
 
+#ifdef USE_FSP_QSPI
+#if MICROPY_HW_HAS_QSPI_FLASH
+static bool r_qspi_get_QE(void) {
+    /* Enter direct communication mode */
+    R_QSPI->SFMCMD = 1U;
+
+    R_QSPI->SFMCOM = 0x35;
+    bool sts = (R_QSPI->SFMCOM >> 1) & 1;
+
+    /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
+     * in the RA6M3 manual R01UH0886EJ0100. */
+    R_QSPI->SFMCMD = 1U;
+
+    /* Exit direct communication mode */
+    R_QSPI->SFMCMD = 0U;
+
+    return sts;
+}
+
+static void r_qspi_set_QE(qspi_instance_ctrl_t *p_instance_ctrl) {
+    /* Enter direct communication mode */
+    R_QSPI->SFMCMD = 1U;
+
+    /* Enable write. */
+    R_QSPI->SFMCOM = p_instance_ctrl->p_cfg->write_enable_command;
+
+    /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
+     * in the RA6M3 manual R01UH0886EJ0100. */
+    R_QSPI->SFMCMD = 1U;
+
+    R_QSPI->SFMCOM = 0x31;
+    R_QSPI->SFMCOM = 0x02;
+
+    /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
+     * in the RA6M3 manual R01UH0886EJ0100. */
+    R_QSPI->SFMCMD = 1U;
+
+    /* Exit direct communication mode */
+    R_QSPI->SFMCMD = 0U;
+}
+
+static void r_qspi_wait_WIP(qspi_instance_ctrl_t *p_instance_ctrl) {
+    /* Enter direct communication mode */
+    R_QSPI->SFMCMD = 1U;
+
+    R_QSPI->SFMCOM = p_instance_ctrl->p_cfg->status_command;
+    while ((R_QSPI->SFMCOM >> p_instance_ctrl->p_cfg->write_status_bit) & 1) {
+        ;
+    }
+
+    /* Close the SPI bus cycle. Reference section 39.10.3 "Generating the SPI Bus Cycle during Direct Communication"
+     * in the RA6M3 manual R01UH0886EJ0100. */
+    R_QSPI->SFMCMD = 1U;
+
+    /* Exit direct communication mode */
+    R_QSPI->SFMCMD = 0U;
+}
+
+static fsp_err_t R_QSPI_QuadEnable(spi_flash_ctrl_t *p_ctrl) {
+    qspi_instance_ctrl_t *p_instance_ctrl = (qspi_instance_ctrl_t *)p_ctrl;
+
+    #if QSPI_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_status);
+    FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    /* Do not enter direct communication mode from XIP mode.  Reference note in section 39.10.2 "Using Direct
+     * Communication Mode" in the RA6M3 manual R01UH0886EJ0100. */
+    FSP_ERROR_RETURN(0U == R_QSPI->SFMSDC_b.SFMXST, FSP_ERR_INVALID_MODE);
+    #endif
+
+    /* Read device status. */
+    if (!r_qspi_get_QE()) {
+        r_qspi_set_QE(p_instance_ctrl);
+    }
+
+    return FSP_SUCCESS;
+}
+
+static fsp_err_t R_QSPI_Wait_WIP(spi_flash_ctrl_t *p_ctrl) {
+    qspi_instance_ctrl_t *p_instance_ctrl = (qspi_instance_ctrl_t *)p_ctrl;
+
+    #if QSPI_CFG_PARAM_CHECKING_ENABLE
+    FSP_ASSERT(NULL != p_instance_ctrl);
+    FSP_ASSERT(NULL != p_status);
+    FSP_ERROR_RETURN(QSPI_PRV_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN);
+
+    /* Do not enter direct communication mode from XIP mode.  Reference note in section 39.10.2 "Using Direct
+     * Communication Mode" in the RA6M3 manual R01UH0886EJ0100. */
+    FSP_ERROR_RETURN(0U == R_QSPI->SFMSDC_b.SFMXST, FSP_ERR_INVALID_MODE);
+    #endif
+
+    /* Wait WIP flag to go 0 */
+    r_qspi_wait_WIP(p_instance_ctrl);
+
+    return FSP_SUCCESS;
+}
+
+static bool lmemprob(void *dst, size_t len) {
+    uint8_t *p;
+    for (p = (uint8_t *)dst; ((len > 0) && (p[0] == 0xFF)); len--) {
+        p++;
+    }
+
+    return len? false : true;
+}
+#endif
+#endif
+
 void *FLASH_SECTION lmemset(void *dst, int c, size_t len) {
     char *p;
     for (p = (char *)dst; len > 0; len--) {
@@ -80,7 +191,7 @@ int FLASH_SECTION lmemcmp(const void *p1, const void *p2, size_t len) {
     return (int)0;
 }
 
-#if defined(RA4M1) | defined(RA4M3) | defined(RA4W1)
+#if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) | MICROPY_HW_HAS_QSPI_FLASH
 
 uint32_t FLASH_SECTION sector_size(uint32_t addr) {
     return FLASH_SECTOR_SIZE;
@@ -94,7 +205,7 @@ uint32_t FLASH_SECTION sector_index(uint32_t addr) {
     return (addr - 0x00000000) / FLASH_SECTOR_SIZE;
 }
 
-#elif defined(RA6M1) | defined(RA6M2)
+#elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
 
 #define REGION1_SECTOR_SIZE 0x8000  // 32K
 #define REGION1_SECTOR_MAX  14
@@ -102,7 +213,7 @@ uint32_t FLASH_SECTION sector_index(uint32_t addr) {
 #define REGION0_SECTOR_MAX  8
 
 uint32_t FLASH_SECTION sector_size(uint32_t addr) {
-    if (addr <= 0x00010000) {
+    if (addr < 0x00010000) {
         return REGION0_SECTOR_SIZE;
     } else {
         return REGION1_SECTOR_SIZE;
@@ -110,7 +221,7 @@ uint32_t FLASH_SECTION sector_size(uint32_t addr) {
 }
 
 uint32_t FLASH_SECTION sector_start(uint32_t addr) {
-    if (addr <= 0x00010000) {
+    if (addr < 0x00010000) {
         return addr & ~(REGION0_SECTOR_SIZE - 1);
     } else {
         return addr & ~(REGION1_SECTOR_SIZE - 1);
@@ -118,10 +229,10 @@ uint32_t FLASH_SECTION sector_start(uint32_t addr) {
 }
 
 uint32_t FLASH_SECTION sector_index(uint32_t addr) {
-    if (addr <= 0x00010000) {
-        return (addr - 0x00010000) / REGION0_SECTOR_SIZE;
+    if (addr < 0x00010000) {
+        return (addr - 0x00000000) / REGION0_SECTOR_SIZE;
     } else {
-        return (addr - 0x000100000) / REGION1_SECTOR_SIZE;
+        return ((addr - 0x00010000) / REGION1_SECTOR_SIZE) + REGION0_SECTOR_SIZE;
     }
 }
 
@@ -169,15 +280,23 @@ bool internal_flash_writex(uint8_t *addr, uint32_t NumBytes, uint8_t *pSectorBuf
         }
         g_b_flash_event_write_complete = false;
         uint8_t *flash_addr = (uint8_t *)((uint32_t)startaddr & FLASH_BUF_ADDR_MASK);
+        #if MICROPY_HW_HAS_QSPI_FLASH
+        for (uint16_t idx = 0; ((err == FSP_SUCCESS) && (idx < FLASH_SECTOR_SIZE)); idx += FLASH_PAGE_SIZE)
+        {
+            err = R_QSPI_Write(&g_qspi0_ctrl, &buf_addr[idx], &flash_addr[idx], FLASH_PAGE_SIZE);
+            err = R_QSPI_Wait_WIP(&g_qspi0_ctrl);
+        }
+        #else
         uint32_t state = ra_disable_irq();
         #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1)
         err = R_FLASH_LP_Write(&g_flash0_ctrl, (uint32_t const)buf_addr, (uint32_t)flash_addr, FLASH_SECTOR_SIZE);
-        #elif defined(RA6M1) | defined(RA6M2)
+        #elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
         err = R_FLASH_HP_Write(&g_flash0_ctrl, (uint32_t const)buf_addr, (uint32_t)flash_addr, FLASH_SECTOR_SIZE);
         #else
         #error "CMSIS MCU Series is not specified."
         #endif
         ra_enable_irq(state);
+        #endif
         if (FSP_SUCCESS != err) {
             error_code = 1;
             goto WriteX_exit;
@@ -205,14 +324,17 @@ bool internal_flash_memset(uint8_t *addr, uint8_t Data, uint32_t NumBytes) {
 }
 
 bool internal_flash_isblockerased(uint8_t *addr, uint32_t BlockLength) {
-    fsp_err_t err = FSP_SUCCESS;
-    flash_result_t blankCheck = FLASH_RESULT_BLANK;
     g_b_flash_event_not_blank = false;
     g_b_flash_event_blank = false;
+    #if MICROPY_HW_HAS_QSPI_FLASH
+    return lmemprob((uint8_t *)((uint32_t)addr & FLASH_BUF_ADDR_MASK), FLASH_SECTOR_SIZE);
+    #else
+    fsp_err_t err = FSP_SUCCESS;
+    flash_result_t blankCheck = FLASH_RESULT_BLANK;
     uint32_t state = ra_disable_irq();
     #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1)
     err = R_FLASH_LP_BlankCheck(&g_flash0_ctrl, (uint32_t const)((uint32_t)addr & FLASH_BUF_ADDR_MASK), FLASH_SECTOR_SIZE, &blankCheck);
-    #elif defined(RA6M1) | defined(RA6M2)
+    #elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     err = R_FLASH_HP_BlankCheck(&g_flash0_ctrl, (uint32_t const)((uint32_t)addr & FLASH_BUF_ADDR_MASK), FLASH_SECTOR_SIZE, &blankCheck);
     #else
     #error "CMSIS MCU Series is not specified."
@@ -227,21 +349,29 @@ bool internal_flash_isblockerased(uint8_t *addr, uint32_t BlockLength) {
     } else {
         return false;
     }
+    #endif
 }
 
 bool internal_flash_eraseblock(uint8_t *addr) {
     uint32_t error_code = 0;
     fsp_err_t err = FSP_SUCCESS;
     g_b_flash_event_erase_complete = false;
+    #if MICROPY_HW_HAS_QSPI_FLASH
+    if (!lmemprob((uint8_t *)((uint32_t)addr & FLASH_BUF_ADDR_MASK), FLASH_SECTOR_SIZE)) {
+        err = R_QSPI_Erase(&g_qspi0_ctrl, (uint8_t *const)addr, FLASH_SECTOR_SIZE);
+        err = R_QSPI_Wait_WIP(&g_qspi0_ctrl);
+    }
+    #else
     uint32_t state = ra_disable_irq();
     #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1)
     err = R_FLASH_LP_Erase(&g_flash0_ctrl, (uint32_t const)addr, 1);
-    #elif defined(RA6M1) | defined(RA6M2)
+    #elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     err = R_FLASH_HP_Erase(&g_flash0_ctrl, (uint32_t const)addr, 1);
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
     ra_enable_irq(state);
+    #endif
     if (err == FSP_SUCCESS) {
         error_code = 0;
     } else {
@@ -277,9 +407,18 @@ void callback_flash(flash_callback_args_t *p_args) {
 
 bool internal_flash_init(void) {
     fsp_err_t err = FSP_SUCCESS;
+    #if MICROPY_HW_HAS_QSPI_FLASH
+    err = R_QSPI_Open(&g_qspi0_ctrl, &g_qspi0_cfg);
+    if (err == FSP_SUCCESS) {
+        R_QSPI_QuadEnable(&g_qspi0_ctrl);
+        return true;
+    } else {
+        return false;
+    }
+    #else
     #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1)
     err = R_FLASH_LP_Open(&g_flash0_ctrl, &g_flash0_cfg);
-    #elif defined(RA6M1) | defined(RA6M2)
+    #elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
     err = R_FLASH_HP_Open(&g_flash0_ctrl, &g_flash0_cfg);
     #else
     #error "CMSIS MCU Series is not specified."
@@ -289,6 +428,7 @@ bool internal_flash_init(void) {
     } else {
         return false;
     }
+    #endif
 }
 
 #else
diff --git a/ports/renesas-ra/ra/ra_flash.h b/ports/renesas-ra/ra/ra_flash.h
index f9afef2a94..f6e01daff5 100644
--- a/ports/renesas-ra/ra/ra_flash.h
+++ b/ports/renesas-ra/ra/ra_flash.h
@@ -29,8 +29,27 @@
 #include <stdint.h>
 #include <stdbool.h>
 
+#if MICROPY_HW_HAS_QSPI_FLASH
+#define SELECT(ic, attr)        ic##_##attr
+#define FLASH(ic, attr)         SELECT(ic, attr)
+#define CHIP                    AT25SF128A
+// #define CHIP                    W25Q128JV
+
+#define W25Q128JV_SECTOR_SIZE   4096ul
+#define W25Q128JV_NUM_BLOCKS    4096ul
+#define W25Q128JV_PAGE_SIZE     256ul
+
+#define AT25SF128A_SECTOR_SIZE  4096ul
+#define AT25SF128A_NUM_BLOCKS   4096ul
+#define AT25SF128A_PAGE_SIZE    256ul
+
+#define FLASH_SECTOR_SIZE       FLASH(CHIP, SECTOR_SIZE)
+#define FLASH_NUM_BLOCKS        FLASH(CHIP, NUM_BLOCKS)
+#define FLASH_PAGE_SIZE         FLASH(CHIP, PAGE_SIZE)
+#else
 #define FLASH_SECTOR_SIZE   ((uint32_t)2048)
 #define FLASH_NUM_BLOCKS    ((uint32_t)128)
+#endif
 #define FLASH_BUF_OFF_MASK  (FLASH_SECTOR_SIZE - 1)
 #define FLASH_BUF_ADDR_MASK (~FLASH_BUF_OFF_MASK)
 #define FLASH_BUF_SIZE      FLASH_SECTOR_SIZE
diff --git a/ports/renesas-ra/ra/ra_gpio.h b/ports/renesas-ra/ra/ra_gpio.h
index 8c16fe3ba1..58df7aafe9 100644
--- a/ports/renesas-ra/ra/ra_gpio.h
+++ b/ports/renesas-ra/ra/ra_gpio.h
@@ -42,10 +42,12 @@ enum CPU_PIN {
     P300 = 0x30, P301, P302, P303, P304, P305, P306, P307, P308, P309, P310, P311, P312, P313, P314, P315,
     P400 = 0x40, P401, P402, P403, P404, P405, P406, P407, P408, P409, P410, P411, P412, P413, P414, P415,
     P500 = 0x50, P501, P502, P503, P504, P505, P506, P507, P508, P509, P510, P511, P512, P513, P514, P515,
-    P600 = 0x90, P601, P602, P603, P604, P605, P606, P607, P608, P609, P610, P611, P612, P613, P614, P615,
+    P600 = 0x60, P601, P602, P603, P604, P605, P606, P607, P608, P609, P610, P611, P612, P613, P614, P615,
     P700 = 0x70, P701, P702, P703, P704, P705, P706, P707, P708, P709, P710, P711, P712, P713, P714, P715,
     P800 = 0x80, P801, P802, P803, P804, P805, P806, P807, P808, P809, P810, P811, P812, P813, P814, P815,
     P900 = 0x90, P901, P902, P903, P904, P905, P906, P907, P908, P909, P910, P911, P912, P913, P914, P915,
+    PA00 = 0xA0, PA01, PA02, PA03, PA04, PA05, PA06, PA07, PA08, PA09, PA10, PA11, PA12, PA13, PA14, PA15,
+    PB00 = 0xB0, PB01, PB02, PB03, PB04, PB05, PB06, PB07, PB08, PB09, PB10, PB11, PB12, PB13, PB14, PB15,
     PIN_END = 0xff,
 };
 
@@ -126,35 +128,35 @@ enum AF_INDEX {
 #define PMR_MASK    (uint32_t)0x00010000
 #define PSEL_MASK   (uint32_t)0x1f000000
 
-#define _PWPR               (*(volatile uint8_t *)(0x40040D03))
+#define _PWPR               (*(volatile uint8_t *)(R_PFS_BASE + 0x503))
 
-#define _PXXPFS(port, bit)  (*(volatile uint32_t *)(0x40040800 + (0x40 * ((uint32_t)port)) + (0x4 * ((uint32_t)bit))))
-#define _PCNTR1(port)       (*(volatile uint32_t *)(0x40040000 + (0x20 * (port))))
-#define _PODR(port)         (*(volatile uint16_t *)(0x40040000 + (0x20 * (port))))
-#define _PDR(port)          (*(volatile uint16_t *)(0x40040002 + (0x20 * (port))))
-#define _PCNTR2(port)       (*(volatile uint32_t *)(0x40040004 + (0x20 * (port))))
-#define _EIDR(port)         (*(volatile uint16_t *)(0x40040004 + (0x20 * (port))))
-#define _PIDR(port)         (*(volatile uint16_t *)(0x40040006 + (0x20 * (port))))
-#define _PCNTR3(port)       (*(volatile uint32_t *)(0x40040008 + (0x20 * (port))))
-#define _PORR(port)         (*(volatile uint16_t *)(0x40040008 + (0x20 * (port))))
-#define _POSR(port)         (*(volatile uint16_t *)(0x4004000a + (0x20 * (port))))
-#define _PCNTR4(port)       (*(volatile uint32_t *)(0x4004000c + (0x20 * (port))))
-#define _EORR(port)         (*(volatile uint16_t *)(0x4004000c + (0x20 * (port))))
-#define _EOSR(port)         (*(volatile uint16_t *)(0x4004000e + (0x20 * (port))))
+#define _PXXPFS(port, bit)  (*(volatile uint32_t *)(R_PFS_BASE + (0x40 * ((uint32_t)port)) + (0x4 * ((uint32_t)bit))))
+#define _PCNTR1(port)       (*(volatile uint32_t *)(R_PORT0_BASE + (0x20 * (port))))
+#define _PODR(port)         (*(volatile uint16_t *)(R_PORT0_BASE + (0x20 * (port))))
+#define _PDR(port)          (*(volatile uint16_t *)(R_PORT0_BASE + 0x2 + (0x20 * (port))))
+#define _PCNTR2(port)       (*(volatile uint32_t *)(R_PORT0_BASE + 0x4 + (0x20 * (port))))
+#define _EIDR(port)         (*(volatile uint16_t *)(R_PORT0_BASE + 0x4 + (0x20 * (port))))
+#define _PIDR(port)         (*(volatile uint16_t *)(R_PORT0_BASE + 0x6 + (0x20 * (port))))
+#define _PCNTR3(port)       (*(volatile uint32_t *)(R_PORT0_BASE + 0x8 + (0x20 * (port))))
+#define _PORR(port)         (*(volatile uint16_t *)(R_PORT0_BASE + 0x8 + (0x20 * (port))))
+#define _POSR(port)         (*(volatile uint16_t *)(R_PORT0_BASE + 0xa + (0x20 * (port))))
+#define _PCNTR4(port)       (*(volatile uint32_t *)(R_PORT0_BASE + 0xc + (0x20 * (port))))
+#define _EORR(port)         (*(volatile uint16_t *)(R_PORT0_BASE + 0xc + (0x20 * (port))))
+#define _EOSR(port)         (*(volatile uint16_t *)(R_PORT0_BASE + 0xe + (0x20 * (port))))
 
-#define _PPXXPFS(port, bit)  ((volatile uint32_t *)(0x40040800 + (0x40 * (port)) + (0x4 * (bit))))
-#define _PPCNTR1(port)       ((volatile uint32_t *)(0x40040000 + (0x20 * (port))))
-#define _PPODR(port)         ((volatile uint16_t *)(0x40040000 + (0x20 * (port))))
-#define _PPDR(port)          ((volatile uint16_t *)(0x40040002 + (0x20 * (port))))
-#define _PPCNTR2(port)       ((volatile uint32_t *)(0x40040004 + (0x20 * (port))))
-#define _PEIDR(port)         ((volatile uint16_t *)(0x40040004 + (0x20 * (port))))
-#define _PPIDR(port)         ((volatile uint16_t *)(0x40040006 + (0x20 * (port))))
-#define _PPCNTR3(port)       ((volatile uint32_t *)(0x40040008 + (0x20 * (port))))
-#define _PPORR(port)         ((volatile uint16_t *)(0x40040008 + (0x20 * (port))))
-#define _PPOSR(port)         ((volatile uint16_t *)(0x4004000a + (0x20 * (port))))
-#define _PPCNTR4(port)       ((volatile uint32_t *)(0x4004000c + (0x20 * (port))))
-#define _PEORR(port)         ((volatile uint16_t *)(0x4004000c + (0x20 * (port))))
-#define _PEOSR(port)         ((volatile uint16_t *)(0x4004000e + (0x20 * (port))))
+#define _PPXXPFS(port, bit)  ((volatile uint32_t *)(R_PFS_BASE + (0x40 * (port)) + (0x4 * (bit))))
+#define _PPCNTR1(port)       ((volatile uint32_t *)(R_PORT0_BASE + (0x20 * (port))))
+#define _PPODR(port)         ((volatile uint16_t *)(R_PORT0_BASE + (0x20 * (port))))
+#define _PPDR(port)          ((volatile uint16_t *)(R_PORT0_BASE + 0x2 + (0x20 * (port))))
+#define _PPCNTR2(port)       ((volatile uint32_t *)(R_PORT0_BASE + 0x4 + (0x20 * (port))))
+#define _PEIDR(port)         ((volatile uint16_t *)(R_PORT0_BASE + 0x4 + (0x20 * (port))))
+#define _PPIDR(port)         ((volatile uint16_t *)(R_PORT0_BASE + 0x6 + (0x20 * (port))))
+#define _PPCNTR3(port)       ((volatile uint32_t *)(R_PORT0_BASE + 0x8 + (0x20 * (port))))
+#define _PPORR(port)         ((volatile uint16_t *)(R_PORT0_BASE + 0x8 + (0x20 * (port))))
+#define _PPOSR(port)         ((volatile uint16_t *)(R_PORT0_BASE + 0xa + (0x20 * (port))))
+#define _PPCNTR4(port)       ((volatile uint32_t *)(R_PORT0_BASE + 0xc + (0x20 * (port))))
+#define _PEORR(port)         ((volatile uint16_t *)(R_PORT0_BASE + 0xc + (0x20 * (port))))
+#define _PEOSR(port)         ((volatile uint16_t *)(R_PORT0_BASE + 0xe + (0x20 * (port))))
 
 void ra_gpio_config(uint32_t pin, uint32_t mode, uint32_t pull, uint32_t drive, uint32_t alt);
 void ra_gpio_mode_output(uint32_t pin);
diff --git a/ports/renesas-ra/ra/ra_gpt.c b/ports/renesas-ra/ra/ra_gpt.c
new file mode 100644
index 0000000000..cca32c4d82
--- /dev/null
+++ b/ports/renesas-ra/ra/ra_gpt.c
@@ -0,0 +1,626 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* FSP has available API for PWM (r_gpt)
+
+R_GPT_Open ( ... )
+R_GPT_Stop ( ... )
+R_GPT_Start ( ... )
+R_GPT_Reset ( ... )
+R_GPT_Enable ( ... )
+R_GPT_Disable ( ... )
+R_GPT_PeriodSet ( ... )
+R_GPT_DutyCycleSet ( ... )
+R_GPT_InfoGet ( ... )
+R_GPT_StatusGet ( ... )
+R_GPT_CounterSet ( ... )
+R_GPT_OutputEnable ( ... )
+R_GPT_OutputDisable ( ... )
+R_GPT_AdcTriggerSet ( ... )
+R_GPT_CallbackSet ( ... )
+R_GPT_Close ( ... )
+
+and this is (The Lazy way)
+
+   ... but looking to other drivers implementation (for example AGT [ra_timer.c/h]), Renesas want to be hard, so ...
+
+   (The Hard way it is)
+*/
+
+#include "hal_data.h"
+#include "ra_config.h"
+#include "ra_gpio.h"
+#include "ra_sci.h"
+// #include "ra_int.h"
+#include "ra_utils.h"
+#include "ra_gpt.h"
+
+
+
+#if defined(RA4M1)
+#define GPT_CH_SIZE 8
+#define CH_GAP 0
+#elif defined(RA4W1)
+#define GPT_CH_SIZE 9
+#define CH_GAP (ch == 6) || (ch == 7)
+#elif defined(RA6M1)
+#define GPT_CH_SIZE 13
+#define CH_GAP 0
+#elif defined(RA6M2) || defined(RA6M3)
+#define GPT_CH_SIZE 14
+#define CH_GAP 0
+#elif defined(RA6M5)
+#define GPT_CH_SIZE 10
+#define CH_GAP 0
+#else
+#error "CMSIS MCU Series is not specified."
+#endif
+
+enum GPT_SOURCE {
+    GPT_PCLKD = 0,
+    GPT_PCLKD4,
+    GPT_PCLKD16,
+    GPT_PCLKD64,
+    GPT_PCLKD256,
+    GPT_PCLKD1024
+};
+
+static R_GPT0_Type *gpt_regs[GPT_CH_SIZE] = {
+    #if defined(RA4M1)
+    R_GPT0,     // GPT320 General PWM Timer 0 (32-bit)
+    R_GPT1,     // GPT321 General PWM Timer 1 (32-bit)
+    R_GPT2,     // GPT162 General PWM Timer 2 (16-bit)
+    R_GPT3,     // GPT163 General PWM Timer 3 (16-bit)
+    R_GPT4,     // GPT164 General PWM Timer 4 (16-bit)
+    R_GPT5,     // GPT165 General PWM Timer 5 (16-bit)
+    R_GPT6,     // GPT166 General PWM Timer 6 (16-bit)
+    R_GPT7,     // GPT167 General PWM Timer 7 (16-bit)
+    #elif defined(RA4W1)
+    R_GPT0,     // GPT320 General PWM Timer 0 (32-bit)
+    R_GPT1,     // GPT321 General PWM Timer 1 (32-bit)
+    R_GPT2,     // GPT322 General PWM Timer 2 (32-bit)
+    R_GPT3,     // GPT323 General PWM Timer 3 (32-bit)
+    R_GPT4,     // GPT164 General PWM Timer 4 (16-bit)
+    R_GPT5,     // GPT165 General PWM Timer 5 (16-bit)
+    NULL,       // N/A            PWM Timer 6 (Does not exist)
+    NULL,       // N/A            PWM Timer 7 (Does not exist)
+    R_GPT8      // GPT168 General PWM Timer 8 (16-bit)
+    #elif defined(RA6M1) || defined(RA6M2) || defined(RA6M3)
+    R_GPT0,     // GPT32EH0 General PWM Timer 0  (32-bit)
+    R_GPT1,     // GPT32EH1 General PWM Timer 1  (32-bit)
+    R_GPT2,     // GPT32EH2 General PWM Timer 2  (32-bit)
+    R_GPT3,     // GPT32EH3 General PWM Timer 3  (32-bit)
+    R_GPT4,     // GPT32E4  General PWM Timer 4  (32-bit)
+    R_GPT5,     // GPT32E5  General PWM Timer 5  (32-bit)
+    R_GPT6,     // GPT32E6  General PWM Timer 6  (32-bit)
+    R_GPT7,     // GPT32E7  General PWM Timer 7  (32-bit)
+    R_GPT8,     // GPT328   General PWM Timer 8  (32-bit)
+    R_GPT9,     // GPT329   General PWM Timer 9  (32-bit)
+    R_GPT10,    // GPT3210  General PWM Timer 10 (32-bit)
+    R_GPT11,    // GPT3211  General PWM Timer 11 (32-bit)
+    R_GPT12,    // GPT3212  General PWM Timer 12 (32-bit)
+    #if defined(RA6M2) || defined(RA6M3)
+    R_GPT13,    // GPT3213  General PWM Timer 13 (32-bit)
+    #endif
+    #elif defined(RA6M5)
+    R_GPT0,     // GPT320 General PWM Timer 0  (32-bit)
+    R_GPT1,     // GPT321 General PWM Timer 1  (32-bit)
+    R_GPT2,     // GPT322 General PWM Timer 2  (32-bit)
+    R_GPT3,     // GPT323 General PWM Timer 3  (32-bit)
+    R_GPT4,     // GPT164 General PWM Timer 4  (16-bit)
+    R_GPT5,     // GPT165 General PWM Timer 5  (16-bit)
+    R_GPT6,     // GPT166 General PWM Timer 6  (16-bit)
+    R_GPT7,     // GPT167 General PWM Timer 7  (16-bit)
+    R_GPT8,     // GPT168 General PWM Timer 8  (16-bit)
+    R_GPT9,     // GPT169 General PWM Timer 9  (16-bit)
+    #else
+    #error "CMSIS MCU Series is not specified."
+    #endif
+};
+
+#define GPT_TMR_PINS_SIZE sizeof(ra_gpt_timer_pins) / sizeof(ra_af_pin_t)
+
+static const ra_af_pin_t ra_gpt_timer_pins[] = {
+    #if defined(RA4M1)
+    { AF_GPT2, 0,  P107 }, { AF_GPT2, 0,  P213 }, { AF_GPT2, 0,  P300 }, { AF_GPT2, 0,  P415 }, // GTIOC0A
+    { AF_GPT2, 0,  P106 }, { AF_GPT2, 0,  P108 }, { AF_GPT2, 0,  P212 }, { AF_GPT2, 0,  P414 }, // GTIOC0B
+    { AF_GPT2, 1,  P105 }, { AF_GPT2, 1,  P109 }, { AF_GPT2, 1,  P405 },                        // GTIOC1A
+    { AF_GPT2, 1,  P104 }, { AF_GPT2, 1,  P110 }, { AF_GPT2, 1,  P406 },                        // GTIOC1B
+    { AF_GPT2, 2,  P103 }, { AF_GPT2, 2,  P113 }, { AF_GPT2, 2,  P500 },                        // GTIOC2A
+    { AF_GPT2, 2,  P102 }, { AF_GPT2, 2,  P114 }, { AF_GPT2, 2,  P501 },                        // GTIOC2B
+    { AF_GPT2, 3,  P111 }, { AF_GPT2, 3,  P403 },                                               // GTIOC3A
+    { AF_GPT2, 3,  P112 }, { AF_GPT2, 3,  P404 }, { AF_GPT2, 3,  P502 },                        // GTIOC3B
+    { AF_GPT2, 4,  P115 }, { AF_GPT2, 4,  P205 }, { AF_GPT2, 4,  P302 },                        // GTIOC4A
+    { AF_GPT2, 4,  P204 }, { AF_GPT2, 4,  P301 }, { AF_GPT2, 4,  P608 },                        // GTIOC4B
+    { AF_GPT2, 5,  P101 }, { AF_GPT2, 5,  P203 }, { AF_GPT2, 5,  P409 }, { AF_GPT2, 5,  P609 }, // GTIOC5A
+    { AF_GPT2, 5,  P100 }, { AF_GPT2, 5,  P202 }, { AF_GPT2, 5,  P408 }, { AF_GPT2, 5,  P610 }, // GTIOC5B
+    { AF_GPT2, 6,  P400 }, { AF_GPT2, 6,  P411 }, { AF_GPT2, 6,  P601 },                        // GTIOC6A
+    { AF_GPT2, 6,  P401 }, { AF_GPT2, 6,  P410 }, { AF_GPT2, 6,  P600 },                        // GTIOC6B
+    { AF_GPT2, 7,  P304 }, { AF_GPT2, 7,  P603 },                                               // GTIOC7A
+    { AF_GPT2, 7,  P303 }, { AF_GPT2, 7,  P602 },                                               // GTIOC7B
+    #elif defined(RA4W1)
+    { AF_GPT2, 0,  P213 }, { AF_GPT2, 0,  P300 },                        // GTIOC0A
+    { AF_GPT2, 0,  P108 }, { AF_GPT2, 0,  P212 }, { AF_GPT2, 0,  P414 }, // GTIOC0B
+    { AF_GPT2, 1,  P105 }, { AF_GPT2, 1,  P109 },                        // GTIOC1A
+    { AF_GPT2, 1,  P104 }, { AF_GPT2, 1,  P110 },                        // GTIOC1B
+    { AF_GPT2, 2,  P103 },                                               // GTIOC2A
+    { AF_GPT2, 2,  P102 }, { AF_GPT2, 2,  P501 },                        // GTIOC2B
+    { AF_GPT2, 3,  P111 },                                               // GTIOC3A
+    { AF_GPT2, 3,  P404 },                                               // GTIOC3B
+    { AF_GPT2, 4,  P205 },                                               // GTIOC4A
+    { AF_GPT2, 4,  P204 },                                               // GTIOC4B
+    { AF_GPT2, 5,  P101 }, { AF_GPT2, 5,  P409 },                        // GTIOC5A
+    { AF_GPT2, 5,  P100 },                                               // GTIOC5B
+    { AF_GPT2, 8,  P107 },                                               // GTIOC8A
+    { AF_GPT2, 8,  P106 },                                               // GTIOC8B
+    #elif defined(RA6M1)
+    { AF_GPT2, 0,  P213 }, { AF_GPT2, 0,  P415 },                        // GTIOC0A
+    { AF_GPT2, 0,  P212 }, { AF_GPT2, 0,  P414 },                        // GTIOC0B
+    { AF_GPT2, 1,  P105 }, { AF_GPT2, 1,  P405 },                        // GTIOC1A
+    { AF_GPT2, 1,  P104 }, { AF_GPT2, 1,  P406 },                        // GTIOC1B
+    { AF_GPT2, 2,  P113 },                                               // GTIOC2A
+    { AF_GPT2, 2,  P114 },                                               // GTIOC2B
+    { AF_GPT2, 3,  P403 },                                               // GTIOC3A
+    { AF_GPT2, 3,  P404 },                                               // GTIOC3B
+    { AF_GPT2, 4,  P115 }, { AF_GPT2, 4,  P205 }, { AF_GPT2, 4,  P302 }, // GTIOC4A
+    { AF_GPT2, 4,  P301 }, { AF_GPT2, 4,  P608 },                        // GTIOC4B
+    { AF_GPT2, 5,  P101 }, { AF_GPT2, 5,  P609 },                        // GTIOC5A
+    { AF_GPT2, 5,  P100 }, { AF_GPT2, 5,  P610 },                        // GTIOC5B
+    { AF_GPT2, 6,  P400 }, { AF_GPT2, 6,  P601 },                        // GTIOC6A
+    { AF_GPT2, 6,  P401 }, { AF_GPT2, 6,  P600 },                        // GTIOC6B
+    { AF_GPT2, 7,  P304 },                                               // GTIOC7A
+    { AF_GPT2, 7,  P303 }, { AF_GPT2, 7,  P602 },                        // GTIOC7B
+    { AF_GPT2, 8,  P107 },                                               // GTIOC8A
+    { AF_GPT2, 8,  P106 },                                               // GTIOC8B
+    { AF_GPT2, 9,  P411 },                                               // GTIOC9A
+    { AF_GPT2, 9,  P410 },                                               // GTIOC9B
+    { AF_GPT2, 10, P409 },                                               // GTIOC10A
+    { AF_GPT2, 10, P408 },                                               // GTIOC10B
+    { AF_GPT2, 11, P500 },                                               // GTIOC11A
+    { AF_GPT2, 11, P501 },                                               // GTIOC11B
+    { AF_GPT2, 12, P502 },                                               // GTIOC12A
+    { AF_GPT2, 12, P503 },                                               // GTIOC12B
+    #elif defined(RA6M2)
+    { AF_GPT2, 0,  P213 }, { AF_GPT2, 0,  P415 }, { AF_GPT2, 0,  P512 },                        // GTIOC0A
+    { AF_GPT2, 0,  P212 }, { AF_GPT2, 0,  P414 }, { AF_GPT2, 0,  P511 },                        // GTIOC0B
+    { AF_GPT2, 1,  P105 }, { AF_GPT2, 1,  P405 },                                               // GTIOC1A
+    { AF_GPT2, 1,  P104 }, { AF_GPT2, 1,  P406 },                                               // GTIOC1B
+    { AF_GPT2, 2,  P113 }, { AF_GPT2, 2,  P713 },                                               // GTIOC2A
+    { AF_GPT2, 2,  P114 }, { AF_GPT2, 2,  P712 },                                               // GTIOC2B
+    { AF_GPT2, 3,  P403 },                                                                      // GTIOC3A
+    { AF_GPT2, 3,  P404 },                                                                      // GTIOC3B
+    { AF_GPT2, 4,  P115 }, { AF_GPT2, 4,  P205 }, { AF_GPT2, 4,  P302 },                        // GTIOC4A
+    { AF_GPT2, 4,  P204 }, { AF_GPT2, 4,  P301 }, { AF_GPT2, 4,  P608 },                        // GTIOC4B
+    { AF_GPT2, 5,  P101 }, { AF_GPT2, 5,  P203 }, { AF_GPT2, 5,  P609 }, { AF_GPT2, 5,  P700 }, // GTIOC5A
+    { AF_GPT2, 5,  P100 }, { AF_GPT2, 5,  P202 }, { AF_GPT2, 5,  P610 }, { AF_GPT2, 5,  P701 }, // GTIOC5B
+    { AF_GPT2, 6,  P400 }, { AF_GPT2, 6,  P601 }, { AF_GPT2, 6,  P702 },                        // GTIOC6A
+    { AF_GPT2, 6,  P401 }, { AF_GPT2, 6,  P600 }, { AF_GPT2, 6,  P703 },                        // GTIOC6B
+    { AF_GPT2, 7,  P304 }, { AF_GPT2, 7,  P603 },                                               // GTIOC7A
+    { AF_GPT2, 7,  P303 }, { AF_GPT2, 7,  P602 },                                               // GTIOC7B
+    { AF_GPT2, 8,  P107 }, { AF_GPT2, 8,  P605 },                                               // GTIOC8A
+    { AF_GPT2, 8,  P106 }, { AF_GPT2, 8,  P604 },                                               // GTIOC8B
+    { AF_GPT2, 9,  P411 },                                                                      // GTIOC9A
+    { AF_GPT2, 9,  P410 },                                                                      // GTIOC9B
+    { AF_GPT2, 10, P409 },                                                                      // GTIOC10A
+    { AF_GPT2, 10, P408 },                                                                      // GTIOC10B
+    { AF_GPT2, 11, P500 },                                                                      // GTIOC11A
+    { AF_GPT2, 11, P501 },                                                                      // GTIOC11B
+    { AF_GPT2, 12, P502 },                                                                      // GTIOC12A
+    { AF_GPT2, 12, P503 },                                                                      // GTIOC12B
+    { AF_GPT2, 13, P504 },                                                                      // GTIOC13A
+    { AF_GPT2, 13, P505 },                                                                      // GTIOC13B
+    #elif defined(RA6M3)
+    { AF_GPT2, 0,  P213 }, { AF_GPT2, 0,  P415 }, { AF_GPT2, 0,  P512 },                        // GTIOC0A
+    { AF_GPT2, 0,  P212 }, { AF_GPT2, 0,  P414 }, { AF_GPT2, 0,  P511 },                        // GTIOC0B
+    { AF_GPT2, 1,  P105 }, { AF_GPT2, 1,  P405 },                                               // GTIOC1A
+    { AF_GPT2, 1,  P104 }, { AF_GPT2, 1,  P406 },                                               // GTIOC1B
+    { AF_GPT2, 2,  P113 }, { AF_GPT2, 2,  P713 },                                               // GTIOC2A
+    { AF_GPT2, 2,  P114 }, { AF_GPT2, 2,  P712 },                                               // GTIOC2B
+    { AF_GPT2, 3,  P403 },                                                                      // GTIOC3A
+    { AF_GPT2, 3,  P404 },                                                                      // GTIOC3B
+    { AF_GPT2, 4,  P115 }, { AF_GPT2, 4,  P205 }, { AF_GPT2, 4,  P302 },                        // GTIOC4A
+    { AF_GPT2, 4,  P204 }, { AF_GPT2, 4,  P301 }, { AF_GPT2, 4,  P608 },                        // GTIOC4B
+    { AF_GPT2, 5,  P101 }, { AF_GPT2, 5,  P203 }, { AF_GPT2, 5,  P609 }, { AF_GPT2, 5,  P700 }, // GTIOC5A
+    { AF_GPT2, 5,  P100 }, { AF_GPT2, 5,  P202 }, { AF_GPT2, 5,  P610 }, { AF_GPT2, 5,  P701 }, // GTIOC5B
+    { AF_GPT2, 6,  P400 }, { AF_GPT2, 6,  P601 }, { AF_GPT2, 6,  P702 },                        // GTIOC6A
+    { AF_GPT2, 6,  P401 }, { AF_GPT2, 6,  P600 }, { AF_GPT2, 6,  P703 },                        // GTIOC6B
+    { AF_GPT2, 7,  P304 }, { AF_GPT2, 7,  P603 },                                               // GTIOC7A
+    { AF_GPT2, 7,  P303 }, { AF_GPT2, 7,  P602 },                                               // GTIOC7B
+    { AF_GPT2, 8,  P107 }, { AF_GPT2, 8,  P605 },                                               // GTIOC8A
+    { AF_GPT2, 8,  P106 }, { AF_GPT2, 8,  P604 },                                               // GTIOC8B
+    { AF_GPT2, 9,  P411 },                                                                      // GTIOC9A
+    { AF_GPT2, 9,  P410 },                                                                      // GTIOC9B
+    { AF_GPT2, 10, P409 },                                                                      // GTIOC10A
+    { AF_GPT2, 10, P408 },                                                                      // GTIOC10B
+    { AF_GPT2, 11, P500 },                                                                      // GTIOC11A
+    { AF_GPT2, 11, P501 },                                                                      // GTIOC11B
+    { AF_GPT2, 12, P502 }, { AF_GPT2, 12, P908 },                                               // GTIOC12A
+    { AF_GPT2, 12, P503 }, { AF_GPT2, 12, P907 },                                               // GTIOC12B
+    { AF_GPT2, 13, P504 }, { AF_GPT2, 13, P906 },                                               // GTIOC13A
+    { AF_GPT2, 13, P505 }, { AF_GPT2, 13, P905 },                                               // GTIOC13B
+    #elif defined(RA6M5)
+    { AF_GPT2, 0,  P213 }, { AF_GPT2, 0,  P300 }, { AF_GPT2, 0,  P415 }, { AF_GPT2, 0,  P512 }, // GTIOC0A
+    { AF_GPT2, 0,  P108 }, { AF_GPT2, 0,  P212 }, { AF_GPT2, 0,  P414 }, { AF_GPT2, 0,  P511 }, // GTIOC0B
+    { AF_GPT2, 1,  P105 }, { AF_GPT2, 1,  P109 }, { AF_GPT2, 1,  P405 },                        // GTIOC1A
+    { AF_GPT2, 1,  P104 }, { AF_GPT2, 1,  P110 }, { AF_GPT2, 1,  P406 },                        // GTIOC1B
+    { AF_GPT2, 2,  P103 }, { AF_GPT2, 2,  P113 }, { AF_GPT2, 2,  P713 },                        // GTIOC2A
+    { AF_GPT2, 2,  P102 }, { AF_GPT2, 2,  P114 }, { AF_GPT2, 2,  P712 },                        // GTIOC2B
+    { AF_GPT2, 3,  P111 }, { AF_GPT2, 3,  P403 },                                               // GTIOC3A
+    { AF_GPT2, 3,  P112 }, { AF_GPT2, 3,  P404 },                                               // GTIOC3B
+    { AF_GPT2, 4,  P115 }, { AF_GPT2, 4,  P205 }, { AF_GPT2, 4,  P302 },                        // GTIOC4A
+    { AF_GPT2, 4,  P204 }, { AF_GPT2, 4,  P301 }, { AF_GPT2, 4,  P608 },                        // GTIOC4B
+    { AF_GPT2, 5,  P101 }, { AF_GPT2, 5,  P203 }, { AF_GPT2, 5,  P609 }, { AF_GPT2, 5,  P700 }, // GTIOC5A
+    { AF_GPT2, 5,  P100 }, { AF_GPT2, 5,  P202 }, { AF_GPT2, 5,  P610 }, { AF_GPT2, 5,  P701 }, // GTIOC5B
+    { AF_GPT2, 6,  P400 }, { AF_GPT2, 6,  P407 }, { AF_GPT2, 6,  P601 }, { AF_GPT2, 6,  P702 }, // GTIOC6A
+    { AF_GPT2, 6,  P401 }, { AF_GPT2, 6,  P408 }, { AF_GPT2, 6,  P600 }, { AF_GPT2, 6,  P703 }, // GTIOC6B
+    { AF_GPT2, 7,  P304 }, { AF_GPT2, 7,  P603 },                                               // GTIOC7A
+    { AF_GPT2, 7,  P303 }, { AF_GPT2, 7,  P602 },                                               // GTIOC7B
+    { AF_GPT2, 8,  P107 }, { AF_GPT2, 8,  P605 },                                               // GTIOC8A
+    { AF_GPT2, 8,  P106 }, { AF_GPT2, 8,  P604 },                                               // GTIOC8B
+    { AF_GPT2, 9,  P411 },                                                                      // GTIOC9A
+    { AF_GPT2, 9,  P410 },                                                                      // GTIOC9B
+    #else
+    #error "CMSIS MCU Series is not specified."
+    #endif
+};
+
+static float ra_gpt_freq[GPT_CH_SIZE];
+static volatile uint16_t ra_gpt_div[GPT_CH_SIZE];
+
+static void ra_gpt_timer_set_pin(uint32_t pin) {
+    bool find = false;
+    uint32_t ch;
+    uint32_t af;
+    find = ra_af_find_ch_af((ra_af_pin_t *)&ra_gpt_timer_pins, GPT_TMR_PINS_SIZE, pin, &ch, &af);
+    if (find) {             // GPIO_MODE_OUTPUT_PP
+        ra_gpio_config(pin, GPIO_MODE_AF_PP, GPIO_NOPULL, GPIO_LOW_POWER, af);
+    }
+}
+
+static void ra_gpt_timer_release_pin(uint32_t pin) {
+    bool find = false;
+    uint32_t ch;
+    uint32_t af;
+    find = ra_af_find_ch_af((ra_af_pin_t *)&ra_gpt_timer_pins, GPT_TMR_PINS_SIZE, pin, &ch, &af);
+    if (find) {                                                    // GPIO_PULLUP
+        ra_gpio_config(pin, GPIO_MODE_INPUT, GPIO_NOPULL, GPIO_LOW_POWER, AF_GPIO);
+    }
+}
+
+bool ra_gpt_timer_is_pwm_pin(uint32_t pin) {
+    uint32_t ch;
+    uint32_t af;
+    return ra_af_find_ch_af((ra_af_pin_t *)&ra_gpt_timer_pins, GPT_TMR_PINS_SIZE, pin, &ch, &af);
+}
+
+void ra_gpt_timer_start(uint32_t ch) {
+    if (CH_GAP || (ch >= GPT_CH_SIZE)) {
+        return;
+    }
+    gpt_regs[ch]->GTCR_b.CST = 1;
+}
+
+void ra_gpt_timer_stop(uint32_t ch) {
+    if (CH_GAP || (ch >= GPT_CH_SIZE)) {
+        return;
+    }
+    gpt_regs[ch]->GTCR_b.CST = 0;
+}
+
+void ra_gpt_timer_set_freq(uint32_t ch, float freq) {
+    R_GPT0_Type *gpt_reg = gpt_regs[ch];
+    uint8_t source = 0;
+    uint32_t period = 0;
+    ra_gpt_freq[ch] = 0.0f;
+
+    if ((!gpt_reg) || (ch >= GPT_CH_SIZE) || (freq == ra_gpt_freq[ch]) || (freq == 0.0f)) {
+        return;
+    }
+
+    ra_gpt_div[ch] = 0;
+
+    #ifdef RA4M1
+    if (ch <= 1) { // 32bit
+    #elif defined(RA4W1) || defined(RA6M5)
+    if (ch <= 3) { // 32bit
+    #elif defined(RA6M1) || defined(RA6M2) || defined(RA6M3)
+    if (1) { // all is 32bit
+    #else
+    #error What is the width of the timer? (How many bits)
+        #endif
+        // float min_freq = ((float)PCLK)/4294967295.0f;
+        if ((freq > (float)(PCLK / 2)) || (freq <= 0.0f)) {
+            return;
+        } else {
+            source = GPT_PCLKD;
+            period = (uint32_t)((float)(PCLK) / freq);
+        }
+    } else { // 16bit
+        float min_freq = ((float)PCLK) / 65565.0f;
+
+        if (freq > (float)(PCLK / 2)) {
+            return;
+        } else if (freq > min_freq) {
+            source = GPT_PCLKD;
+            period = (uint16_t)((float)(PCLK) / freq);
+        } else if (freq > (min_freq / 4.0f)) {
+            source = GPT_PCLKD4;
+            ra_gpt_div[ch] = 4;
+            period = (uint16_t)(((float)(PCLK) / 4.0f) / freq);
+        } else if (freq > (min_freq / 16.0f)) {
+            source = GPT_PCLKD16;
+            ra_gpt_div[ch] = 16;
+            period = (uint16_t)(((float)(PCLK) / 16.0f) / freq);
+        } else if (freq > (min_freq / 64.0f)) {
+            source = GPT_PCLKD64;
+            ra_gpt_div[ch] = 64;
+            period = (uint16_t)(((float)(PCLK) / 64.0f) / freq);
+        } else if (freq > (min_freq / 256.0f)) {
+            source = GPT_PCLKD256;
+            ra_gpt_div[ch] = 256;
+            period = (uint16_t)(((float)(PCLK) / 256.0f) / freq);
+        } else if (freq > (min_freq / 1024.0f)) {
+            source = GPT_PCLKD1024;
+            ra_gpt_div[ch] = 1024;
+            period = (uint16_t)(((float)(PCLK) / 1024.0f) / freq);
+        } else {
+            return;
+        }
+    }
+
+    ra_gpt_freq[ch] = freq;
+
+    float dutyA = (gpt_reg->GTIOR_b.OAE && gpt_reg->GTCCR[0] && gpt_reg->GTPR)? (float)(gpt_reg->GTCCR[0] + 1) / (float)(gpt_reg->GTPR + 1) : 0.0f;
+    float dutyB = (gpt_reg->GTIOR_b.OBE && gpt_reg->GTCCR[0] && gpt_reg->GTPR)? (float)(gpt_reg->GTCCR[1] + 1) / (float)(gpt_reg->GTPR + 1) : 0.0f;
+
+    if (gpt_reg->GTCR_b.CST) { // running
+        if ((gpt_reg->GTCR >> 23) != source) {    // Can't use gpt_reg->GTCR_b.TPCS this structure is declared wrong by FPS v2.3.0 so get the whole reg
+            gpt_reg->GTCR_b.CST = 0;               // stop counter
+            gpt_reg->GTCR_b.TPCS = source << 1;    // Again gpt_reg->GTCR_b.TPCS is wrong and incoming value should be shifted
+            gpt_reg->GTPR = period - 1;
+            gpt_reg->GTPBR = period - 1;
+
+            if (dutyA > 0.0f) {
+                dutyA = dutyA * ((float)(period));
+                gpt_reg->GTCCR[0] = (uint32_t)(dutyA - 1.0f);
+                gpt_reg->GTCCR[2] = gpt_reg->GTCCR[0];
+            }
+
+            if (dutyB > 0.0f) {
+                dutyB = dutyB * ((float)(period));
+                gpt_reg->GTCCR[1] = (uint32_t)(dutyB - 1.0f);
+                gpt_reg->GTCCR[3] = gpt_reg->GTCCR[1];
+            }
+
+            gpt_reg->GTCNT = 0ul;        // clear counter
+            gpt_reg->GTCR_b.CST = 1;     // start counter
+        } else {
+            // gpt_reg->GTPR = period-1;
+            gpt_reg->GTPBR = period - 1;
+
+            if (dutyA > 0.0f) {
+                dutyA = dutyA * ((float)(period));
+                // gpt_reg->GTCCR[0] = (uint32_t)(dutyA - 1.0f);
+                gpt_reg->GTCCR[2] = (uint32_t)(dutyA - 1.0f);
+            }
+
+            if (dutyB > 0.0f) {
+                dutyB = dutyB * ((float)(period));
+                // gpt_reg->GTCCR[1] = (uint32_t)(dutyB - 1.0f);
+                gpt_reg->GTCCR[3] = (uint32_t)(dutyB - 1.0f);
+            }
+        }
+    } else { // stopped
+        gpt_reg->GTCR_b.TPCS = source << 1;
+        gpt_reg->GTPR = period - 1;
+        gpt_reg->GTPBR = period - 1;
+
+        if (dutyA > 0.0f) {
+            dutyA = dutyA * ((float)(period));
+            gpt_reg->GTCCR[0] = (uint32_t)(dutyA - 1.0f);
+            gpt_reg->GTCCR[2] = gpt_reg->GTCCR[0];
+        }
+
+        if (dutyB > 0.0f) {
+            dutyB = dutyB * ((float)(period));
+            gpt_reg->GTCCR[1] = (uint32_t)(dutyB - 1.0f);
+            gpt_reg->GTCCR[3] = gpt_reg->GTCCR[1];
+        }
+    }
+}
+
+float ra_gpt_timer_get_freq(uint32_t ch) {
+    return (CH_GAP || (ch >= GPT_CH_SIZE))? 0.0f : ra_gpt_freq[ch];
+}
+
+float ra_gpt_timer_tick_time(uint32_t ch) {
+    if (CH_GAP || (ch >= GPT_CH_SIZE)) {
+        return 0.0f;
+    } else {
+        float NS = 1000000000.0f;
+        if (ra_gpt_div[ch]) {
+            NS *= (float)ra_gpt_div[ch];
+        }
+        return NS / (float)(PCLK);
+    }
+}
+
+/*
+void ra_gpt_timer_set_period(uint32_t ch, uint32_t ns)
+{
+    R_GPT0_Type *gpt_reg = gpt_regs[ch];
+
+    if((!gpt_reg) || (ch >= GPT_CH_SIZE))
+        return;
+
+    if(ch <= 3)
+    {  //32bit
+    }
+    else
+    {  //16bit
+    }
+}
+*/
+
+uint32_t ra_gpt_timer_get_period(uint32_t ch) {
+    R_GPT0_Type *gpt_reg = gpt_regs[ch];
+
+    if ((!gpt_reg) || (ch >= GPT_CH_SIZE)) {
+        return 0ul;
+    } else {
+        return gpt_reg->GTPR + 1;
+    }
+}
+
+void ra_gpt_timer_set_duty(uint32_t ch, uint8_t id, uint32_t duty) {
+    R_GPT0_Type *gpt_reg = gpt_regs[ch];
+
+    if ((!gpt_reg) || (ch >= GPT_CH_SIZE)) {
+        return;
+    } else {
+        if (gpt_reg->GTCR_b.CST) {
+            gpt_reg->GTCCR[(id == 'A')? 2 : 3] = duty? duty - 1 : duty;
+        } else {
+            gpt_reg->GTCCR[(id == 'A')? 0 : 1] = duty? duty - 1 : duty;
+            if (id == 'A') {
+                gpt_reg->GTCCR[2] = gpt_reg->GTCCR[0];
+            } else {
+                gpt_reg->GTCCR[3] = gpt_reg->GTCCR[1];
+            }
+        }
+    }
+}
+
+uint32_t ra_gpt_timer_get_duty(uint32_t ch, uint8_t id) {
+    R_GPT0_Type *gpt_reg = gpt_regs[ch];
+    if ((!gpt_reg) || (ch >= GPT_CH_SIZE)) {
+        return 0ul;
+    } else
+    if (id == 'A') {
+        return (gpt_reg->GTCCR[0])? gpt_reg->GTCCR[0] + 1 : 0;
+    } else {
+        return (gpt_reg->GTCCR[1])? gpt_reg->GTCCR[1] + 1 : 0;
+    }
+}
+
+void ra_gpt_timer_init(uint32_t pwm_pin, uint32_t ch, uint8_t id, uint32_t duty, float freq) {
+    R_GPT0_Type *gpt_reg = gpt_regs[ch];
+
+    if ((!gpt_reg) || (ch >= GPT_CH_SIZE)) {
+        return;
+    }
+
+    #ifdef RA4M1
+    if (ch <= 1) {
+    #elif defined(RA4W1)
+    if (ch <= 3) {
+    #elif defined(RA6M1) || defined(RA6M2) || defined(RA6M3)
+    if (ch <= 7) {
+    #elif defined(RA6M5)
+    if (ch <= 9) {
+    #else
+    #error Choose proper clock enable BIT!
+        #endif
+        #ifdef RA6M5
+        // R_MSTP_MSTPCRE_MSTPE22_Msk - R_MSTP_MSTPCRE_MSTPE31_Msk
+        ra_mstpcre_start(1UL << (31 - ch));
+        #else
+        ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD5_Msk);
+        #endif
+    } else {
+        ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD6_Msk);
+    }
+
+    ra_gpt_timer_stop(ch);                          // Stop the timer
+    gpt_reg->GTCR_b.MD = 0;                         // Set operating mode
+    gpt_reg->GTUDDTYC_b.UD = 1;                     // Set count direction
+    gpt_reg->GTBER_b.PR = 1;                        // Set buffer operation for the period
+    ra_gpt_timer_set_freq(ch, freq);                // Set count clock & cycle
+
+    gpt_reg->GTCNT = 0;                             // Set initial value for counter
+    if (id == 'A') {
+        gpt_reg->GTIOR_b.GTIOA = 0x9;               // Set GTIOC pin function (Initial low -> Low at GTCCRA/B compare match -> High at cycle end)
+        gpt_reg->GTIOR_b.OAE = 1;                   // Enable GTIOC pin output
+        gpt_reg->GTBER_b.CCRA = 1;                  // Set buffer operation for the duty
+        gpt_reg->GTCCR[0] = duty? duty - 1 : duty;  // Set compare match value
+        gpt_reg->GTCCR[2] = gpt_reg->GTCCR[0];
+    } else {
+        gpt_reg->GTIOR_b.GTIOB = 0x9;
+        gpt_reg->GTIOR_b.OBE = 1;
+        gpt_reg->GTBER_b.CCRB = 1;
+        gpt_reg->GTCCR[1] = duty? duty - 1 : duty;
+        gpt_reg->GTCCR[3] = gpt_reg->GTCCR[1];
+    }
+
+    ra_gpt_timer_set_pin(pwm_pin);
+
+    if (gpt_reg->GTPR && gpt_reg->GTCCR[(id == 'A')? 0 : 1]) {
+        ra_gpt_timer_start(ch);
+    }
+}
+
+void ra_gpt_timer_deinit(uint32_t pwm_pin, uint32_t ch, uint8_t id) {
+    if (CH_GAP || (ch >= GPT_CH_SIZE)) {
+        return;
+    }
+    ra_gpt_timer_stop(ch);
+
+    ra_gpt_div[ch] = 0;
+    ra_gpt_freq[ch] = 0;
+
+    gpt_regs[ch]->GTPR = 0;
+    gpt_regs[ch]->GTPBR = 0;
+
+    if (id == 'A') {
+        gpt_regs[ch]->GTIOR_b.OAE = 0;
+        gpt_regs[ch]->GTCCR[0] = 0;
+        gpt_regs[ch]->GTCCR[2] = 0;
+    } else {
+        gpt_regs[ch]->GTIOR_b.OBE = 0;
+        gpt_regs[ch]->GTCCR[1] = 0;
+        gpt_regs[ch]->GTCCR[3] = 0;
+    }
+
+    #ifdef RA4M1
+    if (ch <= 1) {
+    #elif defined(RA4W1)
+    if (ch <= 3) {
+    #elif defined(RA6M1) || defined(RA6M2) || defined(RA6M3)
+    if (ch <= 7) {
+    #elif defined(RA6M5)
+    if (ch <= 9) {
+    #else
+    #error Choose proper clock enable BIT!
+        #endif
+        #ifdef RA6M5
+        ra_mstpcre_stop(1UL << (31 - ch));
+        #else
+        ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD5_Msk);
+        #endif
+    } else {
+        ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD6_Msk);
+    }
+
+    ra_gpt_timer_release_pin(pwm_pin);
+}
diff --git a/ports/renesas-ra/ra/ra_gpt.h b/ports/renesas-ra/ra/ra_gpt.h
new file mode 100644
index 0000000000..9f88acbbf3
--- /dev/null
+++ b/ports/renesas-ra/ra/ra_gpt.h
@@ -0,0 +1,43 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Vekatech Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef RA_RA_GPT_H_
+#define RA_RA_GPT_H_
+
+#include <stdint.h>
+
+void ra_gpt_timer_start(uint32_t ch);
+void ra_gpt_timer_stop(uint32_t ch);
+void ra_gpt_timer_set_freq(uint32_t ch, float freq);
+float ra_gpt_timer_get_freq(uint32_t ch);
+float ra_gpt_timer_tick_time(uint32_t ch);
+void ra_gpt_timer_set_period(uint32_t ch, uint32_t ns);
+uint32_t ra_gpt_timer_get_period(uint32_t ch);
+void ra_gpt_timer_set_duty(uint32_t ch, uint8_t id, uint32_t duty);
+uint32_t ra_gpt_timer_get_duty(uint32_t ch, uint8_t id);
+void ra_gpt_timer_init(uint32_t pwm_pin, uint32_t ch, uint8_t id, uint32_t duty, float freq);
+void ra_gpt_timer_deinit(uint32_t pwm_pin, uint32_t ch, uint8_t id);
+bool ra_gpt_timer_is_pwm_pin(uint32_t pin);
+
+#endif /* RA_RA_GPT_H_ */
diff --git a/ports/renesas-ra/ra/ra_i2c.c b/ports/renesas-ra/ra/ra_i2c.c
index ad1e3a74e0..783c0c9215 100644
--- a/ports/renesas-ra/ra/ra_i2c.c
+++ b/ports/renesas-ra/ra/ra_i2c.c
@@ -68,7 +68,7 @@ static const ra_af_pin_t scl_pins[] = {
     { AF_I2C, 1, P100 },
     { AF_I2C, 1, P205 },
 
-    #elif defined(RA6M2)
+    #elif defined(RA6M2) || defined(RA6M3)
 
     { AF_I2C, 0, P204 },
     { AF_I2C, 0, P400 },
@@ -76,6 +76,16 @@ static const ra_af_pin_t scl_pins[] = {
     { AF_I2C, 1, P100 },
     { AF_I2C, 1, P205 },
     { AF_I2C, 2, P512 },
+
+    #elif defined(RA6M5)
+
+    { AF_I2C, 0, P400 },
+    { AF_I2C, 0, P408 },
+    { AF_I2C, 1, P205 },
+    { AF_I2C, 1, P512 },
+    { AF_I2C, 2, P410 },
+    { AF_I2C, 2, P415 },
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
@@ -103,7 +113,7 @@ static const ra_af_pin_t sda_pins[] = {
     { AF_I2C, 1, P101 },
     { AF_I2C, 1, P206 },
 
-    #elif defined(RA6M2)
+    #elif defined(RA6M2) || defined(RA6M3)
 
     { AF_I2C, 0, P401 },
     { AF_I2C, 0, P407 },
@@ -111,6 +121,15 @@ static const ra_af_pin_t sda_pins[] = {
     { AF_I2C, 1, P206 },
     { AF_I2C, 2, P511 },
 
+    #elif defined(RA6M5)
+
+    { AF_I2C, 0, P401 },
+    { AF_I2C, 0, P407 },
+    { AF_I2C, 1, P206 },
+    { AF_I2C, 1, P511 },
+    { AF_I2C, 2, P409 },
+    { AF_I2C, 2, P414 },
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
@@ -305,11 +324,16 @@ static void ra_i2c_clock_calc(uint32_t baudrate, uint8_t *cks, uint8_t *brh, uin
         *cks = 1;
         *brh = 9;
         *brl = 20;
-    } else {
+    } else if (baudrate >= 100000) {
         // assume clock is 100000Hz (PCLKB 32MHz)
         *cks = 3;
         *brh = 15;
         *brl = 18;
+    } else {
+        // assume clock is 50000Hz (PCLKB 32MHz)
+        *cks = 4;
+        *brh = 15;
+        *brl = 18;
     }
     #elif defined(RA6M1)
     // PCLKB 60MHz SCLE=0
@@ -328,7 +352,7 @@ static void ra_i2c_clock_calc(uint32_t baudrate, uint8_t *cks, uint8_t *brh, uin
         *brh = 14;
         *brl = 17;
     }
-    #elif defined(RA6M2)
+    #elif defined(RA6M2) || defined(RA6M3)
     // PCLKB 60MHz SCLE=0
     if (baudrate >= RA_I2C_CLOCK_MAX) {
         *cks = 0;
@@ -339,11 +363,38 @@ static void ra_i2c_clock_calc(uint32_t baudrate, uint8_t *cks, uint8_t *brh, uin
         *cks = 2;
         *brh = 8;
         *brl = 19;
-    } else {
+    } else if (baudrate >= 100000) {
         // assume clock is 100000Hz
         *cks = 4;
         *brh = 14;
         *brl = 17;
+    } else {
+        // assume clock is 50000Hz
+        *cks = 5;
+        *brh = 14;
+        *brl = 17;
+    }
+    #elif defined(RA6M5)
+    // PCLKB 50MHz SCLE=0
+    if (baudrate >= RA_I2C_CLOCK_MAX) {
+        *cks = 0;
+        *brh = 12;
+        *brl = 24;
+    } else if (baudrate >= 400000) {
+        // assume clock is 400000Hz
+        *cks = 2;
+        *brh = 7;
+        *brl = 15;
+    } else if (baudrate >= 100000) {
+        // assume clock is 100000Hz
+        *cks = 3;
+        *brh = 24;
+        *brl = 30;
+    } else {
+        // assume clock is 50000Hz
+        *cks = 4;
+        *brh = 24;
+        *brl = 30;
     }
     #else
     #error "CMSIS MCU Series is not specified."
@@ -458,7 +509,9 @@ static void ra_i2c_iceri_isr(R_IIC0_Type *i2c_inst) {
     }
     // Check Start
     if (i2c_inst->ICSR2_b.START != 0) {
-        action->m_status = RA_I2C_STATUS_Started;
+        if (action->m_status == RA_I2C_STATUS_Idle) {
+            action->m_status = RA_I2C_STATUS_Started;
+        }
         i2c_inst->ICSR2_b.START = 0;
     }
     // Check Stop
@@ -504,8 +557,8 @@ static void ra_i2c_icrxi_isr(R_IIC0_Type *i2c_inst) {
 static void ra_i2c_ictxi_isr(R_IIC0_Type *i2c_inst) {
     xaction_t *action = current_xaction;
     xaction_unit_t *unit = current_xaction_unit;
-
-    if (action->m_status == RA_I2C_STATUS_Started) {
+    // When STIE is already checked.        When TIE occurs before STIE
+    if (action->m_status == RA_I2C_STATUS_Started || action->m_status == RA_I2C_STATUS_Idle) {
         i2c_inst->ICDRT = action->m_address;  // I2C send slave address
         action->m_status = RA_I2C_STATUS_AddrWriteCompleted;
         return;
diff --git a/ports/renesas-ra/ra/ra_i2c.h b/ports/renesas-ra/ra/ra_i2c.h
index 93a170ab8a..e2432675a0 100644
--- a/ports/renesas-ra/ra/ra_i2c.h
+++ b/ports/renesas-ra/ra/ra_i2c.h
@@ -28,6 +28,13 @@
 #include <stdint.h>
 #include <stdbool.h>
 
+#ifdef RA6M5
+// #define R_IIC2_BASE            0x4009F200
+#ifndef R_IIC2
+#define R_IIC2             ((R_IIC0_Type *)0x4009F200)
+#endif
+#endif
+
 #define RA_I2C_DEF_TIMEOUT              1000    // 1000 ms
 #define RA_I2C_TIMEOUT_STOP_CONDITION   100000  // counts
 #define RA_I2C_TIMEOUT_BUS_BUSY         100000  // counts
diff --git a/ports/renesas-ra/ra/ra_icu.c b/ports/renesas-ra/ra/ra_icu.c
index 000667b4c6..caac8bfe22 100644
--- a/ports/renesas-ra/ra/ra_icu.c
+++ b/ports/renesas-ra/ra/ra_icu.c
@@ -345,6 +345,180 @@ static const ra_icu_pin_t ra_irq_pins[] = {
     { 15, P511 },
     #endif
 
+    #elif defined(RA6M3)
+
+    #if defined(VECTOR_NUMBER_ICU_IRQ0)
+    { 0, P105 },
+    { 0, P206 }, /* DS */
+    { 0, P400 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ1)
+    { 1, P101 },
+    { 1, P104 },
+    { 1, P205 }, /* DS */
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ2)
+    { 2, P100 },
+    { 2, P213 },
+    { 2, P203 }, /* DS */
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ3)
+    { 3, P110 },
+    { 3, P212 },
+    { 3, P202 }, /* DS */
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ4)
+    { 4, P111 },
+    { 4, P402 }, /* DS */
+    { 4, P411 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ5)
+    { 5, P302 },
+    { 5, P401 }, /* DS */
+    { 5, P410 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ6)
+    { 6, P000 }, /* DS */
+    { 6, P301 },
+    { 6, P409 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ7)
+    { 7, P001 }, /* DS */
+    { 7, P408 },
+    { 7, P706 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ8)
+    { 8, P002 }, /* DS */
+    { 8, P305 },
+    { 8, P415 },
+    { 8, P707 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ9)
+    { 9, P004 }, /*  DS */
+    { 9, P304 },
+    { 9, P414 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ10)
+    { 10, P005 }, /* DS */
+    { 10, P709 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ11)
+    { 11, P006 }, /* DS */
+    { 11, P501 },
+    { 11, P708 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ12)
+    { 12, P008 }, /* DS */
+    { 12, P502 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ13)
+    { 13, P009 }, /* DS */
+    { 13, P015 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ14)
+    { 14, P505 },
+    { 14, P512 },
+    { 14, P010 }, /* DS */
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ15)
+    { 15, P506 },
+    { 15, P511 },
+    #endif
+
+    #elif defined(RA6M5)
+
+    #if defined(VECTOR_NUMBER_ICU_IRQ0)
+    { 0, P105 },
+    { 0, P206 }, /* DS */
+    { 0, P400 },
+    { 0, P806 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ1)
+    { 1, P101 },
+    { 1, P104 },
+    { 1, P205 }, /* DS */
+    { 1, P804 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ2)
+    { 2, P100 },
+    { 2, P203 }, /* DS */
+    { 2, P213 },
+    { 2, P803 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ3)
+    { 3, P110 },
+    { 3, P202 }, /* DS */
+    { 3, P212 },
+    { 3, P802 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ4)
+    { 4, P111 },
+    { 4, P402 }, /* DS */
+    { 4, P411 },
+    { 4, PA10 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ5)
+    { 5, P302 },
+    { 5, P401 }, /* DS */
+    { 5, P410 },
+    { 5, PA09 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ6)
+    { 6, P000 }, /* DS */
+    { 6, P301 },
+    { 6, P409 },
+    { 6, PA08 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ7)
+    { 7, P001 }, /* DS */
+    { 7, P408 },
+    { 7, P706 },
+    { 7, P615 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ8)
+    { 8, P002 }, /* DS */
+    { 8, P305 },
+    { 8, P415 },
+    { 8, P707 },
+    { 8, P905 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ9)
+    { 9, P004 }, /*  DS */
+    { 9, P304 },
+    { 9, P414 },
+    { 9, P906 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ10)
+    { 10, P005 }, /* DS */
+    { 10, P709 },
+    { 10, P907 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ11)
+    { 11, P006 }, /* DS */
+    { 11, P501 },
+    { 11, P708 },
+    { 11, P908 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ12)
+    { 12, P008 }, /* DS */
+    { 12, P502 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ13)
+    { 13, P009 }, /* DS */
+    { 13, P015 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ14)
+    { 14, P010 },
+    { 14, P403 }, /* DS */
+    { 14, P505 },
+    { 14, P512 },
+    #endif
+    #if defined(VECTOR_NUMBER_ICU_IRQ15)
+    { 15, P404 }, /* DS */
+    { 15, P506 },
+    { 15, P511 },
+    #endif
+
     #else
     #error "CMSIS MCU Series is not speficied."
     #endif
diff --git a/ports/renesas-ra/ra/ra_int.h b/ports/renesas-ra/ra/ra_int.h
index cd12908bcd..1b92db99cc 100644
--- a/ports/renesas-ra/ra/ra_int.h
+++ b/ports/renesas-ra/ra/ra_int.h
@@ -29,7 +29,7 @@
 
 #if defined(RA4M1) | defined(RA4W1)
 #define IRQ_MAX 48
-#elif defined(RA6M1) | defined(RA6M2)
+#elif defined(RA6M1) | defined(RA6M2) | defined(RA6M3) | defined(RA6M5)
 #define IRQ_MAX 128
 #else
 #error "CMSIS MCU Series is not specified."
diff --git a/ports/renesas-ra/ra/ra_rtc.c b/ports/renesas-ra/ra/ra_rtc.c
index f108de568d..e23a4d42d2 100644
--- a/ports/renesas-ra/ra/ra_rtc.c
+++ b/ports/renesas-ra/ra/ra_rtc.c
@@ -34,7 +34,7 @@
 #include "hal_data.h"
 #include "ra_rtc.h"
 
-static R_RTC_Type *rtc_reg = (R_RTC_Type *)0x40044000;
+static R_RTC_Type *rtc_reg = R_RTC;
 static R_SYSTEM_Type *system_reg = (R_SYSTEM_Type *)0x4001E000;
 
 #if defined(VECTOR_NUMBER_RTC_ALARM)
diff --git a/ports/renesas-ra/ra/ra_sci.c b/ports/renesas-ra/ra/ra_sci.c
index 5d14067248..81f3ff9675 100644
--- a/ports/renesas-ra/ra/ra_sci.c
+++ b/ports/renesas-ra/ra/ra_sci.c
@@ -265,34 +265,34 @@ static uint32_t ch_to_idx[SCI_CH_MAX] = {
 
 static R_SCI0_Type *sci_regs[] = {
     #if defined(VECTOR_NUMBER_SCI0_RXI)
-    (R_SCI0_Type *)0x40070000,
+    R_SCI0,
     #endif
     #if defined(VECTOR_NUMBER_SCI1_RXI)
-    (R_SCI0_Type *)0x40070020,
+    R_SCI1,
     #endif
     #if defined(VECTOR_NUMBER_SCI2_RXI)
-    (R_SCI0_Type *)0x40070040,
+    R_SCI2,
     #endif
     #if defined(VECTOR_NUMBER_SCI3_RXI)
-    (R_SCI0_Type *)0x40070060,
+    R_SCI3,
     #endif
     #if defined(VECTOR_NUMBER_SCI4_RXI)
-    (R_SCI0_Type *)0x40070080,
+    R_SCI4,
     #endif
     #if defined(VECTOR_NUMBER_SCI5_RXI)
-    (R_SCI0_Type *)0x400700a0,
+    R_SCI5,
     #endif
     #if defined(VECTOR_NUMBER_SCI6_RXI)
-    (R_SCI0_Type *)0x400700c0,
+    R_SCI6,
     #endif
     #if defined(VECTOR_NUMBER_SCI7_RXI)
-    (R_SCI0_Type *)0x400700e0,
+    R_SCI7,
     #endif
     #if defined(VECTOR_NUMBER_SCI8_RXI)
-    (R_SCI0_Type *)0x40070100,
+    R_SCI8,
     #endif
     #if defined(VECTOR_NUMBER_SCI9_RXI)
-    (R_SCI0_Type *)0x40070120,
+    R_SCI9,
     #endif
 };
 
@@ -408,6 +408,77 @@ static const ra_af_pin_t ra_sci_tx_pins[] = {
     { AF_SCI2, 9, P203 },
     { AF_SCI2, 9, P602 },
 
+    #elif defined(RA6M3)
+
+    { AF_SCI1, 0, P101 },
+    { AF_SCI1, 0, P411 },
+
+    { AF_SCI2, 1, P213 },
+    { AF_SCI2, 1, P709 },
+
+    { AF_SCI1, 2, P112 },
+    { AF_SCI1, 2, P302 },
+
+    { AF_SCI2, 3, P310 },
+    { AF_SCI2, 3, P409 },
+    { AF_SCI2, 3, P707 },
+
+    { AF_SCI1, 4, P205 },
+    { AF_SCI1, 4, P512 },
+    { AF_SCI1, 4, P900 },
+
+    { AF_SCI2, 5, P501 },
+    { AF_SCI2, 5, P805 },
+
+    { AF_SCI1, 6, P305 },
+    { AF_SCI1, 6, P506 },
+
+    { AF_SCI2, 7, P401 },
+    { AF_SCI2, 7, P613 },
+
+    { AF_SCI1, 8, P105 },
+    { AF_SCI1, 8, PA00 },
+
+    { AF_SCI2, 9, P109 },
+    { AF_SCI2, 9, P203 },
+    { AF_SCI2, 9, P602 },
+
+    #elif defined(RA6M5)
+
+    { AF_SCI1, 0, P101 },
+    { AF_SCI1, 0, P411 },
+
+    { AF_SCI2, 1, P213 },
+    { AF_SCI2, 1, P709 },
+
+    { AF_SCI1, 2, P112 },
+    { AF_SCI1, 2, P302 },
+
+    { AF_SCI2, 3, P310 },
+    { AF_SCI2, 3, P409 },
+    { AF_SCI2, 3, P707 },
+
+    { AF_SCI1, 4, P205 },
+    { AF_SCI1, 4, P207 },
+    { AF_SCI1, 4, P512 },
+    { AF_SCI1, 4, P900 },
+
+    { AF_SCI2, 5, P501 },
+    { AF_SCI2, 5, P805 },
+
+    { AF_SCI1, 6, P305 },
+    { AF_SCI1, 6, P506 },
+
+    { AF_SCI2, 7, P401 },
+    { AF_SCI2, 7, P613 },
+
+    { AF_SCI1, 8, P105 },
+    { AF_SCI1, 8, PA00 },
+
+    { AF_SCI2, 9, P109 },
+    { AF_SCI2, 9, P203 },
+    { AF_SCI2, 9, P602 },
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
@@ -496,6 +567,41 @@ static const ra_af_pin_t ra_sci_rx_pins[] = {
     { AF_SCI2, 9, P202 },
     { AF_SCI2, 9, P601 },
 
+    #elif defined(RA6M3) || defined(RA6M5)
+
+    { AF_SCI1, 0, P100 },
+    { AF_SCI1, 0, P410 },
+
+    { AF_SCI2, 1, P212 },
+    { AF_SCI2, 1, P708 },
+
+    { AF_SCI1, 2, P113 },
+    { AF_SCI1, 2, P301 },
+
+    { AF_SCI2, 3, P309 },
+    { AF_SCI2, 3, P408 },
+    { AF_SCI2, 3, P706 },
+
+    { AF_SCI1, 4, P206 },
+    { AF_SCI1, 4, P315 },
+    { AF_SCI1, 4, P511 },
+
+    { AF_SCI2, 5, P502 },
+    { AF_SCI2, 5, P513 },
+
+    { AF_SCI1, 6, P304 },
+    { AF_SCI1, 6, P505 },
+
+    { AF_SCI2, 7, P402 },
+    { AF_SCI2, 7, P614 },
+
+    { AF_SCI1, 8, P104 },
+    { AF_SCI1, 8, P607 },
+
+    { AF_SCI2, 9, P110 },
+    { AF_SCI2, 9, P202 },
+    { AF_SCI2, 9, P601 },
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
@@ -584,6 +690,93 @@ static const ra_af_pin_t ra_sci_cts_pins[] = {
     { AF_SCI2, 9, P301 },
     { AF_SCI2, 9, P603 },
 
+    #elif defined(RA6M3)
+
+    { AF_SCI1, 0, P103 },
+    { AF_SCI1, 0, P413 },
+
+    { AF_SCI2, 1, P101 },
+    { AF_SCI2, 1, P711 },
+
+    { AF_SCI1, 2, P110 },
+    { AF_SCI1, 2, P203 },
+
+    { AF_SCI2, 3, P312 },
+    { AF_SCI2, 3, P411 },
+    { AF_SCI2, 3, PB01 },
+
+    { AF_SCI1, 4, P401 },
+    { AF_SCI1, 4, P407 },
+
+    { AF_SCI2, 5, P504 },
+    { AF_SCI2, 5, P507 },
+
+    { AF_SCI1, 6, P307 },
+    { AF_SCI1, 6, P503 },
+
+    { AF_SCI2, 7, P403 },
+    { AF_SCI2, 7, P611 },
+
+    { AF_SCI1, 8, P107 },
+    { AF_SCI1, 8, P606 },
+
+    { AF_SCI2, 9, P108 },
+    { AF_SCI2, 9, P205 },
+    { AF_SCI2, 9, P301 },
+    { AF_SCI2, 9, P603 },
+
+    #elif defined(RA6M5)
+
+    { AF_SCI1, 0, P103 },
+    { AF_SCI1, 0, P413 },
+    { AF_SCI1, 0, P414 }, /* CTS only */
+    { AF_SCI1, 0, P800 }, /* CTS only */
+
+    { AF_SCI2, 1, P101 },
+    { AF_SCI2, 1, P711 },
+
+    { AF_SCI1, 2, P110 },
+    { AF_SCI1, 2, P203 },
+
+    { AF_SCI2, 3, P308 }, /* CTS only */
+    { AF_SCI2, 3, P312 },
+    { AF_SCI2, 3, P411 },
+    { AF_SCI2, 3, P412 }, /* CTS only */
+    { AF_SCI2, 3, P705 }, /* CTS only */
+
+    { AF_SCI1, 4, P401 },
+    { AF_SCI1, 4, P402 }, /* CTS only */
+    { AF_SCI1, 4, P407 },
+    { AF_SCI1, 4, P408 }, /* CTS only */
+
+    { AF_SCI2, 5, P500 }, /* CTS only */
+    { AF_SCI2, 5, P504 },
+    { AF_SCI2, 5, P508 },
+
+    { AF_SCI1, 6, P307 },
+    { AF_SCI1, 6, P308 }, /* CTS only */
+    { AF_SCI1, 6, P502 }, /* CTS only */
+    { AF_SCI1, 6, P503 },
+
+    { AF_SCI2, 7, P403 },
+    { AF_SCI2, 7, P404 }, /* CTS only */
+    { AF_SCI2, 7, P610 }, /* CTS only */
+    { AF_SCI2, 7, P611 },
+
+    { AF_SCI1, 8, P107 },
+    { AF_SCI1, 8, P605 }, /* CTS only */
+    { AF_SCI1, 8, P606 },
+    { AF_SCI1, 8, P801 }, /* CTS only */
+
+    { AF_SCI2, 9, P108 },
+    { AF_SCI2, 9, P114 }, /* CTS only */
+    { AF_SCI2, 9, P205 },
+    { AF_SCI2, 9, P206 }, /* CTS only */
+    { AF_SCI2, 9, P301 },
+    { AF_SCI2, 9, P303 }, /* CTS only */
+    { AF_SCI2, 9, P603 },
+    { AF_SCI2, 9, P604 }, /* CTS only */
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
diff --git a/ports/renesas-ra/ra/ra_spi.c b/ports/renesas-ra/ra/ra_spi.c
index 096519ffd6..b0bb01bfb9 100644
--- a/ports/renesas-ra/ra/ra_spi.c
+++ b/ports/renesas-ra/ra/ra_spi.c
@@ -38,8 +38,8 @@
 #endif
 
 static R_SPI0_Type *spi_regs[] = {
-    (R_SPI0_Type *)0x40072000,
-    (R_SPI0_Type *)0x40072100,
+    R_SPI0,
+    R_SPI1,
 };
 
 static const ra_af_pin_t mosi_pins[] = {
@@ -61,7 +61,7 @@ static const ra_af_pin_t mosi_pins[] = {
     { AF_SPI, 0, P411 }, /* MOSIA_B */
     { AF_SPI, 1, P109 }, /* MOSIB_B */
 
-    #elif defined(RA6M2)
+    #elif defined(RA6M2) || defined(RA6M3)
 
     { AF_SPI, 0, P101 }, /* MOSIA_A */
     { AF_SPI, 0, P411 }, /* MOSIA_B */
@@ -69,6 +69,14 @@ static const ra_af_pin_t mosi_pins[] = {
     { AF_SPI, 1, P203 }, /* MOSIB_A */
     { AF_SPI, 1, P701 }, /* MOSIB_C */
 
+    #elif defined(RA6M5)
+
+    { AF_SPI, 0, P109 }, /* MOSIA_B */
+    { AF_SPI, 0, P203 }, /* MOSIA_A */
+    { AF_SPI, 0, P701 }, /* MOSIA_C */
+    { AF_SPI, 1, P101 }, /* MOSIB_A */
+    { AF_SPI, 1, P411 }, /* MOSIB_B */
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
@@ -94,7 +102,7 @@ static const ra_af_pin_t miso_pins[] = {
     { AF_SPI, 0, P410 }, /* MISOA_B */
     { AF_SPI, 1, P110 }, /* MISOB_B */
 
-    #elif defined(RA6M2)
+    #elif defined(RA6M2) || defined(RA6M3)
 
     { AF_SPI, 0, P100 }, /* MISOA_A */
     { AF_SPI, 0, P410 }, /* MISOA_B */
@@ -102,6 +110,14 @@ static const ra_af_pin_t miso_pins[] = {
     { AF_SPI, 1, P202 }, /* MISOB_A */
     { AF_SPI, 1, P700 }, /* MISOB_C */
 
+    #elif defined(RA6M5)
+
+    { AF_SPI, 0, P110 }, /* MISOA_B */
+    { AF_SPI, 0, P202 }, /* MISOA_A */
+    { AF_SPI, 0, P700 }, /* MISOA_C */
+    { AF_SPI, 1, P100 }, /* MISOB_A */
+    { AF_SPI, 1, P410 }, /* MISOB_B */
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
@@ -127,7 +143,7 @@ static const ra_af_pin_t sck_pins[] = {
     { AF_SPI, 0, P412 }, /* RSPCKA_B */
     { AF_SPI, 1, P111 }, /* RSPCKB_B */
 
-    #elif defined(RA6M2)
+    #elif defined(RA6M2) || defined(RA6M3)
 
     { AF_SPI, 0, P102 }, /* RSPCKA_A */
     { AF_SPI, 0, P412 }, /* RSPCKA_B */
@@ -135,12 +151,144 @@ static const ra_af_pin_t sck_pins[] = {
     { AF_SPI, 1, P204 }, /* RSPCKB_A */
     { AF_SPI, 1, P702 }, /* RSPCKB_C */
 
+    #elif defined(RA6M5)
+
+    { AF_SPI, 0, P111 }, /* RSPCKA_B */
+    { AF_SPI, 0, P204 }, /* RSPCKA_A */
+    { AF_SPI, 0, P702 }, /* RSPCKA_C */
+    { AF_SPI, 1, P102 }, /* RSPCKB_A */
+    { AF_SPI, 1, P412 }, /* RSPCKB_B */
+
     #else
     #error "CMSIS MCU Series is not specified."
     #endif
 };
 #define SCK_PINS_SIZE sizeof(sck_pins) / sizeof(ra_af_pin_t)
 
+typedef struct ra_ssl_pin {
+    uint8_t ssln;
+    uint32_t pin;
+} ra_ssl_pin_t;
+
+static const ra_ssl_pin_t ssl_pins[] = {
+    #if defined(RA4M1)
+
+    { 0, P103 }, /* SSLA0 */
+    { 1, P104 }, /* SSLA1 */
+    { 2, P105 }, /* SSLA2 */
+    { 3, P106 }, /* SSLA3 */
+    { 0, P108 }, /* SSLB0 */
+    { 0, P112 }, /* SSLB0 */
+
+    { 0, P205 }, /* SSLB0 */
+    { 1, P206 }, /* SSLB1 */
+
+    { 1, P300 }, /* SSLB1 */
+    { 2, P301 }, /* SSLB2 */
+    { 3, P302 }, /* SSLB3 */
+
+    { 3, P407 }, /* SSLB3 */
+    { 0, P413 }, /* SSLA0 */
+    { 1, P414 }, /* SSLA1 */
+    { 2, P415 }, /* SSLA2 */
+
+    #elif defined(RA4W1)
+
+    { 0, P103 }, /* SSLA0 */
+    { 1, P104 }, /* SSLA1 */
+    { 2, P105 }, /* SSLA2 */
+    { 3, P106 }, /* SSLA3 */
+    { 0, P108 }, /* SSLB0 */
+
+    { 0, P205 }, /* SSLB0 */
+    { 1, P206 }, /* SSLB1 */
+
+    { 1, P300 }, /* SSLB1 */
+
+    { 3, P407 }, /* SSLB3 */
+    { 1, P414 }, /* SSLA1 */
+
+    #elif defined(RA6M1)
+
+    { 0, P103 }, /* SSLA0_A */
+    { 1, P104 }, /* SSLA1_A */
+    { 2, P105 }, /* SSLA2_A */
+    { 3, P106 }, /* SSLA3_A */
+    { 0, P108 }, /* SSLB0_B */
+    { 0, P112 }, /* SSLB0_B */
+
+    { 1, P300 }, /* SSLB1_B */
+    { 2, P301 }, /* SSLB2_B */
+    { 3, P302 }, /* SSLB3_B */
+
+    { 0, P413 }, /* SSLA0_B */
+    { 1, P414 }, /* SSLA1_B */
+    { 2, P415 }, /* SSLA2_B */
+
+    { 3, P708 }, /* SSLA3_B */
+
+    #elif defined(RA6M2) || defined(RA6M3)
+
+    { 0, P103 }, /* SSLA0_A */
+    { 1, P104 }, /* SSLA1_A */
+    { 2, P105 }, /* SSLA2_A */
+    { 3, P106 }, /* SSLA3_A */
+    { 0, P108 }, /* SSLB0_B */
+    { 0, P112 }, /* SSLB0_B */
+
+    { 0, P205 }, /* SSLB0_A */
+    { 1, P206 }, /* SSLB1_A */
+    { 2, P207 }, /* SSLB2_A */
+
+    { 1, P300 }, /* SSLB1_B */
+    { 2, P301 }, /* SSLB2_B */
+    { 3, P302 }, /* SSLB3_B */
+
+    { 3, P406 }, /* SSLB3_C */
+    { 3, P407 }, /* SSLB3_A */
+    { 0, P413 }, /* SSLA0_B */
+    { 1, P414 }, /* SSLA1_B */
+    { 2, P415 }, /* SSLA2_B */
+
+    { 0, P703 }, /* SSLB0_C */
+    { 1, P704 }, /* SSLB1_C */
+    { 2, P705 }, /* SSLB2_C */
+    { 3, P708 }, /* SSLA3_B */
+
+    #elif defined(RA6M5)
+
+    { 0, P103 }, /* SSLB0_A */
+    { 1, P104 }, /* SSLB1_A */
+    { 2, P105 }, /* SSLB2_A */
+    { 3, P106 }, /* SSLB3_A */
+    { 0, P108 }, /* SSLA0_B */
+    { 0, P112 }, /* SSLA0_B */
+
+    { 0, P205 }, /* SSLA0_A */
+    { 1, P206 }, /* SSLA1_A */
+    { 2, P207 }, /* SSLA2_A */
+
+    { 1, P300 }, /* SSLA1_B */
+    { 2, P301 }, /* SSLA2_B */
+    { 3, P302 }, /* SSLA3_B */
+
+    { 3, P406 }, /* SSLA3_C */
+    { 3, P407 }, /* SSLA3_A */
+    { 0, P413 }, /* SSLB0_B */
+    { 1, P414 }, /* SSLB1_B */
+    { 2, P415 }, /* SSLB2_B */
+
+    { 0, P703 }, /* SSLA0_C */
+    { 1, P704 }, /* SSLA1_C */
+    { 2, P705 }, /* SSLA2_C */
+    { 3, P708 }, /* SSLB3_B */
+
+    #else
+    #error "CMSIS MCU Series is not specified."
+    #endif
+};
+#define SSL_PINS_SIZE sizeof(ssl_pins) / sizeof(ra_ssl_pin_t)
+
 bool ra_af_find_ch(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint8_t *ch) {
     bool find = false;
     uint32_t i;
@@ -178,6 +326,25 @@ bool ra_spi_find_af_ch(uint32_t mosi, uint32_t miso, uint32_t sck, uint8_t *ch)
     return find;
 }
 
+static bool ra_spi_pin_to_ssln(uint32_t pin, uint8_t *ssln) {
+    ra_ssl_pin_t *ssl_pin = (ra_ssl_pin_t *)&ssl_pins;
+    bool find = false;
+    uint32_t i;
+    for (i = 0; i < SSL_PINS_SIZE; i++) {
+        if (ssl_pin->pin == pin) {
+            find = true;
+            if (find) {
+                *ssln = ssl_pin->ssln;
+            } else {
+                *ssln = 0;
+            }
+            break;
+        }
+        ssl_pin++;
+    }
+    return find;
+}
+
 static void ra_spi_module_start(uint32_t ch) {
     if (ch == 0) {
         ra_mstpcrb_start(R_MSTP_MSTPCRB_MSTPB19_Msk);
@@ -202,7 +369,7 @@ static void ra_spi_set_pin(uint32_t pin, bool miso) {
     }
 }
 
-void ra_spi_set_bits(uint32_t ch, uint32_t bits) {
+static void ra_spi_set_bits(uint32_t ch, uint32_t bits) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
     if (bits == 8) {
         spi_reg->SPDCR_b.SPBYT = 1;
@@ -219,17 +386,7 @@ void ra_spi_set_bits(uint32_t ch, uint32_t bits) {
     }
 }
 
-void ra_spi_set_clk(uint32_t ch, uint32_t baud) {
-    R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    if (baud == 0) {
-        return;
-    }
-    spi_reg->SPCR_b.SPE = 0;
-    spi_reg->SPBR = (PCLK / 2 / baud) - 1;
-    spi_reg->SPCR_b.SPE = 1;
-}
-
-void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first) {
+static void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
     if (lsb_first) {
         spi_reg->SPCMD_b[0].LSBF = 1;  // LSB first
@@ -238,7 +395,7 @@ void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first) {
     }
 }
 
-void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase) {
+static void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
     if (polarity != 0) {
         // CPOL(Clock Polarity)
@@ -254,18 +411,6 @@ void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase) {
     }
 }
 
-void ra_spi_set_ch(uint32_t ch) {
-    R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    spi_reg->SPCR = 0x00;        // disable SPI
-    spi_reg->SPSR = 0xa0;
-    spi_reg->SPPCR = 0x00;       // fixed idle value, disable loop-back mode
-    spi_reg->SPSCR = 0x00;       // Disable sequence control
-    spi_reg->SPDCR = 0x40;       // SPBYT=1, SPLW=0 byte access
-    spi_reg->SPCMD[0] = 0xe700;  // LSBF=0, SPB=7, BRDV=0, CPOL=0, CPHA=0
-    spi_reg->SPCR2 = 0x10;
-    spi_reg->SPCR = 0x48;        // Start SPI in master mode
-}
-
 uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
     while (spi_reg->SPSR_b.SPTEF == 0) {
@@ -280,7 +425,6 @@ uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b) {
 
 void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    ra_spi_set_bits(ch, 8);
     while (count-- > 0) {
         while (spi_reg->SPSR_b.SPTEF == 0) {
             ;
@@ -295,7 +439,6 @@ void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
 
 void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    ra_spi_set_bits(ch, 8);
     while (count-- > 0) {
         while (spi_reg->SPSR_b.SPTEF == 0) {
             ;
@@ -310,7 +453,6 @@ void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) {
 
 void ra_spi_write_bytes16(uint32_t ch, uint16_t *buf, uint32_t count) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    ra_spi_set_bits(ch, 16);
     while (count-- > 0) {
         while (spi_reg->SPSR_b.SPTEF == 0) {
             ;
@@ -325,7 +467,6 @@ void ra_spi_write_bytes16(uint32_t ch, uint16_t *buf, uint32_t count) {
 
 void ra_spi_write_bytes32(uint32_t ch, uint32_t *buf, uint32_t count) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    ra_spi_set_bits(ch, 32);
     while (count-- > 0) {
         while (spi_reg->SPSR_b.SPTEF == 0) {
             ;
@@ -350,7 +491,6 @@ void ra_spi_write_bytes(uint32_t ch, uint32_t bits, uint8_t *buf, uint32_t count
 
 void ra_spi_transfer8(uint32_t ch, uint8_t *dst, uint8_t *src, uint32_t count) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    ra_spi_set_bits(ch, 8);
     while (count-- > 0) {
         while (spi_reg->SPSR_b.SPTEF == 0) {
             ;
@@ -359,13 +499,16 @@ void ra_spi_transfer8(uint32_t ch, uint8_t *dst, uint8_t *src, uint32_t count) {
         while (spi_reg->SPSR_b.SPRF == 0) {
             ;
         }
-        *dst++ = (uint8_t)(spi_reg->SPDR_BY);
+        if (dst) {
+            *dst++ = (uint8_t)(spi_reg->SPDR_BY);
+        } else {
+            spi_reg->SPDR_BY;
+        }
     }
 }
 
 void ra_spi_transfer16(uint32_t ch, uint16_t *dst, uint16_t *src, uint32_t count) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    ra_spi_set_bits(ch, 16);
     while (count-- > 0) {
         while (spi_reg->SPSR_b.SPTEF == 0) {
             ;
@@ -374,13 +517,16 @@ void ra_spi_transfer16(uint32_t ch, uint16_t *dst, uint16_t *src, uint32_t count
         while (spi_reg->SPSR_b.SPRF == 0) {
             ;
         }
-        *dst++ = (uint16_t)(spi_reg->SPDR_HA);
+        if (dst) {
+            *dst++ = (uint16_t)(spi_reg->SPDR_HA);
+        } else {
+            spi_reg->SPDR_HA;
+        }
     }
 }
 
 void ra_spi_transfer32(uint32_t ch, uint32_t *dst, uint32_t *src, uint32_t count) {
     R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
-    ra_spi_set_bits(ch, 32);
     while (count-- > 0) {
         while (spi_reg->SPSR_b.SPTEF == 0) {
             ;
@@ -389,7 +535,11 @@ void ra_spi_transfer32(uint32_t ch, uint32_t *dst, uint32_t *src, uint32_t count
         while (spi_reg->SPSR_b.SPRF == 0) {
             ;
         }
-        *dst++ = (uint32_t)(spi_reg->SPDR);
+        if (dst) {
+            *dst++ = (uint32_t)(spi_reg->SPDR);
+        } else {
+            spi_reg->SPDR;
+        }
     }
 }
 
@@ -421,18 +571,53 @@ void ra_spi_get_conf(uint32_t ch, uint16_t *spcmd, uint8_t *spbr) {
     *spbr = spi_reg->SPBR;
 }
 
-void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase) {
-    ra_gpio_mode_output(cs);
-    ra_gpio_write(cs, 1);
+void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase, uint32_t firstbit) {
+    R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch];
+    uint8_t ssln = 0;
+    uint8_t sslp = 0;
+
+    ra_spi_pin_to_ssln(cs, &ssln);
+    sslp &= ~0x0fU;
+    sslp |= (uint8_t)polarity << ssln;
+
     ra_spi_module_start(ch);
+
+    spi_reg->SPSR;              // dummy read to clear OVRF
+    spi_reg->SPSR = 0xa0;       // clear all status
+
+    spi_reg->SPCR = 0x00;       // disable SPI
+    spi_reg->SSLP = sslp;       // select slave active polarity
+    spi_reg->SPPCR = 0x00;      // fixed idle value, disable loop-back mode
+    spi_reg->SPBR = (PCLK / 2 / baud) - 1;      // Set baudrate
+    spi_reg->SPDCR = 0x40;      // SPBYT=1, SPLW=0 byte access
+    spi_reg->SPCKD = 0x00;      // 1RSPCK
+    spi_reg->SPDCR = 0x00;      // 1RSPCK
+    spi_reg->SPND = 0x00;       // 1RSPCK + 2PCLKA
+    spi_reg->SPCR2 = 0x10;      // SCKASE=1
+    spi_reg->SPSCR = 0x00;      // Disable sequence control
+    spi_reg->SPCMD[0] = (0xe700 | (ssln << 4));  // LSBF=0, SPB=7, SSLA:ssln, BRDV=0, CPOL=0, CPHA=0
+    spi_reg->SPDCR2 = 0x00;     // BYSW=0, SINV=0(RA6M5)
+
+    /* set other setting */
+    ra_spi_set_mode(ch, polarity, phase);
+    ra_spi_set_bits(ch, bits);
+    ra_spi_set_lsb_first(ch, firstbit);
+
+    /* NIVC, DMAC setting */
+
+    /* I/O port setting */
     ra_spi_set_pin(mosi, false);
     ra_spi_set_pin(miso, true);
     ra_spi_set_pin(sck, false);
-    ra_spi_set_mode(ch, polarity, phase);
-    ra_spi_set_ch(ch);
-    ra_spi_set_clk(ch, baud);
-    ra_spi_set_bits(ch, bits);
-    ra_spi_set_lsb_first(ch, 0);  // MSB first
+    ra_spi_set_pin(cs, false);
+
+    #if defined(RA6M5)
+    spi_reg->SPCR3 = 0x00;      // default
+    #endif
+
+    spi_reg->SPCR = 0x48;       // Start SPI in master mode
+    spi_reg->SPCR;              // wait for completion
+
     return;
 }
 
diff --git a/ports/renesas-ra/ra/ra_spi.h b/ports/renesas-ra/ra/ra_spi.h
index e75acf8701..c33120a863 100644
--- a/ports/renesas-ra/ra/ra_spi.h
+++ b/ports/renesas-ra/ra/ra_spi.h
@@ -34,16 +34,6 @@
 bool ra_af_find_ch(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint8_t *ch);
 bool ra_spi_find_af_ch(uint32_t mosi, uint32_t miso, uint32_t sck, uint8_t *ch);
 
-// static void ra_spi_module_start(uint32_t ch);
-// static void ra_spi_module_stop(uint32_t ch);
-// static void ra_spi_set_pin(uint8_t pin);
-
-void ra_spi_set_bits(uint32_t ch, uint32_t bits);
-void ra_spi_set_clk(uint32_t ch, uint32_t baud);
-void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first);
-void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase);
-void ra_spi_set_ch(uint32_t ch);
-
 uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b);
 void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count);
 void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count);
@@ -57,7 +47,7 @@ void ra_spi_transfer(uint32_t ch, uint32_t bits, uint8_t *dst, uint8_t *src, uin
 void ra_spi_start_xfer(uint32_t ch, uint16_t spcmd, uint8_t spbr);
 void ra_spi_end_xfer(uint32_t ch);
 void ra_spi_get_conf(uint32_t ch, uint16_t *spcmd, uint8_t *spbr);
-void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase);
+void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase, uint32_t firstbit);
 void ra_spi_deinit(uint32_t ch, uint32_t cs);
 
 #endif /* RA_RA_SPI_H_ */
diff --git a/ports/renesas-ra/ra/ra_timer.c b/ports/renesas-ra/ra/ra_timer.c
index 9c2a3c010e..fc01862706 100644
--- a/ports/renesas-ra/ra/ra_timer.c
+++ b/ports/renesas-ra/ra/ra_timer.c
@@ -43,8 +43,8 @@ enum AGT_SOURCE {
 };
 
 static R_AGTX0_AGT16_Type *agt_regs[AGT_CH_SIZE] = {
-    (R_AGTX0_AGT16_Type *)0x40084000,
-    (R_AGTX0_AGT16_Type *)0x40084100
+    (R_AGTX0_AGT16_Type *)R_AGTX0,
+    (R_AGTX0_AGT16_Type *)R_AGTX1
 };
 
 static uint8_t ch_to_irq[AGT_CH_SIZE] = {
diff --git a/ports/renesas-ra/ra/ra_utils.c b/ports/renesas-ra/ra/ra_utils.c
index ae91427eec..db59c1bb6f 100644
--- a/ports/renesas-ra/ra/ra_utils.c
+++ b/ports/renesas-ra/ra/ra_utils.c
@@ -27,7 +27,7 @@
 #include "ra_utils.h"
 
 static R_SYSTEM_Type *system_reg = (R_SYSTEM_Type *)0x4001E000;
-static R_MSTP_Type *mstp_reg = (R_MSTP_Type *)R_MSTP;
+static R_MSTP_Type *mstp_reg = R_MSTP;
 
 void ra_mstpcra_stop(uint32_t mod_mask) {
     system_reg->PRCR = 0xa502;
@@ -77,6 +77,18 @@ void ra_mstpcrd_start(uint32_t mod_mask) {
     system_reg->PRCR = 0xa500;
 }
 
+void ra_mstpcre_stop(uint32_t mod_mask) {
+    system_reg->PRCR = 0xa502;
+    mstp_reg->MSTPCRE |= mod_mask;
+    system_reg->PRCR = 0xa500;
+}
+
+void ra_mstpcre_start(uint32_t mod_mask) {
+    system_reg->PRCR = 0xa502;
+    mstp_reg->MSTPCRE &= ~mod_mask;
+    system_reg->PRCR = 0xa500;
+}
+
 __WEAK void ctsu_write_isr(void) {
     // dummy
 }
diff --git a/ports/renesas-ra/ra/ra_utils.h b/ports/renesas-ra/ra/ra_utils.h
index 3ff0f3a371..3f954dee72 100644
--- a/ports/renesas-ra/ra/ra_utils.h
+++ b/ports/renesas-ra/ra/ra_utils.h
@@ -52,6 +52,8 @@ void ra_mstpcrc_stop(uint32_t mod_mask);
 void ra_mstpcrc_start(uint32_t mod_mask);
 void ra_mstpcrd_stop(uint32_t mod_mask);
 void ra_mstpcrd_start(uint32_t mod_mask);
+void ra_mstpcre_stop(uint32_t mod_mask);
+void ra_mstpcre_start(uint32_t mod_mask);
 
 /* mask bit definition for Module Stop Control Register B */
 #ifndef R_MSTP_MSTPCRB_MSTPB7_Msk
diff --git a/ports/renesas-ra/spi.h b/ports/renesas-ra/spi.h
index 47d9c13567..04be9f9b64 100644
--- a/ports/renesas-ra/spi.h
+++ b/ports/renesas-ra/spi.h
@@ -34,11 +34,8 @@
 #define SPI_TRANSFER_TIMEOUT(len) ((len) + 100)
 
 void spi_init0(void);
-void spi_init(uint32_t ch);
 void spi_deinit(uint32_t ch);
 int spi_find_index(mp_obj_t id);
-void spi_set_params(uint32_t ch, int32_t baudrate,
-    int32_t polarity, int32_t phase, int32_t bits, int32_t firstbit);
 void spi_transfer(uint32_t ch, uint32_t bits, size_t len, const uint8_t *src, uint8_t *dest, uint32_t timeout);
 
 #endif // MICROPY_INCLUDED_RA_SPI_H