stm32: Add support for F412 MCUs.

ports/stm32/adc.c

@@ -132,10 +132,10 @@
     defined(STM32F407xx) || defined(STM32F417xx) || \
     defined(STM32F401xC) || defined(STM32F401xE)
 #define VBAT_DIV (2)
-#elif defined(STM32F411xE) || defined(STM32F413xx) || \
-    defined(STM32F427xx) || defined(STM32F429xx) || \
-    defined(STM32F437xx) || defined(STM32F439xx) || \
-    defined(STM32F446xx)
+#elif defined(STM32F411xE) || defined(STM32F412Zx) || \
+    defined(STM32F413xx) || defined(STM32F427xx) || \
+    defined(STM32F429xx) || defined(STM32F437xx) || \
+    defined(STM32F439xx) || defined(STM32F446xx)
 #define VBAT_DIV (4)
 #elif defined(STM32F722xx) || defined(STM32F723xx) || \
     defined(STM32F732xx) || defined(STM32F733xx) || \

ports/stm32/boards/stm32f412_af.csv

@@ -0,0 +1,116 @@
+Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,
+,,SYS_AF,TIM1/TIM2,TIM3/TIM4/TIM5,TIM8/9/10/11,I2C1/2/3/I2CFMP1,SPI1/2/3/4/I2S1/2/3/4,SPI2/3/4/5/I2S2/3/4/5/DFSDM1/2,SPI3/I2S3/USART1/2/3,USART3/6/CAN1/DFSDM1,I2C2/I2C3/I2CFMP1/CAN1/2/TIM12/13/14/QUADSPI,DFSDM1/QUADSPI/FSMC/OTG1_FS,,FSMC /SDIO,,,SYS_AF,ADC
+PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,,,,,,,,EVENTOUT,ADC1_IN0
+PortA,PA1,,TIM2_CH2,TIM5_CH2,,,SPI4_MOSI/I2S4_SD,,USART2_RTS,,QUADSPI_BK1_IO3,,,,,,EVENTOUT,ADC1_IN1
+PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,I2S2_CKIN,,USART2_TX,,,,,FSMC_D4,,,EVENTOUT,ADC1_IN2
+PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,I2S2_MCK,,USART2_RX,,,,,FSMC_D5,,,EVENTOUT,ADC1_IN3
+PortA,PA4,,,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,DFSDM1_DATIN1,,,,FSMC_D6,,,EVENTOUT,ADC1_IN4
+PortA,PA5,,TIM2_CH1/TIM2_ETR,,TIM8_CH1N,,SPI1_SCK/I2S1_CK,,,DFSDM1_CKIN1,,,,FSMC_D7,,,EVENTOUT,ADC1_IN5
+PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,I2S2_MCK,,,TIM13_CH1,QUADSPI_BK2_IO0,,SDIO_CMD,,,EVENTOUT,ADC1_IN6
+PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,QUADSPI_BK2_IO1,,,,,EVENTOUT,ADC1_IN7
+PortA,PA8,MCO_1,TIM1_CH1,,,I2C3_SCL,,DFSDM1_CKOUT,USART1_CK,,,USB_FS_SOF,,SDIO_D1,,,EVENTOUT,
+PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,USB_FS_VBUS,,SDIO_D2,,,EVENTOUT,
+PortA,PA10,,TIM1_CH3,,,,SPI2_MOSI/I2S2_SD,SPI5_MOSI/I2S5_SD,USART1_RX,,,USB_FS_ID,,,,,EVENTOUT,
+PortA,PA11,,TIM1_CH4,,,,SPI2_NSS/I2S2_WS,SPI4_MISO,USART1_CTS,USART6_TX,CAN1_RX,USB_FS_DM,,,,,EVENTOUT,
+PortA,PA12,,TIM1_ETR,,,,SPI2_MISO,SPI5_MISO,USART1_RTS,USART6_RX,CAN1_TX,USB_FS_DP,,,,,EVENTOUT,
+PortA,PA13,JTMS/SWDIO,,,,,,,,,,,,,,,EVENTOUT,
+PortA,PA14,JTCK/SWCLK,,,,,,,,,,,,,,,EVENTOUT,
+PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART1_TX,,,,,,,,EVENTOUT,
+PortB,PB0,,TIM1_CH2N,TIM3_CH3,TIM8_CH2N,,,SPI5_SCK/I2S5_CK,,,,,,,,,EVENTOUT,ADC1_IN8
+PortB,PB1,,TIM1_CH3N,TIM3_CH4,TIM8_CH3N,,,SPI5_NSS/I2S5_WS,,DFSDM1_DATIN0,QUADSPI_CLK,,,,,,EVENTOUT,ADC1_IN9
+PortB,PB2,,,,,,,DFSDM1_CKIN0,,,QUADSPI_CLK,,,,,,EVENTOUT,
+PortB,PB3,JTDO,TIM2_CH2,,,I2CFMP1_SDA,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,USART1_RX,UART7_RX,I2C2_SDA,,,,,,EVENTOUT,
+PortB,PB4,JTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,I2S3ext_SD,UART7_TX,I2C3_SDA,,,SDIO_D0,,,EVENTOUT,
+PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,,,SDIO_D3,,,EVENTOUT,
+PortB,PB6,,,TIM4_CH1,,I2C1_SCL,,DFSDM2_CKIN7,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,,SDIO_D0,,,EVENTOUT,
+PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,DFSDM2_DATIN7,USART1_RX,,,,,FSMC_NL,,,EVENTOUT,
+PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,SPI5_MOSI/I2S5_SD,,CAN1_RX,I2C3_SDA,,,SDIO_D4,,,EVENTOUT,
+PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,DFSDM2_DATIN1,,CAN1_TX,I2C2_SDA,,,SDIO_D5,,,EVENTOUT,
+PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,I2S3_MCK,USART3_TX,,I2CFMP4_SCL,,,SDIO_D7,,,EVENTOUT,
+PortB,PB11,,TIM2_CH4,,,I2C2_SDA,I2S2_CKIN,,USART3_RX,,,,,,,,EVENTOUT,
+PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,SPI4_NSS/I2S4_WS,SPI3_SCK/I2S3_CK,USART3__CK,CAN2_RX,DFSDM1_DATIN1,,FSMC_D13/FSMC_DA13,,,EVENTOUT,
+PortB,PB13,,TIM1_CH1N,,,I2CFMP1_SMBA,SPI2_SCK/I2S2_CK,SPI4_SCK/I2S4_CK,,USART3_CTS,CAN2_TX,DFSDM1_CKIN1,,,,,EVENTOUT,
+PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,I2CFMP1_SDA,SPI2_MISO,I2S2ext_SD,USART3_RTS,DFSDM1_DATIN2,TIM12_CH1,FSMC_D0,,SDIO_D6,,,EVENTOUT,
+PortB,PB15,RTC_50HZ,TIM1_CH3N,,TIM8_CH3N,I2CFMP1_SCL,SPI2_MOSI/I2S2_SD,,,DFSDM1_CKIN2,TIM12_CH2,,,SDIO_CK,,,EVENTOUT,
+PortC,PC0,,,,,,,,SAI1_MCLK_B,,,,,,,,EVENTOUT,ADC1_IN10
+PortC,PC1,,,,,,,,SAI1_SD_B,,,,,,,,EVENTOUT,ADC1_IN11
+PortC,PC2,,,,,,SPI2_MISO,I2S2ext_SD,SAI1_SCK_B,DFSDM1_CKOUT,,,,FSMC_NWE,,,EVENTOUT,ADC1_IN12
+PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,SAI1_FS_B,,,,,FSMC_A0,,,EVENTOUT,ADC1_IN13
+PortC,PC4,,,,,,I2S1_MCK,,,,,QUADSPI_BK2_IO2,,FSMC_NE4,,,EVENTOUT,ADC1_IN14
+PortC,PC5,,,,,I2CFMP1_SMBA,,,USART3_RX,,,QUADSPI_BK2_IO3,,FSMC_NOE,,,EVENTOUT,ADC1_IN15
+PortC,PC6,,,TIM3_CH1,TIM8_CH1,2CFMP1_SCL,I2S2_MCK,DFSDM1_CKIN3,,USART6_TX,,FSMC_D1,,SDIO_D6,,,EVENTOUT,
+PortC,PC7,,,TIM3_CH2,TIM8_CH2,I2CFMP1_SDA,SPI2_SCK/I2S2_CK,I2S3_MCK,,USART6_RX,,DFSDM1_DATIN3,,SDIO_D7,,,EVENTOUT,
+PortC,PC8,,,TIM3_CH3,TIM8_CH3,,,,,USART6_CK,QUADSPI_BK1_IO2,,,SDIO_D0,,,EVENTOUT,
+PortC,PC9,MCO_2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S2_CKIN,,,,QUADSPI_BK1_IO0,,,SDIO_D1,,,EVENTOUT,
+PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,,QUADSPI_BK1_IO1,,,SDIO_D2,,,EVENTOUT,
+PortC,PC11,,,,,,I2S3ext_SD,SPI3_MISO,USART3_RX,,QUADSPI_BK2_NCS,FSMC_D2,,SDIO_D3,,,EVENTOUT,
+PortC,PC12,,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,,,FSMC_D3,,SDIO_CK,,,EVENTOUT,
+PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT,
+PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT,
+PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT,
+PortD,PD0,,,,,,,,,,CAN1_RX,,,FSMC_D2/FSMC_DA2,,,EVENTOUT,
+PortD,PD1,,,,,,,,,,CAN1_TX,,,FSMC_D3/FSMC_DA3,,,EVENTOUT,
+PortD,PD2,,,TIM3_ETR,,,,,,,,FSMC_NWE,,SDIO_CMD,,,EVENTOUT,
+PortD,PD3,TRACED1,,,,,SPI2_SCK/I2S2_CK,DFSDM1_DATIN0,USART2_CTS,,QUADSPI_CLK,,,FSMC_CLK,,,EVENTOUT,
+PortD,PD4,,,,,,,DFSDM1_CKIN0,USART2_RTS,,,,,FSMC_NOE,,,EVENTOUT,
+PortD,PD5,,,,,,,,USART2_TX,,,,,FSMC_NWE,,,EVENTOUT,
+PortD,PD6,,,,,,SPI3_MOSI/I2S3_SD,DFSDM1_DATIN1,USART2_RX,,,,,FSMC_NWAIT,,,EVENTOUT,
+PortD,PD7,,,,,,,DFSDM1_CKIN1,USART2_CK,,,,,FSMC_NE1,,,EVENTOUT,
+PortD,PD8,,,,,,,,USART3_TX,,,,,FSMC_D13/FSMC_DA13,,,EVENTOUT,
+PortD,PD9,,,,,,,,USART3_RX,,,,,FSMC_D14/FSMC_DA14,,,EVENTOUT,
+PortD,PD10,,,,,,,,USART3_CK,,,,,FSMC_D15/FSMC_DA15,,,EVENTOUT,
+PortD,PD11,,,,,I2CFMP1_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,,,FSMC_A16,,,EVENTOUT,
+PortD,PD12,,,TIM4_CH1,,I2CFMP1_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,,,FSMC_A17,,,EVENTOUT,
+PortD,PD13,,,TIM4_CH2,,I2CFMP1_SDA,,,,,QUADSPI_BK1_IO3,,,FSMC_A18,,,EVENTOUT,
+PortD,PD14,,,TIM4_CH3,,I2CFMP1_SCL,,,,,,,,FSMC_D0/FSMC_DA0,,,EVENTOUT,
+PortD,PD15,,,TIM4_CH4,,I2CFMP1_SDA,,,,,,,,FSMC_D1/FSMC_DA1,,,EVENTOUT,
+PortE,PE0,,,TIM4_ETR,,,,,,,,,,FSMC_NBL0,,,EVENTOUT,
+PortE,PE1,,,,,,,,,,,,,FSMC_NBL1,,,EVENTOUT,
+PortE,PE2,TRACECLK,,,,,SPI4_SCK/I2S4_CK,SPI5_SCK/I2S5_CK,SAI1_MCLK_A,,QUADSPI_BK1_IO2,,,FSMC_A23,,,EVENTOUT,
+PortE,PE3,TRACED0,,,,,,,SAI1_SD_B,,,,,FSMC_A19,,,EVENTOUT,
+PortE,PE4,TRACED1,,,,,SPI4_NSS/I2S4_WS,SPI5_NSS/I2S5_WS,SAI1_SD_A,DFSDM1_DATIN3,,,,FSMC_A20,,,EVENTOUT,
+PortE,PE5,TRACED2,,,TIM9_CH1,,SPI4_MISO,SPI5_MISO,SAI1_SCK_A,DFSDM1_CKIN3,,,,FSMC_A21,,,EVENTOUT,
+PortE,PE6,TRACED3,,,TIM9_CH2,,SPI4_MOSI/I2S4_SD,SPI5_MOSI/I2S5_SD,SAI1_FS_A,,,,,FSMC_A22,,,EVENTOUT,
+PortE,PE7,,TIM1_ETR,,,,,DFSDM1_DATIN2,,,,QUADSPI_BK2_IO0,,FSMC_D4/FSMC_DA4,,,EVENTOUT,
+PortE,PE8,,TIM1_CH1N,,,,,DFSDM1_CKIN2,,,,QUADSPI_BK2_IO1,,FSMC_D5/FSMC_DA5,,,EVENTOUT,
+PortE,PE9,,TIM1_CH1,,,,,DFSDM1_CKOUT,,,,QUADSPI_BK2_IO2,,FSMC_D6/FSMC_DA6,,,EVENTOUT,
+PortE,PE10,,TIM1_CH2N,,,,,,,,,QUADSPI_BK2_IO3,,FSMC_D7/FSMC_DA7,,,EVENTOUT,
+PortE,PE11,,TIM1_CH2,,,,SPI4_NSS/I2S4_WS,SPI5_NSS/I2S5_WS,,,,,,FSMC_D8/FSMC_DA8,,,EVENTOUT,
+PortE,PE12,,TIM1_CH3N,,,,SPI4_SCK/I2S4_CK,SPI5_SCK/I2S5_CK,,,,,,FSMC_D9/FSMC_DA9,,,EVENTOUT,
+PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,SPI5_MISO,,,,,,FSMC_D10/FSMC_DA10,,,EVENTOUT,
+PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI/I2S4_SD,SPI5_MOSI/I2S5_SD,,,,,,FSMC_D11/FSMC_DA11,,,EVENTOUT,
+PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FSMC_D12/FSMC_DA12,,,EVENTOUT,
+PortF,PF0,,,,,I2C2_SDA,,,,,,,,FSMC_A0,,,EVENTOUT,
+PortF,PF1,,,,,I2C2_SCL,,,,,,,,FSMC_A1,,,EVENTOUT,
+PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FSMC_A2,,,EVENTOUT,
+PortF,PF3,,,TIM5_CH1,,,,,,,,,,FSMC_A3,,,EVENTOUT,
+PortF,PF4,,,TIM5_CH2,,,,,,,,,,FSMC_A4,,,EVENTOUT,
+PortF,PF5,,,TIM5_CH3,,,,,,,,,,FSMC_A5,,,EVENTOUT,
+PortF,PF6,TRACED0,,,TIM10_CH1,,,,SAI1_SD_B,,QUADSPI_BK1_IO3,,,,,,EVENTOUT,
+PortF,PF7,TRACED1,,,TIM11_CH1,,,,SAI1_MCLK_B,,QUADSPI_BK1_IO2,,,,,,EVENTOUT,
+PortF,PF8,,,,,,,,SAI1_SCK_B,,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT,
+PortF,PF9,,,,,,,,SAI1_FS_B,,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT,
+PortF,PF10,,TIM1_ETR,TIM5_CH4,,,,,,,,,,,,,EVENTOUT,
+PortF,PF11,,,,TIM8_ETR,,,,,,,,,,,,EVENTOUT,
+PortF,PF12,,,,TIM8_BKIN,,,,,,,,,FSMC_A6,,,EVENTOUT,
+PortF,PF13,,,,,I2CFMP1_SMBA,,,,,,,,FSMC_A7,,,EVENTOUT,
+PortF,PF14,,,,,I2CFMP1_SCL,,,,,,,,FSMC_A8,,,EVENTOUT,
+PortF,PF15,,,,,I2CFMP1_SDA,,,,,,,,FSMC_A9,,,EVENTOUT,
+PortG,PG0,,,,,,,,,,CAN1_RX,,,FSMC_A10,,,EVENTOUT,
+PortG,PG1,,,,,,,,,,CAN1_TX,,,FSMC_A11,,,EVENTOUT,
+PortG,PG2,,,,,,,,,,,,,FSMC_A12,,,EVENTOUT,
+PortG,PG3,,,,,,,,,,,,,FSMC_A13,,,EVENTOUT,
+PortG,PG4,,,,,,,,,,,,,FSMC_A14,,,EVENTOUT,
+PortG,PG5,,,,,,,,,,,,,FSMC_A15,,,EVENTOUT,
+PortG,PG6,,,,,,,,,,,QUADSPI_BK1_NCS,,,,,EVENTOUT,
+PortG,PG7,,,,,,,,,USART6_CK,,,,,,,EVENTOUT,
+PortG,PG8,,,,,,,,,USART6_RTS,,,,,,,EVENTOUT,
+PortG,PG9,,,,,,,,,USART6_RX,QUADSPI_BK2_IO2,,,FSMC_NE2,,,EVENTOUT,
+PortG,PG10,,,,,,,,,,,,,FSMC_NE3,,,EVENTOUT,
+PortG,PG11,,,,,,,,,,CAN2_RX,,,,,,EVENTOUT,
+PortG,PG12,,,,,,,,,USART6_RTS,CAN2_TX,,,FSMC_NE4,,,EVENTOUT,
+PortG,PG13,TRACED2,,,,,,,,USART6_CTS,,,,FSMC_A24,,,EVENTOUT,
+PortG,PG14,TRACED3,,,,,,,,USART6_TX,QUADSPI_BK2_IO3,,,FSMC_A25,,,EVENTOUT,
+PortG,PG15,,,,,,,,,USART6_CTS,,,,,,,EVENTOUT,
+PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT,
+PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT,

ports/stm32/boards/stm32f412zx.ld

@@ -0,0 +1,28 @@
+/*
+    GNU linker script for STM32F412zx (1MB flash, 256kB RAM)
+*/
+
+/* Specify the memory areas */
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 1024K /* entire flash */
+    FLASH_ISR (rx)  : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0 */
+    FLASH_FS (rx)   : ORIGIN = 0x08004000, LENGTH = 112K /* sectors 1,2,3 are 16K, 4 is 64K */
+    FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K /* sectors 5,6,7,8,9,10,11 are 128K */
+    RAM (xrw)       : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* produce a link error if there is not this amount of RAM for these sections */
+_minimum_stack_size = 2K;
+_minimum_heap_size = 16K;
+
+/* Define the stack.  The stack is full descending so begins just above last byte
+   of RAM.  Note that EABI requires the stack to be 8-byte aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
+_sstack = _estack - 16K; /* tunable */
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_start = _ebss; /* heap starts just after statically allocated memory */
+_heap_end = _sstack;

ports/stm32/flashbdev.c

@@ -53,7 +53,7 @@
 #define FLASH_MEM_SEG2_NUM_BLOCKS (128) // sector 11: 128k
 #endif
 
-#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F446xx)
 
 STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
 #define CACHE_MEM_START_ADDR (&flash_cache_mem[0])

ports/stm32/modmachine.c

@@ -124,7 +124,7 @@ void machine_init(void) {
         if (state & RCC_SR_IWDGRSTF || state & RCC_SR_WWDGRSTF) {
             reset_cause = PYB_RESET_WDT;
         } else if (state & RCC_SR_PORRSTF
-                   #if !defined(STM32F0)
+                   #if !defined(STM32F0) && !defined(STM32F412Zx)
                    || state & RCC_SR_BORRSTF
                    #endif
                    ) {

ports/stm32/timer.c

@@ -820,8 +820,12 @@ STATIC const uint32_t tim_instance_table[MICROPY_HW_MAX_TIMER] = {
     TIM_ENTRY(5, TIM5_IRQn),
     #endif
     #if defined(TIM6)
+    #if defined(STM32F412Zx)
+    TIM_ENTRY(6, TIM6_IRQn),
+    #else
     TIM_ENTRY(6, TIM6_DAC_IRQn),
     #endif
+    #endif
     #if defined(TIM7)
     TIM_ENTRY(7, TIM7_IRQn),
     #endif