kopia lustrzana https://github.com/micropython/micropython
stm32/network_lan: Add the phy_type=x keyword option to network.LAN().
With LAN8742, LAN8720, LAN83825 and DP83848 as possible options, and the symbols PHY_LAN8720, PHY_LAN8742, PHY_DP83825 and PHY_DP8348. The default is PHY_LAN8742 which is the existing behaviour. The eth_init() parameters for the Portenta H7 board are set to phy_addr=0 and phy_type=LAN8742, which matches the previous defaults and the schematics. Tested with LAN8720 and DP83848 breakout boards at 10M Duplex and 100M Duplex modes. Signed-off-by: robert-hh <robert@hammelrath.com>pull/13630/head
robert-hh
Damien George
rodzic
085e3244f0
commit
bf68bb95f9
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@ -251,6 +251,7 @@ SRC_C += \
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pyb_can.c \
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usb.c \
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eth.c \
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eth_phy.c \
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gccollect.c \
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help.c \
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machine_bitstream.c \
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@ -115,7 +115,7 @@ void PORTENTA_board_early_init(void) {
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mp_hal_pin_write(pyb_pin_ETH_RST, 1);
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// Put Eth in low-power mode
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eth_init(ð_instance, MP_HAL_MAC_ETH0, 0);
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eth_init(ð_instance, MP_HAL_MAC_ETH0, 0, ETH_PHY_LAN8742);
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eth_low_power_mode(ð_instance, true);
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#if MICROPY_HW_USB_HS_ULPI3320
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@ -32,6 +32,7 @@
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#include "extmod/modnetwork.h"
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#include "mpu.h"
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#include "eth.h"
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#include "eth_phy.h"
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#if defined(MICROPY_HW_ETH_MDC)
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@ -40,26 +41,6 @@
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#include "lwip/dhcp.h"
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#include "netif/ethernet.h"
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// ETH PHY register definitions (for LAN8742 and LAN8720/LAN8710)
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#undef PHY_BCR
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#define PHY_BCR (0x0000)
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#define PHY_BCR_SOFT_RESET (0x8000)
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#define PHY_BCR_AUTONEG_EN (0x1000)
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#define PHY_BCR_POWER_DOWN (0x0800U)
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#undef PHY_BSR
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#define PHY_BSR (0x0001)
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#define PHY_BSR_LINK_STATUS (0x0004)
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#define PHY_BSR_AUTONEG_DONE (0x0020)
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#define PHY_SCSR (0x001f)
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#define PHY_SCSR_SPEED_Pos (2)
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#define PHY_SCSR_SPEED_Msk (7 << PHY_SCSR_SPEED_Pos)
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#define PHY_SCSR_SPEED_10HALF (1 << PHY_SCSR_SPEED_Pos)
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#define PHY_SCSR_SPEED_10FULL (5 << PHY_SCSR_SPEED_Pos)
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#define PHY_SCSR_SPEED_100HALF (2 << PHY_SCSR_SPEED_Pos)
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#define PHY_SCSR_SPEED_100FULL (6 << PHY_SCSR_SPEED_Pos)
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// ETH DMA RX and TX descriptor definitions
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#if defined(STM32H5)
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#define RX_DESCR_3_OWN_Pos (31)
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@ -137,6 +118,7 @@ typedef struct _eth_t {
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struct netif netif;
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struct dhcp dhcp_struct;
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uint32_t phy_addr;
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int16_t (*phy_get_link_status)(uint32_t phy_addr);
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} eth_t;
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static eth_dma_t eth_dma __attribute__((aligned(16384)));
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@ -146,7 +128,7 @@ eth_t eth_instance;
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static void eth_mac_deinit(eth_t *self);
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static void eth_process_frame(eth_t *self, size_t len, const uint8_t *buf);
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static void eth_phy_write(uint32_t phy_addr, uint32_t reg, uint32_t val) {
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void eth_phy_write(uint32_t phy_addr, uint32_t reg, uint32_t val) {
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#if defined(STM32H5) || defined(STM32H7)
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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@ -174,7 +156,7 @@ static void eth_phy_write(uint32_t phy_addr, uint32_t reg, uint32_t val) {
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#endif
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}
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static uint32_t eth_phy_read(uint32_t phy_addr, uint32_t reg) {
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uint32_t eth_phy_read(uint32_t phy_addr, uint32_t reg) {
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#if defined(STM32H5) || defined(STM32H7)
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while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
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}
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@ -202,10 +184,17 @@ static uint32_t eth_phy_read(uint32_t phy_addr, uint32_t reg) {
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#endif
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}
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void eth_init(eth_t *self, int mac_idx, uint32_t phy_addr) {
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int eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type) {
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mp_hal_get_mac(mac_idx, &self->netif.hwaddr[0]);
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self->netif.hwaddr_len = 6;
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self->phy_addr = phy_addr;
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if (phy_type == ETH_PHY_DP83825 || phy_type == ETH_PHY_DP83848) {
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self->phy_get_link_status = eth_phy_dp838xx_get_link_status;
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} else if (phy_type == ETH_PHY_LAN8720 || phy_type == ETH_PHY_LAN8742) {
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self->phy_get_link_status = eth_phy_lan87xx_get_link_status;
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} else {
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return -1;
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}
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// Configure GPIO
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mp_hal_pin_config_alt_static(MICROPY_HW_ETH_MDC, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_MDC);
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@ -230,6 +219,7 @@ void eth_init(eth_t *self, int mac_idx, uint32_t phy_addr) {
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#else
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__HAL_RCC_ETH_CLK_ENABLE();
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#endif
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return 0;
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}
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void eth_set_trace(eth_t *self, uint32_t value) {
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@ -381,6 +371,14 @@ static int eth_mac_init(eth_t *self) {
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break;
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case 1:
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if (bsr & PHY_BSR_LINK_STATUS) {
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// Announce all modes
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eth_phy_write(self->phy_addr, PHY_ANAR,
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PHY_ANAR_SPEED_10HALF |
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PHY_ANAR_SPEED_10FULL |
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PHY_ANAR_SPEED_100HALF |
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PHY_ANAR_SPEED_100FULL |
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PHY_ANAR_IEEE802_3);
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// Start autonegotiate.
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eth_phy_write(self->phy_addr, PHY_BCR, PHY_BCR_AUTONEG_EN);
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phy_state = 2;
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}
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@ -396,7 +394,7 @@ static int eth_mac_init(eth_t *self) {
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}
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// Get register with link status
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uint16_t phy_scsr = eth_phy_read(self->phy_addr, PHY_SCSR);
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uint16_t phy_scsr = self->phy_get_link_status(self->phy_addr);
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// Burst mode configuration
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#if defined(STM32H5) || defined(STM32H7)
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@ -505,9 +503,9 @@ static int eth_mac_init(eth_t *self) {
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// Set main MAC control register
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ETH->MACCR =
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(phy_scsr & PHY_SCSR_SPEED_Msk) == PHY_SCSR_SPEED_10FULL ? ETH_MACCR_DM
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: (phy_scsr & PHY_SCSR_SPEED_Msk) == PHY_SCSR_SPEED_100HALF ? ETH_MACCR_FES
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: (phy_scsr & PHY_SCSR_SPEED_Msk) == PHY_SCSR_SPEED_100FULL ? (ETH_MACCR_FES | ETH_MACCR_DM)
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phy_scsr == PHY_SPEED_10FULL ? ETH_MACCR_DM
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: phy_scsr == PHY_SPEED_100HALF ? ETH_MACCR_FES
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: phy_scsr == PHY_SPEED_100FULL ? (ETH_MACCR_FES | ETH_MACCR_DM)
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: 0
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;
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mp_hal_delay_ms(2);
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@ -26,10 +26,17 @@
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#ifndef MICROPY_INCLUDED_STM32_ETH_H
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#define MICROPY_INCLUDED_STM32_ETH_H
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enum {
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ETH_PHY_LAN8742 = 0,
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ETH_PHY_LAN8720,
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ETH_PHY_DP83848,
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ETH_PHY_DP83825
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};
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typedef struct _eth_t eth_t;
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extern eth_t eth_instance;
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void eth_init(eth_t *self, int mac_idx, uint32_t phy_addr);
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int eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type);
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void eth_set_trace(eth_t *self, uint32_t value);
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struct netif *eth_netif(eth_t *self);
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int eth_link_status(eth_t *self);
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@ -0,0 +1,59 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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* Copyright (c) 2024 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mphal.h"
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#include "eth_phy.h"
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#if defined(MICROPY_HW_ETH_MDC)
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#define PHY_SCSR_LAN87XX (0x001f)
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#define PHY_SCSR_LAN87XX_SPEED_Pos (2)
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#define PHY_SCSR_LAN87XX_SPEED_Msk (7)
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#define PHY_SCSR_DP838XX (0x0010)
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#define PHY_RECR_DP838XX (0x0015)
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#define PHY_SCSR_DP838XX_DUPLEX_Msk (4)
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#define PHY_SCSR_DP838XX_10M_Msk (2)
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int16_t eth_phy_lan87xx_get_link_status(uint32_t phy_addr) {
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// Get the link mode & speed
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int16_t scsr = eth_phy_read(phy_addr, PHY_SCSR_LAN87XX);
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return (scsr >> PHY_SCSR_LAN87XX_SPEED_Pos) & PHY_SCSR_LAN87XX_SPEED_Msk;
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}
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int16_t eth_phy_dp838xx_get_link_status(uint32_t phy_addr) {
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int16_t scsr = 0;
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// Get the link mode & speed
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uint16_t temp = eth_phy_read(phy_addr, PHY_SCSR_DP838XX);
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scsr = (temp & PHY_SCSR_DP838XX_10M_Msk) ? PHY_SPEED_10HALF : PHY_SPEED_100HALF;
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if (temp & PHY_SCSR_DP838XX_DUPLEX_Msk) {
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scsr |= PHY_DUPLEX;
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}
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return scsr;
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}
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#endif
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@ -0,0 +1,67 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Damien P. George
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* Copyright (c) 2024 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_STM32_PHY_H
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#define MICROPY_INCLUDED_STM32_PYH_H
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#if defined(MICROPY_HW_ETH_MDC)
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// Common ETH PHY register definitions
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#undef PHY_BCR
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#define PHY_BCR (0x0000)
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#define PHY_BCR_SOFT_RESET (0x8000)
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#define PHY_BCR_AUTONEG_EN (0x1000)
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#define PHY_BCR_POWER_DOWN (0x0800U)
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#undef PHY_BSR
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#define PHY_BSR (0x0001)
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#define PHY_BSR_LINK_STATUS (0x0004)
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#define PHY_BSR_AUTONEG_DONE (0x0020)
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#undef PHY_ANAR
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#define PHY_ANAR (0x0004)
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#define PHY_ANAR_SPEED_10HALF (0x0020)
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#define PHY_ANAR_SPEED_10FULL (0x0040)
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#define PHY_ANAR_SPEED_100HALF (0x0080)
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#define PHY_ANAR_SPEED_100FULL (0x0100)
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#define PHY_ANAR_IEEE802_3 (0x0001)
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#define PHY_SPEED_10HALF (1)
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#define PHY_SPEED_10FULL (5)
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#define PHY_SPEED_100HALF (2)
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#define PHY_SPEED_100FULL (6)
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#define PHY_DUPLEX (4)
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uint32_t eth_phy_read(uint32_t phy_addr, uint32_t reg);
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void eth_phy_write(uint32_t phy_addr, uint32_t reg, uint32_t val);
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int16_t eth_phy_lan87xx_get_link_status(uint32_t phy_addr);
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int16_t eth_phy_dp838xx_get_link_status(uint32_t phy_addr);
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#endif
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#endif // MICROPY_INCLUDED_STM32_PHY_H
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@ -54,16 +54,19 @@ static void network_lan_print(const mp_print_t *print, mp_obj_t self_in, mp_prin
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}
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static mp_obj_t network_lan_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
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enum { ARG_phy_addr};
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enum { ARG_phy_addr, ARG_phy_type};
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_phy_addr, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
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{ MP_QSTR_phy_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = ETH_PHY_LAN8742} },
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};
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// Parse args.
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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const network_lan_obj_t *self = &network_lan_eth0;
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eth_init(self->eth, MP_HAL_MAC_ETH0, args[ARG_phy_addr].u_int);
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if (eth_init(self->eth, MP_HAL_MAC_ETH0, args[ARG_phy_addr].u_int, args[ARG_phy_type].u_int) != 0) {
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mp_raise_ValueError(MP_ERROR_TEXT("invalid phy_type"));
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}
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return MP_OBJ_FROM_PTR(self);
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}
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@ -162,6 +165,11 @@ static const mp_rom_map_elem_t network_lan_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_ifconfig), MP_ROM_PTR(&network_lan_ifconfig_obj) },
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{ MP_ROM_QSTR(MP_QSTR_status), MP_ROM_PTR(&network_lan_status_obj) },
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{ MP_ROM_QSTR(MP_QSTR_config), MP_ROM_PTR(&network_lan_config_obj) },
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{ MP_ROM_QSTR(MP_QSTR_PHY_LAN8742), MP_ROM_INT(ETH_PHY_LAN8742) },
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{ MP_ROM_QSTR(MP_QSTR_PHY_LAN8720), MP_ROM_INT(ETH_PHY_LAN8720) },
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{ MP_ROM_QSTR(MP_QSTR_PHY_DP83848), MP_ROM_INT(ETH_PHY_DP83848) },
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{ MP_ROM_QSTR(MP_QSTR_PHY_DP83825), MP_ROM_INT(ETH_PHY_DP83825) },
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};
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static MP_DEFINE_CONST_DICT(network_lan_locals_dict, network_lan_locals_dict_table);
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