kopia lustrzana https://github.com/micropython/micropython
qemu-arm: Add support for Cortex-A9 via sabrelite board.
Signed-off-by: Damien George <damien@micropython.org>pull/5975/head
Damien George
rodzic
f5cba77e50
commit
b84406f313
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@ -16,7 +16,8 @@ ifeq ($(BOARD),netduino2)
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CFLAGS += -mthumb -mcpu=cortex-m3 -mfloat-abi=soft
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CFLAGS += -DQEMU_SOC_STM32
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LDSCRIPT = stm32.ld
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SRC_BOARD_O = lib/utils/gchelper_m3.o
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SRC_BOARD_O = lib/utils/gchelper_native.o lib/utils/gchelper_m3.o
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MPY_CROSS_FLAGS += -march=armv7m
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endif
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ifeq ($(BOARD),microbit)
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@ -24,14 +25,26 @@ CFLAGS += -mthumb -mcpu=cortex-m0 -mfloat-abi=soft
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CFLAGS += -DQEMU_SOC_NRF51
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LDSCRIPT = nrf51.ld
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QEMU_EXTRA = -global nrf51-soc.flash-size=1048576 -global nrf51-soc.sram-size=262144
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SRC_BOARD_O = lib/utils/gchelper_m0.o
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SRC_BOARD_O = lib/utils/gchelper_native.o lib/utils/gchelper_m0.o
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MPY_CROSS_FLAGS += -march=armv7m
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endif
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ifeq ($(BOARD),mps2-an385)
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CFLAGS += -mthumb -mcpu=cortex-m3 -mfloat-abi=soft
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CFLAGS += -DQEMU_SOC_MPS2
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LDSCRIPT = mps2.ld
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SRC_BOARD_O = lib/utils/gchelper_m3.o
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SRC_BOARD_O = lib/utils/gchelper_native.o lib/utils/gchelper_m3.o
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MPY_CROSS_FLAGS += -march=armv7m
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endif
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ifeq ($(BOARD),sabrelite)
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CFLAGS += -mcpu=cortex-a9
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CFLAGS += -DQEMU_SOC_IMX6
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LDSCRIPT = imx6.ld
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QEMU_EXTRA = -m 128M
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SRC_BOARD_O = lib/utils/gchelper_generic.o
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# It's really armv7a but closest supported value is armv6.
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MPY_CROSS_FLAGS += -march=armv6
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endif
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CROSS_COMPILE ?= arm-none-eabi-
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@ -95,7 +108,6 @@ LIB_SRC_C += $(addprefix lib/,\
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libm/atanf.c \
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libm/atan2f.c \
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libm/roundf.c \
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utils/gchelper_native.c \
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utils/sys_stdio_mphal.c \
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)
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@ -125,7 +137,6 @@ ifneq ($(FROZEN_MANIFEST),)
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CFLAGS += -DMICROPY_MODULE_FROZEN_STR
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CFLAGS += -DMICROPY_MODULE_FROZEN_MPY
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CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool
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MPY_CROSS_FLAGS += -march=armv7m
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endif
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all: run
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@ -4,6 +4,11 @@ FROZEN_MANIFEST ?= "freeze('test-frzmpy')"
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include Makefile
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ifeq ($(BOARD),sabrelite)
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# These don't work on Cortex-A9.
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TESTS_EXCLUDE = inlineasm/asmdiv.py inlineasm/asmspecialregs.py
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endif
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CFLAGS += -DTEST
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.PHONY: $(BUILD)/genhdr/tests.h
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@ -11,7 +16,7 @@ CFLAGS += -DTEST
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$(BUILD)/test_main.o: $(BUILD)/genhdr/tests.h
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$(BUILD)/genhdr/tests.h:
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(cd $(TOP)/tests; ./run-tests.py --target=qemu-arm --write-exp)
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$(Q)echo "Generating $@";(cd $(TOP)/tests; ../tools/tinytest-codegen.py) > $@
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$(Q)echo "Generating $@";(cd $(TOP)/tests; ../tools/tinytest-codegen.py $(addprefix --exclude ,$(TESTS_EXCLUDE))) > $@
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$(BUILD)/lib/tinytest/tinytest.o: CFLAGS += -DNO_FORKING
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@ -0,0 +1,47 @@
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/* Vector table is at 0x00000000, entry point is 0x10000000. */
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MEMORY
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{
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ROM : ORIGIN = 0x00000000, LENGTH = 96K
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RAM : ORIGIN = 0x10000000, LENGTH = 128M
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}
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_estack = ORIGIN(RAM) + LENGTH(RAM);
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SECTIONS
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{
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.rom : {
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. = ALIGN(4);
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KEEP(*(.isr_vector))
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. = ALIGN(4);
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} > ROM
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.text : {
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. = ALIGN(4);
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*(.text.Reset_Handler)
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*(.text*)
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*(.rodata*)
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. = ALIGN(4);
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_etext = .;
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_sidata = _etext;
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} > RAM
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.data : AT ( _sidata )
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{
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. = ALIGN(4);
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_sdata = .;
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*(.data*)
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. = ALIGN(4);
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_edata = .;
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} > RAM
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.bss :
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{
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. = ALIGN(4);
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_sbss = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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} > RAM
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}
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@ -3,9 +3,16 @@
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// options to control how MicroPython is built
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#define MICROPY_ALLOC_PATH_MAX (512)
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#define MICROPY_EMIT_X64 (0)
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#if defined(__ARM_ARCH_ISA_ARM)
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#define MICROPY_EMIT_ARM (1)
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#define MICROPY_EMIT_INLINE_THUMB (1)
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#elif defined(__ARM_ARCH_ISA_THUMB)
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#define MICROPY_EMIT_THUMB (1)
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#define MICROPY_EMIT_INLINE_THUMB (1)
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#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void *)((mp_uint_t)(p) | 1))
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#endif
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#define MICROPY_MALLOC_USES_ALLOCATED_SIZE (1)
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#define MICROPY_MEM_STATS (1)
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#define MICROPY_DEBUG_PRINTERS (0)
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@ -43,8 +50,6 @@
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// type definitions for the specific machine
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#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void *)((mp_uint_t)(p) | 1))
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#define MP_SSIZE_MAX (0x7fffffff)
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#define UINT_FMT "%lu"
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@ -28,6 +28,27 @@ void Default_Handler(void) {
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}
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}
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#if defined(__ARM_ARCH_ISA_ARM)
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// ARM architecture with standard ARM ISA.
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__attribute__((naked, section(".isr_vector"))) void isr_vector(void) {
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__asm volatile (
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"b Reset_Handler\n"
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"b Default_Handler\n"
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"b Default_Handler\n"
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"b Default_Handler\n"
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"b Default_Handler\n"
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"nop\n"
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"b Default_Handler\n"
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"b Default_Handler\n"
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);
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}
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#elif defined(__ARM_ARCH_ISA_THUMB)
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// ARM architecture with Thumb-only ISA.
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const uint32_t isr_vector[] __attribute__((section(".isr_vector"))) = {
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(uint32_t)&_estack,
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(uint32_t)&Reset_Handler,
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@ -47,6 +68,8 @@ const uint32_t isr_vector[] __attribute__((section(".isr_vector"))) = {
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(uint32_t)&Default_Handler, // SysTick_Handler
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};
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#endif
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void _start(void) {
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// Enable the UART
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uart_init();
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@ -68,7 +91,11 @@ __attribute__((naked)) void exit(int status) {
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"ldr r1, =0x20026\n" // ADP_Stopped_ApplicationExit, a clean exit
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".notclean:\n"
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"movs r0, #0x18\n" // SYS_EXIT
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#if defined(__ARM_ARCH_ISA_ARM)
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"svc 0x00123456\n"
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#elif defined(__ARM_ARCH_ISA_THUMB)
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"bkpt 0xab\n"
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#endif
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);
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for (;;) {
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}
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@ -75,4 +75,31 @@ void uart_tx_strn(const char *buf, size_t len) {
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}
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}
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#elif defined(QEMU_SOC_IMX6)
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#define UART_UCR1_UARTEN (1 << 0)
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#define UART_UCR2_TXEN (1 << 2)
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typedef struct _UART_t {
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volatile uint32_t URXD; // 0x00
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volatile uint32_t r0[15];
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volatile uint32_t UTXD; // 0x40
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volatile uint32_t r1[15];
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volatile uint32_t UCR1; // 0x80
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volatile uint32_t UCR2; // 0x84
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} UART_t;
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#define UART1 ((UART_t *)(0x02020000))
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void uart_init(void) {
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UART1->UCR1 = UART_UCR1_UARTEN;
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UART1->UCR2 = UART_UCR2_TXEN;
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}
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void uart_tx_strn(const char *buf, size_t len) {
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for (size_t i = 0; i < len; ++i) {
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UART1->UTXD = buf[i];
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}
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}
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#endif
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