kopia lustrzana https://github.com/micropython/micropython
stmhal: Add STM32F7DISC and associated changes.
Dave Hylands
Damien George
rodzic
7e7fb0b7a3
commit
92d4b51ad5
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@ -44,8 +44,13 @@ INC += -I../lib/mp-readline
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INC += -I../lib/netutils
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INC += -I../lib/timeutils
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CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion
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CFLAGS = $(INC) -Wall -Wpointer-arith -Werror -ansi -std=gnu99 -nostdlib $(CFLAGS_MOD) $(CFLAGS_CORTEX_M4) $(COPT)
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CFLAGS_CORTEX_M = -mthumb -mabi=aapcs-linux -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant -Wdouble-promotion
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CFLAGS_MCU_f4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4
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CFLAGS_MCU_f7 = $(CFLAGS_CORTEX_M) -mtune=cortex-m7 -mcpu=cortex-m7
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CFLAGS = $(INC) -Wall -Wpointer-arith -Werror -ansi -std=gnu99 -nostdlib $(CFLAGS_MOD)
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CFLAGS += $(CFLAGS_MCU_$(MCU_SERIES))
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CFLAGS += $(COPT)
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CFLAGS += -Iboards/$(BOARD)
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CFLAGS += -DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>'
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@ -154,6 +159,7 @@ SRC_C = \
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servo.c \
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dac.c \
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adc.c \
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$(wildcard boards/$(BOARD)/*.c)
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SRC_O = \
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startup_stm32.o \
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@ -62,8 +62,11 @@
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defined(STM32F411xE)
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#define VBAT_DIV (2)
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#elif defined(STM32F427xx) || defined(STM32F429xx) || \
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defined(STM32F437xx) || defined(STM32F439xx)
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defined(STM32F437xx) || defined(STM32F439xx) || \
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defined(STM32F746xx)
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#define VBAT_DIV (4)
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#else
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#error Unsupported processor
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#endif
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/* Core temperature sensor definitions */
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@ -0,0 +1,15 @@
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#include STM32_HAL_H
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void STM32F7DISC_board_early_init(void) {
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GPIO_InitTypeDef GPIO_InitStructure;
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__GPIOK_CLK_ENABLE();
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// Turn off the backlight. LCD_BL_CTRL = PK3
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GPIO_InitStructure.Pin = GPIO_PIN_3;
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GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
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GPIO_InitStructure.Pull = GPIO_PULLUP;
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GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
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HAL_GPIO_Init(GPIOK, &GPIO_InitStructure);
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HAL_GPIO_WritePin(GPIOK, GPIO_PIN_3, GPIO_PIN_RESET);
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}
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@ -0,0 +1,59 @@
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#define STM32F7DISC
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#define MICROPY_HW_BOARD_NAME "F7DISC"
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#define MICROPY_HW_MCU_NAME "STM32F746"
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#define MICROPY_HW_HAS_SWITCH (1)
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#define MICROPY_HW_HAS_SDCARD (0)
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#define MICROPY_HW_HAS_MMA7660 (0)
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#define MICROPY_HW_HAS_LIS3DSH (0)
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#define MICROPY_HW_HAS_LCD (0)
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#define MICROPY_HW_ENABLE_RNG (1)
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#define MICROPY_HW_ENABLE_RTC (1)
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#define MICROPY_HW_ENABLE_TIMER (1)
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#define MICROPY_HW_ENABLE_SERVO (0)
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#define MICROPY_HW_ENABLE_DAC (0)
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#define MICROPY_HW_ENABLE_SPI1 (1)
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#define MICROPY_HW_ENABLE_SPI2 (1)
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#define MICROPY_HW_ENABLE_SPI3 (0)
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#define MICROPY_HW_ENABLE_CAN (1)
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#define MICROPY_BOARD_EARLY_INIT STM32F7DISC_board_early_init
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void STM32F7DISC_board_early_init(void);
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// HSE is 8MHz
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#define MICROPY_HW_CLK_PLLM (25)
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#define MICROPY_HW_CLK_PLLN (400)
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#define MICROPY_HW_CLK_PLLP (RCC_PLLP_DIV2)
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#define MICROPY_HW_CLK_PLLQ (8)
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#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_6
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// UART config
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#define MICROPY_HW_UART6_PORT (GPIOC)
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#define MICROPY_HW_UART6_PINS (GPIO_PIN_6 | GPIO_PIN_7)
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#define MICROPY_HW_UART7_PORT (GPIOF)
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#define MICROPY_HW_UART7_PINS (GPIO_PIN_6 | GPIO_PIN_7)
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#define MICROPY_HW_UART_REPL PYB_UART_6
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#define MICROPY_HW_UART_REPL_BAUD 115200
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// I2C busses
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#define MICROPY_HW_I2C1_SCL (pin_B8)
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#define MICROPY_HW_I2C1_SDA (pin_B9)
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// USRSW is pulled low. Pressing the button makes the input go high.
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#define MICROPY_HW_USRSW_PIN (pin_I11)
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#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL)
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#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING)
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#define MICROPY_HW_USRSW_PRESSED (1)
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// LEDs
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#define MICROPY_HW_LED1 (pin_I1) // green
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#define MICROPY_HW_LED_OTYPE (GPIO_MODE_OUTPUT_PP)
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#define MICROPY_HW_LED_ON(pin) (pin->gpio->BSRR = pin->pin_mask)
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#define MICROPY_HW_LED_OFF(pin) (pin->gpio->BSRR = (pin->pin_mask << 16))
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// USB config (CN13 - USB OTG FS)
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#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
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#define MICROPY_HW_USB_OTG_ID_PIN (pin_A10)
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@ -0,0 +1,3 @@
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MCU_SERIES = f7
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AF_FILE = boards/stm32f746_af.csv
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LD_FILE = boards/stm32f746.ld
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@ -0,0 +1,32 @@
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A0,PA0
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A1,PF10
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A2,PF9
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A3,PF8
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A4,PF7
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A5,PF6
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D0,PC7
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D1,PC6
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D2,PG6
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D3,PB4
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D4,PG7
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D5,PA8
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D6,PH6
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D7,PI3
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D8,PI2
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D9,PA15
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D10,PI0
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D11,PB15
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D12,PB14
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D13,PI1
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D14,PB9
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D15,PB8
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LED,PI1
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SW,PI11
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TP1,PH2
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TP2,PI8
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TP3,PH15
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LCD_BL_CTRL,PK3
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USB_VBUS,PA9
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USB_ID,PA10
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USB_DM,PA11
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USB_DP,PA12
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@ -0,0 +1,433 @@
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/**
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******************************************************************************
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* @file stm32f7xx_hal_conf.h
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* @author MCD Application Team
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* @version V1.0.1
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* @date 25-June-2015
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* @brief HAL configuration file.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F7xx_HAL_CONF_H
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#define __STM32F7xx_HAL_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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#define STM32F746xx
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/* ########################## Module Selection ############################## */
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/**
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* @brief This is the list of modules to be used in the HAL driver
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*/
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#define HAL_MODULE_ENABLED
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#define HAL_ADC_MODULE_ENABLED
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#define HAL_CAN_MODULE_ENABLED
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/* #define HAL_CEC_MODULE_ENABLED */
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/* #define HAL_CRC_MODULE_ENABLED */
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/* #define HAL_CRYP_MODULE_ENABLED */
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/* #define HAL_DAC_MODULE_ENABLED */
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/* #define HAL_DCMI_MODULE_ENABLED */
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#define HAL_DMA_MODULE_ENABLED
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/* #define HAL_DMA2D_MODULE_ENABLED */
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/* #define HAL_ETH_MODULE_ENABLED */
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#define HAL_FLASH_MODULE_ENABLED
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/* #define HAL_NAND_MODULE_ENABLED */
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/* #define HAL_NOR_MODULE_ENABLED */
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/* #define HAL_SRAM_MODULE_ENABLED */
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/* #define HAL_SDRAM_MODULE_ENABLED */
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/* #define HAL_HASH_MODULE_ENABLED */
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#define HAL_GPIO_MODULE_ENABLED
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#define HAL_I2C_MODULE_ENABLED
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#define HAL_I2S_MODULE_ENABLED
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/* #define HAL_IWDG_MODULE_ENABLED */
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/* #define HAL_LPTIM_MODULE_ENABLED */
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/* #define HAL_LTDC_MODULE_ENABLED */
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#define HAL_PWR_MODULE_ENABLED
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/* #define HAL_QSPI_MODULE_ENABLED */
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#define HAL_RCC_MODULE_ENABLED
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#define HAL_RNG_MODULE_ENABLED
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#define HAL_RTC_MODULE_ENABLED
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/* #define HAL_SAI_MODULE_ENABLED */
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#define HAL_SD_MODULE_ENABLED
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/* #define HAL_SPDIFRX_MODULE_ENABLED */
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#define HAL_SPI_MODULE_ENABLED
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#define HAL_TIM_MODULE_ENABLED
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#define HAL_UART_MODULE_ENABLED
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/* #define HAL_USART_MODULE_ENABLED */
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/* #define HAL_IRDA_MODULE_ENABLED */
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/* #define HAL_SMARTCARD_MODULE_ENABLED */
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/* #define HAL_WWDG_MODULE_ENABLED */
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#define HAL_CORTEX_MODULE_ENABLED
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#define HAL_PCD_MODULE_ENABLED
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/* #define HAL_HCD_MODULE_ENABLED */
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/* ########################## Timeout Configuration ######################### */
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/**
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* @brief This is the HAL configuration section
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*/
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#define HAL_ACCURATE_TIMEOUT_ENABLED 0
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#define HAL_TIMEOUT_VALUE 0x1FFFFFF
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/* ########################## HSE/HSI Values adaptation ##################### */
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/**
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* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
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* This value is used by the RCC HAL module to compute the system frequency
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* (when HSE is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSE_STARTUP_TIMEOUT)
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#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
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#endif /* HSE_STARTUP_TIMEOUT */
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/**
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* @brief Internal High Speed oscillator (HSI) value.
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* This value is used by the RCC HAL module to compute the system frequency
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* (when HSI is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @brief Internal Low Speed oscillator (LSI) value.
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*/
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#if !defined (LSI_VALUE)
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#define LSI_VALUE ((uint32_t)32000)
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#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
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The real value may vary depending on the variations
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in voltage and temperature. */
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/**
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* @brief External Low Speed oscillator (LSE) value.
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*/
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#if !defined (LSE_VALUE)
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#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
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#endif /* LSE_VALUE */
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/**
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* @brief External clock source for I2S peripheral
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* This value is used by the I2S HAL module to compute the I2S clock source
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* frequency, this source is inserted directly through I2S_CKIN pad.
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*/
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#if !defined (EXTERNAL_CLOCK_VALUE)
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#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* EXTERNAL_CLOCK_VALUE */
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/* Tip: To avoid modifying this file each time you need to use different HSE,
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=== you can define the HSE value in your toolchain compiler preprocessor. */
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/* ########################### System Configuration ######################### */
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/**
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* @brief This is the HAL system configuration section
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*/
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#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
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#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
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#define USE_RTOS 0
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#define ART_ACCLERATOR_ENABLE 1 /* To enable instruction cache and prefetch */
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/* ########################## Assert Selection ############################## */
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/**
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* @brief Uncomment the line below to expanse the "assert_param" macro in the
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* HAL drivers code
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*/
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/* #define USE_FULL_ASSERT 1 */
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/* ################## Ethernet peripheral configuration ##################### */
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/* Section 1 : Ethernet peripheral configuration */
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
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#define MAC_ADDR0 2
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#define MAC_ADDR1 1
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#define MAC_ADDR2 0
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#define MAC_ADDR3 0
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#define MAC_ADDR4 0
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#define MAC_ADDR5 0
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB ((uint32_t)5) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
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/* Section 2: PHY configuration section */
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/* LAN8742A PHY Address*/
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#define LAN8742A_PHY_ADDRESS 0x00
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
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#define PHY_RESET_DELAY ((uint32_t)0x00000FFF)
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/* PHY Configuration delay */
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#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFF)
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#define PHY_READ_TO ((uint32_t)0x0000FFFF)
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#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
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/* Section 3: Common PHY Registers */
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#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
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#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
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/* Section 4: Extended PHY Registers */
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#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
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#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
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#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
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#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
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#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
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#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
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#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
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#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
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#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
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||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F7xx_HAL_CONF_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
GNU linker script for STM32F405
|
||||
*/
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
FLASH_ISR (rx) : ORIGIN = 0x08000000, LENGTH = 16K /* sector 0, 16K */
|
||||
FLASH_FS (r) : ORIGIN = 0x08004000, LENGTH = 112K /* sectors 1, 2, 3 (16K each) sector 4 (64K) */
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x08020000, LENGTH = 896K /* sectors 5-11 7*128KiB = 896K */
|
||||
DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 64K /* Used for storage cache */
|
||||
RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 256K /* SRAM1 = 240K, SRAM2 = 16K */
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* produce a link error if there is not this amount of RAM for these sections */
|
||||
_minimum_stack_size = 2K;
|
||||
_minimum_heap_size = 16K;
|
||||
|
||||
/* Define tho top end of the stack. The stack is full descending so begins just
|
||||
above last byte of RAM. Note that EABI requires the stack to be 8-byte
|
||||
aligned for a call. */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM);
|
||||
|
||||
/* RAM extents for the garbage collector */
|
||||
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_heap_end = 0x2004c000; /* tunable */
|
||||
|
||||
/* define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
|
||||
/* This first flash block is 16K annd the isr vectors only take up
|
||||
about 400 bytes. So we pull in a couple of object files to pad it
|
||||
out. */
|
||||
|
||||
. = ALIGN(4);
|
||||
*/ff.o(.text*)
|
||||
*/stm32f4xx_hal_sd.o(.text*)
|
||||
|
||||
. = ALIGN(4);
|
||||
} >FLASH_ISR
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
/* *(.glue_7) */ /* glue arm to thumb code */
|
||||
/* *(.glue_7t) */ /* glue thumb to arm code */
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbol at end of code */
|
||||
} >FLASH_TEXT
|
||||
|
||||
/*
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
*/
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* This is the initialized data section
|
||||
The program executes knowing that the data is in the RAM
|
||||
but the loader puts the initial values in the FLASH (inidata).
|
||||
It is one task of the startup to copy the initial values from FLASH to RAM. */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
|
||||
_ram_start = .; /* create a global symbol at ram start for garbage collector */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
|
||||
} >RAM AT> FLASH_TEXT
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .; /* define a global symbol at bss start; used by startup code */
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
|
||||
} >RAM
|
||||
|
||||
/* this is to define the start of the heap, and make sure we have a minimum size */
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
_heap_start = .; /* define a global symbol at heap start */
|
||||
. = . + _minimum_heap_size;
|
||||
} >RAM
|
||||
|
||||
/* this just checks there is enough RAM for the stack */
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
. = . + _minimum_stack_size;
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/*
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
*/
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
Port,,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15
|
||||
,,SYS,TIM1/2,TIM3/4/5,TIM8/9/10/11/LPTIM1/CEC,I2C1/2/3/4/CEC,SPI1/2/3/4/5/6,SPI3/SAI1,SPI2/3/USART1/2/3/UART5/SPDIFRX,SAI2/USART6/UART4/5/7/8/SPDIFRX,CAN1/2/TIM12/13/14/QUADSPI/LCD,SAI2/QUADSPI/OTG2_HS/OTG1_FS,ETH/OTG1_FS,FMC/SDMMC1/OTG2_FS,DCMI,LCD,SYS
|
||||
PortA,PA0,,TIM2_CH1/TIM2_ETR,TIM5_CH1,TIM8_ETR,,,,USART2_CTS,UART4_TX,,SAI2_SD_B,ETH_MII_CRS,,,,EVENTOUT
|
||||
PortA,PA1,,TIM2_CH2,TIM5_CH2,,,,,USART2_RTS,UART4_RX,QUADSPI_BK1_IO3,SAI2_MCK_B,ETH_MII_RX_CLK/ETH_RMII_REF_CLK,,,LCD_R2,EVENTOUT
|
||||
PortA,PA2,,TIM2_CH3,TIM5_CH3,TIM9_CH1,,,,USART2_TX,SAI2_SCK_B,,,ETH_MDIO,,,LCD_R1,EVENTOUT
|
||||
PortA,PA3,,TIM2_CH4,TIM5_CH4,TIM9_CH2,,,,USART2_RX,,,OTG_HS_ULPI_D0,ETH_MII_COL,,,LCD_B5,EVENTOUT
|
||||
PortA,PA4,,,,,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,OTG_HS_SOF,DCMI_HSYNC,LCD_VSYNC,EVENTOUT
|
||||
PortA,PA5,,TIM2_CH1/TIM2_ETR,TIM8_CH1N,SPI1_SCK/I2S1_CK,,,,,,,OTG_HS_ULPI_CK,,,,LCD_R4,EVENTOUT
|
||||
PortA,PA6,,TIM1_BKIN,TIM3_CH1,TIM8_BKIN,,SPI1_MISO,,,,TIM13_CH1,,,,DCMI_PIXCLK,LCD_G2,EVENTOUT
|
||||
PortA,PA7,,TIM1_CH1N,TIM3_CH2,TIM8_CH1N,,SPI1_MOSI/I2S1_SD,,,,TIM14_CH1,,ETH_MII_RX_DV/ETH_RMII_CRS_DV,FMC_SDNWE,,,EVENTOUT
|
||||
PortA,PA8,MCO1,TIM1_CH1,,TIM8_BKIN2,I2C3_SCL,,,USART1_CK,,,OTG_FS_SOF,,,,LCD_R6,EVENTOUT
|
||||
PortA,PA9,,TIM1_CH2,,,I2C3_SMBA,SPI2_SCK/I2S2_CK,,USART1_TX,,,,,,DCMI_D0,,EVENTOUT
|
||||
PortA,PA10,,TIM1_CH3,,,,,,USART1_RX,,,OTG_FS_ID,,,DCMI_D1,,EVENTOUT
|
||||
PortA,PA11,,TIM1_CH4,,,,,,USART1_CTS,,CAN1_RX,OTG_FS_DM,,,,LCD_R4,EVENTOUT
|
||||
PortA,PA12,,TIM1_ETR,,,,,,USART1_RTS,SAI2_FS_B,CAN1_TX,OTG_FS_DP,,,,LCD_R5,EVENTOUT
|
||||
PortA,PA13,JTMS,SWDIO,,,,,,,,,,,,,,EVENTOUT
|
||||
PortA,PA14,JTCK,SWCLK,,,,,,,,,,,,,,EVENTOUT
|
||||
PortA,PA15,JTDI,TIM2_CH1/TIM2_ETR,,,HDMICE,CSPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,UART4_RTS,,,,,,,EVENTOUT
|
||||
PortB,PB0,,TIM1_CH2N,TIM3_CH3T,IM8_CH2N,,,,,UART4_CTS,LCD_R3,OTG_HS_ULPI_D1,ETH_MII_RXD2,,,,EVENTOUT
|
||||
PortB,PB1,,TIM1_CH3N,TIM3_CH4T,IM8_CH3N,,,,,,LCD_R6,OTG_HS_ULPI_D2,ETH_MII_RXD3,,,,EVENTOUT
|
||||
PortB,PB2,,,,,,,SAI1_SD_A,SPI3_MOSI/I2S3_SD,,QUADSPI_CLK,,,,,,EVENTOUT
|
||||
PortB,PB3,JTDO/TRACESWO,TIM2_CH2,,,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,,,,,,,,,EVENTOUT
|
||||
PortB,PB4,NJTRST,,TIM3_CH1,,,SPI1_MISO,SPI3_MISO,SPI2_NSS/I2S2_WS,,,,,,,,EVENTOUT
|
||||
PortB,PB5,,,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,,,CAN2_RX,OTG_HS_ULPI_D7,ETH_PPS_OUT,FMC_SDCKE1,DCMI_D10,,EVENTOUT
|
||||
PortB,PB6,,,TIM4_CH1,HDMICEC,I2C1_SCL,,,USART1_TX,,CAN2_TX,QUADSPI_BK1_NCS,,FMC_SDNE1,DCMI_D5,,EVENTOUT
|
||||
PortB,PB7,,,TIM4_CH2,,I2C1_SDA,,,USART1_RX,,,,,FMC_NL,DCMI_VSYNC,,EVENTOUT
|
||||
PortB,PB8,,,TIM4_CH3,TIM10_CH1,I2C1_SCL,,,,,CAN1_RX,,ETH_MII_TXD3,SDMMC1_D4,DCMI_D6,LCD_B6,EVENTOUT
|
||||
PortB,PB9,,,TIM4_CH4,TIM11_CH1,I2C1_SDA,SPI2_NSS/I2S2_WS,,,,CAN1_TX,,,SDMMC1_D5,DCMI_D7,LCD_B7,EVENTOUT
|
||||
PortB,PB10,,TIM2_CH3,,,I2C2_SCL,SPI2_SCK/I2S2_CK,,USART3_TX,,,OTG_HS_ULPI_D3,ETH_MII_RX_ER,,,LCD_G4,EVENTOUT
|
||||
PortB,PB11,,TIM2_CH4,,,I2C2_SDA,,,USART3_RX,,,OTG_HS_ULPI_D4,ETH_MII_TX_EN/ETH_RMII_TX_EN,,,LCD_G5,EVENTOUT
|
||||
PortB,PB12,,TIM1_BKIN,,,I2C2_SMBA,SPI2_NSS/I2S2_WS,,USART3_CK,,CAN2_RX,OTG_HS_ULPI_D5,ETH_MII_TXD0/ETH_RMII_TXD0,OTG_HS_ID,,,EVENTOUT
|
||||
PortB,PB13,,TIM1_CH1N,,,,SPI2_SCK/I2S2_CK,,USART3_CTS,,CAN2_TX,OTG_HS_ULPI_D6,ETH_MII_TXD1/ETH_RMII_TXD1,,,,EVENTOUT
|
||||
PortB,PB14,,TIM1_CH2N,,TIM8_CH2N,,SPI2_MISO,,USART3_RTS,,TIM12_CH1,,,OTG_HS_DM,,,EVENTOUT
|
||||
PortB,PB15,RTC_REFIN,TIM1_CH3N,,TIM8_CH3N,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,OTG_HS_DP,,,EVENTOUT
|
||||
PortC,PC0,,,,,,,,,SAI2_FS_B,,OTG_HS_ULPI_STP,,FMC_SDNWE,,LCD_R5,EVENTOUT
|
||||
PortC,PC1,TRACED0,,,,,SPI2_MOSI/I2S2_SD,SAI1_SD_A,,,,,ETH_MDC,,,,EVENTOUT
|
||||
PortC,PC2,,,,,,SPI2_MISO,,,,,OTG_HS_ULPI_DIR,ETH_MII_TXD2,FMC_SDNE0,,,EVENTOUT
|
||||
PortC,PC3,,,,,,SPI2_MOSI/I2S2_SD,,,,,OTG_HS_ULPI_NXT,ETH_MII_TX_CLK,FMC_SDCKE0,,,EVENTOUT
|
||||
PortC,PC4,,,,,,I2S1_MCK,,,SPDIFRX_IN2,,,ETH_MII_RXD0/ETH_RMII_RXD0,FMC_SDNE0,,,EVENTOUT
|
||||
PortC,PC5,,,,,,,,,SPDIFRX_IN3,,,ETH_MII_RXD1/ETH_RMII_RXD1,FMC_SDCKE0,,,EVENTOUT
|
||||
PortC,PC6,,,TIM3_CH1,TIM8_CH1,,I2S2_MCK,,,USART6_TX,,,,SDMMC1_D6,DCMI_D0,LCD_HSYNC,EVENTOUT
|
||||
PortC,PC7,,,TIM3_CH2,TIM8_CH2,,,I2S3_MCK,,USART6_RX,,,,SDMMC1_D7,DCMI_D1,LCD_G6,EVENTOUT
|
||||
PortC,PC8,TRACED1,,TIM3_CH3,TIM8_CH3,,,,UART5_RTS,USART6_CK,,,,SDMMC1_D0,DCMI_D2,,EVENTOUT
|
||||
PortC,PC9,MCO2,,TIM3_CH4,TIM8_CH4,I2C3_SDA,I2S_CKIN,,UART5_CTS,,QUADSPI_BK1_IO0,,,SDMMC1_D1,DCMI_D3,,EVENTOUT
|
||||
PortC,PC10,,,,,,,SPI3_SCK/I2S3_CK,USART3_TX,UART4_TX,QUADSPI_BK1_IO1,,,SDMMC1_D2,DCMI_D8,LCD_R2,EVENTOUT
|
||||
PortC,PC11,,,,,,,SPI3_MISO,USART3_RX,UART4_RX,QUADSPI_BK2_NCS,,,SDMMC1_D3,DCMI_D4,,EVENTOUT
|
||||
PortC,PC12,TRACED3,,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,UART5_TX,,,,SDMMC1_CK,DCMI_D9,,EVENTOUT
|
||||
PortC,PC13,,,,,,,,,,,,,,,,EVENTOUT
|
||||
PortC,PC14,,,,,,,,,,,,,,,,EVENTOUT
|
||||
PortC,PC15,,,,,,,,,,,,,,,,EVENTOUT
|
||||
PortD,PD0,,,,,,,,,,CAN1_RX,,,FMC_D2,,,EVENTOUT
|
||||
PortD,PD1,,,,,,,,,,CAN1_TX,,,FMC_D3,,,EVENTOUT
|
||||
PortD,PD2,TRACED2,,TIM3_ETR,,,,,,UART5_RX,,,,SDMMC1_CMD,DCMI_D11,,EVENTOUT
|
||||
PortD,PD3,,,,,,SPI2_SCK/I2S2_CK,,USART2_CTS,,,,,FMC_CLK,DCMI_D5,LCD_G7,EVENTOUT
|
||||
PortD,PD4,,,,,,,,USART2_RTS,,,,,FMC_NOE,,,EVENTOUT
|
||||
PortD,PD5,,,,,,,,USART2_TX,,,,,FMC_NWE,,,EVENTOUT
|
||||
PortD,PD6,,,,,,SPI3_MOSI/I2S3_SD,SAI1_SD_A,USART2_RX,,,,,FMC_NWAIT,DCMI_D10,LCD_B2,EVENTOUT
|
||||
PortD,PD7,,,,,,,,USART2_CK,SPDIFRX_IN0,,,,FMC_NE1,,,EVENTOUT
|
||||
PortD,PD8,,,,,,,,USART3_TX,SPDIFRX_IN1,,,,FMC_D13,,,EVENTOUT
|
||||
PortD,PD9,,,,,,,,USART3_RX,,,,,FMC_D14,,,EVENTOUT
|
||||
PortD,PD10,,,,,,,,USART3_CK,,,,,FMC_D15,,LCD_B3,EVENTOUT
|
||||
PortD,PD11,,,,,I2C4_SMBA,,,USART3_CTS,,QUADSPI_BK1_IO0,SAI2_SD_A,,FMC_A16/FMC_CLE,,,EVENTOUT
|
||||
PortD,PD12,,,TIM4_CH1,LPTIM1_IN1,I2C4_SCL,,,USART3_RTS,,QUADSPI_BK1_IO1,SAI2_FS_A,,FMC_A17/FMC_ALE,,,EVENTOUT
|
||||
PortD,PD13,,,TIM4_CH2,LPTIM1_OUT,I2C4_SDA,,,,,QUADSPI_BK1_IO3,SAI2_SCK_A,,FMC_A18,,,EVENTOUT
|
||||
PortD,PD14,,,TIM4_CH3,,,,,,UART8_CTS,,,,FMC_D0,,,EVENTOUT
|
||||
PortD,PD15,,,TIM4_CH4,,,,,,UART8_RTS,,,,FMC_D1,,,EVENTOUT
|
||||
PortE,PE0,,,TIM4_ETR,LPTIM1_ETR,,,,,UART8_RX,,SAI2_MCK_A,,FMC_NBL0,DCMI_D2,,EVENTOUT
|
||||
PortE,PE1,,,,LPTIM1_IN2,,,,,UART8_TX,,,,FMC_NBL1,DCMI_D3,,EVENTOUT
|
||||
PortE,PE2,TRACECLK,,,,,SPI4_SCK,SAI1_MCLK_A,,,QUADSPI_BK1_IO2,,ETH_MII_TXD3,FMC_A23,,,EVENTOUT
|
||||
PortE,PE3,TRACED0,,,,,,SAI1_SD_B,,,,,,FMC_A19,,,EVENTOUT
|
||||
PortE,PE4,TRACED1,,,,,SPI4_NSS,SAI1_FS_A,,,,,,FMC_A20,DCMI_D4,LCD_B0,EVENTOUT
|
||||
PortE,PE5,TRACED2,,,TIM9_CH1,,SPI4_MISO,SAI1_SCK_A,,,,,,FMC_A21,DCMI_D6,LCD_G0,EVENTOUT
|
||||
PortE,PE6,TRACED3,TIM1_BKIN2,,TIM9_CH2,,SPI4_MOSI,SAI1_SD_A,,,,SAI2_MCK_B,,FMC_A22,DCMI_D7,LCD_G1,EVENTOUT
|
||||
PortE,PE7,,TIM1_ETR,,,,,,,UART7_RX,,QUADSPI_BK2_IO0,,FMC_D4,,,EVENTOUT
|
||||
PortE,PE8,,TIM1_CH1N,,,,,,,UART7_TX,,QUADSPI_BK2_IO1,,FMC_D5,,,EVENTOUT
|
||||
PortE,PE9,,TIM1_CH1,,,,,,,UART7_RTS,,QUADSPI_BK2_IO2,,FMC_D6,,,EVENTOUT
|
||||
PortE,PE10,,TIM1_CH2N,,,,,,,UART7_CTS,,QUADSPI_BK2_IO3,,FMC_D7,,,EVENTOUT
|
||||
PortE,PE11,,TIM1_CH2,,,,SPI4_NSS,,,,,SAI2_SD_B,,FMC_D8,,LCD_G3,EVENTOUT
|
||||
PortE,PE12,,TIM1_CH3N,,,,SPI4_SCK,,,,,SAI2_SCK_B,,FMC_D9,,LCD_B4,EVENTOUT
|
||||
PortE,PE13,,TIM1_CH3,,,,SPI4_MISO,,,,,SAI2_FS_B,,FMC_D10,,LCD_DE,EVENTOUT
|
||||
PortE,PE14,,TIM1_CH4,,,,SPI4_MOSI,,,,,SAI2_MCK_B,,FMC_D11,,LCD_CLK,EVENTOUT
|
||||
PortE,PE15,,TIM1_BKIN,,,,,,,,,,,FMC_D12,,LCD_R7,EVENTOUT
|
||||
PortF,PF0,,,,,I2C2_SDA,,,,,,,,FMC_A0,,,EVENTOUT
|
||||
PortF,PF1,,,,,I2C2_SCL,,,,,,,,FMC_A1,,,EVENTOUT
|
||||
PortF,PF2,,,,,I2C2_SMBA,,,,,,,,FMC_A2,,,EVENTOUT
|
||||
PortF,PF3,,,,,,,,,,,,,FMC_A3,,,EVENTOUT
|
||||
PortF,PF4,,,,,,,,,,,,,FMC_A4,,,EVENTOUT
|
||||
PortF,PF5,,,,,,,,,,,,,FMC_A5,,,EVENTOUT
|
||||
PortF,PF6,,,,TIM10_CH1,,SPI5_NSS,SAI1_SD_B,,UART7_RX,QUADSPI_BK1_IO3,,,,,,EVENTOUT
|
||||
PortF,PF7,,,,TIM11_CH1,,SPI5_SCK,SAI1_MCLK_B,,UART7_TX,QUADSPI_BK1_IO2,,,,,,EVENTOUT
|
||||
PortF,PF8,,,,,,SPI5_MISO,SAI1_SCK_B,,UART7_RTS,TIM13_CH1,QUADSPI_BK1_IO0,,,,,EVENTOUT
|
||||
PortF,PF9,,,,,,SPI5_MOSI,SAI1_FS_B,,UART7_CTS,TIM14_CH1,QUADSPI_BK1_IO1,,,,,EVENTOUT
|
||||
PortF,PF10,,,,,,,,,,,,,,DCMI_D11,LCD_DE,EVENTOUT
|
||||
PortF,PF11,,,,,,SPI5_MOSI,,,,,SAI2_SD_B,,FMC_SDNRAS,DCMI_D12,,EVENTOUT
|
||||
PortF,PF12,,,,,,,,,,,,,FMC_A6,,,EVENTOUT
|
||||
PortF,PF13,,,,,I2C4_SMBA,,,,,,,,FMC_A7,,,EVENTOUT
|
||||
PortF,PF14,,,,,I2C4_SCL,,,,,,,,FMC_A8,,,EVENTOUT
|
||||
PortF,PF15,,,,,I2C4_SDA,,,,,,,,FMC_A9,,,EVENTOUT
|
||||
PortG,PG0,,,,,,,,,,,,,FMC_A10,,,EVENTOUT
|
||||
PortG,PG1,,,,,,,,,,,,,FMC_A11,,,EVENTOUT
|
||||
PortG,PG2,,,,,,,,,,,,,FMC_A12,,,EVENTOUT
|
||||
PortG,PG3,,,,,,,,,,,,,FMC_A13,,,EVENTOUT
|
||||
PortG,PG4,,,,,,,,,,,,,FMC_A14/FMC_BA0,,,EVENTOUT
|
||||
PortG,PG5,,,,,,,,,,,,,FMC_A15/FMC_BA1,,,EVENTOUT
|
||||
PortG,PG6,,,,,,,,,,,,,,DCMI_D12,LCD_R7,EVENTOUT
|
||||
PortG,PG7,,,,,,,,,USART6_CK,,,,FMC_INT,DCMI_D13,LCD_CLK,EVENTOUT
|
||||
PortG,PG8,,,,,,SPI6_NSS,,SPDIFRX_IN2,USART6_RTS,,,ETH_PPS_OUT,FMC_SDCLK,,,EVENTOUT
|
||||
PortG,PG9,,,,,,,,SPDIFRX_IN3,USART6_RX,QUADSPI_BK2_IO2,SAI2_FS_B,,FMC_NE2/FMC_NCE,DCMI_VSYNC,,EVENTOUT
|
||||
PortG,PG10,,,,,,,,,,LCD_G3,SAI2_SD_B,,FMC_NE3,DCMI_D2,LCD_B2,EVENTOUT
|
||||
PortG,PG11,,,,,,,,SPDIFRX_IN0,,,,ETH_MII_TX_EN/ETH_RMII_TX_EN,,DCMI_D3,LCD_B3,EVENTOUT
|
||||
PortG,PG12,,,,LPTIM1_IN1,,SPI6_MISO,,SPDIFRX_IN1,USART6_RTS,LCD_B4,,,FMC_NE4,,LCD_B1,EVENTOUT
|
||||
PortG,PG13,TRACED0,,,LPTIM1_OUT,,SPI6_SCK,,,USART6_CTS,,,ETH_MII_TXD0/ETH_RMII_TXD0,FMC_A24,,LCD_R0,EVENTOUT
|
||||
PortG,PG14,TRACED1,,,LPTIM1_ETR,,SPI6_MOSI,,,USART6_TX,QUADSPI_BK2_IO3,,ETH_MII_TXD1/ETH_RMII_TXD1,FMC_A25,,LCD_B0,EVENTOUT
|
||||
PortG,PG15,,,,,,,,,USART6_CTS,,,,FMC_SDNCAS,DCMI_D13,,EVENTOUT
|
||||
PortH,PH0,,,,,,,,,,,,,,,,EVENTOUT
|
||||
PortH,PH1,,,,,,,,,,,,,,,,EVENTOUT
|
||||
PortH,PH2,,,,LPTIM1_IN2,,,,,,QUADSPI_BK2_IO0,SAI2_SCK_B,ETH_MII_CRS,FMC_SDCKE0,,LCD_R0,EVENTOUT
|
||||
PortH,PH3,,,,,,,,,,QUADSPI_BK2_IO1,SAI2_MCK_B,ETH_MII_COL,FMC_SDNE0,,LCD_R1,EVENTOUT
|
||||
PortH,PH4,,,,,I2C2_SCL,,,,,,OTG_HS_ULPI_NXT,,,,,EVENTOUT
|
||||
PortH,PH5,,,,,I2C2_SDA,SPI5_NSS,,,,,,,FMC_SDNWE,,,EVENTOUT
|
||||
PortH,PH6,,,,,I2C2_SMBA,SPI5_SCK,,,,TIM12_CH1,,ETH_MII_RXD2,FMC_SDNE1,DCMI_D8,,EVENTOUT
|
||||
PortH,PH7,,,,,I2C3_SCL,SPI5_MISO,,,,,,ETH_MII_RXD3,FMC_SDCKE1,DCMI_D9,,EVENTOUT
|
||||
PortH,PH8,,,,,I2C3_SDA,,,,,,,,FMC_D16,DCMI_HSYNC,LCD_R2,EVENTOUT
|
||||
PortH,PH9,,,,,I2C3_SMBA,,,,,TIM12_CH2,,,FMC_D17,DCMI_D0,LCD_R3,EVENTOUT
|
||||
PortH,PH10,,,TIM5_CH1,,I2C4_SMBA,,,,,,,,FMC_D18,DCMI_D1,LCD_R4,EVENTOUT
|
||||
PortH,PH11,,,TIM5_CH2,,I2C4_SCL,,,,,,,,FMC_D19,DCMI_D2,LCD_R5,EVENTOUT
|
||||
PortH,PH12,,,TIM5_CH3,,I2C4_SDA,,,,,,,,FMC_D20,DCMI_D3,LCD_R6,EVENTOUT
|
||||
PortH,PH13,,,,TIM8_CH1N,,,,,,CAN1_TX,,,FMC_D21,,LCD_G2,EVENTOUT
|
||||
PortH,PH14,,,,TIM8_CH2N,,,,,,,,,FMC_D22,DCMI_D4,LCD_G3,EVENTOUT
|
||||
PortH,PH15,,,,TIM8_CH3N,,,,,,,,,FMC_D23,DCMI_D11,LCD_G4,EVENTOUT
|
||||
PortI,PI0,,,TIM5_CH4,,,SPI2_NSS/I2S2_WS,,,,,,,FMC_D24,DCMI_D13,LCD_G5,EVENTOUT
|
||||
PortI,PI1,,,,TIM8_BKIN2,,SPI2_SCK/I2S2_CK,,,,,,,FMC_D25,DCMI_D8,LCD_G6,EVENTOUT
|
||||
PortI,PI2,,,,TIM8_CH4,,SPI2_MISO,,,,,,,FMC_D26,DCMI_D9,LCD_G7,EVENTOUT
|
||||
PortI,PI3,,,,TIM8_ETR,,SPI2_MOSI/I2S2_SD,,,,,,,FMC_D27,DCMI_D10,,EVENTOUT
|
||||
PortI,PI4,,,,TIM8_BKIN,,,,,,,SAI2_MCK_A,,FMC_NBL2,DCMI_D5,LCD_B4,EVENTOUT
|
||||
PortI,PI5,,,,TIM8_CH1,,,,,,,SAI2_SCK_A,,FMC_NBL3,DCMI_VSYNC,LCD_B5,EVENTOUT
|
||||
PortI,PI6,,,,TIM8_CH2,,,,,,,SAI2_SD_A,,FMC_D28,DCMI_D6,LCD_B6,EVENTOUT
|
||||
PortI,PI7,,,,TIM8_CH3,,,,,,,SAI2_FS_A,,FMC_D29,DCMI_D7,LCD_B7,EVENTOUT
|
||||
PortI,PI8,,,,,,,,,,,,,,,,EVENTOUT
|
||||
PortI,PI9,,,,,,,,,,CAN1_RX,,,FMC_D30,,LCD_VSYNC,EVENTOUT
|
||||
PortI,PI10,,,,,,,,,,,,ETH_MII_RX_ER,FMC_D31,,LCD_HSYNC,EVENTOUT
|
||||
PortI,PI11,,,,,,,,,,,OTG_HS_ULPI_DIR,,,,,EVENTOUT
|
||||
PortI,PI12,,,,,,,,,,,,,,,LCD_HSYNC,EVENTOUT
|
||||
PortI,PI13,,,,,,,,,,,,,,,LCD_VSYNC,EVENTOUT
|
||||
PortI,PI14,,,,,,,,,,,,,,,LCD_CLK,EVENTOUT
|
||||
PortI,PI15,,,,,,,,,,,,,,,LCD_R0,EVENTOUT
|
||||
PortJ,PJ0,,,,,,,,,,,,,,,LCD_R1,EVENTOUT
|
||||
PortJ,PJ1,,,,,,,,,,,,,,,LCD_R2,EVENTOUT
|
||||
PortJ,PJ2,,,,,,,,,,,,,,,LCD_R3,EVENTOUT
|
||||
PortJ,PJ3,,,,,,,,,,,,,,,LCD_R4,EVENTOUT
|
||||
PortJ,PJ4,,,,,,,,,,,,,,,LCD_R5,EVENTOUT
|
||||
PortJ,PJ5,,,,,,,,,,,,,,,LCD_R6,EVENTOUT
|
||||
PortJ,PJ6,,,,,,,,,,,,,,,LCD_R7,EVENTOUT
|
||||
PortJ,PJ7,,,,,,,,,,,,,,,LCD_G0,EVENTOUT
|
||||
PortJ,PJ8,,,,,,,,,,,,,,,LCD_G1,EVENTOUT
|
||||
PortJ,PJ9,,,,,,,,,,,,,,,LCD_G2,EVENTOUT
|
||||
PortJ,PJ10,,,,,,,,,,,,,,,LCD_G3,EVENTOUT
|
||||
PortJ,PJ11,,,,,,,,,,,,,,,LCD_G4,EVENTOUT
|
||||
PortJ,PJ12,,,,,,,,,,,,,,,LCD_B0,EVENTOUT
|
||||
PortJ,PJ13,,,,,,,,,,,,,,,LCD_B1,EVENTOUT
|
||||
PortJ,PJ14,,,,,,,,,,,,,,,LCD_B2,EVENTOUT
|
||||
PortJ,PJ15,,,,,,,,,,,,,,,LCD_B3,EVENTOUT
|
||||
PortK,PK0,,,,,,,,,,,,,,,LCD_G5,EVENTOUT
|
||||
PortK,PK1,,,,,,,,,,,,,,,LCD_G6,EVENTOUT
|
||||
PortK,PK2,,,,,,,,,,,,,,,LCD_G7,EVENTOUT
|
||||
PortK,PK3,,,,,,,,,,,,,,,LCD_B4,EVENTOUT
|
||||
PortK,PK4,,,,,,,,,,,,,,,LCD_B5,EVENTOUT
|
||||
PortK,PK5,,,,,,,,,,,,,,,LCD_B6,EVENTOUT
|
||||
PortK,PK6,,,,,,,,,,,,,,,LCD_B7,EVENTOUT
|
||||
PortK,PK7,,,,,,,,,,,,,,,LCD_DE,EVENTOUT
|
||||
|
||||
|
|
|
@ -187,21 +187,41 @@ void extint_enable(uint line) {
|
|||
if (line >= EXTI_NUM_VECTORS) {
|
||||
return;
|
||||
}
|
||||
#if defined(STM32F7)
|
||||
// The Cortex-M7 doesn't have bitband support.
|
||||
mp_uint_t irq_state = disable_irq();
|
||||
if (pyb_extint_mode[line] == EXTI_Mode_Interrupt) {
|
||||
EXTI->IMR |= (1 << line);
|
||||
} else {
|
||||
EXTI->EMR |= (1 << line);
|
||||
}
|
||||
enable_irq(irq_state);
|
||||
#else
|
||||
// Since manipulating IMR/EMR is a read-modify-write, and we want this to
|
||||
// be atomic, we use the bit-band area to just affect the bit we're
|
||||
// interested in.
|
||||
EXTI_MODE_BB(pyb_extint_mode[line], line) = 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
void extint_disable(uint line) {
|
||||
if (line >= EXTI_NUM_VECTORS) {
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(STM32F7)
|
||||
// The Cortex-M7 doesn't have bitband support.
|
||||
mp_uint_t irq_state = disable_irq();
|
||||
EXTI->IMR &= ~(1 << line);
|
||||
EXTI->EMR &= ~(1 << line);
|
||||
enable_irq(irq_state);
|
||||
#else
|
||||
// Since manipulating IMR/EMR is a read-modify-write, and we want this to
|
||||
// be atomic, we use the bit-band area to just affect the bit we're
|
||||
// interested in.
|
||||
EXTI_MODE_BB(EXTI_Mode_Interrupt, line) = 0;
|
||||
EXTI_MODE_BB(EXTI_Mode_Event, line) = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
void extint_swint(uint line) {
|
||||
|
|
|
|||
|
|
@ -36,6 +36,9 @@
|
|||
#define EXTI_USB_OTG_HS_WAKEUP (20)
|
||||
#define EXTI_RTC_TIMESTAMP (21)
|
||||
#define EXTI_RTC_WAKEUP (22)
|
||||
#if defined(STM32F7)
|
||||
#define EXTI_LPTIM1_ASYNC_EVENT (23)
|
||||
#endif
|
||||
|
||||
#define EXTI_NUM_VECTORS (PYB_EXTI_NUM_VECTORS)
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,12 @@
|
|||
|
||||
#include "flash.h"
|
||||
|
||||
#if defined(STM32F7)
|
||||
// FLASH_FLAG_PGSERR (Programming Sequence Error) was renamed to
|
||||
// FLASH_FLAG_ERSERR (Erasing Sequence Error) in STM32F7
|
||||
#define FLASH_FLAG_PGSERR FLASH_FLAG_ERSERR
|
||||
#endif
|
||||
|
||||
/* Base address of the Flash sectors */
|
||||
#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
|
||||
|
|
@ -92,7 +98,7 @@ void flash_erase(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32)
|
|||
|
||||
// Clear pending flags (if any)
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR|FLASH_FLAG_PGSERR);
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
|
||||
|
||||
// erase the sector(s)
|
||||
FLASH_EraseInitTypeDef EraseInitStruct;
|
||||
|
|
|
|||
|
|
@ -37,6 +37,10 @@
|
|||
#include "i2c.h"
|
||||
#include MICROPY_HAL_H
|
||||
|
||||
#if !defined(STM32F7)
|
||||
// The STM32F7 has Timing, where the F4 has ClockSpeed and DutyCycle, so we
|
||||
// need to figure that out before we can enable i2c
|
||||
|
||||
/// \moduleref pyb
|
||||
/// \class I2C - a two-wire serial protocol
|
||||
///
|
||||
|
|
@ -748,3 +752,5 @@ const mp_obj_type_t pyb_i2c_type = {
|
|||
.make_new = pyb_i2c_make_new,
|
||||
.locals_dict = (mp_obj_t)&pyb_i2c_locals_dict,
|
||||
};
|
||||
|
||||
#endif // STM32F7
|
||||
|
|
|
|||
|
|
@ -268,9 +268,20 @@ int main(void) {
|
|||
__GPIOC_CLK_ENABLE();
|
||||
__GPIOD_CLK_ENABLE();
|
||||
|
||||
#if defined(__HAL_RCC_DTCMRAMEN_CLK_ENABLE)
|
||||
// The STM32F746 doesn't really have CCM memory, but it does have DTCM,
|
||||
// which behaves more or less like normal SRAM.
|
||||
__HAL_RCC_DTCMRAMEN_CLK_ENABLE();
|
||||
#else
|
||||
// enable the CCM RAM
|
||||
__CCMDATARAMEN_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(MICROPY_BOARD_EARLY_INIT)
|
||||
MICROPY_BOARD_EARLY_INIT();
|
||||
#endif
|
||||
|
||||
//TODO - Move the following to a board_init.c file for the NETDUINO
|
||||
#if 0
|
||||
#if defined(NETDUINO_PLUS_2)
|
||||
{
|
||||
|
|
@ -388,13 +399,14 @@ soft_reset:
|
|||
timer_init0();
|
||||
uart_init0();
|
||||
|
||||
// Change #if 0 to #if 1 if you want REPL on UART_6 (or another uart)
|
||||
// as well as on USB VCP
|
||||
#if 0
|
||||
// Define MICROPY_HW_UART_REPL to be PYB_UART_6 and define
|
||||
// MICROPY_HW_UART_REPL_BAUD in your mpconfigboard.h file if you want a
|
||||
// REPL on a hardware UART as well as on USB VCP
|
||||
#if defined(MICROPY_HW_UART_REPL)
|
||||
{
|
||||
mp_obj_t args[2] = {
|
||||
MP_OBJ_NEW_SMALL_INT(PYB_UART_6),
|
||||
MP_OBJ_NEW_SMALL_INT(115200),
|
||||
MP_OBJ_NEW_SMALL_INT(MICROPY_HW_UART_REPL),
|
||||
MP_OBJ_NEW_SMALL_INT(MICROPY_HW_UART_REPL_BAUD),
|
||||
};
|
||||
MP_STATE_PORT(pyb_stdio_uart) = pyb_uart_type.make_new((mp_obj_t)&pyb_uart_type, MP_ARRAY_SIZE(args), 0, args);
|
||||
}
|
||||
|
|
@ -410,8 +422,10 @@ soft_reset:
|
|||
rng_init0();
|
||||
#endif
|
||||
|
||||
#if !defined(STM32F7) // Temp hack
|
||||
i2c_init0();
|
||||
spi_init0();
|
||||
#endif
|
||||
pyb_usb_init0();
|
||||
|
||||
// Initialise the local flash filesystem.
|
||||
|
|
|
|||
|
|
@ -74,6 +74,14 @@ STATIC NORETURN mp_obj_t pyb_bootloader(void) {
|
|||
HAL_RCC_DeInit();
|
||||
HAL_DeInit();
|
||||
|
||||
#if defined(STM32F7)
|
||||
// arm-none-eabi-gcc 4.9.0 does not correctly inline this
|
||||
// MSP function, so we write it out explicitly here.
|
||||
//__set_MSP(*((uint32_t*) 0x1FF00000));
|
||||
__ASM volatile ("movw r3, #0x0000\nmovt r3, #0x1FF0\nldr r3, [r3, #0]\nMSR msp, r3\n" : : : "r3", "sp");
|
||||
|
||||
((void (*)(void)) *((uint32_t*) 0x1FF00004))();
|
||||
#else
|
||||
__HAL_REMAPMEMORY_SYSTEMFLASH();
|
||||
|
||||
// arm-none-eabi-gcc 4.9.0 does not correctly inline this
|
||||
|
|
@ -82,6 +90,7 @@ STATIC NORETURN mp_obj_t pyb_bootloader(void) {
|
|||
__ASM volatile ("movs r3, #0\nldr r3, [r3, #0]\nMSR msp, r3\n" : : : "r3", "sp");
|
||||
|
||||
((void (*)(void)) *((uint32_t*) 0x00000004))();
|
||||
#endif
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
|
@ -453,6 +462,9 @@ MP_DEFINE_CONST_FUN_OBJ_0(pyb_stop_obj, pyb_stop);
|
|||
|
||||
/// \function standby()
|
||||
STATIC mp_obj_t pyb_standby(void) {
|
||||
#if defined(STM32F7)
|
||||
printf("pyb.standby not supported yet\n");
|
||||
#else
|
||||
// We need to clear the PWR wake-up-flag before entering standby, since
|
||||
// the flag may have been set by a previous wake-up event. Furthermore,
|
||||
// we need to disable the wake-up sources while clearing this flag, so
|
||||
|
|
@ -481,7 +493,7 @@ STATIC mp_obj_t pyb_standby(void) {
|
|||
// enter standby mode
|
||||
HAL_PWR_EnterSTANDBYMode();
|
||||
// we never return; MCU is reset on exit from standby
|
||||
|
||||
#endif
|
||||
return mp_const_none;
|
||||
}
|
||||
MP_DEFINE_CONST_FUN_OBJ_0(pyb_standby_obj, pyb_standby);
|
||||
|
|
@ -577,8 +589,10 @@ STATIC const mp_map_elem_t pyb_module_globals_table[] = {
|
|||
#if defined(MICROPY_HW_LED1)
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_LED), (mp_obj_t)&pyb_led_type },
|
||||
#endif
|
||||
#if !defined(STM32F7) // Temp hack
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_I2C), (mp_obj_t)&pyb_i2c_type },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SPI), (mp_obj_t)&pyb_spi_type },
|
||||
#endif
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&pyb_uart_type },
|
||||
#if MICROPY_HW_ENABLE_CAN
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CAN), (mp_obj_t)&pyb_can_type },
|
||||
|
|
|
|||
|
|
@ -135,7 +135,11 @@ extern const struct _mp_obj_module_t mp_module_network;
|
|||
{ MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_stm), (mp_obj_t)&stm_module }, \
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define PYB_EXTI_NUM_VECTORS (24)
|
||||
#else
|
||||
#define PYB_EXTI_NUM_VECTORS (23)
|
||||
#endif
|
||||
|
||||
#define MP_STATE_PORT MP_STATE_VM
|
||||
|
||||
|
|
|
|||
|
|
@ -3,8 +3,13 @@
|
|||
|
||||
// Basic GPIO functions
|
||||
#define GPIO_read_pin(gpio, pin) (((gpio)->IDR >> (pin)) & 1)
|
||||
#if defined(STM32F7)
|
||||
#define GPIO_set_pin(gpio, pin_mask) (((gpio)->BSRR) = (pin_mask))
|
||||
#define GPIO_clear_pin(gpio, pin_mask) (((gpio)->BSRR) = ((pin_mask) << 16))
|
||||
#else
|
||||
#define GPIO_set_pin(gpio, pin_mask) (((gpio)->BSRRL) = (pin_mask))
|
||||
#define GPIO_clear_pin(gpio, pin_mask) (((gpio)->BSRRH) = (pin_mask))
|
||||
#endif
|
||||
#define GPIO_read_output_pin(gpio, pin) (((gpio)->ODR >> (pin)) & 1)
|
||||
|
||||
extern const byte mp_hal_status_to_errno_table[4];
|
||||
|
|
|
|||
|
|
@ -390,6 +390,9 @@ STATIC mp_obj_t pin_obj_init_helper(const pin_obj_t *self, mp_uint_t n_args, con
|
|||
#ifdef __GPIOJ_CLK_ENABLE
|
||||
case PORT_J: __GPIOJ_CLK_ENABLE(); break;
|
||||
#endif
|
||||
#ifdef __GPIOK_CLK_ENABLE
|
||||
case PORT_K: __GPIOK_CLK_ENABLE(); break;
|
||||
#endif
|
||||
}
|
||||
|
||||
// configure the GPIO as requested
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ enum {
|
|||
PORT_H,
|
||||
PORT_I,
|
||||
PORT_J,
|
||||
PORT_K,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
|
|||
|
|
@ -62,6 +62,7 @@ int DEBUG_printf(const char *fmt, ...) {
|
|||
#endif
|
||||
|
||||
// need this because gcc optimises printf("%c", c) -> putchar(c), and printf("a") -> putchar('a')
|
||||
#undef putchar // Some stdlibs have a #define for putchar
|
||||
int putchar(int c) {
|
||||
char chr = c;
|
||||
mp_hal_stdout_tx_strn_cooked(&chr, 1);
|
||||
|
|
|
|||
|
|
@ -37,6 +37,10 @@
|
|||
#include "spi.h"
|
||||
#include MICROPY_HAL_H
|
||||
|
||||
#if !defined(STM32F7)
|
||||
// The STM32F7 has the SPI pins mapped differently. Need to figure this out
|
||||
// before enabling SPI for the F7
|
||||
|
||||
/// \moduleref pyb
|
||||
/// \class SPI - a master-driven serial protocol
|
||||
///
|
||||
|
|
@ -665,3 +669,5 @@ const mp_obj_type_t pyb_spi_type = {
|
|||
.make_new = pyb_spi_make_new,
|
||||
.locals_dict = (mp_obj_t)&pyb_spi_locals_dict,
|
||||
};
|
||||
|
||||
#endif // STM32F7
|
||||
|
|
|
|||
|
|
@ -1,17 +1,17 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f407xx.s
|
||||
* @file startup_stm32.S
|
||||
* @author MCD Application Team
|
||||
* @version V2.0.0
|
||||
* @date 18-February-2014
|
||||
* @brief STM32F407xx Devices vector table for Atollic TrueSTUDIO toolchain.
|
||||
* @brief STM32Fxxxxx Devices vector table for Atollic TrueSTUDIO toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* After Reset the Cortex-M4/M7 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -44,7 +44,11 @@
|
|||
*/
|
||||
|
||||
.syntax unified
|
||||
#if STM32F7
|
||||
.cpu cortex-m7
|
||||
#else
|
||||
.cpu cortex-m4
|
||||
#endif
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
|
|
@ -107,7 +111,7 @@ LoopFillZerobss:
|
|||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
/* Call the clock system initialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/*bl __libc_init_array*/
|
||||
|
|
@ -130,7 +134,7 @@ Infinite_Loop:
|
|||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* The minimal vector table for a Cortex M4/M7. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
|
|
@ -207,8 +211,13 @@ g_pfnVectors:
|
|||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
#if defined(STM32F7)
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
#else
|
||||
.word FSMC_IRQHandler /* FSMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
#endif
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
|
|
@ -242,6 +251,24 @@ g_pfnVectors:
|
|||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
|
||||
#if defined(STM32F7)
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word SAI2_IRQHandler /* SAI2 */
|
||||
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
|
|
@ -421,11 +448,19 @@ g_pfnVectors:
|
|||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
#if defined(STM32F7)
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
#else
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
#endif
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
|
@ -519,5 +554,48 @@ g_pfnVectors:
|
|||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
#if defined(STM32F7)
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
#endif
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
|
|||
|
|
@ -55,6 +55,15 @@ STATIC byte flash_cache_mem[0x4000] __attribute__((aligned(4))); // 16k
|
|||
#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1
|
||||
#define FLASH_MEM_SEG1_NUM_BLOCKS (128) // sectors 1,2,3,4: 16k+16k+16k+16k(of 64k)=64k
|
||||
|
||||
#elif defined(STM32F746xx)
|
||||
|
||||
// The STM32F746 doesn't really have CCRAM, so we use the 64K DTCM for this.
|
||||
|
||||
#define CACHE_MEM_START_ADDR (0x20000000) // DTCM data RAM, 64k
|
||||
#define FLASH_SECTOR_SIZE_MAX (0x10000) // 64k max, size of DTCM
|
||||
#define FLASH_MEM_SEG1_START_ADDR (0x08004000) // sector 1
|
||||
#define FLASH_MEM_SEG1_NUM_BLOCKS (224) // sectors 1,2,3,4: 16k+16k+16k+64k=112k
|
||||
|
||||
#else
|
||||
#error "no storage support for this MCU"
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -28,26 +28,22 @@
|
|||
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @file system_stm32.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.0.1
|
||||
* @date 26-February-2014
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* @brief CMSIS Cortex-M4/M7 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f4xx.s" file.
|
||||
* the "startup_stm32.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
@ -83,11 +79,11 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
/** @addtogroup stm32fxxx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Includes
|
||||
/** @addtogroup STM32Fxxx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -100,7 +96,7 @@ void __fatal_error(const char *msg);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
||||
/** @addtogroup STM32Fxxx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -108,7 +104,7 @@ void __fatal_error(const char *msg);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Defines
|
||||
/** @addtogroup STM32Fxxx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -125,7 +121,7 @@ void __fatal_error(const char *msg);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Macros
|
||||
/** @addtogroup STM32Fxxx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -133,7 +129,7 @@ void __fatal_error(const char *msg);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Variables
|
||||
/** @addtogroup STM32Fxxx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
|
|
@ -150,7 +146,7 @@ void __fatal_error(const char *msg);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
||||
/** @addtogroup STM32Fxxx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -158,7 +154,7 @@ void __fatal_error(const char *msg);
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Functions
|
||||
/** @addtogroup STM32Fxxx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
|
@ -196,7 +192,7 @@ void SystemInit(void)
|
|||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
|
@ -205,94 +201,6 @@ void SystemInit(void)
|
|||
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
|
||||
* depends on the application requirements), user has to ensure that HSE_VALUE
|
||||
* is same as the real frequency of the crystal used. Otherwise, this function
|
||||
* may have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#if 0
|
||||
// dpgeorge: I think this function is obsolete now with the new HAL library.
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief System Clock Configuration
|
||||
|
|
@ -375,6 +283,14 @@ void SystemClock_Config(void)
|
|||
__fatal_error("HAL_RCC_OscConfig");
|
||||
}
|
||||
|
||||
#if defined(STM32F7)
|
||||
/* Activate the OverDrive to reach the 200 MHz Frequency */
|
||||
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
|
||||
{
|
||||
__fatal_error("HAL_PWREx_EnableOverDrive");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
|
||||
clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
|
|
@ -382,7 +298,12 @@ void SystemClock_Config(void)
|
|||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
|
||||
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
|
||||
|
||||
#if !defined(MICROPY_HW_FLASH_LATENCY)
|
||||
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_5
|
||||
#endif
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, MICROPY_HW_FLASH_LATENCY) != HAL_OK)
|
||||
{
|
||||
__fatal_error("HAL_RCC_ClockConfig");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -36,6 +36,8 @@
|
|||
#include "pybioctl.h"
|
||||
#include MICROPY_HAL_H
|
||||
|
||||
//TODO: Add UART7/8 support for STM32F7
|
||||
|
||||
/// \moduleref pyb
|
||||
/// \class UART - duplex serial communication bus
|
||||
///
|
||||
|
|
@ -297,7 +299,11 @@ int uart_rx_char(pyb_uart_obj_t *self) {
|
|||
return data;
|
||||
} else {
|
||||
// no buffering
|
||||
#if defined(STM32F7)
|
||||
return self->uart.Instance->RDR & self->char_mask;
|
||||
#else
|
||||
return self->uart.Instance->DR & self->char_mask;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -331,7 +337,11 @@ void uart_irq_handler(mp_uint_t uart_id) {
|
|||
}
|
||||
|
||||
if (__HAL_UART_GET_FLAG(&self->uart, UART_FLAG_RXNE) != RESET) {
|
||||
#if defined(STM32F7)
|
||||
int data = self->uart.Instance->RDR; // clears UART_FLAG_RXNE
|
||||
#else
|
||||
int data = self->uart.Instance->DR; // clears UART_FLAG_RXNE
|
||||
#endif
|
||||
data &= self->char_mask;
|
||||
if (self->read_buf_len != 0) {
|
||||
uint16_t next_head = (self->read_buf_head + 1) % self->read_buf_len;
|
||||
|
|
@ -687,7 +697,11 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_readchar_obj, pyb_uart_readchar);
|
|||
// uart.sendbreak()
|
||||
STATIC mp_obj_t pyb_uart_sendbreak(mp_obj_t self_in) {
|
||||
pyb_uart_obj_t *self = self_in;
|
||||
#if defined(STM32F7)
|
||||
self->uart.Instance->RQR = USART_RQR_SBKRQ; // write-only register
|
||||
#else
|
||||
self->uart.Instance->CR1 |= USART_CR1_SBK;
|
||||
#endif
|
||||
return mp_const_none;
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_sendbreak_obj, pyb_uart_sendbreak);
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue