/* READ COMMENT ABOVE. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+ #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+ #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_PREEMPTION
+ #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+ #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+ #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+ #error Missing definition: configUSE_CO_ROUTINES must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+ #error Missing definition: INCLUDE_vTaskPrioritySet must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+ #error Missing definition: INCLUDE_uxTaskPriorityGet must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+ #error Missing definition: INCLUDE_vTaskDelete must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+ #error Missing definition: INCLUDE_vTaskSuspend must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskDelayUntil
+ #error Missing definition: INCLUDE_vTaskDelayUntil must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+ #error Missing definition: INCLUDE_vTaskDelay must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+ #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+ #ifndef configMAX_CO_ROUTINE_PRIORITIES
+ #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+ #endif
+#endif
+
+#ifndef configMAX_PRIORITIES
+ #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+ #define INCLUDE_xTaskGetIdleTaskHandle 0
+#endif
+
+#ifndef INCLUDE_xTimerGetTimerDaemonTaskHandle
+ #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+ #define INCLUDE_xQueueGetMutexHolder 0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+ #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_pcTaskGetTaskName
+ #define INCLUDE_pcTaskGetTaskName 0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+ #define configUSE_APPLICATION_TASK_TAG 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+ #define INCLUDE_uxTaskGetStackHighWaterMark 0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+ #define INCLUDE_eTaskGetState 0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+ #define configUSE_RECURSIVE_MUTEXES 0
+#endif
+
+#ifndef configUSE_MUTEXES
+ #define configUSE_MUTEXES 0
+#endif
+
+#ifndef configUSE_TIMERS
+ #define configUSE_TIMERS 0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+ #define configUSE_COUNTING_SEMAPHORES 0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+ #define configUSE_ALTERNATIVE_API 0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+ #define portCRITICAL_NESTING_IN_TCB 0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+ #define configMAX_TASK_NAME_LEN 16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+ #define configIDLE_SHOULD_YIELD 1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+ #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+ #define INCLUDE_xTaskResumeFromISR 1
+#endif
+
+#ifndef INCLUDE_xEventGroupSetBitFromISR
+ #define INCLUDE_xEventGroupSetBitFromISR 0
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+ #define INCLUDE_xTimerPendFunctionCall 0
+#endif
+
+#ifndef configASSERT
+ #define configASSERT( x )
+ #define configASSERT_DEFINED 0
+#else
+ #define configASSERT_DEFINED 1
+#endif
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+ #ifndef configTIMER_TASK_PRIORITY
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+ #endif /* configTIMER_TASK_PRIORITY */
+
+ #ifndef configTIMER_QUEUE_LENGTH
+ #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+ #endif /* configTIMER_QUEUE_LENGTH */
+
+ #ifndef configTIMER_TASK_STACK_DEPTH
+ #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+ #endif /* configTIMER_TASK_STACK_DEPTH */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+ #define INCLUDE_xTaskGetSchedulerState 0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+ #define INCLUDE_xTaskGetCurrentTaskHandle 0
+#endif
+
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+ #define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+ #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#endif
+
+#ifndef portCLEAN_UP_TCB
+ #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+ #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+ #define portSETUP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+ #define configQUEUE_REGISTRY_SIZE 0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+ #define vQueueAddToRegistry( xQueue, pcName )
+ #define vQueueUnregisterQueue( xQueue )
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+ #define portPOINTER_SIZE_TYPE uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+ /* Used to perform any necessary initialisation - for example, open a file
+ into which trace is to be written. */
+ #define traceSTART()
+#endif
+
+#ifndef traceEND
+ /* Use to close a trace, for example close a file into which trace has been
+ written. */
+ #define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+ /* Called after a task has been selected to run. pxCurrentTCB holds a pointer
+ to the task control block of the selected task. */
+ #define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+ /* Called before stepping the tick count after waking from tickless idle
+ sleep. */
+ #define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+ /* Called immediately before entering tickless idle. */
+ #define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef traceLOW_POWER_IDLE_END
+ /* Called when returning to the Idle task after a tickless idle. */
+ #define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+ /* Called before a task has been selected to run. pxCurrentTCB holds a pointer
+ to the task control block of the task being switched out. */
+ #define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+ /* Called when a task attempts to take a mutex that is already held by a
+ lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task
+ that holds the mutex. uxInheritedPriority is the priority the mutex holder
+ will inherit (the priority of the task that is attempting to obtain the
+ muted. */
+ #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+ /* Called when a task releases a mutex, the holding of which had resulted in
+ the task inheriting the priority of a higher priority task.
+ pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+ mutex. uxOriginalPriority is the task's configured (base) priority. */
+ #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+ /* Task is about to block because it cannot read from a
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore
+ upon which the read was attempted. pxCurrentTCB points to the TCB of the
+ task that attempted the read. */
+ #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+ /* Task is about to block because it cannot write to a
+ queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore
+ upon which the write was attempted. pxCurrentTCB points to the TCB of the
+ task that attempted the write. */
+ #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+ #define configCHECK_FOR_STACK_OVERFLOW 0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+ #define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceQUEUE_CREATE
+ #define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+ #define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+ #define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+ #define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+ #define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+ #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+ #define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+ #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+ #define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+ #define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SEND
+ #define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+ #define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+ #define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+ #define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+ #define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+ #define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+ #define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+ #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+ #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+ #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+ #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+ #define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+ #define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+ #define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+ #define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+ #define traceTASK_DELAY_UNTIL()
+#endif
+
+#ifndef traceTASK_DELAY
+ #define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+ #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+ #define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+ #define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+ #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+ #define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+ #define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+ #define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+ #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+ #define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+ #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+ #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+ #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+ #define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+ #define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+ #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+ #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+ #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+ #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+ #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+ #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+ #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+ #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+ #define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+ #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+ #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+ #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+ #define configGENERATE_RUN_TIME_STATS 0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+ #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+ #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+ #ifndef portGET_RUN_TIME_COUNTER_VALUE
+ #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+ #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information.
+ #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+ #endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+ #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+ #define configUSE_MALLOC_FAILED_HOOK 0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+ #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+ #define portYIELD_WITHIN_API portYIELD
+#endif
+
+#ifndef pvPortMallocAligned
+ #define pvPortMallocAligned( x, puxStackBuffer ) ( ( ( puxStackBuffer ) == NULL ) ? ( pvPortMalloc( ( x ) ) ) : ( puxStackBuffer ) )
+#endif
+
+#ifndef vPortFreeAligned
+ #define vPortFreeAligned( pvBlockToFree ) vPortFree( pvBlockToFree )
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+ #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+ #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+ #define configUSE_TICKLESS_IDLE 0
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+ #define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+ #define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+ #define configUSE_QUEUE_SETS 0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+ #define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef configUSE_TIME_SLICING
+ #define configUSE_TIME_SLICING 1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+ #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
+#endif
+
+#ifndef configUSE_NEWLIB_REENTRANT
+ #define configUSE_NEWLIB_REENTRANT 0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+ #define configUSE_STATS_FORMATTING_FUNCTIONS 0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+ #define configUSE_TRACE_FACILITY 0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+ #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+ #define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#endif
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+ #define configENABLE_BACKWARD_COMPATIBILITY 1
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+ #define eTaskStateGet eTaskGetState
+ #define portTickType TickType_t
+ #define xTaskHandle TaskHandle_t
+ #define xQueueHandle QueueHandle_t
+ #define xSemaphoreHandle SemaphoreHandle_t
+ #define xQueueSetHandle QueueSetHandle_t
+ #define xQueueSetMemberHandle QueueSetMemberHandle_t
+ #define xTimeOutType TimeOut_t
+ #define xMemoryRegion MemoryRegion_t
+ #define xTaskParameters TaskParameters_t
+ #define xTaskStatusType TaskStatus_t
+ #define xTimerHandle TimerHandle_t
+ #define xCoRoutineHandle CoRoutineHandle_t
+ #define pdTASK_HOOK_CODE TaskHookFunction_t
+ #define portTICK_RATE_MS portTICK_PERIOD_MS
+
+ /* Backward compatibility within the scheduler code only - these definitions
+ are not really required but are included for completeness. */
+ #define tmrTIMER_CALLBACK TimerCallbackFunction_t
+ #define pdTASK_CODE TaskFunction_t
+ #define xListItem ListItem_t
+ #define xList List_t
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INC_FREERTOS_H */
+
diff --git a/cc3200/FreeRTOS/Source/include/StackMacros.h b/cc3200/FreeRTOS/Source/include/StackMacros.h
new file mode 100644
index 0000000000..c7cfb2869d
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/StackMacros.h
@@ -0,0 +1,180 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten. Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( configCHECK_FOR_STACK_OVERFLOW == 0 )
+
+ /* FreeRTOSConfig.h is not set to check for stack overflows. */
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW()
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 0 */
+/*-----------------------------------------------------------*/
+
+#if( configCHECK_FOR_STACK_OVERFLOW == 1 )
+
+ /* FreeRTOSConfig.h is only set to use the first method of
+ overflow checking. */
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW()
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH < 0 ) )
+
+ /* Only the current stack state is to be checked. */
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \
+ { \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 0 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 0 ) && ( portSTACK_GROWTH > 0 ) )
+
+ /* Only the current stack state is to be checked. */
+ #define taskFIRST_CHECK_FOR_STACK_OVERFLOW() \
+ { \
+ \
+ /* Is the currently saved stack pointer within the stack limit? */ \
+ if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \
+ { \
+ static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+ \
+ \
+ /* Has the extremity of the task stack ever been written over? */ \
+ if( memcmp( ( void * ) pxCurrentTCB->pxStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+ #define taskSECOND_CHECK_FOR_STACK_OVERFLOW() \
+ { \
+ int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \
+ static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
+ tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+ \
+ \
+ pcEndOfStack -= sizeof( ucExpectedStackBytes ); \
+ \
+ /* Has the extremity of the task stack ever been written over? */ \
+ if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
+ { \
+ vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+ } \
+ }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#endif /* STACK_MACROS_H */
+
diff --git a/cc3200/FreeRTOS/Source/include/croutine.h b/cc3200/FreeRTOS/Source/include/croutine.h
new file mode 100644
index 0000000000..e9a86d0006
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/croutine.h
@@ -0,0 +1,758 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Used to hide the implementation of the co-routine control block. The
+control block structure however has to be included in the header due to
+the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+ crCOROUTINE_CODE pxCoRoutineFunction;
+ ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */
+ ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */
+ UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */
+ UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+ uint16_t uxState; /*< Used internally by the co-routine implementation. */
+} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ *
+ BaseType_t xCoRoutineCreate(
+ crCOROUTINE_CODE pxCoRoutineCode,
+ UBaseType_t uxPriority,
+ UBaseType_t uxIndex
+ );
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ * the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function. See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // This co-routine just delays for a fixed period, then toggles
+ // an LED. Two co-routines are created using this function, so
+ // the uxIndex parameter is used to tell the co-routine which
+ // LED to flash and how int32_t to delay. This assumes xQueue has
+ // already been created.
+ vParTestToggleLED( cLedToFlash[ uxIndex ] );
+ crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+ // Create two co-routines at priority 0. The first is given index 0
+ // so (from the code above) toggles LED 5 every 200 ticks. The second
+ // is given index 1 so toggles LED 6 every 400 ticks.
+ for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+ {
+ xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+ }
+ }
+
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ *
+ void vCoRoutineSchedule( void );
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run. The co-routine will execute until it either blocks, yields or is
+ * preempted by a task. Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+ vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+ for( ;; )
+ {
+ vCoRoutineSchedule();
+ }
+ }
+
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ *
+ crSTART( CoRoutineHandle_t xHandle );
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Co-routine functionality goes here.
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ *
+ crEND();
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Co-routine functionality goes here.
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only. The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function. This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay. This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for. The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+ // Must start every co-routine with a call to crSTART();
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Delay for 200ms.
+ crDELAY( xHandle, xDelayTime );
+
+ // Do something here.
+ }
+
+ // Must end every co-routine with a call to crEND();
+ crEND();
+ }
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay ) \
+ if( ( xTicksToDelay ) > 0 ) \
+ { \
+ vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
+ } \
+ crSET_STATE0( ( xHandle ) );
+
+/**
+ *
+ crQUEUE_SEND(
+ CoRoutineHandle_t xHandle,
+ QueueHandle_t pxQueue,
+ void *pvItemToQueue,
+ TickType_t xTicksToWait,
+ BaseType_t *pxResult
+ )
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function. This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine. This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created. This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+ // Co-routines must begin with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // This assumes the queue has already been created.
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+ if( xResult != pdPASS )
+ {
+ // The message was not posted!
+ }
+
+ // Increment the number to be posted onto the queue.
+ xNumberToPost++;
+
+ // Delay for 100 ticks.
+ crDELAY( xHandle, 100 );
+ }
+
+ // Co-routines must end with a call to crEND().
+ crEND();
+ }
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \
+{ \
+ *( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \
+ { \
+ crSET_STATE0( ( xHandle ) ); \
+ *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \
+ } \
+ if( *pxResult == errQUEUE_YIELD ) \
+ { \
+ crSET_STATE1( ( xHandle ) ); \
+ *pxResult = pdPASS; \
+ } \
+}
+
+/**
+ * croutine. h
+ *
+ crQUEUE_RECEIVE(
+ CoRoutineHandle_t xHandle,
+ QueueHandle_t pxQueue,
+ void *pvBuffer,
+ TickType_t xTicksToWait,
+ BaseType_t *pxResult
+ )
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function. This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine. This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created. This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+
+ // A co-routine receives the number of an LED to flash from a queue. It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+ // All co-routines must start with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Wait for data to become available on the queue.
+ crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+ if( xResult == pdPASS )
+ {
+ // We received the LED to flash - flash it!
+ vParTestToggleLED( uxLEDToFlash );
+ }
+ }
+
+ crEND();
+ }
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \
+{ \
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \
+ if( *( pxResult ) == errQUEUE_BLOCKED ) \
+ { \
+ crSET_STATE0( ( xHandle ) ); \
+ *( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \
+ } \
+ if( *( pxResult ) == errQUEUE_YIELD ) \
+ { \
+ crSET_STATE1( ( xHandle ) ); \
+ *( pxResult ) = pdPASS; \
+ } \
+}
+
+/**
+ * croutine. h
+ *
+ crQUEUE_SEND_FROM_ISR(
+ QueueHandle_t pxQueue,
+ void *pvItemToQueue,
+ BaseType_t xCoRoutinePreviouslyWoken
+ )
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt. The first call
+ * should always pass in pdFALSE. Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue. This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+ // All co-routines must start with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Wait for data to become available on the queue. This assumes the
+ // queue xCommsRxQueue has already been created!
+ crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+ // Was a character received?
+ if( xResult == pdPASS )
+ {
+ // Process the character here.
+ }
+ }
+
+ // All co-routines must end with a call to crEND().
+ crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+ // We loop around reading characters until there are none left in the UART.
+ while( UART_RX_REG_NOT_EMPTY() )
+ {
+ // Obtain the character from the UART.
+ cRxedChar = UART_RX_REG;
+
+ // Post the character onto a queue. xCRWokenByPost will be pdFALSE
+ // the first time around the loop. If the post causes a co-routine
+ // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+ // In this manner we can ensure that if more than one co-routine is
+ // blocked on the queue only one is woken by this ISR no matter how
+ // many characters are posted to the queue.
+ xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+ }
+ }
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ *
+ crQUEUE_SEND_FROM_ISR(
+ QueueHandle_t pxQueue,
+ void *pvBuffer,
+ BaseType_t * pxCoRoutineWoken
+ )
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period. The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+ // All co-routines must start with a call to crSTART().
+ crSTART( xHandle );
+
+ for( ;; )
+ {
+ // Send the next character to the queue.
+ crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+ if( xResult == pdPASS )
+ {
+ // The character was successfully posted to the queue.
+ }
+ else
+ {
+ // Could not post the character to the queue.
+ }
+
+ // Enable the UART Tx interrupt to cause an interrupt in this
+ // hypothetical UART. The interrupt will obtain the character
+ // from the queue and send it.
+ ENABLE_RX_INTERRUPT();
+
+ // Increment to the next character then block for a fixed period.
+ // cCharToTx will maintain its value across the delay as it is
+ // declared static.
+ cCharToTx++;
+ if( cCharToTx > 'x' )
+ {
+ cCharToTx = 'a';
+ }
+ crDELAY( 100 );
+ }
+
+ // All co-routines must end with a call to crEND().
+ crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+ while( UART_TX_REG_EMPTY() )
+ {
+ // Are there any characters in the queue waiting to be sent?
+ // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+ // is woken by the post - ensuring that only a single co-routine is
+ // woken no matter how many times we go around this loop.
+ if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+ {
+ SEND_CHARACTER( cCharToTx );
+ }
+ }
+ }
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here. The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CO_ROUTINE_H */
diff --git a/cc3200/FreeRTOS/Source/include/event_groups.h b/cc3200/FreeRTOS/Source/include/event_groups.h
new file mode 100644
index 0000000000..51e7ea2773
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/event_groups.h
@@ -0,0 +1,726 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning. For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc. A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active. To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose. This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced. For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+typedef void * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t EventBits_t;
+
+/**
+ * event_groups.h
+ *
+ EventGroupHandle_t xEventGroupCreate( void );
+
+ *
+ * Create a new event group. This function cannot be called from an interrupt.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned. If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned. See http://www.freertos.org/a00111.html
+ *
+ * Example usage:
+
+ // Declare a variable to hold the created event group.
+ EventGroupHandle_t xCreatedEventGroup;
+
+ // Attempt to create the event group.
+ xCreatedEventGroup = xEventGroupCreate();
+
+ // Was the event group created successfully?
+ if( xCreatedEventGroup == NULL )
+ {
+ // The event group was not created because there was insufficient
+ // FreeRTOS heap available.
+ }
+ else
+ {
+ // The event group was created.
+ }
+
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToWaitFor,
+ const BaseType_t xClearOnExit,
+ const BaseType_t xWaitForAllBits,
+ const TickType_t xTicksToWait );
+
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested. The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group. For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07. Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout). If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires. If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires. The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired. Test the return value to know
+ * which bits were set. If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set. If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ void aFunction( EventGroupHandle_t xEventGroup )
+ {
+ EventBits_t uxBits;
+ const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+ // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+ // the event group. Clear the bits before exiting.
+ uxBits = xEventGroupWaitBits(
+ xEventGroup, // The event group being tested.
+ BIT_0 | BIT_4, // The bits within the event group to wait for.
+ pdTRUE, // BIT_0 and BIT_4 should be cleared before returning.
+ pdFALSE, // Don't wait for both bits, either bit will do.
+ xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
+
+ if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ {
+ // xEventGroupWaitBits() returned because both bits were set.
+ }
+ else if( ( uxBits & BIT_0 ) != 0 )
+ {
+ // xEventGroupWaitBits() returned because just BIT_0 was set.
+ }
+ else if( ( uxBits & BIT_4 ) != 0 )
+ {
+ // xEventGroupWaitBits() returned because just BIT_4 was set.
+ }
+ else
+ {
+ // xEventGroupWaitBits() returned because xTicksToWait ticks passed
+ // without either BIT_0 or BIT_4 becoming set.
+ }
+ }
+
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+
+ *
+ * Clear bits within an event group. This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group. For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ void aFunction( EventGroupHandle_t xEventGroup )
+ {
+ EventBits_t uxBits;
+
+ // Clear bit 0 and bit 4 in xEventGroup.
+ uxBits = xEventGroupClearBits(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 );// The bits being cleared.
+
+ if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ {
+ // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+ // called. Both will now be clear (not set).
+ }
+ else if( ( uxBits & BIT_0 ) != 0 )
+ {
+ // Bit 0 was set before xEventGroupClearBits() was called. It will
+ // now be clear.
+ }
+ else if( ( uxBits & BIT_4 ) != 0 )
+ {
+ // Bit 4 was set before xEventGroupClearBits() was called. It will
+ // now be clear.
+ }
+ else
+ {
+ // Neither bit 0 nor bit 4 were set in the first place.
+ }
+ }
+
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+ BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set. FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts. As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ // An event group which it is assumed has already been created by a call to
+ // xEventGroupCreate().
+ EventGroupHandle_t xEventGroup;
+
+ void anInterruptHandler( void )
+ {
+ // Clear bit 0 and bit 4 in xEventGroup.
+ xResult = xEventGroupClearBitsFromISR(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 ); // The bits being set.
+
+ if( xResult == pdPASS )
+ {
+ // The message was posted successfully.
+ }
+ }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+ BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+#else
+ #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ *
+ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns. There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared. First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ void aFunction( EventGroupHandle_t xEventGroup )
+ {
+ EventBits_t uxBits;
+
+ // Set bit 0 and bit 4 in xEventGroup.
+ uxBits = xEventGroupSetBits(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 );// The bits being set.
+
+ if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ {
+ // Both bit 0 and bit 4 remained set when the function returned.
+ }
+ else if( ( uxBits & BIT_0 ) != 0 )
+ {
+ // Bit 0 remained set when the function returned, but bit 4 was
+ // cleared. It might be that bit 4 was cleared automatically as a
+ // task that was waiting for bit 4 was removed from the Blocked
+ // state.
+ }
+ else if( ( uxBits & BIT_4 ) != 0 )
+ {
+ // Bit 4 remained set when the function returned, but bit 0 was
+ // cleared. It might be that bit 0 was cleared automatically as a
+ // task that was waiting for bit 0 was removed from the Blocked
+ // state.
+ }
+ else
+ {
+ // Neither bit 0 nor bit 4 remained set. It might be that a task
+ // was waiting for both of the bits to be set, and the bits were
+ // cleared as the task left the Blocked state.
+ }
+ }
+
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *
+ BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set. FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections. Therefore xEventGroupSetBitFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task. If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits. For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+
+ // An event group which it is assumed has already been created by a call to
+ // xEventGroupCreate().
+ EventGroupHandle_t xEventGroup;
+
+ void anInterruptHandler( void )
+ {
+ BaseType_t xHigherPriorityTaskWoken, xResult;
+
+ // xHigherPriorityTaskWoken must be initialised to pdFALSE.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Set bit 0 and bit 4 in xEventGroup.
+ xResult = xEventGroupSetBitsFromISR(
+ xEventGroup, // The event group being updated.
+ BIT_0 | BIT_4 // The bits being set.
+ &xHigherPriorityTaskWoken );
+
+ // Was the message posted successfully?
+ if( xResult == pdPASS )
+ {
+ // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ // switch should be requested. The macro used is port specific and
+ // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ // refer to the documentation page for the port being used.
+ portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ }
+ }
+
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+ BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+#else
+ #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ *
+ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+ const EventBits_t uxBitsToSet,
+ const EventBits_t uxBitsToWaitFor,
+ TickType_t xTicksToWait );
+
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group. This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time. In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested. The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group. For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07. Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired. Test the return value to know
+ * which bits were set. If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set. If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+
+ // Bits used by the three tasks.
+ #define TASK_0_BIT ( 1 << 0 )
+ #define TASK_1_BIT ( 1 << 1 )
+ #define TASK_2_BIT ( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks. It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+ for( ;; )
+ {
+ // Perform task functionality here.
+
+ // Set bit 0 in the event flag to note this task has reached the
+ // sync point. The other two tasks will set the other two bits defined
+ // by ALL_SYNC_BITS. All three tasks have reached the synchronisation
+ // point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms
+ // for this to happen.
+ uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+ if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+ {
+ // All three tasks reached the synchronisation point before the call
+ // to xEventGroupSync() timed out.
+ }
+ }
+ }
+
+ void vTask1( void *pvParameters )
+ {
+ for( ;; )
+ {
+ // Perform task functionality here.
+
+ // Set bit 1 in the event flag to note this task has reached the
+ // synchronisation point. The other two tasks will set the other two
+ // bits defined by ALL_SYNC_BITS. All three tasks have reached the
+ // synchronisation point when all the ALL_SYNC_BITS are set. Wait
+ // indefinitely for this to happen.
+ xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+ // xEventGroupSync() was called with an indefinite block time, so
+ // this task will only reach here if the syncrhonisation was made by all
+ // three tasks, so there is no need to test the return value.
+ }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+ for( ;; )
+ {
+ // Perform task functionality here.
+
+ // Set bit 2 in the event flag to note this task has reached the
+ // synchronisation point. The other two tasks will set the other two
+ // bits defined by ALL_SYNC_BITS. All three tasks have reached the
+ // synchronisation point when all the ALL_SYNC_BITS are set. Wait
+ // indefinitely for this to happen.
+ xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+ // xEventGroupSync() was called with an indefinite block time, so
+ // this task will only reach here if the syncrhonisation was made by all
+ // three tasks, so there is no need to test the return value.
+ }
+ }
+
+
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ *
+ EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+
+ *
+ * Returns the current value of the bits in an event group. This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ *
+ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+
+/**
+ * event_groups.h
+ *
+ void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate(). Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup );
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet );
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear );
+
+#if (configUSE_TRACE_FACILITY == 1)
+ UBaseType_t uxEventGroupGetNumber( void* xEventGroup );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_GROUPS_H */
+
+
diff --git a/cc3200/FreeRTOS/Source/include/list.h b/cc3200/FreeRTOS/Source/include/list.h
new file mode 100644
index 0000000000..c08b11d6cc
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/list.h
@@ -0,0 +1,403 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * This is the list implementation used by the scheduler. While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a
+ * numeric value (xItemValue). Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item. The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker. The list member pxHead always
+ * points to this marker - even though it is at the tail of the list. This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it. These later two
+ * pointers are included for efficiency of list manipulation. There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile. However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable. Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour. The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended. That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation. It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler. If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+ #define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST_ITEM
+{
+ configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */
+ struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */
+ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */
+ void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */
+ void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */
+};
+typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+ configLIST_VOLATILE TickType_t xItemValue;
+ struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+ struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+ configLIST_VOLATILE UBaseType_t uxNumberOfItems;
+ ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+ MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item. The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item. The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item. In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item. The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items. The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list. Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter. Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item. In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \
+{ \
+List_t * const pxConstList = ( pxList ); \
+ /* Increment the index to the next item and return the item, ensuring */ \
+ /* we don't return the marker used at the end of the list. */ \
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
+ if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
+ { \
+ ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
+ } \
+ ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \
+}
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list. Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item. In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list. The list item maintains a
+ * "container" pointer that points to the list it is in. All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used! This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList );
+
+/*
+ * Must be called before a list item is used. This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem );
+
+/*
+ * Insert a list item into a list. The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem );
+
+/*
+ * Insert a list item into a list. The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pvIndex is used to walk through a list. Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pvIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pvIndex. This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pvIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem );
+
+/*
+ * Remove an item from a list. The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed. The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/cc3200/FreeRTOS/Source/include/mpu_wrappers.h b/cc3200/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000000..6777be5d19
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,153 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+ /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+ included from queue.c or task.c to prevent it from having an effect within
+ those files. */
+ #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+ #define xTaskGenericCreate MPU_xTaskGenericCreate
+ #define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions
+ #define vTaskDelete MPU_vTaskDelete
+ #define vTaskDelayUntil MPU_vTaskDelayUntil
+ #define vTaskDelay MPU_vTaskDelay
+ #define uxTaskPriorityGet MPU_uxTaskPriorityGet
+ #define vTaskPrioritySet MPU_vTaskPrioritySet
+ #define eTaskGetState MPU_eTaskGetState
+ #define vTaskSuspend MPU_vTaskSuspend
+ #define vTaskResume MPU_vTaskResume
+ #define vTaskSuspendAll MPU_vTaskSuspendAll
+ #define xTaskResumeAll MPU_xTaskResumeAll
+ #define xTaskGetTickCount MPU_xTaskGetTickCount
+ #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks
+ #define vTaskList MPU_vTaskList
+ #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats
+ #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag
+ #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag
+ #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook
+ #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark
+ #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle
+ #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState
+ #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle
+ #define uxTaskGetSystemState MPU_uxTaskGetSystemState
+
+ #define xQueueGenericCreate MPU_xQueueGenericCreate
+ #define xQueueCreateMutex MPU_xQueueCreateMutex
+ #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive
+ #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive
+ #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore
+ #define xQueueGenericSend MPU_xQueueGenericSend
+ #define xQueueAltGenericSend MPU_xQueueAltGenericSend
+ #define xQueueAltGenericReceive MPU_xQueueAltGenericReceive
+ #define xQueueGenericReceive MPU_xQueueGenericReceive
+ #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting
+ #define vQueueDelete MPU_vQueueDelete
+ #define xQueueGenericReset MPU_xQueueGenericReset
+ #define xQueueCreateSet MPU_xQueueCreateSet
+ #define xQueueSelectFromSet MPU_xQueueSelectFromSet
+ #define xQueueAddToSet MPU_xQueueAddToSet
+ #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet
+ #define xQueuePeekFromISR MPU_xQueuePeekFromISR
+ #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder
+
+ #define pvPortMalloc MPU_pvPortMalloc
+ #define vPortFree MPU_vPortFree
+ #define xPortGetFreeHeapSize MPU_xPortGetFreeHeapSize
+ #define vPortInitialiseBlocks MPU_vPortInitialiseBlocks
+
+ #if configQUEUE_REGISTRY_SIZE > 0
+ #define vQueueAddToRegistry MPU_vQueueAddToRegistry
+ #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue
+ #endif
+
+ /* Remove the privileged function macro. */
+ #define PRIVILEGED_FUNCTION
+
+ #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+ /* Ensure API functions go in the privileged execution section. */
+ #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+ #define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+
+ #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+ #define PRIVILEGED_FUNCTION
+ #define PRIVILEGED_DATA
+ #define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/cc3200/FreeRTOS/Source/include/portable.h b/cc3200/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000000..f63e99f23e
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,426 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Portable layer API. Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Include the macro file relevant to the port being used.
+NOTE: The following definitions are *DEPRECATED* as it is preferred to instead
+just add the path to the correct portmacro.h header file to the compiler's
+include path. */
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+ #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+ #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+ #include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+ #include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+ #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+ #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+ #include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+ #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+ #include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+ #include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+ #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+ #include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+ #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+ #include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+ #include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+ #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+ #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+ #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+ #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+ #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+ #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+ #include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+ #include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+ #include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+ #include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+ #include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+ #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+ #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+ #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+ #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+ #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+ #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+ #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+ #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+ #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+ #include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+ #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+ #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+ #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+ #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+ #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+ #include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+ /* A short file name has to be used in place of the normal
+ FreeRTOSConfig.h when using the Borland compiler. */
+ #include "frconfig.h"
+ #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+ /* A short file name has to be used in place of the normal
+ FreeRTOSConfig.h when using the Borland compiler. */
+ #include "frconfig.h"
+ #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+ typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef __GNUC__
+ #ifdef __AVR32_AVR32A__
+ #include "portmacro.h"
+ #endif
+#endif
+
+#ifdef __ICCAVR32__
+ #ifdef __CORE__
+ #if __CORE__ == __AVR32A__
+ #include "portmacro.h"
+ #endif
+ #endif
+#endif
+
+#ifdef __91467D
+ #include "portmacro.h"
+#endif
+
+#ifdef __96340
+ #include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+ #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+ #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+ #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+/* Catch all to ensure portmacro.h is included in the build. Newer demos
+have the path as part of the project options, rather than as relative from
+the project location. If portENTER_CRITICAL() has not been defined then
+portmacro.h has not yet been included - as every portmacro.h provides a
+portENTER_CRITICAL() definition. Check the demo application for your demo
+to find the path to the correct portmacro.h file. */
+#ifndef portENTER_CRITICAL
+ #include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+ #define portBYTE_ALIGNMENT_MASK ( 0x0007U )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+ #define portBYTE_ALIGNMENT_MASK ( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+ #define portBYTE_ALIGNMENT_MASK ( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+ #define portBYTE_ALIGNMENT_MASK ( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+ #error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+ #define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control. The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+#else
+ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+ uint8_t *pucStartAddress;
+ size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c. This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap. The array is
+ * terminated by a HeapRegions_t structure that has a size of 0. The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions );
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control. This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+ struct xMEMORY_REGION;
+ void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint16_t usStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/cc3200/FreeRTOS/Source/include/projdefs.h b/cc3200/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000000..9eccedff47
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,94 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform. Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks. */
+#define pdMS_TO_TICKS( xTimeInMs ) ( ( ( TickType_t ) ( xTimeInMs ) * configTICK_RATE_HZ ) / ( TickType_t ) 1000 )
+
+#define pdFALSE ( ( BaseType_t ) 0 )
+#define pdTRUE ( ( BaseType_t ) 1 )
+
+#define pdPASS ( pdTRUE )
+#define pdFAIL ( pdFALSE )
+#define errQUEUE_EMPTY ( ( BaseType_t ) 0 )
+#define errQUEUE_FULL ( ( BaseType_t ) 0 )
+
+/* Error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )
+#define errQUEUE_BLOCKED ( -4 )
+#define errQUEUE_YIELD ( -5 )
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/cc3200/FreeRTOS/Source/include/queue.h b/cc3200/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000000..a728a7c51c
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1687 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Type by which queues are referenced. For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+typedef void * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced. For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef void * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef void * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define queueSEND_TO_BACK ( ( BaseType_t ) 0 )
+#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 )
+#define queueOVERWRITE ( ( BaseType_t ) 2 )
+
+/* For internal use only. These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ *
+ QueueHandle_t xQueueCreate(
+ UBaseType_t uxQueueLength,
+ UBaseType_t uxItemSize
+ );
+ *
+ *
+ * Creates a new queue instance. This allocates the storage required by the
+ * new queue and returns a handle for the queue.
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item. Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned. If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ if( xQueue1 == 0 )
+ {
+ // Queue was not created and must not be used.
+ }
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ if( xQueue2 == 0 )
+ {
+ // Queue was not created and must not be used.
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( uxQueueLength, uxItemSize, queueQUEUE_TYPE_BASE )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueSendToToFront(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ TickType_t xTicksToWait
+ );
+ *
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the front of a queue. The item is queued by copy, not by
+ * reference. This function must not be called from an interrupt service
+ * routine. See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the
+ * queue is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueSendToBack(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ TickType_t xTicksToWait
+ );
+ *
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue. The item is queued by copy, not by
+ * reference. This function must not be called from an interrupt service
+ * routine. See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the queue
+ * is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueSend(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ TickType_t xTicksToWait
+ );
+ *
+ *
+ * This is a macro that calls xQueueGenericSend(). It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros. It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue. The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the
+ * queue is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueOverwrite(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue
+ );
+ *
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue. If the queue is already full then overwrite the
+ * value held in the queue. The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront(). However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+ // Create a queue to hold one uint32_t value. It is strongly
+ // recommended *not* to use xQueueOverwrite() on queues that can
+ // contain more than one value, and doing so will trigger an assertion
+ // if configASSERT() is defined.
+ xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+ // Write the value 10 to the queue using xQueueOverwrite().
+ ulVarToSend = 10;
+ xQueueOverwrite( xQueue, &ulVarToSend );
+
+ // Peeking the queue should now return 10, but leave the value 10 in
+ // the queue. A block time of zero is used as it is known that the
+ // queue holds a value.
+ ulValReceived = 0;
+ xQueuePeek( xQueue, &ulValReceived, 0 );
+
+ if( ulValReceived != 10 )
+ {
+ // Error unless the item was removed by a different task.
+ }
+
+ // The queue is still full. Use xQueueOverwrite() to overwrite the
+ // value held in the queue with 100.
+ ulVarToSend = 100;
+ xQueueOverwrite( xQueue, &ulVarToSend );
+
+ // This time read from the queue, leaving the queue empty once more.
+ // A block time of 0 is used again.
+ xQueueReceive( xQueue, &ulValReceived, 0 );
+
+ // The value read should be the last value written, even though the
+ // queue was already full when the value was written.
+ if( ulValReceived != 100 )
+ {
+ // Error!
+ }
+
+ // ...
+}
+
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueGenericSend(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ TickType_t xTicksToWait
+ BaseType_t xCopyPosition
+ );
+ *
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue. The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full. The call will return immediately if this is set to 0 and the
+ * queue is full. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 uint32_t values.
+ xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+ // ...
+
+ if( xQueue1 != 0 )
+ {
+ // Send an uint32_t. Wait for 10 ticks for space to become
+ // available if necessary.
+ if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+ {
+ // Failed to post the message, even after 10 ticks.
+ }
+ }
+
+ if( xQueue2 != 0 )
+ {
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueuePeek(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ TickType_t xTicksToWait
+ );
+ *
+ * This is a macro that calls the xQueueGenericReceive() function.
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided. The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine. See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ if( xQueue == 0 )
+ {
+ // Failed to create the queue.
+ }
+
+ // ...
+
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+ // ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+ if( xQueue != 0 )
+ {
+ // Peek a message on the created queue. Block for 10 ticks if a
+ // message is not immediately available.
+ if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ {
+ // pcRxedMessage now points to the struct AMessage variable posted
+ // by vATask, but the item still remains on the queue.
+ }
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueuePeekFromISR(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ );
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided. The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueReceive(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ TickType_t xTicksToWait
+ );
+ *
+ * This is a macro that calls the xQueueGenericReceive() function.
+ *
+ * Receive an item from a queue. The item is received by copy so a buffer of
+ * adequate size must be provided. The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine. See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty. The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ if( xQueue == 0 )
+ {
+ // Failed to create the queue.
+ }
+
+ // ...
+
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+ // ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+ if( xQueue != 0 )
+ {
+ // Receive a message on the created queue. Block for 10 ticks if a
+ // message is not immediately available.
+ if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ {
+ // pcRxedMessage now points to the struct AMessage variable posted
+ // by vATask.
+ }
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )
+
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueGenericReceive(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ TickType_t xTicksToWait
+ BaseType_t xJustPeek
+ );
+ *
+ * It is preferred that the macro xQueueReceive() be used rather than calling
+ * this function directly.
+ *
+ * Receive an item from a queue. The item is received by copy so a buffer of
+ * adequate size must be provided. The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * This function must not be used in an interrupt service routine. See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueueGenericReceive() will return immediately if the queue is empty and
+ * xTicksToWait is 0.
+ *
+ * @param xJustPeek When set to true, the item received from the queue is not
+ * actually removed from the queue - meaning a subsequent call to
+ * xQueueReceive() will return the same item. When set to false, the item
+ * being received from the queue is also removed from the queue.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+
+ struct AMessage
+ {
+ char ucMessageID;
+ char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+ // Create a queue capable of containing 10 pointers to AMessage structures.
+ // These should be passed by pointer as they contain a lot of data.
+ xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ if( xQueue == 0 )
+ {
+ // Failed to create the queue.
+ }
+
+ // ...
+
+ // Send a pointer to a struct AMessage object. Don't block if the
+ // queue is already full.
+ pxMessage = & xMessage;
+ xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+ // ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+ if( xQueue != 0 )
+ {
+ // Receive a message on the created queue. Block for 10 ticks if a
+ // message is not immediately available.
+ if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ {
+ // pcRxedMessage now points to the struct AMessage variable posted
+ // by vATask.
+ }
+ }
+
+ // ... Rest of task code.
+ }
+
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+ *
+ * Return the number of free spaces available in a queue. This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * void vQueueDelete( QueueHandle_t xQueue );
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueSendToFrontFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue. It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post the byte.
+ xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary.
+ if( xHigherPriorityTaskWoken )
+ {
+ taskYIELD ();
+ }
+ }
+
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueSendToBackFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue. It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post the byte.
+ xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary.
+ if( xHigherPriorityTaskWoken )
+ {
+ taskYIELD ();
+ }
+ }
+
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueOverwriteFromISR(
+ QueueHandle_t xQueue,
+ const void * pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+ *
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue. If the queue is already full then overwrite the
+ * value held in the queue. The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ // Create a queue to hold one uint32_t value. It is strongly
+ // recommended *not* to use xQueueOverwriteFromISR() on queues that can
+ // contain more than one value, and doing so will trigger an assertion
+ // if configASSERT() is defined.
+ xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+ // Write the value 10 to the queue using xQueueOverwriteFromISR().
+ ulVarToSend = 10;
+ xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+ // The queue is full, but calling xQueueOverwriteFromISR() again will still
+ // pass because the value held in the queue will be overwritten with the
+ // new value.
+ ulVarToSend = 100;
+ xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+ // Reading from the queue will now return 100.
+
+ // ...
+
+ if( xHigherPrioritytaskWoken == pdTRUE )
+ {
+ // Writing to the queue caused a task to unblock and the unblocked task
+ // has a priority higher than or equal to the priority of the currently
+ // executing task (the task this interrupt interrupted). Perform a context
+ // switch so this interrupt returns directly to the unblocked task.
+ portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ }
+}
+
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueSendFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken
+ );
+
+ *
+ * This is a macro that calls xQueueGenericSendFromISR(). It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue. It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post the byte.
+ xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary.
+ if( xHigherPriorityTaskWoken )
+ {
+ // Actual macro used here is port specific.
+ portYIELD_FROM_ISR ();
+ }
+ }
+
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueGenericSendFromISR(
+ QueueHandle_t xQueue,
+ const void *pvItemToQueue,
+ BaseType_t *pxHigherPriorityTaskWoken,
+ BaseType_t xCopyPosition
+ );
+
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.
+ *
+ * Post an item on a queue. It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR. In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue. The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+ // We have not woken a task at the start of the ISR.
+ xHigherPriorityTaskWokenByPost = pdFALSE;
+
+ // Loop until the buffer is empty.
+ do
+ {
+ // Obtain a byte from the buffer.
+ cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+ // Post each byte.
+ xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+ } while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+ // Now the buffer is empty we can switch context if necessary. Note that the
+ // name of the yield function required is port specific.
+ if( xHigherPriorityTaskWokenByPost )
+ {
+ taskYIELD_YIELD_FROM_ISR();
+ }
+ }
+
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ *
+ BaseType_t xQueueReceiveFromISR(
+ QueueHandle_t xQueue,
+ void *pvBuffer,
+ BaseType_t *pxTaskWoken
+ );
+ *
+ *
+ * Receive an item from a queue. It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue. If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+ // Create a queue capable of containing 10 characters.
+ xQueue = xQueueCreate( 10, sizeof( char ) );
+ if( xQueue == 0 )
+ {
+ // Failed to create the queue.
+ }
+
+ // ...
+
+ // Post some characters that will be used within an ISR. If the queue
+ // is full then this task will block for xTicksToWait ticks.
+ cValueToPost = 'a';
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ cValueToPost = 'b';
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+ // ... keep posting characters ... this task may block when the queue
+ // becomes full.
+
+ cValueToPost = 'c';
+ xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+ while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+ {
+ // A character was received. Output the character now.
+ vOutputCharacter( cRxedChar );
+
+ // If removing the character from the queue woke the task that was
+ // posting onto the queue cTaskWokenByReceive will have been set to
+ // pdTRUE. No matter how many times this loop iterates only one
+ // task will be woken.
+ }
+
+ if( cTaskWokenByPost != ( char ) pdFALSE;
+ {
+ taskYIELD ();
+ }
+ }
+
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR. These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * xQueueAltGenericSend() is an alternative version of xQueueGenericSend().
+ * Likewise xQueueAltGenericReceive() is an alternative version of
+ * xQueueGenericReceive().
+ *
+ * The source code that implements the alternative (Alt) API is much
+ * simpler because it executes everything from within a critical section.
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the
+ * preferred fully featured API too. The fully featured API has more
+ * complex code that takes longer to execute, but makes much less use of
+ * critical sections. Therefore the alternative API sacrifices interrupt
+ * responsiveness to gain execution speed, whereas the fully featured API
+ * sacrifices execution speed to ensure better interrupt responsiveness.
+ */
+BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );
+BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );
+#define xQueueAltSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+#define xQueueAltSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueAltGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+#define xQueueAltReceive( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )
+#define xQueueAltPeek( xQueue, pvBuffer, xTicksToWait ) xQueueAltGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )
+
+/*
+ * The functions defined above are for passing data to and from tasks. The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code. Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only. Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only. Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state. pdPASS is returned if the
+ * queue is successfully reset. pdFAIL is returned if the queue could not be
+ * reset because there are tasks blocked on the queue waiting to either
+ * receive from the queue or send to the queue.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger. If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available. Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry. This
+ * is the handle returned by a call to xQueueCreate(). Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle. This is the
+ * name that the kernel aware debugger will display. The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if configQUEUE_REGISTRY_SIZE > 0
+ void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register. If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if configQUEUE_REGISTRY_SIZE > 0
+ void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the queue creation function, which is in turn called by
+ * any queue, semaphore or mutex creation function or macro.
+ */
+QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used. Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2: Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3: An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set. Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4: A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set. uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once. To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value. Examples:
+ * + If a queue set is to hold a queue of length 5, another queue of length 12,
+ * and a binary semaphore, then uxEventQueueLength should be set to
+ * (5 + 12 + 1), or 18.
+ * + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ * should be set to (1 + 1 + 1 ), or 3.
+ * + If a queue set is to hold a counting semaphore that has a maximum count of
+ * 5, and a counting semaphore that has a maximum count of 3, then
+ * uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned. Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1: A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned. If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set. A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned. If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore). xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1: See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2: Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3: A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/cc3200/FreeRTOS/Source/include/semphr.h b/cc3200/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000000..5275895438
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,840 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function. Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Macro that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore. The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task. The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore. For this reason this type of
+ * semaphore does not use a priority inheritance mechanism. For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+ // This is a macro so pass the variable in directly.
+ vSemaphoreCreateBinary( xSemaphore );
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#define vSemaphoreCreateBinary( xSemaphore ) \
+ { \
+ ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \
+ if( ( xSemaphore ) != NULL ) \
+ { \
+ ( void ) xSemaphoreGive( ( xSemaphore ) ); \
+ } \
+ }
+
+/**
+ * semphr. h
+ * SemaphoreHandle_t xSemaphoreCreateBinary( void )
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function. Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * Function that creates a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore. The data size is 0
+ * as nothing is actually stored - all that is important is whether the queue is
+ * empty or full (the binary semaphore is available or not).
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task. The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore. For this reason this type of
+ * semaphore does not use a priority inheritance mechanism. For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+ // This is a macro so pass the variable in directly.
+ xSemaphore = xSemaphoreCreateBinary();
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+
+/**
+ * semphr. h
+ * xSemaphoreTake(
+ * SemaphoreHandle_t xSemaphore,
+ * TickType_t xBlockTime
+ * )
+ *
+ * Macro to obtain a semaphore. The semaphore must have previously been
+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available. The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time. A block time of zero can be used to poll the semaphore. A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained. pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+ // Create the semaphore to guard a shared resource.
+ vSemaphoreCreateBinary( xSemaphore );
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+ // ... Do other things.
+
+ if( xSemaphore != NULL )
+ {
+ // See if we can obtain the semaphore. If the semaphore is not available
+ // wait 10 ticks to see if it becomes free.
+ if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ {
+ // We were able to obtain the semaphore and can now access the
+ // shared resource.
+
+ // ...
+
+ // We have finished accessing the shared resource. Release the
+ // semaphore.
+ xSemaphoreGive( xSemaphore );
+ }
+ else
+ {
+ // We could not obtain the semaphore and can therefore not access
+ // the shared resource safely.
+ }
+ }
+ }
+
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ * SemaphoreHandle_t xMutex,
+ * TickType_t xBlockTime
+ * )
+ *
+ * Macro to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also 'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained. This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available. The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time. A block time of zero can be used to poll the semaphore. If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+ // Create the mutex to guard a shared resource.
+ xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+ // ... Do other things.
+
+ if( xMutex != NULL )
+ {
+ // See if we can obtain the mutex. If the mutex is not available
+ // wait 10 ticks to see if it becomes free.
+ if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ {
+ // We were able to obtain the mutex and can now access the
+ // shared resource.
+
+ // ...
+ // For some reason due to the nature of the code further calls to
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real
+ // code these would not be just sequential calls as this would make
+ // no sense. Instead the calls are likely to be buried inside
+ // a more complex call structure.
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+ // The mutex has now been 'taken' three times, so will not be
+ // available to another task until it has also been given back
+ // three times. Again it is unlikely that real code would have
+ // these calls sequentially, but instead buried in a more complex
+ // call structure. This is just for illustrative purposes.
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+
+ // Now the mutex can be taken by other tasks.
+ }
+ else
+ {
+ // We could not obtain the mutex and can therefore not access
+ // the shared resource safely.
+ }
+ }
+ }
+
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+
+
+/*
+ * xSemaphoreAltTake() is an alternative version of xSemaphoreTake().
+ *
+ * The source code that implements the alternative (Alt) API is much
+ * simpler because it executes everything from within a critical section.
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the
+ * preferred fully featured API too. The fully featured API has more
+ * complex code that takes longer to execute, but makes much less use of
+ * critical sections. Therefore the alternative API sacrifices interrupt
+ * responsiveness to gain execution speed, whereas the fully featured API
+ * sacrifices execution speed to ensure better interrupt responsiveness.
+ */
+#define xSemaphoreAltTake( xSemaphore, xBlockTime ) xQueueAltGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )
+
+/**
+ * semphr. h
+ * xSemaphoreGive( SemaphoreHandle_t xSemaphore )
+ *
+ * Macro to release a semaphore. The semaphore must have previously been
+ * created with a call to vSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released. This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred.
+ * Semaphores are implemented using queues. An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+ // Create the semaphore to guard a shared resource.
+ vSemaphoreCreateBinary( xSemaphore );
+
+ if( xSemaphore != NULL )
+ {
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ {
+ // We would expect this call to fail because we cannot give
+ // a semaphore without first "taking" it!
+ }
+
+ // Obtain the semaphore - don't block if the semaphore is not
+ // immediately available.
+ if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+ {
+ // We now have the semaphore and can access the shared resource.
+
+ // ...
+
+ // We have finished accessing the shared resource so can free the
+ // semaphore.
+ if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ {
+ // We would not expect this call to fail because we must have
+ // obtained the semaphore to get here.
+ }
+ }
+ }
+ }
+
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )
+ *
+ * Macro to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also 'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'. This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+ // Create the mutex to guard a shared resource.
+ xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+ // ... Do other things.
+
+ if( xMutex != NULL )
+ {
+ // See if we can obtain the mutex. If the mutex is not available
+ // wait 10 ticks to see if it becomes free.
+ if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+ {
+ // We were able to obtain the mutex and can now access the
+ // shared resource.
+
+ // ...
+ // For some reason due to the nature of the code further calls to
+ // xSemaphoreTakeRecursive() are made on the same mutex. In real
+ // code these would not be just sequential calls as this would make
+ // no sense. Instead the calls are likely to be buried inside
+ // a more complex call structure.
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+ // The mutex has now been 'taken' three times, so will not be
+ // available to another task until it has also been given back
+ // three times. Again it is unlikely that real code would have
+ // these calls sequentially, it would be more likely that the calls
+ // to xSemaphoreGiveRecursive() would be called as a call stack
+ // unwound. This is just for demonstrative purposes.
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+ xSemaphoreGiveRecursive( xMutex );
+
+ // Now the mutex can be taken by other tasks.
+ }
+ else
+ {
+ // We could not obtain the mutex and can therefore not access
+ // the shared resource safely.
+ }
+ }
+ }
+
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) )
+
+/*
+ * xSemaphoreAltGive() is an alternative version of xSemaphoreGive().
+ *
+ * The source code that implements the alternative (Alt) API is much
+ * simpler because it executes everything from within a critical section.
+ * This is the approach taken by many other RTOSes, but FreeRTOS.org has the
+ * preferred fully featured API too. The fully featured API has more
+ * complex code that takes longer to execute, but makes much less use of
+ * critical sections. Therefore the alternative API sacrifices interrupt
+ * responsiveness to gain execution speed, whereas the fully featured API
+ * sacrifices execution speed to ensure better interrupt responsiveness.
+ */
+#define xSemaphoreAltGive( xSemaphore ) xQueueAltGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ *
+ xSemaphoreGiveFromISR(
+ SemaphoreHandle_t xSemaphore,
+ BaseType_t *pxHigherPriorityTaskWoken
+ )
+ *
+ * Macro to release a semaphore. The semaphore must have previously been
+ * created with a call to vSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released. This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT 10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // We want this task to run every 10 ticks of a timer. The semaphore
+ // was created before this task was started.
+
+ // Block waiting for the semaphore to become available.
+ if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+ {
+ // It is time to execute.
+
+ // ...
+
+ // We have finished our task. Return to the top of the loop where
+ // we will block on the semaphore until it is time to execute
+ // again. Note when using the semaphore for synchronisation with an
+ // ISR in this manner there is no need to 'give' the semaphore back.
+ }
+ }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+ // A timer tick has occurred.
+
+ // ... Do other time functions.
+
+ // Is it time for vATask () to run?
+ xHigherPriorityTaskWoken = pdFALSE;
+ ucLocalTickCount++;
+ if( ucLocalTickCount >= TICKS_TO_WAIT )
+ {
+ // Unblock the task by releasing the semaphore.
+ xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+ // Reset the count so we release the semaphore again in 10 ticks time.
+ ucLocalTickCount = 0;
+ }
+
+ if( xHigherPriorityTaskWoken != pdFALSE )
+ {
+ // We can force a context switch here. Context switching from an
+ // ISR uses port specific syntax. Check the demo task for your port
+ // to find the syntax required.
+ }
+ }
+
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ *
+ xSemaphoreTakeFromISR(
+ SemaphoreHandle_t xSemaphore,
+ BaseType_t *pxHigherPriorityTaskWoken
+ )
+ *
+ * Macro to take a semaphore from an ISR. The semaphore must have
+ * previously been created with a call to vSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation. It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken. This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * SemaphoreHandle_t xSemaphoreCreateMutex( void )
+ *
+ * Macro that implements a mutex semaphore by using the existing queue
+ * mechanism.
+ *
+ * Mutexes created using this macro can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros should not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See vSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore. Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ // This is a macro so pass the variable in directly.
+ xSemaphore = xSemaphoreCreateMutex();
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+
+
+/**
+ * semphr. h
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )
+ *
+ * Macro that implements a recursive mutex by using the existing queue
+ * mechanism.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The
+ * xSemaphoreTake() and xSemaphoreGive() macros should not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request. For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also 'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See vSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore. Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ // This is a macro so pass the variable in directly.
+ xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+
+ * \defgroup vSemaphoreCreateMutex vSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+
+/**
+ * semphr. h
+ * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )
+ *
+ * Macro that creates a counting semaphore by using the existing
+ * queue mechanism.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ * In this usage scenario an event handler will 'give' a semaphore each time
+ * an event occurs (incrementing the semaphore count value), and a handler
+ * task will 'take' a semaphore each time it processes an event
+ * (decrementing the semaphore count value). The count value is therefore
+ * the difference between the number of events that have occurred and the
+ * number that have been processed. In this case it is desirable for the
+ * initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ * In this usage scenario the count value indicates the number of resources
+ * available. To obtain control of a resource a task must first obtain a
+ * semaphore - decrementing the semaphore count value. When the count value
+ * reaches zero there are no free resources. When a task finishes with the
+ * resource it 'gives' the semaphore back - incrementing the semaphore count
+ * value. In this case it is desirable for the initial count value to be
+ * equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached. When the
+ * semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ * created.
+ *
+ * @return Handle to the created semaphore. Null if the semaphore could not be
+ * created.
+ *
+ * Example usage:
+
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+ // The max value to which the semaphore can count should be 10, and the
+ // initial value assigned to the count should be 0.
+ xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+ if( xSemaphore != NULL )
+ {
+ // The semaphore was created successfully.
+ // The semaphore can now be used.
+ }
+ }
+
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+
+/**
+ * semphr. h
+ * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
+ *
+ * Delete a semaphore. This function must be used with care. For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/cc3200/FreeRTOS/Source/include/task.h b/cc3200/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000000..8ed65bc28f
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/task.h
@@ -0,0 +1,1567 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V8.1.2"
+#define tskKERNEL_VERSION_MAJOR 8
+#define tskKERNEL_VERSION_MINOR 1
+#define tskKERNEL_VERSION_BUILD 2
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced. For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+typedef void * TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+ eRunning = 0, /* A task is querying the state of itself, so must be running. */
+ eReady, /* The task being queried is in a read or pending ready list. */
+ eBlocked, /* The task being queried is in the Blocked state. */
+ eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+ eDeleted /* The task being queried has been deleted, but its TCB has not yet been freed. */
+} eTaskState;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+ BaseType_t xOverflowCount;
+ TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+ void *pvBaseAddress;
+ uint32_t ulLengthInBytes;
+ uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+ TaskFunction_t pvTaskCode;
+ const char * const pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ uint16_t usStackDepth;
+ void *pvParameters;
+ UBaseType_t uxPriority;
+ StackType_t *puxStackBuffer;
+ MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+ TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */
+ const char *pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ UBaseType_t xTaskNumber; /* A number unique to the task. */
+ eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */
+ UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */
+ UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+ uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See http://www.freertos.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+ uint16_t usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+ eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+ eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */
+ eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+
+/**
+ * Defines the priority used by the idle task. This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD() portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region. Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL() portENTER_CRITICAL()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region. Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL() portEXIT_CRITICAL()
+
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreate(
+ TaskFunction_t pvTaskCode,
+ const char * const pcName,
+ uint16_t usStackDepth,
+ void *pvParameters,
+ UBaseType_t uxPriority,
+ TaskHandle_t *pvCreatedTask
+ );
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map. Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function. Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task. This is mainly used to
+ * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes. For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run. Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+ }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+ // Create the task, storing the handle. Note that the passed parameter ucParameterToPass
+ // must exist for the lifetime of the task, so in this case is declared static. If it was just an
+ // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+ // the new task attempts to access it.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+ configASSERT( xHandle );
+
+ // Use the handle to delete the task.
+ if( xHandle != NULL )
+ {
+ vTaskDelete( xHandle );
+ }
+ }
+
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskGenericCreate( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), ( NULL ), ( NULL ) )
+
+/**
+ * task. h
+ *
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+ vATask, // pvTaskCode - the function that implements the task.
+ "ATask", // pcName - just a text name for the task to assist debugging.
+ 100, // usStackDepth - the stack size DEFINED IN WORDS.
+ NULL, // pvParameters - passed into the task function as the function parameters.
+ ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+ // xRegions - Allocate up to three separate memory regions for access by
+ // the task, with appropriate access permissions. Different processors have
+ // different memory alignment requirements - refer to the FreeRTOS documentation
+ // for full information.
+ {
+ // Base address Length Parameters
+ { cReadWriteArray, 32, portMPU_REGION_READ_WRITE },
+ { cReadOnlyArray, 32, portMPU_REGION_READ_ONLY },
+ { cPrivilegedOnlyAccessArray, 128, portMPU_REGION_PRIVILEGED_READ_WRITE }
+ }
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+ // Create a task from the const structure defined above. The task handle
+ // is requested (the second parameter is not NULL) but in this case just for
+ // demonstration purposes as its not actually used.
+ xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+ // Start the scheduler.
+ vTaskStartScheduler();
+
+ // Will only get here if there was insufficient memory to create the idle
+ // and/or timer task.
+ for( ;; );
+}
+
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#define xTaskCreateRestricted( x, pxCreatedTask ) xTaskGenericCreate( ((x)->pvTaskCode), ((x)->pcName), ((x)->usStackDepth), ((x)->pvParameters), ((x)->uxPriority), (pxCreatedTask), ((x)->puxStackBuffer), ((x)->xRegions) )
+
+/**
+ * task. h
+ *
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted(). These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array. The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+ // Base address Length Parameters
+ { ucOneKByte, 1024, portMPU_REGION_READ_WRITE },
+ { 0, 0, 0 },
+ { 0, 0, 0 }
+};
+
+void vATask( void *pvParameters )
+{
+ // This task was created such that it has access to certain regions of
+ // memory as defined by the MPU configuration. At some point it is
+ // desired that these MPU regions are replaced with that defined in the
+ // xAltRegions const struct above. Use a call to vTaskAllocateMPURegions()
+ // for this purpose. NULL is used as the task handle to indicate that this
+ // function should modify the MPU regions of the calling task.
+ vTaskAllocateMPURegions( NULL, xAltRegions );
+
+ // Now the task can continue its function, but from this point on can only
+ // access its stack and the ucOneKByte array (unless any other statically
+ // defined or shared regions have been declared elsewhere).
+}
+
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void vTaskDelete( TaskHandle_t xTask );
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management. The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE: The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted. It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete (). Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted. Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create the task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // Use the handle to delete the task.
+ vTaskDelete( xHandle );
+ }
+
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * void vTaskDelay( const TickType_t xTicksToDelay );
+ *
+ * Delay a task for a given number of ticks. The actual time that the
+ * task remains blocked depends on the tick rate. The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called. For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes. See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution. It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+ for( ;; )
+ {
+ // Simply toggle the LED every 500ms, blocking between each toggle.
+ vToggleLED();
+ vTaskDelay( xDelay );
+ }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time. This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked. The variable must be initialised with the current time
+ * prior to its first use (see the example below). Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period. The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement. Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+ // Initialise the xLastWakeTime variable with the current time.
+ xLastWakeTime = xTaskGetTickCount ();
+ for( ;; )
+ {
+ // Wait for the next cycle.
+ vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+ // Perform action here.
+ }
+ }
+
+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried. Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to obtain the priority of the created task.
+ // It was created with tskIDLE_PRIORITY, but may have changed
+ // it itself.
+ if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+ {
+ // The task has changed it's priority.
+ }
+
+ // ...
+
+ // Is our priority higher than the created task?
+ if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+ {
+ // Our priority (obtained using NULL handle) is higher.
+ }
+ }
+
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * eTaskState eTaskGetState( TaskHandle_t xTask );
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task. States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called. Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to raise the priority of the created task.
+ vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+ // ...
+
+ // Use a NULL handle to raise our priority to the same value.
+ vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void vTaskSuspend( TaskHandle_t xTaskToSuspend );
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task. When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to suspend the created task.
+ vTaskSuspend( xHandle );
+
+ // ...
+
+ // The created task will not run during this period, unless
+ // another task calls vTaskResume( xHandle ).
+
+ //...
+
+
+ // Suspend ourselves.
+ vTaskSuspend( NULL );
+
+ // We cannot get here unless another task calls vTaskResume
+ // with our handle as the parameter.
+ }
+
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void vTaskResume( TaskHandle_t xTaskToResume );
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+ // Create a task, storing the handle.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+ // ...
+
+ // Use the handle to suspend the created task.
+ vTaskSuspend( xHandle );
+
+ // ...
+
+ // The created task will not run during this period, unless
+ // another task calls vTaskResume( xHandle ).
+
+ //...
+
+
+ // Resume the suspended task ourselves.
+ vTaskResume( xHandle );
+
+ // The created task will once again get microcontroller processing
+ // time in accordance with its priority within the system.
+ }
+
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available. See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * void vTaskStartScheduler( void );
+ *
+ * Starts the real time kernel tick processing. After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+
+ void vAFunction( void )
+ {
+ // Create at least one task before starting the kernel.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+ // Start the real time kernel with preemption.
+ vTaskStartScheduler ();
+
+ // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void vTaskEndScheduler( void );
+ *
+ * NOTE: At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick. All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop. Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port). This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+
+ void vTaskCode( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+
+ // At some point we want to end the real time kernel processing
+ // so call ...
+ vTaskEndScheduler ();
+ }
+ }
+
+ void vAFunction( void )
+ {
+ // Create at least one task before starting the kernel.
+ xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+ // Start the real time kernel with preemption.
+ vTaskStartScheduler ();
+
+ // Will only get here when the vTaskCode () task has called
+ // vTaskEndScheduler (). When we get here we are back to single task
+ // execution.
+ }
+
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * void vTaskSuspendAll( void );
+ *
+ * Suspends the scheduler without disabling interrupts. Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+
+ void vTask1( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+
+ // ...
+
+ // At some point the task wants to perform a long operation during
+ // which it does not want to get swapped out. It cannot use
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ // operation may cause interrupts to be missed - including the
+ // ticks.
+
+ // Prevent the real time kernel swapping out the task.
+ vTaskSuspendAll ();
+
+ // Perform the operation here. There is no need to use critical
+ // sections as we have all the microcontroller processing time.
+ // During this time interrupts will still operate and the kernel
+ // tick count will be maintained.
+
+ // ...
+
+ // The operation is complete. Restart the kernel.
+ xTaskResumeAll ();
+ }
+ }
+
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * BaseType_t xTaskResumeAll( void );
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ * returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+
+ void vTask1( void * pvParameters )
+ {
+ for( ;; )
+ {
+ // Task code goes here.
+
+ // ...
+
+ // At some point the task wants to perform a long operation during
+ // which it does not want to get swapped out. It cannot use
+ // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ // operation may cause interrupts to be missed - including the
+ // ticks.
+
+ // Prevent the real time kernel swapping out the task.
+ vTaskSuspendAll ();
+
+ // Perform the operation here. There is no need to use critical
+ // sections as we have all the microcontroller processing time.
+ // During this time interrupts will still operate and the real
+ // time kernel tick count will be maintained.
+
+ // ...
+
+ // The operation is complete. Restart the kernel. We want to force
+ // a context switch - but there is no point if resuming the scheduler
+ // caused a context switch already.
+ if( !xTaskResumeAll () )
+ {
+ taskYIELD ();
+ }
+ }
+ }
+
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * TickType_t xTaskGetTickCount( void );
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * TickType_t xTaskGetTickCountFromISR( void );
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * uint16_t uxTaskGetNumberOfTasks( void );
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks. A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery );
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery. A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL. INCLUDE_pcTaskGetTaskName must be
+ * set to 1 in FreeRTOSConfig.h for pcTaskGetTaskName() to be available.
+ *
+ * \defgroup pcTaskGetTaskName pcTaskGetTaskName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask. That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started. The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error. This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+ #if configUSE_APPLICATION_TASK_TAG == 1
+ /**
+ * task.h
+ * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+ *
+ * Sets pxHookFunction to be the task hook function used by the task xTask.
+ * Passing xTask as NULL has the effect of setting the calling tasks hook
+ * function.
+ */
+ void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+ /**
+ * task.h
+ * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+ *
+ * Returns the pxHookFunction value assigned to the task xTask.
+ */
+ TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+ #endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+/**
+ * task.h
+ * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+ *
+ * Calls the hook function associated with xTask. Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants. The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task. It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void );
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system. TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task. See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE: This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS. The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter. The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState(). This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+
+ // This example demonstrates how a human readable table of run time stats
+ // information is generated from raw data provided by uxTaskGetSystemState().
+ // The human readable table is written to pcWriteBuffer
+ void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ {
+ TaskStatus_t *pxTaskStatusArray;
+ volatile UBaseType_t uxArraySize, x;
+ uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+ // Make sure the write buffer does not contain a string.
+ *pcWriteBuffer = 0x00;
+
+ // Take a snapshot of the number of tasks in case it changes while this
+ // function is executing.
+ uxArraySize = uxTaskGetNumberOfTasks();
+
+ // Allocate a TaskStatus_t structure for each task. An array could be
+ // allocated statically at compile time.
+ pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+ if( pxTaskStatusArray != NULL )
+ {
+ // Generate raw status information about each task.
+ uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+ // For percentage calculations.
+ ulTotalRunTime /= 100UL;
+
+ // Avoid divide by zero errors.
+ if( ulTotalRunTime > 0 )
+ {
+ // For each populated position in the pxTaskStatusArray array,
+ // format the raw data as human readable ASCII data
+ for( x = 0; x < uxArraySize; x++ )
+ {
+ // What percentage of the total run time has the task used?
+ // This will always be rounded down to the nearest integer.
+ // ulTotalRunTimeDiv100 has already been divided by 100.
+ ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+ if( ulStatsAsPercentage > 0UL )
+ {
+ sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ }
+ else
+ {
+ // If the percentage is zero here then the task has
+ // consumed less than 1% of the total run time.
+ sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
+
+ pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+ }
+ }
+
+ // The array is no longer needed, free the memory it consumes.
+ vPortFree( pxTaskStatusArray );
+ }
+ }
+
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
+
+/**
+ * task. h
+ * void vTaskList( char *pcWriteBuffer );
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available. See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration. It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications. Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms. An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form. This buffer is assumed to be large
+ * enough to contain the generated report. Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * void vTaskGetRunTimeStats( char *pcWriteBuffer );
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available. The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively. The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration. It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task. The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications. Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms. An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form. This buffer is assumed to be large enough to
+ * contain the generated report. Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list. If a non-zero value is returned then a context switch is
+ * required because either:
+ * + A task was removed from a blocked list because its timeout had expired,
+ * or
+ * + Time slicing is in use and there is a task of equal priority to the
+ * currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks. The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur. This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/xTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order. It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * xTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority. In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Generic version of the task creation function which is in turn called by the
+ * xTaskCreate() and xTaskCreateRestricted() macros.
+ */
+BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods. When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section. It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered. eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only. Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+void *pvTaskIncrementMutexHeldCount( void );
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/cc3200/FreeRTOS/Source/include/timers.h b/cc3200/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000000..3949135db7
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1121 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+ #error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint +e956 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue. These are to
+be used solely through the macros that make up the public software timer API,
+as defined below. The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET ( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP ( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced. For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+typedef void * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( const char * const pcTimerName,
+ * TickType_t xTimerPeriodInTicks,
+ * UBaseType_t uxAutoReload,
+ * void * pvTimerID,
+ * TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance. This allocates the storage required
+ * by the new timer, initialises the new timers internal state, and returns a
+ * handle by which the new timer can be referenced.
+ *
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer. This is done
+ * purely to assist debugging. The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period. The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds. For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned. If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * // Optionally do something if the pxTimer parameter is NULL.
+ * configASSERT( pxTimer );
+ *
+ * // Which timer expired?
+ * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ * // Increment the number of times that pxTimer has expired.
+ * lExpireCounters[ lArrayIndex ] += 1;
+ *
+ * // If the timer has expired 10 times then stop it from running.
+ * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ * {
+ * // Do not use a block time if calling a timer API function from a
+ * // timer callback function, as doing so could cause a deadlock!
+ * xTimerStop( pxTimer, 0 );
+ * }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ * // Create then start some timers. Starting the timers before the scheduler
+ * // has been started means the timers will start running immediately that
+ * // the scheduler starts.
+ * for( x = 0; x < NUM_TIMERS; x++ )
+ * {
+ * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel.
+ * ( 100 * x ), // The timer period in ticks.
+ * pdTRUE, // The timers will auto-reload themselves when they expire.
+ * ( void * ) x, // Assign each timer a unique id equal to its array index.
+ * vTimerCallback // Each timer calls the same callback when it expires.
+ * );
+ *
+ * if( xTimers[ x ] == NULL )
+ * {
+ * // The timer was not created.
+ * }
+ * else
+ * {
+ * // Start the timer. No block time is specified, and even if one was
+ * // it would be ignored because the scheduler has not yet been
+ * // started.
+ * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ * {
+ * // The timer could not be set into the Active state.
+ * }
+ * }
+ * }
+ *
+ * // ...
+ * // Create tasks here.
+ * // ...
+ *
+ * // Starting the scheduler will start the timers running as they have already
+ * // been set into the active state.
+ * xTaskStartScheduler();
+ *
+ * // Should not reach here.
+ * for( ;; );
+ * }
+ * @endverbatim
+ */
+TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used within the callback function to identify which timer actually
+ * expired.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ * 1) It has been created but not started, or
+ * 2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state. The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant. A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ * {
+ * // xTimer is active, do something.
+ * }
+ * else
+ * {
+ * // xTimer is not active, do something else.
+ * }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * xTimerGetTimerDaemonTaskHandle() is only available if
+ * INCLUDE_xTimerGetTimerDaemonTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the timer service/daemon task. It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function. If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state. If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called. xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called. The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called. xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system. The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( TimerHandle_t xTimer,
+ * TickType_t xNewPeriod,
+ * TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds. For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called. xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue. When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system. The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created. If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted. If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ * {
+ * // xTimer is already active - delete it.
+ * xTimerDelete( xTimer );
+ * }
+ * else
+ * {
+ * // xTimer is not active, change its period to 500ms. This will also
+ * // cause the timer to start. Block for a maximum of 100 ticks if the
+ * // change period command cannot immediately be sent to the timer
+ * // command queue.
+ * if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ * {
+ * // The command was successfully sent.
+ * }
+ * else
+ * {
+ * // The command could not be sent, even after waiting for 100 ticks
+ * // to pass. Take appropriate action here.
+ * }
+ * }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called. xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system. The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task. Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue. The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code. The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function. If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called. If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state. If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called. xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed. pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called. The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off. In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer. In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * // The timer expired, therefore 5 seconds must have passed since a key
+ * // was pressed. Switch off the LCD back-light.
+ * vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ * // Ensure the LCD back-light is on, then reset the timer that is
+ * // responsible for turning the back-light off after 5 seconds of
+ * // key inactivity. Wait 10 ticks for the command to be successfully sent
+ * // if it cannot be sent immediately.
+ * vSetBacklightState( BACKLIGHT_ON );
+ * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ * {
+ * // The reset command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ * // Create then start the one-shot timer that is responsible for turning
+ * // the back-light off if no keys are pressed within a 5 second period.
+ * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel.
+ * ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ * pdFALSE, // The timer is a one-shot timer.
+ * 0, // The id is not used by the callback so can take any value.
+ * vBacklightTimerCallback // The callback function that switches the LCD back-light off.
+ * );
+ *
+ * if( xBacklightTimer == NULL )
+ * {
+ * // The timer was not created.
+ * }
+ * else
+ * {
+ * // Start the timer. No block time is specified, and even if one was
+ * // it would be ignored because the scheduler has not yet been
+ * // started.
+ * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ * {
+ * // The timer could not be set into the Active state.
+ * }
+ * }
+ *
+ * // ...
+ * // Create tasks here.
+ * // ...
+ *
+ * // Starting the scheduler will start the timer running as it has already
+ * // been set into the active state.
+ * xTaskStartScheduler();
+ *
+ * // Should not reach here.
+ * for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( TimerHandle_t xTimer,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state. If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function. If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue. pdPASS will be returned if the command was
+ * successfully sent to the timer command queue. When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called. The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created. When a
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off. In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer. In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * // The timer expired, therefore 5 seconds must have passed since a key
+ * // was pressed. Switch off the LCD back-light.
+ * vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // Ensure the LCD back-light is on, then restart the timer that is
+ * // responsible for turning the back-light off after 5 seconds of
+ * // key inactivity. This is an interrupt service routine so can only
+ * // call FreeRTOS API functions that end in "FromISR".
+ * vSetBacklightState( BACKLIGHT_ON );
+ *
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ * // as both cause the timer to re-calculate its expiry time.
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ * // declared (in this function).
+ * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The start command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // Perform the rest of the key processing here.
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( TimerHandle_t xTimer,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state. If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function. If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue. pdPASS will be returned if the command was
+ * successfully sent to the timer command queue. When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system. The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started. When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // The interrupt has occurred - simply stop the timer.
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ * // (within this function). As this is an interrupt service routine, only
+ * // FreeRTOS API functions that end in "FromISR" can be used.
+ * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The stop command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ * TickType_t xNewPeriod,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds. For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue. pdPASS will be returned if the
+ * command was successfully sent to the timer command queue. When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system. The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started. When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // The interrupt has occurred - change the period of xTimer to 500ms.
+ * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ * // (within this function). As this is an interrupt service routine, only
+ * // FreeRTOS API functions that end in "FromISR" can be used.
+ * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The command to change the timers period was not executed
+ * // successfully. Take appropriate action here.
+ * }
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( TimerHandle_t xTimer,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue. Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state. If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function. If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue. pdPASS will be returned if the command was
+ * successfully sent to the timer command queue. When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called. The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created. When a
+ * // key is pressed, an LCD back-light is switched on. If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off. In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer. In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * // The timer expired, therefore 5 seconds must have passed since a key
+ * // was pressed. Switch off the LCD back-light.
+ * vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ * // Ensure the LCD back-light is on, then reset the timer that is
+ * // responsible for turning the back-light off after 5 seconds of
+ * // key inactivity. This is an interrupt service routine so can only
+ * // call FreeRTOS API functions that end in "FromISR".
+ * vSetBacklightState( BACKLIGHT_ON );
+ *
+ * // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ * // as both cause the timer to re-calculate its expiry time.
+ * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ * // declared (in this function).
+ * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ * {
+ * // The reset command was not executed successfully. Take appropriate
+ * // action here.
+ * }
+ *
+ * // Perform the rest of the key processing here.
+ *
+ * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ * // should be performed. The syntax required to perform a context switch
+ * // from inside an ISR varies from port to port, and from compiler to
+ * // compiler. Inspect the demos for the port you are using to find the
+ * // actual syntax required.
+ * if( xHigherPriorityTaskWoken != pdFALSE )
+ * {
+ * // Call the interrupt safe yield function here (actual function
+ * // depends on the FreeRTOS port being used).
+ * }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ * void *pvParameter1,
+ * uint32_t ulParameter2,
+ * BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic. In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function. This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task. The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task. If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits. For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The callback function that will execute in the context of the daemon task.
+ * // Note callback functions must all use this same prototype.
+ * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ * {
+ * BaseType_t xInterfaceToService;
+ *
+ * // The interface that requires servicing is passed in the second
+ * // parameter. The first parameter is not used in this case.
+ * xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ * // ...Perform the processing here...
+ * }
+ *
+ * // An ISR that receives data packets from multiple interfaces
+ * void vAnISR( void )
+ * {
+ * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ * // Query the hardware to determine which interface needs processing.
+ * xInterfaceToService = prvCheckInterfaces();
+ *
+ * // The actual processing is to be deferred to a task. Request the
+ * // vProcessInterface() callback function is executed, passing in the
+ * // number of the interface that needs processing. The interface to
+ * // service is passed in the second parameter. The first parameter is
+ * // not used in this case.
+ * xHigherPriorityTaskWoken = pdFALSE;
+ * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ * // switch should be requested. The macro used is port specific and will
+ * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ * // the documentation page for the port being used.
+ * portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken );
+
+ /**
+ * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+ * void *pvParameter1,
+ * uint32_t ulParameter2,
+ * TickType_t xTicksToWait );
+ *
+ *
+ * Used to defer the execution of a function to the RTOS daemon task (the timer
+ * service task, hence this function is implemented in timers.c and is prefixed
+ * with 'Timer').
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task. The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param xTicksToWait Calling this function will result in a message being
+ * sent to the timer daemon task on a queue. xTicksToWait is the amount of
+ * time the calling task should remain in the Blocked state (so not using any
+ * processing time) for space to become available on the timer queue if the
+ * queue is found to be full.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
+
+/**
+ * const char * const pcTimerGetTimerName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetTimerName( TimerHandle_t xTimer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+
diff --git a/cc3200/FreeRTOS/Source/list.c b/cc3200/FreeRTOS/Source/list.c
new file mode 100644
index 0000000000..701472a482
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/list.c
@@ -0,0 +1,204 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#include
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+ /* The list structure contains a list item which is used to mark the
+ end of the list. To initialise the list the list end is inserted
+ as the only list entry. */
+ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+
+ /* The list end value is the highest possible value in the list to
+ ensure it remains at the end of the list. */
+ pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+ /* The list end next and previous pointers point to itself so we know
+ when the list is empty. */
+ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+
+ pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+ /* Make sure the list item is not recorded as being on a list. */
+ pxItem->pvContainer = NULL;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+ /* Insert a new list item into pxList, but rather than sort the list,
+ makes the new list item the last item to be removed by a call to
+ listGET_OWNER_OF_NEXT_ENTRY(). */
+ pxNewListItem->pxNext = pxIndex;
+ pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+ pxIndex->pxPrevious->pxNext = pxNewListItem;
+ pxIndex->pxPrevious = pxNewListItem;
+
+ /* Remember which list the item is in. */
+ pxNewListItem->pvContainer = ( void * ) pxList;
+
+ ( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+ /* Insert the new list item into the list, sorted in xItemValue order.
+
+ If the list already contains a list item with the same item value then
+ the new list item should be placed after it. This ensures that TCB's which
+ are stored in ready lists (all of which have the same xItemValue value)
+ get an equal share of the CPU. However, if the xItemValue is the same as
+ the back marker the iteration loop below will not end. This means we need
+ to guard against this by checking the value first and modifying the
+ algorithm slightly if necessary. */
+ if( xValueOfInsertion == portMAX_DELAY )
+ {
+ pxIterator = pxList->xListEnd.pxPrevious;
+ }
+ else
+ {
+ /* *** NOTE ***********************************************************
+ If you find your application is crashing here then likely causes are:
+ 1) Stack overflow -
+ see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+ 2) Incorrect interrupt priority assignment, especially on Cortex-M3
+ parts where numerically high priority values denote low actual
+ interrupt priorities, which can seem counter intuitive. See
+ configMAX_SYSCALL_INTERRUPT_PRIORITY on http://www.freertos.org/a00110.html
+ 3) Calling an API function from within a critical section or when
+ the scheduler is suspended, or calling an API function that does
+ not end in "FromISR" from an interrupt.
+ 4) Using a queue or semaphore before it has been initialised or
+ before the scheduler has been started (are interrupts firing
+ before vTaskStartScheduler() has been called?).
+ See http://www.freertos.org/FAQHelp.html for more tips, and ensure
+ configASSERT() is defined! http://www.freertos.org/a00110.html#configASSERT
+ **********************************************************************/
+
+ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
+ {
+ /* There is nothing to do here, we are just iterating to the
+ wanted insertion position. */
+ }
+ }
+
+ pxNewListItem->pxNext = pxIterator->pxNext;
+ pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+ pxNewListItem->pxPrevious = pxIterator;
+ pxIterator->pxNext = pxNewListItem;
+
+ /* Remember which list the item is in. This allows fast removal of the
+ item later. */
+ pxNewListItem->pvContainer = ( void * ) pxList;
+
+ ( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in. Obtain the list from the list
+item. */
+List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+
+ pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+ pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+ /* Make sure the index is left pointing to a valid item. */
+ if( pxList->pxIndex == pxItemToRemove )
+ {
+ pxList->pxIndex = pxItemToRemove->pxPrevious;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ pxItemToRemove->pvContainer = NULL;
+ ( pxList->uxNumberOfItems )--;
+
+ return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
new file mode 100644
index 0000000000..b287f7df99
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -0,0 +1,742 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined. The value should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+ #define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+ #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+ /* Ensure the SysTick is clocked at the same frequency as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
+#else
+ /* The way the SysTick is clocked is not modified in case it is not the same
+ as the core. */
+ #define portNVIC_SYSTICK_CLK_BIT ( 0 )
+#endif
+
+/* Constants required to manipulate the core. Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
+#define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT ( 8UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR ( 0x01000000UL )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR ( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case is messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+ #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
+#else
+ #define portTASK_RETURN_ADDRESS prvTaskExitError
+#endif
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts. The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+ static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+ static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+ static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+ static uint8_t ucMaxSysCallPriority = 0;
+ static uint32_t ulMaxPRIGROUPValue = 0;
+ static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ /* Simulate the stack frame as it would be created by a context switch
+ interrupt. */
+ pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+ *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
+ pxTopOfStack--;
+ *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
+ *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+ pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+ return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+ /* A function that implements a task must not exit or attempt to return to
+ its caller as there is nothing to return to. If a task wants to exit it
+ should instead call vTaskDelete( NULL ).
+
+ Artificially force an assert() to be triggered if configASSERT() is
+ defined, then stop here so application writers can catch the error. */
+ configASSERT( uxCriticalNesting == ~0UL );
+ portDISABLE_INTERRUPTS();
+ for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+ __asm volatile (
+ " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
+ " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+ " msr psp, r0 \n" /* Restore the task stack pointer. */
+ " isb \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " orr r14, #0xd \n"
+ " bx r14 \n"
+ " \n"
+ " .align 2 \n"
+ "pxCurrentTCBConst2: .word pxCurrentTCB \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+ __asm volatile(
+ " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
+ " ldr r0, [r0] \n"
+ " ldr r0, [r0] \n"
+ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
+ " cpsie i \n" /* Globally enable interrupts. */
+ " cpsie f \n"
+ " dsb \n"
+ " isb \n"
+ " svc 0 \n" /* System call to start first task. */
+ " nop \n"
+ );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+ /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+ See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+ configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+ #if( configASSERT_DEFINED == 1 )
+ {
+ volatile uint32_t ulOriginalPriority;
+ volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+ volatile uint8_t ucMaxPriorityValue;
+
+ /* Determine the maximum priority from which ISR safe FreeRTOS API
+ functions can be called. ISR safe functions are those that end in
+ "FromISR". FreeRTOS maintains separate thread and ISR API functions to
+ ensure interrupt entry is as fast and simple as possible.
+
+ Save the interrupt priority value that is about to be clobbered. */
+ ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+ /* Determine the number of priority bits available. First write to all
+ possible bits. */
+ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+ /* Read the value back to see how many bits stuck. */
+ ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+ /* Use the same mask on the maximum system call priority. */
+ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+ /* Calculate the maximum acceptable priority group value for the number
+ of bits read back. */
+ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+ while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+ {
+ ulMaxPRIGROUPValue--;
+ ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+ }
+
+ /* Shift the priority group value back to its position within the AIRCR
+ register. */
+ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+ ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+ /* Restore the clobbered interrupt priority register to its original
+ value. */
+ *pucFirstUserPriorityRegister = ulOriginalPriority;
+ }
+ #endif /* conifgASSERT_DEFINED */
+
+ /* Make PendSV and SysTick the lowest priority interrupts. */
+ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+ portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+ /* Start the timer that generates the tick ISR. Interrupts are disabled
+ here already. */
+ vPortSetupTimerInterrupt();
+
+ /* Initialise the critical nesting count ready for the first task. */
+ uxCriticalNesting = 0;
+
+ /* Start the first task. */
+ prvPortStartFirstTask();
+
+ /* Should never get here as the tasks will now be executing! Call the task
+ exit error function to prevent compiler warnings about a static function
+ not being called in the case that the application writer overrides this
+ functionality by defining configTASK_RETURN_ADDRESS. */
+ prvTaskExitError();
+
+ /* Should not get here! */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+ /* Not implemented in ports where there is nothing to return to.
+ Artificially force an assert. */
+ configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+ /* Set a PendSV to request a context switch. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+ /* Barriers are normally not required but do ensure the code is completely
+ within the specified behaviour for the architecture. */
+ __asm volatile( "dsb" );
+ __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+ portDISABLE_INTERRUPTS();
+ uxCriticalNesting++;
+ __asm volatile( "dsb" );
+ __asm volatile( "isb" );
+
+ /* This is not the interrupt safe version of the enter critical function so
+ assert() if it is being called from an interrupt context. Only API
+ functions that end in "FromISR" can be used in an interrupt. Only assert if
+ the critical nesting count is 1 to protect against recursive calls if the
+ assert function also uses a critical section. */
+ if( uxCriticalNesting == 1 )
+ {
+ configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+ configASSERT( uxCriticalNesting );
+ uxCriticalNesting--;
+ if( uxCriticalNesting == 0 )
+ {
+ portENABLE_INTERRUPTS();
+ }
+}
+/*-----------------------------------------------------------*/
+
+__attribute__(( naked )) uint32_t ulPortSetInterruptMask( void )
+{
+ __asm volatile \
+ ( \
+ " mrs r0, basepri \n" \
+ " mov r1, %0 \n" \
+ " msr basepri, r1 \n" \
+ " bx lr \n" \
+ :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
+ );
+
+ /* This return will not be reached but is necessary to prevent compiler
+ warnings. */
+ return 0;
+}
+/*-----------------------------------------------------------*/
+
+__attribute__(( naked )) void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+ __asm volatile \
+ ( \
+ " msr basepri, r0 \n" \
+ " bx lr \n" \
+ :::"r0" \
+ );
+
+ /* Just to avoid compiler warnings. */
+ ( void ) ulNewMaskValue;
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+ /* This is a naked function. */
+
+ __asm volatile
+ (
+ " mrs r0, psp \n"
+ " isb \n"
+ " \n"
+ " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
+ " ldr r2, [r3] \n"
+ " \n"
+ " stmdb r0!, {r4-r11} \n" /* Save the remaining registers. */
+ " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
+ " \n"
+ " stmdb sp!, {r3, r14} \n"
+ " mov r0, %0 \n"
+ " msr basepri, r0 \n"
+ " bl vTaskSwitchContext \n"
+ " mov r0, #0 \n"
+ " msr basepri, r0 \n"
+ " ldmia sp!, {r3, r14} \n"
+ " \n" /* Restore the context, including the critical nesting count. */
+ " ldr r1, [r3] \n"
+ " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
+ " ldmia r0!, {r4-r11} \n" /* Pop the registers. */
+ " msr psp, r0 \n"
+ " isb \n"
+ " bx r14 \n"
+ " \n"
+ " .align 2 \n"
+ "pxCurrentTCBConst: .word pxCurrentTCB \n"
+ ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+ );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+ /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+ executes all interrupts must be unmasked. There is therefore no need to
+ save and then restore the interrupt mask value as its value is already
+ known. */
+ ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Increment the RTOS tick. */
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ /* A context switch is required. Context switching is performed in
+ the PendSV interrupt. Pend the PendSV interrupt. */
+ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+ __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+ {
+ uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+ TickType_t xModifiableIdleTime;
+
+ /* Make sure the SysTick reload value does not overflow the counter. */
+ if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+ {
+ xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+ }
+
+ /* Stop the SysTick momentarily. The time the SysTick is stopped for
+ is accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Calculate the reload value required to wait xExpectedIdleTime
+ tick periods. -1 is used because this code will execute part way
+ through one of the tick periods. */
+ ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+ if( ulReloadValue > ulStoppedTimerCompensation )
+ {
+ ulReloadValue -= ulStoppedTimerCompensation;
+ }
+
+ /* Enter a critical section but don't use the taskENTER_CRITICAL()
+ method as that will mask interrupts that should exit sleep mode. */
+ __asm volatile( "cpsid i" );
+
+ /* If a context switch is pending or a task is waiting for the scheduler
+ to be unsuspended then abandon the low power entry. */
+ if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+ {
+ /* Restart from whatever is left in the count register to complete
+ this tick period. */
+ portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Reset the reload register to the value required for normal tick
+ periods. */
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+ /* Re-enable interrupts - see comments above the cpsid instruction()
+ above. */
+ __asm volatile( "cpsie i" );
+ }
+ else
+ {
+ /* Set the new reload value. */
+ portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+ /* Clear the SysTick count flag and set the count value back to
+ zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+ /* Restart SysTick. */
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+ /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+ set its parameter to 0 to indicate that its implementation contains
+ its own wait for interrupt or wait for event instruction, and so wfi
+ should not be executed again. However, the original expected idle
+ time variable must remain unmodified, so a copy is taken. */
+ xModifiableIdleTime = xExpectedIdleTime;
+ configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+ if( xModifiableIdleTime > 0 )
+ {
+ __asm volatile( "dsb" );
+ __asm volatile( "wfi" );
+ __asm volatile( "isb" );
+ }
+ configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+ /* Stop SysTick. Again, the time the SysTick is stopped for is
+ accounted for as best it can be, but using the tickless mode will
+ inevitably result in some tiny drift of the time maintained by the
+ kernel with respect to calendar time. */
+ ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
+ portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
+
+ /* Re-enable interrupts - see comments above the cpsid instruction()
+ above. */
+ __asm volatile( "cpsie i" );
+
+ if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+ {
+ uint32_t ulCalculatedLoadValue;
+
+ /* The tick interrupt has already executed, and the SysTick
+ count reloaded with ulReloadValue. Reset the
+ portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+ period. */
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+ /* Don't allow a tiny value, or values that have somehow
+ underflowed because the post sleep hook did something
+ that took too long. */
+ if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+ {
+ ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+ }
+
+ portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+ /* The tick interrupt handler will already have pended the tick
+ processing in the kernel. As the pending tick will be
+ processed as soon as this function exits, the tick value
+ maintained by the tick is stepped forward by one less than the
+ time spent waiting. */
+ ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+ }
+ else
+ {
+ /* Something other than the tick interrupt ended the sleep.
+ Work out how long the sleep lasted rounded to complete tick
+ periods (not the ulReload value which accounted for part
+ ticks). */
+ ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+ /* How many complete tick periods passed while the processor
+ was waiting? */
+ ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+ /* The reload value is set to whatever fraction of a single tick
+ period remains. */
+ portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+ }
+
+ /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+ again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+ value. The critical section is used to ensure the tick interrupt
+ can only execute once in the case that the reload register is near
+ zero. */
+ portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+ portENTER_CRITICAL();
+ {
+ portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+ vTaskStepTick( ulCompleteTickPeriods );
+ portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+ }
+ portEXIT_CRITICAL();
+ }
+ }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+ /* Calculate the constants required to configure the tick interrupt. */
+ #if configUSE_TICKLESS_IDLE == 1
+ {
+ ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+ xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+ ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+
+ /* Configure SysTick to interrupt at the requested rate. */
+ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+ portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+ void vPortValidateInterruptPriority( void )
+ {
+ uint32_t ulCurrentInterrupt;
+ uint8_t ucCurrentPriority;
+
+ /* Obtain the number of the currently executing interrupt. */
+ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+
+ /* Is the interrupt number a user defined interrupt? */
+ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+ {
+ /* Look up the interrupt's priority. */
+ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+ /* The following assertion will fail if a service routine (ISR) for
+ an interrupt that has been assigned a priority above
+ configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+ function. ISR safe FreeRTOS API functions must *only* be called
+ from interrupts that have been assigned a priority at or below
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ Numerically low interrupt priority numbers represent logically high
+ interrupt priorities, therefore the priority of the interrupt must
+ be set to a value equal to or numerically *higher* than
+ configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+ Interrupts that use the FreeRTOS API must not be left at their
+ default priority of zero as that is the highest possible priority,
+ which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+ and therefore also guaranteed to be invalid.
+
+ FreeRTOS maintains separate thread and ISR API functions to ensure
+ interrupt entry is as fast and simple as possible.
+
+ The following links provide detailed information:
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html
+ http://www.freertos.org/FAQHelp.html */
+ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+ }
+
+ /* Priority grouping: The interrupt controller (NVIC) allows the bits
+ that define each interrupt's priority to be split between bits that
+ define the interrupt's pre-emption priority bits and bits that define
+ the interrupt's sub-priority. For simplicity all bits must be defined
+ to be pre-emption priority bits. The following assertion will fail if
+ this is not the case (if some bits represent a sub-priority).
+
+ If the application only uses CMSIS libraries for interrupt
+ configuration then the correct setting can be achieved on all Cortex-M
+ devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+ scheduler. Note however that some vendor specific peripheral libraries
+ assume a non-zero priority group setting, in which cases using a value
+ of zero will result in unpredicable behaviour. */
+ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+ }
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
new file mode 100644
index 0000000000..f497393e60
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -0,0 +1,197 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR char
+#define portFLOAT float
+#define portDOUBLE double
+#define portLONG long
+#define portSHORT short
+#define portSTACK_TYPE uint32_t
+#define portBASE_TYPE long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+ typedef uint16_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+ typedef uint32_t TickType_t;
+ #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH ( -1 )
+#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT 8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+#define portNVIC_INT_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK ( 0x1FUL )
+#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL )
+#define portYIELD() vPortYield()
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
+#define portDISABLE_INTERRUPTS() ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS() vPortClearInterruptMask(0)
+#define portENTER_CRITICAL() vPortEnterCritical()
+#define portEXIT_CRITICAL() vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. These are
+not necessary for to use this port. They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+ extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+ #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+ #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+ /* Generic helper function. */
+ __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+ {
+ uint8_t ucReturn;
+
+ __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+ return ucReturn;
+ }
+
+ /* Check the configuration. */
+ #if( configMAX_PRIORITIES > 32 )
+ #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+ #endif
+
+ /* Store/clear the ready priorities in a bit map. */
+ #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+ #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+ /*-----------------------------------------------------------*/
+
+ #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+ void vPortValidateInterruptPriority( void );
+ #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c b/cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000000..94551c25c3
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,465 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize * 2 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE ( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ] __attribute__ ((section (".rtos_heap")))
+__attribute__((aligned (8)));
+
+/* Define the linked list structure. This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+ struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */
+ size_t xBlockSize; /*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks. The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application. When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+ vTaskSuspendAll();
+ {
+ /* If this is the first call to malloc then the heap will require
+ initialisation to setup the list of free blocks. */
+ if( pxEnd == NULL )
+ {
+ prvHeapInit();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Check the requested block size is not so large that the top bit is
+ set. The top bit of the block size member of the BlockLink_t structure
+ is used to determine who owns the block - the application or the
+ kernel, so it must be free. */
+ if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+ {
+ /* The wanted size is increased so it can contain a BlockLink_t
+ structure in addition to the requested amount of bytes. */
+ if( xWantedSize > 0 )
+ {
+ xWantedSize += xHeapStructSize;
+
+ /* Ensure that blocks are always aligned to the required number
+ of bytes. */
+ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+ {
+ /* Byte alignment required. */
+ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+ configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+ {
+ /* Traverse the list from the start (lowest address) block until
+ one of adequate size is found. */
+ pxPreviousBlock = &xStart;
+ pxBlock = xStart.pxNextFreeBlock;
+ while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+ {
+ pxPreviousBlock = pxBlock;
+ pxBlock = pxBlock->pxNextFreeBlock;
+ }
+
+ /* If the end marker was reached then a block of adequate size
+ was not found. */
+ if( pxBlock != pxEnd )
+ {
+ /* Return the memory space pointed to - jumping over the
+ BlockLink_t structure at its start. */
+ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+ /* This block is being returned for use so must be taken out
+ of the list of free blocks. */
+ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+ /* If the block is larger than required it can be split into
+ two. */
+ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+ {
+ /* This block is to be split into two. Create a new
+ block following the number of bytes requested. The void
+ cast is used to prevent byte alignment warnings from the
+ compiler. */
+ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+ configASSERT( ( ( ( uint32_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+ /* Calculate the sizes of two blocks split from the
+ single block. */
+ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+ pxBlock->xBlockSize = xWantedSize;
+
+ /* Insert the new block into the list of free blocks. */
+ prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+ if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+ {
+ xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The block is being returned - it is allocated and owned
+ by the application and has no "next" block. */
+ pxBlock->xBlockSize |= xBlockAllocatedBit;
+ pxBlock->pxNextFreeBlock = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceMALLOC( pvReturn, xWantedSize );
+ }
+ ( void ) xTaskResumeAll();
+
+ #if( configUSE_MALLOC_FAILED_HOOK == 1 )
+ {
+ if( pvReturn == NULL )
+ {
+ extern void vApplicationMallocFailedHook( void );
+ vApplicationMallocFailedHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ configASSERT( ( ( ( uint32_t ) pvReturn ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+ return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+ if( pv != NULL )
+ {
+ /* The memory being freed will have an BlockLink_t structure immediately
+ before it. */
+ puc -= xHeapStructSize;
+
+ /* This casting is to keep the compiler from issuing warnings. */
+ pxLink = ( void * ) puc;
+
+ /* Check the block is actually allocated. */
+ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+ configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+ if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+ {
+ if( pxLink->pxNextFreeBlock == NULL )
+ {
+ /* The block is being returned to the heap - it is no longer
+ allocated. */
+ pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+ vTaskSuspendAll();
+ {
+ /* Add this block to the list of free blocks. */
+ xFreeBytesRemaining += pxLink->xBlockSize;
+ traceFREE( pv, pxLink->xBlockSize );
+ prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+ }
+ ( void ) xTaskResumeAll();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+ return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+ return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+ /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+uint32_t ulAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+ /* Ensure the heap starts on a correctly aligned boundary. */
+ ulAddress = ( uint32_t ) ucHeap;
+
+ if( ( ulAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+ {
+ ulAddress += ( portBYTE_ALIGNMENT - 1 );
+ ulAddress &= ~portBYTE_ALIGNMENT_MASK;
+ xTotalHeapSize -= ulAddress - ( uint32_t ) ucHeap;
+ }
+
+ pucAlignedHeap = ( uint8_t * ) ulAddress;
+
+ /* xStart is used to hold a pointer to the first item in the list of free
+ blocks. The void cast is used to prevent compiler warnings. */
+ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+ xStart.xBlockSize = ( size_t ) 0;
+
+ /* pxEnd is used to mark the end of the list of free blocks and is inserted
+ at the end of the heap space. */
+ ulAddress = ( ( uint32_t ) pucAlignedHeap ) + xTotalHeapSize;
+ ulAddress -= xHeapStructSize;
+ ulAddress &= ~portBYTE_ALIGNMENT_MASK;
+ pxEnd = ( void * ) ulAddress;
+ pxEnd->xBlockSize = 0;
+ pxEnd->pxNextFreeBlock = NULL;
+
+ /* To start with there is a single free block that is sized to take up the
+ entire heap space, minus the space taken by pxEnd. */
+ pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+ pxFirstFreeBlock->xBlockSize = ulAddress - ( uint32_t ) pxFirstFreeBlock;
+ pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+ /* Only one block exists - and it covers the entire usable heap space. */
+ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+ xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+ /* Work out the position of the top bit in a size_t variable. */
+ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+ /* Iterate through the list until a block is found that has a higher address
+ than the block being inserted. */
+ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+ {
+ /* Nothing to do here, just iterate to the right position. */
+ }
+
+ /* Do the block being inserted, and the block it is being inserted after
+ make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxIterator;
+ if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+ {
+ pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+ pxBlockToInsert = pxIterator;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Do the block being inserted, and the block it is being inserted before
+ make a contiguous block of memory? */
+ puc = ( uint8_t * ) pxBlockToInsert;
+ if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+ {
+ if( pxIterator->pxNextFreeBlock != pxEnd )
+ {
+ /* Form one big block from the two blocks. */
+ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxEnd;
+ }
+ }
+ else
+ {
+ pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+ }
+
+ /* If the block being inserted plugged a gab, so was merged with the block
+ before and the block after, then it's pxNextFreeBlock pointer will have
+ already been set, and should not be set here as that would make it point
+ to itself. */
+ if( pxIterator != pxBlockToInsert )
+ {
+ pxIterator->pxNextFreeBlock = pxBlockToInsert;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+}
+
diff --git a/cc3200/FreeRTOS/Source/queue.c b/cc3200/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000000..5e5250d00a
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/queue.c
@@ -0,0 +1,2438 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+#include
+#include
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+ #include "croutine.h"
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* Constants used with the xRxLock and xTxLock structure members. */
+#define queueUNLOCKED ( ( BaseType_t ) -1 )
+#define queueLOCKED_UNMODIFIED ( ( BaseType_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area. When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+pcTail pointer actually points to the mutex holder (if any). Map alternative
+names to the pcHead and pcTail structure members to ensure the readability of
+the code is maintained despite this dual use of two structure members. An
+alternative implementation would be to use a union, but use of a union is
+against the coding standard (although an exception to the standard has been
+permitted where the dual use also significantly changes the type of the
+structure member). */
+#define pxMutexHolder pcTail
+#define uxQueueType pcHead
+#define queueQUEUE_IS_MUTEX NULL
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+ /* If the cooperative scheduler is being used then a yield should not be
+ performed just because a higher priority task has been woken. */
+ #define queueYIELD_IF_USING_PREEMPTION()
+#else
+ #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.
+ */
+typedef struct QueueDefinition
+{
+ int8_t *pcHead; /*< Points to the beginning of the queue storage area. */
+ int8_t *pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+ int8_t *pcWriteTo; /*< Points to the free next place in the storage area. */
+
+ union /* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
+ {
+ int8_t *pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+ UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+ } u;
+
+ List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */
+ List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */
+
+ volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+ UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+ UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */
+
+ volatile BaseType_t xRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
+ volatile BaseType_t xTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxQueueNumber;
+ uint8_t ucQueueType;
+ #endif
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ struct QueueDefinition *pxQueueSetContainer;
+ #endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures. It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ /* The type stored within the queue registry array. This allows a name
+ to be assigned to each queue making kernel aware debugging a little
+ more user friendly. */
+ typedef struct QUEUE_REGISTRY_ITEM
+ {
+ const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ QueueHandle_t xHandle;
+ } xQueueRegistryItem;
+
+ /* The old xQueueRegistryItem name is maintained above then typedefed to the
+ new xQueueRegistryItem name below to enable the use of older kernel aware
+ debuggers. */
+ typedef xQueueRegistryItem QueueRegistryItem_t;
+
+ /* The queue registry is simply an array of QueueRegistryItem_t structures.
+ The pcQueueName member of a structure being NULL is indicative of the
+ array position being vacant. */
+ QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists. If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking. When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+ /*
+ * Checks to see if a queue is a member of a queue set, and if so, notifies
+ * the queue set that the queue contains data.
+ */
+ static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked. Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue ) \
+ taskENTER_CRITICAL(); \
+ { \
+ if( ( pxQueue )->xRxLock == queueUNLOCKED ) \
+ { \
+ ( pxQueue )->xRxLock = queueLOCKED_UNMODIFIED; \
+ } \
+ if( ( pxQueue )->xTxLock == queueUNLOCKED ) \
+ { \
+ ( pxQueue )->xTxLock = queueLOCKED_UNMODIFIED; \
+ } \
+ } \
+ taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+
+ taskENTER_CRITICAL();
+ {
+ pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+ pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+ pxQueue->pcWriteTo = pxQueue->pcHead;
+ pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
+ pxQueue->xRxLock = queueUNLOCKED;
+ pxQueue->xTxLock = queueUNLOCKED;
+
+ if( xNewQueue == pdFALSE )
+ {
+ /* If there are tasks blocked waiting to read from the queue, then
+ the tasks will remain blocked as after this function exits the queue
+ will still be empty. If there are tasks blocked waiting to write to
+ the queue, then one should be unblocked as after this function exits
+ it will be possible to write to it. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
+ {
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Ensure the event queues start in the correct state. */
+ vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+ vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* A value is returned for calling semantic consistency with previous
+ versions. */
+ return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+{
+Queue_t *pxNewQueue;
+size_t xQueueSizeInBytes;
+QueueHandle_t xReturn = NULL;
+
+ /* Remove compiler warnings about unused parameters should
+ configUSE_TRACE_FACILITY not be set to 1. */
+ ( void ) ucQueueType;
+
+ /* Allocate the new queue structure. */
+ if( uxQueueLength > ( UBaseType_t ) 0 )
+ {
+ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );
+ if( pxNewQueue != NULL )
+ {
+ /* Create the list of pointers to queue items. The queue is one byte
+ longer than asked for to make wrap checking easier/faster. */
+ xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ) + ( size_t ) 1; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ pxNewQueue->pcHead = ( int8_t * ) pvPortMalloc( xQueueSizeInBytes );
+ if( pxNewQueue->pcHead != NULL )
+ {
+ /* Initialise the queue members as described above where the
+ queue type is defined. */
+ pxNewQueue->uxLength = uxQueueLength;
+ pxNewQueue->uxItemSize = uxItemSize;
+ ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ pxNewQueue->ucQueueType = ucQueueType;
+ }
+ #endif /* configUSE_TRACE_FACILITY */
+
+ #if( configUSE_QUEUE_SETS == 1 )
+ {
+ pxNewQueue->pxQueueSetContainer = NULL;
+ }
+ #endif /* configUSE_QUEUE_SETS */
+
+ traceQUEUE_CREATE( pxNewQueue );
+ xReturn = pxNewQueue;
+ }
+ else
+ {
+ traceQUEUE_CREATE_FAILED( ucQueueType );
+ vPortFree( pxNewQueue );
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ configASSERT( xReturn );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+ {
+ Queue_t *pxNewQueue;
+
+ /* Prevent compiler warnings about unused parameters if
+ configUSE_TRACE_FACILITY does not equal 1. */
+ ( void ) ucQueueType;
+
+ /* Allocate the new queue structure. */
+ pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) );
+ if( pxNewQueue != NULL )
+ {
+ /* Information required for priority inheritance. */
+ pxNewQueue->pxMutexHolder = NULL;
+ pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+ /* Queues used as a mutex no data is actually copied into or out
+ of the queue. */
+ pxNewQueue->pcWriteTo = NULL;
+ pxNewQueue->u.pcReadFrom = NULL;
+
+ /* Each mutex has a length of 1 (like a binary semaphore) and
+ an item size of 0 as nothing is actually copied into or out
+ of the mutex. */
+ pxNewQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+ pxNewQueue->uxLength = ( UBaseType_t ) 1U;
+ pxNewQueue->uxItemSize = ( UBaseType_t ) 0U;
+ pxNewQueue->xRxLock = queueUNLOCKED;
+ pxNewQueue->xTxLock = queueUNLOCKED;
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ pxNewQueue->ucQueueType = ucQueueType;
+ }
+ #endif
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ pxNewQueue->pxQueueSetContainer = NULL;
+ }
+ #endif
+
+ /* Ensure the event queues start with the correct state. */
+ vListInitialise( &( pxNewQueue->xTasksWaitingToSend ) );
+ vListInitialise( &( pxNewQueue->xTasksWaitingToReceive ) );
+
+ traceCREATE_MUTEX( pxNewQueue );
+
+ /* Start with the semaphore in the expected state. */
+ ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+ }
+ else
+ {
+ traceCREATE_MUTEX_FAILED();
+ }
+
+ configASSERT( pxNewQueue );
+ return pxNewQueue;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+ void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+ {
+ void *pxReturn;
+
+ /* This function is called by xSemaphoreGetMutexHolder(), and should not
+ be called directly. Note: This is a good way of determining if the
+ calling task is the mutex holder, but not a good way of determining the
+ identity of the mutex holder, as the holder may change between the
+ following critical section exiting and the function returning. */
+ taskENTER_CRITICAL();
+ {
+ if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+ }
+ else
+ {
+ pxReturn = NULL;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return pxReturn;
+ } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+ configASSERT( pxMutex );
+
+ /* If this is the task that holds the mutex then pxMutexHolder will not
+ change outside of this task. If this task does not hold the mutex then
+ pxMutexHolder can never coincidentally equal the tasks handle, and as
+ this is the only condition we are interested in it does not matter if
+ pxMutexHolder is accessed simultaneously by another task. Therefore no
+ mutual exclusion is required to test the pxMutexHolder variable. */
+ if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
+ {
+ traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+ /* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
+ the task handle, therefore no underflow check is required. Also,
+ uxRecursiveCallCount is only modified by the mutex holder, and as
+ there can only be one, no mutual exclusion is required to modify the
+ uxRecursiveCallCount member. */
+ ( pxMutex->u.uxRecursiveCallCount )--;
+
+ /* Have we unwound the call count? */
+ if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+ {
+ /* Return the mutex. This will automatically unblock any other
+ task that might be waiting to access the mutex. */
+ ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ /* The mutex cannot be given because the calling task is not the
+ holder. */
+ xReturn = pdFAIL;
+
+ traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+ BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+ configASSERT( pxMutex );
+
+ /* Comments regarding mutual exclusion as per those within
+ xQueueGiveMutexRecursive(). */
+
+ traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+ if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+ {
+ ( pxMutex->u.uxRecursiveCallCount )++;
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );
+
+ /* pdPASS will only be returned if the mutex was successfully
+ obtained. The calling task may have entered the Blocked state
+ before reaching here. */
+ if( xReturn == pdPASS )
+ {
+ ( pxMutex->u.uxRecursiveCallCount )++;
+ }
+ else
+ {
+ traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+ }
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_COUNTING_SEMAPHORES == 1 )
+
+ QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+ {
+ QueueHandle_t xHandle;
+
+ configASSERT( uxMaxCount != 0 );
+ configASSERT( uxInitialCount <= uxMaxCount );
+
+ xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+ if( xHandle != NULL )
+ {
+ ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+ traceCREATE_COUNTING_SEMAPHORE();
+ }
+ else
+ {
+ traceCREATE_COUNTING_SEMAPHORE_FAILED();
+ }
+
+ configASSERT( xHandle );
+ return xHandle;
+ }
+
+#endif /* configUSE_COUNTING_SEMAPHORES */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+
+ /* This function relaxes the coding standard somewhat to allow return
+ statements within the function itself. This is done in the interest
+ of execution time efficiency. */
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* Is there room on the queue now? The running task must be
+ the highest priority task wanting to access the queue. If
+ the head item in the queue is to be overwritten then it does
+ not matter if the queue is full. */
+ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ {
+ traceQUEUE_SEND( pxQueue );
+ xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
+ {
+ if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )
+ {
+ /* The queue is a member of a queue set, and posting
+ to the queue set caused a higher priority task to
+ unblock. A context switch is required. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* If there was a task waiting for data to arrive on the
+ queue then unblock it now. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
+ {
+ /* The unblocked task has a priority higher than
+ our own so yield immediately. Yes it is ok to
+ do this from within the critical section - the
+ kernel takes care of that. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( xYieldRequired != pdFALSE )
+ {
+ /* This path is a special case that will only get
+ executed if the task was holding multiple mutexes
+ and the mutexes were given back in an order that is
+ different to that in which they were taken. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ /* If there was a task waiting for data to arrive on the
+ queue then unblock it now. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
+ {
+ /* The unblocked task has a priority higher than
+ our own so yield immediately. Yes it is ok to do
+ this from within the critical section - the kernel
+ takes care of that. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else if( xYieldRequired != pdFALSE )
+ {
+ /* This path is a special case that will only get
+ executed if the task was holding multiple mutexes and
+ the mutexes were given back in an order that is
+ different to that in which they were taken. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_QUEUE_SETS */
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* The queue was full and no block time is specified (or
+ the block time has expired) so leave now. */
+ taskEXIT_CRITICAL();
+
+ /* Return to the original privilege level before exiting
+ the function. */
+ traceQUEUE_SEND_FAILED( pxQueue );
+ return errQUEUE_FULL;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ /* The queue was full and a block time was specified so
+ configure the timeout structure. */
+ vTaskSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ else
+ {
+ /* Entry time was already set. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* Interrupts and other tasks can send to and receive from the queue
+ now the critical section has been exited. */
+
+ vTaskSuspendAll();
+ prvLockQueue( pxQueue );
+
+ /* Update the timeout state to see if it has expired yet. */
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+ /* Unlocking the queue means queue events can effect the
+ event list. It is possible that interrupts occurring now
+ remove this task from the event list again - but as the
+ scheduler is suspended the task will go onto the pending
+ ready last instead of the actual ready list. */
+ prvUnlockQueue( pxQueue );
+
+ /* Resuming the scheduler will move tasks from the pending
+ ready list into the ready list - so it is feasible that this
+ task is already in a ready list before it yields - in which
+ case the yield will not cause a context switch unless there
+ is also a higher priority task in the pending ready list. */
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ }
+ else
+ {
+ /* Try again. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+ }
+ }
+ else
+ {
+ /* The timeout has expired. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+
+ /* Return to the original privilege level before exiting the
+ function. */
+ traceQUEUE_SEND_FAILED( pxQueue );
+ return errQUEUE_FULL;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_ALTERNATIVE_API == 1 )
+
+ BaseType_t xQueueAltGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )
+ {
+ BaseType_t xEntryTimeSet = pdFALSE;
+ TimeOut_t xTimeOut;
+ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* Is there room on the queue now? To be running we must be
+ the highest priority task wanting to access the queue. */
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+ {
+ traceQUEUE_SEND( pxQueue );
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+ /* If there was a task waiting for data to arrive on the
+ queue then unblock it now. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) == pdTRUE )
+ {
+ /* The unblocked task has a priority higher than
+ our own so yield immediately. */
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ taskEXIT_CRITICAL();
+ return errQUEUE_FULL;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ vTaskSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ taskENTER_CRITICAL();
+ {
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ taskEXIT_CRITICAL();
+ traceQUEUE_SEND_FAILED( pxQueue );
+ return errQUEUE_FULL;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+ }
+
+#endif /* configUSE_ALTERNATIVE_API */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_ALTERNATIVE_API == 1 )
+
+ BaseType_t xQueueAltGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )
+ {
+ BaseType_t xEntryTimeSet = pdFALSE;
+ TimeOut_t xTimeOut;
+ int8_t *pcOriginalReadPosition;
+ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Remember our read position in case we are just peeking. */
+ pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+
+ if( xJustPeeking == pdFALSE )
+ {
+ traceQUEUE_RECEIVE( pxQueue );
+
+ /* Data is actually being removed (not just peeked). */
+ --( pxQueue->uxMessagesWaiting );
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ /* Record the information required to implement
+ priority inheritance should it become necessary. */
+ pxQueue->pxMutexHolder = ( int8_t * ) xTaskGetCurrentTaskHandle();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ else
+ {
+ traceQUEUE_PEEK( pxQueue );
+
+ /* We are not removing the data, so reset our read
+ pointer. */
+ pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+ /* The data is being left in the queue, so see if there are
+ any other tasks waiting for the data. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ /* Tasks that are removed from the event list will get added to
+ the pending ready list as the scheduler is still suspended. */
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority than this task. */
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ taskEXIT_CRITICAL();
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ vTaskSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ taskENTER_CRITICAL();
+ {
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ taskENTER_CRITICAL();
+ {
+ vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ taskEXIT_CRITICAL();
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+ }
+
+
+#endif /* configUSE_ALTERNATIVE_API */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ /* Similar to xQueueGenericSend, except without blocking if there is no room
+ in the queue. Also don't directly wake a task that was blocked on a queue
+ read, instead return a flag to say whether a context switch is required or
+ not (i.e. has a task with a higher priority than us been woken by this
+ post). */
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+ {
+ traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+ if( prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ) != pdFALSE )
+ {
+ /* This is a special case that can only be executed if a task
+ holds multiple mutexes and then gives the mutexes back in an
+ order that is different to that in which they were taken. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* The event list is not altered if the queue is locked. This will
+ be done when the queue is unlocked later. */
+ if( pxQueue->xTxLock == queueUNLOCKED )
+ {
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
+ {
+ if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) == pdTRUE )
+ {
+ /* The queue is a member of a queue set, and posting
+ to the queue set caused a higher priority task to
+ unblock. A context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so
+ record that a context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ context switch is required. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_QUEUE_SETS */
+ }
+ else
+ {
+ /* Increment the lock count so the task that unlocks the queue
+ knows that data was posted while it was locked. */
+ ++( pxQueue->xTxLock );
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+ xReturn = errQUEUE_FULL;
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+ {
+ configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+ }
+ #endif
+
+ /* This function relaxes the coding standard somewhat to allow return
+ statements within the function itself. This is done in the interest
+ of execution time efficiency. */
+
+ for( ;; )
+ {
+ taskENTER_CRITICAL();
+ {
+ /* Is there data in the queue now? To be running we must be
+ the highest priority task wanting to access the queue. */
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Remember the read position in case the queue is only being
+ peeked. */
+ pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+
+ if( xJustPeeking == pdFALSE )
+ {
+ traceQUEUE_RECEIVE( pxQueue );
+
+ /* Actually removing data, not just peeking. */
+ --( pxQueue->uxMessagesWaiting );
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ /* Record the information required to implement
+ priority inheritance should it become necessary. */
+ pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_MUTEXES */
+
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) == pdTRUE )
+ {
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ traceQUEUE_PEEK( pxQueue );
+
+ /* The data is not being removed, so reset the read
+ pointer. */
+ pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+ /* The data is being left in the queue, so see if there are
+ any other tasks waiting for the data. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ /* Tasks that are removed from the event list will get added to
+ the pending ready list as the scheduler is still suspended. */
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority than this task. */
+ queueYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ taskEXIT_CRITICAL();
+ return pdPASS;
+ }
+ else
+ {
+ if( xTicksToWait == ( TickType_t ) 0 )
+ {
+ /* The queue was empty and no block time is specified (or
+ the block time has expired) so leave now. */
+ taskEXIT_CRITICAL();
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ else if( xEntryTimeSet == pdFALSE )
+ {
+ /* The queue was empty and a block time was specified so
+ configure the timeout structure. */
+ vTaskSetTimeOutState( &xTimeOut );
+ xEntryTimeSet = pdTRUE;
+ }
+ else
+ {
+ /* Entry time was already set. */
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ /* Interrupts and other tasks can send to and receive from the queue
+ now the critical section has been exited. */
+
+ vTaskSuspendAll();
+ prvLockQueue( pxQueue );
+
+ /* Update the timeout state to see if it has expired yet. */
+ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+ {
+ if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+ {
+ traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ taskENTER_CRITICAL();
+ {
+ vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif
+
+ vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ prvUnlockQueue( pxQueue );
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Try again. */
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+ }
+ }
+ else
+ {
+ prvUnlockQueue( pxQueue );
+ ( void ) xTaskResumeAll();
+ traceQUEUE_RECEIVE_FAILED( pxQueue );
+ return errQUEUE_EMPTY;
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Cannot block in an ISR, so check there is data available. */
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+ --( pxQueue->uxMessagesWaiting );
+
+ /* If the queue is locked the event list will not be modified.
+ Instead update the lock count so the task that unlocks the queue
+ will know that an ISR has removed data while the queue was
+ locked. */
+ if( pxQueue->xRxLock == queueUNLOCKED )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority than us so
+ force a context switch. */
+ if( pxHigherPriorityTaskWoken != NULL )
+ {
+ *pxHigherPriorityTaskWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Increment the lock count so the task that unlocks the queue
+ knows that data was removed while it was locked. */
+ ++( pxQueue->xRxLock );
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+ configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ /* Cannot block in an ISR, so check there is data available. */
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+ /* Remember the read position so it can be reset as nothing is
+ actually being removed from the queue. */
+ pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+ prvCopyDataFromQueue( pxQueue, pvBuffer );
+ pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+ configASSERT( xQueue );
+
+ taskENTER_CRITICAL();
+ {
+ uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+ }
+ taskEXIT_CRITICAL();
+
+ return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t *pxQueue;
+
+ pxQueue = ( Queue_t * ) xQueue;
+ configASSERT( pxQueue );
+
+ taskENTER_CRITICAL();
+ {
+ uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+ }
+ taskEXIT_CRITICAL();
+
+ return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+ configASSERT( xQueue );
+
+ uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+
+ return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ configASSERT( pxQueue );
+
+ traceQUEUE_DELETE( pxQueue );
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+ {
+ vQueueUnregisterQueue( pxQueue );
+ }
+ #endif
+ if( pxQueue->pcHead != NULL )
+ {
+ vPortFree( pxQueue->pcHead );
+ }
+ vPortFree( pxQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+ {
+ return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+ {
+ ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+ {
+ return ( ( Queue_t * ) xQueue )->ucQueueType;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+
+ if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+ {
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+ {
+ /* The mutex is no longer being held. */
+ xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
+ pxQueue->pxMutexHolder = NULL;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_MUTEXES */
+ }
+ else if( xPosition == queueSEND_TO_BACK )
+ {
+ ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
+ pxQueue->pcWriteTo += pxQueue->uxItemSize;
+ if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ {
+ pxQueue->pcWriteTo = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ ( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
+ if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+ {
+ pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xPosition == queueOVERWRITE )
+ {
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* An item is not being added but overwritten, so subtract
+ one from the recorded number of items in the queue so when
+ one is added again below the number of recorded items remains
+ correct. */
+ --( pxQueue->uxMessagesWaiting );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ ++( pxQueue->uxMessagesWaiting );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+ if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+ {
+ pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+ if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+ {
+ pxQueue->u.pcReadFrom = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+ /* The lock counts contains the number of extra data items placed or
+ removed from the queue while the queue was locked. When a queue is
+ locked items can be added or removed, but the event lists cannot be
+ updated. */
+ taskENTER_CRITICAL();
+ {
+ /* See if data was added to the queue while it was locked. */
+ while( pxQueue->xTxLock > queueLOCKED_UNMODIFIED )
+ {
+ /* Data was posted while the queue was locked. Are any tasks
+ blocked waiting for data to become available? */
+ #if ( configUSE_QUEUE_SETS == 1 )
+ {
+ if( pxQueue->pxQueueSetContainer != NULL )
+ {
+ if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) == pdTRUE )
+ {
+ /* The queue is a member of a queue set, and posting to
+ the queue set caused a higher priority task to unblock.
+ A context switch is required. */
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* Tasks that are removed from the event list will get added to
+ the pending ready list as the scheduler is still suspended. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ context switch is required. */
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+ }
+ #else /* configUSE_QUEUE_SETS */
+ {
+ /* Tasks that are removed from the event list will get added to
+ the pending ready list as the scheduler is still suspended. */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority so record that a
+ context switch is required. */
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ break;
+ }
+ }
+ #endif /* configUSE_QUEUE_SETS */
+
+ --( pxQueue->xTxLock );
+ }
+
+ pxQueue->xTxLock = queueUNLOCKED;
+ }
+ taskEXIT_CRITICAL();
+
+ /* Do the same for the Rx lock. */
+ taskENTER_CRITICAL();
+ {
+ while( pxQueue->xRxLock > queueLOCKED_UNMODIFIED )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ vTaskMissedYield();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ --( pxQueue->xRxLock );
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ pxQueue->xRxLock = queueUNLOCKED;
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+ taskENTER_CRITICAL();
+ {
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+ configASSERT( xQueue );
+ if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+ taskENTER_CRITICAL();
+ {
+ if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+ configASSERT( xQueue );
+ if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ /* If the queue is already full we may have to block. A critical section
+ is required to prevent an interrupt removing something from the queue
+ between the check to see if the queue is full and blocking on the queue. */
+ portDISABLE_INTERRUPTS();
+ {
+ if( prvIsQueueFull( pxQueue ) != pdFALSE )
+ {
+ /* The queue is full - do we want to block or just leave without
+ posting? */
+ if( xTicksToWait > ( TickType_t ) 0 )
+ {
+ /* As this is called from a coroutine we cannot block directly, but
+ return indicating that we need to block. */
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+ portENABLE_INTERRUPTS();
+ return errQUEUE_BLOCKED;
+ }
+ else
+ {
+ portENABLE_INTERRUPTS();
+ return errQUEUE_FULL;
+ }
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ portDISABLE_INTERRUPTS();
+ {
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+ {
+ /* There is room in the queue, copy the data into the queue. */
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+ xReturn = pdPASS;
+
+ /* Were any co-routines waiting for data to become available? */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ /* In this instance the co-routine could be placed directly
+ into the ready list as we are within a critical section.
+ Instead the same pending ready list mechanism is used as if
+ the event were caused from within an interrupt. */
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The co-routine waiting has a higher priority so record
+ that a yield might be appropriate. */
+ xReturn = errQUEUE_YIELD;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xReturn = errQUEUE_FULL;
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ /* If the queue is already empty we may have to block. A critical section
+ is required to prevent an interrupt adding something to the queue
+ between the check to see if the queue is empty and blocking on the queue. */
+ portDISABLE_INTERRUPTS();
+ {
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+ {
+ /* There are no messages in the queue, do we want to block or just
+ leave with nothing? */
+ if( xTicksToWait > ( TickType_t ) 0 )
+ {
+ /* As this is a co-routine we cannot block directly, but return
+ indicating that we need to block. */
+ vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+ portENABLE_INTERRUPTS();
+ return errQUEUE_BLOCKED;
+ }
+ else
+ {
+ portENABLE_INTERRUPTS();
+ return errQUEUE_FULL;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ portDISABLE_INTERRUPTS();
+ {
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Data is available from the queue. */
+ pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+ if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+ {
+ pxQueue->u.pcReadFrom = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ --( pxQueue->uxMessagesWaiting );
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+ xReturn = pdPASS;
+
+ /* Were any co-routines waiting for space to become available? */
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ /* In this instance the co-routine could be placed directly
+ into the ready list as we are within a critical section.
+ Instead the same pending ready list mechanism is used as if
+ the event were caused from within an interrupt. */
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ xReturn = errQUEUE_YIELD;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+ }
+ portENABLE_INTERRUPTS();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+ {
+ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ /* Cannot block within an ISR so if there is no space on the queue then
+ exit without doing anything. */
+ if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+ {
+ prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+ /* We only want to wake one co-routine per ISR, so check that a
+ co-routine has not already been woken. */
+ if( xCoRoutinePreviouslyWoken == pdFALSE )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ return pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xCoRoutinePreviouslyWoken;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+ BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ /* We cannot block from an ISR, so check there is data available. If
+ not then just leave without doing anything. */
+ if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+ {
+ /* Copy the data from the queue. */
+ pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+ if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+ {
+ pxQueue->u.pcReadFrom = pxQueue->pcHead;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ --( pxQueue->uxMessagesWaiting );
+ ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+ if( ( *pxCoRoutineWoken ) == pdFALSE )
+ {
+ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+ {
+ if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+ {
+ *pxCoRoutineWoken = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ xReturn = pdPASS;
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ {
+ UBaseType_t ux;
+
+ /* See if there is an empty space in the registry. A NULL name denotes
+ a free slot. */
+ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ {
+ if( xQueueRegistry[ ux ].pcQueueName == NULL )
+ {
+ /* Store the information on this queue. */
+ xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+ xQueueRegistry[ ux ].xHandle = xQueue;
+
+ traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+ void vQueueUnregisterQueue( QueueHandle_t xQueue )
+ {
+ UBaseType_t ux;
+
+ /* See if the handle of the queue being unregistered in actually in the
+ registry. */
+ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+ {
+ if( xQueueRegistry[ ux ].xHandle == xQueue )
+ {
+ /* Set the name to NULL to show that this slot if free again. */
+ xQueueRegistry[ ux ].pcQueueName = NULL;
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+ void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait )
+ {
+ Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+ /* This function should not be called by application code hence the
+ 'Restricted' in its name. It is not part of the public API. It is
+ designed for use by kernel code, and has special calling requirements.
+ It can result in vListInsert() being called on a list that can only
+ possibly ever have one item in it, so the list will be fast, but even
+ so it should be called with the scheduler locked and not from a critical
+ section. */
+
+ /* Only do anything if there are no messages in the queue. This function
+ will not actually cause the task to block, just place it on a blocked
+ list. It will not block until the scheduler is unlocked - at which
+ time a yield will be performed. If an item is added to the queue while
+ the queue is locked, and the calling task blocks on the queue, then the
+ calling task will be immediately unblocked when the queue is unlocked. */
+ prvLockQueue( pxQueue );
+ if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+ {
+ /* There is nothing in the queue, block for the specified period. */
+ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ prvUnlockQueue( pxQueue );
+ }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+ {
+ QueueSetHandle_t pxQueue;
+
+ pxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+ return pxQueue;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+ {
+ BaseType_t xReturn;
+
+ taskENTER_CRITICAL();
+ {
+ if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+ {
+ /* Cannot add a queue/semaphore to more than one queue set. */
+ xReturn = pdFAIL;
+ }
+ else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+ {
+ /* Cannot add a queue/semaphore to a queue set if there are already
+ items in the queue/semaphore. */
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+ xReturn = pdPASS;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+ {
+ BaseType_t xReturn;
+ Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+ if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+ {
+ /* The queue was not a member of the set. */
+ xReturn = pdFAIL;
+ }
+ else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+ {
+ /* It is dangerous to remove a queue from a set when the queue is
+ not empty because the queue set will still hold pending events for
+ the queue. */
+ xReturn = pdFAIL;
+ }
+ else
+ {
+ taskENTER_CRITICAL();
+ {
+ /* The queue is no longer contained in the set. */
+ pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+ }
+ taskEXIT_CRITICAL();
+ xReturn = pdPASS;
+ }
+
+ return xReturn;
+ } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+ {
+ QueueSetMemberHandle_t xReturn = NULL;
+
+ ( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+ {
+ QueueSetMemberHandle_t xReturn = NULL;
+
+ ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+ static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
+ {
+ Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+ BaseType_t xReturn = pdFALSE;
+
+ /* This function must be called form a critical section. */
+
+ configASSERT( pxQueueSetContainer );
+ configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+ if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+ {
+ traceQUEUE_SEND( pxQueueSetContainer );
+ /* The data copied is the handle of the queue that contains data. */
+ xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
+
+ if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+ {
+ if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+ {
+ /* The task waiting has a higher priority */
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/cc3200/FreeRTOS/Source/tasks.c b/cc3200/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000000..11bbc251c1
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/tasks.c
@@ -0,0 +1,3613 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include
+#include
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "StackMacros.h"
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+ /* At the bottom of this file are two optional functions that can be used
+ to generate human readable text from the raw data generated by the
+ uxTaskGetSystemState() function. Note the formatting functions are provided
+ for convenience only, and are NOT considered part of the kernel. */
+ #include
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+/* Sanity check the configuration. */
+#if configUSE_TICKLESS_IDLE != 0
+ #if INCLUDE_vTaskSuspend != 1
+ #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
+ #endif /* INCLUDE_vTaskSuspend */
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Defines the size, in words, of the stack allocated to the idle task.
+ */
+#define tskIDLE_STACK_SIZE configMINIMAL_STACK_SIZE
+
+#if( configUSE_PREEMPTION == 0 )
+ /* If the cooperative scheduler is being used then a yield should not be
+ performed just because a higher priority task has been woken. */
+ #define taskYIELD_IF_USING_PREEMPTION()
+#else
+ #define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Task control block. A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock
+{
+ volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+ #if ( portUSING_MPU_WRAPPERS == 1 )
+ xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+ #endif
+
+ ListItem_t xGenericListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+ ListItem_t xEventListItem; /*< Used to reference a task from an event list. */
+ UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */
+ StackType_t *pxStack; /*< Points to the start of the stack. */
+ char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+ #if ( portSTACK_GROWTH > 0 )
+ StackType_t *pxEndOfStack; /*< Points to the end of the stack on architectures where the stack grows up from low memory. */
+ #endif
+
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+ UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+ #endif
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */
+ UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
+ #endif
+
+ #if ( configUSE_MUTEXES == 1 )
+ UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+ UBaseType_t uxMutexesHeld;
+ #endif
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ TaskHookFunction_t pxTaskTag;
+ #endif
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
+ #endif
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ /* Allocate a Newlib reent structure that is specific to this task.
+ Note Newlib support has been included by popular demand, but is not
+ used by the FreeRTOS maintainers themselves. FreeRTOS is not
+ responsible for resulting newlib operation. User must be familiar with
+ newlib and must provide system-wide implementations of the necessary
+ stubs. Be warned that (at the time of writing) the current newlib design
+ implements a system-wide malloc() that must be provided with locks. */
+ struct _reent xNewLib_reent;
+ #endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to to
+ * be global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+ #define static
+#endif
+
+/*lint -e956 A manual analysis and inspection has been used to determine which
+static variables must be declared volatile. */
+
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------*/
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+ PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */
+ PRIVILEGED_DATA static volatile UBaseType_t uxTasksDeleted = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */
+
+#endif
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+ PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */
+
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = portMAX_DELAY;
+
+/* Context switches are held pending while the scheduler is suspended. Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended. The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+ PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */
+ PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint +e956 */
+
+/* Debugging and trace facilities private variables and macros. ------------*/
+
+/*
+ * The value used to fill the stack of a task when the task is created. This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE ( 0xa5U )
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskBLOCKED_CHAR ( 'B' )
+#define tskREADY_CHAR ( 'R' )
+#define tskDELETED_CHAR ( 'D' )
+#define tskSUSPENDED_CHAR ( 'S' )
+
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+ /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+ performed in a generic way that is not optimised to any particular
+ microcontroller architecture. */
+
+ /* uxTopReadyPriority holds the priority of the highest priority ready
+ state task. */
+ #define taskRECORD_READY_PRIORITY( uxPriority ) \
+ { \
+ if( ( uxPriority ) > uxTopReadyPriority ) \
+ { \
+ uxTopReadyPriority = ( uxPriority ); \
+ } \
+ } /* taskRECORD_READY_PRIORITY */
+
+ /*-----------------------------------------------------------*/
+
+ #define taskSELECT_HIGHEST_PRIORITY_TASK() \
+ { \
+ /* Find the highest priority queue that contains ready tasks. */ \
+ while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopReadyPriority ] ) ) ) \
+ { \
+ configASSERT( uxTopReadyPriority ); \
+ --uxTopReadyPriority; \
+ } \
+ \
+ /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
+ the same priority get an equal share of the processor time. */ \
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopReadyPriority ] ) ); \
+ } /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+ /*-----------------------------------------------------------*/
+
+ /* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+ they are only required when a port optimised method of task selection is
+ being used. */
+ #define taskRESET_READY_PRIORITY( uxPriority )
+ #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+ /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+ performed in a way that is tailored to the particular microcontroller
+ architecture being used. */
+
+ /* A port optimised version is provided. Call the port defined macros. */
+ #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+ /*-----------------------------------------------------------*/
+
+ #define taskSELECT_HIGHEST_PRIORITY_TASK() \
+ { \
+ UBaseType_t uxTopPriority; \
+ \
+ /* Find the highest priority queue that contains ready tasks. */ \
+ portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \
+ configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
+ listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
+ } /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+ /*-----------------------------------------------------------*/
+
+ /* A port optimised version is provided, call it only if the TCB being reset
+ is being referenced from a ready list. If it is referenced from a delayed
+ or suspended list then it won't be in a ready list. */
+ #define taskRESET_READY_PRIORITY( uxPriority ) \
+ { \
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \
+ { \
+ portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \
+ } \
+ }
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS() \
+{ \
+ List_t *pxTemp; \
+ \
+ /* The delayed tasks list should be empty when the lists are switched. */ \
+ configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \
+ \
+ pxTemp = pxDelayedTaskList; \
+ pxDelayedTaskList = pxOverflowDelayedTaskList; \
+ pxOverflowDelayedTaskList = pxTemp; \
+ xNumOfOverflows++; \
+ prvResetNextTaskUnblockTime(); \
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task. It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB ) \
+ traceMOVED_TASK_TO_READY_STATE( pxTCB ) \
+ taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \
+ vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xGenericListItem ) )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter. This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order). However, it is occasionally borrowed for other purposes. It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose. The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if configUSE_16_BIT_TICKS == 1
+ #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U
+#else
+ #define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL
+#endif
+
+/* Callback function prototypes. --------------------------*/
+#if configCHECK_FOR_STACK_OVERFLOW > 0
+ extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+#endif
+
+#if configUSE_TICK_HOOK > 0
+ extern void vApplicationTickHook( void );
+#endif
+
+/* File private functions. --------------------------------*/
+
+/*
+ * Utility to ready a TCB for a given task. Mainly just copies the parameters
+ * into the TCB structure.
+ */
+static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Utility to ready all the lists used by the scheduler. This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions. The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+ static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task. This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted. If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state. Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake ) PRIVILEGED_FUNCTION;
+
+/*
+ * Allocates memory from the heap for a TCB and associated stack. Checks the
+ * allocation was successful.
+ */
+static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+ static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+ static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskGenericCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, StackType_t * const puxStackBuffer, const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+BaseType_t xReturn;
+TCB_t * pxNewTCB;
+
+ configASSERT( pxTaskCode );
+ configASSERT( ( ( uxPriority & ( ~portPRIVILEGE_BIT ) ) < configMAX_PRIORITIES ) );
+
+ /* Allocate the memory required by the TCB and stack for the new task,
+ checking that the allocation was successful. */
+ pxNewTCB = prvAllocateTCBAndStack( usStackDepth, puxStackBuffer );
+
+ if( pxNewTCB != NULL )
+ {
+ StackType_t *pxTopOfStack;
+
+ #if( portUSING_MPU_WRAPPERS == 1 )
+ /* Should the task be created in privileged mode? */
+ BaseType_t xRunPrivileged;
+ if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+ {
+ xRunPrivileged = pdTRUE;
+ }
+ else
+ {
+ xRunPrivileged = pdFALSE;
+ }
+ uxPriority &= ~portPRIVILEGE_BIT;
+ #endif /* portUSING_MPU_WRAPPERS == 1 */
+
+ /* Calculate the top of stack address. This depends on whether the
+ stack grows from high memory to low (as per the 80x86) or vice versa.
+ portSTACK_GROWTH is used to make the result positive or negative as
+ required by the port. */
+ #if( portSTACK_GROWTH < 0 )
+ {
+ pxTopOfStack = pxNewTCB->pxStack + ( usStackDepth - ( uint16_t ) 1 );
+ pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ( portPOINTER_SIZE_TYPE ) ~portBYTE_ALIGNMENT_MASK ) ); /*lint !e923 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. */
+
+ /* Check the alignment of the calculated top of stack is correct. */
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+ }
+ #else /* portSTACK_GROWTH */
+ {
+ pxTopOfStack = pxNewTCB->pxStack;
+
+ /* Check the alignment of the stack buffer is correct. */
+ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+ /* If we want to use stack checking on architectures that use
+ a positive stack growth direction then we also need to store the
+ other extreme of the stack space. */
+ pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( usStackDepth - 1 );
+ }
+ #endif /* portSTACK_GROWTH */
+
+ /* Setup the newly allocated TCB with the initial state of the task. */
+ prvInitialiseTCBVariables( pxNewTCB, pcName, uxPriority, xRegions, usStackDepth );
+
+ /* Initialize the TCB stack to look as if the task was already running,
+ but had been interrupted by the scheduler. The return address is set
+ to the start of the task function. Once the stack has been initialised
+ the top of stack variable is updated. */
+ #if( portUSING_MPU_WRAPPERS == 1 )
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+ }
+ #else /* portUSING_MPU_WRAPPERS */
+ {
+ pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+ }
+ #endif /* portUSING_MPU_WRAPPERS */
+
+ if( ( void * ) pxCreatedTask != NULL )
+ {
+ /* Pass the TCB out - in an anonymous way. The calling function/
+ task can use this as a handle to delete the task later if
+ required.*/
+ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Ensure interrupts don't access the task lists while they are being
+ updated. */
+ taskENTER_CRITICAL();
+ {
+ uxCurrentNumberOfTasks++;
+ if( pxCurrentTCB == NULL )
+ {
+ /* There are no other tasks, or all the other tasks are in
+ the suspended state - make this the current task. */
+ pxCurrentTCB = pxNewTCB;
+
+ if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+ {
+ /* This is the first task to be created so do the preliminary
+ initialisation required. We will not recover if this call
+ fails, but we will report the failure. */
+ prvInitialiseTaskLists();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* If the scheduler is not already running, make this task the
+ current task if it is the highest priority task to be created
+ so far. */
+ if( xSchedulerRunning == pdFALSE )
+ {
+ if( pxCurrentTCB->uxPriority <= uxPriority )
+ {
+ pxCurrentTCB = pxNewTCB;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ uxTaskNumber++;
+
+ #if ( configUSE_TRACE_FACILITY == 1 )
+ {
+ /* Add a counter into the TCB for tracing only. */
+ pxNewTCB->uxTCBNumber = uxTaskNumber;
+ }
+ #endif /* configUSE_TRACE_FACILITY */
+ traceTASK_CREATE( pxNewTCB );
+
+ prvAddTaskToReadyList( pxNewTCB );
+
+ xReturn = pdPASS;
+ portSETUP_TCB( pxNewTCB );
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+ traceTASK_CREATE_FAILED();
+ }
+
+ if( xReturn == pdPASS )
+ {
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* If the created task is of a higher priority than the current task
+ then it should run now. */
+ if( pxCurrentTCB->uxPriority < uxPriority )
+ {
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+ void vTaskDelete( TaskHandle_t xTaskToDelete )
+ {
+ TCB_t *pxTCB;
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the calling task that is
+ being deleted. */
+ pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+ /* Remove task from the ready list and place in the termination list.
+ This will stop the task from be scheduled. The idle task will check
+ the termination list and free up any memory allocated by the
+ scheduler for the TCB and stack. */
+ if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Is the task waiting on an event also? */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xGenericListItem ) );
+
+ /* Increment the ucTasksDeleted variable so the idle task knows
+ there is a task that has been deleted and that it should therefore
+ check the xTasksWaitingTermination list. */
+ ++uxTasksDeleted;
+
+ /* Increment the uxTaskNumberVariable also so kernel aware debuggers
+ can detect that the task lists need re-generating. */
+ uxTaskNumber++;
+
+ traceTASK_DELETE( pxTCB );
+ }
+ taskEXIT_CRITICAL();
+
+ /* Force a reschedule if it is the currently running task that has just
+ been deleted. */
+ if( xSchedulerRunning != pdFALSE )
+ {
+ if( pxTCB == pxCurrentTCB )
+ {
+ configASSERT( uxSchedulerSuspended == 0 );
+
+ /* The pre-delete hook is primarily for the Windows simulator,
+ in which Windows specific clean up operations are performed,
+ after which it is not possible to yield away from this task -
+ hence xYieldPending is used to latch that a context switch is
+ required. */
+ portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ /* Reset the next expected unblock time in case it referred to
+ the task that has just been deleted. */
+ taskENTER_CRITICAL();
+ {
+ prvResetNextTaskUnblockTime();
+ }
+ taskEXIT_CRITICAL();
+ }
+ }
+ }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+ void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+ {
+ TickType_t xTimeToWake;
+ BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+ configASSERT( pxPreviousWakeTime );
+ configASSERT( ( xTimeIncrement > 0U ) );
+ configASSERT( uxSchedulerSuspended == 0 );
+
+ vTaskSuspendAll();
+ {
+ /* Minor optimisation. The tick count cannot change in this
+ block. */
+ const TickType_t xConstTickCount = xTickCount;
+
+ /* Generate the tick time at which the task wants to wake. */
+ xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+ if( xConstTickCount < *pxPreviousWakeTime )
+ {
+ /* The tick count has overflowed since this function was
+ lasted called. In this case the only time we should ever
+ actually delay is if the wake time has also overflowed,
+ and the wake time is greater than the tick time. When this
+ is the case it is as if neither time had overflowed. */
+ if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+ {
+ xShouldDelay = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* The tick time has not overflowed. In this case we will
+ delay if either the wake time has overflowed, and/or the
+ tick time is less than the wake time. */
+ if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+ {
+ xShouldDelay = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* Update the wake time ready for the next call. */
+ *pxPreviousWakeTime = xTimeToWake;
+
+ if( xShouldDelay != pdFALSE )
+ {
+ traceTASK_DELAY_UNTIL();
+
+ /* Remove the task from the ready list before adding it to the
+ blocked list as the same list item is used for both lists. */
+ if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* The current task must be in a ready list, so there is
+ no need to check, and the port reset macro can be called
+ directly. */
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ prvAddCurrentTaskToDelayedList( xTimeToWake );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ xAlreadyYielded = xTaskResumeAll();
+
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may
+ have put ourselves to sleep. */
+ if( xAlreadyYielded == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+ void vTaskDelay( const TickType_t xTicksToDelay )
+ {
+ TickType_t xTimeToWake;
+ BaseType_t xAlreadyYielded = pdFALSE;
+
+
+ /* A delay time of zero just forces a reschedule. */
+ if( xTicksToDelay > ( TickType_t ) 0U )
+ {
+ configASSERT( uxSchedulerSuspended == 0 );
+ vTaskSuspendAll();
+ {
+ traceTASK_DELAY();
+
+ /* A task that is removed from the event list while the
+ scheduler is suspended will not get placed in the ready
+ list or removed from the blocked list until the scheduler
+ is resumed.
+
+ This task cannot be in an event list as it is the currently
+ executing task. */
+
+ /* Calculate the time to wake - this may overflow but this is
+ not a problem. */
+ xTimeToWake = xTickCount + xTicksToDelay;
+
+ /* We must remove ourselves from the ready list before adding
+ ourselves to the blocked list as the same list item is used for
+ both lists. */
+ if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* The current task must be in a ready list, so there is
+ no need to check, and the port reset macro can be called
+ directly. */
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ prvAddCurrentTaskToDelayedList( xTimeToWake );
+ }
+ xAlreadyYielded = xTaskResumeAll();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Force a reschedule if xTaskResumeAll has not already done so, we may
+ have put ourselves to sleep. */
+ if( xAlreadyYielded == pdFALSE )
+ {
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_eTaskGetState == 1 )
+
+ eTaskState eTaskGetState( TaskHandle_t xTask )
+ {
+ eTaskState eReturn;
+ List_t *pxStateList;
+ const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+ configASSERT( pxTCB );
+
+ if( pxTCB == pxCurrentTCB )
+ {
+ /* The task calling this function is querying its own state. */
+ eReturn = eRunning;
+ }
+ else
+ {
+ taskENTER_CRITICAL();
+ {
+ pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xGenericListItem ) );
+ }
+ taskEXIT_CRITICAL();
+
+ if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
+ {
+ /* The task being queried is referenced from one of the Blocked
+ lists. */
+ eReturn = eBlocked;
+ }
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ else if( pxStateList == &xSuspendedTaskList )
+ {
+ /* The task being queried is referenced from the suspended
+ list. Is it genuinely suspended or is it block
+ indefinitely? */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+ {
+ eReturn = eSuspended;
+ }
+ else
+ {
+ eReturn = eBlocked;
+ }
+ }
+ #endif
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ else if( pxStateList == &xTasksWaitingTermination )
+ {
+ /* The task being queried is referenced from the deleted
+ tasks list. */
+ eReturn = eDeleted;
+ }
+ #endif
+
+ else
+ {
+ /* If the task is not in any other state, it must be in the
+ Ready (including pending ready) state. */
+ eReturn = eReady;
+ }
+ }
+
+ return eReturn;
+ } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+ UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ UBaseType_t uxReturn;
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then we are changing the
+ priority of the calling function. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+ uxReturn = pxTCB->uxPriority;
+ }
+ taskEXIT_CRITICAL();
+
+ return uxReturn;
+ }
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+ void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+ {
+ TCB_t *pxTCB;
+ UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+ BaseType_t xYieldRequired = pdFALSE;
+
+ configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+ /* Ensure the new priority is valid. */
+ if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+ {
+ uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the priority of the calling
+ task that is being changed. */
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ uxCurrentBasePriority = pxTCB->uxBasePriority;
+ }
+ #else
+ {
+ uxCurrentBasePriority = pxTCB->uxPriority;
+ }
+ #endif
+
+ if( uxCurrentBasePriority != uxNewPriority )
+ {
+ /* The priority change may have readied a task of higher
+ priority than the calling task. */
+ if( uxNewPriority > uxCurrentBasePriority )
+ {
+ if( pxTCB != pxCurrentTCB )
+ {
+ /* The priority of a task other than the currently
+ running task is being raised. Is the priority being
+ raised above that of the running task? */
+ if( uxNewPriority >= pxCurrentTCB->uxPriority )
+ {
+ xYieldRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ /* The priority of the running task is being raised,
+ but the running task must already be the highest
+ priority task able to run so no yield is required. */
+ }
+ }
+ else if( pxTCB == pxCurrentTCB )
+ {
+ /* Setting the priority of the running task down means
+ there may now be another task of higher priority that
+ is ready to execute. */
+ xYieldRequired = pdTRUE;
+ }
+ else
+ {
+ /* Setting the priority of any other task down does not
+ require a yield as the running task must be above the
+ new priority of the task being modified. */
+ }
+
+ /* Remember the ready list the task might be referenced from
+ before its uxPriority member is changed so the
+ taskRESET_READY_PRIORITY() macro can function correctly. */
+ uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ /* Only change the priority being used if the task is not
+ currently using an inherited priority. */
+ if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+ {
+ pxTCB->uxPriority = uxNewPriority;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* The base priority gets set whatever. */
+ pxTCB->uxBasePriority = uxNewPriority;
+ }
+ #else
+ {
+ pxTCB->uxPriority = uxNewPriority;
+ }
+ #endif
+
+ /* Only reset the event list item value if the value is not
+ being used for anything else. */
+ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ {
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* If the task is in the blocked or suspended list we need do
+ nothing more than change it's priority variable. However, if
+ the task is in a ready list it needs to be removed and placed
+ in the list appropriate to its new priority. */
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )
+ {
+ /* The task is currently in its ready list - remove before adding
+ it to it's new ready list. As we are in a critical section we
+ can do this even if the scheduler is suspended. */
+ if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* It is known that the task is in its ready list so
+ there is no need to check again and the port level
+ reset macro can be called directly. */
+ portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xYieldRequired == pdTRUE )
+ {
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Remove compiler warning about unused variables when the port
+ optimised task selection is not being used. */
+ ( void ) uxPriorityUsedOnEntry;
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+ {
+ TCB_t *pxTCB;
+
+ taskENTER_CRITICAL();
+ {
+ /* If null is passed in here then it is the running task that is
+ being suspended. */
+ pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+ traceTASK_SUSPEND( pxTCB );
+
+ /* Remove task from the ready/delayed list and place in the
+ suspended list. */
+ if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Is the task waiting on an event also? */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) );
+ }
+ taskEXIT_CRITICAL();
+
+ if( pxTCB == pxCurrentTCB )
+ {
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* The current task has just been suspended. */
+ configASSERT( uxSchedulerSuspended == 0 );
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ /* The scheduler is not running, but the task that was pointed
+ to by pxCurrentTCB has just been suspended and pxCurrentTCB
+ must be adjusted to point to a different task. */
+ if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+ {
+ /* No other tasks are ready, so set pxCurrentTCB back to
+ NULL so when the next task is created pxCurrentTCB will
+ be set to point to it no matter what its relative priority
+ is. */
+ pxCurrentTCB = NULL;
+ }
+ else
+ {
+ vTaskSwitchContext();
+ }
+ }
+ }
+ else
+ {
+ if( xSchedulerRunning != pdFALSE )
+ {
+ /* A task other than the currently running task was suspended,
+ reset the next expected unblock time in case it referred to the
+ task that is now in the Suspended state. */
+ taskENTER_CRITICAL();
+ {
+ prvResetNextTaskUnblockTime();
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+ {
+ BaseType_t xReturn = pdFALSE;
+ const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+ /* Accesses xPendingReadyList so must be called from a critical
+ section. */
+
+ /* It does not make sense to check if the calling task is suspended. */
+ configASSERT( xTask );
+
+ /* Is the task being resumed actually in the suspended list? */
+ if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xGenericListItem ) ) != pdFALSE )
+ {
+ /* Has the task already been resumed from within an ISR? */
+ if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+ {
+ /* Is it in the suspended list because it is in the Suspended
+ state, or because is is blocked with no timeout? */
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
+ {
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+ } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+ void vTaskResume( TaskHandle_t xTaskToResume )
+ {
+ TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+
+ /* It does not make sense to resume the calling task. */
+ configASSERT( xTaskToResume );
+
+ /* The parameter cannot be NULL as it is impossible to resume the
+ currently executing task. */
+ if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
+ {
+ taskENTER_CRITICAL();
+ {
+ if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )
+ {
+ traceTASK_RESUME( pxTCB );
+
+ /* As we are in a critical section we can access the ready
+ lists even if the scheduler is suspended. */
+ ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+
+ /* We may have just resumed a higher priority task. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ /* This yield may not cause the task just resumed to run,
+ but will leave the lists in the correct state for the
+ next yield. */
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+ BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+ {
+ BaseType_t xYieldRequired = pdFALSE;
+ TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+ UBaseType_t uxSavedInterruptStatus;
+
+ configASSERT( xTaskToResume );
+
+ /* RTOS ports that support interrupt nesting have the concept of a
+ maximum system call (or maximum API call) interrupt priority.
+ Interrupts that are above the maximum system call priority are keep
+ permanently enabled, even when the RTOS kernel is in a critical section,
+ but cannot make any calls to FreeRTOS API functions. If configASSERT()
+ is defined in FreeRTOSConfig.h then
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has
+ been assigned a priority above the configured maximum system call
+ priority. Only FreeRTOS functions that end in FromISR can be called
+ from interrupts that have been assigned a priority at or (logically)
+ below the maximum system call interrupt priority. FreeRTOS maintains a
+ separate interrupt safe API to ensure interrupt entry is as fast and as
+ simple as possible. More information (albeit Cortex-M specific) is
+ provided on the following link:
+ http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ if( prvTaskIsTaskSuspended( pxTCB ) == pdTRUE )
+ {
+ traceTASK_RESUME_FROM_ISR( pxTCB );
+
+ /* Check the ready lists can be accessed. */
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ /* Ready lists can be accessed so move the task from the
+ suspended list to the ready list directly. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ xYieldRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ /* The delayed or ready lists cannot be accessed so the task
+ is held in the pending ready list until the scheduler is
+ unsuspended. */
+ vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xYieldRequired;
+ }
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+ /* Add the idle task at the lowest priority. */
+ #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+ {
+ /* Create the idle task, storing its handle in xIdleTaskHandle so it can
+ be returned by the xTaskGetIdleTaskHandle() function. */
+ xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+ }
+ #else
+ {
+ /* Create the idle task without storing its handle. */
+ xReturn = xTaskCreate( prvIdleTask, "IDLE", tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), NULL ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+ }
+ #endif /* INCLUDE_xTaskGetIdleTaskHandle */
+
+ #if ( configUSE_TIMERS == 1 )
+ {
+ if( xReturn == pdPASS )
+ {
+ xReturn = xTimerCreateTimerTask();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_TIMERS */
+
+ if( xReturn == pdPASS )
+ {
+ /* Interrupts are turned off here, to ensure a tick does not occur
+ before or during the call to xPortStartScheduler(). The stacks of
+ the created tasks contain a status word with interrupts switched on
+ so interrupts will automatically get re-enabled when the first task
+ starts to run. */
+ portDISABLE_INTERRUPTS();
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ /* Switch Newlib's _impure_ptr variable to point to the _reent
+ structure specific to the task that will run first. */
+ _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+ }
+ #endif /* configUSE_NEWLIB_REENTRANT */
+
+ xSchedulerRunning = pdTRUE;
+ xTickCount = ( TickType_t ) 0U;
+
+ /* If configGENERATE_RUN_TIME_STATS is defined then the following
+ macro must be defined to configure the timer/counter used to generate
+ the run time counter time base. */
+ portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+ /* Setting up the timer tick is hardware specific and thus in the
+ portable interface. */
+ if( xPortStartScheduler() != pdFALSE )
+ {
+ /* Should not reach here as if the scheduler is running the
+ function will not return. */
+ }
+ else
+ {
+ /* Should only reach here if a task calls xTaskEndScheduler(). */
+ }
+ }
+ else
+ {
+ /* This line will only be reached if the kernel could not be started,
+ because there was not enough FreeRTOS heap to create the idle task
+ or the timer task. */
+ configASSERT( xReturn );
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+ /* Stop the scheduler interrupts and call the portable scheduler end
+ routine so the original ISRs can be restored if necessary. The port
+ layer must ensure interrupts enable bit is left in the correct state. */
+ portDISABLE_INTERRUPTS();
+ xSchedulerRunning = pdFALSE;
+ vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+ /* A critical section is not required as the variable is of type
+ BaseType_t. Please read Richard Barry's reply in the following link to a
+ post in the FreeRTOS support forum before reporting this as a bug! -
+ http://goo.gl/wu4acr */
+ ++uxSchedulerSuspended;
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+ static TickType_t prvGetExpectedIdleTime( void )
+ {
+ TickType_t xReturn;
+
+ if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+ {
+ xReturn = 0;
+ }
+ else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+ {
+ /* There are other idle priority tasks in the ready state. If
+ time slicing is used then the very next tick interrupt must be
+ processed. */
+ xReturn = 0;
+ }
+ else
+ {
+ xReturn = xNextTaskUnblockTime - xTickCount;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+ /* If uxSchedulerSuspended is zero then this function does not match a
+ previous call to vTaskSuspendAll(). */
+ configASSERT( uxSchedulerSuspended );
+
+ /* It is possible that an ISR caused a task to be removed from an event
+ list while the scheduler was suspended. If this was the case then the
+ removed task will have been added to the xPendingReadyList. Once the
+ scheduler has been resumed it is safe to move all the pending ready
+ tasks from this list into their appropriate ready list. */
+ taskENTER_CRITICAL();
+ {
+ --uxSchedulerSuspended;
+
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+ {
+ /* Move any readied tasks from the pending list into the
+ appropriate ready list. */
+ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+ {
+ pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
+ prvAddTaskToReadyList( pxTCB );
+
+ /* If we have moved a task that has a priority higher than
+ the current task then we should yield. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* If any ticks occurred while the scheduler was suspended then
+ they should be processed now. This ensures the tick count does
+ not slip, and that any delayed tasks are resumed at the correct
+ time. */
+ if( uxPendedTicks > ( UBaseType_t ) 0U )
+ {
+ while( uxPendedTicks > ( UBaseType_t ) 0U )
+ {
+ if( xTaskIncrementTick() != pdFALSE )
+ {
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ --uxPendedTicks;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ if( xYieldPending == pdTRUE )
+ {
+ #if( configUSE_PREEMPTION != 0 )
+ {
+ xAlreadyYielded = pdTRUE;
+ }
+ #endif
+ taskYIELD_IF_USING_PREEMPTION();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+ /* Critical section required if running on a 16 bit processor. */
+ taskENTER_CRITICAL();
+ {
+ xTicks = xTickCount;
+ }
+ taskEXIT_CRITICAL();
+
+ return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+ /* RTOS ports that support interrupt nesting have the concept of a maximum
+ system call (or maximum API call) interrupt priority. Interrupts that are
+ above the maximum system call priority are kept permanently enabled, even
+ when the RTOS kernel is in a critical section, but cannot make any calls to
+ FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h
+ then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+ failure if a FreeRTOS API function is called from an interrupt that has been
+ assigned a priority above the configured maximum system call priority.
+ Only FreeRTOS functions that end in FromISR can be called from interrupts
+ that have been assigned a priority at or (logically) below the maximum
+ system call interrupt priority. FreeRTOS maintains a separate interrupt
+ safe API to ensure interrupt entry is as fast and as simple as possible.
+ More information (albeit Cortex-M specific) is provided on the following
+ link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+ portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+ {
+ xReturn = xTickCount;
+ }
+ portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+ /* A critical section is not required because the variables are of type
+ BaseType_t. */
+ return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_pcTaskGetTaskName == 1 )
+
+ char *pcTaskGetTaskName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ {
+ TCB_t *pxTCB;
+
+ /* If null is passed in here then the name of the calling task is being queried. */
+ pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+ configASSERT( pxTCB );
+ return &( pxTCB->pcTaskName[ 0 ] );
+ }
+
+#endif /* INCLUDE_pcTaskGetTaskName */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+ {
+ UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+ vTaskSuspendAll();
+ {
+ /* Is there a space in the array for each task in the system? */
+ if( uxArraySize >= uxCurrentNumberOfTasks )
+ {
+ /* Fill in an TaskStatus_t structure with information on each
+ task in the Ready state. */
+ do
+ {
+ uxQueue--;
+ uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+ } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ /* Fill in an TaskStatus_t structure with information on each
+ task in the Blocked state. */
+ uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+ uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+ #if( INCLUDE_vTaskDelete == 1 )
+ {
+ /* Fill in an TaskStatus_t structure with information on
+ each task that has been deleted but not yet cleaned up. */
+ uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+ }
+ #endif
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ /* Fill in an TaskStatus_t structure with information on
+ each task in the Suspended state. */
+ uxTask += prvListTaskWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+ }
+ #endif
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1)
+ {
+ if( pulTotalRunTime != NULL )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+ #else
+ *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+ }
+ }
+ #else
+ {
+ if( pulTotalRunTime != NULL )
+ {
+ *pulTotalRunTime = 0;
+ }
+ }
+ #endif
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ ( void ) xTaskResumeAll();
+
+ return uxTask;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+ TaskHandle_t xTaskGetIdleTaskHandle( void )
+ {
+ /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+ started, then xIdleTaskHandle will be NULL. */
+ configASSERT( ( xIdleTaskHandle != NULL ) );
+ return xIdleTaskHandle;
+ }
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+ void vTaskStepTick( const TickType_t xTicksToJump )
+ {
+ /* Correct the tick count value after a period during which the tick
+ was suppressed. Note this does *not* call the tick hook function for
+ each stepped tick. */
+ configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+ xTickCount += xTicksToJump;
+ traceINCREASE_TICK_COUNT( xTicksToJump );
+ }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+ /* Called by the portable layer each time a tick interrupt occurs.
+ Increments the tick then checks to see if the new tick value will cause any
+ tasks to be unblocked. */
+ traceTASK_INCREMENT_TICK( xTickCount );
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ /* Increment the RTOS tick, switching the delayed and overflowed
+ delayed lists if it wraps to 0. */
+ ++xTickCount;
+
+ {
+ /* Minor optimisation. The tick count cannot change in this
+ block. */
+ const TickType_t xConstTickCount = xTickCount;
+
+ if( xConstTickCount == ( TickType_t ) 0U )
+ {
+ taskSWITCH_DELAYED_LISTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* See if this tick has made a timeout expire. Tasks are stored in
+ the queue in the order of their wake time - meaning once one task
+ has been found whose block time has not expired there is no need to
+ look any further down the list. */
+ if( xConstTickCount >= xNextTaskUnblockTime )
+ {
+ for( ;; )
+ {
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ {
+ /* The delayed list is empty. Set xNextTaskUnblockTime
+ to the maximum possible value so it is extremely
+ unlikely that the
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass
+ next time through. */
+ xNextTaskUnblockTime = portMAX_DELAY;
+ break;
+ }
+ else
+ {
+ /* The delayed list is not empty, get the value of the
+ item at the head of the delayed list. This is the time
+ at which the task at the head of the delayed list must
+ be removed from the Blocked state. */
+ pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+ xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xGenericListItem ) );
+
+ if( xConstTickCount < xItemValue )
+ {
+ /* It is not time to unblock this item yet, but the
+ item value is the time at which the task at the head
+ of the blocked list must be removed from the Blocked
+ state - so record the item value in
+ xNextTaskUnblockTime. */
+ xNextTaskUnblockTime = xItemValue;
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* It is time to remove the item from the Blocked state. */
+ ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
+
+ /* Is the task waiting on an event also? If so remove
+ it from the event list. */
+ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+ {
+ ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Place the unblocked task into the appropriate ready
+ list. */
+ prvAddTaskToReadyList( pxTCB );
+
+ /* A task being unblocked cannot cause an immediate
+ context switch if preemption is turned off. */
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ /* Preemption is on, but a context switch should
+ only be performed if the unblocked task has a
+ priority that is equal to or higher than the
+ currently executing task. */
+ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_PREEMPTION */
+ }
+ }
+ }
+ }
+
+ /* Tasks of equal priority to the currently running task will share
+ processing time (time slice) if preemption is on, and the application
+ writer has not explicitly turned time slicing off. */
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+ {
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+ #if ( configUSE_TICK_HOOK == 1 )
+ {
+ /* Guard against the tick hook being called when the pended tick
+ count is being unwound (when the scheduler is being unlocked). */
+ if( uxPendedTicks == ( UBaseType_t ) 0U )
+ {
+ vApplicationTickHook();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_TICK_HOOK */
+ }
+ else
+ {
+ ++uxPendedTicks;
+
+ /* The tick hook gets called at regular intervals, even if the
+ scheduler is locked. */
+ #if ( configUSE_TICK_HOOK == 1 )
+ {
+ vApplicationTickHook();
+ }
+ #endif
+ }
+
+ #if ( configUSE_PREEMPTION == 1 )
+ {
+ if( xYieldPending != pdFALSE )
+ {
+ xSwitchRequired = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_PREEMPTION */
+
+ return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+ {
+ TCB_t *xTCB;
+
+ /* If xTask is NULL then it is the task hook of the calling task that is
+ getting set. */
+ if( xTask == NULL )
+ {
+ xTCB = ( TCB_t * ) pxCurrentTCB;
+ }
+ else
+ {
+ xTCB = ( TCB_t * ) xTask;
+ }
+
+ /* Save the hook function in the TCB. A critical section is required as
+ the value can be accessed from an interrupt. */
+ taskENTER_CRITICAL();
+ xTCB->pxTaskTag = pxHookFunction;
+ taskEXIT_CRITICAL();
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+ {
+ TCB_t *xTCB;
+ TaskHookFunction_t xReturn;
+
+ /* If xTask is NULL then we are setting our own task hook. */
+ if( xTask == NULL )
+ {
+ xTCB = ( TCB_t * ) pxCurrentTCB;
+ }
+ else
+ {
+ xTCB = ( TCB_t * ) xTask;
+ }
+
+ /* Save the hook function in the TCB. A critical section is required as
+ the value can be accessed from an interrupt. */
+ taskENTER_CRITICAL();
+ {
+ xReturn = xTCB->pxTaskTag;
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+ BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+ {
+ TCB_t *xTCB;
+ BaseType_t xReturn;
+
+ /* If xTask is NULL then we are calling our own task hook. */
+ if( xTask == NULL )
+ {
+ xTCB = ( TCB_t * ) pxCurrentTCB;
+ }
+ else
+ {
+ xTCB = ( TCB_t * ) xTask;
+ }
+
+ if( xTCB->pxTaskTag != NULL )
+ {
+ xReturn = xTCB->pxTaskTag( pvParameter );
+ }
+ else
+ {
+ xReturn = pdFAIL;
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+ if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+ {
+ /* The scheduler is currently suspended - do not allow a context
+ switch. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ xYieldPending = pdFALSE;
+ traceTASK_SWITCHED_OUT();
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+ portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+ #else
+ ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+ #endif
+
+ /* Add the amount of time the task has been running to the
+ accumulated time so far. The time the task started running was
+ stored in ulTaskSwitchedInTime. Note that there is no overflow
+ protection here so count values are only valid until the timer
+ overflows. The guard against negative values is to protect
+ against suspect run time stat counter implementations - which
+ are provided by the application, not the kernel. */
+ if( ulTotalRunTime > ulTaskSwitchedInTime )
+ {
+ pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ ulTaskSwitchedInTime = ulTotalRunTime;
+ }
+ #endif /* configGENERATE_RUN_TIME_STATS */
+
+ /* Check for stack overflow, if configured. */
+ taskFIRST_CHECK_FOR_STACK_OVERFLOW();
+ taskSECOND_CHECK_FOR_STACK_OVERFLOW();
+
+ /* Select a new task to run using either the generic C or port
+ optimised asm code. */
+ taskSELECT_HIGHEST_PRIORITY_TASK();
+ traceTASK_SWITCHED_IN();
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ /* Switch Newlib's _impure_ptr variable to point to the _reent
+ structure specific to this task. */
+ _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+ }
+ #endif /* configUSE_NEWLIB_REENTRANT */
+ }
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+TickType_t xTimeToWake;
+
+ configASSERT( pxEventList );
+
+ /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+ SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+ /* Place the event list item of the TCB in the appropriate event list.
+ This is placed in the list in priority order so the highest priority task
+ is the first to be woken by the event. The queue that contains the event
+ list is locked, preventing simultaneous access from interrupts. */
+ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+ /* The task must be removed from from the ready list before it is added to
+ the blocked list as the same list item is used for both lists. Exclusive
+ access to the ready lists guaranteed because the scheduler is locked. */
+ if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* The current task must be in a ready list, so there is no need to
+ check, and the port reset macro can be called directly. */
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ if( xTicksToWait == portMAX_DELAY )
+ {
+ /* Add the task to the suspended task list instead of a delayed task
+ list to ensure the task is not woken by a timing event. It will
+ block indefinitely. */
+ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );
+ }
+ else
+ {
+ /* Calculate the time at which the task should be woken if the event
+ does not occur. This may overflow but this doesn't matter, the
+ scheduler will handle it. */
+ xTimeToWake = xTickCount + xTicksToWait;
+ prvAddCurrentTaskToDelayedList( xTimeToWake );
+ }
+ }
+ #else /* INCLUDE_vTaskSuspend */
+ {
+ /* Calculate the time at which the task should be woken if the event does
+ not occur. This may overflow but this doesn't matter, the scheduler
+ will handle it. */
+ xTimeToWake = xTickCount + xTicksToWait;
+ prvAddCurrentTaskToDelayedList( xTimeToWake );
+ }
+ #endif /* INCLUDE_vTaskSuspend */
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+TickType_t xTimeToWake;
+
+ configASSERT( pxEventList );
+
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
+ the event groups implementation. */
+ configASSERT( uxSchedulerSuspended != 0 );
+
+ /* Store the item value in the event list item. It is safe to access the
+ event list item here as interrupts won't access the event list item of a
+ task that is not in the Blocked state. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+ /* Place the event list item of the TCB at the end of the appropriate event
+ list. It is safe to access the event list here because it is part of an
+ event group implementation - and interrupts don't access event groups
+ directly (instead they access them indirectly by pending function calls to
+ the task level). */
+ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+ /* The task must be removed from the ready list before it is added to the
+ blocked list. Exclusive access can be assured to the ready list as the
+ scheduler is locked. */
+ if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* The current task must be in a ready list, so there is no need to
+ check, and the port reset macro can be called directly. */
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ if( xTicksToWait == portMAX_DELAY )
+ {
+ /* Add the task to the suspended task list instead of a delayed task
+ list to ensure it is not woken by a timing event. It will block
+ indefinitely. */
+ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xGenericListItem ) );
+ }
+ else
+ {
+ /* Calculate the time at which the task should be woken if the event
+ does not occur. This may overflow but this doesn't matter, the
+ kernel will manage it correctly. */
+ xTimeToWake = xTickCount + xTicksToWait;
+ prvAddCurrentTaskToDelayedList( xTimeToWake );
+ }
+ }
+ #else /* INCLUDE_vTaskSuspend */
+ {
+ /* Calculate the time at which the task should be woken if the event does
+ not occur. This may overflow but this doesn't matter, the kernel
+ will manage it correctly. */
+ xTimeToWake = xTickCount + xTicksToWait;
+ prvAddCurrentTaskToDelayedList( xTimeToWake );
+ }
+ #endif /* INCLUDE_vTaskSuspend */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TIMERS == 1
+
+ void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, const TickType_t xTicksToWait )
+ {
+ TickType_t xTimeToWake;
+
+ configASSERT( pxEventList );
+
+ /* This function should not be called by application code hence the
+ 'Restricted' in its name. It is not part of the public API. It is
+ designed for use by kernel code, and has special calling requirements -
+ it should be called from a critical section. */
+
+
+ /* Place the event list item of the TCB in the appropriate event list.
+ In this case it is assume that this is the only task that is going to
+ be waiting on this event list, so the faster vListInsertEnd() function
+ can be used in place of vListInsert. */
+ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+ /* We must remove this task from the ready list before adding it to the
+ blocked list as the same list item is used for both lists. This
+ function is called form a critical section. */
+ if( uxListRemove( &( pxCurrentTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ /* The current task must be in a ready list, so there is no need to
+ check, and the port reset macro can be called directly. */
+ portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Calculate the time at which the task should be woken if the event does
+ not occur. This may overflow but this doesn't matter. */
+ xTimeToWake = xTickCount + xTicksToWait;
+
+ traceTASK_DELAY_UNTIL();
+ prvAddCurrentTaskToDelayedList( xTimeToWake );
+ }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+ /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be
+ called from a critical section within an ISR. */
+
+ /* The event list is sorted in priority order, so the first in the list can
+ be removed as it is known to be the highest priority. Remove the TCB from
+ the delayed list, and add it to the ready list.
+
+ If an event is for a queue that is locked then this function will never
+ get called - the lock count on the queue will get modified instead. This
+ means exclusive access to the event list is guaranteed here.
+
+ This function assumes that a check has already been made to ensure that
+ pxEventList is not empty. */
+ pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+ configASSERT( pxUnblockedTCB );
+ ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );
+ prvAddTaskToReadyList( pxUnblockedTCB );
+ }
+ else
+ {
+ /* The delayed and ready lists cannot be accessed, so hold this task
+ pending until the scheduler is resumed. */
+ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+ }
+
+ if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* Return true if the task removed from the event list has a higher
+ priority than the calling task. This allows the calling task to know if
+ it should force a context switch now. */
+ xReturn = pdTRUE;
+
+ /* Mark that a yield is pending in case the user is not using the
+ "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+ /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by
+ the event flags implementation. */
+ configASSERT( uxSchedulerSuspended != pdFALSE );
+
+ /* Store the new item value in the event list. */
+ listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+ /* Remove the event list form the event flag. Interrupts do not access
+ event flags. */
+ pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
+ configASSERT( pxUnblockedTCB );
+ ( void ) uxListRemove( pxEventListItem );
+
+ /* Remove the task from the delayed list and add it to the ready list. The
+ scheduler is suspended so interrupts will not be accessing the ready
+ lists. */
+ ( void ) uxListRemove( &( pxUnblockedTCB->xGenericListItem ) );
+ prvAddTaskToReadyList( pxUnblockedTCB );
+
+ if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+ {
+ /* Return true if the task removed from the event list has
+ a higher priority than the calling task. This allows
+ the calling task to know if it should force a context
+ switch now. */
+ xReturn = pdTRUE;
+
+ /* Mark that a yield is pending in case the user is not using the
+ "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+ xYieldPending = pdTRUE;
+ }
+ else
+ {
+ xReturn = pdFALSE;
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+ configASSERT( pxTimeOut );
+ pxTimeOut->xOverflowCount = xNumOfOverflows;
+ pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+ configASSERT( pxTimeOut );
+ configASSERT( pxTicksToWait );
+
+ taskENTER_CRITICAL();
+ {
+ /* Minor optimisation. The tick count cannot change in this block. */
+ const TickType_t xConstTickCount = xTickCount;
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is
+ the maximum block time then the task should block indefinitely, and
+ therefore never time out. */
+ if( *pxTicksToWait == portMAX_DELAY )
+ {
+ xReturn = pdFALSE;
+ }
+ else /* We are not blocking indefinitely, perform the checks below. */
+ #endif
+
+ if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+ {
+ /* The tick count is greater than the time at which vTaskSetTimeout()
+ was called, but has also overflowed since vTaskSetTimeOut() was called.
+ It must have wrapped all the way around and gone past us again. This
+ passed since vTaskSetTimeout() was called. */
+ xReturn = pdTRUE;
+ }
+ else if( ( xConstTickCount - pxTimeOut->xTimeOnEntering ) < *pxTicksToWait )
+ {
+ /* Not a genuine timeout. Adjust parameters for time remaining. */
+ *pxTicksToWait -= ( xConstTickCount - pxTimeOut->xTimeOnEntering );
+ vTaskSetTimeOutState( pxTimeOut );
+ xReturn = pdFALSE;
+ }
+ else
+ {
+ xReturn = pdTRUE;
+ }
+ }
+ taskEXIT_CRITICAL();
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+ xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+ {
+ UBaseType_t uxReturn;
+ TCB_t *pxTCB;
+
+ if( xTask != NULL )
+ {
+ pxTCB = ( TCB_t * ) xTask;
+ uxReturn = pxTCB->uxTaskNumber;
+ }
+ else
+ {
+ uxReturn = 0U;
+ }
+
+ return uxReturn;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+ {
+ TCB_t *pxTCB;
+
+ if( xTask != NULL )
+ {
+ pxTCB = ( TCB_t * ) xTask;
+ pxTCB->uxTaskNumber = uxHandle;
+ }
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions. The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+ /* Stop warnings. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* See if any tasks have been deleted. */
+ prvCheckTasksWaitingTermination();
+
+ #if ( configUSE_PREEMPTION == 0 )
+ {
+ /* If we are not using preemption we keep forcing a task switch to
+ see if any other task has become available. If we are using
+ preemption we don't need to do this as any task becoming available
+ will automatically get the processor anyway. */
+ taskYIELD();
+ }
+ #endif /* configUSE_PREEMPTION */
+
+ #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+ {
+ /* When using preemption tasks of equal priority will be
+ timesliced. If a task that is sharing the idle priority is ready
+ to run then the idle task should yield before the end of the
+ timeslice.
+
+ A critical region is not required here as we are just reading from
+ the list, and an occasional incorrect value will not matter. If
+ the ready list at the idle priority contains more than one task
+ then a task other than the idle task is ready to execute. */
+ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+ {
+ taskYIELD();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+ #if ( configUSE_IDLE_HOOK == 1 )
+ {
+ extern void vApplicationIdleHook( void );
+
+ /* Call the user defined function from within the idle task. This
+ allows the application designer to add background functionality
+ without the overhead of a separate task.
+ NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+ CALL A FUNCTION THAT MIGHT BLOCK. */
+ vApplicationIdleHook();
+ }
+ #endif /* configUSE_IDLE_HOOK */
+
+ /* This conditional compilation should use inequality to 0, not equality
+ to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+ user defined low power mode implementations require
+ configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+ #if ( configUSE_TICKLESS_IDLE != 0 )
+ {
+ TickType_t xExpectedIdleTime;
+
+ /* It is not desirable to suspend then resume the scheduler on
+ each iteration of the idle task. Therefore, a preliminary
+ test of the expected idle time is performed without the
+ scheduler suspended. The result here is not necessarily
+ valid. */
+ xExpectedIdleTime = prvGetExpectedIdleTime();
+
+ if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ {
+ vTaskSuspendAll();
+ {
+ /* Now the scheduler is suspended, the expected idle
+ time can be sampled again, and this time its value can
+ be used. */
+ configASSERT( xNextTaskUnblockTime >= xTickCount );
+ xExpectedIdleTime = prvGetExpectedIdleTime();
+
+ if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+ {
+ traceLOW_POWER_IDLE_BEGIN();
+ portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+ traceLOW_POWER_IDLE_END();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ ( void ) xTaskResumeAll();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_TICKLESS_IDLE */
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE != 0
+
+ eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+ {
+ eSleepModeStatus eReturn = eStandardSleep;
+
+ if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+ {
+ /* A task was made ready while the scheduler was suspended. */
+ eReturn = eAbortSleep;
+ }
+ else if( xYieldPending != pdFALSE )
+ {
+ /* A yield was pended while the scheduler was suspended. */
+ eReturn = eAbortSleep;
+ }
+ else
+ {
+ #if configUSE_TIMERS == 0
+ {
+ /* The idle task exists in addition to the application tasks. */
+ const UBaseType_t uxNonApplicationTasks = 1;
+
+ /* If timers are not being used and all the tasks are in the
+ suspended list (which might mean they have an infinite block
+ time rather than actually being suspended) then it is safe to
+ turn all clocks off and just wait for external interrupts. */
+ if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+ {
+ eReturn = eNoTasksWaitingTimeout;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configUSE_TIMERS */
+ }
+
+ return eReturn;
+ }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTCBVariables( TCB_t * const pxTCB, const char * const pcName, UBaseType_t uxPriority, const MemoryRegion_t * const xRegions, const uint16_t usStackDepth ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+UBaseType_t x;
+
+ /* Store the task name in the TCB. */
+ for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+ {
+ pxTCB->pcTaskName[ x ] = pcName[ x ];
+
+ /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+ configMAX_TASK_NAME_LEN characters just in case the memory after the
+ string is not accessible (extremely unlikely). */
+ if( pcName[ x ] == 0x00 )
+ {
+ break;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ /* Ensure the name string is terminated in the case that the string length
+ was greater or equal to configMAX_TASK_NAME_LEN. */
+ pxTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+
+ /* This is used as an array index so must ensure it's not too large. First
+ remove the privilege bit if one is present. */
+ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+ {
+ uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ pxTCB->uxPriority = uxPriority;
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ pxTCB->uxBasePriority = uxPriority;
+ pxTCB->uxMutexesHeld = 0;
+ }
+ #endif /* configUSE_MUTEXES */
+
+ vListInitialiseItem( &( pxTCB->xGenericListItem ) );
+ vListInitialiseItem( &( pxTCB->xEventListItem ) );
+
+ /* Set the pxTCB as a link back from the ListItem_t. This is so we can get
+ back to the containing TCB from a generic item in a list. */
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xGenericListItem ), pxTCB );
+
+ /* Event lists are always in priority order. */
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ listSET_LIST_ITEM_OWNER( &( pxTCB->xEventListItem ), pxTCB );
+
+ #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+ {
+ pxTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+ }
+ #endif /* portCRITICAL_NESTING_IN_TCB */
+
+ #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+ {
+ pxTCB->pxTaskTag = NULL;
+ }
+ #endif /* configUSE_APPLICATION_TASK_TAG */
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ pxTCB->ulRunTimeCounter = 0UL;
+ }
+ #endif /* configGENERATE_RUN_TIME_STATS */
+
+ #if ( portUSING_MPU_WRAPPERS == 1 )
+ {
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, pxTCB->pxStack, usStackDepth );
+ }
+ #else /* portUSING_MPU_WRAPPERS */
+ {
+ ( void ) xRegions;
+ ( void ) usStackDepth;
+ }
+ #endif /* portUSING_MPU_WRAPPERS */
+
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ /* Initialise this task's Newlib reent structure. */
+ _REENT_INIT_PTR( ( &( pxTCB->xNewLib_reent ) ) );
+ }
+ #endif /* configUSE_NEWLIB_REENTRANT */
+}
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+ void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+ {
+ TCB_t *pxTCB;
+
+ /* If null is passed in here then we are deleting ourselves. */
+ pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+ vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+ }
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+ for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+ {
+ vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+ }
+
+ vListInitialise( &xDelayedTaskList1 );
+ vListInitialise( &xDelayedTaskList2 );
+ vListInitialise( &xPendingReadyList );
+
+ #if ( INCLUDE_vTaskDelete == 1 )
+ {
+ vListInitialise( &xTasksWaitingTermination );
+ }
+ #endif /* INCLUDE_vTaskDelete */
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ vListInitialise( &xSuspendedTaskList );
+ }
+ #endif /* INCLUDE_vTaskSuspend */
+
+ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+ using list2. */
+ pxDelayedTaskList = &xDelayedTaskList1;
+ pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+ #if ( INCLUDE_vTaskDelete == 1 )
+ {
+ BaseType_t xListIsEmpty;
+
+ /* ucTasksDeleted is used to prevent vTaskSuspendAll() being called
+ too often in the idle task. */
+ while( uxTasksDeleted > ( UBaseType_t ) 0U )
+ {
+ vTaskSuspendAll();
+ {
+ xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );
+ }
+ ( void ) xTaskResumeAll();
+
+ if( xListIsEmpty == pdFALSE )
+ {
+ TCB_t *pxTCB;
+
+ taskENTER_CRITICAL();
+ {
+ pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+ ( void ) uxListRemove( &( pxTCB->xGenericListItem ) );
+ --uxCurrentNumberOfTasks;
+ --uxTasksDeleted;
+ }
+ taskEXIT_CRITICAL();
+
+ prvDeleteTCB( pxTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ #endif /* vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( const TickType_t xTimeToWake )
+{
+ /* The list item will be inserted in wake time order. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xGenericListItem ), xTimeToWake );
+
+ if( xTimeToWake < xTickCount )
+ {
+ /* Wake time has overflowed. Place this item in the overflow list. */
+ vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );
+ }
+ else
+ {
+ /* The wake time has not overflowed, so the current block list is used. */
+ vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xGenericListItem ) );
+
+ /* If the task entering the blocked state was placed at the head of the
+ list of blocked tasks then xNextTaskUnblockTime needs to be updated
+ too. */
+ if( xTimeToWake < xNextTaskUnblockTime )
+ {
+ xNextTaskUnblockTime = xTimeToWake;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static TCB_t *prvAllocateTCBAndStack( const uint16_t usStackDepth, StackType_t * const puxStackBuffer )
+{
+TCB_t *pxNewTCB;
+
+ /* Allocate space for the TCB. Where the memory comes from depends on
+ the implementation of the port malloc function. */
+ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+ if( pxNewTCB != NULL )
+ {
+ /* Allocate space for the stack used by the task being created.
+ The base of the stack memory stored in the TCB so the task can
+ be deleted later if required. */
+ pxNewTCB->pxStack = ( StackType_t * ) pvPortMallocAligned( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ), puxStackBuffer ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ if( pxNewTCB->pxStack == NULL )
+ {
+ /* Could not allocate the stack. Delete the allocated TCB. */
+ vPortFree( pxNewTCB );
+ pxNewTCB = NULL;
+ }
+ else
+ {
+ /* Avoid dependency on memset() if it is not required. */
+ #if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+ {
+ /* Just to help debugging. */
+ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) usStackDepth * sizeof( StackType_t ) );
+ }
+ #endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */
+ }
+ }
+
+ return pxNewTCB;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+ static UBaseType_t prvListTaskWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+ {
+ volatile TCB_t *pxNextTCB, *pxFirstTCB;
+ UBaseType_t uxTask = 0;
+
+ if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+ {
+ listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+ /* Populate an TaskStatus_t structure within the
+ pxTaskStatusArray array for each task that is referenced from
+ pxList. See the definition of TaskStatus_t in task.h for the
+ meaning of each TaskStatus_t structure member. */
+ do
+ {
+ listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+
+ pxTaskStatusArray[ uxTask ].xHandle = ( TaskHandle_t ) pxNextTCB;
+ pxTaskStatusArray[ uxTask ].pcTaskName = ( const char * ) &( pxNextTCB->pcTaskName [ 0 ] );
+ pxTaskStatusArray[ uxTask ].xTaskNumber = pxNextTCB->uxTCBNumber;
+ pxTaskStatusArray[ uxTask ].eCurrentState = eState;
+ pxTaskStatusArray[ uxTask ].uxCurrentPriority = pxNextTCB->uxPriority;
+
+ #if ( INCLUDE_vTaskSuspend == 1 )
+ {
+ /* If the task is in the suspended list then there is a chance
+ it is actually just blocked indefinitely - so really it should
+ be reported as being in the Blocked state. */
+ if( eState == eSuspended )
+ {
+ if( listLIST_ITEM_CONTAINER( &( pxNextTCB->xEventListItem ) ) != NULL )
+ {
+ pxTaskStatusArray[ uxTask ].eCurrentState = eBlocked;
+ }
+ }
+ }
+ #endif /* INCLUDE_vTaskSuspend */
+
+ #if ( configUSE_MUTEXES == 1 )
+ {
+ pxTaskStatusArray[ uxTask ].uxBasePriority = pxNextTCB->uxBasePriority;
+ }
+ #else
+ {
+ pxTaskStatusArray[ uxTask ].uxBasePriority = 0;
+ }
+ #endif
+
+ #if ( configGENERATE_RUN_TIME_STATS == 1 )
+ {
+ pxTaskStatusArray[ uxTask ].ulRunTimeCounter = pxNextTCB->ulRunTimeCounter;
+ }
+ #else
+ {
+ pxTaskStatusArray[ uxTask ].ulRunTimeCounter = 0;
+ }
+ #endif
+
+ #if ( portSTACK_GROWTH > 0 )
+ {
+ pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxEndOfStack );
+ }
+ #else
+ {
+ pxTaskStatusArray[ uxTask ].usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxNextTCB->pxStack );
+ }
+ #endif
+
+ uxTask++;
+
+ } while( pxNextTCB != pxFirstTCB );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return uxTask;
+ }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+ static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+ {
+ uint32_t ulCount = 0U;
+
+ while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+ {
+ pucStackByte -= portSTACK_GROWTH;
+ ulCount++;
+ }
+
+ ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+ return ( uint16_t ) ulCount;
+ }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+ UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+ {
+ TCB_t *pxTCB;
+ uint8_t *pucEndOfStack;
+ UBaseType_t uxReturn;
+
+ pxTCB = prvGetTCBFromHandle( xTask );
+
+ #if portSTACK_GROWTH < 0
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+ }
+ #else
+ {
+ pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+ }
+ #endif
+
+ uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+ return uxReturn;
+ }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+ static void prvDeleteTCB( TCB_t *pxTCB )
+ {
+ /* This call is required specifically for the TriCore port. It must be
+ above the vPortFree() calls. The call is also used by ports/demos that
+ want to allocate and clean RAM statically. */
+ portCLEAN_UP_TCB( pxTCB );
+
+ /* Free up the memory allocated by the scheduler for the task. It is up
+ to the task to free any memory allocated at the application level. */
+ #if ( configUSE_NEWLIB_REENTRANT == 1 )
+ {
+ _reclaim_reent( &( pxTCB->xNewLib_reent ) );
+ }
+ #endif /* configUSE_NEWLIB_REENTRANT */
+ vPortFreeAligned( pxTCB->pxStack );
+ vPortFree( pxTCB );
+ }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+ if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+ {
+ /* The new current delayed list is empty. Set
+ xNextTaskUnblockTime to the maximum possible value so it is
+ extremely unlikely that the
+ if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+ there is an item in the delayed list. */
+ xNextTaskUnblockTime = portMAX_DELAY;
+ }
+ else
+ {
+ /* The new current delayed list is not empty, get the value of
+ the item at the head of the delayed list. This is the time at
+ which the task at the head of the delayed list should be removed
+ from the Blocked state. */
+ ( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xGenericListItem ) );
+ }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+ TaskHandle_t xTaskGetCurrentTaskHandle( void )
+ {
+ TaskHandle_t xReturn;
+
+ /* A critical section is not required as this is not called from
+ an interrupt and the current TCB will always be the same for any
+ individual execution thread. */
+ xReturn = pxCurrentTCB;
+
+ return xReturn;
+ }
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+ BaseType_t xTaskGetSchedulerState( void )
+ {
+ BaseType_t xReturn;
+
+ if( xSchedulerRunning == pdFALSE )
+ {
+ xReturn = taskSCHEDULER_NOT_STARTED;
+ }
+ else
+ {
+ if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+ {
+ xReturn = taskSCHEDULER_RUNNING;
+ }
+ else
+ {
+ xReturn = taskSCHEDULER_SUSPENDED;
+ }
+ }
+
+ return xReturn;
+ }
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+ {
+ TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+
+ /* If the mutex was given back by an interrupt while the queue was
+ locked then the mutex holder might now be NULL. */
+ if( pxMutexHolder != NULL )
+ {
+ if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )
+ {
+ /* Adjust the mutex holder state to account for its new
+ priority. Only reset the event list item value if the value is
+ not being used for anything else. */
+ if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+ {
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* If the task being modified is in the ready state it will need to
+ be moved into a new list. */
+ if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xGenericListItem ) ) != pdFALSE )
+ {
+ if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Inherit the priority before being moved into the new list. */
+ pxTCB->uxPriority = pxCurrentTCB->uxPriority;
+ prvAddTaskToReadyList( pxTCB );
+ }
+ else
+ {
+ /* Just inherit the priority. */
+ pxTCB->uxPriority = pxCurrentTCB->uxPriority;
+ }
+
+ traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+ {
+ TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+ BaseType_t xReturn = pdFALSE;
+
+ if( pxMutexHolder != NULL )
+ {
+ configASSERT( pxTCB->uxMutexesHeld );
+ ( pxTCB->uxMutexesHeld )--;
+
+ if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+ {
+ /* Only disinherit if no other mutexes are held. */
+ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+ {
+ /* The holding task must be the running task to be able to give
+ the mutex back. Remove the holding task from the ready list. */
+ if( uxListRemove( &( pxTCB->xGenericListItem ) ) == ( UBaseType_t ) 0 )
+ {
+ taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Disinherit the priority before adding the task into the new
+ ready list. */
+ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+ pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+ /* Reset the event list item value. It cannot be in use for
+ any other purpose if this task is running, and it must be
+ running to give back the mutex. */
+ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+ prvAddTaskToReadyList( pxTCB );
+
+ /* Return true to indicate that a context switch is required.
+ This is only actually required in the corner case whereby
+ multiple mutexes were held and the mutexes were given back
+ in an order different to that in which they were taken. */
+ xReturn = pdTRUE;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+ }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+ void vTaskEnterCritical( void )
+ {
+ portDISABLE_INTERRUPTS();
+
+ if( xSchedulerRunning != pdFALSE )
+ {
+ ( pxCurrentTCB->uxCriticalNesting )++;
+
+ /* This is not the interrupt safe version of the enter critical
+ function so assert() if it is being called from an interrupt
+ context. Only API functions that end in "FromISR" can be used in an
+ interrupt. Only assert if the critical nesting count is 1 to
+ protect against recursive calls if the assert function also uses a
+ critical section. */
+ if( pxCurrentTCB->uxCriticalNesting == 1 )
+ {
+ portASSERT_IF_IN_ISR();
+ }
+
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+ void vTaskExitCritical( void )
+ {
+ if( xSchedulerRunning != pdFALSE )
+ {
+ if( pxCurrentTCB->uxCriticalNesting > 0U )
+ {
+ ( pxCurrentTCB->uxCriticalNesting )--;
+
+ if( pxCurrentTCB->uxCriticalNesting == 0U )
+ {
+ portENABLE_INTERRUPTS();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )
+
+ void vTaskList( char * pcWriteBuffer )
+ {
+ TaskStatus_t *pxTaskStatusArray;
+ volatile UBaseType_t uxArraySize, x;
+ char cStatus;
+
+ /*
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many
+ * of the demo applications. Do not consider it to be part of the
+ * scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that
+ * displays task names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that
+ * might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms. An alternative, tiny, third party,
+ * and limited functionality implementation of sprintf() is provided in
+ * many of the FreeRTOS/Demo sub-directories in a file called
+ * printf-stdarg.c (note printf-stdarg.c does not provide a full
+ * snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly
+ * through a call to vTaskList().
+ */
+
+
+ /* Make sure the write buffer does not contain a string. */
+ *pcWriteBuffer = 0x00;
+
+ /* Take a snapshot of the number of tasks in case it changes while this
+ function is executing. */
+ uxArraySize = uxCurrentNumberOfTasks;
+
+ /* Allocate an array index for each task. */
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+ if( pxTaskStatusArray != NULL )
+ {
+ /* Generate the (binary) data. */
+ uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+ /* Create a human readable table from the binary data. */
+ for( x = 0; x < uxArraySize; x++ )
+ {
+ switch( pxTaskStatusArray[ x ].eCurrentState )
+ {
+ case eReady: cStatus = tskREADY_CHAR;
+ break;
+
+ case eBlocked: cStatus = tskBLOCKED_CHAR;
+ break;
+
+ case eSuspended: cStatus = tskSUSPENDED_CHAR;
+ break;
+
+ case eDeleted: cStatus = tskDELETED_CHAR;
+ break;
+
+ default: /* Should not get here, but it is included
+ to prevent static checking errors. */
+ cStatus = 0x00;
+ break;
+ }
+
+ sprintf( pcWriteBuffer, "%s\t\t%c\t%u\t%u\t%u\r\n", pxTaskStatusArray[ x ].pcTaskName, cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
+ pcWriteBuffer += strlen( pcWriteBuffer );
+ }
+
+ /* Free the array again. */
+ vPortFree( pxTaskStatusArray );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) )
+
+ void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ {
+ TaskStatus_t *pxTaskStatusArray;
+ volatile UBaseType_t uxArraySize, x;
+ uint32_t ulTotalTime, ulStatsAsPercentage;
+
+ #if( configUSE_TRACE_FACILITY != 1 )
+ {
+ #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+ }
+ #endif
+
+ /*
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many
+ * of the demo applications. Do not consider it to be part of the
+ * scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+ * of the uxTaskGetSystemState() output into a human readable table that
+ * displays the amount of time each task has spent in the Running state
+ * in both absolute and percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+ * function that might bloat the code size, use a lot of stack, and
+ * provide different results on different platforms. An alternative,
+ * tiny, third party, and limited functionality implementation of
+ * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+ * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+ * a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly
+ * through a call to vTaskGetRunTimeStats().
+ */
+
+ /* Make sure the write buffer does not contain a string. */
+ *pcWriteBuffer = 0x00;
+
+ /* Take a snapshot of the number of tasks in case it changes while this
+ function is executing. */
+ uxArraySize = uxCurrentNumberOfTasks;
+
+ /* Allocate an array index for each task. */
+ pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+ if( pxTaskStatusArray != NULL )
+ {
+ /* Generate the (binary) data. */
+ uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+ /* For percentage calculations. */
+ ulTotalTime /= 100UL;
+
+ /* Avoid divide by zero errors. */
+ if( ulTotalTime > 0 )
+ {
+ /* Create a human readable table from the binary data. */
+ for( x = 0; x < uxArraySize; x++ )
+ {
+ /* What percentage of the total run time has the task used?
+ This will always be rounded down to the nearest integer.
+ ulTotalRunTimeDiv100 has already been divided by 100. */
+ ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+ if( ulStatsAsPercentage > 0UL )
+ {
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+ {
+ sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ }
+ #else
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ printf() library can be used. */
+ sprintf( pcWriteBuffer, "%s\t\t%u\t\t%u%%\r\n", pxTaskStatusArray[ x ].pcTaskName, ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
+ }
+ #endif
+ }
+ else
+ {
+ /* If the percentage is zero here then the task has
+ consumed less than 1% of the total run time. */
+ #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+ {
+ sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
+ #else
+ {
+ /* sizeof( int ) == sizeof( long ) so a smaller
+ printf() library can be used. */
+ sprintf( pcWriteBuffer, "%s\t\t%u\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+ }
+ #endif
+ }
+
+ pcWriteBuffer += strlen( pcWriteBuffer );
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Free the array again. */
+ vPortFree( pxTaskStatusArray );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+ uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+ /* Reset the event list item to its normal value - so it can be used with
+ queues and semaphores. */
+ listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+ return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+ void *pvTaskIncrementMutexHeldCount( void )
+ {
+ /* If xSemaphoreCreateMutex() is called before any tasks have been created
+ then pxCurrentTCB will be NULL. */
+ if( pxCurrentTCB != NULL )
+ {
+ ( pxCurrentTCB->uxMutexesHeld )++;
+ }
+
+ return pxCurrentTCB;
+ }
+
+#endif /* configUSE_MUTEXES */
+
+/*-----------------------------------------------------------*/
+
+#ifdef FREERTOS_MODULE_TEST
+ #include "tasks_test_access_functions.h"
+#endif
+
diff --git a/cc3200/FreeRTOS/Source/timers.c b/cc3200/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000000..32e89a1f07
--- /dev/null
+++ b/cc3200/FreeRTOS/Source/timers.c
@@ -0,0 +1,885 @@
+/*
+ FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+ All rights reserved
+
+ VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+ ***************************************************************************
+ * *
+ * FreeRTOS provides completely free yet professionally developed, *
+ * robust, strictly quality controlled, supported, and cross *
+ * platform software that has become a de facto standard. *
+ * *
+ * Help yourself get started quickly and support the FreeRTOS *
+ * project by purchasing a FreeRTOS tutorial book, reference *
+ * manual, or both from: http://www.FreeRTOS.org/Documentation *
+ * *
+ * Thank you! *
+ * *
+ ***************************************************************************
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+ >>! NOTE: The modification to the GPL is included to allow you to !<<
+ >>! distribute a combined work that includes FreeRTOS without being !<<
+ >>! obliged to provide the source code for proprietary components !<<
+ >>! outside of the FreeRTOS kernel. !<<
+
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ FOR A PARTICULAR PURPOSE. Full license text is available from the following
+ link: http://www.freertos.org/a00114.html
+
+ 1 tab == 4 spaces!
+
+ ***************************************************************************
+ * *
+ * Having a problem? Start by reading the FAQ "My application does *
+ * not run, what could be wrong?" *
+ * *
+ * http://www.FreeRTOS.org/FAQHelp.html *
+ * *
+ ***************************************************************************
+
+ http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ license and Real Time Engineers Ltd. contact details.
+
+ http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+ http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+ Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
+ licenses offer ticketed support, indemnification and middleware.
+
+ http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+ engineered and independently SIL3 certified version for use in safety and
+ mission critical applications that require provable dependability.
+
+ 1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers. That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+ #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality. This #if is closed at the very bottom
+of this file. If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY ( TickType_t ) 0U
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl
+{
+ const char *pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+ ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */
+ TickType_t xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+ UBaseType_t uxAutoReload; /*<< Set to pdTRUE if the timer should be automatically restarted once expired. Set to pdFALSE if the timer is, in effect, a one-shot timer. */
+ void *pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */
+ TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */
+ #if( configUSE_TRACE_FACILITY == 1 )
+ UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+ #endif
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback. The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+ TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+ Timer_t * pxTimer; /*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+ PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
+ void *pvParameter1; /* << The value that will be used as the callback functions first parameter. */
+ uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+ BaseType_t xMessageID; /*<< The command being sent to the timer service task. */
+ union
+ {
+ TimerParameter_t xTimerParameters;
+
+ /* Don't include xCallbackParameters if it is not going to be used as
+ it makes the structure (and therefore the timer queue) larger. */
+ #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+ CallbackParameters_t xCallbackParameters;
+ #endif /* INCLUDE_xTimerPendFunctionCall */
+ } u;
+} DaemonTaskMessage_t;
+
+/*lint -e956 A manual analysis and inspection has been used to determine which
+static variables must be declared volatile. */
+
+/* The list in which active timers are stored. Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list. Only the
+timer service task is allowed to access these lists. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+
+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
+
+ PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+#endif
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon). Timer functionality is controlled by this
+ * task. Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time. Reload the timer if it is an
+ * auto reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed. Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false. If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it. Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+ /* This function is called when the scheduler is started if
+ configUSE_TIMERS is set to 1. Check that the infrastructure used by the
+ timer service task has been created/initialised. If timers have already
+ been created then the initialisation will already have been performed. */
+ prvCheckForValidListAndQueue();
+
+ if( xTimerQueue != NULL )
+ {
+ #if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
+ {
+ /* Create the timer task, storing its handle in xTimerTaskHandle so
+ it can be returned by the xTimerGetTimerDaemonTaskHandle() function. */
+ xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, &xTimerTaskHandle );
+ }
+ #else
+ {
+ /* Create the timer task without storing its handle. */
+ xReturn = xTaskCreate( prvTimerTask, "Tmr Svc", ( uint16_t ) configTIMER_TASK_STACK_DEPTH, NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, NULL);
+ }
+ #endif
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ configASSERT( xReturn );
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxNewTimer;
+
+ /* Allocate the timer structure. */
+ if( xTimerPeriodInTicks == ( TickType_t ) 0U )
+ {
+ pxNewTimer = NULL;
+ }
+ else
+ {
+ pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+ if( pxNewTimer != NULL )
+ {
+ /* Ensure the infrastructure used by the timer service task has been
+ created/initialised. */
+ prvCheckForValidListAndQueue();
+
+ /* Initialise the timer structure members using the function parameters. */
+ pxNewTimer->pcTimerName = pcTimerName;
+ pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+ pxNewTimer->uxAutoReload = uxAutoReload;
+ pxNewTimer->pvTimerID = pvTimerID;
+ pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+ vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+
+ traceTIMER_CREATE( pxNewTimer );
+ }
+ else
+ {
+ traceTIMER_CREATE_FAILED();
+ }
+ }
+
+ /* 0 is not a valid value for xTimerPeriodInTicks. */
+ configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+ return ( TimerHandle_t ) pxNewTimer;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+ /* Send a message to the timer service task to perform a particular action
+ on a particular timer definition. */
+ if( xTimerQueue != NULL )
+ {
+ /* Send a command to the timer service task to start the xTimer timer. */
+ xMessage.xMessageID = xCommandID;
+ xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+ xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
+
+ if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+ {
+ if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+ {
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+ }
+ else
+ {
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+ }
+ }
+ else
+ {
+ xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+ }
+
+ traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTimerGetTimerDaemonTaskHandle == 1 )
+
+ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+ {
+ /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+ started, then xTimerTaskHandle will be NULL. */
+ configASSERT( ( xTimerTaskHandle != NULL ) );
+ return xTimerTaskHandle;
+ }
+
+#endif
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetTimerName( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+ return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+ /* Remove the timer from the list of active timers. A check has already
+ been performed to ensure the list is not empty. */
+ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ traceTIMER_EXPIRED( pxTimer );
+
+ /* If the timer is an auto reload timer then calculate the next
+ expiry time and re-insert the timer in the list of active timers. */
+ if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+ {
+ /* The timer is inserted into a list using a time relative to anything
+ other than the current time. It will therefore be inserted into the
+ correct list relative to the time this task thinks it is now. */
+ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) == pdTRUE )
+ {
+ /* The timer expired before it was added to the active timer
+ list. Reload it now. */
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ configASSERT( xResult );
+ ( void ) xResult;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ /* Call the timer callback. */
+ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTimerTask( void *pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+ /* Just to avoid compiler warnings. */
+ ( void ) pvParameters;
+
+ for( ;; )
+ {
+ /* Query the timers list to see if it contains any timers, and if so,
+ obtain the time at which the next timer will expire. */
+ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+ /* If a timer has expired, process it. Otherwise, block this task
+ until either a timer does expire, or a command is received. */
+ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+ /* Empty the command queue. */
+ prvProcessReceivedCommands();
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, const BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+ vTaskSuspendAll();
+ {
+ /* Obtain the time now to make an assessment as to whether the timer
+ has expired or not. If obtaining the time causes the lists to switch
+ then don't process this timer as any timers that remained in the list
+ when the lists were switched will have been processed within the
+ prvSampleTimeNow() function. */
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+ if( xTimerListsWereSwitched == pdFALSE )
+ {
+ /* The tick count has not overflowed, has the timer expired? */
+ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+ {
+ ( void ) xTaskResumeAll();
+ prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+ }
+ else
+ {
+ /* The tick count has not overflowed, and the next expire
+ time has not been reached yet. This task should therefore
+ block to wait for the next expire time or a command to be
+ received - whichever comes first. The following line cannot
+ be reached unless xNextExpireTime > xTimeNow, except in the
+ case when the current timer list is empty. */
+ vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ) );
+
+ if( xTaskResumeAll() == pdFALSE )
+ {
+ /* Yield to wait for either a command to arrive, or the block time
+ to expire. If a command arrived between the critical section being
+ exited and this yield then the yield will not cause the task
+ to block. */
+ portYIELD_WITHIN_API();
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ }
+ else
+ {
+ ( void ) xTaskResumeAll();
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+ /* Timers are listed in expiry time order, with the head of the list
+ referencing the task that will expire first. Obtain the time at which
+ the timer with the nearest expiry time will expire. If there are no
+ active timers then just set the next expire time to 0. That will cause
+ this task to unblock when the tick count overflows, at which point the
+ timer lists will be switched and the next expiry time can be
+ re-assessed. */
+ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+ if( *pxListWasEmpty == pdFALSE )
+ {
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+ }
+ else
+ {
+ /* Ensure the task unblocks when the tick count rolls over. */
+ xNextExpireTime = ( TickType_t ) 0U;
+ }
+
+ return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+ xTimeNow = xTaskGetTickCount();
+
+ if( xTimeNow < xLastTime )
+ {
+ prvSwitchTimerLists();
+ *pxTimerListsWereSwitched = pdTRUE;
+ }
+ else
+ {
+ *pxTimerListsWereSwitched = pdFALSE;
+ }
+
+ xLastTime = xTimeNow;
+
+ return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+ if( xNextExpiryTime <= xTimeNow )
+ {
+ /* Has the expiry time elapsed between the command to start/reset a
+ timer was issued, and the time the command was processed? */
+ if( ( xTimeNow - xCommandTime ) >= pxTimer->xTimerPeriodInTicks )
+ {
+ /* The time between a command being issued and the command being
+ processed actually exceeds the timers period. */
+ xProcessTimerNow = pdTRUE;
+ }
+ else
+ {
+ vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+ }
+ }
+ else
+ {
+ if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+ {
+ /* If, since the command was issued, the tick count has overflowed
+ but the expiry time has not, then the timer must have already passed
+ its expiry time and should be processed immediately. */
+ xProcessTimerNow = pdTRUE;
+ }
+ else
+ {
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ }
+ }
+
+ return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+ while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+ {
+ #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+ {
+ /* Negative commands are pended function calls rather than timer
+ commands. */
+ if( xMessage.xMessageID < ( BaseType_t ) 0 )
+ {
+ const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+ /* The timer uses the xCallbackParameters member to request a
+ callback be executed. Check the callback is not NULL. */
+ configASSERT( pxCallback );
+
+ /* Call the function. */
+ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* INCLUDE_xTimerPendFunctionCall */
+
+ /* Commands that are positive are timer commands rather than pended
+ function calls. */
+ if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+ {
+ /* The messages uses the xTimerParameters member to work on a
+ software timer. */
+ pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+ if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
+ {
+ /* The timer is in a list, remove it. */
+ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+
+ traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+ /* In this case the xTimerListsWereSwitched parameter is not used, but
+ it must be present in the function call. prvSampleTimeNow() must be
+ called after the message is received from xTimerQueue so there is no
+ possibility of a higher priority task adding a message to the message
+ queue with a time that is ahead of the timer daemon task (because it
+ pre-empted the timer daemon task after the xTimeNow value was set). */
+ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+ switch( xMessage.xMessageID )
+ {
+ case tmrCOMMAND_START :
+ case tmrCOMMAND_START_FROM_ISR :
+ case tmrCOMMAND_RESET :
+ case tmrCOMMAND_RESET_FROM_ISR :
+ case tmrCOMMAND_START_DONT_TRACE :
+ /* Start or restart a timer. */
+ if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) == pdTRUE )
+ {
+ /* The timer expired before it was added to the active
+ timer list. Process it now. */
+ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+ traceTIMER_EXPIRED( pxTimer );
+
+ if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+ {
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+ configASSERT( xResult );
+ ( void ) xResult;
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ break;
+
+ case tmrCOMMAND_STOP :
+ case tmrCOMMAND_STOP_FROM_ISR :
+ /* The timer has already been removed from the active list.
+ There is nothing to do here. */
+ break;
+
+ case tmrCOMMAND_CHANGE_PERIOD :
+ case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+ pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+ configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+ /* The new period does not really have a reference, and can be
+ longer or shorter than the old one. The command time is
+ therefore set to the current time, and as the period cannot be
+ zero the next expiry time can only be in the future, meaning
+ (unlike for the xTimerStart() case above) there is no fail case
+ that needs to be handled here. */
+ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+ break;
+
+ case tmrCOMMAND_DELETE :
+ /* The timer has already been removed from the active list,
+ just free up the memory. */
+ vPortFree( pxTimer );
+ break;
+
+ default :
+ /* Don't expect to get here. */
+ break;
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+ /* The tick count has overflowed. The timer lists must be switched.
+ If there are any timers still referenced from the current timer list
+ then they must have expired and should be processed before the lists
+ are switched. */
+ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+ {
+ xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+ /* Remove the timer from the list. */
+ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+ traceTIMER_EXPIRED( pxTimer );
+
+ /* Execute its callback, then send a command to restart the timer if
+ it is an auto-reload timer. It cannot be restarted here as the lists
+ have not yet been switched. */
+ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+ if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+ {
+ /* Calculate the reload value, and if the reload value results in
+ the timer going into the same timer list then it has already expired
+ and the timer should be re-inserted into the current list so it is
+ processed again within this loop. Otherwise a command should be sent
+ to restart the timer to ensure it is only inserted into a list after
+ the lists have been swapped. */
+ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+ if( xReloadTime > xNextExpireTime )
+ {
+ listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+ listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+ vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+ }
+ else
+ {
+ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+ configASSERT( xResult );
+ ( void ) xResult;
+ }
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+
+ pxTemp = pxCurrentTimerList;
+ pxCurrentTimerList = pxOverflowTimerList;
+ pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+ /* Check that the list from which active timers are referenced, and the
+ queue used to communicate with the timer service, have been
+ initialised. */
+ taskENTER_CRITICAL();
+ {
+ if( xTimerQueue == NULL )
+ {
+ vListInitialise( &xActiveTimerList1 );
+ vListInitialise( &xActiveTimerList2 );
+ pxCurrentTimerList = &xActiveTimerList1;
+ pxOverflowTimerList = &xActiveTimerList2;
+ xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+ configASSERT( xTimerQueue );
+
+ #if ( configQUEUE_REGISTRY_SIZE > 0 )
+ {
+ if( xTimerQueue != NULL )
+ {
+ vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ #endif /* configQUEUE_REGISTRY_SIZE */
+ }
+ else
+ {
+ mtCOVERAGE_TEST_MARKER();
+ }
+ }
+ taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xTimerIsInActiveList;
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+ /* Is the timer in the list of active timers? */
+ taskENTER_CRITICAL();
+ {
+ /* Checking to see if it is in the NULL list in effect checks to see if
+ it is referenced from either the current or the overflow timer lists in
+ one go, but the logic has to be reversed, hence the '!'. */
+ xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );
+ }
+ taskEXIT_CRITICAL();
+
+ return xTimerIsInActiveList;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+
+ return pxTimer->pvTimerID;
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+ BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+ {
+ DaemonTaskMessage_t xMessage;
+ BaseType_t xReturn;
+
+ /* Complete the message with the function parameters and post it to the
+ daemon task. */
+ xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+ xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+ xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+ xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+ xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+ tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+ return xReturn;
+ }
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+ {
+ DaemonTaskMessage_t xMessage;
+ BaseType_t xReturn;
+
+ /* Complete the message with the function parameters and post it to the
+ daemon task. */
+ xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+ xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+ xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+ xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+ xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+ tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+ return xReturn;
+ }
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality. If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/cc3200/Makefile b/cc3200/Makefile
new file mode 100644
index 0000000000..246445fb57
--- /dev/null
+++ b/cc3200/Makefile
@@ -0,0 +1,40 @@
+# Select the board to build for: if not given on the command line,
+# then default to LAUNCHXL
+BOARD ?= LAUNCHXL
+ifeq ($(wildcard boards/$(BOARD)/.),)
+$(error Invalid BOARD specified)
+endif
+
+# If the build directory is not given, make it reflect the board name.
+BUILD ?= build/$(BOARD)
+
+include ../py/mkenv.mk
+-include ../../localconfig.mk
+
+CROSS_COMPILE ?= arm-none-eabi-
+
+BTYPE ?= release
+
+CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -march=armv7e-m -mabi=aapcs -mcpu=cortex-m4 -msoft-float -mfloat-abi=soft -fsingle-precision-constant -Wdouble-promotion
+CFLAGS = -Wall -Wpointer-arith -Werror -ansi -std=gnu99 -nostdlib $(CFLAGS_CORTEX_M4)
+CFLAGS += -g -ffunction-sections -fdata-sections -fno-common -fsigned-char -mno-unaligned-access
+CFLAGS += -Iboards/$(BOARD)
+
+LDFLAGS = -Wl,-nostdlib -Wl,--gc-sections -Wl,-Map=$@.map --specs=nano.specs
+
+ifeq ($(BTARGET), application)
+# qstr definitions (must come before including py.mk)
+QSTR_DEFS = qstrdefsport.h $(BUILD)/pins_qstr.h
+# include MicroPython make definitions
+include ../py/py.mk
+include application.mk
+else
+ifeq ($(BTARGET), bootloader)
+include bootmgr/bootloader.mk
+else
+$(error Invalid BTARGET specified)
+endif
+endif
+
+# always include MicroPython make rules
+include ../py/mkrules.mk
diff --git a/cc3200/README.md b/cc3200/README.md
new file mode 100644
index 0000000000..9ba83b0fb0
--- /dev/null
+++ b/cc3200/README.md
@@ -0,0 +1,82 @@
+# Build Instructions for the CC3200
+
+Currently the CC3200 port of Micro Python builds under Linux and OSX and not under Windows.
+
+The tool chain required for the build can be found at .
+
+In order to download the image to the CC3200 you will need the CCS_Uniflash tool from TI, which at this
+moment is only available for Windows, so, you need Linux/OSX to build and Windows to flash the image.
+
+## To build an image suitable for debugging:
+
+In order to debug the port specific code, optimizations need to be disabled on the
+port file (check the Makefile for specific details). You can use CCS from TI.
+Use the CC3200.ccxml file supplied with this distribution for the debuuger configuration.
+```bash
+make BTARGET=application BTYPE=debug
+```
+## To build an image suitable to be flashed to the device:
+```bash
+make BTARGET=application BTYPE=release
+```
+## Building the bootloader
+```bash
+make BTARGET=bootloader BTYPE=release
+```
+
+## Flashing the CC3200
+- Make sure the SOP2 jumper is in position.
+- Open CCS_Uniflash and connect to the board (by default on port 22).
+- Format the serial flash (select 1MB size in case of the CC3200-LAUNCHXL, leave the rest unchecked).
+- Mark the following files for erasing: `/cert/ca.pem`, `/cert/client.pm`, `/cert/private.key` and `/tmp/pac.bin`.
+- Add a new file with the name of /sys/factimg.bin, and select the correct URL to point to cc3200\build\\MCUIMG.BIN.
+- Click "Program" to apply all changes.
+- Flash the latest service pack (servicepack_1.0.0.1.2.bin) using the "Service Pack Update" button.
+- Close CCS_Uniflash, remove the SOP2 jumper and reset the board.
+
+## Playing with MicroPython and the CC3200:
+
+Once the software is running, you have two options to access the MicroPython REPL:
+
+- Through the UART.
+ **Connect to PORT 22, baud rate = 115200, parity = none, stop bits = 1**
+- Through telnet.
+ * Connect to the network created by the board (as boots up in AP mode), **ssid = "micropy-wlan", key = "micropython"**
+ * You can also reinitialize the WLAN in station mode and connect to another AP, or in AP mode but with a
+ different ssid and/or key.
+ * Use your favourite telnet client with the following settings: **host = 192.168.1.1, port = 23.**
+ * Log in with **user = "micro" and password = "python"**
+
+The board has a small file system of 64K located in the serial flash connected to the CC3200. SD cards are also supported, but
+since the CC3200 LaunchXL doesn't come with an SD card socket installed, you will need to add one yourself. Any SD card breakout
+board will do, as long as you connect it as described here:
+
+## Uploading scripts:
+
+To upload your MicroPython scripts to the FTP server, open your FTP client of choice and connect to:
+**ftp://192.168.1.1, user = "micro", password = "python"**
+
+I have tested the FTP server with **FileZilla, FireFTP, FireFox, IE and Chrome,** other clients should work as well, but I am
+not 100% sure of it.
+
+## Upgrading the firmware Over The Air:
+
+OTA software updates can be performed through the FTP server. After building a new MCUIMG.BIN in release mode, upload it to:
+`/SFLASH/SYS/MCUIMG.BIN` it will take around 8s (The TI simplelink file system is quite slow because every file is mirrored for
+safety). You won't see the file being stored inside `/SFLASH/SYS/` because it's actually saved bypassing FatFS, but rest assured that
+the file was successfully transferred, and it has been signed with a MD5 checksum to verify its integrity.
+Now, reset the MCU by pressing the switch on the board, or by typing:
+
+```python
+import pyb
+pyb.hard_reset()
+```
+
+### Note regarding FileZilla:
+
+Do not use the quick connect button, instead, open the site manager and create a new configuration. In the "General" tab make
+sure that encryption is set to: "Only use plain FTP (insecure)". In the Transfer Settings tab limit the max number of connections
+to one, otherwise FileZilla will try to open a second command connection when retrieving and saving files, and for simplicity and
+to reduce code size, only one command and one data connections are possible.
+
+
\ No newline at end of file
diff --git a/cc3200/application.lds b/cc3200/application.lds
new file mode 100644
index 0000000000..553b4400be
--- /dev/null
+++ b/cc3200/application.lds
@@ -0,0 +1,151 @@
+/*****************************************************************************
+* cc3200.lds
+*
+* GCC Linker script for the CC3200
+*
+* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+__stack_size__ = 1024; /* interrupts are handled using this stack */
+__min_heap_size__ = 4K;
+__rtos_heap_size = 16K;
+
+MEMORY
+{
+ SRAMB (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+ SRAM (rwx) : ORIGIN = 0x20004000, LENGTH = 0x0003C000
+}
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ /* place the FreeRTOS heap (the micropython stack will live here) */
+ .rtos_heap (NOLOAD) :
+ {
+ . = ALIGN(8);
+ *(.rtos_heap*)
+ . = ALIGN(8);
+ } > SRAMB
+
+ _ertos_heap = ORIGIN(SRAMB) + LENGTH(SRAMB);
+
+ .text :
+ {
+ _text = .;
+ KEEP(*(.intvecs))
+ *(.text*)
+ *(.rodata*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(8);
+ } > SRAM
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ _etext = .;
+ } > SRAM
+
+ __init_data = .;
+
+ /* used by the start-up to initialize data */
+ _sidata = LOADADDR(.data);
+
+ .data : AT(__init_data)
+ {
+ . = ALIGN(8);
+ _data = .;
+ *(.data*)
+ . = ALIGN(8);
+ _edata = .;
+ } > SRAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ _ebss = .;
+ } > SRAM
+
+ /* allocate the micropython heap */
+ .heap :
+ {
+ . = ALIGN(8);
+ _heap = .;
+ . = . + __min_heap_size__;
+ . = . + (ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ - ABSOLUTE(.));
+ . = ALIGN(8);
+ _eheap = .;
+ } > SRAM
+
+ /* allocate the main stack */
+ .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :
+ {
+ . = ALIGN(8);
+ _stack = .;
+ . = . + __stack_size__;
+ . = ALIGN(8);
+ _estack = .;
+ } > SRAM
+}
diff --git a/cc3200/application.mk b/cc3200/application.mk
new file mode 100644
index 0000000000..6d8a869ed0
--- /dev/null
+++ b/cc3200/application.mk
@@ -0,0 +1,231 @@
+APP_INC = -I.
+APP_INC += -I..
+APP_INC += -Ifatfs/src
+APP_INC += -Ifatfs/src/drivers
+APP_INC += -IFreeRTOS
+APP_INC += -IFreeRTOS/Source/include
+APP_INC += -IFreeRTOS/Source/portable/GCC/ARM_CM3
+APP_INC += -Iftp
+APP_INC += -Ihal
+APP_INC += -Ihal/inc
+APP_INC += -Imisc
+APP_INC += -Imods
+APP_INC += -Isimplelink
+APP_INC += -Isimplelink/include
+APP_INC += -Isimplelink/oslib
+APP_INC += -Itelnet
+APP_INC += -Iutil
+APP_INC += -Ibootmgr
+APP_INC += -I$(PY_SRC)
+APP_INC += -I$(BUILD)
+APP_INC += -I../lib/fatfs
+APP_INC += -I../lib/mp-readline
+APP_INC += -I../stmhal
+
+APP_CPPDEFINES = -Dgcc -DTARGET_IS_CC3200 -DSL_FULL -DUSE_FREERTOS
+
+APP_FATFS_SRC_C = $(addprefix fatfs/src/,\
+ drivers/sflash_diskio.c \
+ drivers/sd_diskio.c \
+ option/syscall.c \
+ diskio.c \
+ ffconf.c \
+ )
+
+APP_RTOS_SRC_C = $(addprefix FreeRTOS/Source/,\
+ croutine.c \
+ event_groups.c \
+ list.c \
+ queue.c \
+ tasks.c \
+ timers.c \
+ portable/GCC/ARM_CM3/port.c \
+ portable/MemMang/heap_4.c \
+ )
+
+APP_FTP_SRC_C = $(addprefix ftp/,\
+ ftp.c \
+ updater.c \
+ )
+
+APP_HAL_SRC_C = $(addprefix hal/,\
+ adc.c \
+ aes.c \
+ cc3200_hal.c \
+ cpu.c \
+ crc.c \
+ des.c \
+ gpio.c \
+ i2c.c \
+ i2s.c \
+ interrupt.c \
+ pin.c \
+ prcm.c \
+ sdhost.c \
+ shamd5.c \
+ spi.c \
+ startup_gcc.c \
+ systick.c \
+ timer.c \
+ uart.c \
+ utils.c \
+ wdt.c \
+ )
+
+APP_MISC_SRC_C = $(addprefix misc/,\
+ FreeRTOSHooks.c \
+ gpio_named_pins.c \
+ help.c \
+ mperror.c \
+ mpexception.c \
+ pin_defs_cc3200.c \
+ )
+
+APP_MODS_SRC_C = $(addprefix mods/,\
+ modnetwork.c \
+ modpyb.c \
+ moduos.c \
+ modusocket.c \
+ modutime.c \
+ modwlan.c \
+ pybextint.c \
+ pybgpio.c \
+ pybrtc.c \
+ pybstdio.c \
+ pybsystick.c \
+ pybuart.c \
+ )
+
+APP_SL_SRC_C = $(addprefix simplelink/,\
+ source/device.c \
+ source/driver.c \
+ source/flowcont.c \
+ source/fs.c \
+ source/netapp.c \
+ source/netcfg.c \
+ source/socket.c \
+ source/wlan.c \
+ oslib/osi_freertos.c \
+ cc_pal.c \
+ )
+
+APP_TELNET_SRC_C = $(addprefix telnet/,\
+ telnet.c \
+ )
+
+APP_UTIL_SRC_C = $(addprefix util/,\
+ fifo.c \
+ gccollect.c \
+ random.c \
+ socketfifo.c \
+ )
+
+APP_UTIL_SRC_S = $(addprefix util/,\
+ gchelper.s \
+ )
+
+APP_MAIN_SRC_C = \
+ main.c \
+ mptask.c \
+ serverstask.c
+
+APP_LIB_SRC_C = $(addprefix lib/,\
+ fatfs/ff.c \
+ mp-readline/readline.c \
+ )
+
+APP_STM_SRC_C = $(addprefix stmhal/,\
+ bufhelper.c \
+ file.c \
+ import.c \
+ input.c \
+ irq.c \
+ lexerfatfs.c \
+ moduselect.c \
+ printf.c \
+ pyexec.c \
+ string0.c \
+ )
+
+OBJ = $(PY_O) $(addprefix $(BUILD)/, $(APP_FATFS_SRC_C:.c=.o) $(APP_RTOS_SRC_C:.c=.o) $(APP_FTP_SRC_C:.c=.o) $(APP_HAL_SRC_C:.c=.o) $(APP_MISC_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(APP_MODS_SRC_C:.c=.o) $(APP_SL_SRC_C:.c=.o) $(APP_TELNET_SRC_C:.c=.o) $(APP_UTIL_SRC_C:.c=.o) $(APP_UTIL_SRC_S:.s=.o))
+OBJ += $(addprefix $(BUILD)/, $(APP_MAIN_SRC_C:.c=.o) $(APP_LIB_SRC_C:.c=.o) $(APP_STM_SRC_C:.c=.o))
+OBJ += $(BUILD)/pins.o
+
+# Add the linker script
+LINKER_SCRIPT = application.lds
+LDFLAGS += -T $(LINKER_SCRIPT)
+
+# Add the application specific CFLAGS
+CFLAGS += $(APP_CPPDEFINES) $(APP_INC)
+
+# Disable strict aliasing for the simplelink driver
+$(BUILD)/simplelink/source/driver.o: CFLAGS += -fno-strict-aliasing
+
+# Check if we would like to debug the port code
+ifeq ($(BTYPE), release)
+# Optimize everything and define the NDEBUG flag
+CFLAGS += -Os -DNDEBUG
+else
+ifeq ($(BTYPE), debug)
+# Define the DEBUG flag
+CFLAGS += -DDEBUG=DEBUG
+# Optimize the stable sources only
+$(BUILD)/extmod/%.o: CFLAGS += -Os
+$(BUILD)/lib/%.o: CFLAGS += -Os
+$(BUILD)/fatfs/src/%.o: CFLAGS += -Os
+$(BUILD)/FreeRTOS/Source/%.o: CFLAGS += -Os
+$(BUILD)/ftp/%.o: CFLAGS += -Os
+$(BUILD)/hal/%.o: CFLAGS += -Os
+$(BUILD)/misc/%.o: CFLAGS += -Os
+$(BUILD)/py/%.o: CFLAGS += -Os
+$(BUILD)/simplelink/%.o: CFLAGS += -Os
+$(BUILD)/stmhal/%.o: CFLAGS += -Os
+$(BUILD)/telnet/%.o: CFLAGS += -Os
+$(BUILD)/util/%.o: CFLAGS += -Os
+$(BUILD)/pins.o: CFLAGS += -Os
+else
+$(error Invalid BTYPE specified)
+endif
+endif
+
+SHELL = bash
+APP_SIGN = appsign.sh
+
+all: $(BUILD)/MCUIMG.BIN
+
+$(BUILD)/application.axf: $(OBJ) $(LINKER_SCRIPT)
+ $(ECHO) "LINK $@"
+ $(Q)$(CC) -o $@ $(LDFLAGS) $(OBJ) $(LIBS)
+ $(Q)$(SIZE) $@
+
+$(BUILD)/application.bin: $(BUILD)/application.axf
+ $(ECHO) "Create $@"
+ $(Q)$(OBJCOPY) -O binary $< $@
+
+$(BUILD)/MCUIMG.BIN: $(BUILD)/application.bin
+ $(ECHO) "Create $@"
+ $(Q)$(SHELL) $(APP_SIGN) $(BOARD)
+
+MAKE_PINS = boards/make-pins.py
+BOARD_PINS = boards/$(BOARD)/pins.csv
+AF_FILE = boards/cc3200_af.csv
+PREFIX_FILE = boards/cc3200_prefix.c
+GEN_PINS_SRC = $(BUILD)/pins.c
+GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
+GEN_PINS_QSTR = $(BUILD)/pins_qstr.h
+
+# Making OBJ use an order-only dependency on the generated pins.h file
+# has the side effect of making the pins.h file before we actually compile
+# any of the objects. The normal dependency generation will deal with the
+# case when pins.h is modified. But when it doesn't exist, we don't know
+# which source files might need it.
+$(OBJ): | $(GEN_PINS_HDR)
+
+# Call make-pins.py to generate both pins_gen.c and pins.h
+$(GEN_PINS_SRC) $(GEN_PINS_HDR) $(GEN_PINS_QSTR): $(BOARD_PINS) $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD)
+ $(ECHO) "Create $@"
+ $(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) > $(GEN_PINS_SRC)
+
+$(BUILD)/pins.o: $(BUILD)/pins.c
+ $(call compile_c)
diff --git a/cc3200/appsign.sh b/cc3200/appsign.sh
new file mode 100644
index 0000000000..a4b9188872
--- /dev/null
+++ b/cc3200/appsign.sh
@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Build location
+# First parameter passed is the board type
+BUILD=build/$1
+
+# Generate the MD5 hash
+echo -n md5sum --binary $BUILD/application.bin | awk '{ print $1 }' > __md5hash.bin
+
+# Concatenate it with the application binary
+cat $BUILD/application.bin __md5hash.bin > $BUILD/MCUIMG.BIN
+
+# Remove the tmp files
+rm -f __md5hash.bin
+
+# Remove hte unsigned binary
+rm -f $BUILD/application.bin
diff --git a/cc3200/boards/LAUNCHXL/mpconfigboard.h b/cc3200/boards/LAUNCHXL/mpconfigboard.h
new file mode 100644
index 0000000000..9979621b2b
--- /dev/null
+++ b/cc3200/boards/LAUNCHXL/mpconfigboard.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define LAUNCHXL
+
+#define MICROPY_HW_BOARD_NAME "LaunchPad"
+#define MICROPY_HW_MCU_NAME "CC3200"
+
+#define MICROPY_HW_HAS_SDCARD (1)
+#define MICROPY_HW_ENABLE_RNG (1)
+#define MICROPY_HW_ENABLE_RTC (1)
+
+#define MICROPY_STDIO_UART PYB_UART_1
+#define MICROPY_STDIO_UART_BAUD 115200
diff --git a/cc3200/boards/LAUNCHXL/pins.csv b/cc3200/boards/LAUNCHXL/pins.csv
new file mode 100644
index 0000000000..38071e1307
--- /dev/null
+++ b/cc3200/boards/LAUNCHXL/pins.csv
@@ -0,0 +1,25 @@
+P12,58
+P13,4
+P14,3
+P15,61
+P16,59
+P17,5
+P18,62
+P19,1
+P110,2
+P33,57
+P34,60
+P37,63
+P38,53
+P39,64
+P310,50
+P49,16
+P410,17
+P22,18
+P23,8
+P24,45
+P26,7
+P27,6
+P28,21
+P29,55
+P210,15
\ No newline at end of file
diff --git a/cc3200/boards/cc3200_af.csv b/cc3200/boards/cc3200_af.csv
new file mode 100644
index 0000000000..746a8b08c6
--- /dev/null
+++ b/cc3200/boards/cc3200_af.csv
@@ -0,0 +1,66 @@
+Pin,Name,Default,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,ADC
+1,GPIO10,GPIO10,GPIO10,I2C_SCL,,GT_PWM06,,,SDCARD_CLK,UART1_TX,,,,,GT_CCP01,,,,
+2,GPIO11,GPIO11,GPIO11,I2C_SDA,,GT_PWM07,pXCLK(XVCLK),,SDCARD_CMD,UART1_RX,,,,,GT_CCP02,McAFSX,,,
+3,GPIO12,GPIO12,GPIO12,,,McACLK,pVS(VSYNC),I2C_SCL,,UART0_TX,,,,,GT_CCP03,,,,
+4,GPIO13,GPIO13,GPIO13,,,,pHS(HSYNC),I2C_SDA,,UART0_RX,,,,,GT_CCP04,,,,
+5,GPIO14,GPIO14,GPIO14,,,,pDATA8(CAM_D4),2C_SCL,,GSPI_CLK,,,,,GT_CCP05,,,,
+6,GPIO15,GPIO15,GPIO15,,,,pDATA9(CAM_D5),I2C_SDA,,GSPI_MISO,,,,,,GT_CCP06,,,
+7,GPIO16,GPIO16,GPIO16,,,,pDATA10(CAM_D6),UART1_TX,,GSPI_MOSI,,,,,,GT_CCP07,,,
+8,GPIO17,GPIO17,GPIO17,,,,pDATA11(CAM_D7),UART1_RX,,GSPI_CS,,,,,,,,,
+9,VDD_DIG1,VDD_DIG1,VDD_DIG1,,,,,,,,,,,,,,,,
+10,VIN_IO1,VIN_IO1,VIN_IO1,,,,,,,,,,,,,,,,
+11,FLASH_SPI_CLK,FLASH_SPI_CLK,FLASH_SPI_CLK,,,,,,,,,,,,,,,,
+12,FLASH_SPI_DOUT,FLASH_SPI_DOUT,FLASH_SPI_DOUT,,,,,,,,,,,,,,,,
+13,FLASH_SPI_DIN,FLASH_SPI_DIN,FLASH_SPI_DIN,,,,,,,,,,,,,,,,
+14,FLASH_SPI_CS,FLASH_SPI_CS,FLASH_SPI_CS,,,,,,,,,,,,,,,,
+15,GPIO22,GPIO22,GPIO22,,,,,GT_CCP04,,McAFSX,,,,,,,,,
+16,GPIO23,TDI,GPIO23,TDI,UART1_TX,,,,,,,2C_SCL,,,,,,,
+17,GPIO24,TDO,GPIO24,TDO,UART1_RX,,GT_CCP06,PWM0,McAFSX,,,I2C_SDA,,,,,,,
+18,GPIO28,GPIO28,GPIO28,,,,,,,,,,,,,,,,
+19,TCK,TCK,,TCK,,,,,,,GT_PWM03,,,,,,,,
+20,GPIO29,TMS,GPIO29,TMS,,,,,,,,,,,,,,,
+21,GPIO25,SOP2,GPIO25,,McAFSX,,,,,,,GT_PWM02,,,,,,,
+22,WLAN_XTAL_N,WLAN_XTAL_N,WLAN_XTAL_N,,,,,,,,,,,,,,,,
+23,WLAN_XTAL_P,WLAN_XTAL_P,WLAN_XTAL_P,,,,,,,,,,,,,,,,
+24,VDD_PLL,VDD_PLL,VDD_PLL,,,,,,,,,,,,,,,,
+25,LDO_IN2,LDO_IN2,LDO_IN2,,,,,,,,,,,,,,,,
+26,NC,NC,NC,,,,,,,,,,,,,,,,
+27,NC,NC,NC,,,,,,,,,,,,,,,,
+28,NC,NC,NC,,,,,,,,,,,,,,,,
+29,ANTSEL1,ANTSEL1,ANTSEL1,,,,,,,,,,,,,,,,
+30,ANTSEL2,ANTSEL2,ANTSEL2,,,,,,,,,,,,,,,,
+31,RF_BG,RF_BG,RF_BG,,,,,,,,,,,,,,,,
+32,nRESET,nRESET,nRESET,,,,,,,,,,,,,,,,
+33,VDD_PA_IN,VDD_PA_IN,VDD_PA_IN,,,,,,,,,,,,,,,,
+34,SOP1,SOP1,SOP1,,,,,,,,,,,,,,,,
+35,SOP0,SOP0,SOP0,,,,,,,,,,,,,,,,
+36,LDO_IN1,LDO_IN1,LDO_IN1,,,,,,,,,,,,,,,,
+37,VIN_DCDC_ANA,VIN_DCDC_ANA,VIN_DCDC_ANA,,,,,,,,,,,,,,,,
+38,DCDC_ANA_SW,DCDC_ANA_SW,DCDC_ANA_SW,,,,,,,,,,,,,,,,
+39,VIN_DCDC_PA,VIN_DCDC_ PA,VIN_DCDC_PA,,,,,,,,,,,,,,,,
+40,DCDC_PA_SW_P,DCDC_PA_SW_P,DCDC_PA_SW_P,,,,,,,,,,,,,,,,
+41,DCDC_PA_SW_N,DCDC_PA_SW_N,DCDC_PA_SW_N,,,,,,,,,,,,,,,,
+42,DCDC_PA_OUT,DCDC_PA_O UT,DCDC_PA_O UT,,,,,,,,,,,,,,,,
+43,DCDC_DIG_SW,DCDC_DIG_ SW,DCDC_DIG_ SW,,,,,,,,,,,,,,,,
+44,VIN_DCDC_DIG,VIN_DCDC_ DIG,VIN_DCDC_ DIG,,,,,,,,,,,,,,,,
+45,GPIO31,DCDC_ANA2_SW_P,GPIO31,,UART1_RX,,,,McAXR0,GSPI_CLK,,UART0_RX,,,McAFSX,,,,
+46,DCDC_ANA2_SW_N,DCDC_ANA2_SW_N,DCDC_ANA2_SW_N,,,,,,,,,,,,,,,,
+47,VDD_ANA2,VDD_ANA2,VDD_ANA2,,,,,,,,,,,,,,,,
+48,VDD_ANA1,VDD_ANA1,VDD_ANA1,,,,,,,,,,,,,,,,
+49,VDD_RAM,VDD_RAM,VDD_RAM,,,,,,,,,,,,,,,,
+50,GPIO0,GPIO0,GPIO0,,,UART0_RTS,McAXR0,,McAXR1,GT_CCP00,,GSPI_CS,UART1_RTS,,UART0_CTS,,,,
+51,RTC_XTAL_P,RTC_XTAL_P,RTC_XTAL_P,,,,,,,,,,,,,,,,
+52,RTC_XTAL_N,RTC_XTAL_N,GPIO32,,McACLK,,McAXR0,,UART0_RTS,,GSPI_MOSI,,,,,,,,
+53,GPIO30,GPIO30,GPIO30,,McACLK,McAFSX,GT_CCP05,,,GSPI_MISO,,UART0_TX,,,,,,,
+54,VIN_IO2,VIN_IO2,VIN_IO2,,,,,,,,,,,,,,,,
+55,GPIO1,GPIO1,GPIO1,,,GSPI_MISO,pCLK (PIXCLK),,UART1_TX,GT_CCP01,,,,,,,,,
+56,VDD_DIG2,VDD_DIG2,VDD_DIG2,,,,,,,,,,,,,,,,
+57,GPIO2,GPIO2,GPIO2,,,UART0_RX,,,UART1_RX,GT_CCP02,,,,,,,,,ADC_CH0
+58,GPIO3,GPIO3,GPIO3,,,,pDATA7(CAM_D3),,UART1_TX,,,,,,,,,,ADC_CH1
+59,GPIO4,GPIO4,GPIO4,,,,pDATA6(CAM_D2),,UART1_RX,,,,,,,,,,ADC_CH2
+60,GPIO5,GPIO5,GPIO5,,,,pDATA5(CAM_D1),,McAXR1,GT_CCP05,,,,,,,,,ADC_CH3
+61,GPIO6,GPIO6,GPIO6,,,UART1_CTS,pDATA4(CAM_D0),UART0_RTS,UART0_CTS,GT_CCP06,,,,,,,,,
+62,GPIO7,GPIO7,GPIO7,,,UART1_RTS,,,,,,,UART0_RTS,UART0_TX,,McACLKX,,,
+63,GPIO8,GPIO8,GPIO8,,,,,,SDCARD_IRQ,McAFSX,,,,,GT_CCP06,,,,
+64,GPIO9,GPIO9,GPIO9,,,GT_PWM05,,,SDCARD_DATA,McAXR0,,,,,GT_CCP00,,,,
+65,GND_TAB,GND_TAB,GND_TAB,,,,,,,,,,,,,,,,
diff --git a/cc3200/boards/cc3200_prefix.c b/cc3200/boards/cc3200_prefix.c
new file mode 100644
index 0000000000..1d0748c6a2
--- /dev/null
+++ b/cc3200/boards/cc3200_prefix.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// cc3200_prefix.c becomes the initial portion of the generated pins file.
+
+#include
+#include
+
+#include "mpconfig.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "inc/hw_types.h"
+#include "inc/hw_memmap.h"
+#include "pybgpio.h"
+
+
+#define GPIO(p_gpio_name, p_port, p_bit, p_pin_num) \
+{ \
+ { &gpio_type }, \
+ .name = MP_QSTR_ ## p_gpio_name, \
+ .port = PORT_A ## p_port, \
+ .bit = (p_bit), \
+ .pin_num = (p_pin_num) \
+}
diff --git a/cc3200/boards/make-pins.py b/cc3200/boards/make-pins.py
new file mode 100644
index 0000000000..ad0c9b7b8e
--- /dev/null
+++ b/cc3200/boards/make-pins.py
@@ -0,0 +1,182 @@
+#!/usr/bin/env python
+"""Creates the pin file for the CC3200."""
+
+from __future__ import print_function
+
+import argparse
+import sys
+import csv
+
+
+def parse_port_pin(name_str):
+ """Parses a string and returns a (port, gpio_bit) tuple."""
+ if len(name_str) < 5:
+ raise ValueError("Expecting pin name to be at least 5 characters")
+ if name_str[:4] != 'GPIO':
+ raise ValueError("Expecting pin name to start with GPIO")
+ if not name_str[4:].isdigit():
+ raise ValueError("Expecting numeric GPIO number")
+ port = int(int(name_str[4:]) / 8)
+ gpio_bit = 1 << int(int(name_str[4:]) % 8)
+ return (port, gpio_bit)
+
+
+class Pin(object):
+ """Holds the information associated with a pin."""
+ def __init__(self, name, port, gpio_bit, pin_num):
+ self.name = name
+ self.port = port
+ self.gpio_bit = gpio_bit
+ self.pin_num = pin_num
+ self.board_pin = False
+
+ def cpu_pin_name(self):
+ return self.name
+
+ def is_board_pin(self):
+ return self.board_pin
+
+ def set_is_board_pin(self):
+ self.board_pin = True
+
+ def print(self):
+ print('const gpio_obj_t pin_{:6s} = GPIO({:6s}, {:1d}, {:3d}, {:2d});'.format(
+ self.name, self.name, self.port, self.gpio_bit, self.pin_num))
+
+ def print_header(self, hdr_file):
+ hdr_file.write('extern const gpio_obj_t pin_{:s};\n'.
+ format(self.name))
+
+
+class Pins(object):
+
+ def __init__(self):
+ self.cpu_pins = [] # list of pin objects
+
+ def find_pin(self, port, gpio_bit):
+ for pin in self.cpu_pins:
+ if pin.port == port and pin.gpio_bit == gpio_bit:
+ return pin
+
+ def find_pin_by_num(self, pin_num):
+ for pin in self.cpu_pins:
+ if pin.pin_num == pin_num:
+ return pin
+
+ def parse_af_file(self, filename, pin_col, pinname_col):
+ with open(filename, 'r') as csvfile:
+ rows = csv.reader(csvfile)
+ for row in rows:
+ try:
+ (port_num, gpio_bit) = parse_port_pin(row[pinname_col])
+ except:
+ continue
+ if not row[pin_col].isdigit():
+ raise ValueError("Invalid pin number: {:s} in row {:s}".format(row[pin_col]), row)
+ # Pin numbers must start from 0 when used with the TI API
+ pin_num = int(row[pin_col]) - 1;
+ pin = Pin(row[pinname_col], port_num, gpio_bit, pin_num)
+ self.cpu_pins.append(pin)
+
+ def parse_board_file(self, filename, cpu_pin_num_col):
+ with open(filename, 'r') as csvfile:
+ rows = csv.reader(csvfile)
+ for row in rows:
+ # Pin numbers must start from 0 when used with the TI API
+ pin = self.find_pin_by_num(int(row[cpu_pin_num_col]) - 1)
+ if pin:
+ pin.set_is_board_pin()
+
+ def print_named(self, label, pins):
+ print('')
+ print('STATIC const mp_map_elem_t gpio_{:s}_pins_locals_dict_table[] = {{'.format(label))
+ for pin in pins:
+ if pin.is_board_pin():
+ print(' {{ MP_OBJ_NEW_QSTR(MP_QSTR_{:6s}), (mp_obj_t)&pin_{:6s} }},'.format(pin.cpu_pin_name(), pin.cpu_pin_name()))
+ print('};')
+ print('MP_DEFINE_CONST_DICT(gpio_{:s}_pins_locals_dict, gpio_{:s}_pins_locals_dict_table);'.format(label, label));
+
+ def print(self):
+ for pin in self.cpu_pins:
+ if pin.is_board_pin():
+ pin.print()
+ self.print_named('cpu', self.cpu_pins)
+ print('')
+
+ def print_header(self, hdr_filename):
+ with open(hdr_filename, 'wt') as hdr_file:
+ for pin in self.cpu_pins:
+ if pin.is_board_pin():
+ pin.print_header(hdr_file)
+
+ def print_qstr(self, qstr_filename):
+ with open(qstr_filename, 'wt') as qstr_file:
+ qstr_set = set([])
+ for pin in self.cpu_pins:
+ if pin.is_board_pin():
+ qstr_set |= set([pin.cpu_pin_name()])
+ for qstr in sorted(qstr_set):
+ print('Q({})'.format(qstr), file=qstr_file)
+
+
+def main():
+ parser = argparse.ArgumentParser(
+ prog="make-pins.py",
+ usage="%(prog)s [options] [command]",
+ description="Generate board specific pin file"
+ )
+ parser.add_argument(
+ "-a", "--af",
+ dest="af_filename",
+ help="Specifies the alternate function file for the chip",
+ default="cc3200_af.csv"
+ )
+ parser.add_argument(
+ "-b", "--board",
+ dest="board_filename",
+ help="Specifies the board file",
+ )
+ parser.add_argument(
+ "-p", "--prefix",
+ dest="prefix_filename",
+ help="Specifies beginning portion of generated pins file",
+ default="cc3200_prefix.c"
+ )
+ parser.add_argument(
+ "-q", "--qstr",
+ dest="qstr_filename",
+ help="Specifies name of generated qstr header file",
+ default="build/pins_qstr.h"
+ )
+ parser.add_argument(
+ "-r", "--hdr",
+ dest="hdr_filename",
+ help="Specifies name of generated pin header file",
+ default="build/pins.h"
+ )
+ args = parser.parse_args(sys.argv[1:])
+
+ pins = Pins()
+
+ print('// This file was automatically generated by make-pins.py')
+ print('//')
+ if args.af_filename:
+ print('// --af {:s}'.format(args.af_filename))
+ pins.parse_af_file(args.af_filename, 0, 1)
+
+ if args.board_filename:
+ print('// --board {:s}'.format(args.board_filename))
+ pins.parse_board_file(args.board_filename, 1)
+
+ if args.prefix_filename:
+ print('// --prefix {:s}'.format(args.prefix_filename))
+ print('')
+ with open(args.prefix_filename, 'r') as prefix_file:
+ print(prefix_file.read())
+ pins.print()
+ pins.print_qstr(args.qstr_filename)
+ pins.print_header(args.hdr_filename)
+
+
+if __name__ == "__main__":
+ main()
diff --git a/cc3200/bootmgr/bootgen.sh b/cc3200/bootmgr/bootgen.sh
new file mode 100644
index 0000000000..f90dc73155
--- /dev/null
+++ b/cc3200/bootmgr/bootgen.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+
+# Re-locator Path
+RELOCATOR=bootmgr/relocator
+
+# Boot Manager Path
+# First parameter passed is the board type
+BOOTMGR=bootmgr/build/$1
+
+# Check for re-locator binary
+if [ ! -f $RELOCATOR/relocator.bin ]; then
+
+ echo "Error : Relocator Not found!"
+ exit
+else
+ echo "Relocator found..."
+fi
+
+# Check for boot manager binary
+if [ ! -f $BOOTMGR/bootmgr.bin ]; then
+
+ echo "Error : Boot Manager Not found!"
+ exit
+else
+ echo "Boot Manager found..."
+fi
+
+# echo
+echo "Generating bootloader..."
+
+# Generate an all 0 bin file
+dd if=/dev/zero of=__tmp.bin ibs=1 count=256 conv=notrunc >/dev/null 2>&1
+
+# Generate 0 a padded version of relocator
+dd if=$RELOCATOR/relocator.bin of=__tmp.bin ibs=1 conv=notrunc >/dev/null 2>&1
+
+# Concatenate re-locator and boot-manager
+cat __tmp.bin $BOOTMGR/bootmgr.bin > $BOOTMGR/bootloader.bin
+
+# Remove the tmp files
+rm -f __tmp.bin
+
+# Remove bootmgr.bin
+rm -f $BOOTMGR/bootmgr.bin
diff --git a/cc3200/bootmgr/bootloader.mk b/cc3200/bootmgr/bootloader.mk
new file mode 100644
index 0000000000..757770f60c
--- /dev/null
+++ b/cc3200/bootmgr/bootloader.mk
@@ -0,0 +1,123 @@
+BUILD = bootmgr/build/$(BOARD)
+
+BOOT_INC = -Ibootmgr
+BOOT_INC += -Ibootmgr/sl
+BOOT_INC += -Ihal
+BOOT_INC += -Ihal/inc
+BOOT_INC += -Isimplelink
+BOOT_INC += -Isimplelink/include
+BOOT_INC += -Isimplelink/oslib
+BOOT_INC += -Iutil
+BOOT_INC += -I..
+BOOT_INC += -I.
+BOOT_INC += -I$(PY_SRC)
+BOOT_INC += -I$(BUILD)
+
+BOOT_CPPDEFINES = -Dgcc -DBOOTLOADER -DTARGET_IS_CC3200 -DSL_TINY
+
+BOOT_HAL_SRC_C = $(addprefix hal/,\
+ cpu.c \
+ interrupt.c \
+ prcm.c \
+ shamd5.c \
+ spi.c \
+ startup_gcc.c \
+ systick.c \
+ utils.c \
+ )
+
+BOOT_SL_SRC_C = $(addprefix simplelink/,\
+ source/device.c \
+ source/driver.c \
+ source/flowcont.c \
+ source/fs.c \
+ source/netapp.c \
+ source/netcfg.c \
+ source/nonos.c \
+ source/socket.c \
+ source/spawn.c \
+ source/wlan.c \
+ cc_pal.c \
+ )
+
+BOOT_UTIL_SRC_C = $(addprefix util/,\
+ hash.c \
+ )
+
+BOOT_MAIN_SRC_C = \
+ bootmgr/main.c
+
+BOOT_MAIN_SRC_S = \
+ bootmgr/runapp.s
+
+BOOT_PY_SRC_C = $(addprefix py/,\
+ pfenv.c \
+ pfenv_printf.c \
+ )
+
+BOOT_STM_SRC_C = $(addprefix stmhal/,\
+ printf.c \
+ string0.c \
+ )
+
+OBJ = $(addprefix $(BUILD)/, $(BOOT_HAL_SRC_C:.c=.o) $(BOOT_SL_SRC_C:.c=.o) $(BOOT_UTIL_SRC_C:.c=.o) $(BOOT_MAIN_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(BOOT_MAIN_SRC_S:.s=.o) $(BOOT_PY_SRC_C:.c=.o) $(BOOT_STM_SRC_C:.c=.o))
+
+# Add the linker script
+LINKER_SCRIPT = bootmgr/bootmgr.lds
+LDFLAGS += -T $(LINKER_SCRIPT)
+
+# Add the bootloader specific CFLAGS
+CFLAGS += $(BOOT_CPPDEFINES) $(BOOT_INC)
+
+# Optimize for size all sources except for main
+
+
+# Disable strict aliasing for the simplelink driver
+$(BUILD)/simplelink/source/driver.o: CFLAGS += -fno-strict-aliasing
+
+# Check if we would like to debug the port code
+ifeq ($(BTYPE), release)
+# Optimize everything and define the NDEBUG flag
+CFLAGS += -Os -DNDEBUG
+else
+ifeq ($(BTYPE), debug)
+# Define the DEBUG flag
+CFLAGS += -DDEBUG=DEBUG
+# Optimize the stable sources only
+$(BUILD)/hal/%.o: CFLAGS += -Os
+$(BUILD)/simplelink/%.o: CFLAGS += -Os
+$(BUILD)/py/%.o: CFLAGS += -Os
+$(BUILD)/stmhal/%.o: CFLAGS += -Os
+else
+$(error Invalid BTYPE specified)
+endif
+endif
+
+SHELL = bash
+BOOT_GEN = bootmgr/bootgen.sh
+HEADER_BUILD = $(BUILD)/genhdr
+
+all: $(BUILD)/bootloader.bin
+
+$(BUILD)/bootmgr.axf: $(OBJ) $(LINKER_SCRIPT)
+ $(ECHO) "LINK $@"
+ $(Q)$(CC) -o $@ $(LDFLAGS) $(OBJ) $(LIBS)
+ $(Q)$(SIZE) $@
+
+$(BUILD)/bootmgr.bin: $(BUILD)/bootmgr.axf
+ $(ECHO) "Create $@"
+ $(Q)$(OBJCOPY) -O binary $< $@
+
+$(BUILD)/bootloader.bin: $(BUILD)/bootmgr.bin
+ $(ECHO) "Create $@"
+ $(Q)$(SHELL) $(BOOT_GEN) $(BOARD)
+
+# Create an empty "qstrdefs.generated.h" needed by py/mkrules.mk
+$(HEADER_BUILD)/qstrdefs.generated.h: | $(HEADER_BUILD)
+ touch $@
+
+# Create an empty "py-version.h" needed by py/mkrules.mk
+$(HEADER_BUILD)/py-version.h: | $(HEADER_BUILD)
+ touch $@
+
\ No newline at end of file
diff --git a/cc3200/bootmgr/bootmgr.h b/cc3200/bootmgr/bootmgr.h
new file mode 100644
index 0000000000..fa1d7c3619
--- /dev/null
+++ b/cc3200/bootmgr/bootmgr.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __BOOTMGR_H__
+#define __BOOTMGR_H__
+
+//****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+// User image tokens
+//*****************************************************************************
+#define FACTORY_IMG_TOKEN 0x5555AAAA
+#define UPDATE_IMG_TOKEN 0xAA5555AA
+#define USER_BOOT_INFO_TOKEN 0xA5A55A5A
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define APP_IMG_SRAM_OFFSET 0x20004000
+#define DEVICE_IS_CC3101RS 0x18
+#define DEVICE_IS_CC3101S 0x1B
+
+//*****************************************************************************
+// Function prototype
+//*****************************************************************************
+extern void Run(unsigned long);
+
+//****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__BOOTMGR_H__
diff --git a/cc3200/bootmgr/bootmgr.lds b/cc3200/bootmgr/bootmgr.lds
new file mode 100644
index 0000000000..456f424905
--- /dev/null
+++ b/cc3200/bootmgr/bootmgr.lds
@@ -0,0 +1,95 @@
+/*****************************************************************************
+* bootmgr.lds
+*
+* GCC Linker script for get_time application.
+*
+* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+__stack_size__ = 1024;
+
+MEMORY
+{
+ SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000
+}
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+ .text :
+ {
+ _text = .;
+ KEEP(*(.intvecs))
+ *(.text*)
+ *(.rodata*)
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(8);
+ } > SRAM
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ _etext = .;
+ } > SRAM
+
+ __init_data = .;
+
+ .data : AT(__init_data)
+ {
+ _data = .;
+ *(.data*)
+ . = ALIGN (8);
+ _edata = .;
+ } > SRAM
+
+ .bss :
+ {
+ _bss = .;
+ *(.bss*)
+ *(COMMON)
+ _ebss = .;
+ } > SRAM
+
+ .stack ORIGIN(SRAM) + LENGTH(SRAM) - __stack_size__ :
+ {
+ . = ALIGN(8);
+ _stack = .;
+ . = . + __stack_size__;
+ . = ALIGN(8);
+ _estack = .;
+ } > SRAM
+}
+
diff --git a/cc3200/bootmgr/flc.h b/cc3200/bootmgr/flc.h
new file mode 100644
index 0000000000..7023bc68c8
--- /dev/null
+++ b/cc3200/bootmgr/flc.h
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __FLC_H__
+#define __FLC_H__
+
+/******************************************************************************
+
+ If building with a C++ compiler, make all of the definitions in this header
+ have a C binding.
+
+*******************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/******************************************************************************
+ Image file names
+*******************************************************************************/
+#define IMG_BOOT_INFO "/sys/bootinfo.bin"
+#define IMG_FACTORY "/sys/factimg.bin"
+#define IMG_UPDATE "/sys/updtimg.bin"
+
+#define IMG_SRVPACK "/sys/servicepack.ucf"
+#define SRVPACK_SIGN "/sys/servicepack.sig"
+
+/******************************************************************************
+ Image file sizes
+*******************************************************************************/
+#define IMG_SIZE (232 * 1024) /* 16KB are reserved for the bootloader and at least 8KB for the heap*/
+#define SRVPACK_SIZE (16 * 1024)
+#define SIGN_SIZE (2 * 1024)
+
+/******************************************************************************
+ Active Image
+*******************************************************************************/
+#define IMG_ACT_FACTORY 0
+#define IMG_ACT_UPDATE 1
+
+#define IMG_STATUS_CHECK 0
+#define IMG_STATUS_READY 1
+
+/******************************************************************************
+ Boot Info structure
+*******************************************************************************/
+typedef struct sBootInfo
+{
+ _u8 ActiveImg;
+ _u8 Status;
+ _u8 : 8;
+ _u8 : 8;
+}sBootInfo_t;
+
+
+/******************************************************************************
+
+ Mark the end of the C bindings section for C++ compilers.
+
+*******************************************************************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __FLC_H__ */
diff --git a/cc3200/bootmgr/main.c b/cc3200/bootmgr/main.c
new file mode 100644
index 0000000000..ee8a32d347
--- /dev/null
+++ b/cc3200/bootmgr/main.c
@@ -0,0 +1,355 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include
+#include "hw_ints.h"
+#include "hw_types.h"
+#include "hw_gpio.h"
+#include "hw_memmap.h"
+#include "hw_gprcm.h"
+#include "hw_common_reg.h"
+#include "pin.h"
+#include "gpio.h"
+#include "rom.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "simplelink.h"
+#include "interrupt.h"
+#include "gpio.h"
+#include "flc.h"
+#include "bootmgr.h"
+#include "shamd5.h"
+#include "hash.h"
+#include "utils.h"
+#include "cc3200_hal.h"
+
+
+//*****************************************************************************
+// Local Constants
+//*****************************************************************************
+#define SL_STOP_TIMEOUT 500
+#define BOOTMGR_HASH_ALGO SHAMD5_ALGO_MD5
+#define BOOTMGR_HASH_SIZE 32
+#define BOOTMGR_BUFF_SIZE 512
+
+#define BOOTMGR_WAIT_SAFE_MODE_MS 2000
+#define BOOTMGR_WAIT_SAFE_MODE_TOOGLE_MS 250
+
+#define BOOTMGR_SAFE_MODE_ENTER_MS 1000
+#define BOOTMGR_SAFE_MODE_ENTER_TOOGLE_MS 100
+
+#define BOOTMGR_PINS_PRCM PRCM_GPIOA3
+#define BOOTMGR_PINS_PORT GPIOA3_BASE
+#define BOOTMGR_LED_PIN_NUM PIN_21
+#define BOOTMGR_SFE_PIN_NUM PIN_45
+#define BOOTMGR_LED_PORT_PIN GPIO_PIN_1 // GPIO25
+#define BOOTMGR_SFE_PORT_PIN GPIO_PIN_7 // GPIO31
+
+
+//*****************************************************************************
+// Exported functions declarations
+//*****************************************************************************
+extern void bootmgr_run_app (_u32 base);
+
+//*****************************************************************************
+// Local functions declarations
+//*****************************************************************************
+static void bootmgr_board_init (void);
+static bool bootmgr_verify (void);
+static void bootmgr_load_and_execute (_u8 *image);
+static bool safe_mode_boot (void);
+static void bootmgr_image_loader (sBootInfo_t *psBootInfo);
+
+//*****************************************************************************
+// Private data
+//*****************************************************************************
+static _u8 bootmgr_file_buf[BOOTMGR_BUFF_SIZE];
+static _u8 bootmgr_hash_buf[BOOTMGR_HASH_SIZE + 1];
+
+//*****************************************************************************
+// Vector Table
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+
+//*****************************************************************************
+// WLAN Event handler callback hookup function
+//*****************************************************************************
+void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent)
+{
+
+}
+
+//*****************************************************************************
+// HTTP Server callback hookup function
+//*****************************************************************************
+void SimpleLinkHttpServerCallback(SlHttpServerEvent_t *pHttpEvent,
+ SlHttpServerResponse_t *pHttpResponse)
+{
+
+}
+
+//*****************************************************************************
+// Net APP Event callback hookup function
+//*****************************************************************************
+void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent)
+{
+
+}
+
+//*****************************************************************************
+// General Event callback hookup function
+//*****************************************************************************
+void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent)
+{
+
+}
+
+//*****************************************************************************
+// Socket Event callback hookup function
+//*****************************************************************************
+void SimpleLinkSockEventHandler(SlSockEvent_t *pSock)
+{
+
+}
+
+//*****************************************************************************
+//! Board Initialization & Configuration
+//*****************************************************************************
+static void bootmgr_board_init(void) {
+ // Set vector table base
+ MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]);
+
+ // Enable Processor Interrupts
+ MAP_IntMasterEnable();
+ MAP_IntEnable(FAULT_SYSTICK);
+
+ // Mandatory MCU Initialization
+ PRCMCC3200MCUInit();
+
+ // Enable the Data Hashing Engine
+ HASH_Init();
+
+ // Enable GPIOA3 Peripheral Clock
+ MAP_PRCMPeripheralClkEnable(BOOTMGR_PINS_PRCM, PRCM_RUN_MODE_CLK);
+
+ // Configure the bld
+ MAP_PinTypeGPIO(BOOTMGR_LED_PIN_NUM, PIN_MODE_0, false);
+ MAP_PinConfigSet(BOOTMGR_LED_PIN_NUM, PIN_STRENGTH_6MA, PIN_TYPE_STD);
+ MAP_GPIODirModeSet(BOOTMGR_PINS_PORT, BOOTMGR_LED_PORT_PIN, GPIO_DIR_MODE_OUT);
+
+ // Configure the safe mode pin
+ MAP_PinTypeGPIO(BOOTMGR_SFE_PIN_NUM, PIN_MODE_0, false);
+ MAP_PinConfigSet(BOOTMGR_SFE_PIN_NUM, PIN_STRENGTH_6MA, PIN_TYPE_STD_PU);
+ MAP_GPIODirModeSet(BOOTMGR_PINS_PORT, BOOTMGR_SFE_PORT_PIN, GPIO_DIR_MODE_IN);
+}
+
+//*****************************************************************************
+//! Verifies the integrity of the new application binary
+//*****************************************************************************
+static bool bootmgr_verify (void) {
+ SlFsFileInfo_t FsFileInfo;
+ _u32 reqlen, offset = 0;
+ _i32 fHandle;
+
+ // open the file for reading
+ if (0 == sl_FsOpen((_u8 *)IMG_UPDATE, FS_MODE_OPEN_READ, NULL, &fHandle)) {
+ // get the file size
+ sl_FsGetInfo((_u8 *)IMG_UPDATE, 0, &FsFileInfo);
+
+ if (FsFileInfo.FileLen > BOOTMGR_HASH_SIZE) {
+ FsFileInfo.FileLen -= BOOTMGR_HASH_SIZE;
+ HASH_SHAMD5Start(BOOTMGR_HASH_ALGO, FsFileInfo.FileLen);
+ do {
+ if ((FsFileInfo.FileLen - offset) > BOOTMGR_BUFF_SIZE) {
+ reqlen = BOOTMGR_BUFF_SIZE;
+ }
+ else {
+ reqlen = FsFileInfo.FileLen - offset;
+ }
+
+ offset += sl_FsRead(fHandle, offset, bootmgr_file_buf, reqlen);
+ HASH_SHAMD5Update(bootmgr_file_buf, reqlen);
+ } while (offset < FsFileInfo.FileLen);
+
+ HASH_SHAMD5Read (bootmgr_file_buf);
+
+ // convert the resulting hash to hex
+ for (_u32 i = 0; i < (BOOTMGR_HASH_SIZE / 2); i++) {
+ snprintf ((char *)&bootmgr_hash_buf[(i * 2)], 3, "%02x", bootmgr_file_buf[i]);
+ }
+
+ // read the hash from the file and close it
+ ASSERT (BOOTMGR_HASH_SIZE == sl_FsRead(fHandle, offset, bootmgr_file_buf, BOOTMGR_HASH_SIZE));
+ sl_FsClose (fHandle, NULL, NULL, 0);
+ bootmgr_file_buf[BOOTMGR_HASH_SIZE] = '\0';
+ // compare both hashes
+ if (!strcmp((const char *)bootmgr_hash_buf, (const char *)bootmgr_file_buf)) {
+ // it's a match
+ return true;
+ }
+ }
+ // close the file
+ sl_FsClose(fHandle, NULL, NULL, 0);
+ }
+ return false;
+}
+
+//*****************************************************************************
+//! Loads the application from sFlash and executes
+//*****************************************************************************
+static void bootmgr_load_and_execute (_u8 *image) {
+ SlFsFileInfo_t pFsFileInfo;
+ _i32 fhandle;
+ // open the application binary
+ if (!sl_FsOpen(image, FS_MODE_OPEN_READ, NULL, &fhandle)) {
+ // get the file size
+ if (!sl_FsGetInfo(image, 0, &pFsFileInfo)) {
+ // read the application into SRAM
+ if (pFsFileInfo.FileLen == sl_FsRead(fhandle, 0, (unsigned char *)APP_IMG_SRAM_OFFSET, pFsFileInfo.FileLen)) {
+ // close the file
+ sl_FsClose(fhandle, 0, 0, 0);
+ // stop the network services
+ sl_Stop(SL_STOP_TIMEOUT);
+ // execute the application
+ bootmgr_run_app(APP_IMG_SRAM_OFFSET);
+ }
+ }
+ }
+}
+
+//*****************************************************************************
+//! Check for the safe mode pin
+//*****************************************************************************
+static bool safe_mode_boot (void) {
+ _u32 count = 0;
+ while (!MAP_GPIOPinRead(BOOTMGR_PINS_PORT, BOOTMGR_SFE_PORT_PIN) &&
+ ((BOOTMGR_WAIT_SAFE_MODE_TOOGLE_MS * count++) < BOOTMGR_WAIT_SAFE_MODE_MS)) {
+ // toogle the led
+ MAP_GPIOPinWrite(BOOTMGR_PINS_PORT, BOOTMGR_LED_PORT_PIN, ~MAP_GPIOPinRead(GPIOA3_BASE, BOOTMGR_LED_PORT_PIN));
+ UtilsDelay(UTILS_DELAY_US_TO_COUNT(BOOTMGR_WAIT_SAFE_MODE_TOOGLE_MS * 1000));
+ }
+ return MAP_GPIOPinRead(BOOTMGR_PINS_PORT, BOOTMGR_SFE_PORT_PIN) ? false : true;
+}
+
+//*****************************************************************************
+//! Load the proper image based on information from boot info and executes it.
+//*****************************************************************************
+static void bootmgr_image_loader(sBootInfo_t *psBootInfo) {
+ _i32 fhandle;
+ if (safe_mode_boot()) {
+ _u32 count = 0;
+ while ((BOOTMGR_SAFE_MODE_ENTER_TOOGLE_MS * count++) > BOOTMGR_SAFE_MODE_ENTER_MS) {
+ // toogle the led
+ MAP_GPIOPinWrite(BOOTMGR_PINS_PORT, BOOTMGR_LED_PORT_PIN, ~MAP_GPIOPinRead(GPIOA3_BASE, BOOTMGR_LED_PORT_PIN));
+ UtilsDelay(UTILS_DELAY_US_TO_COUNT(BOOTMGR_SAFE_MODE_ENTER_TOOGLE_MS * 1000));
+ }
+ psBootInfo->ActiveImg = IMG_ACT_FACTORY;
+ // turn the led off
+ MAP_GPIOPinWrite(BOOTMGR_PINS_PORT, BOOTMGR_LED_PORT_PIN, 0);
+ }
+ // do we have a new update image that needs to be verified?
+ else if ((psBootInfo->ActiveImg == IMG_ACT_UPDATE) && (psBootInfo->Status == IMG_STATUS_CHECK)) {
+ if (!bootmgr_verify()) {
+ // delete the corrupted file
+ sl_FsDel((_u8 *)IMG_UPDATE, 0);
+ // switch to the factory image
+ psBootInfo->ActiveImg = IMG_ACT_FACTORY;
+ }
+ // in any case, set the status as "READY"
+ psBootInfo->Status = IMG_STATUS_READY;
+ // write the new boot info
+ if (!sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_WRITE, NULL, &fhandle)) {
+ sl_FsWrite(fhandle, 0, (unsigned char *)psBootInfo, sizeof(sBootInfo_t));
+ // close the file
+ sl_FsClose(fhandle, 0, 0, 0);
+ }
+ }
+
+ // now boot the active image
+ if (IMG_ACT_UPDATE == psBootInfo->ActiveImg) {
+ bootmgr_load_and_execute((unsigned char *)IMG_UPDATE);
+ }
+ else {
+ bootmgr_load_and_execute((unsigned char *)IMG_FACTORY);
+ }
+}
+
+//*****************************************************************************
+//! Main function
+//*****************************************************************************
+int main (void) {
+ sBootInfo_t sBootInfo = { .ActiveImg = IMG_ACT_FACTORY, .Status = IMG_STATUS_READY };
+ bool bootapp = false;
+ _i32 fhandle;
+
+ // Board Initialization
+ bootmgr_board_init();
+
+ // start simplelink since we need it to access the sflash
+ sl_Start(NULL, NULL, NULL);
+
+ // if a boot info file is found, load it, else, create a new one with the default boot info
+ if (!sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_READ, NULL, &fhandle)) {
+ if (sizeof(sBootInfo_t) == sl_FsRead(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t))) {
+ bootapp = true;
+ }
+ sl_FsClose(fhandle, 0, 0, 0);
+ }
+ if (!bootapp) {
+ // create a new boot info file
+ _u32 BootInfoCreateFlag = _FS_FILE_OPEN_FLAG_COMMIT | _FS_FILE_PUBLIC_WRITE | _FS_FILE_PUBLIC_READ;
+ if (!sl_FsOpen ((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_CREATE((2 * sizeof(sBootInfo_t)),
+ BootInfoCreateFlag), NULL, &fhandle)) {
+ // Write the default boot info.
+ if (sizeof(sBootInfo_t) == sl_FsWrite(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t))) {
+ bootapp = true;
+ }
+ sl_FsClose(fhandle, 0, 0, 0);
+ }
+ }
+
+ if (bootapp) {
+ // load and execute the image based on the boot info
+ bootmgr_image_loader(&sBootInfo);
+ }
+
+ // stop simplelink
+ sl_Stop(SL_STOP_TIMEOUT);
+
+ // if we've reached this point, then it means a fatal error occurred and the application
+ // could not be loaded, so, loop forever and signal the crash to the user
+ while (true) {
+ // keep the bld on
+ MAP_GPIOPinWrite(BOOTMGR_PINS_PORT, BOOTMGR_LED_PORT_PIN, BOOTMGR_LED_PORT_PIN);
+ __asm volatile(" dsb \n"
+ " isb \n"
+ " wfi \n");
+ }
+}
+
diff --git a/cc3200/bootmgr/runapp.s b/cc3200/bootmgr/runapp.s
new file mode 100644
index 0000000000..45c6dcb195
--- /dev/null
+++ b/cc3200/bootmgr/runapp.s
@@ -0,0 +1,19 @@
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+ .text
+ .align 2
+
+@ void bootmgr_run_app(_u32 base)
+ .global bootmgr_run_app
+ .thumb
+ .thumb_func
+ .type bootmgr_run_app, %function
+bootmgr_run_app:
+ @ set the SP
+ ldr sp, [r0]
+ add r0, r0, #4
+
+ @ jump to the entry code
+ ldr r1, [r0]
+ bx r1
diff --git a/cc3200/bootmgr/sl/user.h b/cc3200/bootmgr/sl/user.h
new file mode 100644
index 0000000000..8ef7677fe5
--- /dev/null
+++ b/cc3200/bootmgr/sl/user.h
@@ -0,0 +1,1059 @@
+/*
+ * user.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+#ifndef __USER_H__
+#define __USER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup porting_user_include Porting - User Include Files
+
+ This section IS NOT REQUIRED in case user provided primitives are handled
+ in makefiles or project configurations (IDE)
+
+ PORTING ACTION:
+ - Include all required header files for the definition of:
+ -# Transport layer library API (e.g. SPI, UART)
+ -# OS primitives definitions (e.g. Task spawn, Semaphores)
+ -# Memory management primitives (e.g. alloc, free)
+
+ ******************************************************************************
+ */
+
+#include
+#include "cc_pal.h"
+
+/*!
+ \def MAX_CONCURRENT_ACTIONS
+
+ \brief Defines the maximum number of concurrent action in the system
+ Min:1 , Max: 32
+
+ Actions which has async events as return, can be
+
+ \sa
+
+ \note In case there are not enough resources for the actions needed in the system,
+ error is received: POOL_IS_EMPTY
+ one option is to increase MAX_CONCURRENT_ACTIONS
+ (improves performance but results in memory consumption)
+ Other option is to call the API later (decrease performance)
+
+ \warning In case of setting to one, recommend to use non-blocking recv\recvfrom to allow
+ multiple socket recv
+*/
+#define MAX_CONCURRENT_ACTIONS 10
+/*!
+ \def CPU_FREQ_IN_MHZ
+ \brief Defines CPU frequency for Host side, for better accuracy of busy loops, if any
+ \sa
+ \note
+
+ \warning If not set the default CPU frequency is set to 200MHz
+ This option will be deprecated in future release
+*/
+
+#define CPU_FREQ_IN_MHZ 80
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup porting_capabilities Porting - Capabilities Set
+
+ This section IS NOT REQUIRED in case one of the following pre defined
+ capabilities set is in use:
+ - SL_TINY
+ - SL_SMALL
+ - SL_FULL
+
+ PORTING ACTION:
+ - Define one of the pre-defined capabilities set or uncomment the
+ relevant definitions below to select the required capabilities
+
+ @{
+
+ *******************************************************************************
+*/
+
+/*!
+ \def SL_INC_ARG_CHECK
+
+ \brief Defines whether the SimpleLink driver perform argument check
+ or not
+
+ When defined, the SimpleLink driver perform argument check on
+ function call. Removing this define could reduce some code
+ size and improve slightly the performances but may impact in
+ unpredictable behavior in case of invalid arguments
+
+ \sa
+
+ \note belongs to \ref proting_sec
+
+ \warning Removing argument check may cause unpredictable behavior in
+ case of invalid arguments.
+ In this case the user is responsible to argument validity
+ (for example all handlers must not be NULL)
+*/
+#define SL_INC_ARG_CHECK
+
+
+/*!
+ \def SL_INC_STD_BSD_API_NAMING
+
+ \brief Defines whether SimpleLink driver should expose standard BSD
+ APIs or not
+
+ When defined, the SimpleLink driver in addtion to its alternative
+ BSD APIs expose also standard BSD APIs.
+ Stadrad BSD API includs the following functions:
+ socket , close , accept , bind , listen , connect , select ,
+ setsockopt , getsockopt , recv , recvfrom , write , send , sendto ,
+ gethostbyname
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_STD_BSD_API_NAMING
+
+
+/*!
+ \brief Defines whether to include extended API in SimpleLink driver
+ or not
+
+ When defined, the SimpleLink driver will include also all
+ exteded API of the included packages
+
+ \sa ext_api
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_EXT_API
+
+/*!
+ \brief Defines whether to include WLAN package in SimpleLink driver
+ or not
+
+ When defined, the SimpleLink driver will include also
+ the WLAN package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_WLAN_PKG
+
+/*!
+ \brief Defines whether to include SOCKET package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also
+ the SOCKET package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCKET_PKG
+
+/*!
+ \brief Defines whether to include NET_APP package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also the
+ NET_APP package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_NET_APP_PKG
+
+/*!
+ \brief Defines whether to include NET_CFG package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also
+ the NET_CFG package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_NET_CFG_PKG
+
+/*!
+ \brief Defines whether to include NVMEM package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also the
+ NVMEM package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_NVMEM_PKG
+
+/*!
+ \brief Defines whether to include socket server side APIs
+ in SimpleLink driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ server side APIs
+
+ \sa server_side
+
+ \note
+
+ \warning
+*/
+#define SL_INC_SOCK_SERVER_SIDE_API
+
+/*!
+ \brief Defines whether to include socket client side APIs in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ client side APIs
+
+ \sa client_side
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCK_CLIENT_SIDE_API
+
+/*!
+ \brief Defines whether to include socket receive APIs in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ receive side APIs
+
+ \sa recv_api
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCK_RECV_API
+
+/*!
+ \brief Defines whether to include socket send APIs in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ send side APIs
+
+ \sa send_api
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCK_SEND_API
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup ported_enable_device Ported on CC32XX - Device Enable/Disable
+
+ The enable/disable API provide mechanism to enable/disable the network processor
+
+
+ PORTING ACTION:
+ - None
+ @{
+
+ ******************************************************************************
+ */
+
+/*!
+ \brief Preamble to the enabling the Network Processor.
+ Placeholder to implement any pre-process operations
+ before enabling networking operations.
+
+ \sa sl_DeviceEnable
+
+ \note belongs to \ref ported_sec
+
+*/
+#define sl_DeviceEnablePreamble() NwpPowerOnPreamble()
+
+/*!
+ \brief Enable the Network Processor
+
+ \sa sl_DeviceDisable
+
+ \note belongs to \ref ported_sec
+
+*/
+#define sl_DeviceEnable() NwpPowerOn()
+
+/*!
+ \brief Disable the Network Processor
+
+ \sa sl_DeviceEnable
+
+ \note belongs to \ref ported_sec
+*/
+#define sl_DeviceDisable() NwpPowerOff()
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+/*!
+ ******************************************************************************
+
+ \defgroup ported_interface Ported on CC32XX - Communication Interface
+
+ The simple link device can work with different communication
+ channels (e.g. spi/uart). Texas Instruments provides single driver
+ that can work with all these types. This section bind between the
+ physical communication interface channel and the SimpleLink driver
+
+
+ \note Correct and efficient implementation of this driver is critical
+ for the performances of the SimpleLink device on this platform.
+
+
+ PORTING ACTION:
+ - None
+
+ @{
+
+ ******************************************************************************
+*/
+
+#define _SlFd_t Fd_t
+
+/*!
+ \brief Opens an interface communication port to be used for communicating
+ with a SimpleLink device
+
+ Given an interface name and option flags, this function opens
+ the communication port and creates a file descriptor.
+ This file descriptor is used afterwards to read and write
+ data from and to this specific communication channel.
+ The speed, clock polarity, clock phase, chip select and all other
+ specific attributes of the channel are all should be set to hardcoded
+ in this function.
+
+ \param ifName - points to the interface name/path. The interface name is an
+ optional attributes that the simple link driver receives
+ on opening the driver (sl_Start).
+ In systems that the spi channel is not implemented as
+ part of the os device drivers, this parameter could be NULL.
+
+ \param flags - optional flags parameters for future use
+
+ \return upon successful completion, the function shall open the channel
+ and return a non-negative integer representing the file descriptor.
+ Otherwise, -1 shall be returned
+
+ \sa sl_IfClose , sl_IfRead , sl_IfWrite
+
+ \note The prototype of the function is as follow:
+ Fd_t xxx_IfOpen(char* pIfName , unsigned long flags);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfOpen spi_Open
+
+/*!
+ \brief Closes an opened interface communication port
+
+ \param fd - file descriptor of opened communication channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa sl_IfOpen , sl_IfRead , sl_IfWrite
+
+ \note The prototype of the function is as follow:
+ int xxx_IfClose(Fd_t Fd);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfClose spi_Close
+
+/*!
+ \brief Attempts to read up to len bytes from an opened communication channel
+ into a buffer starting at pBuff.
+
+ \param fd - file descriptor of an opened communication channel
+
+ \param pBuff - pointer to the first location of a buffer that contains enough
+ space for all expected data
+
+ \param len - number of bytes to read from the communication channel
+
+ \return upon successful completion, the function shall return the number of read bytes.
+ Otherwise, 0 shall be returned
+
+ \sa sl_IfClose , sl_IfOpen , sl_IfWrite
+
+
+ \note The prototype of the function is as follow:
+ int xxx_IfRead(Fd_t Fd , char* pBuff , int Len);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfRead spi_Read
+
+/*!
+ \brief attempts to write up to len bytes to the SPI channel
+
+ \param fd - file descriptor of an opened communication channel
+
+ \param pBuff - pointer to the first location of a buffer that contains
+ the data to send over the communication channel
+
+ \param len - number of bytes to write to the communication channel
+
+ \return upon successful completion, the function shall return the number of sent bytes.
+ therwise, 0 shall be returned
+
+ \sa sl_IfClose , sl_IfOpen , sl_IfRead
+
+ \note This function could be implemented as zero copy and return only upon successful completion
+ of writing the whole buffer, but in cases that memory allocation is not too tight, the
+ function could copy the data to internal buffer, return back and complete the write in
+ parallel to other activities as long as the other SPI activities would be blocked until
+ the entire buffer write would be completed
+
+ The prototype of the function is as follow:
+ int xxx_IfWrite(Fd_t Fd , char* pBuff , int Len);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfWrite spi_Write
+
+/*!
+ \brief register an interrupt handler routine for the host IRQ
+
+ \param InterruptHdl - pointer to interrupt handler routine
+
+ \param pValue - pointer to a memory structure that is passed
+ to the interrupt handler.
+
+ \return upon successful registration, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa
+
+ \note If there is already registered interrupt handler, the function
+ should overwrite the old handler with the new one
+
+ \note If the handler is a null pointer, the function should un-register the
+ interrupt handler, and the interrupts can be disabled.
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfRegIntHdlr(InterruptHdl , pValue) NwpRegisterInterruptHandler(InterruptHdl , pValue)
+
+/*!
+ \brief Masks the Host IRQ
+
+ \sa sl_IfUnMaskIntHdlr
+
+
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+
+
+#define sl_IfMaskIntHdlr() NwpMaskInterrupt()
+
+/*!
+ \brief Unmasks the Host IRQ
+
+ \sa sl_IfMaskIntHdlr
+
+
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+
+#define sl_IfUnMaskIntHdlr() NwpUnMaskInterrupt()
+
+/*!
+ \brief Write Handers for statistics debug on write
+
+ \param interface handler - pointer to interrupt handler routine
+
+
+ \return no return value
+
+ \sa
+
+ \note An optional hooks for monitoring before and after write info
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+/* #define SL_START_WRITE_STAT */
+
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+*/
+
+/*!
+ ******************************************************************************
+
+ \defgroup ported_os Ported on CC32XX - Operating System
+
+ The simple link driver can run on multi-threaded environment as well
+ as non-os environment (mail loop)
+
+ This section IS NOT REQUIRED in case you are working on non-os environment.
+
+ If you choose to work in multi-threaded environment under any operating system
+ you will have to provide some basic adaptation routines to allow the driver
+ to protect access to resources from different threads (locking object) and
+ to allow synchronization between threads (sync objects).
+
+ PORTING ACTION:
+ -# Uncomment SL_PLATFORM_MULTI_THREADED define
+ -# Bind locking object routines
+ -# Bind synchronization object routines
+ -# Optional - Bind spawn thread routine
+
+ @{
+
+ ******************************************************************************
+*/
+
+/*
+#define SL_PLATFORM_MULTI_THREADED
+*/
+
+#ifdef SL_PLATFORM_MULTI_THREADED
+#include "osi.h"
+
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define SL_OS_RET_CODE_OK ((int)OSI_OK)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define SL_OS_WAIT_FOREVER ((OsiTime_t)OSI_WAIT_FOREVER)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define SL_OS_NO_WAIT ((OsiTime_t)OSI_NO_WAIT)
+
+/*!
+ \brief type definition for a time value
+
+ \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc.
+
+ \note belongs to \ref ported_sec
+*/
+#define _SlTime_t OsiTime_t
+
+/*!
+ \brief type definition for a sync object container
+
+ Sync object is object used to synchronize between two threads or thread and interrupt handler.
+ One thread is waiting on the object and the other thread send a signal, which then
+ release the waiting thread.
+ The signal must be able to be sent from interrupt context.
+ This object is generally implemented by binary semaphore or events.
+
+ \note On each porting or platform the type could be whatever is needed - integer, structure etc.
+
+ \note belongs to \ref ported_sec
+*/
+typedef OsiSyncObj_t _SlSyncObj_t;
+
+
+/*!
+ \brief This function creates a sync object
+
+ The sync object is used for synchronization between diffrent thread or ISR and
+ a thread.
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_SyncObjCreate(pSyncObj,pName) osi_SyncObjCreate(pSyncObj)
+
+
+/*!
+ \brief This function deletes a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_SyncObjDelete(pSyncObj) osi_SyncObjDelete(pSyncObj)
+
+
+/*!
+ \brief This function generates a sync signal for the object.
+
+ All suspended threads waiting on this sync object are resumed
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signaling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function could be called from ISR context
+ \warning
+*/
+#define sl_SyncObjSignal(pSyncObj) osi_SyncObjSignal(pSyncObj)
+
+/*!
+ \brief This function generates a sync signal for the object from Interrupt
+
+ This is for RTOS that should signal from IRQ using a dedicated API
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signaling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function could be called from ISR context
+ \warning
+*/
+#define sl_SyncObjSignalFromIRQ(pSyncObj) osi_SyncObjSignalFromISR(pSyncObj)
+
+/*!
+ \brief This function waits for a sync signal of the specific sync object
+
+ \param pSyncObj - pointer to the sync object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the sync signal
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+ \return upon successful reception of the signal within the timeout window return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_SyncObjWait(pSyncObj,Timeout) osi_SyncObjWait(pSyncObj,Timeout)
+
+/*!
+ \brief type definition for a locking object container
+
+ Locking object are used to protect a resource from mutual accesses of two or more threads.
+ The locking object should suppurt reentrant locks by a signal thread.
+ This object is generally implemented by mutex semaphore
+
+ \note On each porting or platform the type could be whatever is needed - integer, structure etc.
+ \note belongs to \ref ported_sec
+*/
+typedef OsiLockObj_t _SlLockObj_t;
+
+/*!
+ \brief This function creates a locking object.
+
+ The locking object is used for protecting a shared resources between different
+ threads.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjCreate(pLockObj,pName) osi_LockObjCreate(pLockObj)
+
+/*!
+ \brief This function deletes a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjDelete(pLockObj) osi_LockObjDelete(pLockObj)
+
+/*!
+ \brief This function locks a locking object.
+
+ All other threads that call this function before this thread calls
+ the osi_LockObjUnlock would be suspended
+
+ \param pLockObj - pointer to the locking object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the locking object
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+
+ \return upon successful reception of the locking object the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjLock(pLockObj,Timeout) osi_LockObjLock(pLockObj,Timeout)
+
+/*!
+ \brief This function unlock a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful unlocking the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjUnlock(pLockObj) osi_LockObjUnlock(pLockObj)
+
+#endif
+/*!
+ \brief This function call the pEntry callback from a different context
+
+ \param pEntry - pointer to the entry callback function
+
+ \param pValue - pointer to any type of memory structure that would be
+ passed to pEntry callback from the execution thread.
+
+ \param flags - execution flags - reserved for future usage
+
+ \return upon successful registration of the spawn the function should return 0
+ (the function is not blocked till the end of the execution of the function
+ and could be returned before the execution is actually completed)
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+//#define SL_PLATFORM_EXTERNAL_SPAWN
+
+#ifdef SL_PLATFORM_EXTERNAL_SPAWN
+#define sl_Spawn(pEntry,pValue,flags) osi_Spawn(pEntry,pValue,flags)
+#endif
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+/*!
+ ******************************************************************************
+
+ \defgroup porting_mem_mgm Porting - Memory Management
+
+ This section declare in which memory management model the SimpleLink driver
+ will run:
+ -# Static
+ -# Dynamic
+
+ This section IS NOT REQUIRED in case Static model is selected.
+
+ The default memory model is Static
+
+ PORTING ACTION:
+ - If dynamic model is selected, define the alloc and free functions.
+
+ @{
+
+ *****************************************************************************
+*/
+
+/*!
+ \brief Defines whether the SimpleLink driver is working in dynamic
+ memory model or not
+
+ When defined, the SimpleLink driver use dynamic allocations
+ if dynamic allocation is selected malloc and free functions
+ must be retrieved
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define SL_MEMORY_MGMT_DYNAMIC 1
+#define SL_MEMORY_MGMT_STATIC 0
+
+#define SL_MEMORY_MGMT SL_MEMORY_MGMT_STATIC
+
+#ifdef SL_MEMORY_MGMT_DYNAMIC
+#ifdef SL_PLATFORM_MULTI_THREADED
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Malloc(Size) mem_Malloc(Size)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Free(pMem) mem_Free(pMem)
+#else
+#include
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Malloc(Size) malloc(Size)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Free(pMem) free(pMem)
+#endif
+#endif
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup porting_events Porting - Event Handlers
+
+ This section includes the asynchronous event handlers routines
+
+ PORTING ACTION:
+ -Uncomment the required handler and define your routine as the value
+ of this handler
+
+ @{
+
+ ******************************************************************************
+ */
+
+/*!
+ \brief
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_GeneralEvtHdlr SimpleLinkGeneralEventHandler
+
+
+/*!
+ \brief An event handler for WLAN connection or disconnection indication
+ This event handles async WLAN events.
+ Possible events are:
+ SL_WLAN_CONNECT_EVENT - indicates WLAN is connected
+ SL_WLAN_DISCONNECT_EVENT - indicates WLAN is disconnected
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_WlanEvtHdlr SimpleLinkWlanEventHandler
+
+
+/*!
+ \brief An event handler for IP address asynchronous event. Usually accepted after new WLAN connection.
+ This event handles networking events.
+ Possible events are:
+ SL_NETAPP_IPV4_ACQUIRED - IP address was acquired (DHCP or Static)
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_NetAppEvtHdlr SimpleLinkNetAppEventHandler
+
+/*!
+ \brief A callback for HTTP server events.
+ Possible events are:
+ SL_NETAPP_HTTPGETTOKENVALUE - NWP requests to get the value of a specific token
+ SL_NETAPP_HTTPPOSTTOKENVALUE - NWP post to the host a new value for a specific token
+
+ \param pServerEvent - Contains the relevant event information (SL_NETAPP_HTTPGETTOKENVALUE or SL_NETAPP_HTTPPOSTTOKENVALUE)
+
+ \param pServerResponse - Should be filled by the user with the relevant response information (i.e SL_NETAPP_HTTPSETTOKENVALUE as a response to SL_NETAPP_HTTPGETTOKENVALUE event)
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_HttpServerCallback SimpleLinkHttpServerCallback
+/*!
+ \brief
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_SockEvtHdlr SimpleLinkSockEventHandler
+
+
+
+#define _SL_USER_TYPES
+#define _u8 unsigned char
+#define _i8 signed char
+
+#define _u16 unsigned short
+#define _i16 signed short
+
+#define _u32 unsigned int
+#define _i32 signed int
+#define _volatile volatile
+#define _const const
+
+
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __USER_H__
diff --git a/cc3200/fatfs/src/diskio.c b/cc3200/fatfs/src/diskio.c
new file mode 100644
index 0000000000..83041d6463
--- /dev/null
+++ b/cc3200/fatfs/src/diskio.c
@@ -0,0 +1,208 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2014 */
+/*-----------------------------------------------------------------------*/
+/* If a working storage control module is available, it should be */
+/* attached to the FatFs via a glue function rather than modifying it. */
+/* This is an example of glue functions to attach various exsisting */
+/* storage control modules to the FatFs module with a defined API. */
+/*-----------------------------------------------------------------------*/
+#include
+#include
+
+#include "mpconfig.h"
+#include "diskio.h" /* FatFs lower layer API */
+#include "sflash_diskio.h" /* Serial flash disk IO API */
+#if MICROPY_HW_HAS_SDCARD
+#include "sd_diskio.h" /* SDCARD disk IO API */
+#endif
+#include "modutime.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "prcm.h"
+
+/* Definitions of physical drive number for each drive */
+#define SFLASH 0 /* Map SFLASH drive to drive number 0 */
+#define SDCARD 1 /* Map SD card to drive number 1 */
+
+
+/*-----------------------------------------------------------------------*/
+/* Get Drive Status */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_status (
+ BYTE pdrv /* Physical drive nmuber to identify the drive */
+)
+{
+ switch (pdrv) {
+ case SFLASH :
+ return sflash_disk_status();
+#if MICROPY_HW_HAS_SDCARD
+ case SDCARD :
+ return sd_disk_status();
+#endif
+ default:
+ break;
+ }
+ return STA_NODISK;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Inidialize a Drive */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (
+ BYTE pdrv /* Physical drive nmuber to identify the drive */
+)
+{
+ DSTATUS stat = 0;
+
+ switch (pdrv) {
+ case SFLASH :
+ if (RES_OK != sflash_disk_init()) {
+ stat = STA_NOINIT;
+ }
+ return stat;
+#if MICROPY_HW_HAS_SDCARD
+ case SDCARD :
+ if (RES_OK != sd_disk_init()) {
+ stat = STA_NOINIT;
+ }
+ return stat;
+#endif
+ default:
+ break;
+ }
+ return STA_NOINIT;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s) */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_read (
+ BYTE pdrv, /* Physical drive nmuber to identify the drive */
+ BYTE *buff, /* Data buffer to store read data */
+ DWORD sector, /* Sector address in LBA */
+ UINT count /* Number of sectors to read */
+)
+{
+ switch (pdrv) {
+ case SFLASH :
+ return sflash_disk_read(buff, sector, count);
+#if MICROPY_HW_HAS_SDCARD
+ case SDCARD :
+ return sd_disk_read(buff, sector, count);
+#endif
+ default:
+ break;
+ }
+
+ return RES_PARERR;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s) */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_WRITE
+DRESULT disk_write (
+ BYTE pdrv, /* Physical drive nmuber to identify the drive */
+ const BYTE *buff, /* Data to be written */
+ DWORD sector, /* Sector address in LBA */
+ UINT count /* Number of sectors to write */
+)
+{
+ switch (pdrv) {
+ case SFLASH :
+ return sflash_disk_write(buff, sector, count);
+#if MICROPY_HW_HAS_SDCARD
+ case SDCARD :
+ return sd_disk_write(buff, sector, count);
+#endif
+ default:
+ break;
+ }
+
+ return RES_PARERR;
+}
+#endif
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_IOCTL
+DRESULT disk_ioctl (
+ BYTE pdrv, /* Physical drive nmuber (0..) */
+ BYTE cmd, /* Control code */
+ void *buff /* Buffer to send/receive control data */
+)
+{
+ switch (pdrv) {
+ case SFLASH:
+ switch (cmd) {
+ case CTRL_SYNC:
+ return sflash_disk_flush();
+ case GET_SECTOR_COUNT:
+ *((DWORD*)buff) = SFLASH_SECTOR_COUNT;
+ return RES_OK;
+ break;
+ case GET_SECTOR_SIZE:
+ *((WORD*)buff) = SFLASH_SECTOR_SIZE;
+ return RES_OK;
+ break;
+ case GET_BLOCK_SIZE:
+ *((DWORD*)buff) = 1; // high-level sector erase size in units of the block size
+ return RES_OK;
+ }
+ break;
+#if MICROPY_HW_HAS_SDCARD
+ case SDCARD:
+ switch (cmd) {
+ case CTRL_SYNC:
+ return RES_OK;
+ case GET_SECTOR_COUNT:
+ *(WORD*)buff = sd_disk_info.ulNofBlock;
+ break;
+ case GET_SECTOR_SIZE :
+ *(WORD*)buff = SD_SECTOR_SIZE;
+ break;
+ case GET_BLOCK_SIZE:
+ *((DWORD*)buff) = 1; // high-level sector erase size in units of the block size
+ return RES_OK;
+ }
+ break;
+#endif
+ }
+ return RES_PARERR;
+}
+#endif
+
+#if !_FS_READONLY && !_FS_NORTC
+DWORD get_fattime (
+ void
+)
+{
+ mod_struct_time tm;
+ uint32_t seconds;
+ uint16_t mseconds;
+
+ // Get the time from the on-chip RTC and convert it to struct_time
+ MAP_PRCMRTCGet(&seconds, &mseconds);
+ mod_time_seconds_since_2000_to_struct_time(seconds, &tm);
+
+ return ((tm.tm_year - 1980) << 25) | ((tm.tm_mon) << 21) |
+ ((tm.tm_mday) << 16) | ((tm.tm_hour) << 11) |
+ ((tm.tm_min) << 5) | (tm.tm_sec >> 1);
+}
+#endif
+
diff --git a/cc3200/fatfs/src/diskio.h b/cc3200/fatfs/src/diskio.h
new file mode 100644
index 0000000000..6e4a056f06
--- /dev/null
+++ b/cc3200/fatfs/src/diskio.h
@@ -0,0 +1,62 @@
+/*-----------------------------------------------------------------------/
+/ Low level disk interface modlue include file (C)ChaN, 2014 /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define _USE_WRITE 1 /* 1: Enable disk_write function */
+#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE DSTATUS;
+
+/* Results of Disk Functions */
+typedef enum {
+ RES_OK = 0, /* 0: Successful */
+ RES_ERROR, /* 1: R/W Error */
+ RES_WRPRT, /* 2: Write Protected */
+ RES_NOTRDY, /* 3: Not Ready */
+ RES_PARERR /* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+DSTATUS disk_initialize (BYTE pdrv);
+DSTATUS disk_status (BYTE pdrv);
+DRESULT disk_read (BYTE pdrv, BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
+DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
+
+
+/* Disk Status Bits (DSTATUS) */
+
+#define STA_NOINIT 0x01 /* Drive not initialized */
+#define STA_NODISK 0x02 /* No medium in the drive */
+#define STA_PROTECT 0x04 /* Write protected */
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC 0 /* Complete pending write process (needed at _FS_READONLY == 0) */
+#define GET_SECTOR_COUNT 1 /* Get media size (needed at _USE_MKFS == 1) */
+#define GET_SECTOR_SIZE 2 /* Get sector size (needed at _MAX_SS != _MIN_SS) */
+#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at _USE_MKFS == 1) */
+#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at _USE_TRIM == 1) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cc3200/fatfs/src/drivers/sd_diskio.c b/cc3200/fatfs/src/drivers/sd_diskio.c
new file mode 100644
index 0000000000..29d92dd64a
--- /dev/null
+++ b/cc3200/fatfs/src/drivers/sd_diskio.c
@@ -0,0 +1,446 @@
+//*****************************************************************************
+// sd_diskio.c
+//
+// Low level SD Card access hookup for FatFS
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "objtuple.h"
+#include "objlist.h"
+#include "runtime.h"
+#include "hw_types.h"
+#include "hw_memmap.h"
+#include "hw_ints.h"
+#include "rom.h"
+#include "rom_map.h"
+#include "diskio.h"
+#include "sd_diskio.h"
+#include "sdhost.h"
+#include "pin.h"
+#include "prcm.h"
+#include "stdcmd.h"
+#include "utils.h"
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define DISKIO_RETRY_TIMEOUT 0xFFFFFFFF
+
+#define CARD_TYPE_UNKNOWN 0
+#define CARD_TYPE_MMC 1
+#define CARD_TYPE_SDCARD 2
+
+#define CARD_CAP_CLASS_SDSC 0
+#define CARD_CAP_CLASS_SDHC 1
+
+#define CARD_VERSION_1 0
+#define CARD_VERSION_2 1
+
+//*****************************************************************************
+// Disk Info for attached disk
+//*****************************************************************************
+DiskInfo_t sd_disk_info = {CARD_TYPE_UNKNOWN, CARD_VERSION_1, CARD_CAP_CLASS_SDSC, 0, 0, STA_NOINIT, 0};
+
+//*****************************************************************************
+//
+//! Send Command to card
+//!
+//! \param ulCmd is the command to be send
+//! \paran ulArg is the command argument
+//!
+//! This function sends command to attached card and check the response status
+//! if any.
+//!
+//! \return Returns 0 on success, 1 otherwise
+//
+//*****************************************************************************
+static unsigned int CardSendCmd (unsigned int ulCmd, unsigned int ulArg) {
+ unsigned long ulStatus;
+
+ // Clear interrupt status
+ MAP_SDHostIntClear(SDHOST_BASE,0xFFFFFFFF);
+
+ // Send command
+ MAP_SDHostCmdSend(SDHOST_BASE,ulCmd,ulArg);
+
+ // Wait for command complete or error
+ do {
+ ulStatus = MAP_SDHostIntStatus(SDHOST_BASE);
+ ulStatus = (ulStatus & (SDHOST_INT_CC | SDHOST_INT_ERRI));
+ } while (!ulStatus);
+
+ // Check error status
+ if (ulStatus & SDHOST_INT_ERRI) {
+ // Reset the command line
+ MAP_SDHostCmdReset(SDHOST_BASE);
+ return 1;
+ }
+ else {
+ return 0;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the capacity of specified card
+//!
+//! \param ulRCA is the Relative Card Address (RCA)
+//!
+//! This function gets the capacity of card addressed by \e ulRCA paramaeter.
+//!
+//! \return Returns 0 on success, 1 otherwise.
+//
+//*****************************************************************************
+static unsigned int CardCapacityGet(DiskInfo_t *psDiskInfo) {
+ unsigned long ulRet;
+ unsigned long ulResp[4];
+ unsigned long ulBlockSize;
+ unsigned long ulBlockCount;
+ unsigned long ulCSizeMult;
+ unsigned long ulCSize;
+
+ // Read the CSD register
+ ulRet = CardSendCmd(CMD_SEND_CSD, (psDiskInfo->usRCA << 16));
+
+ if(ulRet == 0) {
+ // Read the response
+ MAP_SDHostRespGet(SDHOST_BASE,ulResp);
+
+ // 136 bit CSD register is read into an array of 4 words.
+ // ulResp[0] = CSD[31:0]
+ // ulResp[1] = CSD[63:32]
+ // ulResp[2] = CSD[95:64]
+ // ulResp[3] = CSD[127:96]
+ if(ulResp[3] >> 30) {
+ ulBlockSize = SD_SECTOR_SIZE * 1024;
+ ulBlockCount = (ulResp[1] >> 16 | ((ulResp[2] & 0x3F) << 16)) + 1;
+ }
+ else {
+ ulBlockSize = 1 << ((ulResp[2] >> 16) & 0xF);
+ ulCSizeMult = ((ulResp[1] >> 15) & 0x7);
+ ulCSize = ((ulResp[1] >> 30) | (ulResp[2] & 0x3FF) << 2);
+ ulBlockCount = (ulCSize + 1) * (1 << (ulCSizeMult + 2));
+ }
+
+ // Calculate the card capacity in bytes
+ psDiskInfo->ulBlockSize = ulBlockSize;
+ psDiskInfo->ulNofBlock = ulBlockCount;
+ }
+
+ return ulRet;
+}
+
+//*****************************************************************************
+//
+//! Select a card for reading or writing
+//!
+//! \param Card is the pointer to card attribute structure.
+//!
+//! This function selects a card for reading or writing using its RCA from
+//! \e Card parameter.
+//!
+//! \return Returns 0 success, 1 otherwise.
+//
+//*****************************************************************************
+static unsigned int CardSelect (DiskInfo_t *sDiskInfo) {
+ unsigned long ulRCA;
+ unsigned long ulRet;
+
+ ulRCA = sDiskInfo->usRCA;
+
+ // Send select command with card's RCA.
+ ulRet = CardSendCmd(CMD_SELECT_CARD, (ulRCA << 16));
+
+ if (ulRet == 0) {
+ while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+ }
+
+ // Delay 250ms for the card to become ready
+ HAL_Delay (250);
+
+ return ulRet;
+}
+
+//*****************************************************************************
+//
+//! Initializes physical drive
+//!
+//! This function initializes the physical drive
+//!
+//! \return Returns 0 on succeeded.
+//*****************************************************************************
+DSTATUS sd_disk_init (void) {
+ unsigned long ulRet;
+ unsigned long ulResp[4];
+
+ if (sd_disk_info.bStatus != 0) {
+ sd_disk_info.bStatus = STA_NODISK;
+ // Send std GO IDLE command
+ if (CardSendCmd(CMD_GO_IDLE_STATE, 0) == 0) {
+ // Get interface operating condition for the card
+ ulRet = CardSendCmd(CMD_SEND_IF_COND,0x000001A5);
+ MAP_SDHostRespGet(SDHOST_BASE,ulResp);
+
+ // It's a SD ver 2.0 or higher card
+ if (ulRet == 0 && ((ulResp[0] & 0xFF) == 0xA5)) {
+ // Version 1 card do not respond to this command
+ sd_disk_info.ulVersion = CARD_VERSION_2;
+ sd_disk_info.ucCardType = CARD_TYPE_SDCARD;
+
+ // Wait for card to become ready.
+ do {
+ // Send ACMD41
+ CardSendCmd(CMD_APP_CMD, 0);
+ ulRet = CardSendCmd(CMD_SD_SEND_OP_COND, 0x40E00000);
+
+ // Response contains 32-bit OCR register
+ MAP_SDHostRespGet(SDHOST_BASE, ulResp);
+
+ } while (((ulResp[0] >> 31) == 0));
+
+ if (ulResp[0] & (1UL<<30)) {
+ sd_disk_info.ulCapClass = CARD_CAP_CLASS_SDHC;
+ }
+ sd_disk_info.bStatus = 0;
+ }
+ //It's a MMC or SD 1.x card
+ else {
+ // Wait for card to become ready.
+ do {
+ CardSendCmd(CMD_APP_CMD, 0);
+ ulRet = CardSendCmd(CMD_SD_SEND_OP_COND,0x00E00000);
+ if (ulRet == 0) {
+ // Response contains 32-bit OCR register
+ MAP_SDHostRespGet(SDHOST_BASE, ulResp);
+ }
+ } while (((ulRet == 0) && (ulResp[0] >> 31) == 0));
+
+ if (ulRet == 0) {
+ sd_disk_info.ucCardType = CARD_TYPE_SDCARD;
+ sd_disk_info.bStatus = 0;
+ }
+ else {
+ if (CardSendCmd(CMD_SEND_OP_COND, 0) == 0) {
+ // MMC not supported by the controller
+ sd_disk_info.ucCardType = CARD_TYPE_MMC;
+ }
+ }
+ }
+ }
+
+ // Get the RCA of the attached card
+ if (sd_disk_info.bStatus == 0) {
+ ulRet = CardSendCmd(CMD_ALL_SEND_CID, 0);
+ if (ulRet == 0) {
+ CardSendCmd(CMD_SEND_REL_ADDR,0);
+ MAP_SDHostRespGet(SDHOST_BASE, ulResp);
+
+ // Fill in the RCA
+ sd_disk_info.usRCA = (ulResp[0] >> 16);
+
+ // Get tha card capacity
+ CardCapacityGet(&sd_disk_info);
+ }
+
+ // Select the card.
+ ulRet = CardSelect(&sd_disk_info);
+ if (ulRet == 0) {
+ sd_disk_info.bStatus = 0;
+ }
+ }
+ // Set card rd/wr block len
+ MAP_SDHostBlockSizeSet(SDHOST_BASE, SD_SECTOR_SIZE);
+ }
+
+ return sd_disk_info.bStatus;
+}
+
+//*****************************************************************************
+//
+//! Gets the disk status.
+//!
+//! This function gets the current status of the drive.
+//!
+//! \return Returns the current status of the specified drive
+//
+//*****************************************************************************
+DSTATUS sd_disk_status (void) {
+ return sd_disk_info.bStatus;
+}
+
+//*****************************************************************************
+//
+//! Returns wether the sd card is ready to be accessed or not
+//
+//*****************************************************************************
+bool sd_disk_ready (void) {
+ return (!sd_disk_info.bStatus);
+}
+
+//*****************************************************************************
+//
+//! Reads sector(s) from the disk drive.
+//!
+//!
+//! This function reads specified number of sectors from the drive
+//!
+//! \return Returns RES_OK on success.
+//
+//*****************************************************************************
+DRESULT sd_disk_read (BYTE* pBuffer, DWORD ulSectorNumber, UINT SectorCount) {
+ DRESULT Res = RES_ERROR;
+ unsigned long ulSize;
+
+ if (SectorCount > 0) {
+ // Return if disk not initialized
+ if (sd_disk_info.bStatus & STA_NOINIT) {
+ return RES_NOTRDY;
+ }
+
+ // SDSC uses linear address, SDHC uses block address
+ if (sd_disk_info.ulCapClass == CARD_CAP_CLASS_SDSC) {
+ ulSectorNumber = ulSectorNumber * SD_SECTOR_SIZE;
+ }
+
+ // Set the block count
+ MAP_SDHostBlockCountSet(SDHOST_BASE, SectorCount);
+
+ // Compute the number of words
+ ulSize = (SD_SECTOR_SIZE * SectorCount) / 4;
+
+ // Check if 1 block or multi block transfer
+ if (SectorCount == 1) {
+ // Send single block read command
+ if (CardSendCmd(CMD_READ_SINGLE_BLK, ulSectorNumber) == 0) {
+ // Read the block of data
+ while (ulSize--) {
+ MAP_SDHostDataRead(SDHOST_BASE, (unsigned long *)pBuffer);
+ pBuffer += 4;
+ }
+ Res = RES_OK;
+ }
+ }
+ else {
+ // Send multi block read command
+ if (CardSendCmd(CMD_READ_MULTI_BLK, ulSectorNumber) == 0) {
+ // Read the data
+ while (ulSize--) {
+ MAP_SDHostDataRead(SDHOST_BASE, (unsigned long *)pBuffer);
+ pBuffer += 4;
+ }
+ CardSendCmd(CMD_STOP_TRANS, 0);
+ Res = RES_OK;
+ }
+ }
+ }
+
+ return Res;
+}
+
+//*****************************************************************************
+//
+//! Wrties sector(s) to the disk drive.
+//!
+//!
+//! This function writes specified number of sectors to the drive
+//!
+//! \return Returns RES_OK on success.
+//
+//*****************************************************************************
+DRESULT sd_disk_write (const BYTE* pBuffer, DWORD ulSectorNumber, UINT SectorCount) {
+ DRESULT Res = RES_ERROR;
+ unsigned long ulSize;
+
+ if (SectorCount > 0) {
+ // Return if disk not initialized
+ if (sd_disk_info.bStatus & STA_NOINIT) {
+ return RES_NOTRDY;
+ }
+
+ // SDSC uses linear address, SDHC uses block address
+ if (sd_disk_info.ulCapClass == CARD_CAP_CLASS_SDSC) {
+ ulSectorNumber = ulSectorNumber * SD_SECTOR_SIZE;
+ }
+
+ // Set the block count
+ MAP_SDHostBlockCountSet(SDHOST_BASE, SectorCount);
+
+ // Compute the number of words
+ ulSize = (SD_SECTOR_SIZE * SectorCount) / 4;
+
+ // Check if 1 block or multi block transfer
+ if (SectorCount == 1) {
+ // Send single block write command
+ if (CardSendCmd(CMD_WRITE_SINGLE_BLK, ulSectorNumber) == 0) {
+ // Write the data
+ while (ulSize--) {
+ MAP_SDHostDataWrite (SDHOST_BASE, (*(unsigned long *)pBuffer));
+ pBuffer += 4;
+ }
+ // Wait for data transfer complete
+ while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+ Res = RES_OK;
+ }
+ }
+ else {
+ // Set the card write block count
+ if (sd_disk_info.ucCardType == CARD_TYPE_SDCARD) {
+ CardSendCmd(CMD_APP_CMD,sd_disk_info.usRCA << 16);
+ CardSendCmd(CMD_SET_BLK_CNT, SectorCount);
+ }
+
+ // Send multi block write command
+ if (CardSendCmd(CMD_WRITE_MULTI_BLK, ulSectorNumber) == 0) {
+ // Write the data buffer
+ while (ulSize--) {
+ MAP_SDHostDataWrite(SDHOST_BASE, (*(unsigned long *)pBuffer));
+ pBuffer += 4;
+ }
+ // Wait for transfer complete
+ while (!(MAP_SDHostIntStatus(SDHOST_BASE) & SDHOST_INT_TC));
+ CardSendCmd(CMD_STOP_TRANS, 0);
+ Res = RES_OK;
+ }
+ }
+ }
+
+ return Res;
+}
diff --git a/cc3200/fatfs/src/drivers/sd_diskio.h b/cc3200/fatfs/src/drivers/sd_diskio.h
new file mode 100644
index 0000000000..93135c7984
--- /dev/null
+++ b/cc3200/fatfs/src/drivers/sd_diskio.h
@@ -0,0 +1,28 @@
+#ifndef SD_DISKIO_H_
+#define SD_DISKIO_H_
+
+#define SD_SECTOR_SIZE 512
+
+//*****************************************************************************
+// Disk Info Structure definition
+//*****************************************************************************
+typedef struct
+{
+ unsigned char ucCardType;
+ unsigned int ulVersion;
+ unsigned int ulCapClass;
+ unsigned int ulNofBlock;
+ unsigned int ulBlockSize;
+ DSTATUS bStatus;
+ unsigned short usRCA;
+}DiskInfo_t;
+
+extern DiskInfo_t sd_disk_info;
+
+DSTATUS sd_disk_init (void);
+DSTATUS sd_disk_status (void);
+bool sd_disk_ready (void);
+DRESULT sd_disk_read (BYTE* pBuffer, DWORD ulSectorNumber, UINT bSectorCount);
+DRESULT sd_disk_write (const BYTE* pBuffer, DWORD ulSectorNumber, UINT bSectorCount);
+
+#endif /* SD_DISKIO_H_ */
diff --git a/cc3200/fatfs/src/drivers/sflash_diskio.c b/cc3200/fatfs/src/drivers/sflash_diskio.c
new file mode 100644
index 0000000000..cb28913bfd
--- /dev/null
+++ b/cc3200/fatfs/src/drivers/sflash_diskio.c
@@ -0,0 +1,186 @@
+#include
+#include
+#include "std.h"
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "simplelink.h"
+#include "diskio.h"
+#include "sflash_diskio.h"
+#include "debug.h"
+#include "modwlan.h"
+
+#ifdef USE_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+
+#define SFLASH_TIMEOUT_MAX_MS 5500
+#define SFLASH_WAIT_TIME_MS 5
+
+static _u8 sflash_block_name[] = "__NNN__.fsb";
+static _u8 *sflash_block_cache;
+static bool sflash_init_done = false;
+static bool sflash_cache_is_dirty;
+static uint32_t sflash_ublock;
+static uint32_t sflash_prblock;
+
+
+static void print_block_name (_u32 ublock) {
+ char _sblock[4];
+ snprintf (_sblock, sizeof(_sblock), "%03u", ublock);
+ memcpy (&sflash_block_name[2], _sblock, 3);
+}
+
+static bool sflash_access (_u32 mode, _i32 (* sl_FsFunction)(_i32 FileHdl, _u32 Offset, _u8* pData, _u32 Len)) {
+ _i32 fileHandle;
+ bool retval = false;
+
+ // wlan must be enabled in order to access the serial flash
+#ifdef USE_FREERTOS
+ xSemaphoreTake (xWlanSemaphore, portMAX_DELAY);
+#endif
+ if (0 == sl_FsOpen(sflash_block_name, mode, NULL, &fileHandle)) {
+ if (SFLASH_BLOCK_SIZE == sl_FsFunction (fileHandle, 0, sflash_block_cache, SFLASH_BLOCK_SIZE)) {
+ retval = true;
+ }
+ sl_FsClose (fileHandle, NULL, NULL, 0);
+ }
+#ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+#endif
+ return retval;
+}
+
+DRESULT sflash_disk_init (void) {
+ _i32 fileHandle;
+ SlFsFileInfo_t FsFileInfo;
+
+ if (!sflash_init_done) {
+ // Allocate space for the block cache
+ ASSERT ((sflash_block_cache = mem_Malloc(SFLASH_BLOCK_SIZE)) != NULL);
+
+ // Proceed to format the memory if not done yet
+ for (int i = 0; i < SFLASH_BLOCK_COUNT; i++) {
+ print_block_name (i);
+ #ifdef USE_FREERTOS
+ xSemaphoreTake (xWlanSemaphore, portMAX_DELAY);
+ #endif
+ // Create the block file if it doesn't exist
+ if (sl_FsGetInfo(sflash_block_name, 0, &FsFileInfo) < 0) {
+ if (!sl_FsOpen(sflash_block_name, FS_MODE_OPEN_CREATE(SFLASH_BLOCK_SIZE, 0), NULL, &fileHandle)) {
+ sl_FsClose(fileHandle, NULL, NULL, 0);
+ #ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+ #endif
+ memset(sflash_block_cache, 0xFF, SFLASH_BLOCK_SIZE);
+ if (!sflash_access(FS_MODE_OPEN_WRITE, sl_FsWrite)) {
+ return RES_ERROR;
+ }
+ }
+ else {
+ // Unexpected failure while creating the file
+ #ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+ #endif
+ return RES_ERROR;
+ }
+ }
+ #ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+ #endif
+ }
+ sflash_init_done = true;
+ sflash_prblock = UINT32_MAX;
+ sflash_cache_is_dirty = false;
+ }
+ return RES_OK;
+}
+
+DRESULT sflash_disk_status(void) {
+ if (!sflash_init_done) {
+ return STA_NOINIT;
+ }
+ return 0;
+}
+
+DRESULT sflash_disk_read(BYTE *buff, DWORD sector, UINT count) {
+ uint32_t secindex;
+
+ if (!sflash_init_done) {
+ return STA_NOINIT;
+ }
+
+ if (sector + count > SFLASH_SECTOR_COUNT || count == 0) {
+ return RES_PARERR;
+ }
+
+ for (int i = 0; i < count; i++) {
+ secindex = (sector + i) % SFLASH_SECTORS_PER_BLOCK;
+ sflash_ublock = (sector + i) / SFLASH_SECTORS_PER_BLOCK;
+ // See if it's time to read a new block
+ if (sflash_prblock != sflash_ublock) {
+ if (sflash_disk_flush() != RES_OK) {
+ return RES_ERROR;
+ }
+ sflash_prblock = sflash_ublock;
+ print_block_name (sflash_ublock);
+ if (!sflash_access(FS_MODE_OPEN_READ, sl_FsRead)) {
+ return RES_ERROR;
+ }
+ }
+ // Copy the requested sector from the block cache
+ memcpy (buff, &sflash_block_cache[(secindex * SFLASH_SECTOR_SIZE)], SFLASH_SECTOR_SIZE);
+ buff += SFLASH_BLOCK_SIZE;
+ }
+ return RES_OK;
+}
+
+DRESULT sflash_disk_write(const BYTE *buff, DWORD sector, UINT count) {
+ uint32_t secindex;
+ int32_t index = 0;
+
+ if (!sflash_init_done) {
+ return STA_NOINIT;
+ }
+
+ if (sector + count > SFLASH_SECTOR_COUNT || count == 0) {
+ return RES_PARERR;
+ }
+
+ do {
+ secindex = (sector + index) % SFLASH_SECTORS_PER_BLOCK;
+ sflash_ublock = (sector + index) / SFLASH_SECTORS_PER_BLOCK;
+ // Check if it's a different block than last time
+ if (sflash_prblock != sflash_ublock) {
+ if (sflash_disk_flush() != RES_OK) {
+ return RES_ERROR;
+ }
+ sflash_prblock = sflash_ublock;
+ print_block_name (sflash_ublock);
+ // Read the block into the cache
+ if (!sflash_access(FS_MODE_OPEN_READ, sl_FsRead)) {
+ return RES_ERROR;
+ }
+ }
+ // Copy the input sector to the block cache
+ memcpy (&sflash_block_cache[(secindex * SFLASH_SECTOR_SIZE)], buff, SFLASH_SECTOR_SIZE);
+ buff += SFLASH_BLOCK_SIZE;
+ sflash_cache_is_dirty = true;
+ } while (++index < count);
+
+ return RES_OK;
+}
+
+DRESULT sflash_disk_flush (void) {
+ // Write back the cache if it's dirty
+ if (sflash_cache_is_dirty) {
+ if (!sflash_access(FS_MODE_OPEN_WRITE, sl_FsWrite)) {
+ return RES_ERROR;
+ }
+ sflash_cache_is_dirty = false;
+ }
+ return RES_OK;
+}
+
diff --git a/cc3200/fatfs/src/drivers/sflash_diskio.h b/cc3200/fatfs/src/drivers/sflash_diskio.h
new file mode 100644
index 0000000000..26669f5898
--- /dev/null
+++ b/cc3200/fatfs/src/drivers/sflash_diskio.h
@@ -0,0 +1,16 @@
+#ifndef SFLASH_DISKIO_H_
+#define SFLASH_DISKIO_H_
+
+#define SFLASH_BLOCK_SIZE 2048
+#define SFLASH_BLOCK_COUNT 32 // makes for 64KB of space
+#define SFLASH_SECTOR_SIZE 512
+#define SFLASH_SECTOR_COUNT ((SFLASH_BLOCK_SIZE * SFLASH_BLOCK_COUNT) / SFLASH_SECTOR_SIZE)
+#define SFLASH_SECTORS_PER_BLOCK (SFLASH_BLOCK_SIZE / SFLASH_SECTOR_SIZE)
+
+DRESULT sflash_disk_init(void);
+DRESULT sflash_disk_status(void);
+DRESULT sflash_disk_read(BYTE *buff, DWORD sector, UINT count);
+DRESULT sflash_disk_write(const BYTE *buff, DWORD sector, UINT count);
+DRESULT sflash_disk_flush(void);
+
+#endif /* SFLASH_DISKIO_H_ */
diff --git a/cc3200/fatfs/src/drivers/stdcmd.h b/cc3200/fatfs/src/drivers/stdcmd.h
new file mode 100644
index 0000000000..464e2ddfaa
--- /dev/null
+++ b/cc3200/fatfs/src/drivers/stdcmd.h
@@ -0,0 +1,62 @@
+//*****************************************************************************
+// stdcmd.h
+//
+// Defines standard SD Card commands for CC3200 SDHOST module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __STDCMD_H__
+#define __STDCMD_H__
+
+//*****************************************************************************
+// Standard MMC/SD Card Commands
+//*****************************************************************************
+#define CMD_GO_IDLE_STATE SDHOST_CMD_0
+#define CMD_SEND_IF_COND SDHOST_CMD_8|SDHOST_RESP_LEN_48
+#define CMD_SEND_CSD SDHOST_CMD_9|SDHOST_RESP_LEN_136
+#define CMD_APP_CMD SDHOST_CMD_55|SDHOST_RESP_LEN_48
+#define CMD_SD_SEND_OP_COND SDHOST_CMD_41|SDHOST_RESP_LEN_48
+#define CMD_SEND_OP_COND SDHOST_CMD_1|SDHOST_RESP_LEN_48
+#define CMD_READ_SINGLE_BLK SDHOST_CMD_17|SDHOST_RD_CMD|SDHOST_RESP_LEN_48
+#define CMD_READ_MULTI_BLK SDHOST_CMD_18|SDHOST_RD_CMD|SDHOST_RESP_LEN_48|SDHOST_MULTI_BLK
+#define CMD_WRITE_SINGLE_BLK SDHOST_CMD_24|SDHOST_WR_CMD|SDHOST_RESP_LEN_48
+#define CMD_WRITE_MULTI_BLK SDHOST_CMD_25|SDHOST_WR_CMD|SDHOST_RESP_LEN_48|SDHOST_MULTI_BLK
+#define CMD_SELECT_CARD SDHOST_CMD_7|SDHOST_RESP_LEN_48B
+#define CMD_DESELECT_CARD SDHOST_CMD_7
+#define CMD_STOP_TRANS SDHOST_CMD_12|SDHOST_RESP_LEN_48B
+#define CMD_SET_BLK_CNT SDHOST_CMD_23|SDHOST_RESP_LEN_48
+#define CMD_ALL_SEND_CID SDHOST_CMD_2|SDHOST_RESP_LEN_136
+#define CMD_SEND_REL_ADDR SDHOST_CMD_3|SDHOST_RESP_LEN_48
+
+#endif //__STDCMD_H__
diff --git a/cc3200/fatfs/src/ffconf.c b/cc3200/fatfs/src/ffconf.c
new file mode 100644
index 0000000000..a52eed55ac
--- /dev/null
+++ b/cc3200/fatfs/src/ffconf.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "mpconfig.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "ff.h"
+#include "ffconf.h"
+#include "diskio.h"
+
+#if _FS_RPATH
+extern BYTE ff_CurrVol;
+#endif
+
+STATIC bool check_path(const TCHAR **path, const char *mount_point_str, mp_uint_t mount_point_len) {
+ stoupper ((char *)(*path));
+ if (strncmp(*path, mount_point_str, mount_point_len) == 0) {
+ if ((*path)[mount_point_len] == '/') {
+ *path += mount_point_len;
+ return true;
+ } else if ((*path)[mount_point_len] == '\0') {
+ *path = "/";
+ return true;
+ }
+ }
+ return false;
+}
+
+// "path" is the path to lookup; will advance this pointer beyond the volume name.
+// Returns logical drive number (-1 means invalid path).
+int ff_get_ldnumber (const TCHAR **path) {
+ if (!(*path)) {
+ return -1;
+ }
+
+ if (**path != '/') {
+ #if _FS_RPATH
+ return ff_CurrVol;
+ #else
+ return -1;
+ #endif
+ }
+
+ if (check_path(path, "/SFLASH", 7)) {
+ return 0;
+ }
+#if MICROPY_HW_HAS_SDCARD
+ else if (check_path(path, "/SD", 3)) {
+ return 1;
+ }
+#endif
+ else {
+ return -1;
+ }
+}
+
+void ff_get_volname(BYTE vol, TCHAR **dest) {
+#if MICROPY_HW_HAS_SDCARD
+ if (vol == 0)
+#endif
+ {
+ memcpy(*dest, "/SFLASH", 7);
+ *dest += 7;
+ }
+#if MICROPY_HW_HAS_SDCARD
+ else
+ {
+ memcpy(*dest, "/SD", 3);
+ *dest += 3;
+ }
+#endif
+}
diff --git a/cc3200/fatfs/src/ffconf.h b/cc3200/fatfs/src/ffconf.h
new file mode 100644
index 0000000000..d2d123e2ef
--- /dev/null
+++ b/cc3200/fatfs/src/ffconf.h
@@ -0,0 +1,276 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module configuration file R0.10c (C)ChaN, 2014
+/---------------------------------------------------------------------------*/
+
+#include
+#include "mpconfig.h"
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+#define _FFCONF 80376 /* Revision ID */
+
+/*---------------------------------------------------------------------------/
+/ Functions and Buffer Configurations
+/---------------------------------------------------------------------------*/
+
+#define _FS_TINY 1
+/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
+/ At the tiny configuration, size of the file object (FIL) is reduced _MAX_SS
+/ bytes. Instead of private sector buffer eliminated from the file object,
+/ common sector buffer in the file system object (FATFS) is used for the file
+/ data transfer. */
+
+
+#define _FS_READONLY 0
+/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
+/ Read-only configuration removes basic writing API functions, f_write(),
+/ f_sync(), f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(),
+/ f_getfree() and optional writing functions as well. */
+
+
+#define _FS_MINIMIZE 0
+/* This option defines minimization level to remove some API functions.
+/
+/ 0: All basic functions are enabled.
+/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(),
+/ f_truncate() and f_rename() function are removed.
+/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
+/ 3: f_lseek() function is removed in addition to 2. */
+
+
+#define _USE_STRFUNC 0
+/* This option switches string functions, f_gets(), f_putc(), f_puts() and
+/ f_printf().
+/
+/ 0: Disable string functions.
+/ 1: Enable without LF-CRLF conversion.
+/ 2: Enable with LF-CRLF conversion. */
+
+
+#define _USE_MKFS 1
+/* This option switches f_mkfs() function. (0:Disable or 1:Enable)
+/ To enable it, also _FS_READONLY need to be set to 0. */
+
+
+#define _USE_FASTSEEK 0
+/* This option switches fast seek feature. (0:Disable or 1:Enable) */
+
+
+#define _USE_LABEL 0
+/* This option switches volume label functions, f_getlabel() and f_setlabel().
+/ (0:Disable or 1:Enable) */
+
+
+#define _USE_FORWARD 0
+/* This option switches f_forward() function. (0:Disable or 1:Enable) */
+/* To enable it, also _FS_TINY need to be set to 1. */
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/---------------------------------------------------------------------------*/
+
+#define _CODE_PAGE (MICROPY_LFN_CODE_PAGE)
+/* This option specifies the OEM code page to be used on the target system.
+/ Incorrect setting of the code page can cause a file open failure.
+/
+/ 932 - Japanese Shift_JIS (DBCS, OEM, Windows)
+/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
+/ 949 - Korean (DBCS, OEM, Windows)
+/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
+/ 1250 - Central Europe (Windows)
+/ 1251 - Cyrillic (Windows)
+/ 1252 - Latin 1 (Windows)
+/ 1253 - Greek (Windows)
+/ 1254 - Turkish (Windows)
+/ 1255 - Hebrew (Windows)
+/ 1256 - Arabic (Windows)
+/ 1257 - Baltic (Windows)
+/ 1258 - Vietnam (OEM, Windows)
+/ 437 - U.S. (OEM)
+/ 720 - Arabic (OEM)
+/ 737 - Greek (OEM)
+/ 775 - Baltic (OEM)
+/ 850 - Multilingual Latin 1 (OEM)
+/ 858 - Multilingual Latin 1 + Euro (OEM)
+/ 852 - Latin 2 (OEM)
+/ 855 - Cyrillic (OEM)
+/ 866 - Russian (OEM)
+/ 857 - Turkish (OEM)
+/ 862 - Hebrew (OEM)
+/ 874 - Thai (OEM, Windows)
+/ 1 - ASCII (No extended character. Valid for only non-LFN configuration.) */
+
+
+#define _USE_LFN (MICROPY_ENABLE_LFN)
+#define _MAX_LFN (MICROPY_ALLOC_PATH_MAX)
+/* The _USE_LFN option switches the LFN feature.
+/
+/ 0: Disable LFN feature. _MAX_LFN has no effect.
+/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
+/ 2: Enable LFN with dynamic working buffer on the STACK.
+/ 3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/ When enable the LFN feature, Unicode handling functions (option/unicode.c) must
+/ be added to the project. The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes.
+/ When use stack for the working buffer, take care on stack overflow. When use heap
+/ memory for the working buffer, memory management functions, ff_memalloc() and
+/ ff_memfree(), must be added to the project. */
+
+
+#define _LFN_UNICODE 0
+/* This option switches character encoding on the API. (0:ANSI/OEM or 1:Unicode)
+/ To use Unicode string for the path name, enable LFN feature and set _LFN_UNICODE
+/ to 1. This option also affects behavior of string I/O functions. */
+
+
+#define _STRF_ENCODE 3
+/* When _LFN_UNICODE is 1, this option selects the character encoding on the file to
+/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
+/
+/ 0: ANSI/OEM
+/ 1: UTF-16LE
+/ 2: UTF-16BE
+/ 3: UTF-8
+/
+/ When _LFN_UNICODE is 0, this option has no effect. */
+
+
+#define _FS_RPATH 2
+/* This option configures relative path feature.
+/
+/ 0: Disable relative path feature and remove related functions.
+/ 1: Enable relative path feature. f_chdir() and f_chdrive() are available.
+/ 2: f_getcwd() function is available in addition to 1.
+/
+/ Note that directory items read via f_readdir() are affected by this option. */
+
+
+/*---------------------------------------------------------------------------/
+/ Drive/Volume Configurations
+/---------------------------------------------------------------------------*/
+
+#define _VOLUMES 2
+/* Number of volumes (logical drives) to be used. */
+
+
+#define _STR_VOLUME_ID 0
+#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
+/* _STR_VOLUME_ID option switches string volume ID feature.
+/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
+/ number in the path name. _VOLUME_STRS defines the drive ID strings for each
+/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for
+/ the drive ID strings are: A-Z and 0-9. */
+
+
+#define _MULTI_PARTITION 0
+/* This option switches multi-partition feature. By default (0), each logical drive
+/ number is bound to the same physical drive number and only an FAT volume found on
+/ the physical drive will be mounted. When multi-partition feature is enabled (1),
+/ each logical drive number is bound to arbitrary physical drive and partition
+/ listed in the VolToPart[]. Also f_fdisk() funciton will be enabled. */
+
+
+#define _MIN_SS 512
+#define _MAX_SS 512
+/* These options configure the range of sector size to be supported. (512, 1024,
+/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and
+/ harddisk. But a larger value may be required for on-board flash memory and some
+/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
+/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the
+/ disk_ioctl() function. */
+
+
+#define _USE_TRIM 0
+/* This option switches ATA-TRIM feature. (0:Disable or 1:Enable)
+/ To enable Trim feature, also CTRL_TRIM command should be implemented to the
+/ disk_ioctl() function. */
+
+
+#define _FS_NOFSINFO 0
+/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
+/ option, and f_getfree() function at first time after volume mount will force
+/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
+/
+/ bit0=0: Use free cluster count in the FSINFO if available.
+/ bit0=1: Do not trust free cluster count in the FSINFO.
+/ bit1=0: Use last allocated cluster number in the FSINFO if available.
+/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
+*/
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/---------------------------------------------------------------------------*/
+
+#define _FS_NORTC 0
+#define _NORTC_MON 11
+#define _NORTC_MDAY 9
+#define _NORTC_YEAR 2014
+/* The _FS_NORTC option switches timestamp feature. If the system does not have
+/ an RTC function or valid timestamp is not needed, set _FS_NORTC to 1 to disable
+/ the timestamp feature. All objects modified by FatFs will have a fixed timestamp
+/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR.
+/ When timestamp feature is enabled (_FS_NORTC == 0), get_fattime() function need
+/ to be added to the project to read current time form RTC. _NORTC_MON,
+/ _NORTC_MDAY and _NORTC_YEAR have no effect.
+/ These options have no effect at read-only configuration (_FS_READONLY == 1). */
+
+
+#define _FS_LOCK 2
+/* The _FS_LOCK option switches file lock feature to control duplicated file open
+/ and illegal operation to open objects. This option must be 0 when _FS_READONLY
+/ is 1.
+/
+/ 0: Disable file lock feature. To avoid volume corruption, application program
+/ should avoid illegal open, remove and rename to the open objects.
+/ >0: Enable file lock feature. The value defines how many files/sub-directories
+/ can be opened simultaneously under file lock control. Note that the file
+/ lock feature is independent of re-entrancy. */
+
+
+#define _FS_REENTRANT 1
+#define _FS_TIMEOUT 2000
+#define _SYNC_t SemaphoreHandle_t
+/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs
+/ module itself. Note that regardless of this option, file access to different
+/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
+/ and f_fdisk() function, are always not re-entrant. Only file/directory access
+/ to the same volume is under control of this feature.
+/
+/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
+/ 1: Enable re-entrancy. Also user provided synchronization handlers,
+/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
+/ function, must be added to the project. Samples are available in
+/ option/syscall.c.
+/
+/ The _FS_TIMEOUT defines timeout period in unit of time tick.
+/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
+/ SemaphoreHandle_t and etc.. */
+
+
+#define _WORD_ACCESS 0
+/* The _WORD_ACCESS option is an only platform dependent option. It defines
+/ which access method is used to the word data on the FAT volume.
+/
+/ 0: Byte-by-byte access. Always compatible with all platforms.
+/ 1: Word access. Do not choose this unless under both the following conditions.
+/
+/ * Address misaligned memory access is always allowed to ALL instructions.
+/ * Byte order on the memory is little-endian.
+/
+/ If it is the case, _WORD_ACCESS can also be set to 1 to reduce code size.
+/ Following table shows allowable settings of some processor types.
+/
+/ ARM7TDMI 0 ColdFire 0 V850E 0
+/ Cortex-M3 0 Z80 0/1 V850ES 0/1
+/ Cortex-M0 0 x86 0/1 TLCS-870 0/1
+/ AVR 0/1 RX600(LE) 0/1 TLCS-900 0/1
+/ AVR32 0 RL78 0 R32C 0
+/ PIC18 0/1 SH-2 0 M16C 0/1
+/ PIC24 0 H8S 0 MSP430 0
+/ PIC32 0 H8/300H 0 8051 0/1
+*/
+
diff --git a/cc3200/fatfs/src/option/syscall.c b/cc3200/fatfs/src/option/syscall.c
new file mode 100644
index 0000000000..40c22cd755
--- /dev/null
+++ b/cc3200/fatfs/src/option/syscall.c
@@ -0,0 +1,156 @@
+/*------------------------------------------------------------------------*/
+/* Sample code of OS dependent controls for FatFs */
+/* (C)ChaN, 2014 */
+/*------------------------------------------------------------------------*/
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "ff.h"
+
+
+#if _FS_REENTRANT
+/*------------------------------------------------------------------------*/
+/* Create a Synchronization Object */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to create a new
+/ synchronization object, such as semaphore and mutex. When a 0 is returned,
+/ the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_cre_syncobj ( /* !=0:Function succeeded, ==0:Could not create due to any error */
+ BYTE vol, /* Corresponding logical drive being processed */
+ _SYNC_t *sobj /* Pointer to return the created sync object */
+)
+{
+ int ret;
+
+//
+// *sobj = CreateMutex(NULL, FALSE, NULL); /* Win32 */
+// ret = (int)(*sobj != INVALID_HANDLE_VALUE);
+
+// *sobj = SyncObjects[vol]; /* uITRON (give a static created sync object) */
+// ret = 1; /* The initial value of the semaphore must be 1. */
+
+// *sobj = OSMutexCreate(0, &err); /* uC/OS-II */
+// ret = (int)(err == OS_NO_ERR);
+
+ *sobj = xSemaphoreCreateMutex(); /* FreeRTOS */
+ ret = (int)(*sobj != NULL);
+
+ return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Delete a Synchronization Object */
+/*------------------------------------------------------------------------*/
+/* This function is called in f_mount() function to delete a synchronization
+/ object that created with ff_cre_syncobj function. When a 0 is returned,
+/ the f_mount() function fails with FR_INT_ERR.
+*/
+
+int ff_del_syncobj ( /* !=0:Function succeeded, ==0:Could not delete due to any error */
+ _SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
+)
+{
+ int ret;
+
+
+// ret = CloseHandle(sobj); /* Win32 */
+
+// ret = 1; /* uITRON (nothing to do) */
+
+// OSMutexDel(sobj, OS_DEL_ALWAYS, &err); /* uC/OS-II */
+// ret = (int)(err == OS_NO_ERR);
+
+ vSemaphoreDelete(sobj); /* FreeRTOS */
+ ret = 1;
+
+ return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Request Grant to Access the Volume */
+/*------------------------------------------------------------------------*/
+/* This function is called on entering file functions to lock the volume.
+/ When a 0 is returned, the file function fails with FR_TIMEOUT.
+*/
+
+int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
+ _SYNC_t sobj /* Sync object to wait */
+)
+{
+ int ret;
+
+// ret = (int)(WaitForSingleObject(sobj, _FS_TIMEOUT) == WAIT_OBJECT_0); /* Win32 */
+
+// ret = (int)(wai_sem(sobj) == E_OK); /* uITRON */
+
+// OSMutexPend(sobj, _FS_TIMEOUT, &err)); /* uC/OS-II */
+// ret = (int)(err == OS_NO_ERR);
+
+ ret = (int)(xSemaphoreTake(sobj, _FS_TIMEOUT) == pdTRUE); /* FreeRTOS */
+
+ return ret;
+}
+
+
+
+/*------------------------------------------------------------------------*/
+/* Release Grant to Access the Volume */
+/*------------------------------------------------------------------------*/
+/* This function is called on leaving file functions to unlock the volume.
+*/
+
+void ff_rel_grant (
+ _SYNC_t sobj /* Sync object to be signaled */
+)
+{
+// ReleaseMutex(sobj); /* Win32 */
+
+// sig_sem(sobj); /* uITRON */
+
+// OSMutexPost(sobj); /* uC/OS-II */
+
+ xSemaphoreGive(sobj); /* FreeRTOS */
+}
+
+#endif
+
+
+
+
+#if _USE_LFN == 3 /* LFN with a working buffer on the heap */
+/*------------------------------------------------------------------------*/
+/* Allocate a memory block */
+/*------------------------------------------------------------------------*/
+/* If a NULL is returned, the file function fails with FR_NOT_ENOUGH_CORE.
+*/
+
+void* ff_memalloc ( /* Returns pointer to the allocated memory block */
+ UINT msize /* Number of bytes to allocate */
+)
+{
+ return malloc(msize); /* Allocate a new memory block with POSIX API */
+}
+
+
+/*------------------------------------------------------------------------*/
+/* Free a memory block */
+/*------------------------------------------------------------------------*/
+
+void ff_memfree (
+ void* mblock /* Pointer to the memory block to free */
+)
+{
+ free(mblock); /* Discard the memory block with POSIX API */
+}
+
+#endif
diff --git a/cc3200/ftp/ftp.c b/cc3200/ftp/ftp.c
new file mode 100644
index 0000000000..79bf08c2e7
--- /dev/null
+++ b/cc3200/ftp/ftp.c
@@ -0,0 +1,1062 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "osi.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "pybrtc.h"
+#include "ftp.h"
+#include "simplelink.h"
+#include "modwlan.h"
+#include "modutime.h"
+#include "debug.h"
+#include "serverstask.h"
+#include "ff.h"
+#include "fifo.h"
+#include "socketfifo.h"
+#include "diskio.h"
+#include "sd_diskio.h"
+#include "updater.h"
+
+
+/******************************************************************************
+ DEFINE PRIVATE CONSTANTS
+ ******************************************************************************/
+#define FTP_CMD_PORT 21
+#define FTP_ACTIVE_DATA_PORT 20
+#define FTP_PASIVE_DATA_PORT 2024
+#define FTP_BUFFER_SIZE 512
+#define FTP_TX_RETRIES_MAX 25
+#define FTP_CMD_SIZE_MAX 6
+#define FTP_CMD_CLIENTS_MAX 1
+#define FTP_DATA_CLIENTS_MAX 1
+#define FTP_MAX_PARAM_SIZE (MICROPY_ALLOC_PATH_MAX + 1)
+#define FTP_UNIX_TIME_20000101 946684800
+#define FTP_UNIX_TIME_20150101 1420070400
+#define FTP_UNIX_SECONDS_180_DAYS 15552000
+#define FTP_DATA_TIMEOUT_MS 5000 // 5 seconds
+#define FTP_CMD_TIMEOUT_MS 120000 // 2 minutes
+#define FTP_SOCKETFIFO_ELEMENTS_MAX 4
+#define FTP_CYCLE_TIME_MS (SERVERS_CYCLE_TIME_MS * 2)
+
+/******************************************************************************
+ DEFINE PRIVATE TYPES
+ ******************************************************************************/
+typedef enum {
+ E_FTP_RESULT_OK = 0,
+ E_FTP_RESULT_CONTINUE,
+ E_FTP_RESULT_FAILED
+} ftp_result_t;
+
+typedef enum {
+ E_FTP_STE_DISABLED = 0,
+ E_FTP_STE_START,
+ E_FTP_STE_READY,
+ E_FTP_STE_END_TRANSFER,
+ E_FTP_STE_CONTINUE_LISTING,
+ E_FTP_STE_CONTINUE_FILE_TX,
+ E_FTP_STE_CONTINUE_FILE_RX
+} ftp_state_t;
+
+typedef enum {
+ E_FTP_STE_SUB_DISCONNECTED = 0,
+ E_FTP_STE_SUB_LISTEN_FOR_DATA,
+ E_FTP_STE_SUB_DATA_CONNECTED
+} ftp_data_substate_t;
+
+typedef union {
+ ftp_data_substate_t data;
+} ftp_substate_t;
+
+typedef struct {
+ bool uservalid : 1;
+ bool passvalid : 1;
+}ftp_loggin_t;
+
+typedef enum {
+ E_FTP_NOTHING_OPEN = 0,
+ E_FTP_FILE_OPEN,
+ E_FTP_DIR_OPEN
+} ftp_e_open_t;
+
+typedef enum {
+ E_FTP_CLOSE_NONE = 0,
+ E_FTP_CLOSE_DATA,
+ E_FTP_CLOSE_CMD_AND_DATA,
+} ftp_e_closesocket_t;
+
+typedef struct {
+ uint8_t *dBuffer;
+ union {
+ DIR dp;
+ FIL fp;
+ };
+ int16_t lc_sd;
+ int16_t ld_sd;
+ int16_t c_sd;
+ int16_t ctimeout;
+ int16_t d_sd;
+ int16_t dtimeout;
+ ftp_state_t state;
+ ftp_substate_t substate;
+ uint8_t txRetries;
+ uint8_t logginRetries;
+ ftp_loggin_t loggin;
+ uint8_t e_open;
+ bool closechild;
+ bool enabled;
+ bool swupdating;
+
+} ftp_data_t;
+
+typedef struct {
+ char * cmd;
+}ftp_cmd_t;
+
+typedef struct {
+ char * month;
+}ftp_month_t;
+
+typedef enum {
+ E_FTP_CMD_NOT_SUPPORTED = -1,
+ E_FTP_CMD_FEAT = 0,
+ E_FTP_CMD_SYST,
+ E_FTP_CMD_CDUP,
+ E_FTP_CMD_CWD,
+ E_FTP_CMD_PWD,
+ E_FTP_CMD_XPWD,
+ E_FTP_CMD_SIZE,
+ E_FTP_CMD_MDTM,
+ E_FTP_CMD_TYPE,
+ E_FTP_CMD_USER,
+ E_FTP_CMD_PASS,
+ E_FTP_CMD_PASV,
+ E_FTP_CMD_LIST,
+ E_FTP_CMD_RETR,
+ E_FTP_CMD_STOR,
+ E_FTP_CMD_DELE,
+ E_FTP_CMD_RMD,
+ E_FTP_CMD_MKD,
+ E_FTP_CMD_RNFR,
+ E_FTP_CMD_RNTO,
+ E_FTP_CMD_NOOP,
+ E_FTP_CMD_QUIT,
+ E_FTP_NUM_FTP_CMDS
+}ftp_cmd_index_t;
+
+/******************************************************************************
+ DECLARE PRIVATE DATA
+ ******************************************************************************/
+static ftp_data_t ftp_data;
+static char *ftp_path;
+static char *ftp_scratch_buffer;
+static char *ftp_cmd_buffer;
+static const ftp_cmd_t ftp_cmd_table[] = { { "FEAT" }, { "SYST" }, { "CDUP" }, { "CWD" },
+ { "PWD" }, { "XPWD" }, { "SIZE" }, { "MDTM" },
+ { "TYPE" }, { "USER" }, { "PASS" }, { "PASV" },
+ { "LIST" }, { "RETR" }, { "STOR" }, { "DELE" },
+ { "RMD" }, { "MKD" }, { "RNFR" }, { "RNTO" },
+ { "NOOP" }, { "QUIT" } };
+
+static const ftp_month_t ftp_month[] = { { "Jan" }, { "Feb" }, { "Mar" }, { "Apr" },
+ { "May" }, { "Jun" }, { "Jul" }, { "Ago" },
+ { "Sep" }, { "Oct" }, { "Nov" }, { "Dec" } };
+
+static SocketFifoElement_t *ftp_fifoelements;
+static FIFO_t ftp_socketfifo;
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+static void ftp_wait_for_enabled (void);
+static bool ftp_create_listening_socket (_i16 *sd, _u16 port, _u8 backlog);
+static ftp_result_t ftp_wait_for_connection (_i16 l_sd, _i16 *n_sd);
+static ftp_result_t ftp_send_non_blocking (_i16 sd, void *data, _i16 Len);
+static void ftp_send_reply (_u16 status, char *message);
+static void ftp_send_data (_u32 datasize);
+static void ftp_send_from_fifo (void);
+static ftp_result_t ftp_recv_non_blocking (_i16 sd, void *buff, _i16 Maxlen, _i32 *rxLen);
+static void ftp_process_cmd (void);
+static void ftp_close_files (void);
+static void ftp_close_filesystem_on_error (void);
+static void ftp_close_cmd_data (void);
+static void ftp_reset (void);
+static ftp_cmd_index_t ftp_pop_command (char **str);
+static void ftp_pop_param (char **str, char *param);
+static int ftp_print_eplf_item (char *dest, uint32_t destsize, FILINFO *fno);
+static int ftp_print_eplf_drive (char *dest, uint32_t destsize, char *name);
+static bool ftp_open_file (const char *path, int mode);
+static ftp_result_t ftp_read_file (char *filebuf, uint32_t desiredsize, uint32_t *actualsize);
+static ftp_result_t ftp_write_file (char *filebuf, uint32_t size);
+static ftp_result_t ftp_open_dir_for_listing (const char *path, char *list, uint32_t maxlistsize, uint32_t *listsize);
+static ftp_result_t ftp_list_dir (char *list, uint32_t maxlistsize, uint32_t *listsize);
+static void ftp_open_child (char *pwd, char *dir);
+static void ftp_close_child (char *pwd);
+static void ftp_return_to_previous_path (char *pwd, char *dir);
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+void ftp_init (void) {
+ // Allocate memory for the data buffer, and the file system structs (from the RTOS heap)
+ ASSERT ((ftp_data.dBuffer = mem_Malloc(FTP_BUFFER_SIZE)) != NULL);
+ ASSERT ((ftp_path = mem_Malloc(FTP_MAX_PARAM_SIZE)) != NULL);
+ ASSERT ((ftp_scratch_buffer = mem_Malloc(FTP_MAX_PARAM_SIZE)) != NULL);
+ ASSERT ((ftp_cmd_buffer = mem_Malloc(FTP_MAX_PARAM_SIZE + FTP_CMD_SIZE_MAX)) != NULL);
+ ASSERT ((ftp_fifoelements = mem_Malloc(FTP_SOCKETFIFO_ELEMENTS_MAX * sizeof(SocketFifoElement_t))) != NULL);
+ SOCKETFIFO_Init (&ftp_socketfifo, (void *)ftp_fifoelements, FTP_SOCKETFIFO_ELEMENTS_MAX);
+ ftp_data.c_sd = -1;
+ ftp_data.d_sd = -1;
+ ftp_data.lc_sd = -1;
+ ftp_data.ld_sd = -1;
+ ftp_data.e_open = E_FTP_NOTHING_OPEN;
+ ftp_data.state = E_FTP_STE_DISABLED;
+ ftp_data.substate.data = E_FTP_STE_SUB_DISCONNECTED;
+ ftp_data.swupdating = false;
+}
+
+void ftp_run (void) {
+ switch (ftp_data.state) {
+ case E_FTP_STE_DISABLED:
+ ftp_wait_for_enabled();
+ break;
+ case E_FTP_STE_START:
+ if (ftp_create_listening_socket(&ftp_data.lc_sd, FTP_CMD_PORT, FTP_CMD_CLIENTS_MAX )) {
+ ftp_data.state = E_FTP_STE_READY;
+ }
+ break;
+ case E_FTP_STE_READY:
+ if (ftp_data.c_sd < 0 && ftp_data.substate.data == E_FTP_STE_SUB_DISCONNECTED) {
+ if (E_FTP_RESULT_OK == ftp_wait_for_connection(ftp_data.lc_sd, &ftp_data.c_sd)) {
+ ftp_data.txRetries = 0;
+ ftp_data.logginRetries = 0;
+ ftp_data.ctimeout = 0;
+ ftp_data.loggin.uservalid = false;
+ ftp_data.loggin.passvalid = false;
+ strcpy (ftp_path, "/");
+ ftp_send_reply (220, "Micropython FTP Server");
+ break;
+ }
+ }
+ if (SOCKETFIFO_IsEmpty()) {
+ if (ftp_data.c_sd > 0 && ftp_data.substate.data != E_FTP_STE_SUB_LISTEN_FOR_DATA) {
+ ftp_process_cmd();
+ if (ftp_data.state != E_FTP_STE_READY) {
+ break;
+ }
+ }
+ }
+ break;
+ case E_FTP_STE_END_TRANSFER:
+ break;
+ case E_FTP_STE_CONTINUE_LISTING:
+ // go on with listing only if the transmit buffer is empty
+ if (SOCKETFIFO_IsEmpty()) {
+ uint32_t listsize;
+ ftp_list_dir((char *)ftp_data.dBuffer, FTP_BUFFER_SIZE, &listsize);
+ if (listsize > 0) {
+ ftp_send_data(listsize);
+ }
+ else {
+ ftp_send_reply(226, NULL);
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ }
+ ftp_data.ctimeout = 0;
+ }
+ break;
+ case E_FTP_STE_CONTINUE_FILE_TX:
+ // read the next block from the file only if the previous one has been sent
+ if (SOCKETFIFO_IsEmpty()) {
+ uint32_t readsize;
+ ftp_result_t result;
+ result = ftp_read_file ((char *)ftp_data.dBuffer, FTP_BUFFER_SIZE, &readsize);
+ if (readsize > 0 && result != E_FTP_RESULT_FAILED) {
+ ftp_send_data(readsize);
+ ftp_data.ctimeout = 0;
+ if (result == E_FTP_RESULT_OK) {
+ ftp_send_reply(226, NULL);
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ }
+ }
+ else {
+ ftp_send_reply(451, NULL);
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ }
+ }
+ break;
+ case E_FTP_STE_CONTINUE_FILE_RX:
+ if (SOCKETFIFO_IsEmpty()) {
+ _i32 len;
+ ftp_result_t result;
+ if (E_FTP_RESULT_OK == (result = ftp_recv_non_blocking(ftp_data.d_sd, ftp_data.dBuffer, FTP_BUFFER_SIZE, &len))) {
+ ftp_data.dtimeout = 0;
+ ftp_data.ctimeout = 0;
+ // its a software update
+ if (ftp_data.swupdating) {
+ if (updater_write(ftp_data.dBuffer, len)) {
+ break;
+ }
+ }
+ // user file being received
+ else if (E_FTP_RESULT_OK == ftp_write_file ((char *)ftp_data.dBuffer, len)) {
+ break;
+ }
+ ftp_send_reply(451, NULL);
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ }
+ else if (result == E_FTP_RESULT_CONTINUE) {
+ if (ftp_data.dtimeout++ > FTP_DATA_TIMEOUT_MS / FTP_CYCLE_TIME_MS) {
+ ftp_close_files();
+ ftp_send_reply(426, NULL);
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ }
+ }
+ else {
+ if (ftp_data.swupdating) {
+ ftp_data.swupdating = false;
+ updater_finnish();
+ }
+ ftp_close_files();
+ ftp_send_reply(226, NULL);
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ switch (ftp_data.substate.data) {
+ case E_FTP_STE_SUB_DISCONNECTED:
+ break;
+ case E_FTP_STE_SUB_LISTEN_FOR_DATA:
+ if (E_FTP_RESULT_OK == ftp_wait_for_connection(ftp_data.ld_sd, &ftp_data.d_sd)) {
+ ftp_data.dtimeout = 0;
+ ftp_data.substate.data = E_FTP_STE_SUB_DATA_CONNECTED;
+ }
+ else if (ftp_data.dtimeout++ > FTP_DATA_TIMEOUT_MS / FTP_CYCLE_TIME_MS) {
+ ftp_data.dtimeout = 0;
+ // close the listening socket
+ servers_close_socket(&ftp_data.ld_sd);
+ ftp_data.substate.data = E_FTP_STE_SUB_DISCONNECTED;
+ }
+ break;
+ case E_FTP_STE_SUB_DATA_CONNECTED:
+ if (ftp_data.state == E_FTP_STE_READY && ftp_data.dtimeout++ > FTP_DATA_TIMEOUT_MS / FTP_CYCLE_TIME_MS) {
+ // close the listening and the data socket
+ servers_close_socket(&ftp_data.ld_sd);
+ servers_close_socket(&ftp_data.d_sd);
+ ftp_close_filesystem_on_error ();
+ ftp_data.substate.data = E_FTP_STE_SUB_DISCONNECTED;
+ }
+ break;
+ default:
+ break;
+ }
+
+ // send data pending in the queue
+ ftp_send_from_fifo();
+
+ // check the state of the data sockets
+ if (ftp_data.d_sd < 0 && (ftp_data.state > E_FTP_STE_READY)) {
+ ftp_data.substate.data = E_FTP_STE_SUB_DISCONNECTED;
+ ftp_data.state = E_FTP_STE_READY;
+ }
+}
+
+void ftp_enable (void) {
+ ftp_data.enabled = true;
+}
+
+void ftp_disable (void) {
+ ftp_reset();
+ ftp_data.enabled = false;
+ ftp_data.state = E_FTP_STE_DISABLED;
+}
+
+/******************************************************************************
+ DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
+static void ftp_wait_for_enabled (void) {
+ // Check if the telnet service has been enabled
+ if (ftp_data.enabled) {
+ ftp_data.state = E_FTP_STE_START;
+ }
+}
+
+static bool ftp_create_listening_socket (_i16 *sd, _u16 port, _u8 backlog) {
+ SlSockNonblocking_t nonBlockingOption;
+ sockaddr_in sServerAddress;
+ _i16 _sd;
+ _i16 result;
+
+ // Open a socket for ftp data listen
+ ASSERT ((*sd = sl_Socket(AF_INET, SOCK_STREAM, IPPROTO_IP)) > 0);
+ _sd = *sd;
+
+ if (_sd > 0) {
+ // Enable non-blocking mode
+ nonBlockingOption.NonblockingEnabled = 1;
+ ASSERT (sl_SetSockOpt(_sd, SOL_SOCKET, SL_SO_NONBLOCKING, &nonBlockingOption, sizeof(nonBlockingOption)) == SL_SOC_OK);
+
+ // Bind the socket to a port number
+ sServerAddress.sin_family = AF_INET;
+ sServerAddress.sin_addr.s_addr = htonl(INADDR_ANY);
+ sServerAddress.sin_port = htons(port);
+
+ ASSERT (sl_Bind(_sd, (const SlSockAddr_t *)&sServerAddress, sizeof(sServerAddress)) == SL_SOC_OK);
+
+ // Start listening
+ ASSERT ((result = sl_Listen (_sd, backlog)) == SL_SOC_OK);
+
+ return (result == SL_SOC_OK) ? true : false;
+ }
+ return false;
+}
+
+static ftp_result_t ftp_wait_for_connection (_i16 l_sd, _i16 *n_sd) {
+ sockaddr_in sClientAddress;
+ SlSocklen_t in_addrSize;
+
+ // accepts a connection from a TCP client, if there is any, otherwise returns SL_EAGAIN
+ *n_sd = sl_Accept(l_sd, (SlSockAddr_t *)&sClientAddress, (SlSocklen_t *)&in_addrSize);
+ _i16 _sd = *n_sd;
+ if (_sd == SL_EAGAIN) {
+ return E_FTP_RESULT_CONTINUE;
+ }
+ else if (_sd < 0) {
+ // error
+ ftp_reset();
+ return E_FTP_RESULT_FAILED;
+ }
+
+ // client connected, so go on
+ return E_FTP_RESULT_OK;
+}
+
+static ftp_result_t ftp_send_non_blocking (_i16 sd, void *data, _i16 Len) {
+ int16_t result = sl_Send(sd, data, Len, 0);
+
+ if (result > 0) {
+ ftp_data.txRetries = 0;
+ return E_FTP_RESULT_OK;
+ }
+ else if ((FTP_TX_RETRIES_MAX >= ++ftp_data.txRetries) && (result == SL_EAGAIN)) {
+ return E_FTP_RESULT_CONTINUE;
+ }
+ else {
+ // error
+ ftp_reset();
+ return E_FTP_RESULT_FAILED;
+ }
+}
+
+static void ftp_send_reply (_u16 status, char *message) {
+ SocketFifoElement_t fifoelement;
+ if (!message) {
+ message = "";
+ }
+ snprintf((char *)ftp_cmd_buffer, 4, "%u", status);
+ strcat ((char *)ftp_cmd_buffer, " ");
+ strcat ((char *)ftp_cmd_buffer, message);
+ strcat ((char *)ftp_cmd_buffer, "\r\n");
+ fifoelement.sd = &ftp_data.c_sd;
+ fifoelement.datasize = strlen((char *)ftp_cmd_buffer);
+ fifoelement.data = mem_Malloc(fifoelement.datasize);
+ if (status == 221) {
+ fifoelement.closesockets = E_FTP_CLOSE_CMD_AND_DATA;
+ }
+ else if (status == 426 || status == 451 || status == 550) {
+ fifoelement.closesockets = E_FTP_CLOSE_DATA;
+ }
+ else {
+ fifoelement.closesockets = E_FTP_CLOSE_NONE;
+ }
+ fifoelement.freedata = true;
+ if (fifoelement.data) {
+ memcpy (fifoelement.data, ftp_cmd_buffer, fifoelement.datasize);
+ if (!SOCKETFIFO_Push (&fifoelement)) {
+ mem_Free(fifoelement.data);
+ }
+ }
+}
+
+static void ftp_send_data (_u32 datasize) {
+ SocketFifoElement_t fifoelement;
+
+ fifoelement.data = ftp_data.dBuffer;
+ fifoelement.datasize = datasize;
+ fifoelement.sd = &ftp_data.d_sd;
+ fifoelement.closesockets = E_FTP_CLOSE_NONE;
+ fifoelement.freedata = false;
+ SOCKETFIFO_Push (&fifoelement);
+}
+
+static void ftp_send_from_fifo (void) {
+ SocketFifoElement_t fifoelement;
+ if (SOCKETFIFO_Peek (&fifoelement)) {
+ _i16 _sd = *fifoelement.sd;
+ if (_sd > 0) {
+ if (E_FTP_RESULT_OK == ftp_send_non_blocking (_sd, fifoelement.data, fifoelement.datasize)) {
+ SOCKETFIFO_Pop (&fifoelement);
+ if (fifoelement.closesockets != E_FTP_CLOSE_NONE) {
+ servers_close_socket(&ftp_data.d_sd);
+ if (fifoelement.closesockets == E_FTP_CLOSE_CMD_AND_DATA) {
+ servers_close_socket(&ftp_data.ld_sd);
+ // this one is the command socket
+ servers_close_socket(fifoelement.sd);
+ ftp_data.substate.data = E_FTP_STE_SUB_DISCONNECTED;
+ }
+ ftp_close_filesystem_on_error();
+ }
+ if (fifoelement.freedata) {
+ mem_Free(fifoelement.data);
+ }
+ }
+ }
+ // socket closed, remove from the queue
+ else {
+ SOCKETFIFO_Pop (&fifoelement);
+ if (fifoelement.freedata) {
+ mem_Free(fifoelement.data);
+ }
+ }
+ }
+ else if (ftp_data.state == E_FTP_STE_END_TRANSFER && (ftp_data.d_sd > 0)) {
+ // close the listening and the data sockets
+ servers_close_socket(&ftp_data.ld_sd);
+ servers_close_socket(&ftp_data.d_sd);
+ if (ftp_data.swupdating) {
+ ftp_data.swupdating = false;
+ }
+ }
+}
+
+static ftp_result_t ftp_recv_non_blocking (_i16 sd, void *buff, _i16 Maxlen, _i32 *rxLen) {
+ *rxLen = sl_Recv(sd, buff, Maxlen, 0);
+
+ if (*rxLen > 0) {
+ return E_FTP_RESULT_OK;
+ }
+ else if (*rxLen != SL_EAGAIN) {
+ // error
+ return E_FTP_RESULT_FAILED;
+ }
+ return E_FTP_RESULT_CONTINUE;
+}
+
+static void ftp_get_param_and_open_child (char **bufptr) {
+ ftp_pop_param (bufptr, ftp_scratch_buffer);
+ ftp_open_child (ftp_path, ftp_scratch_buffer);
+ ftp_data.closechild = true;
+}
+
+static void ftp_process_cmd (void) {
+ _i32 len;
+ char *bufptr = (char *)ftp_cmd_buffer;
+ ftp_result_t result;
+ uint32_t listsize;
+ FILINFO fno;
+ FRESULT fres;
+
+ ftp_data.closechild = false;
+ // also use the reply buffer to receive new commands
+ if (E_FTP_RESULT_OK == (result = ftp_recv_non_blocking(ftp_data.c_sd, ftp_cmd_buffer, FTP_BUFFER_SIZE, &len))) {
+ // bufptr is moved as commands are being popped
+ ftp_cmd_index_t cmd = ftp_pop_command(&bufptr);
+ if (!ftp_data.loggin.passvalid && (cmd != E_FTP_CMD_USER && cmd != E_FTP_CMD_PASS && cmd != E_FTP_CMD_QUIT)) {
+ ftp_send_reply(332, NULL);
+ return;
+ }
+ switch (cmd) {
+ case E_FTP_CMD_FEAT:
+ ftp_send_reply(211, "no-features");
+ break;
+ case E_FTP_CMD_SYST:
+ ftp_send_reply(215, "UNIX Type: L8");
+ break;
+ case E_FTP_CMD_CDUP:
+ ftp_close_child(ftp_path);
+ ftp_send_reply(250, NULL);
+ break;
+ case E_FTP_CMD_CWD:
+ {
+ fres = FR_NO_PATH;
+ ftp_pop_param (&bufptr, ftp_scratch_buffer);
+ ftp_open_child (ftp_path, ftp_scratch_buffer);
+ if ((ftp_path[0] == '/' && ftp_path[1] == '\0') || ((fres = f_opendir (&ftp_data.dp, ftp_path)) == FR_OK)) {
+ if (fres == FR_OK) {
+ f_closedir(&ftp_data.dp);
+ }
+ ftp_send_reply(250, NULL);
+ }
+ else {
+ ftp_close_child (ftp_path);
+ ftp_send_reply(550, NULL);
+ }
+ }
+ break;
+ case E_FTP_CMD_PWD:
+ case E_FTP_CMD_XPWD:
+ ftp_send_reply(257, ftp_path);
+ break;
+ case E_FTP_CMD_SIZE:
+ {
+ ftp_get_param_and_open_child (&bufptr);
+ if (FR_OK == f_stat (ftp_path, &fno)) {
+ // send the size
+ snprintf((char *)ftp_data.dBuffer, FTP_BUFFER_SIZE, "%u", (_u32)fno.fsize);
+ ftp_send_reply(213, (char *)ftp_data.dBuffer);
+ }
+ else {
+ ftp_send_reply(550, NULL);
+ }
+ }
+ break;
+ case E_FTP_CMD_MDTM:
+ ftp_get_param_and_open_child (&bufptr);
+ if (FR_OK == f_stat (ftp_path, &fno)) {
+ // send the last modified time
+ snprintf((char *)ftp_data.dBuffer, FTP_BUFFER_SIZE, "%u%02u%02u%02u%02u%02u",
+ 1980 + ((fno.fdate >> 9) & 0x7f), (fno.fdate >> 5) & 0x0f,
+ fno.fdate & 0x1f, (fno.ftime >> 11) & 0x1f,
+ (fno.ftime >> 5) & 0x3f, 2 * (fno.ftime & 0x1f));
+ ftp_send_reply(213, (char *)ftp_data.dBuffer);
+ }
+ else {
+ ftp_send_reply(550, NULL);
+ }
+ break;
+ case E_FTP_CMD_TYPE:
+ ftp_send_reply(200, NULL);
+ break;
+ case E_FTP_CMD_USER:
+ ftp_pop_param (&bufptr, ftp_scratch_buffer);
+ if (!memcmp(ftp_scratch_buffer, servers_user, MAX(strlen(ftp_scratch_buffer), strlen(servers_user)))) {
+ ftp_data.loggin.uservalid = true;
+ }
+ ftp_send_reply(331, NULL);
+ break;
+ case E_FTP_CMD_PASS:
+ ftp_pop_param (&bufptr, ftp_scratch_buffer);
+ if (!memcmp(ftp_scratch_buffer, servers_pass, MAX(strlen(ftp_scratch_buffer), strlen(servers_pass))) &&
+ ftp_data.loggin.uservalid) {
+ ftp_data.loggin.passvalid = true;
+ ftp_send_reply(230, NULL);
+ }
+ else {
+ ftp_send_reply(530, NULL);
+ }
+ break;
+ case E_FTP_CMD_PASV:
+ {
+ // some servers (e.g. google chrome) send PASV several times very quickly
+ servers_close_socket(&ftp_data.d_sd);
+ ftp_data.substate.data = E_FTP_STE_SUB_DISCONNECTED;
+ bool socketcreated = true;
+ if (ftp_data.ld_sd < 0) {
+ socketcreated = ftp_create_listening_socket(&ftp_data.ld_sd, FTP_PASIVE_DATA_PORT, FTP_DATA_CLIENTS_MAX);
+ }
+ if (socketcreated) {
+ uint32_t ip;
+ uint8_t *pip = (uint8_t *)&ip;
+ ftp_data.dtimeout = 0;
+ wlan_get_ip(&ip);
+ snprintf((char *)ftp_data.dBuffer, FTP_BUFFER_SIZE, "(%u,%u,%u,%u,%u,%u)",
+ pip[0], pip[1], pip[2], pip[3], (FTP_PASIVE_DATA_PORT >> 8), (FTP_PASIVE_DATA_PORT & 0xFF));
+ ftp_data.substate.data = E_FTP_STE_SUB_LISTEN_FOR_DATA;
+ ftp_send_reply(227, (char *)ftp_data.dBuffer);
+ }
+ else {
+ ftp_send_reply(425, NULL);
+ }
+ }
+ break;
+ case E_FTP_CMD_LIST:
+ if ((result = ftp_open_dir_for_listing(ftp_path, (char *)ftp_data.dBuffer, FTP_BUFFER_SIZE, &listsize)) == E_FTP_RESULT_OK) {
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ ftp_send_reply(150, NULL);
+ ftp_send_data(listsize);
+ ftp_send_reply(226, NULL);
+ }
+ else if (result == E_FTP_RESULT_CONTINUE) {
+ ftp_data.state = E_FTP_STE_CONTINUE_LISTING;
+ ftp_send_reply(150, NULL);
+ }
+ else {
+ ftp_send_reply(550, NULL);
+ }
+ break;
+ case E_FTP_CMD_RETR:
+ ftp_get_param_and_open_child (&bufptr);
+ if (ftp_open_file (ftp_path, FA_READ)) {
+ ftp_data.state = E_FTP_STE_CONTINUE_FILE_TX;
+ ftp_send_reply(150, NULL);
+ }
+ else {
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ ftp_send_reply(550, NULL);
+ }
+ break;
+ case E_FTP_CMD_STOR:
+ ftp_get_param_and_open_child (&bufptr);
+ // first check if a software update is being requested
+ if (updater_check_path (ftp_path)) {
+ // start by erasing the previous status file
+ // must be done before starting the updater
+ f_unlink(ftp_path);
+ if (updater_start()) {
+ ftp_data.swupdating = true;
+ ftp_data.state = E_FTP_STE_CONTINUE_FILE_RX;
+ ftp_send_reply(150, NULL);
+ }
+ else {
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ ftp_send_reply(550, NULL);
+ }
+ }
+ else {
+ if (ftp_open_file (ftp_path, FA_WRITE | FA_CREATE_ALWAYS)) {
+ ftp_data.state = E_FTP_STE_CONTINUE_FILE_RX;
+ ftp_send_reply(150, NULL);
+ }
+ else {
+ ftp_data.state = E_FTP_STE_END_TRANSFER;
+ ftp_send_reply(550, NULL);
+ }
+ }
+ break;
+ case E_FTP_CMD_DELE:
+ case E_FTP_CMD_RMD:
+ ftp_get_param_and_open_child (&bufptr);
+ if (FR_OK == f_unlink(ftp_path)) {
+ ftp_send_reply(250, NULL);
+ }
+ else {
+ ftp_send_reply(550, NULL);
+ }
+ break;
+ case E_FTP_CMD_MKD:
+ ftp_get_param_and_open_child (&bufptr);
+ if (FR_OK == f_mkdir(ftp_path)) {
+ ftp_send_reply(250, NULL);
+ }
+ else {
+ ftp_send_reply(550, NULL);
+ }
+ break;
+ case E_FTP_CMD_RNFR:
+ ftp_get_param_and_open_child (&bufptr);
+ if (FR_OK == f_stat (ftp_path, &fno)) {
+ ftp_send_reply(350, NULL);
+ // save the current path
+ strcpy ((char *)ftp_data.dBuffer, ftp_path);
+ }
+ else {
+ ftp_send_reply(550, NULL);
+ }
+ break;
+ case E_FTP_CMD_RNTO:
+ ftp_get_param_and_open_child (&bufptr);
+ // old path was saved in the data buffer
+ if (FR_OK == (fres = f_rename ((char *)ftp_data.dBuffer, ftp_path))) {
+ ftp_send_reply(250, NULL);
+ }
+ else {
+ ftp_send_reply(550, NULL);
+ }
+ break;
+ case E_FTP_CMD_NOOP:
+ ftp_send_reply(200, NULL);
+ break;
+ case E_FTP_CMD_QUIT:
+ ftp_send_reply(221, NULL);
+ break;
+ default:
+ // command not implemented
+ ftp_send_reply(502, NULL);
+ break;
+ }
+
+ if (ftp_data.closechild) {
+ ftp_return_to_previous_path(ftp_path, ftp_scratch_buffer);
+ }
+ }
+ else if (result == E_FTP_RESULT_CONTINUE) {
+ if (ftp_data.ctimeout++ > (FTP_CMD_TIMEOUT_MS / FTP_CYCLE_TIME_MS)) {
+ ftp_send_reply(221, NULL);
+ }
+ }
+ else {
+ ftp_close_cmd_data ();
+ }
+}
+
+static void ftp_close_files (void) {
+ if (ftp_data.e_open == E_FTP_FILE_OPEN) {
+ f_close(&ftp_data.fp);
+ }
+ else if (ftp_data.e_open == E_FTP_DIR_OPEN) {
+ f_closedir(&ftp_data.dp);
+ }
+ ftp_data.e_open = E_FTP_NOTHING_OPEN;
+}
+
+static void ftp_close_filesystem_on_error (void) {
+ ftp_close_files();
+ if (ftp_data.swupdating) {
+ updater_finnish ();
+ ftp_data.swupdating = false;
+ }
+}
+
+static void ftp_close_cmd_data (void) {
+ servers_close_socket(&ftp_data.c_sd);
+ servers_close_socket(&ftp_data.d_sd);
+ ftp_close_filesystem_on_error ();
+}
+
+static void ftp_reset (void) {
+ // close all connections and start all over again
+ servers_close_socket(&ftp_data.lc_sd);
+ servers_close_socket(&ftp_data.ld_sd);
+ ftp_close_cmd_data();
+ ftp_data.state = E_FTP_STE_START;
+ ftp_data.substate.data = E_FTP_STE_SUB_DISCONNECTED;
+ SOCKETFIFO_Flush();
+}
+
+static ftp_cmd_index_t ftp_pop_command (char **str) {
+ char _cmd[FTP_CMD_SIZE_MAX];
+ ftp_pop_param (str, _cmd);
+ stoupper (_cmd);
+ for (ftp_cmd_index_t i = 0; i < E_FTP_NUM_FTP_CMDS; i++) {
+ if (!strcmp (_cmd, ftp_cmd_table[i].cmd)) {
+ // move one step further to skip the space
+ (*str)++;
+ return i;
+ }
+ }
+ return E_FTP_CMD_NOT_SUPPORTED;
+}
+
+static void ftp_pop_param (char **str, char *param) {
+ while (**str != ' ' && **str != '\r' && **str != '\n' && **str != '\0') {
+ *param++ = **str;
+ (*str)++;
+ }
+ *param = '\0';
+}
+
+static int ftp_print_eplf_item (char *dest, uint32_t destsize, FILINFO *fno) {
+
+ char *type = (fno->fattrib & AM_DIR) ? "d" : "-";
+ uint32_t tseconds;
+ uint16_t mseconds;
+ uint mindex = (((fno->fdate >> 5) & 0x0f) > 0) ? (((fno->fdate >> 5) & 0x0f) - 1) : 0;
+ uint day = ((fno->fdate & 0x1f) > 0) ? (fno->fdate & 0x1f) : 1;
+ uint fseconds = mod_time_seconds_since_2000(1980 + ((fno->fdate >> 9) & 0x7f),
+ (fno->fdate >> 5) & 0x0f,
+ fno->fdate & 0x1f,
+ (fno->ftime >> 11) & 0x1f,
+ (fno->ftime >> 5) & 0x3f,
+ 2 * (fno->ftime & 0x1f));
+ MAP_PRCMRTCGet(&tseconds, &mseconds);
+ if (FTP_UNIX_SECONDS_180_DAYS < tseconds - fseconds) {
+ return snprintf(dest, destsize, "%srw-rw-r-- 1 root root %9u %s %2u %5u %s\r\n",
+ type, (_u32)fno->fsize, ftp_month[mindex].month, day,
+ 1980 + ((fno->fdate >> 9) & 0x7f), fno->fname);
+ }
+ else {
+ return snprintf(dest, destsize, "%srw-rw-r-- 1 root root %9u %s %2u %02u:%02u %s\r\n",
+ type, (_u32)fno->fsize, ftp_month[mindex].month, day,
+ (fno->ftime >> 11) & 0x1f, (fno->ftime >> 5) & 0x3f, fno->fname);
+ }
+}
+
+static int ftp_print_eplf_drive (char *dest, uint32_t destsize, char *name) {
+ mod_struct_time tm;
+ uint32_t tseconds;
+ uint16_t mseconds;
+ char *type = "d";
+
+ mod_time_seconds_since_2000_to_struct_time((FTP_UNIX_TIME_20150101 - FTP_UNIX_TIME_20000101), &tm);
+
+ MAP_PRCMRTCGet(&tseconds, &mseconds);
+ if (FTP_UNIX_SECONDS_180_DAYS < tseconds - (FTP_UNIX_TIME_20150101 - FTP_UNIX_TIME_20000101)) {
+ return snprintf(dest, destsize, "%srw-rw-r-- 1 root root %9u %s %2u %5u %s\r\n",
+ type, 0, ftp_month[(tm.tm_mon - 1)].month, tm.tm_mday, tm.tm_year, name);
+ }
+ else {
+ return snprintf(dest, destsize, "%srw-rw-r-- 1 root root %9u %s %2u %02u:%02u %s\r\n",
+ type, 0, ftp_month[(tm.tm_mon - 1)].month, tm.tm_mday, tm.tm_hour, tm.tm_min, name);
+ }
+}
+
+static bool ftp_open_file (const char *path, int mode) {
+ FRESULT res = f_open(&ftp_data.fp, path, mode);
+ if (res != FR_OK) {
+ return false;
+ }
+ ftp_data.e_open = E_FTP_FILE_OPEN;
+ return true;
+}
+
+static ftp_result_t ftp_read_file (char *filebuf, uint32_t desiredsize, uint32_t *actualsize) {
+ ftp_result_t result = E_FTP_RESULT_CONTINUE;
+ FRESULT res = f_read(&ftp_data.fp, filebuf, desiredsize, (UINT *)actualsize);
+ if (res != FR_OK) {
+ ftp_close_files();
+ result = E_FTP_RESULT_FAILED;
+ *actualsize = 0;
+ }
+ else if (*actualsize < desiredsize) {
+ ftp_close_files();
+ result = E_FTP_RESULT_OK;
+ }
+ return result;
+}
+
+static ftp_result_t ftp_write_file (char *filebuf, uint32_t size) {
+ ftp_result_t result = E_FTP_RESULT_FAILED;
+ uint32_t actualsize;
+ FRESULT res = f_write(&ftp_data.fp, filebuf, size, (UINT *)&actualsize);
+ if ((actualsize == size) && (FR_OK == res)) {
+ result = E_FTP_RESULT_OK;
+ }
+ else {
+ ftp_close_files();
+ }
+ return result;
+}
+
+static ftp_result_t ftp_open_dir_for_listing (const char *path, char *list, uint32_t maxlistsize, uint32_t *listsize) {
+ uint next = 0;
+ // "hack" to list root directory
+ if (path[0] == '/' && path[1] == '\0') {
+ next += ftp_print_eplf_drive((list + next), (maxlistsize - next), "SFLASH");
+#if MICROPY_HW_HAS_SDCARD
+ if (sd_disk_ready()) {
+ next += ftp_print_eplf_drive((list + next), (maxlistsize - next), "SD");
+ }
+#endif
+ *listsize = next;
+ return E_FTP_RESULT_OK;
+ }
+
+ FRESULT res;
+ res = f_opendir(&ftp_data.dp, path); /* Open the directory */
+ if (res != FR_OK) {
+ return E_FTP_RESULT_FAILED;
+ }
+ ftp_data.e_open = E_FTP_DIR_OPEN;
+ return E_FTP_RESULT_CONTINUE;
+}
+
+static ftp_result_t ftp_list_dir (char *list, uint32_t maxlistsize, uint32_t *listsize) {
+ uint next = 0;
+ uint count = 0;
+ FRESULT res;
+ FILINFO fno;
+ ftp_result_t result = E_FTP_RESULT_CONTINUE;
+
+ /* read up to 4 directory items */
+ while (count++ < 4) {
+ res = f_readdir(&ftp_data.dp, &fno); /* Read a directory item */
+ if (res != FR_OK || fno.fname[0] == 0) {
+ result = E_FTP_RESULT_OK;
+ break; /* Break on error or end of dp */
+ }
+ if (fno.fname[0] == '.' && fno.fname[1] == 0) continue; /* Ignore . entry */
+ if (fno.fname[0] == '.' && fno.fname[1] == '.' && fno.fname[2] == 0) continue; /* Ignore .. entry */
+
+ // Add the entry to the list
+ next += ftp_print_eplf_item((list + next), (maxlistsize - next), &fno);
+ }
+ if (result == E_FTP_RESULT_OK) {
+ ftp_close_files();
+ }
+ *listsize = next;
+ return result;
+}
+
+static void ftp_open_child (char *pwd, char *dir) {
+ if (dir[0] == '/') {
+ strcpy (pwd, dir);
+ }
+ else {
+ if (strlen(pwd) > 1) {
+ strcat (pwd, "/");
+ }
+ strcat (pwd, dir);
+ }
+
+ uint len = strlen(pwd);
+ if ((len > 1) && (pwd[len - 1] == '/')) {
+ pwd[len - 1] = '\0';
+ }
+}
+
+static void ftp_close_child (char *pwd) {
+ uint len = strlen(pwd);
+ while (len && (pwd[len] != '/')) {
+ len--;
+ }
+ if (len == 0) {
+ strcpy (pwd, "/");
+ }
+ else {
+ pwd[len] = '\0';
+ }
+}
+
+static void ftp_return_to_previous_path (char *pwd, char *dir) {
+ uint newlen = strlen(pwd) - strlen(dir);
+ if ((newlen > 2) && (pwd[newlen - 1] == '/')) {
+ pwd[newlen - 1] = '\0';
+ }
+ else {
+ if (newlen == 0) {
+ strcpy (pwd, "/");
+ }
+ else {
+ pwd[newlen] = '\0';
+ }
+ }
+}
diff --git a/cc3200/ftp/ftp.h b/cc3200/ftp/ftp.h
new file mode 100644
index 0000000000..d4b391ddc0
--- /dev/null
+++ b/cc3200/ftp/ftp.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef FTP_H_
+#define FTP_H_
+
+/******************************************************************************
+ DECLARE EXPORTED FUNCTIONS
+ ******************************************************************************/
+extern void ftp_init (void);
+extern void ftp_run (void);
+extern void ftp_enable (void);
+extern void ftp_disable (void);
+#endif /* FTP_H_ */
diff --git a/cc3200/ftp/updater.c b/cc3200/ftp/updater.c
new file mode 100644
index 0000000000..426d82bae7
--- /dev/null
+++ b/cc3200/ftp/updater.c
@@ -0,0 +1,121 @@
+#include
+#include
+#include "std.h"
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "simplelink.h"
+#include "flc.h"
+#include "updater.h"
+#include "shamd5.h"
+#include "modwlan.h"
+#include "debug.h"
+
+/******************************************************************************
+ DEFINE PRIVATE CONSTANTS
+ ******************************************************************************/
+#define UPDATER_IMG_PATH "/SFLASH/SYS/MCUIMG.BIN"
+#define UPDATER_SRVPACK_PATH "/SFLASH/SYS/SRVPCK.UCF"
+#define UPDATER_SIGN_PATH "/SFLASH/SYS/SRVPCK.SIG"
+
+/******************************************************************************
+ DEFINE TYPES
+ ******************************************************************************/
+typedef struct {
+ char *path;
+ _i32 fhandle;
+ _u32 fsize;
+ _u32 foffset;
+} updater_data_t;
+
+/******************************************************************************
+ DECLARE PRIVATE DATA
+ ******************************************************************************/
+static updater_data_t updater_data;
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+bool updater_check_path (void *path) {
+ // conert the path supplied to upper case
+ stoupper (path);
+ if (!strcmp(UPDATER_IMG_PATH, path)) {
+ updater_data.path = IMG_UPDATE;
+ updater_data.fsize = IMG_SIZE;
+ return true;
+ }
+ else if (!strcmp(UPDATER_SRVPACK_PATH, path)) {
+ updater_data.path = IMG_SRVPACK;
+ updater_data.fsize = SRVPACK_SIZE;
+ return true;
+ }
+ else if (!strcmp(UPDATER_SIGN_PATH, path)) {
+ updater_data.path = SRVPACK_SIGN;
+ updater_data.fsize = SIGN_SIZE;
+ return true;
+ }
+ return false;
+}
+
+bool updater_start (void) {
+ _u32 AccessModeAndMaxSize = FS_MODE_OPEN_WRITE;
+ SlFsFileInfo_t FsFileInfo;
+#ifdef USE_FREERTOS
+ xSemaphoreTake (xWlanSemaphore, portMAX_DELAY);
+#endif
+ if (0 != sl_FsGetInfo((_u8 *)updater_data.path, 0, &FsFileInfo)) {
+ // file doesn't exist, create it
+ AccessModeAndMaxSize = FS_MODE_OPEN_CREATE(updater_data.fsize, 0);
+ }
+ if (!sl_FsOpen((_u8 *)updater_data.path, AccessModeAndMaxSize, NULL, &updater_data.fhandle)) {
+ updater_data.foffset = 0;
+ return true;
+ }
+#ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+#endif
+ return false;
+}
+
+bool updater_write (uint8_t *buf, uint32_t len) {
+ if (len == sl_FsWrite(updater_data.fhandle, updater_data.foffset, buf, len)) {
+ updater_data.foffset += len;
+ return true;
+ }
+ return false;
+}
+
+void updater_finnish (void) {
+ sBootInfo_t sBootInfo;
+ _i32 fhandle;
+
+ if (updater_data.fhandle > 0) {
+ // close the file being updated
+ sl_FsClose(updater_data.fhandle, NULL, NULL, 0);
+
+ if (!strcmp (IMG_UPDATE, updater_data.path)) {
+ // open the boot info file for reading
+ if (!sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_READ, NULL, &fhandle)) {
+ ASSERT (sizeof(sBootInfo_t) == sl_FsRead(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t)));
+ sl_FsClose(fhandle, 0, 0, 0);
+ // open the file for writing
+ ASSERT (sl_FsOpen((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_WRITE, NULL, &fhandle) == 0);
+ }
+ else {
+ _u32 BootInfoCreateFlag = _FS_FILE_OPEN_FLAG_COMMIT | _FS_FILE_PUBLIC_WRITE | _FS_FILE_PUBLIC_READ;
+ ASSERT (sl_FsOpen ((unsigned char *)IMG_BOOT_INFO, FS_MODE_OPEN_CREATE((2 * sizeof(sBootInfo_t)),
+ BootInfoCreateFlag), NULL, &fhandle) == 0);
+ }
+
+ // write the new boot info
+ sBootInfo.ActiveImg = IMG_ACT_UPDATE;
+ sBootInfo.Status = IMG_STATUS_CHECK;
+ ASSERT (sizeof(sBootInfo_t) == sl_FsWrite(fhandle, 0, (unsigned char *)&sBootInfo, sizeof(sBootInfo_t)));
+ sl_FsClose(fhandle, 0, 0, 0);
+ }
+ }
+ updater_data.fhandle = -1;
+#ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+#endif
+}
diff --git a/cc3200/ftp/updater.h b/cc3200/ftp/updater.h
new file mode 100644
index 0000000000..3f1e791766
--- /dev/null
+++ b/cc3200/ftp/updater.h
@@ -0,0 +1,11 @@
+
+#ifndef UPDATER_H_
+#define UPDATER_H_
+
+bool updater_check_path (void *path);
+bool updater_start (void);
+bool updater_write (uint8_t *buf, uint32_t len);
+void updater_finnish (void);
+bool updater_verify (uint8_t *rbuff, uint8_t *hasbuff);
+
+#endif /* UPDATER_H_ */
diff --git a/cc3200/hal/adc.c b/cc3200/hal/adc.c
new file mode 100644
index 0000000000..23d219e1d9
--- /dev/null
+++ b/cc3200/hal/adc.c
@@ -0,0 +1,692 @@
+//*****************************************************************************
+//
+// adc.c
+//
+// Driver for the ADC module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup ADC_Analog_to_Digital_Converter_api
+//! @{
+//
+//*****************************************************************************
+#include "inc/hw_types.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_adc.h"
+#include "inc/hw_apps_config.h"
+#include "interrupt.h"
+#include "adc.h"
+
+
+//*****************************************************************************
+//
+//! Enables the ADC
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function sets the ADC global enable
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCEnable(unsigned long ulBase)
+{
+ //
+ // Set the global enable bit in the control register.
+ //
+ HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1;
+}
+
+//*****************************************************************************
+//
+//! Disable the ADC
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function clears the ADC global enable
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCDisable(unsigned long ulBase)
+{
+ //
+ // Clear the global enable bit in the control register.
+ //
+ HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ;
+}
+
+//*****************************************************************************
+//
+//! Enables specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function enables specified ADC channel and configures the
+//! pin as analog pin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulCh;
+
+ ulCh = (ulChannel == ADC_CH_0)? 0x02 :
+ (ulChannel == ADC_CH_1)? 0x04 :
+ (ulChannel == ADC_CH_2)? 0x08 : 0x10;
+
+ HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh;
+}
+
+//*****************************************************************************
+//
+//! Disables specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channelsber
+//!
+//! This function disables specified ADC channel.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulCh;
+
+ ulCh = (ulChannel == ADC_CH_0)? 0x02 :
+ (ulChannel == ADC_CH_1)? 0x04 :
+ (ulChannel == ADC_CH_2)? 0x08 : 0x10;
+
+ HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh;
+}
+
+//*****************************************************************************
+//
+//! Enables and registers ADC interrupt handler for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//! \param pfnHandler is a pointer to the function to be called when the
+//! ADC channel interrupt occurs.
+//!
+//! This function enables and registers ADC interrupt handler for specified
+//! channel. Individual interrupt for each channel should be enabled using
+//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear
+//! the interrupt source.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
+ void (*pfnHandler)(void))
+{
+ unsigned long ulIntNo;
+
+ //
+ // Get the interrupt number associted with the specified channel
+ //
+ ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
+ (ulChannel == ADC_CH_1)? INT_ADCCH1 :
+ (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
+
+ //
+ // Register the interrupt handler
+ //
+ IntRegister(ulIntNo,pfnHandler);
+
+ //
+ // Enable ADC interrupt
+ //
+ IntEnable(ulIntNo);
+}
+
+
+//*****************************************************************************
+//
+//! Disables and unregisters ADC interrupt handler for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function disables and unregisters ADC interrupt handler for specified
+//! channel. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulIntNo;
+
+ //
+ // Get the interrupt number associted with the specified channel
+ //
+ ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
+ (ulChannel == ADC_CH_1)? INT_ADCCH1 :
+ (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
+
+ //
+ // Disable ADC interrupt
+ //
+ IntDisable(ulIntNo);
+
+ //
+ // Unregister the interrupt handler
+ //
+ IntUnregister(ulIntNo);
+}
+
+//*****************************************************************************
+//
+//! Enables individual interrupt sources for specified channel
+//!
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated ADC interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//! - \b ADC_DMA_DONE for DMA done
+//! - \b ADC_FIFO_OVERFLOW for FIFO over flow
+//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow
+//! - \b ADC_FIFO_EMPTY for FIFO empty
+//! - \b ADC_FIFO_FULL for FIFO full
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulIntFlags)
+{
+ unsigned long ulOffset;
+ unsigned long ulDmaMsk;
+
+ //
+ // Enable DMA Done interrupt
+ //
+ if(ulIntFlags & ADC_DMA_DONE)
+ {
+ ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+ (ulChannel == ADC_CH_1)?0x00002000:
+ (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
+ }
+
+ ulIntFlags = ulIntFlags & 0x0F;
+ //
+ // Get the interrupt enable register offset for specified channel
+ //
+ ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
+
+ //
+ // Unmask the specified interrupts
+ //
+ HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf);
+}
+
+
+//*****************************************************************************
+//
+//! Disables individual interrupt sources for specified channel
+//!
+//!
+//! \param ulBase is the base address of the ADC.
+//! \param ulChannel is one of the valid ADC channels
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function disables the indicated ADC interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The parameters\e ulIntFlags and \e ulChannel should be as explained in
+//! ADCIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulIntFlags)
+{
+ unsigned long ulOffset;
+ unsigned long ulDmaMsk;
+
+ //
+ // Disable DMA Done interrupt
+ //
+ if(ulIntFlags & ADC_DMA_DONE)
+ {
+ ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+ (ulChannel == ADC_CH_1)?0x00002000:
+ (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
+ }
+
+ //
+ // Get the interrupt enable register offset for specified channel
+ //
+ ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
+
+ //
+ // Unmask the specified interrupts
+ //
+ HWREG(ulBase + ulOffset) &= ~ulIntFlags;
+}
+
+
+//*****************************************************************************
+//
+//! Gets the current channel interrupt status
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function returns the interrupt status of the specified ADC channel.
+//!
+//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
+//!
+//! \return Return the ADC channel interrupt status, enumerated as a bit
+//! field of values described in ADCIntEnable()
+//
+//*****************************************************************************
+unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulOffset;
+ unsigned long ulDmaMsk;
+ unsigned long ulIntStatus;
+
+ //
+ // Get DMA Done interrupt status
+ //
+ ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+ (ulChannel == ADC_CH_1)?0x00002000:
+ (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+ ulIntStatus = HWREG(APPS_CONFIG_BASE +
+ APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk;
+
+
+ //
+ // Get the interrupt enable register offset for specified channel
+ //
+ ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
+
+ //
+ // Read ADC interrupt status
+ //
+ ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf;
+
+ //
+ // Return the current interrupt status
+ //
+ return(ulIntStatus);
+}
+
+
+//*****************************************************************************
+//
+//! Clears the current channel interrupt sources
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
+//!
+//! This function clears individual interrupt source for the specified
+//! ADC channel.
+//!
+//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulIntFlags)
+{
+ unsigned long ulOffset;
+ unsigned long ulDmaMsk;
+
+ //
+ // Clear DMA Done interrupt
+ //
+ if(ulIntFlags & ADC_DMA_DONE)
+ {
+ ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
+ (ulChannel == ADC_CH_1)?0x00002000:
+ (ulChannel == ADC_CH_2)?0x00004000:0x00008000;
+
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
+ }
+
+ //
+ // Get the interrupt enable register offset for specified channel
+ //
+ ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
+
+ //
+ // Clear the specified interrupts
+ //
+ HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE));
+}
+
+//*****************************************************************************
+//
+//! Enables the ADC DMA operation for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function enables the DMA operation for specified ADC channel
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulBitMask;
+
+ //
+ // Get the bit mask for enabling DMA for specified channel
+ //
+ ulBitMask = (ulChannel == ADC_CH_0)?0x01:
+ (ulChannel == ADC_CH_1)?0x04:
+ (ulChannel == ADC_CH_2)?0x10:0x40;
+
+ //
+ // Enable DMA request for the specified channel
+ //
+ HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask;
+}
+
+//*****************************************************************************
+//
+//! Disables the ADC DMA operation for specified channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels
+//!
+//! This function disables the DMA operation for specified ADC channel
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \return None.
+//
+//*****************************************************************************
+void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulBitMask;
+
+ //
+ // Get the bit mask for disabling DMA for specified channel
+ //
+ ulBitMask = (ulChannel == ADC_CH_0)?0x01:
+ (ulChannel == ADC_CH_1)?0x04:
+ (ulChannel == ADC_CH_2)?0x10:0x40;
+
+ //
+ // Disable DMA request for the specified channel
+ //
+ HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask;
+}
+
+//*****************************************************************************
+//
+//! Configures the ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulValue is wrap arround value of the timer
+//!
+//! This function Configures the ADC internal timer. The ADC timer is a 17 bit
+//! used to timestamp the ADC data samples internally.
+//! User can read the timestamp along with the sample from the FIFO register(s).
+//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp
+//!
+//! The parameter \e ulValue can take any value between 0 - 2^17
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue)
+{
+ unsigned long ulReg;
+
+ //
+ // Read the currrent config
+ //
+ ulReg = HWREG(ulBase + ADC_O_adc_timer_configuration);
+
+ //
+ // Mask and set timer count field
+ //
+ ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF));
+
+ //
+ // Set the timer count value
+ //
+ HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg;
+}
+
+//*****************************************************************************
+//
+//! Resets ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function resets 17-bit ADC internal timer
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerReset(unsigned long ulBase)
+{
+ //
+ // Reset the timer
+ //
+ HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24);
+}
+
+//*****************************************************************************
+//
+//! Enables ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function enables 17-bit ADC internal timer
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerEnable(unsigned long ulBase)
+{
+ //
+ // Enable the timer
+ //
+ HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25);
+}
+
+//*****************************************************************************
+//
+//! Disables ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function disables 17-bit ADC internal timer
+//!
+//! \returns None.
+//
+//*****************************************************************************
+void ADCTimerDisable(unsigned long ulBase)
+{
+ //
+ // Disable the timer
+ //
+ HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of ADC internal timer
+//!
+//! \param ulBase is the base address of the ADC
+//!
+//! This function the current value of 17-bit ADC internal timer
+//!
+//! \returns Return the current value of ADC internal timer.
+//
+//*****************************************************************************
+unsigned long ADCTimerValueGet(unsigned long ulBase)
+{
+ return(HWREG(ulBase + ADC_O_adc_timer_current_count));
+}
+
+//*****************************************************************************
+//
+//! Gets the current FIFO level for specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels.
+//!
+//! This function returns the current FIFO level for specified ADC channel.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \returns Return the current FIFO level for specified channel
+//
+//*****************************************************************************
+unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulOffset;
+
+ //
+ // Get the fifo level register offset for specified channel
+ //
+ ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel;
+
+ //
+ // Return FIFO level
+ //
+ return(HWREG(ulBase + ulOffset) & 0x7);
+}
+
+//*****************************************************************************
+//
+//! Reads FIFO for specified ADC channel
+//!
+//! \param ulBase is the base address of the ADC
+//! \param ulChannel is one of the valid ADC channels.
+//!
+//! This function returns one data sample from the channel fifo as specified by
+//! \e ulChannel parameter.
+//!
+//! The parameter \e ulChannel should be one of the following
+//!
+//! - \b ADC_CH_0 for channel 0
+//! - \b ADC_CH_1 for channel 1
+//! - \b ADC_CH_2 for channel 2
+//! - \b ADC_CH_3 for channel 3
+//!
+//! \returns Return one data sample from the channel fifo.
+//
+//*****************************************************************************
+unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel)
+{
+ unsigned long ulOffset;
+
+ //
+ // Get the fifo register offset for specified channel
+ //
+ ulOffset = ADC_O_channel0FIFODATA + ulChannel;
+
+ //
+ // Return FIFO level
+ //
+ return(HWREG(ulBase + ulOffset));
+}
+
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/adc.h b/cc3200/hal/adc.h
new file mode 100644
index 0000000000..fce1a7305e
--- /dev/null
+++ b/cc3200/hal/adc.h
@@ -0,0 +1,117 @@
+//*****************************************************************************
+//
+// adc.h
+//
+// Defines and Macros for the ADC.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __ADC_H__
+#define __ADC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+//{
+#endif
+
+//*****************************************************************************
+// Values that can be passed to APIs as ulChannel parameter
+//*****************************************************************************
+#define ADC_CH_0 0x00000000
+#define ADC_CH_1 0x00000008
+#define ADC_CH_2 0x00000010
+#define ADC_CH_3 0x00000018
+
+
+//*****************************************************************************
+//
+// Values that can be passed to ADCIntEnable(), ADCIntDisable()
+// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus()
+//
+//*****************************************************************************
+#define ADC_DMA_DONE 0x00000010
+#define ADC_FIFO_OVERFLOW 0x00000008
+#define ADC_FIFO_UNDERFLOW 0x00000004
+#define ADC_FIFO_EMPTY 0x00000002
+#define ADC_FIFO_FULL 0x00000001
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void ADCEnable(unsigned long ulBase);
+extern void ADCDisable(unsigned long ulBase);
+extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel);
+extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel);
+extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
+ void (*pfnHandler)(void));
+extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel);
+extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulIntFlags);
+extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulIntFlags);
+extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel);
+extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
+ unsigned long ulIntFlags);
+extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel);
+extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel);
+extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue);
+extern void ADCTimerEnable(unsigned long ulBase);
+extern void ADCTimerDisable(unsigned long ulBase);
+extern void ADCTimerReset(unsigned long ulBase);
+extern unsigned long ADCTimerValueGet(unsigned long ulBase);
+extern unsigned char ADCFIFOLvlGet(unsigned long ulBase,
+ unsigned long ulChannel);
+extern unsigned long ADCFIFORead(unsigned long ulBase,
+ unsigned long ulChannel);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ADC_H__
+
diff --git a/cc3200/hal/aes.c b/cc3200/hal/aes.c
new file mode 100644
index 0000000000..9f3175ec2b
--- /dev/null
+++ b/cc3200/hal/aes.c
@@ -0,0 +1,1330 @@
+//*****************************************************************************
+//
+// aes.c
+//
+// Driver for the AES module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup AES_Advanced_Encryption_Standard_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_aes.h"
+#include "inc/hw_dthe.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "aes.h"
+#include "debug.h"
+#include "interrupt.h"
+
+#define AES_BLOCK_SIZE_IN_BYTES 16
+
+//*****************************************************************************
+//
+//! Configures the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Config is the configuration of the AES module.
+//!
+//! This function configures the AES module based on the specified parameters.
+//! It does not change any DMA- or interrupt-related parameters.
+//!
+//! The ui32Config parameter is a bit-wise OR of a number of configuration
+//! flags. The valid flags are grouped based on their function.
+//!
+//! The direction of the operation is specified with only of following flags:
+//!
+//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode
+//! - \b AES_CFG_DIR_DECRYPT - Decryption mode
+//!
+//! The key size is specified with only one of the following flags:
+//!
+//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits
+//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits
+//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits
+//!
+//! The mode of operation is specified with only one of the following flags.
+//!
+//! - \b AES_CFG_MODE_ECB - Electronic codebook mode
+//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode
+//! - \b AES_CFG_MODE_CFB - Cipher feedback mode
+//! - \b AES_CFG_MODE_CTR - Counter mode
+//! - \b AES_CFG_MODE_ICM - Integer counter mode
+//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode
+//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with
+//! ciphertext stealing with previous/intermediate tweak value and j loaded
+//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with
+//! ciphertext stealing with key2, i and j loaded
+//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with
+//! ciphertext stealing with key2 and i loaded, j = 0
+//! - \b AES_CFG_MODE_F8 - F8 mode
+//! - \b AES_CFG_MODE_F9 - F9 mode
+//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication
+//! code mode
+//! - \b AES_CFG_MODE_GCM - Galois/counter mode
+//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H
+//! loaded and Y0-encrypted forced to zero
+//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H
+//! loaded and Y0-encrypted calculated internally
+//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH
+//! (both H and Y0-encrypted calculated internally)
+//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode
+//!
+//! The following defines are used to specify the counter width. It is only
+//! required to be defined when using CTR, CCM, or GCM modes, only one of the
+//! following defines must be used to specify the counter width length:
+//!
+//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits
+//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits
+//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits
+//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits
+//!
+//! Only one of the following defines must be used to specify the length field
+//! for CCM operations (L):
+//!
+//! - \b AES_CFG_CCM_L_2 - 2 bytes
+//! - \b AES_CFG_CCM_L_4 - 4 bytes
+//! - \b AES_CFG_CCM_L_8 - 8 bytes
+//!
+//! Only one of the following defines must be used to specify the length of the
+//! authentication field for CCM operations (M) through the \e ui32Config
+//! argument in the AESConfigSet() function:
+//!
+//! - \b AES_CFG_CCM_M_4 - 4 bytes
+//! - \b AES_CFG_CCM_M_6 - 6 bytes
+//! - \b AES_CFG_CCM_M_8 - 8 bytes
+//! - \b AES_CFG_CCM_M_10 - 10 bytes
+//! - \b AES_CFG_CCM_M_12 - 12 bytes
+//! - \b AES_CFG_CCM_M_14 - 14 bytes
+//! - \b AES_CFG_CCM_M_16 - 16 bytes
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) ||
+ (ui32Config & AES_CFG_DIR_DECRYPT));
+ ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) ||
+ (ui32Config & AES_CFG_KEY_SIZE_192BIT) ||
+ (ui32Config & AES_CFG_KEY_SIZE_256BIT));
+ ASSERT((ui32Config & AES_CFG_MODE_ECB) ||
+ (ui32Config & AES_CFG_MODE_CBC) ||
+ (ui32Config & AES_CFG_MODE_CTR) ||
+ (ui32Config & AES_CFG_MODE_ICM) ||
+ (ui32Config & AES_CFG_MODE_CFB) ||
+ (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) ||
+ (ui32Config & AES_CFG_MODE_XTS_K2IJL) ||
+ (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) ||
+ (ui32Config & AES_CFG_MODE_F8) ||
+ (ui32Config & AES_CFG_MODE_F9) ||
+ (ui32Config & AES_CFG_MODE_CTR) ||
+ (ui32Config & AES_CFG_MODE_CBCMAC) ||
+ (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) ||
+ (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) ||
+ (ui32Config & AES_CFG_MODE_GCM_HY0CALC) ||
+ (ui32Config & AES_CFG_MODE_CCM));
+ ASSERT(((ui32Config & AES_CFG_MODE_CTR) ||
+ (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) ||
+ (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) ||
+ (ui32Config & AES_CFG_MODE_GCM_HY0CALC) ||
+ (ui32Config & AES_CFG_MODE_CCM)) &&
+ ((ui32Config & AES_CFG_CTR_WIDTH_32) ||
+ (ui32Config & AES_CFG_CTR_WIDTH_64) ||
+ (ui32Config & AES_CFG_CTR_WIDTH_96) ||
+ (ui32Config & AES_CFG_CTR_WIDTH_128)));
+ ASSERT((ui32Config & AES_CFG_MODE_CCM) &&
+ ((ui32Config & AES_CFG_CCM_L_2) ||
+ (ui32Config & AES_CFG_CCM_L_4) ||
+ (ui32Config & AES_CFG_CCM_L_8)) &&
+ ((ui32Config & AES_CFG_CCM_M_4) ||
+ (ui32Config & AES_CFG_CCM_M_6) ||
+ (ui32Config & AES_CFG_CCM_M_8) ||
+ (ui32Config & AES_CFG_CCM_M_10) ||
+ (ui32Config & AES_CFG_CCM_M_12) ||
+ (ui32Config & AES_CFG_CCM_M_14) ||
+ (ui32Config & AES_CFG_CCM_M_16)));
+
+ //
+ // Backup the save context field before updating the register.
+ //
+ if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT)
+ {
+ ui32Config |= AES_CTRL_SAVE_CONTEXT;
+ }
+
+ //
+ // Write the CTRL register with the new value
+ //
+ HWREG(ui32Base + AES_O_CTRL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Writes the key 1 configuration registers, which are used for encryption or
+//! decryption.
+//!
+//! \param ui32Base is the base address for the AES module.
+//! \param pui8Key is an array of bytes, containing the key to be
+//! configured. The least significant word in the 0th index.
+//! \param ui32Keysize is the size of the key, which must be one of the
+//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or
+//! \b AES_CFG_KEY_SIZE_256.
+//!
+//! This function writes key 1 configuration registers based on the key
+//! size. This function is used in all modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) ||
+ (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) ||
+ (ui32Keysize == AES_CFG_KEY_SIZE_256BIT));
+
+ //
+ // With all key sizes, the first 4 words are written.
+ //
+ HWREG(ui32Base + AES_O_KEY1_0) = * ((uint32_t *)(pui8Key + 0));
+ HWREG(ui32Base + AES_O_KEY1_1) = * ((uint32_t *)(pui8Key + 4));
+ HWREG(ui32Base + AES_O_KEY1_2) = * ((uint32_t *)(pui8Key + 8));
+ HWREG(ui32Base + AES_O_KEY1_3) = * ((uint32_t *)(pui8Key + 12));
+
+ //
+ // The key is 192 or 256 bits. Write the next 2 words.
+ //
+ if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT)
+ {
+ HWREG(ui32Base + AES_O_KEY1_4) = * ((uint32_t *)(pui8Key + 16));
+ HWREG(ui32Base + AES_O_KEY1_5) = * ((uint32_t *)(pui8Key + 20));
+ }
+
+ //
+ // The key is 256 bits. Write the last 2 words.
+ //
+ if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT)
+ {
+ HWREG(ui32Base + AES_O_KEY1_6) = * ((uint32_t *)(pui8Key + 24));
+ HWREG(ui32Base + AES_O_KEY1_7) = * ((uint32_t *)(pui8Key + 28));
+ }
+}
+
+//*****************************************************************************
+//
+//! Writes the key 2 configuration registers, which are used for encryption or
+//! decryption.
+//!
+//! \param ui32Base is the base address for the AES module.
+//! \param pui8Key is an array of bytes, containing the key to be
+//! configured. The least significant word in the 0th index.
+//! \param ui32Keysize is the size of the key, which must be one of the
+//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or
+//! \b AES_CFG_KEY_SIZE_256.
+//!
+//! This function writes the key 2 configuration registers based on the key
+//! size. This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) ||
+ (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) ||
+ (ui32Keysize == AES_CFG_KEY_SIZE_256BIT));
+
+ //
+ // With all key sizes, the first 4 words are written.
+ //
+ HWREG(ui32Base + AES_O_KEY2_0) = * ((uint32_t *)(pui8Key + 0));
+ HWREG(ui32Base + AES_O_KEY2_1) = * ((uint32_t *)(pui8Key + 4));
+ HWREG(ui32Base + AES_O_KEY2_2) = * ((uint32_t *)(pui8Key + 8));
+ HWREG(ui32Base + AES_O_KEY2_3) = * ((uint32_t *)(pui8Key + 12));
+
+ //
+ // The key is 192 or 256 bits. Write the next 2 words.
+ //
+ if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT)
+ {
+ HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 16));
+ HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 20));
+ }
+
+ //
+ // The key is 256 bits. Write the last 2 words.
+ //
+ if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT)
+ {
+ HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 24));
+ HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 28));
+ }
+}
+
+//*****************************************************************************
+//
+//! Writes key 3 configuration registers, which are used for encryption or
+//! decryption.
+//!
+//! \param ui32Base is the base address for the AES module.
+//! \param pui8Key is a pointer to an array bytes, containing
+//! the key to be configured. The least significant word is in the 0th index.
+//!
+//! This function writes the key 2 configuration registers with key 3 data
+//! used in CBC-MAC and F8 modes. This key is always 128 bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Write the key into the upper 4 key registers
+ //
+ HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 0));
+ HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 4));
+ HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 8));
+ HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 12));
+}
+
+//*****************************************************************************
+//
+//! Writes the Initial Vector (IV) register, needed in some of the AES Modes.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8IVdata is an array of 16 bytes (128 bits), containing the IV
+//! value to be configured. The least significant word is in the 0th index.
+//!
+//! This functions writes the initial vector registers in the AES module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Write the initial vector registers.
+ //
+ HWREG(ui32Base + AES_O_IV_IN_0) = *((uint32_t *)(pui8IVdata+0));
+ HWREG(ui32Base + AES_O_IV_IN_1) = *((uint32_t *)(pui8IVdata+4));
+ HWREG(ui32Base + AES_O_IV_IN_2) = *((uint32_t *)(pui8IVdata+8));
+ HWREG(ui32Base + AES_O_IV_IN_3) = *((uint32_t *)(pui8IVdata+12));
+}
+
+//*****************************************************************************
+//
+//! Saves the tag registers to a user-defined location.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8TagData is pointer to the location that stores the tag data.
+//!
+//! This function stores the tag data for use authenticated encryption and
+//! decryption operations.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Read the tag data.
+ //
+ *((uint32_t *)(pui8TagData+0)) = HWREG((ui32Base + AES_O_TAG_OUT_0));
+ *((uint32_t *)(pui8TagData+4)) = HWREG((ui32Base + AES_O_TAG_OUT_1));
+ *((uint32_t *)(pui8TagData+8)) = HWREG((ui32Base + AES_O_TAG_OUT_2));
+ *((uint32_t *)(pui8TagData+12)) = HWREG((ui32Base + AES_O_TAG_OUT_3));
+}
+
+//*****************************************************************************
+//
+//! Used to set the write crypto data length in the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui64Length is the crypto data length in bytes.
+//!
+//! This function stores the cryptographic data length in blocks for all modes.
+//! Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up
+//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used. For
+//! basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the
+//! length field, indicating that the length is infinite.
+//!
+//! When this function is called, the engine is triggered to start using
+//! this context.
+//!
+//! \note This length does not include the authentication-only data used in
+//! some modes. Use the AESAuthLengthSet() function to specify the
+//! authentication data length.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Write the length register by shifting the 64-bit ui64Length.
+ //
+ HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length);
+ HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32);
+}
+
+//*****************************************************************************
+//
+//! Sets the optional additional authentication data (AAD) length.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Length is the length in bytes.
+//!
+//! This function is only used to write the authentication data length in the
+//! combined modes (GCM or CCM) and XTS mode. Supported AAD lengths for CCM
+//! are from 0 to (2^16 - 28) bytes. For GCM, any value up to (2^32 - 1) can
+//! be used. For XTS mode, this register is used to load j. Loading of j is
+//! only required if j != 0. j represents the sequential number of the 128-bit
+//! blocks inside the data unit. Consequently, j must be multiplied by 16
+//! when passed to this function, thereby placing the block number in
+//! bits [31:4] of the register.
+//!
+//! When this function is called, the engine is triggered to start using
+//! this context for GCM and CCM.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Write the length into the register.
+ //
+ HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length;
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers without blocking.
+//! This api writes data in blocks
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8Dest is a pointer to an array of words of data.
+//! \param ui8Length the length can be from 1 to 16
+//!
+//! This function reads a block of either plaintext or ciphertext out of the
+//! AES module. If the output data is not ready, the function returns
+//! false. If the read completed successfully, the function returns true.
+//! A block is 16 bytes or 4 words.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
+{
+ volatile uint32_t pui32Dest[4];
+ uint8_t ui8BytCnt;
+ uint8_t *pui8DestTemp;
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ if((ui8Length == 0)||(ui8Length>16))
+ {
+ return(false);
+ }
+
+ //
+ // Check if the output is ready before reading the data. If it not ready,
+ // return false.
+ //
+ if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+ {
+ return(false);
+ }
+
+ //
+ // Read a block of data from the data registers
+ //
+ pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3);
+ pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2);
+ pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1);
+ pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0);
+
+ //
+ //Copy the data to a block memory
+ //
+ pui8DestTemp = (uint8_t *)pui32Dest;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
+ }
+ //
+ // Read successful, return true.
+ //
+ return(true);
+}
+
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers with blocking.
+//! This api writes data in blocks
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8Dest is a pointer to an array of words.
+//! \param ui8Length is the length of data in bytes to be read.
+//! ui8Length can be from 1 to 16
+//!
+//! This function reads a block of either plaintext or ciphertext out of the
+//! AES module. If the output is not ready, the function waits until it
+//! is ready. A block is 16 bytes or 4 words.
+//!
+//! \return None.
+//
+//*****************************************************************************
+
+void
+AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
+{
+ volatile uint32_t pui32Dest[4];
+ uint8_t ui8BytCnt;
+ uint8_t *pui8DestTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ if((ui8Length == 0)||(ui8Length>16))
+ {
+ return;
+ }
+
+
+ //
+ // Wait for the output to be ready before reading the data.
+ //
+ while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+ {
+ }
+
+ //
+ // Read a block of data from the data registers
+ //
+ pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3);
+ pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2);
+ pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1);
+ pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0);
+ //
+ //Copy the data to a block memory
+ //
+ pui8DestTemp = (uint8_t *)pui32Dest;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
+ }
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8Src is a pointer to an array of words of data.
+//! \param ui8Length the length can be from 1 to 16
+//!
+//! This function writes a block of either plaintext or ciphertext into the
+//! AES module. If the input is not ready, the function returns false
+//! If the write completed successfully, the function returns true.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
+{
+ volatile uint32_t pui32Src[4]={0,0,0,0};
+ uint8_t ui8BytCnt;
+ uint8_t *pui8SrcTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ if((ui8Length == 0)||(ui8Length>16))
+ {
+ return(false);
+ }
+
+ //
+ // Check if the input is ready. If not, then return false.
+ //
+ if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))))
+ {
+ return(false);
+ }
+
+
+ //
+ //Copy the data to a block memory
+ //
+ pui8SrcTemp = (uint8_t *)pui32Src;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
+ }
+ //
+ // Write a block of data into the data registers.
+ //
+ HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0];
+ HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1];
+ HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2];
+ HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3];
+
+ //
+ // Write successful, return true.
+ //
+ return(true);
+}
+
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers with blocking.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8Src is a pointer to an array of bytes.
+//! \param ui8Length the length can be from 1 to 16
+//!
+//! This function writes a block of either plaintext or ciphertext into the
+//! AES module. If the input is not ready, the function waits until it is
+//! ready before performing the write.
+//!
+//! \return None.
+//
+//*****************************************************************************
+
+void
+AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
+{
+ volatile uint32_t pui32Src[4]={0,0,0,0};
+ uint8_t ui8BytCnt;
+ uint8_t *pui8SrcTemp;
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ if((ui8Length == 0)||(ui8Length>16))
+ {
+ return;
+ }
+ //
+ // Wait for input ready.
+ //
+ while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0)
+ {
+ }
+
+ //
+ //Copy the data to a block memory
+ //
+ pui8SrcTemp = (uint8_t *)pui32Src;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
+ }
+
+ //
+ // Write a block of data into the data registers.
+ //
+ HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0];
+ HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1];
+ HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2];
+ HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3];
+}
+
+
+//*****************************************************************************
+//
+//! Used to process(transform) blocks of data, either encrypt or decrypt it.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8Src is a pointer to the memory location where the input data
+//! is stored.
+//! \param pui8Dest is a pointer to the memory location output is written.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//!
+//! This function iterates the encryption or decryption mechanism number over
+//! the data length. Before calling this function, ensure that the AES
+//! module is properly configured the key, data size, mode, etc. Only ECB,
+//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used. The data
+//! is processed in 4-word (16-byte) blocks.
+//!
+//! \note This function only supports values of \e ui32Length less than 2^32,
+//! because the memory size is restricted to between 0 to 2^32 bytes.
+//!
+//! \return Returns true if data was processed successfully. Returns false
+//! if data processing failed.
+//
+//*****************************************************************************
+bool
+AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
+ uint32_t ui32Length)
+{
+ uint32_t ui32Count, ui32BlkCount, ui32ByteCount;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Write the length register first, which triggers the engine to start
+ // using this context.
+ //
+ AESDataLengthSet(AES_BASE, (uint64_t) ui32Length);
+
+ //
+ // Now loop until the blocks are written.
+ //
+ ui32BlkCount = ui32Length/16;
+ for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1)
+ {
+ //
+ // Write the data registers.
+ //
+ AESDataWrite(ui32Base, pui8Src + (ui32Count*16) ,16);
+
+ //
+ // Read the data registers.
+ //
+ AESDataRead(ui32Base, pui8Dest + (ui32Count*16) ,16);
+
+ }
+
+ //
+ //Now handle the residue bytes
+ //
+ ui32ByteCount = ui32Length%16;
+ if(ui32ByteCount)
+ {
+ //
+ // Write the data registers.
+ //
+ AESDataWrite(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,ui32ByteCount);
+
+ //
+ // Read the data registers.
+ //
+ AESDataRead(ui32Base, pui8Dest + (ui32Count*ui32BlkCount) ,ui32ByteCount);
+ }
+
+
+
+ //
+ // Return true to indicate successful completion of the function.
+ //
+ return(true);
+}
+//*****************************************************************************
+//
+//! Used to generate message authentication code (MAC) using CBC-MAC and F9 mode.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8Src is a pointer to the memory location where the input data
+//! is stored.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//! \param pui8Tag is a pointer to a 4-word array where the hash tag is
+//! written.
+//!
+//! This function processes data to produce a hash tag that can be used tor
+//! authentication. Before calling this function, ensure that the AES
+//! module is properly configured the key, data size, mode, etc. Only
+//! CBC-MAC and F9 modes should be used.
+//!
+//! \return Returns true if data was processed successfully. Returns false
+//! if data processing failed.
+//
+//*****************************************************************************
+bool
+AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, uint32_t ui32Length,
+ uint8_t *pui8Tag)
+{
+ uint32_t ui32Count, ui32BlkCount, ui32ByteCount;
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Write the length register first, which triggers the engine to start
+ // using this context.
+ //
+ AESDataLengthSet(AES_BASE, (uint64_t) ui32Length);
+
+ //
+ // Write the data registers.
+ //
+
+ //
+ // Now loop until the blocks are written.
+ //
+ ui32BlkCount = ui32Length/16;
+ for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1)
+ {
+ //
+ // Write the data registers.
+ //
+ AESDataWrite(ui32Base, pui8Src + ui32Count*16 ,16);
+ }
+
+ //
+ //Now handle the residue bytes
+ //
+ ui32ByteCount = ui32Length%16;
+ if(ui32ByteCount)
+ {
+ //
+ // Write the data registers.
+ //
+ AESDataWrite(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,ui32ByteCount);
+ }
+
+ //
+ // Wait for the context data regsiters to be ready.
+ //
+ while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0)
+ {
+ }
+
+ //
+ // Read the hash tag value.
+ //
+ AESTagRead(AES_BASE, pui8Tag);
+
+ //
+ // Return true to indicate successful completion of the function.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Used for Authenticated encryption (AE) of the data. Processes and authenticates blocks of data,
+//! either encrypt the data or decrypt the data.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pui8Src is a pointer to the memory location where the input data
+//! is stored. The data must be padded to the 16-byte boundary.
+//! \param pui8Dest is a pointer to the memory location output is written.
+//! The space for written data must be rounded up to the 16-byte boundary.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//! \param pui8AuthSrc is a pointer to the memory location where the
+//! additional authentication data is stored. The data must be padded to the
+//! 16-byte boundary.
+//! \param ui32AuthLength is the length of the additional authentication
+//! data in bytes.
+//! \param pui8Tag is a pointer to a 4-word array where the hash tag is
+//! written.
+//!
+//! This function encrypts or decrypts blocks of data in addition to
+//! authentication data. A hash tag is also produced. Before calling this
+//! function, ensure that the AES module is properly configured the key,
+//! data size, mode, etc. Only CCM and GCM modes should be used.
+//!
+//! \return Returns true if data was processed successfully. Returns false
+//! if data processing failed.
+//
+//*****************************************************************************
+bool
+AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
+ uint32_t ui32Length, uint8_t *pui8AuthSrc,
+ uint32_t ui32AuthLength, uint8_t *pui8Tag)
+{
+ uint32_t ui32Count;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Set the data length.
+ //
+ AESDataLengthSet(AES_BASE, (uint64_t) ui32Length);
+
+ //
+ // Set the additional authentication data length.
+ //
+ AESAuthDataLengthSet(AES_BASE, ui32AuthLength);
+
+ //
+ // Now loop until the authentication data blocks are written.
+ //
+ for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16)
+ {
+ //
+ // Write the data registers.
+ //
+ AESDataWrite(ui32Base, pui8AuthSrc + (ui32Count),16);
+ }
+
+ //
+ // Now loop until the data blocks are written.
+ //
+ for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16)
+ {
+ //
+ // Write the data registers.
+ //
+ AESDataWrite(ui32Base, pui8Src + (ui32Count),16);
+
+ //
+ //
+ // Read the data registers.
+ //
+ AESDataRead(ui32Base, pui8Dest + (ui32Count),16);
+ }
+
+ //
+ // Wait for the context data regsiters to be ready.
+ //
+ while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0)
+ {
+ }
+
+ //
+ // Read the hash tag value.
+ //
+ AESTagRead(AES_BASE, pui8Tag);
+
+ //
+ // Return true to indicate successful completion of the function.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Returns the current AES module interrupt status.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! \return Returns a bit mask of the interrupt sources, which is a logical OR
+//! of any of the following:
+//!
+//! - \b AES_INT_CONTEXT_IN - Context interrupt
+//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt.
+//! - \b AES_INT_DATA_IN - Data input interrupt
+//! - \b AES_INT_DATA_OUT - Data output interrupt
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//! interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//
+//*****************************************************************************
+uint32_t
+AESIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ uint32_t ui32Temp;
+ uint32_t ui32IrqEnable;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Read the IRQ status register and return the value.
+ //
+ if(bMasked)
+ {
+ ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_MIS);
+ ui32IrqEnable = HWREG(ui32Base + AES_O_IRQENABLE);
+ return((HWREG(ui32Base + AES_O_IRQSTATUS) &
+ ui32IrqEnable) | ((ui32Temp & 0x0000000F) << 16));
+ }
+ else
+ {
+ ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_RIS);
+ return(HWREG(ui32Base + AES_O_IRQSTATUS) |
+ ((ui32Temp & 0x0000000F) << 16));
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables AES module interrupts.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to enable.
+//!
+//! This function enables the interrupts in the AES module. The \e ui32IntFlags
+//! parameter is the logical OR of any of the following:
+//!
+//! - \b AES_INT_CONTEXT_IN - Context interrupt
+//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt
+//! - \b AES_INT_DATA_IN - Data input interrupt
+//! - \b AES_INT_DATA_OUT - Data output interrupt
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//! interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \note Interrupts that have been previously been enabled are not disabled
+//! when this function is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) ||
+ (ui32IntFlags == AES_INT_CONTEXT_OUT) ||
+ (ui32IntFlags == AES_INT_DATA_IN) ||
+ (ui32IntFlags == AES_INT_DATA_OUT) ||
+ (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||
+ (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||
+ (ui32IntFlags == AES_INT_DMA_DATA_IN) ||
+ (ui32IntFlags == AES_INT_DMA_DATA_OUT));
+
+ //
+ // Set the flags.
+ //
+ HWREG(DTHE_BASE + DTHE_O_AES_IM) &= ~((ui32IntFlags & 0x000F0000) >> 16);
+ HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
+}
+
+//*****************************************************************************
+//
+//! Disables AES module interrupts.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to disable.
+//!
+//! This function disables the interrupt sources in the AES module. The
+//! \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b AES_INT_CONTEXT_IN - Context interrupt
+//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt
+//! - \b AES_INT_DATA_IN - Data input interrupt
+//! - \b AES_INT_DATA_OUT - Data output interrupt
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//! interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \note The DMA done interrupts are the only interrupts that can be cleared.
+//! The remaining interrupts can be disabled instead using AESIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) ||
+ (ui32IntFlags == AES_INT_CONTEXT_OUT) ||
+ (ui32IntFlags == AES_INT_DATA_IN) ||
+ (ui32IntFlags == AES_INT_DATA_OUT) ||
+ (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||
+ (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||
+ (ui32IntFlags == AES_INT_DMA_DATA_IN) ||
+ (ui32IntFlags == AES_INT_DMA_DATA_OUT));
+
+ //
+ // Clear the flags.
+ //
+ HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x000F0000) >> 16);
+ HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
+}
+
+//*****************************************************************************
+//
+//! Clears AES module interrupts.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to disable.
+//!
+//! This function clears the interrupt sources in the AES module. The
+//! \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done
+//! interrupt
+//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \note Only the DMA done interrupts can be cleared. The remaining
+//! interrupts should be disabled with AESIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) ||
+ (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) ||
+ (ui32IntFlags == AES_INT_DMA_DATA_IN) ||
+ (ui32IntFlags == AES_INT_DMA_DATA_OUT));
+
+ HWREG(DTHE_BASE + DTHE_O_AES_IC) = ((ui32IntFlags >> 16) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled AES interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables AES interrupts on the interrupt controller; specific AES
+//! interrupt sources must be enabled using AESIntEnable(). The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! AESIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() is used to enable AES interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_AES, pfnHandler);
+
+ //
+ // Enable the interrupt
+ //
+ IntEnable(INT_AES);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESIntUnregister(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_AES);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_AES);
+}
+
+//*****************************************************************************
+//
+//! Enables uDMA requests for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Flags is a bit mask of the uDMA requests to be enabled.
+//!
+//! This function enables the uDMA request sources in the AES module.
+//! The \e ui32Flags parameter is the logical OR of any of the following:
+//!
+//! - \b AES_DMA_DATA_IN
+//! - \b AES_DMA_DATA_OUT
+//! - \b AES_DMA_CONTEXT_IN
+//! - \b AES_DMA_CONTEXT_OUT
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32Flags == AES_DMA_DATA_IN) ||
+ (ui32Flags == AES_DMA_DATA_OUT) ||
+ (ui32Flags == AES_DMA_CONTEXT_IN) ||
+ (ui32Flags == AES_DMA_CONTEXT_OUT));
+
+ //
+ // Set the flags in the current register value.
+ //
+ HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags;
+}
+
+//*****************************************************************************
+//
+//! Disables uDMA requests for the AES module.
+//!
+//! \param ui32Base is the base address of the AES module.
+//! \param ui32Flags is a bit mask of the uDMA requests to be disabled.
+//!
+//! This function disables the uDMA request sources in the AES module.
+//! The \e ui32Flags parameter is the logical OR of any of the
+//! following:
+//!
+//! - \b AES_DMA_DATA_IN
+//! - \b AES_DMA_DATA_OUT
+//! - \b AES_DMA_CONTEXT_IN
+//! - \b AES_DMA_CONTEXT_OUT
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == AES_BASE);
+ ASSERT((ui32Flags == AES_DMA_DATA_IN) ||
+ (ui32Flags == AES_DMA_DATA_OUT) ||
+ (ui32Flags == AES_DMA_CONTEXT_IN) ||
+ (ui32Flags == AES_DMA_CONTEXT_OUT));
+
+ //
+ // Clear the flags in the current register value.
+ //
+ HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/aes.h b/cc3200/hal/aes.h
new file mode 100644
index 0000000000..e3213e6101
--- /dev/null
+++ b/cc3200/hal/aes.h
@@ -0,0 +1,217 @@
+//*****************************************************************************
+//
+// aes.h
+//
+// Defines and Macros for the AES module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_AES_H__
+#define __DRIVERLIB_AES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the operation direction in the
+// ui32Config argument in the AESConfig function. Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_DIR_ENCRYPT 0x00000004
+#define AES_CFG_DIR_DECRYPT 0x00000000
+
+//*****************************************************************************
+//
+// The following defines are used to specify the key size in the ui32Config
+// argument in the AESConfig function. Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_KEY_SIZE_128BIT 0x00000008
+#define AES_CFG_KEY_SIZE_192BIT 0x00000010
+#define AES_CFG_KEY_SIZE_256BIT 0x00000018
+
+//*****************************************************************************
+//
+// The following defines are used to specify the mode of operation in the
+// ui32Config argument in the AESConfig function. Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_MODE_M 0x2007fe60
+#define AES_CFG_MODE_ECB 0x00000000
+#define AES_CFG_MODE_CBC 0x00000020
+#define AES_CFG_MODE_CTR 0x00000040
+#define AES_CFG_MODE_ICM 0x00000200
+#define AES_CFG_MODE_CFB 0x00000400
+#define AES_CFG_MODE_XTS_TWEAKJL \
+ 0x00000800
+#define AES_CFG_MODE_XTS_K2IJL \
+ 0x00001000
+#define AES_CFG_MODE_XTS_K2ILJ0 \
+ 0x00001800
+#define AES_CFG_MODE_F8 0x00002000
+#define AES_CFG_MODE_F9 0x20004000
+#define AES_CFG_MODE_CBCMAC 0x20008000
+#define AES_CFG_MODE_GCM_HLY0ZERO \
+ 0x20010040
+#define AES_CFG_MODE_GCM_HLY0CALC \
+ 0x20020040
+#define AES_CFG_MODE_GCM_HY0CALC \
+ 0x20030040
+#define AES_CFG_MODE_CCM 0x20040040
+
+//*****************************************************************************
+//
+// The following defines are used to specify the counter width in the
+// ui32Config argument in the AESConfig function. It is only required to
+// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CTR_WIDTH_32 0x00000000
+#define AES_CFG_CTR_WIDTH_64 0x00000080
+#define AES_CFG_CTR_WIDTH_96 0x00000100
+#define AES_CFG_CTR_WIDTH_128 0x00000180
+
+//*****************************************************************************
+//
+// The following defines are used to define the width of the length field for
+// CCM operation through the ui32Config argument in the AESConfig function.
+// This value is also known as L. Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CCM_L_2 0x00080000
+#define AES_CFG_CCM_L_4 0x00180000
+#define AES_CFG_CCM_L_8 0x00380000
+
+//*****************************************************************************
+//
+// The following defines are used to define the length of the authentication
+// field for CCM operations through the ui32Config argument in the AESConfig
+// function. This value is also known as M. Only one is permitted.
+//
+//*****************************************************************************
+#define AES_CFG_CCM_M_4 0x00400000
+#define AES_CFG_CCM_M_6 0x00800000
+#define AES_CFG_CCM_M_8 0x00c00000
+#define AES_CFG_CCM_M_10 0x01000000
+#define AES_CFG_CCM_M_12 0x01400000
+#define AES_CFG_CCM_M_14 0x01800000
+#define AES_CFG_CCM_M_16 0x01c00000
+
+//*****************************************************************************
+//
+// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
+// AESIntStatus functions.
+//
+//*****************************************************************************
+#define AES_INT_CONTEXT_IN 0x00000001
+#define AES_INT_CONTEXT_OUT 0x00000008
+#define AES_INT_DATA_IN 0x00000002
+#define AES_INT_DATA_OUT 0x00000004
+#define AES_INT_DMA_CONTEXT_IN 0x00010000
+#define AES_INT_DMA_CONTEXT_OUT 0x00020000
+#define AES_INT_DMA_DATA_IN 0x00040000
+#define AES_INT_DMA_DATA_OUT 0x00080000
+
+//*****************************************************************************
+//
+// Defines used when enabling and disabling DMA requests in the
+// AESEnableDMA and AESDisableDMA functions.
+//
+//*****************************************************************************
+#define AES_DMA_DATA_IN 0x00000040
+#define AES_DMA_DATA_OUT 0x00000020
+#define AES_DMA_CONTEXT_IN 0x00000080
+#define AES_DMA_CONTEXT_OUT 0x00000100
+
+//*****************************************************************************
+//
+// Function prototypes.
+//
+//*****************************************************************************
+extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key,
+ uint32_t ui32Keysize);
+extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key,
+ uint32_t ui32Keysize);
+extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key);
+extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
+extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData);
+extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length);
+extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
+ uint8_t ui8Length);
+extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
+ uint8_t ui8Length);
+extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
+ uint8_t ui8Length);
+extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
+ uint8_t ui8Length);
+extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
+ uint8_t *pui8Dest,
+ uint32_t ui32Length);
+extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src,
+ uint32_t ui32Length,
+ uint8_t *pui8Tag);
+extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src,
+ uint8_t *pui8Dest, uint32_t ui32Length,
+ uint8_t *pui8AuthSrc, uint32_t ui32AuthLength,
+ uint8_t *pui8Tag);
+extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
+extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
+extern void AESIntUnregister(uint32_t ui32Base);
+extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_AES_H__
diff --git a/cc3200/hal/cc3200_asm.h b/cc3200/hal/cc3200_asm.h
new file mode 100644
index 0000000000..37e828c838
--- /dev/null
+++ b/cc3200/hal/cc3200_asm.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef CC3200_ASM_H_
+#define CC3200_ASM_H_
+
+// We have inlined IRQ functions for efficiency (they are generally
+// 1 machine instruction).
+//
+// Note on IRQ state: you should not need to know the specific
+// value of the state variable, but rather just pass the return
+// value from disable_irq back to enable_irq. If you really need
+// to know the machine-specific values, see irq.h.
+
+#ifndef __disable_irq
+#define __disable_irq() __asm__ volatile ("cpsid i");
+#endif
+
+#ifndef DEBUG
+__attribute__(( always_inline ))
+static inline void __WFI(void) {
+ __asm volatile (" dsb \n"
+ " isb \n"
+ " wfi \n");
+}
+#else
+// For some reason the debugger gets disconnected when entering any of the sleep modes
+__attribute__(( always_inline ))
+static inline void __WFI(void) {
+ __asm volatile (" dsb \n"
+ " isb \n");
+}
+#endif
+
+__attribute__(( always_inline ))
+static inline uint32_t __get_PRIMASK(void) {
+ uint32_t result;
+ __asm volatile ("mrs %0, primask" : "=r" (result));
+ return(result);
+}
+
+__attribute__(( always_inline ))
+static inline void __set_PRIMASK(uint32_t priMask) {
+ __asm volatile ("msr primask, %0" : : "r" (priMask) : "memory");
+}
+
+__attribute__(( always_inline ))
+static inline void enable_irq(mp_uint_t state) {
+ __set_PRIMASK(state);
+}
+
+__attribute__(( always_inline ))
+static inline mp_uint_t disable_irq(void) {
+ mp_uint_t state = __get_PRIMASK();
+ __disable_irq();
+ return state;
+}
+
+#endif /* CC3200_ASM_H_ */
diff --git a/cc3200/hal/cc3200_hal.c b/cc3200/hal/cc3200_hal.c
new file mode 100644
index 0000000000..8424065c51
--- /dev/null
+++ b/cc3200/hal/cc3200_hal.c
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+ /******************************************************************************
+ IMPORTS
+ ******************************************************************************/
+#include
+#include
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "hw_memmap.h"
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "rom_map.h"
+#include "interrupt.h"
+#include "systick.h"
+#include "prcm.h"
+#include "sdhost.h"
+#include "pin.h"
+#include "mpexception.h"
+
+#ifdef USE_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+
+
+/******************************************************************************
+ DECLARE CONSTANTS
+ ******************************************************************************/
+#define HAL_SDCARD_FREQUENCY_HZ 15000000 // 15MHz
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+#ifndef USE_FREERTOS
+static void hal_TickInit (void);
+#endif
+#if MICROPY_HW_HAS_SDCARD
+static void hal_EnableSdCard (void);
+#endif
+
+/******************************************************************************
+ DECLARE LOCAL VARIABLES
+ ******************************************************************************/
+static volatile uint32_t HAL_tickCount;
+
+/******************************************************************************
+ DECLARE IMPORTED DATA
+ ******************************************************************************/
+extern void (* const g_pfnVectors[256])(void);
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+void HAL_SystemInit (void) {
+ MAP_IntVTableBaseSet((unsigned long)&g_pfnVectors[0]);
+
+ // in the case of a release image, these steps are already performed by
+ // the bootloader so we can skip it and gain some code space
+#ifndef NDEBUG
+ MAP_IntMasterEnable();
+ PRCMCC3200MCUInit();
+#endif
+
+#ifndef USE_FREERTOS
+ hal_TickInit();
+#endif
+#if MICROPY_HW_HAS_SDCARD
+ hal_EnableSdCard();
+#endif
+}
+
+void HAL_SystemDeInit (void) {
+}
+
+void HAL_IncrementTick(void) {
+ HAL_tickCount++;
+}
+
+uint32_t HAL_GetTick(void) {
+ return HAL_tickCount;
+}
+
+void HAL_Delay(uint32_t delay) {
+#ifdef USE_FREERTOS
+ vTaskDelay (delay / portTICK_PERIOD_MS);
+#else
+ uint32_t start = HAL_tickCount;
+ // Wraparound of tick is taken care of by 2's complement arithmetic.
+ while (HAL_tickCount - start < delay) {
+ // Enter sleep mode, waiting for (at least) the SysTick interrupt.
+ __WFI();
+ }
+#endif
+}
+
+void mp_hal_set_interrupt_char (int c) {
+ mpexception_set_interrupt_char (c);
+}
+
+/******************************************************************************
+ DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
+
+#ifndef USE_FREERTOS
+static void hal_TickInit (void) {
+ HAL_tickCount = 0;
+ MAP_SysTickIntRegister(HAL_IncrementTick);
+ MAP_IntEnable(FAULT_SYSTICK);
+ MAP_SysTickIntEnable();
+ MAP_SysTickPeriodSet(HAL_FCPU_HZ / HAL_SYSTICK_PERIOD_US);
+ // Force a reload of the SysTick counter register
+ HWREG(NVIC_ST_CURRENT) = 0;
+ MAP_SysTickEnable();
+}
+#endif
+
+#if MICROPY_HW_HAS_SDCARD
+static void hal_EnableSdCard (void) {
+ // Configure PIN_06 for SDHOST0 SDHost_D0
+ MAP_PinTypeSDHost(PIN_06, PIN_MODE_8);
+ // Configure PIN_07 for SDHOST0 SDHost_CLK
+ MAP_PinTypeSDHost(PIN_07, PIN_MODE_8);
+ // Configure PIN_08 for SDHOST0 SDHost_CMD
+ MAP_PinTypeSDHost(PIN_08, PIN_MODE_8);
+ // Set the SD card clock as an output pin
+ MAP_PinDirModeSet(PIN_07, PIN_DIR_MODE_OUT);
+ // Enable SD peripheral clock
+ MAP_PRCMPeripheralClkEnable(PRCM_SDHOST, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+ // Reset MMCHS
+ MAP_PRCMPeripheralReset(PRCM_SDHOST);
+ // Configure MMCHS
+ MAP_SDHostInit(SDHOST_BASE);
+ // Configure the card clock
+ MAP_SDHostSetExpClk(SDHOST_BASE, MAP_PRCMPeripheralClockGet(PRCM_SDHOST), HAL_SDCARD_FREQUENCY_HZ);
+}
+#endif
diff --git a/cc3200/hal/cc3200_hal.h b/cc3200/hal/cc3200_hal.h
new file mode 100644
index 0000000000..9562c827e8
--- /dev/null
+++ b/cc3200/hal/cc3200_hal.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef CC3200_LAUNCHXL_HAL_CC3200_HAL_H_
+#define CC3200_LAUNCHXL_HAL_CC3200_HAL_H_
+
+#include
+#include
+
+/******************************************************************************
+ DEFINE CONSTANTS
+ ******************************************************************************/
+
+#define HAL_FCPU_MHZ 80U
+#define HAL_FCPU_HZ (1000000U * HAL_FCPU_MHZ)
+#define HAL_SYSTICK_PERIOD_US 1000U
+#define UTILS_DELAY_US_TO_COUNT(us) (((us) * HAL_FCPU_MHZ) / 3)
+
+/******************************************************************************
+ DEFINE TYPES
+ ******************************************************************************/
+
+/******************************************************************************
+ DEFINE FUNCTION-LIKE MACROS
+ ******************************************************************************/
+
+#define HAL_INTRODUCE_SYNC_BARRIER() { \
+ __asm(" dsb \n" \
+ " isb \n"); \
+ }
+
+/******************************************************************************
+ DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+extern void HAL_SystemInit (void);
+extern void HAL_SystemDeInit (void);
+extern void HAL_IncrementTick(void);
+extern uint32_t HAL_GetTick(void);
+extern void HAL_Delay(uint32_t delay);
+extern void mp_hal_set_interrupt_char (int c);
+
+#endif /* CC3200_LAUNCHXL_HAL_CC3200_HAL_H_ */
diff --git a/cc3200/hal/cc_types.h b/cc3200/hal/cc_types.h
new file mode 100644
index 0000000000..40a94a6d9c
--- /dev/null
+++ b/cc3200/hal/cc_types.h
@@ -0,0 +1,58 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __CC_TYPES_H__
+#define __CC_TYPES_H__
+
+typedef unsigned long long u64;
+typedef unsigned long u32;
+typedef int i32;
+typedef unsigned short u16;
+typedef short i16;
+typedef unsigned char u8;
+typedef char i8;
+
+typedef void * cc_hndl;
+
+typedef u32 (*sys_irq_dsbl)();
+typedef void (*sys_irq_enbl)(u32 mask);
+#define UNUSED(x) ((x) = (x))
+
+#define INTRODUCE_SYNC_BARRIER() { \
+ __asm(" dsb \n" \
+ " isb \n"); \
+ }
+
+#endif //__CC_TYPES_H__
diff --git a/cc3200/hal/cpu.c b/cc3200/hal/cpu.c
new file mode 100644
index 0000000000..29d10afb25
--- /dev/null
+++ b/cc3200/hal/cpu.c
@@ -0,0 +1,412 @@
+//*****************************************************************************
+//
+// cpu.c
+//
+// Instruction wrappers for special CPU instructions needed by the
+// drivers.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+#include "cpu.h"
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUcpsid(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n"
+ " dsb \n"
+ " isb \n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n"
+ " dsb \n"
+ " isb \n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsid(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsid i\n"
+ " dsb \n"
+ " isb \n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function returning the state of PRIMASK (indicating whether
+// interrupts are enabled or disabled).
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUprimask(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUprimask(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUprimask(void)
+{
+ //
+ // Read PRIMASK and disable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
+// on entry.
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUcpsie(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n"
+ " dsb \n"
+ " isb \n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n"
+ " dsb \n"
+ " isb \n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUcpsie(void)
+{
+ //
+ // Read PRIMASK and enable interrupts.
+ //
+ __asm(" mrs r0, PRIMASK\n"
+ " cpsie i\n"
+ " dsb \n"
+ " isb \n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for the WFI instruction.
+//
+//*****************************************************************************
+#if defined(gcc)
+void __attribute__((naked))
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" dsb \n"
+ " isb \n"
+ " wfi \n"
+ " bx lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" dsb \n"
+ " isb \n"
+ " wfi \n");
+}
+#endif
+#if defined(ccs)
+void
+CPUwfi(void)
+{
+ //
+ // Wait for the next interrupt.
+ //
+ __asm(" dsb \n"
+ " isb \n"
+ " wfi \n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for writing the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(gcc)
+void __attribute__((naked))
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+
+ //
+ // Set the BASEPRI register
+ //
+ __asm(" msr BASEPRI, r0\n"
+ " dsb \n"
+ " isb \n"
+ " bx lr\n");
+}
+#endif
+#if defined(ewarm)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+ //
+ // Set the BASEPRI register
+ //
+ __asm(" msr BASEPRI, r0\n"
+ " dsb \n"
+ " isb \n");
+}
+#endif
+#if defined(ccs)
+void
+CPUbasepriSet(unsigned long ulNewBasepri)
+{
+ //
+ // Set the BASEPRI register
+ //
+ __asm(" msr BASEPRI, r0\n"
+ " dsb \n"
+ " isb \n");
+}
+#endif
+
+//*****************************************************************************
+//
+// Wrapper function for reading the BASEPRI register.
+//
+//*****************************************************************************
+#if defined(gcc)
+unsigned long __attribute__((naked))
+CPUbasepriGet(void)
+{
+ unsigned long ulRet;
+
+ //
+ // Read BASEPRI
+ //
+ __asm(" mrs r0, BASEPRI\n"
+ " bx lr\n"
+ : "=r" (ulRet));
+
+ //
+ // The return is handled in the inline assembly, but the compiler will
+ // still complain if there is not an explicit return here (despite the fact
+ // that this does not result in any code being produced because of the
+ // naked attribute).
+ //
+ return(ulRet);
+}
+#endif
+#if defined(ewarm)
+unsigned long
+CPUbasepriGet(void)
+{
+ //
+ // Read BASEPRI
+ //
+ __asm(" mrs r0, BASEPRI\n");
+
+ //
+ // "Warning[Pe940]: missing return statement at end of non-void function"
+ // is suppressed here to avoid putting a "bx lr" in the inline assembly
+ // above and a superfluous return statement here.
+ //
+#pragma diag_suppress=Pe940
+}
+#pragma diag_default=Pe940
+#endif
+#if defined(ccs)
+unsigned long
+CPUbasepriGet(void)
+{
+ //
+ // Read BASEPRI
+ //
+ __asm(" mrs r0, BASEPRI\n"
+ " bx lr\n");
+
+ //
+ // The following keeps the compiler happy, because it wants to see a
+ // return value from this function. It will generate code to return
+ // a zero. However, the real return is the "bx lr" above, so the
+ // return(0) is never executed and the function returns with the value
+ // you expect in R0.
+ //
+ return(0);
+}
+#endif
diff --git a/cc3200/hal/cpu.h b/cc3200/hal/cpu.h
new file mode 100644
index 0000000000..4a0fc0dcc0
--- /dev/null
+++ b/cc3200/hal/cpu.h
@@ -0,0 +1,75 @@
+//*****************************************************************************
+//
+// cpu.h
+//
+// Prototypes for the CPU instruction wrapper functions.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern unsigned long CPUprimask(void);
+extern void CPUwfi(void);
+extern unsigned long CPUbasepriGet(void);
+extern void CPUbasepriSet(unsigned long ulNewBasepri);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
diff --git a/cc3200/hal/crc.c b/cc3200/hal/crc.c
new file mode 100644
index 0000000000..9ccb92c385
--- /dev/null
+++ b/cc3200/hal/crc.c
@@ -0,0 +1,305 @@
+//*****************************************************************************
+//
+// crc.c
+//
+// Driver for the CRC module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup CRC_Cyclic_Redundancy_Check_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_dthe.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "crc.h"
+#include "debug.h"
+
+//*****************************************************************************
+//
+//! Set the configuration of CRC functionality with the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32CRCConfig is the configuration of the CRC engine.
+//!
+//! This function configures the operation of the CRC engine within the EC
+//! module. The configuration is specified with the \e ui32CRCConfig argument.
+//! It is the logical OR of any of the following options:
+//!
+//! CRC Initialization Value
+//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value
+//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s'
+//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s'
+//!
+//! Input Data Size
+//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits
+//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits
+//!
+//! Post Process Reverse/Inverse
+//! - \b EC_CRC_CFG_RESINV - Result inverse enable
+//! - \b EC_CRC_CFG_OBR - Output reverse enable
+//!
+//! Input Bit Reverse
+//! - \b EC_CRC_CFG_IBR - Bit reverse enable
+//!
+//! Endian Control
+//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word
+//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word
+//!
+//! Operation Type
+//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005
+//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021
+//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7
+//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41
+//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DTHE_BASE);
+ ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
+ (ui32CRCConfig & CRC_CFG_INIT_0) ||
+ (ui32CRCConfig & CRC_CFG_INIT_1) ||
+ (ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
+ (ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
+ (ui32CRCConfig & CRC_CFG_RESINV) ||
+ (ui32CRCConfig & CRC_CFG_OBR) ||
+ (ui32CRCConfig & CRC_CFG_IBR) ||
+ (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
+ (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
+ (ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
+ (ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
+ (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
+ (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
+ (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
+
+ //
+ // Write the control register with the configuration.
+ //
+ HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig;
+}
+
+//*****************************************************************************
+//
+//! Write the seed value for CRC operations in the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32Seed is the seed value.
+//!
+//! This function writes the seed value for use with CRC operations in the
+//! EC module. This value is the start value for CRC operations. If this
+//! value is not written, then the residual seed from the previous operation
+//! is used as the starting value.
+//!
+//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is
+//! set with the CRCConfigSet() function.
+//
+//*****************************************************************************
+void
+CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DTHE_BASE);
+
+ //
+ // Write the seed value to the seed register.
+ //
+ HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed;
+}
+
+//*****************************************************************************
+//
+//! Write data into the EC module for CRC operations.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param ui32Data is the data to be written.
+//!
+//! This function writes either 8 or 32 bits of data into the EC module for
+//! CRC operations. The distinction between 8 and 32 bits of data is made
+//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag
+//! is set using the CRCConfigSet() function.
+//!
+//! When writing 8 bits of data, ensure the data is in the least signficant
+//! byte position. The remaining bytes should be written with zero. For
+//! example, when writing 0xAB, \e ui32Data should be 0x000000AB.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DTHE_BASE);
+
+ //
+ // Write the data
+ //
+ HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data;
+}
+
+//*****************************************************************************
+//
+//! Reads the result of a CRC operation in the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//!
+//! This function reads either the unmodified CRC result or the post
+//! processed CRC result from the EC module. The post-processing options
+//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR
+//! parameters in the CRCConfigSet() function.
+//!
+//! \return The CRC result.
+//
+//*****************************************************************************
+uint32_t
+CRCResultRead(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DTHE_BASE);
+
+ //
+ // return value.
+ //
+ return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP));
+
+}
+
+//*****************************************************************************
+//
+//! Process data to generate a CRC with the EC module.
+//!
+//! \param ui32Base is the base address of the EC module.
+//! \param puiDataIn is a pointer to an array of data that is processed.
+//! \param ui32DataLength is the number of data items that are processed
+//! to produce the CRC.
+//! \param ui32Config the config parameter to determine the CRC mode
+//!
+//! This function processes an array of data to produce a CRC result.
+//! This function takes the CRC mode as the parameter.
+//!
+//! The data in the array pointed to be \e pui32DataIn is either an array
+//! of bytes or an array or words depending on the selection of the input
+//! data size options \b EC_CRC_CFG_SIZE_8BIT and
+//! \b EC_CRC_CFG_SIZE_32BIT.
+//!
+//! This function returns either the unmodified CRC result or the
+//! post- processed CRC result from the EC module. The post-processing
+//! options are selectable through \b EC_CRC_CFG_RESINV and
+//! \b EC_CRC_CFG_OBR parameters.
+//!
+//! \return The CRC result.
+//
+//*****************************************************************************
+uint32_t
+CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
+ uint32_t ui32DataLength, uint32_t ui32Config)
+{
+ uint8_t *pui8DataIn;
+ uint32_t *pui32DataIn;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DTHE_BASE);
+
+ //
+ // See if the CRC is operating in 8-bit or 32-bit mode.
+ //
+ if(ui32Config & DTHE_CRC_CTRL_SIZE)
+ {
+ //
+ // The CRC is operating in 8-bit mode, so create an 8-bit pointer to
+ // the data.
+ //
+ pui8DataIn = (uint8_t *)puiDataIn;
+
+ //
+ // Loop through the input data.
+ //
+ while(ui32DataLength--)
+ {
+ //
+ // Write the next data byte.
+ //
+ HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++;
+ }
+ }
+ else
+ {
+ //
+ // The CRC is operating in 32-bit mode, so loop through the input data.
+ //
+ pui32DataIn = (uint32_t *)puiDataIn;
+ while(ui32DataLength--)
+ {
+ //
+ // Write the next data word.
+ //
+ HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++;
+ }
+ }
+
+ //
+ // Return the result.
+ //
+ return(CRCResultRead(ui32Base));
+}
+
+
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/crc.h b/cc3200/hal/crc.h
new file mode 100644
index 0000000000..c0858bb1ba
--- /dev/null
+++ b/cc3200/hal/crc.h
@@ -0,0 +1,98 @@
+//*****************************************************************************
+//
+// crc.h
+//
+// Defines and Macros for CRC module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_CRC_H__
+#define __DRIVERLIB_CRC_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used in the ui32Config argument of the
+// ECConfig function.
+//
+//*****************************************************************************
+#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed
+#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s'
+#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s'
+#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size
+#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size
+#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable
+#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable
+#define CRC_CFG_IBR 0x00000080 // Bit reverse enable
+#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word
+#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word
+#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005
+#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021
+#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7
+#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41
+#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum
+
+//*****************************************************************************
+//
+// Function prototypes.
+//
+//*****************************************************************************
+extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
+extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
+ uint32_t ui32DataLength, uint32_t ui32Config);
+extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
+extern uint32_t CRCResultRead(uint32_t ui32Base);
+extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_CRC_H__
diff --git a/cc3200/hal/debug.h b/cc3200/hal/debug.h
new file mode 100644
index 0000000000..1f6556704e
--- /dev/null
+++ b/cc3200/hal/debug.h
@@ -0,0 +1,63 @@
+//*****************************************************************************
+//
+// debug.h
+//
+// Macros for assisting debug of the driver library.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+#ifndef __DEBUG_H__
+#define __DEBUG_H__
+
+#include "assert.h"
+
+//*****************************************************************************
+//
+// Prototype for the function that is called when an invalid argument is passed
+// to an API. This is only used when doing a DEBUG build.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// The ASSERT macro, which does the actual assertion checking. Typically, this
+// will be for procedure arguments.
+//
+//*****************************************************************************
+#if defined(DEBUG) && !defined(BOOTLOADER)
+#define ASSERT(expr) assert(expr)
+#else
+#define ASSERT(expr) (void)(expr)
+#endif
+
+#endif // __DEBUG_H__
diff --git a/cc3200/hal/des.c b/cc3200/hal/des.c
new file mode 100644
index 0000000000..ad8de1cc3c
--- /dev/null
+++ b/cc3200/hal/des.c
@@ -0,0 +1,887 @@
+//*****************************************************************************
+//
+// des.c
+//
+// Driver for the DES data transformation.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup DES_Data_Encryption_Standard_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_des.h"
+#include "inc/hw_dthe.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "debug.h"
+#include "des.h"
+#include "interrupt.h"
+
+
+//*****************************************************************************
+//
+//! Configures the DES module for operation.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Config is the configuration of the DES module.
+//!
+//! This function configures the DES module for operation.
+//!
+//! The \e ui32Config parameter is a bit-wise OR of a number of configuration
+//! flags. The valid flags are grouped below based on their function.
+//!
+//! The direction of the operation is specified with one of the following two
+//! flags. Only one is permitted.
+//!
+//! - \b DES_CFG_DIR_ENCRYPT - Encryption
+//! - \b DES_CFG_DIR_DECRYPT - Decryption
+//!
+//! The operational mode of the DES engine is specified with one of the
+//! following flags. Only one is permitted.
+//!
+//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode
+//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode
+//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode
+//!
+//! The selection of single DES or triple DES is specified with one of the
+//! following two flags. Only one is permitted.
+//!
+//! - \b DES_CFG_SINGLE - Single DES
+//! - \b DES_CFG_TRIPLE - Triple DES
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ //
+ // Backup the save context field.
+ //
+ ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT);
+
+ //
+ // Write the control register.
+ //
+ HWREG(ui32Base + DES_O_CTRL) = ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Sets the key used for DES operations.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Key is a pointer to an array that holds the key
+//!
+//! This function sets the key used for DES operations.
+//!
+//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or
+//! 192 bits (6 words) if triple DES is being used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESKeySet(uint32_t ui32Base, uint8_t *pui8Key)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ //
+ // Write the first part of the key.
+ //
+ HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0));
+ HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4));
+
+ //
+ // If we are performing triple DES, then write the key registers for
+ // the second and third rounds.
+ //
+ if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE)
+ {
+ HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8));
+ HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12));
+ HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16));
+ HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20));
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the initialization vector in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to
+//! be written into the initialization vectors registers.
+//!
+//! This function sets the initialization vector in the DES module. It returns
+//! true if the registers were successfully written. If the context registers
+//! cannot be written at the time the function was called, then false is
+//! returned.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ //
+ // Check to see if context registers can be overwritten. If not, return
+ // false.
+ //
+ if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0)
+ {
+ return(false);
+ }
+
+ //
+ // Write the initialization vector registers.
+ //
+ HWREG(ui32Base + DES_O_IV_L) = *((uint32_t *) (pui8IVdata + 0));
+ HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4));
+
+ //
+ // Return true to indicate the write was successful.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Sets the crytographic data length in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Length is the length of the data in bytes.
+//!
+//! This function writes the cryptographic data length into the DES module.
+//! When this register is written, the engine is triggersed to start using
+//! this context.
+//!
+//! \note Data lengths up to (2^32 - 1) bytes are allowed.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ //
+ // Write the length register.
+ //
+ HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Dest is a pointer to an array of 2 words.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function returns true if the data was ready when the function was
+//! called. If the data was not ready, false is returned.
+//!
+//! \return True or false.
+//
+//*****************************************************************************
+bool
+DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
+{
+ volatile uint32_t pui32Dest[2];
+ uint8_t ui8BytCnt;
+ uint8_t *pui8DestTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+ if((ui8Length == 0)||(ui8Length>8))
+ {
+ return(false);
+ }
+
+ //
+ // Check to see if the data is ready to be read.
+ //
+ if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
+ {
+ return(false);
+ }
+
+ //
+ // Read two words of data from the data registers.
+ //
+ pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
+ pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
+
+ //
+ //Copy the data to a block memory
+ //
+ pui8DestTemp = (uint8_t *)pui32Dest;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
+ }
+
+ //
+ // Return true to indicate a successful write.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Reads plaintext/ciphertext from data registers with blocking.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Dest is a pointer to an array of bytes.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function waits until the DES module is finished and encrypted or
+//! decrypted data is ready. The output data is then stored in the pui8Dest
+//! array.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
+{
+ volatile uint32_t pui32Dest[2];
+ uint8_t ui8BytCnt;
+ uint8_t *pui8DestTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+ if((ui8Length == 0)||(ui8Length>8))
+ {
+ return;
+ }
+ //
+ // Wait for data output to be ready.
+ //
+ while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0)
+ {
+ }
+
+ //
+ // Read two words of data from the data registers.
+ //
+ pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
+ pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
+
+ //
+ //Copy the data to a block memory
+ //
+ pui8DestTemp = (uint8_t *)pui32Dest;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
+ }
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Src is a pointer to an array of 2 words.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function returns false if the DES module is not ready to accept
+//! data. It returns true if the data was written successfully.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
+{
+
+ volatile uint32_t pui32Src[2]={0,0};
+ uint8_t ui8BytCnt;
+ uint8_t *pui8SrcTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ if((ui8Length == 0)||(ui8Length>8))
+ {
+ return(false);
+ }
+
+ //
+ // Check if the DES module is ready to encrypt or decrypt data. If it
+ // is not, return false.
+ //
+ if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))))
+ {
+ return(false);
+ }
+
+ //
+ // Copy the data to a block memory
+ //
+ pui8SrcTemp = (uint8_t *)pui32Src;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
+ }
+
+ //
+ // Write the data.
+ //
+ HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
+ HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
+
+ //
+ // Return true to indicate a successful write.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Writes plaintext/ciphertext to data registers without blocking
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Src is a pointer to an array of bytes.
+//! \param ui8Length the length can be from 1 to 8
+//!
+//! This function waits until the DES module is ready before writing the
+//! data contained in the pui8Src array.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
+{
+ volatile uint32_t pui32Src[2]={0,0};
+ uint8_t ui8BytCnt;
+ uint8_t *pui8SrcTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ if((ui8Length == 0)||(ui8Length>8))
+ {
+ return;
+ }
+
+ //
+ // Wait for the input ready bit to go high.
+ //
+ while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0)
+ {
+ }
+
+ //
+ //Copy the data to a block memory
+ //
+ pui8SrcTemp = (uint8_t *)pui32Src;
+ for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
+ {
+ *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
+ }
+
+ //
+ // Write the data.
+ //
+ HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
+ HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
+}
+
+//*****************************************************************************
+//
+//! Processes blocks of data through the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pui8Src is a pointer to an array of words that contains the
+//! source data for processing.
+//! \param pui8Dest is a pointer to an array of words consisting of the
+//! processed data.
+//! \param ui32Length is the length of the cryptographic data in bytes.
+//! It must be a multiple of eight.
+//!
+//! This function takes the data contained in the pui8Src array and processes
+//! it using the DES engine. The resulting data is stored in the
+//! pui8Dest array. The function blocks until all of the data has been
+//! processed. If processing is successful, the function returns true.
+//!
+//! \note This functions assumes that the DES module has been configured,
+//! and initialization values and keys have been written.
+//!
+//! \return true or false.
+//
+//*****************************************************************************
+bool
+DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
+ uint32_t ui32Length)
+{
+ uint32_t ui32Count, ui32BlkCount, ui32ByteCount;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+ ASSERT((ui32Length % 8) == 0);
+
+ //
+ // Write the length register first. This triggers the engine to start
+ // using this context.
+ //
+ HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
+
+
+ //
+ // Now loop until the blocks are written.
+ //
+ ui32BlkCount = ui32Length/8;
+ for(ui32Count = 0; ui32Count > 16);
+ HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
+}
+
+//*****************************************************************************
+//
+//! Disables interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
+//!
+//! This function disables interrupt sources in the DES module.
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DATA_IN - Data input interrupt
+//! - \b DES_INT_DATA_OUT - Data output interrupt
+//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+ ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
+ (ui32IntFlags & DES_INT_DATA_IN) ||
+ (ui32IntFlags & DES_INT_DATA_OUT) ||
+ (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+ (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+ (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+ //
+ // Clear the interrupts from the flags.
+ //
+ HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x00070000) >> 16);
+ HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
+}
+
+//*****************************************************************************
+//
+//! Clears interrupts in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
+//!
+//! This function disables interrupt sources in the DES module.
+//! \e ui32IntFlags should be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt
+//! - \b DES_INT_DMA_DATA_IN - Data input interrupt
+//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt
+//!
+//! \note The DMA done interrupts are the only interrupts that can be cleared.
+//! The remaining interrupts can be disabled instead using DESIntDisable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+ ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
+ (ui32IntFlags & DES_INT_DMA_DATA_IN) ||
+ (ui32IntFlags & DES_INT_DMA_DATA_OUT));
+
+ HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled DES interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables DES interrupts on the interrupt controller; specific DES
+//! interrupt sources must be enabled using DESIntEnable(). The interrupt
+//! handler being registered must clear the source of the interrupt using
+//! DESIntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() should be used to enable DES interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_DES, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(INT_DES);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESIntUnregister(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_DES);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_DES);
+}
+
+//*****************************************************************************
+//
+//! Enables DMA request sources in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Flags is a bit mask of the DMA requests to be enabled.
+//!
+//! This function enables DMA request sources in the DES module. The
+//! \e ui32Flags parameter should be the logical OR of any of the following:
+//!
+//! - \b DES_DMA_CONTEXT_IN - Context In
+//! - \b DES_DMA_DATA_OUT - Data Out
+//! - \b DES_DMA_DATA_IN - Data In
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+ ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
+ (ui32Flags & DES_DMA_DATA_OUT) ||
+ (ui32Flags & DES_DMA_DATA_IN));
+
+ //
+ // Set the data in and data out DMA request enable bits.
+ //
+ HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags;
+}
+
+//*****************************************************************************
+//
+//! Disables DMA request sources in the DES module.
+//!
+//! \param ui32Base is the base address of the DES module.
+//! \param ui32Flags is a bit mask of the DMA requests to be disabled.
+//!
+//! This function disables DMA request sources in the DES module. The
+//! \e ui32Flags parameter should be the logical OR of any of the following:
+//!
+//! - \b DES_DMA_CONTEXT_IN - Context In
+//! - \b DES_DMA_DATA_OUT - Data Out
+//! - \b DES_DMA_DATA_IN - Data In
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == DES_BASE);
+ ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
+ (ui32Flags & DES_DMA_DATA_OUT) ||
+ (ui32Flags & DES_DMA_DATA_IN));
+
+ //
+ // Disable the DMA sources.
+ //
+ HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/des.h b/cc3200/hal/des.h
new file mode 100644
index 0000000000..3bee5e6c9b
--- /dev/null
+++ b/cc3200/hal/des.h
@@ -0,0 +1,143 @@
+//*****************************************************************************
+//
+// des.h
+//
+// Defines and Macros for the DES module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_DES_H__
+#define __DRIVERLIB_DES_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following defines are used to specify the direction with the
+// ui32Config argument in the DESConfig() function. Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_DIR_DECRYPT 0x00000000
+#define DES_CFG_DIR_ENCRYPT 0x00000004
+
+//*****************************************************************************
+//
+// The following defines are used to specify the operational with the
+// ui32Config argument in the DESConfig() function. Only one is permitted.
+//
+//*****************************************************************************
+#define DES_CFG_MODE_ECB 0x00000000
+#define DES_CFG_MODE_CBC 0x00000010
+#define DES_CFG_MODE_CFB 0x00000020
+
+//*****************************************************************************
+//
+// The following defines are used to select between single DES and triple DES
+// with the ui32Config argument in the DESConfig() function. Only one is
+// permitted.
+//
+//*****************************************************************************
+#define DES_CFG_SINGLE 0x00000000
+#define DES_CFG_TRIPLE 0x00000008
+
+//*****************************************************************************
+//
+// The following defines are used with the DESIntEnable(), DESIntDisable() and
+// DESIntStatus() functions.
+//
+//*****************************************************************************
+#define DES_INT_CONTEXT_IN 0x00000001
+#define DES_INT_DATA_IN 0x00000002
+#define DES_INT_DATA_OUT 0x00000004
+#define DES_INT_DMA_CONTEXT_IN 0x00010000
+#define DES_INT_DMA_DATA_IN 0x00020000
+#define DES_INT_DMA_DATA_OUT 0x00040000
+
+//*****************************************************************************
+//
+// The following defines are used with the DESEnableDMA() and DESDisableDMA()
+// functions.
+//
+//*****************************************************************************
+#define DES_DMA_CONTEXT_IN 0x00000080
+#define DES_DMA_DATA_OUT 0x00000040
+#define DES_DMA_DATA_IN 0x00000020
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
+ uint8_t ui8Length);
+extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
+ uint8_t ui8Length);
+extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
+ uint8_t *pui8Dest, uint32_t ui32Length);
+extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
+ uint8_t ui8Length);
+extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
+ uint8_t ui8Length);
+extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
+extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
+extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
+extern void DESIntUnregister(uint32_t ui32Base);
+extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
+extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key);
+extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_DES_H__
diff --git a/cc3200/hal/fault_registers.h b/cc3200/hal/fault_registers.h
new file mode 100644
index 0000000000..739745e92a
--- /dev/null
+++ b/cc3200/hal/fault_registers.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef FAULT_REGISTERS_H_
+#define FAULT_REGISTERS_H_
+
+
+typedef struct
+{
+ uint32_t IERR :1;
+ uint32_t DERR :1;
+ uint32_t :1;
+ uint32_t MUSTKE :1;
+ uint32_t MSTKE :1;
+ uint32_t MLSPERR :1;
+ uint32_t :1;
+ uint32_t MMARV :1;
+ uint32_t IBUS :1;
+ uint32_t PRECISE :1;
+ uint32_t IMPRE :1;
+ uint32_t BUSTKE :1;
+ uint32_t BSTKE :1;
+ uint32_t BLSPERR :1;
+ uint32_t :1;
+ uint32_t BFARV :1;
+ uint32_t UNDEF :1;
+ uint32_t INVSTAT :1;
+ uint32_t INVCP :1;
+ uint32_t NOCP :1;
+ uint32_t :4;
+ uint32_t UNALIGN :1;
+ uint32_t DIVO0 :1;
+ uint32_t :6;
+
+}_CFSR_t;
+
+
+typedef struct
+{
+
+ uint32_t DBG :1;
+ uint32_t FORCED :1;
+ uint32_t :28;
+ uint32_t VECT :1;
+ uint32_t :1;
+
+}_HFSR_t;
+
+
+#endif /* FAULT_REGISTERS_H_ */
diff --git a/cc3200/hal/gpio.c b/cc3200/hal/gpio.c
new file mode 100644
index 0000000000..59aa71aa57
--- /dev/null
+++ b/cc3200/hal/gpio.c
@@ -0,0 +1,706 @@
+//*****************************************************************************
+//
+// gpio.c
+//
+// Driver for the GPIO module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup GPIO_General_Purpose_InputOutput_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_common_reg.h"
+#include "debug.h"
+#include "gpio.h"
+#include "interrupt.h"
+
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a GPIO base address.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function determines if a GPIO port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#if defined(DEBUG) && !defined(BOOTLOADER)
+static tBoolean
+GPIOBaseValid(unsigned long ulPort)
+{
+ return((ulPort == GPIOA0_BASE) ||
+ (ulPort == GPIOA1_BASE) ||
+ (ulPort == GPIOA2_BASE) ||
+ (ulPort == GPIOA3_BASE) ||
+ (ulPort == GPIOA4_BASE));
+}
+#else
+#define GPIOBaseValid(ulPort) (ulPort)
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the GPIO interrupt number.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! Given a GPIO base address, returns the corresponding interrupt number.
+//!
+//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
+//
+//*****************************************************************************
+static long
+GPIOGetIntNumber(unsigned long ulPort)
+{
+ unsigned int ulInt;
+
+ //
+ // Determine the GPIO interrupt number for the given module.
+ //
+ switch(ulPort)
+ {
+ case GPIOA0_BASE:
+ {
+ ulInt = INT_GPIOA0;
+ break;
+ }
+
+ case GPIOA1_BASE:
+ {
+ ulInt = INT_GPIOA1;
+ break;
+ }
+
+ case GPIOA2_BASE:
+ {
+ ulInt = INT_GPIOA2;
+ break;
+ }
+
+ case GPIOA3_BASE:
+ {
+ ulInt = INT_GPIOA3;
+ break;
+ }
+
+ default:
+ {
+ return(-1);
+ }
+ }
+
+ //
+ // Return GPIO interrupt number.
+ //
+ return(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Sets the direction and mode of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulPinIO is the pin direction and/or mode.
+//!
+//! This function will set the specified pin(s) on the selected GPIO port
+//! as either an input or output under software control, or it will set the
+//! pin to be under hardware control.
+//!
+//! The parameter \e ulPinIO is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_DIR_MODE_IN
+//! - \b GPIO_DIR_MODE_OUT
+//!
+//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
+//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
+//! will be programmed as a software controlled output.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note GPIOPadConfigSet() must also be used to configure the corresponding
+//! pad(s) in order for them to propagate the signal to/from the GPIO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT));
+
+ //
+ // Set the pin direction and mode.
+ //
+ HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ?
+ (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) :
+ (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the direction and mode of a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the direction and control mode for a specified pin on
+//! the selected GPIO port. The pin can be configured as either an input or
+//! output under software control, or it can be under hardware control. The
+//! type of control and direction are returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIODirModeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulDir;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the pin direction
+ //
+ ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR);
+ return(((ulDir & ucPin) ? 1 : 0));
+}
+
+//*****************************************************************************
+//
+//! Sets the interrupt type for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ulIntType specifies the type of interrupt trigger mechanism.
+//!
+//! This function sets up the various interrupt trigger mechanisms for the
+//! specified pin(s) on the selected GPIO port.
+//!
+//! The parameter \e ulIntType is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b GPIO_FALLING_EDGE
+//! - \b GPIO_RISING_EDGE
+//! - \b GPIO_BOTH_EDGES
+//! - \b GPIO_LOW_LEVEL
+//! - \b GPIO_HIGH_LEVEL
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \note In order to avoid any spurious interrupts, the user must
+//! ensure that the GPIO inputs remain stable for the duration of
+//! this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+ ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
+ (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
+ (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
+
+ //
+ // Set the pin interrupt type.
+ //
+ HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ?
+ (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) :
+ (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ?
+ (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) :
+ (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins)));
+ HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ?
+ (HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) :
+ (HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins)));
+}
+
+//*****************************************************************************
+//
+//! Gets the interrupt type for a pin.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPin is the pin number.
+//!
+//! This function gets the interrupt type for a specified pin on the selected
+//! GPIO port. The pin can be configured as a falling edge, rising edge, or
+//! both edge detected interrupt, or it can be configured as a low level or
+//! high level detected interrupt. The type of interrupt detection mechanism
+//! is returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIOIntTypeSet().
+//
+//*****************************************************************************
+unsigned long
+GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
+{
+ unsigned long ulIBE, ulIS, ulIEV;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the pin interrupt type.
+ //
+ ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE);
+ ulIS = HWREG(ulPort + GPIO_O_GPIO_IS);
+ ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV);
+ return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
+ ((ulIEV & ucPin) ? 4 : 0));
+}
+
+//*****************************************************************************
+//
+//! Enables the specified GPIO interrupts.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to enable.
+//!
+//! This function enables the indicated GPIO interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
+//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
+//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
+//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
+//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
+//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
+//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
+//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
+//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Enable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the specified GPIO interrupts.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to disable.
+//!
+//! This function disables the indicated GPIO interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
+//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
+//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
+//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
+//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
+//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
+//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
+//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
+//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Disable the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets interrupt status for the specified GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param bMasked specifies whether masked or raw interrupt status is
+//! returned.
+//!
+//! If \e bMasked is set as \b true, then the masked interrupt status is
+//! returned; otherwise, the raw interrupt status will be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in GPIOIntEnable().
+//
+//*****************************************************************************
+long
+GPIOIntStatus(unsigned long ulPort, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the interrupt status.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulPort + GPIO_O_GPIO_MIS));
+ }
+ else
+ {
+ return(HWREG(ulPort + GPIO_O_GPIO_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the interrupt for the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! Clears the interrupt for the specified pin(s).
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to GPIOIntEnable().
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Clear the interrupts.
+ //
+ HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
+//! function.
+//!
+//! This function will ensure that the interrupt handler specified by
+//! \e pfnIntHandler is called when an interrupt is detected from the selected
+//! GPIO port. This function will also enable the corresponding GPIO interrupt
+//! in the interrupt controller; individual pin interrupts and interrupt
+//! sources must be enabled with GPIOIntEnable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulPort, pfnIntHandler);
+
+ //
+ // Enable the GPIO interrupt.
+ //
+ IntEnable(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Removes an interrupt handler for a GPIO port.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function will unregister the interrupt handler for the specified
+//! GPIO port. This function will also disable the corresponding
+//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
+//! and interrupt sources must be disabled with GPIOIntDisable().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOIntUnregister(unsigned long ulPort)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Get the interrupt number associated with the specified GPIO.
+ //
+ ulPort = GPIOGetIntNumber(ulPort);
+
+ //
+ // Disable the GPIO interrupt.
+ //
+ IntDisable(ulPort);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulPort);
+}
+
+//*****************************************************************************
+//
+//! Reads the values present of the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//!
+//! The values at the specified pin(s) are read, as specified by \e ucPins.
+//! Values are returned for both input and output pin(s), and the value
+//! for pin(s) that are not specified by \e ucPins are set to 0.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return Returns a bit-packed byte providing the state of the specified
+//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
+//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
+//! is returned as a 0. Bits 31:8 should be ignored.
+//
+//*****************************************************************************
+long
+GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Return the pin value(s).
+ //
+ return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))));
+}
+
+//*****************************************************************************
+//
+//! Writes a value to the specified pin(s).
+//!
+//! \param ulPort is the base address of the GPIO port.
+//! \param ucPins is the bit-packed representation of the pin(s).
+//! \param ucVal is the value to write to the pin(s).
+//!
+//! Writes the corresponding bit values to the output pin(s) specified by
+//! \e ucPins. Writing to a pin configured as an input pin has no effect.
+//!
+//! The pin(s) are specified using a bit-packed byte, where each bit that is
+//! set identifies the pin to be accessed, and where bit 0 of the byte
+//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Write the pins.
+ //
+ HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal;
+}
+
+//*****************************************************************************
+//
+//! Enables a GPIO port as a trigger to start a DMA transaction.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function enables a GPIO port to be used as a trigger to start a uDMA
+//! transaction. The GPIO pin will still generate interrupts if the interrupt is
+//! enabled for the selected pin.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODMATriggerEnable(unsigned long ulPort)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Set the pin as a DMA trigger.
+ //
+ if(ulPort == GPIOA0_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1;
+ }
+ else if(ulPort == GPIOA1_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2;
+ }
+ else if(ulPort == GPIOA2_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4;
+ }
+ else if(ulPort == GPIOA3_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables a GPIO port as a trigger to start a DMA transaction.
+//!
+//! \param ulPort is the base address of the GPIO port.
+//!
+//! This function disables a GPIO port to be used as a trigger to start a uDMA
+//! transaction. This function can be used to disable this feature if it was
+//! enabled via a call to GPIODMATriggerEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+GPIODMATriggerDisable(unsigned long ulPort)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(GPIOBaseValid(ulPort));
+
+ //
+ // Set the pin as a DMA trigger.
+ //
+ if(ulPort == GPIOA0_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1;
+ }
+ else if(ulPort == GPIOA1_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2;
+ }
+ else if(ulPort == GPIOA2_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4;
+ }
+ else if(ulPort == GPIOA3_BASE)
+ {
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8;
+ }
+}
+
+
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/gpio.h b/cc3200/hal/gpio.h
new file mode 100644
index 0000000000..35acf79a60
--- /dev/null
+++ b/cc3200/hal/gpio.h
@@ -0,0 +1,139 @@
+//*****************************************************************************
+//
+// gpio.h
+//
+// Defines and Macros for GPIO API.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ucPins argument to several
+// of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
+// returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
+#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
+// in the ulIntFlags parameter.
+//
+//*****************************************************************************
+#define GPIO_INT_DMA 0x00000100
+#define GPIO_INT_PIN_0 0x00000001
+#define GPIO_INT_PIN_1 0x00000002
+#define GPIO_INT_PIN_2 0x00000004
+#define GPIO_INT_PIN_3 0x00000008
+#define GPIO_INT_PIN_4 0x00000010
+#define GPIO_INT_PIN_5 0x00000020
+#define GPIO_INT_PIN_6 0x00000040
+#define GPIO_INT_PIN_7 0x00000080
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO);
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType);
+extern void GPIODMATriggerEnable(unsigned long ulPort);
+extern void GPIODMATriggerDisable(unsigned long ulPort);
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags);
+extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags);
+extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked);
+extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags);
+extern void GPIOIntRegister(unsigned long ulPort,
+ void (*pfnIntHandler)(void));
+extern void GPIOIntUnregister(unsigned long ulPort);
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
+ unsigned char ucVal);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPIO_H__
diff --git a/cc3200/hal/i2c.c b/cc3200/hal/i2c.c
new file mode 100644
index 0000000000..5208687674
--- /dev/null
+++ b/cc3200/hal/i2c.c
@@ -0,0 +1,2057 @@
+//*****************************************************************************
+//
+// i2c.c
+//
+// Driver for Inter-IC (I2C) bus block.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup I2C_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_i2c.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "debug.h"
+#include "i2c.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// A mapping of I2C base address to interrupt number.
+//
+//*****************************************************************************
+static const uint32_t g_ppui32I2CIntMap[][2] =
+{
+ { I2CA0_BASE, INT_I2CA0},
+};
+
+static const int_fast8_t g_i8I2CIntMapRows =
+ sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]);
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks an I2C base address.
+//!
+//! \param ui32Base is the base address of the I2C module.
+//!
+//! This function determines if a I2C module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static bool
+_I2CBaseValid(uint32_t ui32Base)
+{
+ return((ui32Base == I2CA0_BASE));
+}
+#else
+#define _I2CBaseValid(ui32Base) (ui32Base)
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the I2C interrupt number.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! Given a I2C base address, this function returns the corresponding
+//! interrupt number.
+//!
+//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid.
+//
+//*****************************************************************************
+static uint32_t
+_I2CIntNumberGet(uint32_t ui32Base)
+{
+ int_fast8_t i8Idx, i8Rows;
+ const uint32_t (*ppui32I2CIntMap)[2];
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ ppui32I2CIntMap = g_ppui32I2CIntMap;
+ i8Rows = g_i8I2CIntMapRows;
+
+ //
+ // Loop through the table that maps I2C base addresses to interrupt
+ // numbers.
+ //
+ for(i8Idx = 0; i8Idx < i8Rows; i8Idx++)
+ {
+ //
+ // See if this base address matches.
+ //
+ if(ppui32I2CIntMap[i8Idx][0] == ui32Base)
+ {
+ //
+ // Return the corresponding interrupt number.
+ //
+ return(ppui32I2CIntMap[i8Idx][1]);
+ }
+ }
+
+ //
+ // The base address could not be found, so return an error.
+ //
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Initializes the I2C Master block.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui32I2CClk is the rate of the clock supplied to the I2C module.
+//! \param bFast set up for fast data transfers.
+//!
+//! This function initializes operation of the I2C Master block by configuring
+//! the bus speed for the master and enabling the I2C Master block.
+//!
+//! If the parameter \e bFast is \b true, then the master block is set up to
+//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at
+//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually
+//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps)
+//! mode, a specific command is used to switch to the faster clocks after the
+//! initial communication with the slave is done at either 100 Kbps or
+//! 400 Kbps.
+//!
+//! The peripheral clock is the same as the processor clock. This value is
+//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
+//! constant and known (to save the code/execution overhead of a call to
+//! SysCtlClockGet()).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
+ bool bFast)
+{
+ uint32_t ui32SCLFreq;
+ uint32_t ui32TPR;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Must enable the device before doing anything else.
+ //
+ I2CMasterEnable(ui32Base);
+
+ //
+ // Get the desired SCL speed.
+ //
+ if(bFast == true)
+ {
+ ui32SCLFreq = 400000;
+ }
+ else
+ {
+ ui32SCLFreq = 100000;
+ }
+
+ //
+ // Compute the clock divider that achieves the fastest speed less than or
+ // equal to the desired speed. The numerator is biased to favor a larger
+ // clock divider so that the resulting clock is always less than or equal
+ // to the desired clock, never greater.
+ //
+ ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) /
+ (2 * 10 * ui32SCLFreq)) - 1;
+ HWREG(ui32Base + I2C_O_MTPR) = ui32TPR;
+
+ //
+ // Check to see if this I2C peripheral is High-Speed enabled. If yes, also
+ // choose the fastest speed that is less than or equal to 3.4 Mbps.
+ //
+ if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS)
+ {
+ ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) /
+ (2 * 3 * 3400000)) - 1;
+ HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR;
+ }
+}
+
+//*****************************************************************************
+//
+//! Initializes the I2C Slave block.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui8SlaveAddr 7-bit slave address
+//!
+//! This function initializes operation of the I2C Slave block by configuring
+//! the slave address and enabling the I2C Slave block.
+//!
+//! The parameter \e ui8SlaveAddr is the value that is compared against the
+//! slave address sent by an I2C master.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+ ASSERT(!(ui8SlaveAddr & 0x80));
+
+ //
+ // Must enable the device before doing anything else.
+ //
+ I2CSlaveEnable(ui32Base);
+
+ //
+ // Set up the slave address.
+ //
+ HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
+}
+
+//*****************************************************************************
+//
+//! Sets the I2C slave address.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui8AddrNum determines which slave address is set.
+//! \param ui8SlaveAddr is the 7-bit slave address
+//!
+//! This function writes the specified slave address. The \e ui32AddrNum field
+//! dictates which slave address is configured. For example, a value of 0
+//! configures the primary address and a value of 1 configures the secondary.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+ ASSERT(!(ui8AddrNum > 1));
+ ASSERT(!(ui8SlaveAddr & 0x80));
+
+ //
+ // Determine which slave address is being set.
+ //
+ switch(ui8AddrNum)
+ {
+ //
+ // Set up the primary slave address.
+ //
+ case 0:
+ {
+ HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr;
+ break;
+ }
+
+ //
+ // Set up and enable the secondary slave address.
+ //
+ case 1:
+ {
+ HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr;
+ break;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master block.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function enables operation of the I2C Master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable the master block.
+ //
+ HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave block.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! This fucntion enables operation of the I2C Slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable the clock to the slave block.
+ //
+ HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE;
+
+ //
+ // Enable the slave.
+ //
+ HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C master block.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function disables operation of the I2C master block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Disable the master block.
+ //
+ HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE);
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C slave block.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! This function disables operation of the I2C slave block.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Disable the slave.
+ //
+ HWREG(ui32Base + I2C_O_SCSR) = 0;
+
+ //
+ // Disable the clock to the slave block.
+ //
+ HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the I2C module.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! I2C interrupt occurs.
+//!
+//! This function sets the handler to be called when an I2C interrupt occurs.
+//! This function enables the global interrupt in the interrupt controller;
+//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and
+//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's
+//! responsibility to clear the interrupt source via I2CMasterIntClear() and
+//! I2CSlaveIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void))
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Determine the interrupt number based on the I2C port.
+ //
+ ui32Int = _I2CIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(ui32Int, pfnHandler);
+
+ //
+ // Enable the I2C interrupt.
+ //
+ IntEnable(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the I2C module.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function clears the handler to be called when an I2C interrupt
+//! occurs. This function also masks off the interrupt in the interrupt r
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CIntUnregister(uint32_t ui32Base)
+{
+ uint32_t ui32Int;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Determine the interrupt number based on the I2C port.
+ //
+ ui32Int = _I2CIntNumberGet(ui32Base);
+
+ ASSERT(ui32Int != 0);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ui32Int);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ui32Int);
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Master interrupt.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function enables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable the master interrupt.
+ //
+ HWREG(ui32Base + I2C_O_MIMR) = 1;
+}
+
+//*****************************************************************************
+//
+//! Enables individual I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated I2C Master interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt
+//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
+//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt
+//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt
+//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt
+//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt
+//! - \b I2C_MASTER_INT_START - Start Condition interrupt
+//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt
+//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt
+//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt
+//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt
+//! - \b I2C_MASTER_INT_DATA - Data interrupt
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable the master interrupt.
+ //
+ HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enables the I2C Slave interrupt.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! This function enables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable the slave interrupt.
+ //
+ HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Enables individual I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated I2C Slave interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt
+//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
+//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt
+//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt
+//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt
+//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt
+//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt
+//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt
+//! - \b I2C_SLAVE_INT_DATA - Data interrupt
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable the slave interrupt.
+ //
+ HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Master interrupt.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function disables the I2C Master interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Disable the master interrupt.
+ //
+ HWREG(ui32Base + I2C_O_MIMR) = 0;
+}
+
+//*****************************************************************************
+//
+//! Disables individual I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated I2C Master interrupt sources. Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CMasterIntEnableEx().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Disable the master interrupt.
+ //
+ HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the I2C Slave interrupt.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! This function disables the I2C Slave interrupt source.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Disable the slave interrupt.
+ //
+ HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA;
+}
+
+//*****************************************************************************
+//
+//! Disables individual I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui32IntFlags is the bit mask of the interrupt sources to be
+//! disabled.
+//!
+//! This function disables the indicated I2C Slave interrupt sources. Only
+//! the sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Disable the slave interrupt.
+ //
+ HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Master interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C Master module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+bool
+I2CMasterIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false);
+ }
+ else
+ {
+ return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Master interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C Master module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in I2CMasterIntEnableEx().
+//
+//*****************************************************************************
+uint32_t
+I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ui32Base + I2C_O_MMIS));
+ }
+ else
+ {
+ return(HWREG(ui32Base + I2C_O_MRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C Slave module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, returned as \b true if active
+//! or \b false if not active.
+//
+//*****************************************************************************
+bool
+I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false);
+ }
+ else
+ {
+ return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current I2C Slave interrupt status.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param bMasked is false if the raw interrupt status is requested and
+//! true if the masked interrupt status is requested.
+//!
+//! This function returns the interrupt status for the I2C Slave module.
+//! Either the raw interrupt status or the status of interrupts that are
+//! allowed to reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in I2CSlaveIntEnableEx().
+//
+//*****************************************************************************
+uint32_t
+I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ui32Base + I2C_O_SMIS));
+ }
+ else
+ {
+ return(HWREG(ui32Base + I2C_O_SRIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! The I2C Master interrupt source is cleared, so that it no longer
+//! asserts. This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntClear(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Clear the I2C master interrupt source.
+ //
+ HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC;
+
+ //
+ // Workaround for I2C master interrupt clear errata for some
+ // devices. For later devices, this write is ignored and therefore
+ // harmless (other than the slight performance hit).
+ //
+ HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Master interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified I2C Master interrupt sources are cleared, so that they no
+//! longer assert. This function must be called in the interrupt handler to
+//! keep the interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CMasterIntEnableEx().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Clear the I2C master interrupt source.
+ //
+ HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! The I2C Slave interrupt source is cleared, so that it no longer asserts.
+//! This function must be called in the interrupt handler to keep the interrupt
+//! from being triggered again immediately upon exit.
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClear(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Clear the I2C slave interrupt source.
+ //
+ HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC;
+}
+
+//*****************************************************************************
+//
+//! Clears I2C Slave interrupt sources.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified I2C Slave interrupt sources are cleared, so that they no
+//! longer assert. This function must be called in the interrupt handler to
+//! keep the interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ui32IntFlags parameter has the same definition as the
+//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx().
+//!
+//! \note Because there is a write buffer in the Cortex-M processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Clear the I2C slave interrupt source.
+ //
+ HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags;
+}
+
+//*****************************************************************************
+//
+//! Sets the address that the I2C Master places on the bus.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui8SlaveAddr 7-bit slave address
+//! \param bReceive flag indicating the type of communication with the slave
+//!
+//! This function configures the address that the I2C Master places on the
+//! bus when initiating a transaction. When the \e bReceive parameter is set
+//! to \b true, the address indicates that the I2C Master is initiating a
+//! read from the slave; otherwise the address indicates that the I2C
+//! Master is initiating a write to the slave.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr,
+ bool bReceive)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+ ASSERT(!(ui8SlaveAddr & 0x80));
+
+ //
+ // Set the address of the slave with which the master will communicate.
+ //
+ HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive;
+}
+
+//*****************************************************************************
+//
+//! Reads the state of the SDA and SCL pins.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function returns the state of the I2C bus by providing the real time
+//! values of the SDA and SCL pins.
+//!
+//!
+//! \return Returns the state of the bus with SDA in bit position 1 and SCL in
+//! bit position 0.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterLineStateGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return the line state.
+ //
+ return(HWREG(ui32Base + I2C_O_MBMON));
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C Master is busy.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function returns an indication of whether or not the I2C Master is
+//! busy transmitting or receiving data.
+//!
+//! \return Returns \b true if the I2C Master is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+bool
+I2CMasterBusy(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return the busy status.
+ //
+ if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Indicates whether or not the I2C bus is busy.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function returns an indication of whether or not the I2C bus is busy.
+//! This function can be used in a multi-master environment to determine if
+//! another master is currently using the bus.
+//!
+//! \return Returns \b true if the I2C bus is busy; otherwise, returns
+//! \b false.
+//
+//*****************************************************************************
+bool
+I2CMasterBusBusy(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return the bus busy status.
+ //
+ if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY)
+ {
+ return(true);
+ }
+ else
+ {
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Controls the state of the I2C Master module.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui32Cmd command to be issued to the I2C Master module.
+//!
+//! This function is used to control the state of the Master module send and
+//! receive operations. The \e ui8Cmd parameter can be one of the following
+//! values:
+//!
+//! - \b I2C_MASTER_CMD_SINGLE_SEND
+//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE
+//! - \b I2C_MASTER_CMD_BURST_SEND_START
+//! - \b I2C_MASTER_CMD_BURST_SEND_CONT
+//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH
+//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH
+//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
+//! - \b I2C_MASTER_CMD_QUICK_COMMAND
+//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND
+//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND
+//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH
+//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH
+//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+ ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) ||
+ (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) ||
+ (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) ||
+ (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) ||
+ (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) ||
+ (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND));
+
+ //
+ // Send the command.
+ //
+ HWREG(ui32Base + I2C_O_MCS) = ui32Cmd;
+}
+
+//*****************************************************************************
+//
+//! Gets the error status of the I2C Master module.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function is used to obtain the error status of the Master module send
+//! and receive operations.
+//!
+//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE,
+//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or
+//! \b I2C_MASTER_ERR_ARB_LOST.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterErr(uint32_t ui32Base)
+{
+ uint32_t ui32Err;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Get the raw error state
+ //
+ ui32Err = HWREG(ui32Base + I2C_O_MCS);
+
+ //
+ // If the I2C master is busy, then all the other bit are invalid, and
+ // don't have an error to report.
+ //
+ if(ui32Err & I2C_MCS_BUSY)
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+
+ //
+ // Check for errors.
+ //
+ if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST))
+ {
+ return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_ACK | I2C_MCS_ADRACK));
+ }
+ else
+ {
+ return(I2C_MASTER_ERR_NONE);
+ }
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Master.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui8Data data to be transmitted from the I2C Master.
+//!
+//! This function places the supplied data into I2C Master Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Write the byte.
+ //
+ HWREG(ui32Base + I2C_O_MDR) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Master.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function reads a byte of data from the I2C Master Data Register.
+//!
+//! \return Returns the byte received from by the I2C Master, cast as an
+//! uint32_t.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterDataGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Read a byte.
+ //
+ return(HWREG(ui32Base + I2C_O_MDR));
+}
+
+//*****************************************************************************
+//
+//! Sets the Master clock timeout value.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui32Value is the number of I2C clocks before the timeout is
+//! asserted.
+//!
+//! This function enables and configures the clock low timeout feature in the
+//! I2C peripheral. This feature is implemented as a 12-bit counter, with the
+//! upper 8-bits being programmable. For example, to program a timeout of 20ms
+//! with a 100kHz SCL frequency, \e ui32Value would be 0x7d.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Write the timeout value.
+ //
+ HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value;
+}
+
+//*****************************************************************************
+//
+//! Configures ACK override behavior of the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param bEnable enables or disables ACK override.
+//!
+//! This function enables or disables ACK override, allowing the user
+//! application to drive the value on SDA during the ACK cycle.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable or disable based on bEnable.
+ //
+ if(bEnable)
+ {
+ HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN;
+ }
+ else
+ {
+ HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Writes the ACK value.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer.
+//!
+//! This function puts the desired ACK value on SDA during the ACK cycle. The
+//! value written is only valid when ACK override is enabled using
+//! I2CSlaveACKOverride().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // ACK or NACK based on the value of bACK.
+ //
+ if(bACK)
+ {
+ HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL;
+ }
+ else
+ {
+ HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the I2C Slave module status
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! This function returns the action requested from a master, if any.
+//! Possible values are:
+//!
+//! - \b I2C_SLAVE_ACT_NONE
+//! - \b I2C_SLAVE_ACT_RREQ
+//! - \b I2C_SLAVE_ACT_TREQ
+//! - \b I2C_SLAVE_ACT_RREQ_FBR
+//! - \b I2C_SLAVE_ACT_OWN2SEL
+//! - \b I2C_SLAVE_ACT_QCMD
+//! - \b I2C_SLAVE_ACT_QCMD_DATA
+//!
+//! \note Not all devices support the second I2C slave's own address
+//! or the quick command function. Please consult the device data sheet to
+//! determine if these features are supported.
+//!
+//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been
+//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that
+//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ
+//! to indicate that an I2C master has requested that the I2C Slave module send
+//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent
+//! data to the I2C slave and the first byte following the slave's own address
+//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C
+//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick
+//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the
+//! data bit was set when the quick command was received.
+//
+//*****************************************************************************
+uint32_t
+I2CSlaveStatus(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return the slave status.
+ //
+ return(HWREG(ui32Base + I2C_O_SCSR));
+}
+
+//*****************************************************************************
+//
+//! Transmits a byte from the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui8Data is the data to be transmitted from the I2C Slave
+//!
+//! This function places the supplied data into I2C Slave Data Register.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Write the byte.
+ //
+ HWREG(ui32Base + I2C_O_SDR) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! Receives a byte that has been sent to the I2C Slave.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! This function reads a byte of data from the I2C Slave Data Register.
+//!
+//! \return Returns the byte received from by the I2C Slave, cast as an
+//! uint32_t.
+//
+//*****************************************************************************
+uint32_t
+I2CSlaveDataGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Read a byte.
+ //
+ return(HWREG(ui32Base + I2C_O_SDR));
+}
+
+//*****************************************************************************
+//
+//! Configures the I2C transmit (TX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//! \param ui32Config is the configuration of the FIFO using specified macros.
+//!
+//! This configures the I2C peripheral's transmit FIFO. The transmit FIFO can
+//! be used by the master or slave, but not both. The following macros are
+//! used to configure the TX FIFO behavior for master or slave, with or without
+//! DMA:
+//!
+//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE,
+//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA
+//!
+//! To select the trigger level, one of the following macros should be used:
+//!
+//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2,
+//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4,
+//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6,
+//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Clear transmit configuration data.
+ //
+ HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000;
+
+ //
+ // Store new transmit configuration data.
+ //
+ HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Flushes the transmit (TX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//!
+//! This function flushes the I2C transmit FIFO.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CTxFIFOFlush(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Flush the TX FIFO.
+ //
+ HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH;
+}
+
+//*****************************************************************************
+//
+//! Configures the I2C receive (RX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//! \param ui32Config is the configuration of the FIFO using specified macros.
+//!
+//! This configures the I2C peripheral's receive FIFO. The receive FIFO can be
+//! used by the master or slave, but not both. The following macros are used
+//! to configure the RX FIFO behavior for master or slave, with or without DMA:
+//!
+//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE,
+//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA
+//!
+//! To select the trigger level, one of the following macros should be used:
+//!
+//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2,
+//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4,
+//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6,
+//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Clear receive configuration data.
+ //
+ HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff;
+
+ //
+ // Store new receive configuration data.
+ //
+ HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Flushes the receive (RX) FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//!
+//! This function flushes the I2C receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CRxFIFOFlush(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Flush the TX FIFO.
+ //
+ HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH;
+}
+
+//*****************************************************************************
+//
+//! Gets the current FIFO status.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//!
+//! This function retrieves the status for both the transmit (TX) and receive
+//! (RX) FIFOs. The trigger level for the transmit FIFO is set using
+//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet().
+//!
+//! \return Returns the FIFO status, enumerated as a bit field containing
+//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY,
+//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and
+//! \b I2C_FIFO_TX_EMPTY.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFOStatus(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Return the contents of the FIFO status register.
+ //
+ return(HWREG(ui32Base + I2C_O_FIFOSTATUS));
+}
+
+//*****************************************************************************
+//
+//! Writes a data byte to the I2C transmit FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//! \param ui8Data is the data to be placed into the transmit FIFO.
+//!
+//! This function adds a byte of data to the I2C transmit FIFO. If there is
+//! no space available in the FIFO, this function waits for space to become
+//! available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Wait until there is space.
+ //
+ while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
+ {
+ }
+
+ //
+ // Place data into the FIFO.
+ //
+ HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
+}
+
+//*****************************************************************************
+//
+//! Writes a data byte to the I2C transmit FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//! \param ui8Data is the data to be placed into the transmit FIFO.
+//!
+//! This function adds a byte of data to the I2C transmit FIFO. If there is
+//! no space available in the FIFO, this function returns a zero.
+//!
+//! \return The number of elements added to the I2C transmit FIFO.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // If FIFO is full, return zero.
+ //
+ if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF)
+ {
+ return(0);
+ }
+ else
+ {
+ HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data;
+ return(1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Reads a byte from the I2C receive FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//!
+//! This function reads a byte of data from I2C receive FIFO and places it in
+//! the location specified by the \e pui8Data parameter. If there is no data
+//! available, this function waits until data is received before returning.
+//!
+//! \return The data byte.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFODataGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Wait until there is data to read.
+ //
+ while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
+ {
+ }
+
+ //
+ // Read a byte.
+ //
+ return(HWREG(ui32Base + I2C_O_FIFODATA));
+}
+
+//*****************************************************************************
+//
+//! Reads a byte from the I2C receive FIFO.
+//!
+//! \param ui32Base is the base address of the I2C Master or Slave module.
+//! \param pui8Data is a pointer where the read data is stored.
+//!
+//! This function reads a byte of data from I2C receive FIFO and places it in
+//! the location specified by the \e pui8Data parameter. If there is no data
+//! available, this functions returns 0.
+//!
+//! \return The number of elements read from the I2C receive FIFO.
+//
+//*****************************************************************************
+uint32_t
+I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // If nothing in the FIFO, return zero.
+ //
+ if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE)
+ {
+ return(0);
+ }
+ else
+ {
+ *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA);
+ return(1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Set the burst length for a I2C master FIFO operation.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui8Length is the length of the burst transfer.
+//!
+//! This function configures the burst length for a I2C Master FIFO operation.
+//! The burst field is limited to 8 bits or 256 bytes. The burst length
+//! applies to a single I2CMCS BURST operation meaning that it specifies the
+//! burst length for only the current operation (can be TX or RX). Each burst
+//! operation must configure the burst length prior to writing the BURST bit
+//! in the I2CMCS using I2CMasterControl().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255));
+
+ //
+ // Set the burst length.
+ //
+ HWREG(ui32Base + I2C_O_MBLEN) = ui8Length;
+}
+
+//*****************************************************************************
+//
+//! Returns the current value of the burst transfer counter.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//!
+//! This function returns the current value of the burst transfer counter that
+//! is used by the FIFO mechanism. Software can use this value to determine
+//! how many bytes remain in a transfer, or where in the transfer the burst
+//! operation was if an error has occurred.
+//!
+//! \return None.
+//
+//*****************************************************************************
+uint32_t
+I2CMasterBurstCountGet(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Get burst count.
+ //
+ return(HWREG(ui32Base + I2C_O_MBCNT));
+}
+
+//*****************************************************************************
+//
+//! Configures the I2C Master glitch filter.
+//!
+//! \param ui32Base is the base address of the I2C Master module.
+//! \param ui32Config is the glitch filter configuration.
+//!
+//! This function configures the I2C Master glitch filter. The value passed in
+//! to \e ui32Config determines the sampling range of the glitch filter, which
+//! is configurable between 1 and 32 system clock cycles. The default
+//! configuration of the glitch filter is 0 system clock cycles, which means
+//! that it's disabled.
+//!
+//! The \e ui32Config field should be any of the following values:
+//!
+//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED
+//! - \b I2C_MASTER_GLITCH_FILTER_1
+//! - \b I2C_MASTER_GLITCH_FILTER_2
+//! - \b I2C_MASTER_GLITCH_FILTER_3
+//! - \b I2C_MASTER_GLITCH_FILTER_4
+//! - \b I2C_MASTER_GLITCH_FILTER_8
+//! - \b I2C_MASTER_GLITCH_FILTER_16
+//! - \b I2C_MASTER_GLITCH_FILTER_32
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Configure the glitch filter field of MTPR.
+ //
+ HWREG(ui32Base + I2C_O_MTPR) |= ui32Config;
+}
+
+//*****************************************************************************
+//
+//! Enables FIFO usage for the I2C Slave module.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//! \param ui32Config is the desired FIFO configuration of the I2C Slave.
+//!
+//! This function configures the I2C Slave module to use the FIFO(s). This
+//! function should be used in combination with I2CTxFIFOConfigSet() and/or
+//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell
+//! the FIFO hardware whether to interact with the I2C Master or Slave. The
+//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and
+//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config
+//! field.
+//!
+//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(),
+//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration.
+//! Therefore, application software should call I2CSlaveEnable() followed by
+//! I2CSlaveFIFOEnable() with the desired FIFO configuration.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Enable the FIFOs for the slave.
+ //
+ HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+//! Disable FIFO usage for the I2C Slave module.
+//!
+//! \param ui32Base is the base address of the I2C Slave module.
+//!
+//! This function disables the FIFOs for the I2C Slave. After calling this
+//! this function, the FIFOs are disabled, but the Slave remains active.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+I2CSlaveFIFODisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(_I2CBaseValid(ui32Base));
+
+ //
+ // Disable slave FIFOs.
+ //
+ HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/i2c.h b/cc3200/hal/i2c.h
new file mode 100644
index 0000000000..67f77fa9a5
--- /dev/null
+++ b/cc3200/hal/i2c.h
@@ -0,0 +1,361 @@
+//*****************************************************************************
+//
+// i2c.h
+//
+// Prototypes for the I2C Driver.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __DRIVERLIB_I2C_H__
+#define __DRIVERLIB_I2C_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Defines for the API.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// Interrupt defines.
+//
+//*****************************************************************************
+#define I2C_INT_MASTER 0x00000001
+#define I2C_INT_SLAVE 0x00000002
+
+//*****************************************************************************
+//
+// I2C Master commands.
+//
+//*****************************************************************************
+#define I2C_MASTER_CMD_SINGLE_SEND \
+ 0x00000007
+#define I2C_MASTER_CMD_SINGLE_RECEIVE \
+ 0x00000007
+#define I2C_MASTER_CMD_BURST_SEND_START \
+ 0x00000003
+#define I2C_MASTER_CMD_BURST_SEND_CONT \
+ 0x00000001
+#define I2C_MASTER_CMD_BURST_SEND_FINISH \
+ 0x00000005
+#define I2C_MASTER_CMD_BURST_SEND_STOP \
+ 0x00000004
+#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
+ 0x00000004
+#define I2C_MASTER_CMD_BURST_RECEIVE_START \
+ 0x0000000b
+#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
+ 0x00000009
+#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
+ 0x00000005
+#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
+ 0x00000004
+#define I2C_MASTER_CMD_QUICK_COMMAND \
+ 0x00000027
+#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
+ 0x00000013
+#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \
+ 0x00000046
+#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \
+ 0x00000046
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \
+ 0x00000042
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \
+ 0x00000040
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \
+ 0x00000044
+#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \
+ 0x00000004
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \
+ 0x0000004a
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \
+ 0x00000048
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \
+ 0x00000044
+#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \
+ 0x00000004
+
+//*****************************************************************************
+//
+// I2C Master glitch filter configuration.
+//
+//*****************************************************************************
+#define I2C_MASTER_GLITCH_FILTER_DISABLED \
+ 0
+#define I2C_MASTER_GLITCH_FILTER_1 \
+ 0x00010000
+#define I2C_MASTER_GLITCH_FILTER_2 \
+ 0x00020000
+#define I2C_MASTER_GLITCH_FILTER_3 \
+ 0x00030000
+#define I2C_MASTER_GLITCH_FILTER_4 \
+ 0x00040000
+#define I2C_MASTER_GLITCH_FILTER_8 \
+ 0x00050000
+#define I2C_MASTER_GLITCH_FILTER_16 \
+ 0x00060000
+#define I2C_MASTER_GLITCH_FILTER_32 \
+ 0x00070000
+
+//*****************************************************************************
+//
+// I2C Master error status.
+//
+//*****************************************************************************
+#define I2C_MASTER_ERR_NONE 0
+#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
+#define I2C_MASTER_ERR_DATA_ACK 0x00000008
+#define I2C_MASTER_ERR_ARB_LOST 0x00000010
+#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
+
+//*****************************************************************************
+//
+// I2C Slave action requests
+//
+//*****************************************************************************
+#define I2C_SLAVE_ACT_NONE 0
+#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
+#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
+#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
+#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
+#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
+#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
+
+//*****************************************************************************
+//
+// Miscellaneous I2C driver definitions.
+//
+//*****************************************************************************
+#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
+
+//*****************************************************************************
+//
+// I2C Master interrupts.
+//
+//*****************************************************************************
+#define I2C_MASTER_INT_RX_FIFO_FULL \
+ 0x00000800 // RX FIFO Full Interrupt
+#define I2C_MASTER_INT_TX_FIFO_EMPTY \
+ 0x00000400 // TX FIFO Empty Interrupt
+#define I2C_MASTER_INT_RX_FIFO_REQ \
+ 0x00000200 // RX FIFO Request Interrupt
+#define I2C_MASTER_INT_TX_FIFO_REQ \
+ 0x00000100 // TX FIFO Request Interrupt
+#define I2C_MASTER_INT_ARB_LOST \
+ 0x00000080 // Arb Lost Interrupt
+#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt
+#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt
+#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt
+#define I2C_MASTER_INT_TX_DMA_DONE \
+ 0x00000008 // TX DMA Complete Interrupt
+#define I2C_MASTER_INT_RX_DMA_DONE \
+ 0x00000004 // RX DMA Complete Interrupt
+#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt
+#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt
+
+//*****************************************************************************
+//
+// I2C Slave interrupts.
+//
+//*****************************************************************************
+#define I2C_SLAVE_INT_RX_FIFO_FULL \
+ 0x00000100 // RX FIFO Full Interrupt
+#define I2C_SLAVE_INT_TX_FIFO_EMPTY \
+ 0x00000080 // TX FIFO Empty Interrupt
+#define I2C_SLAVE_INT_RX_FIFO_REQ \
+ 0x00000040 // RX FIFO Request Interrupt
+#define I2C_SLAVE_INT_TX_FIFO_REQ \
+ 0x00000020 // TX FIFO Request Interrupt
+#define I2C_SLAVE_INT_TX_DMA_DONE \
+ 0x00000010 // TX DMA Complete Interrupt
+#define I2C_SLAVE_INT_RX_DMA_DONE \
+ 0x00000008 // RX DMA Complete Interrupt
+#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt
+#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt
+#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt
+
+//*****************************************************************************
+//
+// I2C Slave FIFO configuration macros.
+//
+//*****************************************************************************
+#define I2C_SLAVE_TX_FIFO_ENABLE \
+ 0x00000002
+#define I2C_SLAVE_RX_FIFO_ENABLE \
+ 0x00000004
+
+//*****************************************************************************
+//
+// I2C FIFO configuration macros.
+//
+//*****************************************************************************
+#define I2C_FIFO_CFG_TX_MASTER 0x00000000
+#define I2C_FIFO_CFG_TX_SLAVE 0x00008000
+#define I2C_FIFO_CFG_RX_MASTER 0x00000000
+#define I2C_FIFO_CFG_RX_SLAVE 0x80000000
+#define I2C_FIFO_CFG_TX_MASTER_DMA \
+ 0x00002000
+#define I2C_FIFO_CFG_TX_SLAVE_DMA \
+ 0x0000a000
+#define I2C_FIFO_CFG_RX_MASTER_DMA \
+ 0x20000000
+#define I2C_FIFO_CFG_RX_SLAVE_DMA \
+ 0xa0000000
+#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
+#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001
+#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002
+#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003
+#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004
+#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005
+#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006
+#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007
+#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008
+#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
+#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000
+#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000
+#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000
+#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000
+#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000
+#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000
+#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000
+#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000
+
+//*****************************************************************************
+//
+// I2C FIFO status.
+//
+//*****************************************************************************
+#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \
+ 0x00040000
+#define I2C_FIFO_RX_FULL 0x00020000
+#define I2C_FIFO_RX_EMPTY 0x00010000
+#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \
+ 0x00000004
+#define I2C_FIFO_TX_FULL 0x00000002
+#define I2C_FIFO_TX_EMPTY 0x00000001
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
+extern void I2CIntUnregister(uint32_t ui32Base);
+extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CTxFIFOFlush(uint32_t ui32Base);
+extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CRxFIFOFlush(uint32_t ui32Base);
+extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
+extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
+ uint8_t ui8Data);
+extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
+extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
+ uint8_t *pui8Data);
+extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
+ uint8_t ui8Length);
+extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
+extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
+ uint32_t ui32Config);
+extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
+extern void I2CSlaveFIFODisable(uint32_t ui32Base);
+extern bool I2CMasterBusBusy(uint32_t ui32Base);
+extern bool I2CMasterBusy(uint32_t ui32Base);
+extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
+extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
+extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern void I2CMasterDisable(uint32_t ui32Base);
+extern void I2CMasterEnable(uint32_t ui32Base);
+extern uint32_t I2CMasterErr(uint32_t ui32Base);
+extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
+ bool bFast);
+extern void I2CMasterIntClear(uint32_t ui32Base);
+extern void I2CMasterIntDisable(uint32_t ui32Base);
+extern void I2CMasterIntEnable(uint32_t ui32Base);
+extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
+extern void I2CMasterIntEnableEx(uint32_t ui32Base,
+ uint32_t ui32IntFlags);
+extern void I2CMasterIntDisableEx(uint32_t ui32Base,
+ uint32_t ui32IntFlags);
+extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
+ bool bMasked);
+extern void I2CMasterIntClearEx(uint32_t ui32Base,
+ uint32_t ui32IntFlags);
+extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
+extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
+extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
+extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
+extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
+ uint8_t ui8SlaveAddr,
+ bool bReceive);
+extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
+extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
+extern void I2CSlaveDisable(uint32_t ui32Base);
+extern void I2CSlaveEnable(uint32_t ui32Base);
+extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
+extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
+ uint8_t ui8SlaveAddr);
+extern void I2CSlaveIntClear(uint32_t ui32Base);
+extern void I2CSlaveIntDisable(uint32_t ui32Base);
+extern void I2CSlaveIntEnable(uint32_t ui32Base);
+extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
+ uint32_t ui32IntFlags);
+extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
+extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
+extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
+ bool bMasked);
+extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __DRIVERLIB_I2C_H__
diff --git a/cc3200/hal/i2s.c b/cc3200/hal/i2s.c
new file mode 100644
index 0000000000..36ff45b22d
--- /dev/null
+++ b/cc3200/hal/i2s.c
@@ -0,0 +1,922 @@
+//*****************************************************************************
+//
+// i2s.c
+//
+// Driver for the I2S interface.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup I2S_api
+//! @{
+//
+//*****************************************************************************
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_mcasp.h"
+#include "inc/hw_apps_config.h"
+#include "interrupt.h"
+#include "i2s.h"
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define MCASP_GBL_RCLK 0x00000001
+#define MCASP_GBL_RHCLK 0x00000002
+#define MCASP_GBL_RSER 0x00000004
+#define MCASP_GBL_RSM 0x00000008
+#define MCASP_GBL_RFSYNC 0x00000010
+#define MCASP_GBL_XCLK 0x00000100
+#define MCASP_GBL_XHCLK 0x00000200
+#define MCASP_GBL_XSER 0x00000400
+#define MCASP_GBL_XSM 0x00000800
+#define MCASP_GBL_XFSYNC 0x00001000
+
+
+//*****************************************************************************
+//
+//! \internal
+//! Releases the specifed submodule out of reset.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulFlag is one of the valid sub module.
+//!
+//! This function Releases the specifed submodule out of reset.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void I2SGBLEnable(unsigned long ulBase, unsigned long ulFlag)
+{
+ unsigned long ulReg;
+
+ //
+ // Read global control register
+ //
+ ulReg = HWREG(ulBase + MCASP_O_GBLCTL);
+
+ //
+ // Remove the sub modules reset as specified by ulFlag parameter
+ //
+ ulReg |= ulFlag;
+
+ //
+ // Write the configuration
+ //
+ HWREG(ulBase + MCASP_O_GBLCTL) = ulReg;
+
+ //
+ // Wait for write completeion
+ //
+ while(HWREG(ulBase + MCASP_O_GBLCTL) != ulReg)
+ {
+
+ }
+
+}
+
+//*****************************************************************************
+//
+//! Enables transmit and/or receive.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulMode is one of the valid modes.
+//!
+//! This function enables the I2S module in specified mode. The parameter
+//! \e ulMode should be one of the following
+//!
+//! -\b I2S_MODE_TX_ONLY
+//! -\b I2S_MODE_TX_RX_SYNC
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SEnable(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Set FSYNC anc BitClk as output
+ //
+ HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000;
+
+ if(ulMode & 0x2)
+ {
+ //
+ // Remove Rx HCLK reset
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_RHCLK);
+
+ //
+ // Remove Rx XCLK reset
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_RCLK);
+
+ //
+ // Enable Rx SERDES(s)
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_RSER);
+
+ //
+ // Enable Rx state machine
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_RSM);
+
+ //
+ // Enable FSync generator
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_RFSYNC);
+ }
+
+ if(ulMode & 0x1)
+ {
+ //
+ // Remove Tx HCLK reset
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_XHCLK);
+
+ //
+ // Remove Tx XCLK reset
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_XCLK);
+
+ //
+ // Enable Tx SERDES(s)
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_XSER);
+
+ //
+ // Enable Tx state machine
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_XSM);
+
+ //
+ // Enable FSync generator
+ //
+ I2SGBLEnable(ulBase, MCASP_GBL_XFSYNC);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables transmit and/or receive.
+//!
+//! \param ulBase is the base address of the I2S module.
+//!
+//! This function disables transmit and/or receive from I2S module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SDisable(unsigned long ulBase)
+{
+ //
+ // Reset all sub modules
+ //
+ HWREG(ulBase + MCASP_O_GBLCTL) = 0;
+
+ //
+ // Wait for write to complete
+ //
+ while( HWREG(ulBase + MCASP_O_GBLCTL) != 0)
+ {
+
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits to send data over the specified data line
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulDataLine is one of the valid data lines.
+//! \param ulData is the data to be transmitted.
+//!
+//! This function sends the \e ucData to the transmit register for the
+//! specified data line. If there is no space available, this
+//! function waits until there is space available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long ulData)
+{
+ //
+ // Compute register the offeset
+ //
+ ulDataLine = (ulDataLine-1) << 2;
+
+ //
+ // Wait for free space in fifo
+ //
+ while(!( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA))
+ {
+
+ }
+
+ //
+ // Write Data into the FIFO
+ //
+ HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData;
+}
+
+//*****************************************************************************
+//
+//! Sends data over the specified data line
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulDataLine is one of the valid data lines.
+//! \param ulData is the data to be transmitted.
+//!
+//! This function writes the \e ucData to the transmit register for
+//! the specified data line. This function does not block, so if there is no
+//! space available, then \b -1 is returned, and the application must retry the
+//! function later.
+//!
+//! \return Returns 0 on success, -1 otherwise.
+//
+//*****************************************************************************
+long I2SDataPutNonBlocking(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long ulData)
+{
+
+ //
+ // Compute register the offeset
+ //
+ ulDataLine = (ulDataLine-1) << 2;
+
+ //
+ // Send Data if fifo has free space
+ //
+ if( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA)
+ {
+ //
+ // Write data into the FIFO
+ //
+ HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData;
+ return 0;
+ }
+
+ //
+ // FIFO is full
+ //
+ return(-1);
+}
+
+//*****************************************************************************
+//
+//! Waits for data from the specified data line.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulDataLine is one of the valid data lines.
+//! \param pulData is pointer to receive data variable.
+//!
+//! This function gets data from the receive register for the specified
+//! data line. If there are no data available, this function waits until a
+//! receive before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long *pulData)
+{
+
+ //
+ // Compute register the offeset
+ //
+ ulDataLine = (ulDataLine-1) << 2;
+
+ //
+ // Wait for atleat on word in FIFO
+ //
+ while(!(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA))
+ {
+
+ }
+
+ //
+ // Read the Data
+ //
+ *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine);
+}
+
+
+//*****************************************************************************
+//
+//! Receives data from the specified data line.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulDataLine is one of the valid data lines.
+//! \param pulData is pointer to receive data variable.
+//!
+//! This function gets data from the receive register for the specified
+//! data line.
+//!
+//!
+//! \return Returns 0 on success, -1 otherwise.
+//
+//*****************************************************************************
+long I2SDataGetNonBlocking(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long *pulData)
+{
+
+ //
+ // Compute register the offeset
+ //
+ ulDataLine = (ulDataLine-1) << 2;
+
+ //
+ // Check if data is available in FIFO
+ //
+ if(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA)
+ {
+ //
+ // Read the Data
+ //
+ *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine);
+ return 0;
+ }
+
+ //
+ // FIFO is empty
+ //
+ return -1;
+}
+
+
+//*****************************************************************************
+//
+//! Sets the configuration of the I2S module.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulI2SClk is the rate of the clock supplied to the I2S module.
+//! \param ulBitClk is the desired bit rate.
+//! \param ulConfig is the data format.
+//!
+//! This function configures the I2S for operation in the specified data
+//! format. The bit rate is provided in the \e ulBitClk parameter and the data
+//! format in the \e ulConfig parameter.
+//!
+//! The \e ulConfig parameter is the logical OR of two values: the slot size
+//! and the data read/write port select.
+//!
+//! Following selects the slot size:
+//! -\b I2S_SLOT_SIZE_24
+//! -\b I2S_SLOT_SIZE_16
+//!
+//! Following selects the data read/write port:
+//! -\b I2S_PORT_DMA
+//! -\b I2S_PORT_CPU
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
+ unsigned long ulBitClk, unsigned long ulConfig)
+{
+ unsigned long ulHClkDiv;
+ unsigned long ulClkDiv;
+
+ //
+ // Calculate clock dividers
+ //
+ ulHClkDiv = ((ulI2SClk/ulBitClk)-1);
+ ulClkDiv = 0;
+
+ //
+ // Check if HCLK divider is overflowing
+ //
+ if(ulHClkDiv > 0xFFF)
+ {
+ ulHClkDiv = 0xFFF;
+
+ //
+ // Calculate clock divider
+ //
+ ulClkDiv = ((ulI2SClk/(ulBitClk * (ulHClkDiv + 1))) & 0x1F);
+ }
+
+ HWREG(ulBase + MCASP_O_ACLKXCTL) = (0xA0|ulClkDiv);
+
+ HWREG(ulBase + MCASP_O_AHCLKXCTL) = (0x8000|ulHClkDiv);
+
+ //
+ // Write the Tx format register
+ //
+ HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0xFFFF));
+
+ //
+ // Write the Rx format register
+ //
+ HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0xFFFF));
+
+ //
+ // Configure Tx FSync generator in I2S mode
+ //
+ HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113;
+
+ //
+ // Configure Rx FSync generator in I2S mode
+ //
+ HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113;
+
+ //
+ // Set Tx bit valid mask
+ //
+ HWREG(ulBase + MCASP_O_TXMASK) = 0xFFFFFFFF;
+
+ //
+ // Set Rx bit valid mask
+ //
+ HWREG(ulBase + MCASP_O_RXMASK) = 0xFFFFFFFF;
+
+ //
+ // Set Tx slot valid mask
+ //
+ HWREG(ulBase + MCASP_O_TXTDM) = 0x3;
+
+ //
+ // Set Rx slot valid mask
+ //
+ HWREG(ulBase + MCASP_O_RXTDM) = 0x3;
+}
+
+//*****************************************************************************
+//
+//! Configure and enable transmit FIFO.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulTxLevel is the transmit FIFO DMA request level.
+//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO.
+//!
+//! This function configures and enable I2S transmit FIFO.
+//!
+//! The parameter \e ulTxLevel sets the level at which transmit DMA requests
+//! are generated. This should be non-zero integer multiple of number of
+//! serializers enabled as transmitters
+//!
+//! The parameter \e ulWordsPerTransfer sets the number of words that are
+//! transferred from the transmit FIFO to the data line(s). This value must
+//! equal the number of serializers used as transmitters.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulWordsPerTransfer)
+{
+ //
+ // Set transmit FIFO configuration and
+ // enable it
+ //
+ HWREG(ulBase + MCASP_0_WFIFOCTL) = ((1 <<16) | ((ulTxLevel & 0xFF) << 8)
+ | (ulWordsPerTransfer & 0x1F));
+
+}
+
+//*****************************************************************************
+//
+//! Disables transmit FIFO.
+//!
+//! \param ulBase is the base address of the I2S module.
+//!
+//! This function disables the I2S transmit FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2STxFIFODisable(unsigned long ulBase)
+{
+ //
+ // Disable transmit FIFO.
+ //
+ HWREG(ulBase + MCASP_0_WFIFOCTL) = 0;
+}
+
+//*****************************************************************************
+//
+//! Configure and enable receive FIFO.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulRxLevel is the receive FIFO DMA request level.
+//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO.
+//!
+//! This function configures and enable I2S receive FIFO.
+//!
+//! The parameter \e ulRxLevel sets the level at which receive DMA requests
+//! are generated. This should be non-zero integer multiple of number of
+//! serializers enabled as receivers.
+//!
+//! The parameter \e ulWordsPerTransfer sets the number of words that are
+//! transferred to the receive FIFO from the data line(s). This value must
+//! equal the number of serializers used as receivers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,
+ unsigned long ulWordsPerTransfer)
+{
+ //
+ // Set FIFO configuration
+ //
+ HWREG(ulBase + MCASP_0_RFIFOCTL) = ( (1 <<16) | ((ulRxLevel & 0xFF) << 8)
+ | (ulWordsPerTransfer & 0x1F));
+
+}
+
+//*****************************************************************************
+//
+//! Disables receive FIFO.
+//!
+//! \param ulBase is the base address of the I2S module.
+//!
+//! This function disables the I2S receive FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SRxFIFODisable(unsigned long ulBase)
+{
+ //
+ // Disable receive FIFO.
+ //
+ HWREG(ulBase + MCASP_0_RFIFOCTL) = 0;
+}
+
+//*****************************************************************************
+//
+//! Get the transmit FIFO status.
+//!
+//! \param ulBase is the base address of the I2S module.
+//!
+//! This function gets the number of 32-bit words currently in the transmit
+//! FIFO.
+//!
+//! \return Returns transmit FIFO status.
+//
+//*****************************************************************************
+unsigned long I2STxFIFOStatusGet(unsigned long ulBase)
+{
+ //
+ // Return transmit FIFO level
+ //
+ return HWREG(ulBase + MCASP_0_WFIFOSTS);
+}
+
+//*****************************************************************************
+//
+//! Get the receive FIFO status.
+//!
+//! \param ulBase is the base address of the I2S module.
+//!
+//! This function gets the number of 32-bit words currently in the receive
+//! FIFO.
+//!
+//! \return Returns receive FIFO status.
+//
+//*****************************************************************************
+unsigned long I2SRxFIFOStatusGet(unsigned long ulBase)
+{
+ //
+ // Return receive FIFO level
+ //
+ return HWREG(ulBase + MCASP_0_RFIFOSTS);
+}
+
+//*****************************************************************************
+//
+//! Configure the serializer in specified mode.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulDataLine is the data line (serilizer) to be configured.
+//! \param ulSerMode is the required serializer mode.
+//! \param ulInActState sets the inactive state of the data line.
+//!
+//! This function configure and enable the serializer associated with the given
+//! data line in specified mode.
+//!
+//! The paramenter \e ulDataLine selects to data line to be configured and
+//! can be one of the following:
+//! -\b I2S_DATA_LINE_0
+//! -\b I2S_DATA_LINE_1
+//!
+//! The parameter \e ulSerMode can be one of the following:
+//! -\b I2S_SER_MODE_TX
+//! -\b I2S_SER_MODE_RX
+//! -\b I2S_SER_MODE_DISABLE
+//!
+//! The parameter \e ulInActState can be one of the following
+//! -\b I2S_INACT_TRI_STATE
+//! -\b I2S_INACT_LOW_LEVEL
+//! -\b I2S_INACT_LOW_HIGH
+//!
+//! \return Returns receive FIFO status.
+//
+//*****************************************************************************
+void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long ulSerMode, unsigned long ulInActState)
+{
+ if( ulSerMode == I2S_SER_MODE_TX)
+ {
+ //
+ // Set the data line in output mode
+ //
+ HWREG(ulBase + MCASP_O_PDIR) |= ulDataLine;
+ }
+ else
+ {
+ //
+ // Set the data line in input mode
+ //
+ HWREG(ulBase + MCASP_O_PDIR) &= ~ulDataLine;
+ }
+
+ //
+ // Set the serializer configuration.
+ //
+ HWREG(ulBase + MCASP_O_XRSRCTL0 + ((ulDataLine-1) << 2))
+ = (ulSerMode | ulInActState);
+}
+
+//*****************************************************************************
+//
+//! Enables individual I2S interrupt sources.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated I2S interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! -\b I2S_INT_XUNDRN
+//! -\b I2S_INT_XSYNCERR
+//! -\b I2S_INT_XLAST
+//! -\b I2S_INT_XDATA
+//! -\b I2S_INT_XSTAFRM
+//! -\b I2S_INT_XDMA
+//! -\b I2S_INT_ROVRN
+//! -\b I2S_INT_RSYNCERR
+//! -\b I2S_INT_RLAST
+//! -\b I2S_INT_RDATA
+//! -\b I2S_INT_RSTAFRM
+//! -\b I2S_INT_RDMA
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+
+ //
+ // Enable DMA done interrupts
+ //
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR )
+ |= ((ulIntFlags &0xC0000000) >> 20);
+
+ //
+ // Enable specific Tx Interrupts
+ //
+ HWREG(ulBase + MCASP_O_EVTCTLX) |= (ulIntFlags & 0xFF);
+
+ //
+ // Enable specific Rx Interrupts
+ //
+ HWREG(ulBase + MCASP_O_EVTCTLR) |= ((ulIntFlags >> 16) & 0xFF);
+}
+
+//*****************************************************************************
+//
+//! Disables individual I2S interrupt sources.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated I2S interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to I2SIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Disable DMA done interrupts
+ //
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET)
+ |= ((ulIntFlags &0xC0000000) >> 20);
+
+ //
+ // Disable specific Tx Interrupts
+ //
+ HWREG(ulBase + MCASP_O_EVTCTLX) &= ~(ulIntFlags & 0xFF);
+
+ //
+ // Disable specific Rx Interrupts
+ //
+ HWREG(ulBase + MCASP_O_EVTCTLR) &= ~((ulIntFlags >> 16) & 0xFF);
+}
+
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the I2S module.
+//!
+//! This function returns the raw interrupt status for I2S enumerated
+//! as a bit field of values:
+//! -\b I2S_STS_XERR
+//! -\b I2S_STS_XDMAERR
+//! -\b I2S_STS_XSTAFRM
+//! -\b I2S_STS_XDATA
+//! -\b I2S_STS_XLAST
+//! -\b I2S_STS_XSYNCERR
+//! -\b I2S_STS_XUNDRN
+//! -\b I2S_STS_XDMA
+//! -\b I2S_STS_RERR
+//! -\b I2S_STS_RDMAERR
+//! -\b I2S_STS_RSTAFRM
+//! -\b I2S_STS_RDATA
+//! -\b I2S_STS_RLAST
+//! -\b I2S_STS_RSYNCERR
+//! -\b I2S_STS_ROVERN
+//! -\b I2S_STS_RDMA
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described above.
+//
+//*****************************************************************************
+unsigned long I2SIntStatus(unsigned long ulBase)
+{
+ unsigned long ulStatus;
+
+ //
+ // Get DMA interrupt status
+ //
+ ulStatus =
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW) << 20;
+
+ ulStatus &= 0xC0000000;
+
+ //
+ // Read Tx Interrupt status
+ //
+ ulStatus |= HWREG(ulBase + MCASP_O_TXSTAT);
+
+ //
+ // Read Rx Interrupt status
+ //
+ ulStatus |= HWREG(ulBase + MCASP_O_RXSTAT) << 16;
+
+ //
+ // Return the status
+ //
+ return ulStatus;
+}
+
+//*****************************************************************************
+//
+//! Clears I2S interrupt sources.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param ulStatFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified I2S interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the value
+//! describe in I2SIntStatus().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SIntClear(unsigned long ulBase, unsigned long ulStatFlags)
+{
+ //
+ // Clear DMA done interrupts
+ //
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK)
+ |= ((ulStatFlags &0xC0000000) >> 20);
+
+ //
+ // Clear Tx Interrupt
+ //
+ HWREG(ulBase + MCASP_O_TXSTAT) = ulStatFlags & 0x1FF ;
+
+ //
+ // Clear Rx Interrupt
+ //
+ HWREG(ulBase + MCASP_O_RXSTAT) = (ulStatFlags >> 16) & 0x1FF;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a I2S interrupt.
+//!
+//! \param ulBase is the base address of the I2S module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! I2S interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller; specific
+//! I2S interrupts must be enabled via I2SIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler
+ //
+ IntRegister(INT_I2S,pfnHandler);
+
+ //
+ // Enable the interrupt
+ //
+ IntEnable(INT_I2S);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a I2S interrupt.
+//!
+//! \param ulBase is the base address of the I2S module.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a I2S interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void I2SIntUnregister(unsigned long ulBase)
+{
+ //
+ // Disable interrupt
+ //
+ IntDisable(INT_I2S);
+
+ //
+ // Unregister the handler
+ //
+ IntUnregister(INT_I2S);
+
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/i2s.h b/cc3200/hal/i2s.h
new file mode 100644
index 0000000000..b4d58ff1a9
--- /dev/null
+++ b/cc3200/hal/i2s.h
@@ -0,0 +1,202 @@
+//*****************************************************************************
+//
+// i2s.h
+//
+// Defines and Macros for the I2S.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// I2S DMA ports.
+//
+//*****************************************************************************
+#define I2S_TX_DMA_PORT 0x4401E200
+#define I2S_RX_DMA_PORT 0x4401E280
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter.
+//
+//*****************************************************************************
+#define I2S_SLOT_SIZE_24 0x00B200B4
+#define I2S_SLOT_SIZE_16 0x00700074
+
+#define I2S_PORT_CPU 0x00000008
+#define I2S_PORT_DMA 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed as ulDataLine parameter.
+//
+//*****************************************************************************
+#define I2S_DATA_LINE_0 0x00000001
+#define I2S_DATA_LINE_1 0x00000002
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SSerializerConfig() as the ulSerMode
+// parameter.
+//
+//*****************************************************************************
+#define I2S_SER_MODE_TX 0x00000001
+#define I2S_SER_MODE_RX 0x00000002
+#define I2S_SER_MODE_DISABLE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SSerializerConfig() as the ulInActState
+// parameter.
+//
+//*****************************************************************************
+#define I2S_INACT_TRI_STATE 0x00000000
+#define I2S_INACT_LOW_LEVEL 0x00000008
+#define I2S_INACT_HIGH_LEVEL 0x0000000C
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the
+// ulIntFlags parameter.
+//
+//*****************************************************************************
+#define I2S_INT_XUNDRN 0x00000001
+#define I2S_INT_XSYNCERR 0x00000002
+#define I2S_INT_XLAST 0x00000010
+#define I2S_INT_XDATA 0x00000020
+#define I2S_INT_XSTAFRM 0x00000080
+#define I2S_INT_XDMA 0x80000000
+#define I2S_INT_ROVRN 0x00010000
+#define I2S_INT_RSYNCERR 0x00020000
+#define I2S_INT_RLAST 0x00100000
+#define I2S_INT_RDATA 0x00200000
+#define I2S_INT_RSTAFRM 0x00800000
+#define I2S_INT_RDMA 0x40000000
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SIntClear() as the
+// ulIntFlags parameter and returned from I2SIntStatus().
+//
+//*****************************************************************************
+#define I2S_STS_XERR 0x00000100
+#define I2S_STS_XDMAERR 0x00000080
+#define I2S_STS_XSTAFRM 0x00000040
+#define I2S_STS_XDATA 0x00000020
+#define I2S_STS_XLAST 0x00000010
+#define I2S_STS_XSYNCERR 0x00000002
+#define I2S_STS_XUNDRN 0x00000001
+#define I2S_STS_XDMA 0x80000000
+#define I2S_STS_RERR 0x01000000
+#define I2S_STS_RDMAERR 0x00800000
+#define I2S_STS_RSTAFRM 0x00400000
+#define I2S_STS_RDATA 0x00200000
+#define I2S_STS_RLAST 0x00100000
+#define I2S_STS_RSYNCERR 0x00020000
+#define I2S_STS_ROVERN 0x00010000
+#define I2S_STS_RDMA 0x40000000
+
+//*****************************************************************************
+//
+// Values that can be passed to I2SEnable() as the ulMode parameter.
+//
+//*****************************************************************************
+#define I2S_MODE_TX_ONLY 0x00000001
+#define I2S_MODE_TX_RX_SYNC 0x00000003
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void I2SEnable(unsigned long ulBase, unsigned long ulMode);
+extern void I2SDisable(unsigned long ulBase);
+
+extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long ulData);
+extern long I2SDataPutNonBlocking(unsigned long ulBase,
+ unsigned long ulDataLine, unsigned long ulData);
+
+extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long *pulData);
+extern long I2SDataGetNonBlocking(unsigned long ulBase,
+ unsigned long ulDataLine, unsigned long *pulData);
+
+extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
+ unsigned long ulBitClk, unsigned long ulConfig);
+
+extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulWordsPerTransfer);
+extern void I2STxFIFODisable(unsigned long ulBase);
+extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,
+ unsigned long ulWordsPerTransfer);
+extern void I2SRxFIFODisable(unsigned long ulBase);
+extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase);
+extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase);
+
+extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,
+ unsigned long ulSerMode, unsigned long ulInActState);
+
+extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long I2SIntStatus(unsigned long ulBase);
+extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void I2SIntUnregister(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__I2S_H__
+
diff --git a/cc3200/hal/inc/asmdefs.h b/cc3200/hal/inc/asmdefs.h
new file mode 100644
index 0000000000..c2a6f97342
--- /dev/null
+++ b/cc3200/hal/inc/asmdefs.h
@@ -0,0 +1,229 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__ module
+#define __TEXT__ rseg CODE:CODE(2)
+#define __DATA__ rseg DATA:DATA(2)
+#define __BSS__ rseg DATA:DATA(2)
+#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ alignrom 2
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__ thumb
+#define __WORD__ dcd
+#define __INLINE_DATA__ data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ thumb
+ require8
+ preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__ ;
+#define __TEXT__ area ||.text||, code, readonly, align=2
+#define __DATA__ area ||.data||, data, align=2
+#define __BSS__ area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ align 4
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__
+#define __WORD__ dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__
diff --git a/cc3200/hal/inc/hw_adc.h b/cc3200/hal/inc/hw_adc.h
new file mode 100644
index 0000000000..525ce905c6
--- /dev/null
+++ b/cc3200/hal/inc/hw_adc.h
@@ -0,0 +1,888 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ADC_CTRL 0x00000000 // ADC control register.
+#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting
+#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting
+#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting
+#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting
+#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting
+#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting
+#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting
+#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting
+#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable
+ // register
+#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable
+ // register
+#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable
+ // register
+#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable
+ // register
+#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable
+ // register
+#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable
+ // register
+#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable
+ // register
+#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable
+ // register
+#define ADC_O_adc_ch0_irq_status \
+ 0x00000044 // Channel 0 interrupt status
+ // register
+
+#define ADC_O_adc_ch1_irq_status \
+ 0x00000048 // Channel 1 interrupt status
+ // register
+
+#define ADC_O_adc_ch2_irq_status \
+ 0x0000004C
+
+#define ADC_O_adc_ch3_irq_status \
+ 0x00000050 // Channel 3 interrupt status
+ // register
+
+#define ADC_O_adc_ch4_irq_status \
+ 0x00000054 // Channel 4 interrupt status
+ // register
+
+#define ADC_O_adc_ch5_irq_status \
+ 0x00000058
+
+#define ADC_O_adc_ch6_irq_status \
+ 0x0000005C // Channel 6 interrupt status
+ // register
+
+#define ADC_O_adc_ch7_irq_status \
+ 0x00000060 // Channel 7 interrupt status
+ // register
+
+#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register
+#define ADC_O_adc_timer_configuration \
+ 0x00000068 // ADC timer configuration register
+
+#define ADC_O_adc_timer_current_count \
+ 0x00000070 // ADC timer current count register
+
+#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register
+#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register
+#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register
+#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register
+#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register
+#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register
+#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register
+#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register
+#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register
+#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status
+ // register
+#define ADC_O_adc_ch2_fifo_lvl 0x0000009C
+#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status
+ // register
+#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status
+ // register
+#define ADC_O_adc_ch5_fifo_lvl 0x000000A8
+#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status
+ // register
+#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status
+ // register
+
+#define ADC_O_ADC_CH_ENABLE 0x000000B8
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ADC_CTRL register.
+//
+//******************************************************************************
+#define ADC_ADC_CTRL_adc_cap_scale \
+ 0x00000020 // ADC CAP SCALE.
+
+#define ADC_ADC_CTRL_adc_buf_bypass \
+ 0x00000010 // ADC ANA CIO buffer bypass.
+ // Signal is modelled in ANA TOP.
+ // When '1': ADC buffer is bypassed.
+
+#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1:
+ // ADC buffer is enabled.
+#define ADC_ADC_CTRL_adc_core_en \
+ 0x00000004 // ANA ADC core en. This signal act
+ // as glbal enable to ADC CIO. When
+ // 1: ADC core is enabled.
+
+#define ADC_ADC_CTRL_adc_soft_reset \
+ 0x00000002 // ADC soft reset. When '1' : reset
+ // ADC internal logic.
+
+#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC
+ // module is enabled
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_gain_adc_channel0_gain_M \
+ 0x00000003 // gain setting for ADC channel 0.
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch0_gain_adc_channel0_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_gain_adc_channel1_gain_M \
+ 0x00000003 // gain setting for ADC channel 1.
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch1_gain_adc_channel1_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_gain_adc_channel2_gain_M \
+ 0x00000003 // gain setting for ADC channel 2.
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch2_gain_adc_channel2_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_gain_adc_channel3_gain_M \
+ 0x00000003 // gain setting for ADC channel 3.
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch3_gain_adc_channel3_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_gain_adc_channel4_gain_M \
+ 0x00000003 // gain setting for ADC channel 4
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch4_gain_adc_channel4_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_gain_adc_channel5_gain_M \
+ 0x00000003 // gain setting for ADC channel 5.
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch5_gain_adc_channel5_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_gain_adc_channel6_gain_M \
+ 0x00000003 // gain setting for ADC channel 6
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch6_gain_adc_channel6_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_gain register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_gain_adc_channel7_gain_M \
+ 0x00000003 // gain setting for ADC channel 7.
+ // when "00": 1x when "01: 2x when
+ // "10":3x when "11" 4x
+
+#define ADC_adc_ch7_gain_adc_channel7_gain_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_irq_en register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \
+ 0x0000000F // interrupt enable register for
+ // per ADC channel bit 3: when '1'
+ // -> enable FIFO overflow interrupt
+ // bit 2: when '1' -> enable FIFO
+ // underflow interrupt bit 1: when
+ // "1' -> enable FIFO empty
+ // interrupt bit 0: when "1" ->
+ // enable FIFO full interrupt
+
+#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_irq_status register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \
+ 0x0000000F // interrupt status register for
+ // per ADC channel. Interrupt status
+ // can be cleared on write. bit 3:
+ // when value '1' is written ->
+ // would clear FIFO overflow
+ // interrupt status in the next
+ // cycle. if same interrupt is set
+ // in the same cycle then interurpt
+ // would be set and clear command
+ // will be ignored. bit 2: when
+ // value '1' is written -> would
+ // clear FIFO underflow interrupt
+ // status in the next cycle. bit 1:
+ // when value '1' is written ->
+ // would clear FIFO empty interrupt
+ // status in the next cycle. bit 0:
+ // when value '1' is written ->
+ // would clear FIFO full interrupt
+ // status in the next cycle.
+
+#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_dma_mode_en register.
+//
+//******************************************************************************
+#define ADC_adc_dma_mode_en_DMA_MODEenable_M \
+ 0x000000FF // this register enable DMA mode.
+ // when '1' respective ADC channel
+ // is enabled for DMA. When '0' only
+ // interrupt mode is enabled. Bit 0:
+ // channel 0 DMA mode enable. Bit 1:
+ // channel 1 DMA mode enable. Bit 2:
+ // channel 2 DMA mode enable. Bit 3:
+ // channel 3 DMA mode enable. bit 4:
+ // channel 4 DMA mode enable. bit 5:
+ // channel 5 DMA mode enable. bit 6:
+ // channel 6 DMA mode enable. bit 7:
+ // channel 7 DMA mode enable.
+
+#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_timer_configuration register.
+//
+//******************************************************************************
+#define ADC_adc_timer_configuration_timeren \
+ 0x02000000 // when '1' timer is enabled.
+
+#define ADC_adc_timer_configuration_timerreset \
+ 0x01000000 // when '1' reset timer.
+
+#define ADC_adc_timer_configuration_timercount_M \
+ 0x00FFFFFF // Timer count configuration. 17
+ // bit counter is supported. Other
+ // MSB's are redundent.
+
+#define ADC_adc_timer_configuration_timercount_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_timer_current_count register.
+//
+//******************************************************************************
+#define ADC_adc_timer_current_count_timercurrentcount_M \
+ 0x0001FFFF // Timer count configuration
+
+#define ADC_adc_timer_current_count_timercurrentcount_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel0FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel1FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel2FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel3FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel4FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel5FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel6FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_channel7FIFODATA register.
+//
+//******************************************************************************
+#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \
+ 0xFFFFFFFF // read to this register would
+ // return ADC data along with time
+ // stamp information in following
+ // format: bits [13:0] : ADC sample
+ // bits [31:14]: : time stamp per
+ // ADC sample
+
+#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch0_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch1_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch2_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch3_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch4_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch5_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch6_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// ADC_O_adc_ch7_fifo_lvl register.
+//
+//******************************************************************************
+#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \
+ 0x00000007 // This register shows current FIFO
+ // level. FIFO is 4 word wide.
+ // Possible supported levels are :
+ // 0x0 to 0x3
+
+#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0
+
+
+
+#endif // __HW_ADC_H__
diff --git a/cc3200/hal/inc/hw_aes.h b/cc3200/hal/inc/hw_aes.h
new file mode 100644
index 0000000000..3ab0398b35
--- /dev/null
+++ b/cc3200/hal/inc/hw_aes.h
@@ -0,0 +1,802 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_AES_H__
+#define __HW_AES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the AES_P register offsets.
+//
+//*****************************************************************************
+#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third
+ // key
+#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit
+ // key) / CBC-MAC third key (MSW)
+#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC
+ // third key (LSW)
+#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit
+ // key) / CBC-MAC third key
+#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key /
+ // Hash Key input
+#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit
+ // key) + CCM/CBC-MAC second key
+ // (MSW) / Hash Key input (MSW)
+#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key
+ // (LSW) / Hash Key input (LSW)
+#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key /
+ // Hash Key input
+#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key)
+#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key)
+#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key)
+#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key)
+#define AES_O_KEY1_2 0x00000030 // Key
+#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key)
+#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key)
+#define AES_O_KEY1_1 0x0000003C // Key
+#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input
+ // (LSW)
+#define AES_O_IV_IN_1 0x00000044 // Initialization vector input
+#define AES_O_IV_IN_2 0x00000048 // Initialization vector input
+#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input
+ // (MSW)
+#define AES_O_CTRL 0x00000050 // register determines the mode of
+ // operation of the AES Engine
+#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers
+ // (LSW and MSW) store the
+ // cryptographic data length in
+ // bytes for all modes. Once
+ // processing with this context is
+ // started@@ this length decrements
+ // to zero. Data lengths up to (2^61
+ // – 1) bytes are allowed. For GCM@@
+ // any value up to 2^36 - 32 bytes
+ // can be used. This is because a
+ // 32-bit counter mode is used; the
+ // maximum number of 128-bit blocks
+ // is 2^32 – 2@@ resulting in a
+ // maximum number of bytes of 2^36 -
+ // 32. A write to this register
+ // triggers the engine to start
+ // using this context. This is valid
+ // for all modes except GCM and CCM.
+ // Note that for the combined
+ // modes@@ this length does not
+ // include the authentication only
+ // data; the authentication length
+ // is specified in the
+ // AES_AUTH_LENGTH register below.
+ // All modes must have a length > 0.
+ // For the combined modes@@ it is
+ // allowed to have one of the
+ // lengths equal to zero. For the
+ // basic encryption modes
+ // (ECB/CBC/CTR/ICM/CFB128) it is
+ // allowed to program zero to the
+ // length field; in that case the
+ // length is assumed infinite. All
+ // data must be byte (8-bit)
+ // aligned; bit aligned data streams
+ // are not supported by the AES
+ // Engine. For a Host read
+ // operation@@ these registers
+ // return all-zeroes.
+#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers
+ // (LSW and MSW) store the
+ // cryptographic data length in
+ // bytes for all modes. Once
+ // processing with this context is
+ // started@@ this length decrements
+ // to zero. Data lengths up to (2^61
+ // – 1) bytes are allowed. For GCM@@
+ // any value up to 2^36 - 32 bytes
+ // can be used. This is because a
+ // 32-bit counter mode is used; the
+ // maximum number of 128-bit blocks
+ // is 2^32 – 2@@ resulting in a
+ // maximum number of bytes of 2^36 -
+ // 32. A write to this register
+ // triggers the engine to start
+ // using this context. This is valid
+ // for all modes except GCM and CCM.
+ // Note that for the combined
+ // modes@@ this length does not
+ // include the authentication only
+ // data; the authentication length
+ // is specified in the
+ // AES_AUTH_LENGTH register below.
+ // All modes must have a length > 0.
+ // For the combined modes@@ it is
+ // allowed to have one of the
+ // lengths equal to zero. For the
+ // basic encryption modes
+ // (ECB/CBC/CTR/ICM/CFB128) it is
+ // allowed to program zero to the
+ // length field; in that case the
+ // length is assumed infinite. All
+ // data must be byte (8-bit)
+ // aligned; bit aligned data streams
+ // are not supported by the AES
+ // Engine. For a Host read
+ // operation@@ these registers
+ // return all-zeroes.
+#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The
+ // authentication length register
+ // store the authentication data
+ // length in bytes for combined
+ // modes only (GCM or CCM) Supported
+ // AAD-lengths for CCM are from 0 to
+ // (2^16 - 2^8) bytes. For GCM any
+ // value up to (2^32 - 1) bytes can
+ // be used. Once processing with
+ // this context is started@@ this
+ // length decrements to zero. A
+ // write to this register triggers
+ // the engine to start using this
+ // context for GCM and CCM. For XTS
+ // this register is optionally used
+ // to load ‘j’. Loading of ‘j’ is
+ // only required if ‘j’ != 0. ‘j’ is
+ // a 28-bit value and must be
+ // written to bits [31-4] of this
+ // register. ‘j’ represents the
+ // sequential number of the 128-bit
+ // block inside the data unit. For
+ // the first block in a unit@@ this
+ // value is zero. It is not required
+ // to provide a ‘j’ for each new
+ // data block within a unit. Note
+ // that it is possible to start with
+ // a ‘j’ unequal to zero; refer to
+ // Table 4 for more details. For a
+ // Host read operation@@ these
+ // registers return all-zeroes.
+#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write
+ // plaintext/ciphertext (MSW)
+#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write
+ // plaintext/ciphertext
+#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write
+ // plaintext/ciphertext
+#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write
+ // plaintext/ciphertext (LSW)
+#define AES_O_TAG_OUT_0 0x00000070
+#define AES_O_TAG_OUT_1 0x00000074
+#define AES_O_TAG_OUT_2 0x00000078
+#define AES_O_TAG_OUT_3 0x0000007C
+#define AES_O_REVISION 0x00000080 // Register AES_REVISION
+#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This
+ // register configures the DMA
+ // signals and controls the IDLE and
+ // reset logic
+#define AES_O_SYSSTATUS 0x00000088
+#define AES_O_IRQSTATUS 0x0000008C // This register indicates the
+ // interrupt status. If one of the
+ // interrupt bits is set the
+ // interrupt output will be asserted
+#define AES_O_IRQENABLE 0x00000090 // This register contains an enable
+ // bit for each unique interrupt
+ // generated by the module. It
+ // matches the layout of
+ // AES_IRQSTATUS register. An
+ // interrupt is enabled when the bit
+ // in this register is set to ‘1’.
+ // An interrupt that is enabled is
+ // propagated to the SINTREQUEST_x
+ // output. All interrupts need to be
+ // enabled explicitly by writing
+ // this register.
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_6 register.
+//
+//******************************************************************************
+#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_6_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_7 register.
+//
+//******************************************************************************
+#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_7_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_4 register.
+//
+//******************************************************************************
+#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_4_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_5 register.
+//
+//******************************************************************************
+#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_5_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_2 register.
+//
+//******************************************************************************
+#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_2_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_3 register.
+//
+//******************************************************************************
+#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_3_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_0 register.
+//
+//******************************************************************************
+#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_0_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_1 register.
+//
+//******************************************************************************
+#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY2_1_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_6 register.
+//
+//******************************************************************************
+#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_6_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_7 register.
+//
+//******************************************************************************
+#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_7_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_4 register.
+//
+//******************************************************************************
+#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_4_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_5 register.
+//
+//******************************************************************************
+#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_5_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_2 register.
+//
+//******************************************************************************
+#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_2_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_3 register.
+//
+//******************************************************************************
+#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_3_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_0 register.
+//
+//******************************************************************************
+#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_0_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_1 register.
+//
+//******************************************************************************
+#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data
+#define AES_KEY1_1_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
+//
+//******************************************************************************
+#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data
+#define AES_IV_IN_0_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
+//
+//******************************************************************************
+#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data
+#define AES_IV_IN_1_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
+//
+//******************************************************************************
+#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data
+#define AES_IV_IN_2_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
+//
+//******************************************************************************
+#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data
+#define AES_IV_IN_3_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_CTRL register.
+//
+//******************************************************************************
+#define AES_CTRL_CONTEXT_READY \
+ 0x80000000 // If ‘1’@@ this read-only status
+ // bit indicates that the context
+ // data registers can be overwritten
+ // and the host is permitted to
+ // write the next context.
+
+#define AES_CTRL_SVCTXTRDY \
+ 0x40000000 // If ‘1’@@ this read-only status
+ // bit indicates that an AES
+ // authentication TAG and/or IV
+ // block(s) is/are available for the
+ // host to retrieve. This bit is
+ // only asserted if the
+ // ‘save_context’ bit is set to ‘1’.
+ // The bit is mutual exclusive with
+ // the ‘context_ready’ bit.
+
+#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate
+ // that an authentication TAG or
+ // result IV needs to be stored as a
+ // result context. If this bit is
+ // set@@ context output DMA and/or
+ // interrupt will be asserted if the
+ // operation is finished and related
+ // signals are enabled.
+#define AES_CTRL_CCM_M 0x01C00000 // Defines “M†that indicated the
+ // length of the authentication
+ // field for CCM operations; the
+ // authentication field length
+ // equals two times (the value of
+ // CCM-M plus one). Note that the
+ // AES Engine always returns a
+ // 128-bit authentication field@@ of
+ // which the M least significant
+ // bytes are valid. All values are
+ // supported.
+#define AES_CTRL_CCM_S 22
+#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L†that indicated the
+ // width of the length field for CCM
+ // operations; the length field in
+ // bytes equals the value of CMM-L
+ // plus one. Supported values for L
+ // are (programmed value): 2 (1)@@ 4
+ // (3) and 8 (7).
+#define AES_CTRL_CCM_L_S 19
+#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a
+ // combined mode@@ using AES for
+ // both authentication and
+ // encryption. No additional mode
+ // selection is required. 0 Other
+ // mode selected 1 ccm mode selected
+#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is
+ // a combined mode@@ using the
+ // Galois field multiplier GF(2^128)
+ // for authentication and AES-CTR
+ // mode for encryption@@ the bits
+ // specify the GCM mode. 0x0 No
+ // operation 0x1 GHASH with H loaded
+ // and Y0-encrypted forced to zero
+ // 0x2 GHASH with H loaded and
+ // Y0-encrypted calculated
+ // internally 0x3 Autonomous GHASH
+ // (both H and Y0-encrypted
+ // calculated internally)
+#define AES_CTRL_GCM_S 16
+#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the
+ // Direction bit must be set to ‘1’
+ // for this mode. 0 Other mode
+ // selected 1 cbcmac mode selected
+#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the
+ // AES key size must be set to
+ // 128-bit for this mode. 0 Other
+ // mode selected 1 f9 selected
+#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the
+ // AES key size must be set to
+ // 128-bit for this mode. 0 Other
+ // mode selected 1 f8 selected
+#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected;
+ // the bits specify the XTS mode.01
+ // = Previous/intermediate tweak
+ // value and ‘j’ loaded (value is
+ // loaded via IV@@ j is loaded via
+ // the AAD length register) 0x0 No
+ // operation 0x1
+ // Previous/intermediate tweak value
+ // and ‘j’ loaded (value is loaded
+ // via IV@@ j is loaded via the AAD
+ // length register) 0x2 Key2@@ i and
+ // j loaded (i is loaded via IV@@ j
+ // is loaded via the AAD length
+ // register) 0x3 Key2 and i loaded@@
+ // j=0 (i is loaded via IV)
+#define AES_CTRL_XTS_S 11
+#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback
+ // mode (CFB128) is selected. 0
+ // other mode selected 1 cfb
+ // selected
+#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM)
+ // is selected@@ this is a counter
+ // mode with a 16-bit wide counter.
+ // 0 Other mode selected. 1 ICM mode
+ // selected
+#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for
+ // AES-CTR mode 0x0 Counter is 32
+ // bits 0x1 Counter is 64 bits 0x2
+ // Counter is 128 bits 0x3 Counter
+ // is 192 bits
+#define AES_CTRL_CTR_WIDTH_S 7
+#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for
+ // GCM and CCM@@ when
+ // encryption/decryption is
+ // required. 0 Other mode selected 1
+ // Counter mode
+#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc
+ // mode
+#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is
+ // 128 bits. 0x2 Key is 192 bits 0x3
+ // Key is 256
+#define AES_CTRL_KEY_SIZE_S 3
+#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt
+ // operation is performed. If set to
+ // ‘0’ a decrypt operation is
+ // performed. Read 0 decryption is
+ // selected Read 1 Encryption is
+ // selected
+#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status
+ // bit indicates that the 16-byte
+ // input buffer is empty@@ and the
+ // host is permitted to write the
+ // next block of data.
+#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status
+ // bit indicates that an AES output
+ // block is available for the host
+ // to retrieve.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// AES_O_C_LENGTH_0 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// AES_O_C_LENGTH_1 register.
+//
+//******************************************************************************
+#define AES_C_LENGTH_1_LENGTH_M \
+ 0x1FFFFFFF // Data length (MSW) length
+ // registers (LSW and MSW) store the
+ // cryptographic data length in
+ // bytes for all modes. Once
+ // processing with this context is
+ // started@@ this length decrements
+ // to zero. Data lengths up to (2^61
+ // – 1) bytes are allowed. For GCM@@
+ // any value up to 2^36 - 32 bytes
+ // can be used. This is because a
+ // 32-bit counter mode is used; the
+ // maximum number of 128-bit blocks
+ // is 2^32 – 2@@ resulting in a
+ // maximum number of bytes of 2^36 -
+ // 32. A write to this register
+ // triggers the engine to start
+ // using this context. This is valid
+ // for all modes except GCM and CCM.
+ // Note that for the combined
+ // modes@@ this length does not
+ // include the authentication only
+ // data; the authentication length
+ // is specified in the
+ // AES_AUTH_LENGTH register below.
+ // All modes must have a length > 0.
+ // For the combined modes@@ it is
+ // allowed to have one of the
+ // lengths equal to zero. For the
+ // basic encryption modes
+ // (ECB/CBC/CTR/ICM/CFB128) it is
+ // allowed to program zero to the
+ // length field; in that case the
+ // length is assumed infinite. All
+ // data must be byte (8-bit)
+ // aligned; bit aligned data streams
+ // are not supported by the AES
+ // Engine. For a Host read
+ // operation@@ these registers
+ // return all-zeroes.
+
+#define AES_C_LENGTH_1_LENGTH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// AES_O_AUTH_LENGTH register.
+//
+//******************************************************************************
+#define AES_AUTH_LENGTH_AUTH_M \
+ 0xFFFFFFFF // data
+
+#define AES_AUTH_LENGTH_AUTH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_0 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
+#define AES_DATA_IN_0_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_1 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
+#define AES_DATA_IN_1_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_2 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
+#define AES_DATA_IN_2_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_3 register.
+//
+//******************************************************************************
+#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
+#define AES_DATA_IN_3_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW)
+#define AES_TAG_OUT_0_HASH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW)
+#define AES_TAG_OUT_1_HASH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW)
+#define AES_TAG_OUT_2_HASH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register.
+//
+//******************************************************************************
+#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW)
+#define AES_TAG_OUT_3_HASH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_REVISION register.
+//
+//******************************************************************************
+#define AES_REVISION_SCHEME_M 0xC0000000
+#define AES_REVISION_SCHEME_S 30
+#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
+ // compatible module family. If
+ // there is no level of software
+ // compatibility a new Func number
+ // (and hence REVISION) should be
+ // assigned.
+#define AES_REVISION_FUNC_S 16
+#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by
+ // IP design owner. RTL follows a
+ // numbering such as X.Y.R.Z which
+ // are explained in this table. R
+ // changes ONLY when: (1) PDS
+ // uploads occur which may have been
+ // due to spec changes (2) Bug fixes
+ // occur (3) Resets to '0' when X or
+ // Y changes. Design team has an
+ // internal 'Z' (customer invisible)
+ // number which increments on every
+ // drop that happens due to DV and
+ // RTL updates. Z resets to 0 when R
+ // increments.
+#define AES_REVISION_R_RTL_S 11
+#define AES_REVISION_X_MAJOR_M \
+ 0x00000700 // Major Revision (X)@@ maintained
+ // by IP specification owner. X
+ // changes ONLY when: (1) There is a
+ // major feature addition. An
+ // example would be adding Master
+ // Mode to Utopia Level2. The Func
+ // field (or Class/Type in old PID
+ // format) will remain the same. X
+ // does NOT change due to: (1) Bug
+ // fixes (2) Change in feature
+ // parameters.
+
+#define AES_REVISION_X_MAJOR_S 8
+#define AES_REVISION_CUSTOM_M 0x000000C0
+#define AES_REVISION_CUSTOM_S 6
+#define AES_REVISION_Y_MINOR_M \
+ 0x0000003F // Minor Revision (Y)@@ maintained
+ // by IP specification owner. Y
+ // changes ONLY when: (1) Features
+ // are scaled (up or down).
+ // Flexibility exists in that this
+ // feature scalability may either be
+ // represented in the Y change or a
+ // specific register in the IP that
+ // indicates which features are
+ // exactly available. (2) When
+ // feature creeps from Is-Not list
+ // to Is list. But this may not be
+ // the case once it sees silicon; in
+ // which case X will change. Y does
+ // NOT change due to: (1) Bug fixes
+ // (2) Typos or clarifications (3)
+ // major functional/feature
+ // change/addition/deletion. Instead
+ // these changes may be reflected
+ // via R@@ S@@ X as applicable. Spec
+ // owner maintains a
+ // customer-invisible number 'S'
+ // which changes due to: (1)
+ // Typos/clarifications (2) Bug
+ // documentation. Note that this bug
+ // is not due to a spec change but
+ // due to implementation.
+ // Nevertheless@@ the spec tracks
+ // the IP bugs. An RTL release (say
+ // for silicon PG1.1) that occurs
+ // due to bug fix should document
+ // the corresponding spec number
+ // (X.Y.S) in its release notes.
+
+#define AES_REVISION_Y_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSCONFIG register.
+//
+//******************************************************************************
+#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \
+ 0x00000200 // If set to '1' the two context
+ // out requests
+ // (dma_req_context_out_en@@ Bit [8]
+ // above@@ and context_out interrupt
+ // enable@@ Bit [3] of AES_IRQENABLE
+ // register) are mapped on the
+ // corresponding data output request
+ // bit. In this case@@ the original
+ // ‘context out’ bit values are
+ // ignored.
+
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
+ 0x00000100 // If set to ‘1’@@ the DMA context
+ // output request is enabled (for
+ // context data out@@ e.g. TAG for
+ // authentication modes). 0 Dma
+ // disabled 1 Dma enabled
+
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
+ 0x00000080 // If set to ‘1’@@ the DMA context
+ // request is enabled. 0 Dma
+ // disabled 1 Dma enabled
+
+#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
+ 0x00000040 // If set to ‘1’@@ the DMA output
+ // request is enabled. 0 Dma
+ // disabled 1 Dma enabled
+
+#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
+ 0x00000020 // If set to ‘1’@@ the DMA input
+ // request is enabled. 0 Dma
+ // disabled 1 Dma enabled
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSSTATUS register.
+//
+//******************************************************************************
+#define AES_SYSSTATUS_RESETDONE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQSTATUS register.
+//
+//******************************************************************************
+#define AES_IRQSTATUS_CONTEXT_OUT \
+ 0x00000008 // This bit indicates
+ // authentication tag (and IV)
+ // interrupt(s) is/are active and
+ // triggers the interrupt output.
+
+#define AES_IRQSTATUS_DATA_OUT \
+ 0x00000004 // This bit indicates data output
+ // interrupt is active and triggers
+ // the interrupt output.
+
+#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
+ // interrupt is active and triggers
+ // the interrupt output.
+#define AES_IRQSTATUS_CONTEX_IN \
+ 0x00000001 // This bit indicates context
+ // interrupt is active and triggers
+ // the interrupt output.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQENABLE register.
+//
+//******************************************************************************
+#define AES_IRQENABLE_CONTEXT_OUT \
+ 0x00000008 // This bit indicates
+ // authentication tag (and IV)
+ // interrupt(s) is/are active and
+ // triggers the interrupt output.
+
+#define AES_IRQENABLE_DATA_OUT \
+ 0x00000004 // This bit indicates data output
+ // interrupt is active and triggers
+ // the interrupt output.
+
+#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input
+ // interrupt is active and triggers
+ // the interrupt output.
+#define AES_IRQENABLE_CONTEX_IN \
+ 0x00000001 // This bit indicates context
+ // interrupt is active and triggers
+ // the interrupt output.
+
+
+
+
+#endif // __HW_AES_H__
diff --git a/cc3200/hal/inc/hw_apps_config.h b/cc3200/hal/inc/hw_apps_config.h
new file mode 100644
index 0000000000..b8789b9802
--- /dev/null
+++ b/cc3200/hal/inc/hw_apps_config.h
@@ -0,0 +1,747 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+
+#ifndef __HW_APPS_CONFIG_H__
+#define __HW_APPS_CONFIG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the APPS_CONFIG register offsets.
+//
+//*****************************************************************************
+#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \
+ 0x00000000 // Patch trap address Register
+ // array
+
+#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \
+ 0x00000078
+
+#define APPS_CONFIG_O_FAULT_STATUS_REG \
+ 0x0000007C
+
+#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \
+ 0x00000080
+
+#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \
+ 0x00000084
+
+#define APPS_CONFIG_O_DMA_DONE_INT_MASK \
+ 0x0000008C
+
+#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \
+ 0x00000090
+
+#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \
+ 0x00000094
+
+#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \
+ 0x00000098
+
+#define APPS_CONFIG_O_DMA_DONE_INT_ACK \
+ 0x0000009C
+
+#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \
+ 0x000000A0
+
+#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \
+ 0x000000A4
+
+#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \
+ 0x000000A8
+
+#define APPS_CONFIG_O_RESERVD_REG_0 \
+ 0x000000AC
+
+#define APPS_CONFIG_O_GPT_TRIG_SEL \
+ 0x000000B0
+
+#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \
+ 0x000000B4
+
+#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \
+ 0x000000B8
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \
+ 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus
+ // fault is generated for the
+ // address
+ // PATCH_TRAP_ADDR_REG[n][31:0] from
+ // Idcode bus. The exception routine
+ // should take care to jump to the
+ // location where the patch
+ // correspond to this address is
+ // kept.
+
+#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_PATCH_TRAP_EN_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \
+ 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus
+ // fault is generated for the
+ // address PATCH_TRAP_ADD[n][31:0]
+ // from Idcode bus. The exception
+ // routine should take care to jump
+ // to the location where the patch
+ // correspond to this address is
+ // kept.
+
+#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_FAULT_STATUS_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \
+ 0x0000003E // This field shows because of
+ // which patch trap address the
+ // bus_fault is generated. If the
+ // PATCH_ERR bit is set, then it
+ // means the bus fault is generated
+ // because of
+ // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX]
+
+#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1
+#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \
+ 0x00000001 // This bit is set when there is a
+ // bus fault because of patched
+ // address access to the Apps boot
+ // rom. Write 0 to clear this
+ // register.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \
+ 0x00000001 // This bit is set when there is a
+ // an error in memss write access.
+ // And the address causing this
+ // error is captured in
+ // MEMSS_ERR_ADDR_REG. To capture
+ // the next error address one have
+ // to clear this bit.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_MASK register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \
+ 0x0000F000 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+ // bit 14: ADC channel 7 interrupt
+ // enable/disable bit 13: ADC
+ // channel 5 interrupt
+ // enable/disable bit 12: ADC
+ // channel 3 interrupt
+ // enable/disable bit 11: ADC
+ // channel 1 interrupt
+ // enable/disable
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12
+#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \
+ 0x00000800 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \
+ 0x00000400 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \
+ 0x00000200 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \
+ 0x00000100 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \
+ 0x00000080 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \
+ 0x00000040 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \
+ 0x00000020 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \
+ 0x00000010 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \
+ 0x00000008 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \
+ 0x00000004 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \
+ 0x00000002 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \
+ 0x00000001 // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \
+ 0x0000F000 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect bit 14: ADC channel 7 DMA
+ // Done IRQ bit 13: ADC channel 5
+ // DMA Done IRQ bit 12: ADC channel
+ // 3 DMA Done IRQ bit 11: ADC
+ // channel 1 DMA Done IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \
+ 0x00000800 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \
+ 0x00000400 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \
+ 0x00000200 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \
+ 0x00000100 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \
+ 0x00000080 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \
+ 0x00000040 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \
+ 0x00000020 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \
+ 0x00000010 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \
+ 0x00000008 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \
+ 0x00000004 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \
+ 0x00000002 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \
+ 0x00000001 // write 1 to set mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \
+ 0x0000F000 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect bit 14: ADC channel 7 DMA
+ // Done IRQ mask bit 13: ADC channel
+ // 5 DMA Done IRQ mask bit 12: ADC
+ // channel 3 DMA Done IRQ mask bit
+ // 11: ADC channel 1 DMA Done IRQ
+ // mask
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \
+ 0x00000800 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \
+ 0x00000400 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \
+ 0x00000200 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \
+ 0x00000100 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \
+ 0x00000080 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \
+ 0x00000040 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \
+ 0x00000020 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \
+ 0x00000010 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \
+ 0x00000008 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \
+ 0x00000004 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \
+ 0x00000002 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \
+ 0x00000001 // write 1 to clear mask of the
+ // corresponding DMA DONE IRQ;0 = no
+ // effect
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \
+ 0xFFFFFFFF // write 1 or 0 to clear all
+ // DMA_DONE interrupt;
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_ACK register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \
+ 0x0000F000 // write 1 to clear corresponding
+ // interrupt; 0 = no effect; bit 14:
+ // ADC channel 7 DMA Done IRQ bit
+ // 13: ADC channel 5 DMA Done IRQ
+ // bit 12: ADC channel 3 DMA Done
+ // IRQ bit 11: ADC channel 1 DMA
+ // Done IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12
+#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \
+ 0x00000800 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \
+ 0x00000400 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \
+ 0x00000200 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \
+ 0x00000100 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \
+ 0x00000080 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \
+ 0x00000040 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \
+ 0x00000020 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \
+ 0x00000010 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \
+ 0x00000008 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \
+ 0x00000004 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \
+ 0x00000002 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \
+ 0x00000001 // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \
+ 0x0000F000 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask bit 14: ADC
+ // channel 7 DMA Done IRQ bit 13:
+ // ADC channel 5 DMA Done IRQ bit
+ // 12: ADC channel 3 DMA Done IRQ
+ // bit 11: ADC channel 1 DMA Done
+ // IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \
+ 0x00000800 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \
+ 0x00000400 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \
+ 0x00000200 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \
+ 0x00000100 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \
+ 0x00000080 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \
+ 0x00000040 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \
+ 0x00000020 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \
+ 0x00000010 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \
+ 0x00000008 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \
+ 0x00000004 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \
+ 0x00000002 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \
+ 0x00000001 // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by DMA_DONE_INT mask
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register.
+//
+//******************************************************************************
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \
+ 0x0000F000 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive bit 14: ADC channel 7
+ // DMA Done IRQ bit 13: ADC channel
+ // 5 DMA Done IRQ bit 12: ADC
+ // channel 3 DMA Done IRQ bit 11:
+ // ADC channel 1 DMA Done IRQ
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \
+ 0x00000800 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \
+ 0x00000400 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \
+ 0x00000200 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \
+ 0x00000100 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \
+ 0x00000080 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \
+ 0x00000040 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \
+ 0x00000020 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \
+ 0x00000010 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \
+ 0x00000008 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \
+ 0x00000004 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \
+ 0x00000002 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \
+ 0x00000001 // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \
+ 0x00000001 // Write 1 to clear the LSB of
+ // FAULT_STATUS_REG
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_RESERVD_REG_0 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_GPT_TRIG_SEL register.
+//
+//******************************************************************************
+#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \
+ 0x000000FF // This bit is implemented for GPT
+ // trigger mode select. GPT IP
+ // support 2 modes: RTC mode and
+ // external trigger. When this bit
+ // is set to logic '1': enable
+ // external trigger mode for APPS
+ // GPT CP0 and CP1 pin. bit 0: when
+ // set '1' enable external GPT
+ // trigger 0 on GPIO0 CP0 pin else
+ // RTC mode is selected. bit 1: when
+ // set '1' enable external GPT
+ // trigger 1 on GPIO0 CP1 pin else
+ // RTC mode is selected. bit 2: when
+ // set '1' enable external GPT
+ // trigger 2 on GPIO1 CP0 pin else
+ // RTC mode is selected. bit 3: when
+ // set '1' enable external GPT
+ // trigger 3 on GPIO1 CP1 pin else
+ // RTC mode is selected. bit 4: when
+ // set '1' enable external GPT
+ // trigger 4 on GPIO2 CP0 pin else
+ // RTC mode is selected. bit 5: when
+ // set '1' enable external GPT
+ // trigger 5 on GPIO2 CP1 pin else
+ // RTC mode is selected. bit 6: when
+ // set '1' enable external GPT
+ // trigger 6 on GPIO3 CP0 pin else
+ // RTC mode is selected. bit 7: when
+ // set '1' enable external GPT
+ // trigger 7 on GPIO3 CP1 pin else
+ // RTC mode is selected.
+
+#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \
+ 0x00000007 // Capture data from d2d_spare pads
+
+#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register.
+//
+//******************************************************************************
+#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \
+ 0x00000007 // Send data to d2d_spare pads -
+ // eventually this will get
+ // registered in top die
+
+#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0
+
+
+
+#endif // __HW_APPS_CONFIG_H__
diff --git a/cc3200/hal/inc/hw_apps_rcm.h b/cc3200/hal/inc/hw_apps_rcm.h
new file mode 100644
index 0000000000..edb52d26be
--- /dev/null
+++ b/cc3200/hal/inc/hw_apps_rcm.h
@@ -0,0 +1,1506 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_APPS_RCM_H__
+#define __HW_APPS_RCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the APPS_RCM register offsets.
+//
+//*****************************************************************************
+#define APPS_RCM_O_CAMERA_CLK_GEN \
+ 0x00000000
+
+#define APPS_RCM_O_CAMERA_CLK_GATING \
+ 0x00000004
+
+#define APPS_RCM_O_CAMERA_SOFT_RESET \
+ 0x00000008
+
+#define APPS_RCM_O_MCASP_CLK_GATING \
+ 0x00000014
+
+#define APPS_RCM_O_MCASP_SOFT_RESET \
+ 0x00000018
+
+#define APPS_RCM_O_MMCHS_CLK_GEN \
+ 0x00000020
+
+#define APPS_RCM_O_MMCHS_CLK_GATING \
+ 0x00000024
+
+#define APPS_RCM_O_MMCHS_SOFT_RESET \
+ 0x00000028
+
+#define APPS_RCM_O_MCSPI_A1_CLK_GEN \
+ 0x0000002C
+
+#define APPS_RCM_O_MCSPI_A1_CLK_GATING \
+ 0x00000030
+
+#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \
+ 0x00000034
+
+#define APPS_RCM_O_MCSPI_A2_CLK_GEN \
+ 0x00000038
+
+#define APPS_RCM_O_MCSPI_A2_CLK_GATING \
+ 0x00000040
+
+#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \
+ 0x00000044
+
+#define APPS_RCM_O_UDMA_A_CLK_GATING \
+ 0x00000048
+
+#define APPS_RCM_O_UDMA_A_SOFT_RESET \
+ 0x0000004C
+
+#define APPS_RCM_O_GPIO_A_CLK_GATING \
+ 0x00000050
+
+#define APPS_RCM_O_GPIO_A_SOFT_RESET \
+ 0x00000054
+
+#define APPS_RCM_O_GPIO_B_CLK_GATING \
+ 0x00000058
+
+#define APPS_RCM_O_GPIO_B_SOFT_RESET \
+ 0x0000005C
+
+#define APPS_RCM_O_GPIO_C_CLK_GATING \
+ 0x00000060
+
+#define APPS_RCM_O_GPIO_C_SOFT_RESET \
+ 0x00000064
+
+#define APPS_RCM_O_GPIO_D_CLK_GATING \
+ 0x00000068
+
+#define APPS_RCM_O_GPIO_D_SOFT_RESET \
+ 0x0000006C
+
+#define APPS_RCM_O_GPIO_E_CLK_GATING \
+ 0x00000070
+
+#define APPS_RCM_O_GPIO_E_SOFT_RESET \
+ 0x00000074
+
+#define APPS_RCM_O_WDOG_A_CLK_GATING \
+ 0x00000078
+
+#define APPS_RCM_O_WDOG_A_SOFT_RESET \
+ 0x0000007C
+
+#define APPS_RCM_O_UART_A0_CLK_GATING \
+ 0x00000080
+
+#define APPS_RCM_O_UART_A0_SOFT_RESET \
+ 0x00000084
+
+#define APPS_RCM_O_UART_A1_CLK_GATING \
+ 0x00000088
+
+#define APPS_RCM_O_UART_A1_SOFT_RESET \
+ 0x0000008C
+
+#define APPS_RCM_O_GPT_A0_CLK_GATING \
+ 0x00000090
+
+#define APPS_RCM_O_GPT_A0_SOFT_RESET \
+ 0x00000094
+
+#define APPS_RCM_O_GPT_A1_CLK_GATING \
+ 0x00000098
+
+#define APPS_RCM_O_GPT_A1_SOFT_RESET \
+ 0x0000009C
+
+#define APPS_RCM_O_GPT_A2_CLK_GATING \
+ 0x000000A0
+
+#define APPS_RCM_O_GPT_A2_SOFT_RESET \
+ 0x000000A4
+
+#define APPS_RCM_O_GPT_A3_CLK_GATING \
+ 0x000000A8
+
+#define APPS_RCM_O_GPT_A3_SOFT_RESET \
+ 0x000000AC
+
+#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \
+ 0x000000B0
+
+#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \
+ 0x000000B4
+
+#define APPS_RCM_O_CRYPTO_CLK_GATING \
+ 0x000000B8
+
+#define APPS_RCM_O_CRYPTO_SOFT_RESET \
+ 0x000000BC
+
+#define APPS_RCM_O_MCSPI_S0_CLK_GATING \
+ 0x000000C8
+
+#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \
+ 0x000000CC
+
+#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \
+ 0x000000D0
+
+#define APPS_RCM_O_I2C_CLK_GATING \
+ 0x000000D8
+
+#define APPS_RCM_O_I2C_SOFT_RESET \
+ 0x000000DC
+
+#define APPS_RCM_O_APPS_LPDS_REQ \
+ 0x000000E4
+
+#define APPS_RCM_O_APPS_TURBO_REQ \
+ 0x000000EC
+
+#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \
+ 0x00000108
+
+#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \
+ 0x0000010C
+
+#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \
+ 0x00000110
+
+#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \
+ 0x00000114
+
+#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \
+ 0x00000118
+
+#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \
+ 0x00000120
+
+#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \
+ 0x00000124
+
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CAMERA_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of Camera func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8
+#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \
+ 0x000000F8
+
+#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of Camera func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CAMERA_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17
+#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable camera clk during
+ // deep-sleep mode
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9
+#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable camera clk during
+ // sleep mode ; 0- Disable camera
+ // clk during sleep mode
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1
+#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable camera clk during run
+ // mode ; 0- Disable camera clk
+ // during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CAMERA_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \
+ 0x00000002 // 1 - Camera clocks/resets are
+ // enabled ; 0 - Camera
+ // clocks/resets are disabled
+
+#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for Camera-core
+ // ; 0 - De-assert reset for
+ // Camera-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17
+#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MCASP clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MCASP_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9
+#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MCASP clk during sleep
+ // mode ; 0- Disable MCASP clk
+ // during sleep mode
+
+#define APPS_RCM_MCASP_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1
+#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MCASP clk during run
+ // mode ; 0- Disable MCASP clk
+ // during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \
+ 0x00000002 // 1 - MCASP Clocks/resets are
+ // enabled ; 0 - MCASP Clocks/resets
+ // are disabled
+
+#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for MCASP-core
+ // ; 0 - De-assert reset for
+ // MCASP-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MMCHS_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MMCHS func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8
+#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \
+ 0x000000F8
+
+#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MMCHS func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MMCHS_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17
+#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MMCHS clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9
+#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MMCHS clk during sleep
+ // mode ; 0- Disable MMCHS clk
+ // during sleep mode
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1
+#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MMCHS clk during run
+ // mode ; 0- Disable MMCHS clk
+ // during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MMCHS_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \
+ 0x00000002 // 1 - MMCHS Clocks/resets are
+ // enabled ; 0 - MMCHS Clocks/resets
+ // are disabled
+
+#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for MMCHS-core
+ // ; 0 - De-assert reset for
+ // MMCHS-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A1_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \
+ 0x00010000 // 0 - XTAL clk is used as baud clk
+ // for MCSPI_A1 ; 1 - PLL divclk is
+ // used as baud clk for MCSPI_A1.
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \
+ 0x0000F800
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A1 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \
+ 0x000000F8
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A1 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A1_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17
+#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MCSPI_A1 clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9
+#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MCSPI_A1 clk during
+ // sleep mode ; 0- Disable MCSPI_A1
+ // clk during sleep mode
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1
+#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MCSPI_A1 clk during
+ // run mode ; 0- Disable MCSPI_A1
+ // clk during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A1_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \
+ 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are
+ // enabled ; 0 - MCSPI_A1
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for
+ // MCSPI_A1-core ; 0 - De-assert
+ // reset for MCSPI_A1-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A2_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \
+ 0x00010000 // 0 - XTAL clk is used as baud-clk
+ // for MCSPI_A2 ; 1 - PLL divclk is
+ // used as baud-clk for MCSPI_A2
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \
+ 0x0000F800
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A2 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \
+ 0x000000F8
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A2 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A2_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17
+#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MCSPI_A2 clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9
+#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MCSPI_A2 clk during
+ // sleep mode ; 0- Disable MCSPI_A2
+ // clk during sleep mode
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1
+#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MCSPI_A2 clk during
+ // run mode ; 0- Disable MCSPI_A2
+ // clk during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A2_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \
+ 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are
+ // enabled ; 0 - MCSPI_A2
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for
+ // MCSPI_A2-core ; 0 - De-assert
+ // reset for MCSPI_A2-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UDMA_A_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable UDMA_A clk during
+ // deep-sleep mode 0 - Disable
+ // UDMA_A clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9
+#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable UDMA_A clk during
+ // sleep mode 0 - Disable UDMA_A clk
+ // during sleep mode ;
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1
+#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable UDMA_A clk during run
+ // mode 0 - Disable UDMA_A clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UDMA_A_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \
+ 0x00000002 // 1 - UDMA_A Clocks/Resets are
+ // enabled ; 0 - UDMA_A
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for DMA_A ; 0 -
+ // De-assert reset for DMA_A
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_A_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_A clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_A clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_A clk during
+ // sleep mode 0 - Disable GPIO_A clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_A clk during run
+ // mode 0 - Disable GPIO_A clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_A_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_A Clocks/Resets are
+ // enabled ; 0 - GPIO_A
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_A ; 0
+ // - De-assert reset for GPIO_A
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_B_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_B clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_B clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_B clk during
+ // sleep mode 0 - Disable GPIO_B clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_B clk during run
+ // mode 0 - Disable GPIO_B clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_B_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_B Clocks/Resets are
+ // enabled ; 0 - GPIO_B
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_B ; 0
+ // - De-assert reset for GPIO_B
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_C_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_C clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_C clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_C clk during
+ // sleep mode 0 - Disable GPIO_C clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_C clk during run
+ // mode 0 - Disable GPIO_C clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_C_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_C Clocks/Resets are
+ // enabled ; 0 - GPIO_C
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_C ; 0
+ // - De-assert reset for GPIO_C
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_D_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_D clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_D clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_D clk during
+ // sleep mode 0 - Disable GPIO_D clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_D clk during run
+ // mode 0 - Disable GPIO_D clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_D_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_D Clocks/Resets are
+ // enabled ; 0 - GPIO_D
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_D ; 0
+ // - De-assert reset for GPIO_D
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_E_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_E clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_E clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_E clk during
+ // sleep mode 0 - Disable GPIO_E clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_E clk during run
+ // mode 0 - Disable GPIO_E clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_E_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_E Clocks/Resets are
+ // enabled ; 0 - GPIO_E
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_E ; 0
+ // - De-assert reset for GPIO_E
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_WDOG_A_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \
+ 0x03000000 // "00" - Sysclk ; "01" - REF_CLK
+ // (38.4 MHz) ; "10/11" - Slow_clk
+
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable WDOG_A clk during
+ // deep-sleep mode 0 - Disable
+ // WDOG_A clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable WDOG_A clk during
+ // sleep mode 0 - Disable WDOG_A clk
+ // during sleep mode ;
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable WDOG_A clk during run
+ // mode 0 - Disable WDOG_A clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_WDOG_A_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \
+ 0x00000002 // 1 - WDOG_A Clocks/Resets are
+ // enabled ; 0 - WDOG_A
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for WDOG_A ; 0
+ // - De-assert reset for WDOG_A
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A0_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable UART_A0 clk during
+ // deep-sleep mode 0 - Disable
+ // UART_A0 clk during deep-sleep
+ // mode ;
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9
+#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable UART_A0 clk during
+ // sleep mode 0 - Disable UART_A0
+ // clk during sleep mode ;
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1
+#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable UART_A0 clk during
+ // run mode 0 - Disable UART_A0 clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A0_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \
+ 0x00000002 // 1 - UART_A0 Clocks/Resets are
+ // enabled ; 0 - UART_A0
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for UART_A0 ; 0
+ // - De-assert reset for UART_A0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A1_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable UART_A1 clk during
+ // deep-sleep mode 0 - Disable
+ // UART_A1 clk during deep-sleep
+ // mode ;
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9
+#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable UART_A1 clk during
+ // sleep mode 0 - Disable UART_A1
+ // clk during sleep mode ;
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1
+#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable UART_A1 clk during
+ // run mode 0 - Disable UART_A1 clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A1_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \
+ 0x00000002 // 1 - UART_A1 Clocks/Resets are
+ // enabled ; 0 - UART_A1
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // UART_A1 ; 0 - De-assert the soft
+ // reset for UART_A1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A0_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A0 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A0 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A0 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A0 clock during sleep
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A0 clock
+ // during run ; 0 - Disable the
+ // GPT_A0 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A0_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A0 clocks/resets are
+ // enabled ; 0 - GPT_A0
+ // clocks/resets are disabled
+
+#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A0 ; 0 - De-assert the soft
+ // reset for GPT_A0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A1_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A1 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A1 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A1 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A1 clock during sleep
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A1 clock
+ // during run ; 0 - Disable the
+ // GPT_A1 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A1_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A1 clocks/resets are
+ // enabled ; 0 - GPT_A1
+ // clocks/resets are disabled
+
+#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A1 ; 0 - De-assert the soft
+ // reset for GPT_A1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A2_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A2 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A2 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A2 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A2 clock during sleep
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A2 clock
+ // during run ; 0 - Disable the
+ // GPT_A2 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A2_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A2 clocks/resets are
+ // enabled ; 0 - GPT_A2
+ // clocks/resets are disabled
+
+#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A2 ; 0 - De-assert the soft
+ // reset for GPT_A2
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A3_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A3 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A3 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A3 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A3 clock during sleep
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A3 clock
+ // during run ; 0 - Disable the
+ // GPT_A3 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A3_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A3 Clocks/resets are
+ // enabled ; 0 - GPT_A3
+ // Clocks/resets are disabled
+
+#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A3 ; 0 - De-assert the soft
+ // reset for GPT_A3
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \
+ 0x03FF0000
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \
+ 0x0000FFFF
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \
+ 0x00010000 // 1 - Assert the reset for MCASP
+ // Frac-clk div; 0 - Donot assert
+ // the reset for MCASP frac clk-div
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \
+ 0x000003FF
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CRYPTO_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable the Crypto clock
+ // during deep-sleep
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9
+#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the Crypto clock
+ // during sleep ; 0 - Disable the
+ // Crypto clock during sleep
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1
+#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the Crypto clock
+ // during run ; 0 - Disable the
+ // Crypto clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CRYPTO_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \
+ 0x00000002 // 1 - Crypto clocks/resets are
+ // enabled ; 0 - Crypto
+ // clocks/resets are disabled
+
+#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // Crypto ; 0 - De-assert the soft
+ // reset for Crypto
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_S0_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable the MCSPI_S0 clock
+ // during deep-sleep
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9
+#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the MCSPI_S0 clock
+ // during sleep ; 0 - Disable the
+ // MCSPI_S0 clock during sleep
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1
+#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the MCSPI_S0 clock
+ // during run ; 0 - Disable the
+ // MCSPI_S0 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_S0_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \
+ 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are
+ // enabled ; 0 - MCSPI_S0
+ // Clocks/resets are disabled
+
+#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // MCSPI_S0 ; 0 - De-assert the soft
+ // reset for MCSPI_S0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \
+ 0x00010000 // 0 - XTAL clk is used as baud-clk
+ // for MCSPI_S0 ; 1 - PLL divclk is
+ // used as buad-clk for MCSPI_S0
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \
+ 0x0000F800
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_S0 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \
+ 0x000000F8
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_S0 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_I2C_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the I2C Clock during
+ // deep-sleep 0 - Disable the I2C
+ // clock during deep-sleep
+
+#define APPS_RCM_I2C_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_I2C_CLK_GATING_NU1_S 9
+#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the I2C clock during
+ // sleep ; 0 - Disable the I2C clock
+ // during sleep
+
+#define APPS_RCM_I2C_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_I2C_CLK_GATING_NU2_S 1
+#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the I2C clock during
+ // run ; 0 - Disable the I2C clock
+ // during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_I2C_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \
+ 0x00000002 // 1 - I2C Clocks/Resets are
+ // enabled ; 0 - I2C clocks/resets
+ // are disabled
+
+#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // Shared-I2C ; 0 - De-assert the
+ // soft reset for Shared-I2C
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_LPDS_REQ register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \
+ 0x00000001 // 1 - Request for LPDS
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_TURBO_REQ register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \
+ 0x00000001 // 1 - Request for TURBO
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \
+ 0x00000002 // 1 - Enable the NWP to wake APPS
+ // from deep-sleep ; 0 - Disable NWP
+ // to wake APPS from deep-sleep
+
+#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \
+ 0x00000001 // 1 - Enable deep-sleep wake timer
+ // in APPS RCM for deep-sleep; 0 -
+ // Disable deep-sleep wake timer in
+ // APPS RCM
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \
+ 0xFFFF0000 // Configuration (in slow_clks)
+ // which says when to request for
+ // OPP during deep-sleep exit
+
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \
+ 0x0000FFFF // Configuration (in slow_clks)
+ // which says when to request for
+ // WAKE during deep-sleep exit
+
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \
+ 0x00000002 // 1- Enable the sleep wakeup due
+ // to NWP request. 0- Disable the
+ // sleep wakeup due to NWP request
+
+#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \
+ 0x00000001 // 1- Enable the sleep wakeup due
+ // to sleep-timer; 0-Disable the
+ // sleep wakeup due to sleep-timer
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \
+ 0xFFFFFFFF // Configuration (number of
+ // sysclks-80MHz) for the Sleep
+ // wakeup timer
+
+#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \
+ 0x00000001 // When 1 => APPS generated a wake
+ // request to NWP (When NWP is in
+ // any of its low-power modes :
+ // SLP/DSLP/LPDS)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \
+ 0x00000008 // 1 - Indicates that deep-sleep
+ // timer expiry had caused the
+ // wakeup from deep-sleep
+
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \
+ 0x00000004 // 1 - Indicates that sleep timer
+ // expiry had caused the wakeup from
+ // sleep
+
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \
+ 0x00000002 // 1 - Indicates that NWP had
+ // caused the wakeup from deep-sleep
+
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \
+ 0x00000001 // 1 - Indicates that NWP had
+ // caused the wakeup from Sleep
+
+
+
+
+#endif // __HW_APPS_RCM_H__
diff --git a/cc3200/hal/inc/hw_camera.h b/cc3200/hal/inc/hw_camera.h
new file mode 100644
index 0000000000..4461a28467
--- /dev/null
+++ b/cc3200/hal/inc/hw_camera.h
@@ -0,0 +1,519 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAMERA_H__
+#define __HW_CAMERA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAMERA register offsets.
+//
+//*****************************************************************************
+#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP
+ // revision code ( Parallel Mode)
+#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the
+ // various parameters of the OCP
+ // interface (CCP and Parallel Mode)
+#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status
+ // information about the module
+ // excluding the interrupt status
+ // information (CCP and Parallel
+ // Mode)
+#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups
+ // all the status of the module
+ // internal events that can generate
+ // an interrupt (CCP & Parallel
+ // Mode)
+#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register
+ // allows to enable/disable the
+ // module internal sources of
+ // interrupt on an event-by-event
+ // basis (CCP & Parallel Mode)
+#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the
+ // various parameters of the Camera
+ // Core block (CCP & Parallel Mode)
+#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA
+ // interface of the Camera Core
+ // block (CCP & Parallel Mode)
+#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value
+ // of the clock divisor used to
+ // generate the external clock
+ // (Parallel Mode)
+#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to
+ // the FIFO and read from the FIFO
+ // (CCP & Parallel Mode)
+#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status
+ // of some important variables of
+ // the camera core module (CCP &
+ // Parallel Mode)
+#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values
+ // of the generic parameters of the
+ // module
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_REVISION register.
+//
+//******************************************************************************
+#define CAMERA_CC_REVISION_REV_M \
+ 0x000000FF // IP revision [7:4] Major revision
+ // [3:0] Minor revision Examples:
+ // 0x10 for 1.0 0x21 for 2.1
+
+#define CAMERA_CC_REVISION_REV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_SYSCONFIG register.
+//
+//******************************************************************************
+#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
+ 0x00000018 // Slave interface power management
+ // req/ack control """00""
+ // Force-idle. An idle request is
+ // acknoledged unconditionally"
+ // """01"" No-idle. An idle request
+ // is never acknowledged" """10""
+ // reserved (Smart-idle not
+ // implemented)"
+
+#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
+#define CAMERA_CC_SYSCONFIG_SOFT_RESET \
+ 0x00000002 // Software reset. Set this bit to
+ // 1 to trigger a module reset. The
+ // bit is automatically reset by the
+ // hardware. During reset it always
+ // returns 0. 0 Normal mode 1 The
+ // module is reset
+
+#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
+ 0x00000001 // Internal OCP clock gating
+ // strategy 0 OCP clock is
+ // free-running 1 Automatic OCP
+ // clock gating strategy is applied
+ // based on the OCP interface
+ // activity
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_SYSSTATUS register.
+//
+//******************************************************************************
+#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
+ 0x00000001 // Internal Reset Monitoring 0
+ // Internal module reset is on-going
+ // 1 Reset completed
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_IRQSTATUS register.
+//
+//******************************************************************************
+#define CAMERA_CC_IRQSTATUS_FS_IRQ \
+ 0x00080000 // Frame Start has occurred 0 Event
+ // false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_LE_IRQ \
+ 0x00040000 // Line End has occurred 0 Event
+ // false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_LS_IRQ \
+ 0x00020000 // Line Start has occurred 0 Event
+ // false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_FE_IRQ \
+ 0x00010000 // Frame End has occurred 0 Event
+ // false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
+ 0x00000800 // FSP code error 0 Event false "1
+ // Event is true (""pending"")" 0
+ // Event status bit unchanged 1
+ // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
+ 0x00000400 // Frame Height Error 0 Event false
+ // "1 Event is true (""pending"")" 0
+ // Event status bit unchanged 1
+ // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
+ 0x00000200 // False Synchronization Code 0
+ // Event false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
+ 0x00000100 // Shifted Synchronization Code 0
+ // Event false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
+ 0x00000010 // FIFO is not empty 0 Event false
+ // "1 Event is true (""pending"")" 0
+ // Event status bit unchanged 1
+ // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
+ 0x00000008 // FIFO is full 0 Event false "1
+ // Event is true (""pending"")" 0
+ // Event status bit unchanged 1
+ // Event status bit is reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
+ 0x00000004 // FIFO threshold has been reached
+ // 0 Event false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
+ 0x00000002 // FIFO overflow has occurred 0
+ // Event false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
+ 0x00000001 // FIFO underflow has occurred 0
+ // Event false "1 Event is true
+ // (""pending"")" 0 Event status bit
+ // unchanged 1 Event status bit is
+ // reset
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_IRQENABLE register.
+//
+//******************************************************************************
+#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
+ 0x00080000 // Frame Start Interrupt Enable 0
+ // Event is masked 1 Event generates
+ // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
+ 0x00040000 // Line End Interrupt Enable 0
+ // Event is masked 1 Event generates
+ // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
+ 0x00020000 // Line Start Interrupt Enable 0
+ // Event is masked 1 Event generates
+ // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
+ 0x00010000 // Frame End Interrupt Enable 0
+ // Event is masked 1 Event generates
+ // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
+ 0x00000800 // FSP code Interrupt Enable 0
+ // Event is masked 1 Event generates
+ // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
+ 0x00000400 // Frame Height Error Interrupt
+ // Enable 0 Event is masked 1 Event
+ // generates an interrupt when it
+ // occurs
+
+#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
+ 0x00000200 // False Synchronization Code
+ // Interrupt Enable 0 Event is
+ // masked 1 Event generates an
+ // interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
+ 0x00000100 // False Synchronization Code
+ // Interrupt Enable 0 Event is
+ // masked 1 Event generates an
+ // interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
+ 0x00000010 // FIFO Threshold Interrupt Enable
+ // 0 Event is masked 1 Event
+ // generates an interrupt when it
+ // occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
+ 0x00000008 // FIFO Threshold Interrupt Enable
+ // 0 Event is masked 1 Event
+ // generates an interrupt when it
+ // occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
+ 0x00000004 // FIFO Threshold Interrupt Enable
+ // 0 Event is masked 1 Event
+ // generates an interrupt when it
+ // occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
+ 0x00000002 // FIFO Overflow Interrupt Enable 0
+ // Event is masked 1 Event generates
+ // an interrupt when it occurs
+
+#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
+ 0x00000001 // FIFO Underflow Interrupt Enable
+ // 0 Event is masked 1 Event
+ // generates an interrupt when it
+ // occurs
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
+//
+//******************************************************************************
+#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
+ 0x00080000 // Synchronize all camera sensor
+ // inputs This must be set during
+ // the configuration phase before
+ // CC_EN set to '1'. This can be
+ // used in very high frequency to
+ // avoid dependancy to the IO
+ // timings. 0 No synchro (most of
+ // applications) 1 Synchro enabled
+ // (should never be required)
+
+#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite
+ // states machines of the camera
+ // core module - by writing a 1 to
+ // this bit. must be applied when
+ // CC_EN = 0 Reads returns 0
+#define CAMERA_CC_CTRL_CC_FRAME_TRIG \
+ 0x00020000 // Set the modality in which CC_EN
+ // works when a disabling of the
+ // sensor camera core is wanted "If
+ // CC_FRAME_TRIG = 1 by writing
+ // ""0"" to CC_EN" the module is
+ // disabled at the end of the frame
+ // "If CC_FRAME_TRIG = 0 by writing
+ // ""0"" to CC_EN" the module is
+ // disabled immediately
+
+#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of
+ // the camera core module "By
+ // writing ""1"" to this field the
+ // module is enabled." "By writing
+ // ""0"" to this field the module is
+ // disabled at" the end of the frame
+ // if CC_FRAM_TRIG =1 and is
+ // disabled immediately if
+ // CC_FRAM_TRIG = 0
+#define CAMERA_CC_CTRL_NOBT_SYNCHRO \
+ 0x00002000 // Enables to start at the
+ // beginning of the frame or not in
+ // NoBT 0 Acquisition starts when
+ // Vertical synchro is high 1
+ // Acquisition starts when Vertical
+ // synchro goes from low to high
+ // (beginning of the frame) -
+ // Recommended.
+
+#define CAMERA_CC_CTRL_BT_CORRECT \
+ 0x00001000 // Enables the correction within
+ // the sync codes in BT mode 0
+ // correction is not enabled 1
+ // correction is enabled
+
+#define CAMERA_CC_CTRL_PAR_ORDERCAM \
+ 0x00000800 // Enables swap between image-data
+ // in parallel mode 0 swap is not
+ // enabled 1 swap is enabled
+
+#define CAMERA_CC_CTRL_PAR_CLK_POL \
+ 0x00000400 // Inverts the clock coming from
+ // the sensor in parallel mode 0
+ // clock not inverted - data sampled
+ // on rising edge 1 clock inverted -
+ // data sampled on falling edge
+
+#define CAMERA_CC_CTRL_NOBT_HS_POL \
+ 0x00000200 // Sets the polarity of the
+ // synchronization signals in NOBT
+ // parallel mode 0 CAM_P_HS is
+ // active high 1 CAM_P_HS is active
+ // low
+
+#define CAMERA_CC_CTRL_NOBT_VS_POL \
+ 0x00000100 // Sets the polarity of the
+ // synchronization signals in NOBT
+ // parallel mode 0 CAM_P_VS is
+ // active high 1 CAM_P_VS is active
+ // low
+
+#define CAMERA_CC_CTRL_PAR_MODE_M \
+ 0x0000000E // Sets the Protocol Mode of the
+ // Camera Core module in parallel
+ // mode (when CCP_MODE = 0) """000""
+ // Parallel NOBT 8-bit" """001""
+ // Parallel NOBT 10-bit" """010""
+ // Parallel NOBT 12-bit" """011""
+ // reserved" """100"" Parallet BT
+ // 8-bit" """101"" Parallel BT
+ // 10-bit" """110"" reserved"
+ // """111"" FIFO test mode. Refer to
+ // Table 12 - FIFO Write and Read
+ // access"
+
+#define CAMERA_CC_CTRL_PAR_MODE_S 1
+#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode
+ // 0 CCP mode disabled 1 CCP mode
+ // enabled
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_CTRL_DMA register.
+//
+//******************************************************************************
+#define CAMERA_CC_CTRL_DMA_DMA_EN \
+ 0x00000100 // Sets the number of dma request
+ // lines 0 DMA interface disabled
+ // The DMA request line stays
+ // inactive 1 DMA interface enabled
+ // The DMA request line is
+ // operational
+
+#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
+ 0x0000007F // Sets the threshold of the FIFO
+ // the assertion of the dmarequest
+ // line takes place when the
+ // threshold is reached.
+ // """0000000"" threshold set to 1"
+ // """0000001"" threshold set to 2"
+ // … """1111111"" threshold set to
+ // 128"
+
+#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_CTRL_XCLK register.
+//
+//******************************************************************************
+#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
+ 0x0000001F // Sets the clock divisor value for
+ // CAM_XCLK generation. based on
+ // CAM_MCK (value of CAM_MCLK is
+ // 96MHz) """00000"" CAM_XCLK Stable
+ // Low Level" Divider not enabled
+ // """00001"" CAM_XCLK Stable High
+ // Level" Divider not enabled from 2
+ // to 30 CAM_XCLK = CAM_MCLK /
+ // XCLK_DIV """11111"" Bypass -
+ // CAM_XCLK = CAM_MCLK"
+
+#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_FIFO_DATA register.
+//
+//******************************************************************************
+#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
+ 0xFFFFFFFF // Writes the 32-bit word into the
+ // FIFO Reads the 32-bit word from
+ // the FIFO
+
+#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
+//
+//******************************************************************************
+#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
+ 0xFF000000 // FIFO READ Pointer This field
+ // shows the value of the FIFO read
+ // pointer Expected value ranges
+ // from 0 to 127
+
+#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
+#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
+ 0x00FF0000 // FIFO WRITE pointer This field
+ // shows the value of the FIFO write
+ // pointer Expected value ranges
+ // from 0 to 127
+
+#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
+#define CAMERA_CC_TEST_FIFO_LEVEL_M \
+ 0x0000FF00 // FIFO level (how many 32-bit
+ // words the FIFO contains) This
+ // field shows the value of the FIFO
+ // level and can assume values from
+ // 0 to 128
+
+#define CAMERA_CC_TEST_FIFO_LEVEL_S 8
+#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
+ 0x000000FF // FIFO level peak This field shows
+ // the max value of the FIFO level
+ // and can assume values from 0 to
+ // 128
+
+#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// CAMERA_O_CC_GEN_PAR register.
+//
+//******************************************************************************
+#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
+ 0x00000007 // Camera Core FIFO DEPTH generic
+ // parameter
+
+#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
+
+
+
+#endif // __HW_CAMERA_H__
diff --git a/cc3200/hal/inc/hw_common_reg.h b/cc3200/hal/inc/hw_common_reg.h
new file mode 100644
index 0000000000..417544ad48
--- /dev/null
+++ b/cc3200/hal/inc/hw_common_reg.h
@@ -0,0 +1,1117 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMMON_REG_H__
+#define __HW_COMMON_REG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the COMMON_REG register offsets.
+//
+//*****************************************************************************
+#define COMMON_REG_O_I2C_Properties_Register \
+ 0x00000000
+
+#define COMMON_REG_O_SPI_Properties_Register \
+ 0x00000004
+
+#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \
+ 0x0000000C
+
+#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \
+ 0x00000010
+
+#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \
+ 0x00000014
+
+#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \
+ 0x00000018
+
+#define COMMON_REG_O_Flash_ctrl_reg \
+ 0x0000001C
+
+#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \
+ 0x00000024
+
+#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \
+ 0x00000028
+
+#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \
+ 0x0000002C
+
+#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \
+ 0x00000030
+
+#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \
+ 0x00000034
+
+#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \
+ 0x00000038
+
+#define COMMON_REG_O_GPIO_properties_register \
+ 0x0000003C
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \
+ 0x00000040
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \
+ 0x00000044
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \
+ 0x00000048
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \
+ 0x0000004C
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \
+ 0x00000050
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \
+ 0x00000054
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \
+ 0x00000058
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \
+ 0x0000005C
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \
+ 0x00000060
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \
+ 0x00000064
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \
+ 0x00000068
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \
+ 0x0000006C
+
+#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \
+ 0x00000070
+
+#define COMMON_REG_O_NW_SEMAPPHORE_PEND \
+ 0x00000074
+
+#define COMMON_REG_O_SEMAPHORE_STATUS \
+ 0x00000078
+
+#define COMMON_REG_O_IDMEM_TIM_Update \
+ 0x0000007C
+
+#define COMMON_REG_O_FPGA_ROM_WR_EN \
+ 0x00000080
+
+#define COMMON_REG_O_NW_INT_MASK \
+ 0x00000084
+
+#define COMMON_REG_O_NW_INT_MASK_SET \
+ 0x00000088
+
+#define COMMON_REG_O_NW_INT_MASK_CLR \
+ 0x0000008C
+
+#define COMMON_REG_O_NW_INT_STS_CLR \
+ 0x00000090
+
+#define COMMON_REG_O_NW_INT_ACK 0x00000094
+#define COMMON_REG_O_NW_INT_TRIG \
+ 0x00000098
+
+#define COMMON_REG_O_NW_INT_STS_MASKED \
+ 0x0000009C
+
+#define COMMON_REG_O_NW_INT_STS_RAW \
+ 0x000000A0
+
+#define COMMON_REG_O_APPS_INT_MASK \
+ 0x000000A4
+
+#define COMMON_REG_O_APPS_INT_MASK_SET \
+ 0x000000A8
+
+#define COMMON_REG_O_APPS_INT_MASK_CLR \
+ 0x000000AC
+
+#define COMMON_REG_O_APPS_INT_STS_CLR \
+ 0x000000B0
+
+#define COMMON_REG_O_APPS_INT_ACK \
+ 0x000000B4
+
+#define COMMON_REG_O_APPS_INT_TRIG \
+ 0x000000B8
+
+#define COMMON_REG_O_APPS_INT_STS_MASKED \
+ 0x000000BC
+
+#define COMMON_REG_O_APPS_INT_STS_RAW \
+ 0x000000C0
+
+#define COMMON_REG_O_IDMEM_TIM_Updated \
+ 0x000000C4
+
+#define COMMON_REG_O_APPS_GPIO_TRIG_EN \
+ 0x000000C8
+
+#define COMMON_REG_O_EMU_DEBUG_REG \
+ 0x000000CC
+
+#define COMMON_REG_O_SEMAPHORE_STATUS2 \
+ 0x000000D0
+
+#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \
+ 0x000000D4
+
+#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \
+ 0x000000D8
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_I2C_Properties_Register register.
+//
+//******************************************************************************
+#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \
+ 0x00000003 // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SPI_Properties_Register register.
+//
+//******************************************************************************
+#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \
+ 0x00000003 // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \
+ 0x0000000F // Interrupt enable APPS bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_sh_resource_Interrupt_status register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \
+ 0x0000000F // Interrupt enable APPS bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register.
+//
+//******************************************************************************
+#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \
+ 0x0000000F // Interrupt enable NWP bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NWP_sh_resource_Interrupt_status register.
+//
+//******************************************************************************
+#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \
+ 0x0000000F // Interrupt enable NWP bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Flash_ctrl_reg register.
+//
+//******************************************************************************
+#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \
+ 0x00000003 // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M0_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \
+ 0x0003FFFF // Master 0 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M1_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \
+ 0x0003FFFF // Master 1 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M2_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \
+ 0x0003FFFF // Master 2 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M3_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \
+ 0x0003FFFF // Master 3 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M4_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \
+ 0x0003FFFF // Master 4 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M5_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \
+ 0x0003FFFF // Master 5 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_GPIO_properties_register register.
+//
+//******************************************************************************
+#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \
+ 0x000003FF // Shared GPIO configuration
+ // register. Bit [1:0] to configure
+ // GPIO0 Bit [3:2] to configure
+ // GPIO1 Bit [5:4] to configure
+ // GPIO2 Bit [7:6] to configure
+ // GPIO3 Bit [9:8] to configure
+ // GPIO4 each GPIO can be
+ // individully selected. When “00â€
+ // GPIO is free resource. When “01â€
+ // GPIO is APPS resource. When “10â€
+ // GPIO is NWP resource. Writing 11
+ // doesnt have any affect, i.e. If
+ // one write only relevant gpio
+ // semaphore and other bits are 1s,
+ // it'll not disturb the other
+ // semaphore bits. For example : Say
+ // If NW wants to take control of
+ // gpio-1, one should write
+ // 10'b11_1111_1011 and if one wants
+ // to release it write
+ // 10'b11_1111_0011.
+
+#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE1 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE2 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE3 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE4 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE5 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE6 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE7 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE8 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE9 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE10 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE11 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE12 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \
+ 0xFFFFFFFF // APPS NW semaphore register - not
+ // reflected in status.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_SEMAPPHORE_PEND register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \
+ 0xFFFFFFFF // APPS SEMAPOHORE STATUS
+
+#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_SEMAPPHORE_PEND register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \
+ 0xFFFFFFFF // NW SEMAPHORE STATUS
+
+#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_STATUS register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \
+ 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore
+ // status of flash_control 7:6
+ // :semaphore status of
+ // gpio_properties 5:4
+ // :semaphore status of
+ // spi_propertie 1:0 :semaphore
+ // status of i2c_propertie
+
+#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_IDMEM_TIM_Update register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_FPGA_ROM_WR_EN register.
+//
+//******************************************************************************
+#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \
+ 0x00000001 // when '1' enables Write into
+ // IDMEM CORE ROM, APPS ROM, NWP ROM
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_MASK register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \
+ 0xFFFFFFFF // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_MASK_SET register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \
+ 0xFFFFFFFF // write 1 to set corresponding bit
+ // in NW_INT_MASK;0 = no effect
+
+#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_MASK_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // bit in NW_INT_MASK;0 = no effect
+
+#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_STS_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+ // interrupt is not lost if coincide
+ // with write operation
+
+#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_ACK register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt;0 = no effect
+
+#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_TRIG register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \
+ 0xFFFFFFFF // Writing a 1 to a bit in this
+ // register causes the the Host CPU
+ // if enabled (not masked). This
+ // register is self-clearing.
+ // Writing 0 has no effect
+
+#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_STS_MASKED register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by NW_INT mask
+
+#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_STS_RAW register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_MASK register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \
+ 0xFFFFFFFF // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_MASK_SET register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \
+ 0xFFFFFFFF // write 1 to set corresponding bit
+ // in APPS_INT_MASK;0 = no effect
+
+#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_MASK_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // bit in APPS_INT_MASK;0 = no
+ // effect
+
+#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_STS_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+ // interrupt is not lost if coincide
+ // with write operation
+
+#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_ACK register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt;0 = no effect
+
+#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_TRIG register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \
+ 0xFFFFFFFF // Writing a 1 to a bit in this
+ // register causes the the Host CPU
+ // if enabled (not masked). This
+ // register is self-clearing.
+ // Writing 0 has no effect
+
+#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_STS_MASKED register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by APPS_INT mask
+
+#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_STS_RAW register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_IDMEM_TIM_Updated register.
+//
+//******************************************************************************
+#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \
+ 0x00000001 // toggle in this signal
+ // indicatesIDMEM_TIM_UPDATE
+ // register mentioned above is
+ // updated.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_GPIO_TRIG_EN register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \
+ 0x0000001F // APPS GPIO Trigger EN control.
+ // Bit 0: when '1' enable GPIO 0
+ // trigger. This bit enables trigger
+ // for all GPIO 0 pins (GPIO 0 to
+ // GPIO7). Bit 1: when '1' enable
+ // GPIO 1 trigger. This bit enables
+ // trigger for all GPIO 1 pins (
+ // GPIO8 to GPIO15). Bit 2: when '1'
+ // enable GPIO 2 trigger. This bit
+ // enables trigger for all GPIO 2
+ // pins (GPIO16 to GPIO23). Bit 3:
+ // when '1' enable GPIO 3 trigger.
+ // This bit enables trigger for all
+ // GPIO 3 pins (GPIO24 to GPIO31).
+ // Bit 4: when '1' enable GPIO 4
+ // trigger. This bit enables trigger
+ // for all GPIO 4 pins.(GPIO32 to
+ // GPIO39)
+
+#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_EMU_DEBUG_REG register.
+//
+//******************************************************************************
+#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \
+ 0xFFFFFFFF // 0 th bit used for stalling APPS
+ // DMA and 1st bit is used for
+ // stalling NWP DMA for debug
+ // purpose. Other bits are unused.
+
+#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_STATUS2 register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \
+ 0x00FFFFFF // SEMAPHORE STATUS 23:22
+ // :semaphore status of
+ // apps_nw_semaphore11 21:20
+ // :semaphore status of
+ // apps_nw_semaphore11 19:18
+ // :semaphore status of
+ // apps_nw_semaphore10 17:16
+ // :semaphore status of
+ // apps_nw_semaphore9 15:14
+ // :semaphore status of
+ // apps_nw_semaphore8 13:12
+ // :semaphore status of
+ // apps_nw_semaphore7 11:10
+ // :semaphore status of
+ // apps_nw_semaphore6 9:8 :semaphore
+ // status of apps_nw_semaphore5 7:6
+ // :semaphore status of
+ // apps_nw_semaphore4 5:4 :semaphore
+ // status of apps_nw_semaphore3 3:2
+ // :semaphore status of
+ // apps_nw_semaphore2 1:0 :semaphore
+ // status of apps_nw_semaphore1
+
+#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \
+ 0x0003FFFF // 1:0 : prvious owner of
+ // i2c_properties_reg[1:0] 3:2 :
+ // prvious owner of
+ // spi_properties_reg[1:0] 5:4 :
+ // prvious owner of
+ // gpio_properties_reg[1:0] 9:8 :
+ // prvious owner of
+ // gpio_properties_reg[3:2] 11:10 :
+ // prvious owner of
+ // gpio_properties_reg[5:4] 13:12 :
+ // prvious owner of
+ // gpio_properties_reg[7:6] 15:14 :
+ // prvious owner of
+ // gpio_properties_reg[9:8] 17:16 :
+ // prvious owner of
+ // flash_control_reg[1:0]
+
+#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \
+ 0x00FFFFFF // 1:0 : previous owner of
+ // apps_nw_semaphore1_reg[1:0] 3:2 :
+ // previous owner of
+ // apps_nw_semaphore2_reg[1:0] 5:4 :
+ // previous owner of
+ // apps_nw_semaphore3_reg[1:0] 7:6 :
+ // previous owner of
+ // apps_nw_semaphore4_reg[1:0] 9:8 :
+ // previous owner of
+ // apps_nw_semaphore5_reg[1:0] 11:10
+ // : previous owner of
+ // apps_nw_semaphore6_reg[1:0] 13:12
+ // : previous owner of
+ // apps_nw_semaphore7_reg[1:0] 15:14
+ // : previous owner of
+ // apps_nw_semaphore8_reg[1:0] 17:16
+ // : previous owner of
+ // apps_nw_semaphore9_reg[1:0] 19:18
+ // : previous owner of
+ // apps_nw_semaphore10_reg[1:0]
+ // 21:20 : previous owner of
+ // apps_nw_semaphore11_reg[1:0]
+ // 23:22 : previous owner of
+ // apps_nw_semaphore12_reg[1:0]
+
+#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0
+
+
+
+#endif // __HW_COMMON_REG_H__
diff --git a/cc3200/hal/inc/hw_des.h b/cc3200/hal/inc/hw_des.h
new file mode 100644
index 0000000000..c3aed65627
--- /dev/null
+++ b/cc3200/hal/inc/hw_des.h
@@ -0,0 +1,339 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_DES_H__
+#define __HW_DES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the DES_P register offsets.
+//
+//*****************************************************************************
+#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key
+#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key
+#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key
+#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key
+#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit
+ // key/192-bit key
+#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit
+ // key/192-bit key
+#define DES_O_IV_L 0x00000018 // Initialization vector LSW
+#define DES_O_IV_H 0x0000001C // Initialization vector MSW
+#define DES_O_CTRL 0x00000020
+#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data
+ // length in bytes for all modes.
+ // Once processing is started with
+ // this context this length
+ // decrements to zero. Data lengths
+ // up to (2^32 – 1) bytes are
+ // allowed. A write to this register
+ // triggers the engine to start
+ // using this context. For a Host
+ // read operation these registers
+ // return all-zeroes.
+#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write
+ // encrypted/decrypted data.
+#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write
+ // encrypted/decrypted data.
+#define DES_O_REVISION 0x00000030
+#define DES_O_SYSCONFIG 0x00000034
+#define DES_O_SYSSTATUS 0x00000038
+#define DES_O_IRQSTATUS 0x0000003C // This register indicates the
+ // interrupt status. If one of the
+ // interrupt bits is set the
+ // interrupt output will be asserted
+#define DES_O_IRQENABLE 0x00000040 // This register contains an enable
+ // bit for each unique interrupt
+ // generated by the module. It
+ // matches the layout of
+ // DES_IRQSTATUS register. An
+ // interrupt is enabled when the bit
+ // in this register is set to 1
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_L register.
+//
+//******************************************************************************
+#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3
+#define DES_KEY3_L_KEY3_L_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_H register.
+//
+//******************************************************************************
+#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3
+#define DES_KEY3_H_KEY3_H_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_L register.
+//
+//******************************************************************************
+#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2
+#define DES_KEY2_L_KEY2_L_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_H register.
+//
+//******************************************************************************
+#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2
+#define DES_KEY2_H_KEY2_H_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_L register.
+//
+//******************************************************************************
+#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1
+#define DES_KEY1_L_KEY1_L_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_H register.
+//
+//******************************************************************************
+#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1
+#define DES_KEY1_H_KEY1_H_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_L register.
+//
+//******************************************************************************
+#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC
+ // CFB modes
+#define DES_IV_L_IV_L_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_H register.
+//
+//******************************************************************************
+#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC
+ // CFB modes
+#define DES_IV_H_IV_H_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_CTRL register.
+//
+//******************************************************************************
+#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit
+ // indicates that the context data
+ // registers can be overwritten and
+ // the host is permitted to write
+ // the next context.
+#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0
+ // ecb mode 0x1 cbc mode 0x2 cfb
+ // mode 0x3 reserved
+#define DES_CTRL_MODE_S 4
+#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
+ // encryption/decryption. 0 des mode
+ // 1 tdes mode
+#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0
+ // decryption is selected 1
+ // Encryption is selected
+#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to
+ // encrypt/decrypt data
+#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data
+ // decrypted/encrypted ready
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_LENGTH register.
+//
+//******************************************************************************
+#define DES_LENGTH_LENGTH_M 0xFFFFFFFF
+#define DES_LENGTH_LENGTH_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_L register.
+//
+//******************************************************************************
+#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption
+#define DES_DATA_L_DATA_L_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_H register.
+//
+//******************************************************************************
+#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption
+#define DES_DATA_H_DATA_H_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_REVISION register.
+//
+//******************************************************************************
+#define DES_REVISION_SCHEME_M 0xC0000000
+#define DES_REVISION_SCHEME_S 30
+#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
+ // compatible module family. If
+ // there is no level of software
+ // compatibility a new Func number
+ // (and hence REVISION) should be
+ // assigned.
+#define DES_REVISION_FUNC_S 16
+#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
+ // design owner. RTL follows a
+ // numbering such as X.Y.R.Z which
+ // are explained in this table. R
+ // changes ONLY when: (1) PDS
+ // uploads occur which may have been
+ // due to spec changes (2) Bug fixes
+ // occur (3) Resets to '0' when X or
+ // Y changes. Design team has an
+ // internal 'Z' (customer invisible)
+ // number which increments on every
+ // drop that happens due to DV and
+ // RTL updates. Z resets to 0 when R
+ // increments.
+#define DES_REVISION_R_RTL_S 11
+#define DES_REVISION_X_MAJOR_M \
+ 0x00000700 // Major Revision (X) maintained by
+ // IP specification owner. X changes
+ // ONLY when: (1) There is a major
+ // feature addition. An example
+ // would be adding Master Mode to
+ // Utopia Level2. The Func field (or
+ // Class/Type in old PID format)
+ // will remain the same. X does NOT
+ // change due to: (1) Bug fixes (2)
+ // Change in feature parameters.
+
+#define DES_REVISION_X_MAJOR_S 8
+#define DES_REVISION_CUSTOM_M 0x000000C0
+#define DES_REVISION_CUSTOM_S 6
+#define DES_REVISION_Y_MINOR_M \
+ 0x0000003F // Minor Revision (Y) maintained by
+ // IP specification owner. Y changes
+ // ONLY when: (1) Features are
+ // scaled (up or down). Flexibility
+ // exists in that this feature
+ // scalability may either be
+ // represented in the Y change or a
+ // specific register in the IP that
+ // indicates which features are
+ // exactly available. (2) When
+ // feature creeps from Is-Not list
+ // to Is list. But this may not be
+ // the case once it sees silicon; in
+ // which case X will change. Y does
+ // NOT change due to: (1) Bug fixes
+ // (2) Typos or clarifications (3)
+ // major functional/feature
+ // change/addition/deletion. Instead
+ // these changes may be reflected
+ // via R S X as applicable. Spec
+ // owner maintains a
+ // customer-invisible number 'S'
+ // which changes due to: (1)
+ // Typos/clarifications (2) Bug
+ // documentation. Note that this bug
+ // is not due to a spec change but
+ // due to implementation.
+ // Nevertheless the spec tracks the
+ // IP bugs. An RTL release (say for
+ // silicon PG1.1) that occurs due to
+ // bug fix should document the
+ // corresponding spec number (X.Y.S)
+ // in its release notes.
+
+#define DES_REVISION_Y_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSCONFIG register.
+//
+//******************************************************************************
+#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
+ 0x00000080 // If set to ‘1’ the DMA context
+ // request is enabled. 0 Dma
+ // disabled 1 Dma enabled
+
+#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
+ 0x00000040 // If set to ‘1’ the DMA output
+ // request is enabled. 0 Dma
+ // disabled 1 Dma enabled
+
+#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
+ 0x00000020 // If set to ‘1’ the DMA input
+ // request is enabled. 0 Dma
+ // disabled 1 Dma enabled
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSSTATUS register.
+//
+//******************************************************************************
+#define DES_SYSSTATUS_RESETDONE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQSTATUS register.
+//
+//******************************************************************************
+#define DES_IRQSTATUS_DATA_OUT \
+ 0x00000004 // This bit indicates data output
+ // interrupt is active and triggers
+ // the interrupt output.
+
+#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
+ // interrupt is active and triggers
+ // the interrupt output.
+#define DES_IRQSTATUS_CONTEX_IN \
+ 0x00000001 // This bit indicates context
+ // interrupt is active and triggers
+ // the interrupt output.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQENABLE register.
+//
+//******************************************************************************
+#define DES_IRQENABLE_M_DATA_OUT \
+ 0x00000004 // If this bit is set to ‘1’ the
+ // secure data output interrupt is
+ // enabled.
+
+#define DES_IRQENABLE_M_DATA_IN \
+ 0x00000002 // If this bit is set to ‘1’ the
+ // secure data input interrupt is
+ // enabled.
+
+#define DES_IRQENABLE_M_CONTEX_IN \
+ 0x00000001 // If this bit is set to ‘1’ the
+ // secure context interrupt is
+ // enabled.
+
+
+
+
+#endif // __HW_DES_H__
diff --git a/cc3200/hal/inc/hw_dthe.h b/cc3200/hal/inc/hw_dthe.h
new file mode 100644
index 0000000000..1d302f426b
--- /dev/null
+++ b/cc3200/hal/inc/hw_dthe.h
@@ -0,0 +1,392 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+//*****************************************************************************
+
+#ifndef __HW_DTHE_H__
+#define __HW_DTHE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the DTHE register offsets.
+//
+//*****************************************************************************
+#define DTHE_O_SHA_IM 0x00000810
+#define DTHE_O_SHA_RIS 0x00000814
+#define DTHE_O_SHA_MIS 0x00000818
+#define DTHE_O_SHA_IC 0x0000081C
+#define DTHE_O_AES_IM 0x00000820
+#define DTHE_O_AES_RIS 0x00000824
+#define DTHE_O_AES_MIS 0x00000828
+#define DTHE_O_AES_IC 0x0000082C
+#define DTHE_O_DES_IM 0x00000830
+#define DTHE_O_DES_RIS 0x00000834
+#define DTHE_O_DES_MIS 0x00000838
+#define DTHE_O_DES_IC 0x0000083C
+#define DTHE_O_EIP_CGCFG 0x00000A00
+#define DTHE_O_EIP_CGREQ 0x00000A04
+#define DTHE_O_CRC_CTRL 0x00000C00
+#define DTHE_O_CRC_SEED 0x00000C10
+#define DTHE_O_CRC_DIN 0x00000C14
+#define DTHE_O_CRC_RSLT_PP 0x00000C18
+#define DTHE_O_RAND_KEY0 0x00000F00
+#define DTHE_O_RAND_KEY1 0x00000F04
+#define DTHE_O_RAND_KEY2 0x00000F08
+#define DTHE_O_RAND_KEY3 0x00000F0C
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_SHAMD5_IMST register.
+//
+//******************************************************************************
+#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is
+ // raised when DMA writes last word
+ // of input data to internal FIFO of
+ // the engine
+#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is
+ // raised when DMA complets the
+ // output context movement from
+ // internal register
+#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is
+ // raised when DMA complets Context
+ // write to internal register
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_SHAMD5_IRIS register.
+//
+//******************************************************************************
+#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done
+#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done
+#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_SHAMD5_IMIS register.
+//
+//******************************************************************************
+#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done
+#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done
+#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_SHAMD5_ICIS register.
+//
+//******************************************************************************
+#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement doneâ€
+ // flag
+#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done†flag
+#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done†flag
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_AES_IMST register.
+//
+//******************************************************************************
+#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is
+ // raised when DMA finishes writing
+ // last word of the process result
+#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is
+ // raised when DMA writes last word
+ // of input data to internal FIFO of
+ // the engine
+#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is
+ // raised when DMA complets the
+ // output context movement from
+ // internal register
+#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is
+ // raised when DMA complets Context
+ // write to internal register
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_AES_IRIS register.
+//
+//******************************************************************************
+#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done
+#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done
+#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done
+#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_AES_IMIS register.
+//
+//******************************************************************************
+#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done
+#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done
+#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done
+#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_AES_ICIS register.
+//
+//******************************************************************************
+#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement
+ // done†flag
+#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement doneâ€
+ // flag
+#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done†flag
+#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done†flag
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_DES_IMST register.
+//
+//******************************************************************************
+#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is
+ // raised when DMA finishes writing
+ // last word of the process result
+#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is
+ // raised when DMA writes last word
+ // of input data to internal FIFO of
+ // the engine
+#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is
+ // raised when DMA complets Context
+ // write to internal register
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_DES_IRIS register.
+//
+//******************************************************************************
+#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done
+#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done
+#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_DES_IMIS register.
+//
+//******************************************************************************
+#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done
+#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done
+#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_DES_ICIS register.
+//
+//******************************************************************************
+#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement
+ // done†flag
+#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement doneâ€
+ // flag
+#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done†flag
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_EIP_CGCFG register.
+//
+//******************************************************************************
+#define DTHE_EIP_CGCFG_EIP29_CFG \
+ 0x00000010 // Clock gating protocol setting
+ // for EIP29T. 0 – Follow direct
+ // protocol 1 – Follow idle_req/ack
+ // protocol.
+
+#define DTHE_EIP_CGCFG_EIP75_CFG \
+ 0x00000008 // Clock gating protocol setting
+ // for EIP75T. 0 – Follow direct
+ // protocol 1 – Follow idle_req/ack
+ // protocol.
+
+#define DTHE_EIP_CGCFG_EIP16_CFG \
+ 0x00000004 // Clock gating protocol setting
+ // for DES. 0 – Follow direct
+ // protocol 1 – Follow idle_req/ack
+ // protocol.
+
+#define DTHE_EIP_CGCFG_EIP36_CFG \
+ 0x00000002 // Clock gating protocol setting
+ // for AES. 0 – Follow direct
+ // protocol 1 – Follow idle_req/ack
+ // protocol.
+
+#define DTHE_EIP_CGCFG_EIP57_CFG \
+ 0x00000001 // Clock gating protocol setting
+ // for SHAMD5. 0 – Follow direct
+ // protocol 1 – Follow idle_req/ack
+ // protocol.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_EIP_CGREQ register.
+//
+//******************************************************************************
+#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5†write “1†to lower
+ // bits [4:0] will set the bit.
+ // Write “0†will be ignored When
+ // “0x2†write “1†to lower bit
+ // [4:0] will clear the bit. Write
+ // “0†will be ignored for other key
+ // value, regular read write
+ // operation
+#define DTHE_EIP_CGREQ_Key_S 28
+#define DTHE_EIP_CGREQ_EIP29_REQ \
+ 0x00000010 // 0 – request clock gating 1 –
+ // request to un-gate the clock.
+
+#define DTHE_EIP_CGREQ_EIP75_REQ \
+ 0x00000008 // 0 – request clock gating 1 –
+ // request to un-gate the clock.
+
+#define DTHE_EIP_CGREQ_EIP16_REQ \
+ 0x00000004 // 0 – request clock gating 1 –
+ // request to un-gate the clock.
+
+#define DTHE_EIP_CGREQ_EIP36_REQ \
+ 0x00000002 // 0 – request clock gating 1 –
+ // request to un-gate the clock.
+
+#define DTHE_EIP_CGREQ_EIP57_REQ \
+ 0x00000001 // 0 – request clock gating 1 –
+ // request to un-gate the clock.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register.
+//
+//******************************************************************************
+#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED
+ // register context as starting
+ // value 10 – all “zero†11 – all
+ // “one†This is self clearing. With
+ // first write to data register this
+ // value clears to zero and remain
+ // zero for rest of the operation
+ // unless written again
+#define DTHE_CRC_CTRL_INIT_S 13
+#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8
+ // bit
+#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result
+ // before storing to CRC_RSLT_PP0
+#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result
+ // byte before storing to
+ // CRC_RSLT_PP0. applicable for all
+ // bytes in word
+#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For
+ // all bytes in word
+#define DTHE_CRC_CTRL_ENDIAN_M \
+ 0x00000030 // Endian control [0] – swap byte
+ // in half-word [1] – swap half word
+
+#define DTHE_CRC_CTRL_ENDIAN_S 4
+#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 –
+ // polynomial 0x8005 0001 –
+ // polynomial 0x1021 0010 –
+ // polynomial 0x4C11DB7 0011 –
+ // polynomial 0x1EDC6F41 1000 – TCP
+ // checksum TYPE in DTHE_S_CRC_CTRL
+ // & DTHE_S_CRC_CTRL should be
+ // exclusive
+#define DTHE_CRC_CTRL_TYPE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DTHE_O_CRC_SEED register.
+//
+//******************************************************************************
+#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and
+ // checksum operation. Please see
+ // CTRL register for more detail.
+ // This resister also holds the
+ // latest result of CRC or checksum
+ // operation
+#define DTHE_CRC_SEED_SEED_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the DTHE_O_CRC_DIN register.
+//
+//******************************************************************************
+#define DTHE_CRC_DIN_DATA_IN_M \
+ 0xFFFFFFFF // Input data for CRC or checksum
+ // operation
+
+#define DTHE_CRC_DIN_DATA_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_CRC_RSLT_PP register.
+//
+//******************************************************************************
+#define DTHE_CRC_RSLT_PP_RSLT_PP_M \
+ 0xFFFFFFFF // Input data for CRC or checksum
+ // operation
+
+#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_RAND_KEY0 register.
+//
+//******************************************************************************
+#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key
+ // [31:0]
+#define DTHE_RAND_KEY0_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_RAND_KEY1 register.
+//
+//******************************************************************************
+#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key
+ // [63:32]
+#define DTHE_RAND_KEY1_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_RAND_KEY2 register.
+//
+//******************************************************************************
+#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key
+ // [95:34]
+#define DTHE_RAND_KEY2_KEY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// DTHE_O_RAND_KEY3 register.
+//
+//******************************************************************************
+#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key
+ // [127:96]
+#define DTHE_RAND_KEY3_KEY_S 0
+
+
+
+#endif // __HW_DTHE_H__
diff --git a/cc3200/hal/inc/hw_flash_ctrl.h b/cc3200/hal/inc/hw_flash_ctrl.h
new file mode 100644
index 0000000000..b57044aa13
--- /dev/null
+++ b/cc3200/hal/inc/hw_flash_ctrl.h
@@ -0,0 +1,1862 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_CTRL_H__
+#define __HW_FLASH_CTRL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH_CTRL register offsets.
+//
+//*****************************************************************************
+#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA)
+ // offset 0x000 During a write
+ // operation this register contains
+ // a 4-byte-aligned address and
+ // specifies where the data is
+ // written. During erase operations
+ // this register contains a 1
+ // KB-aligned CPU byte address and
+ // specifies which block is erased.
+ // Note that the alignment
+ // requirements must be met by
+ // software or the results of the
+ // operation are unpredictable.
+#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset
+ // 0x004 This register contains the
+ // data to be written during the
+ // programming cycle or read during
+ // the read cycle. Note that the
+ // contents of this register are
+ // undefined for a read access of an
+ // execute-only block. This register
+ // is not used during erase cycles.
+#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC)
+ // offset 0x008 When this register
+ // is written the Flash memory
+ // controller initiates the
+ // appropriate access cycle for the
+ // location specified by the Flash
+ // Memory Address (FMA) register .
+ // If the access is a write access
+ // the data contained in the Flash
+ // Memory Data (FMD) register is
+ // written to the specified address.
+ // This register must be the final
+ // register written and initiates
+ // the memory operation. The four
+ // control bits in the lower byte of
+ // this register are used to
+ // initiate memory operations.
+#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt
+ // Status (FCRIS) offset 0x00C This
+ // register indicates that the Flash
+ // memory controller has an
+ // interrupt condition. An interrupt
+ // is sent to the interrupt
+ // controller only if the
+ // corresponding FCIM register bit
+ // is set.
+#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask
+ // (FCIM) offset 0x010 This register
+ // controls whether the Flash memory
+ // controller generates interrupts
+ // to the controller.
+#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked
+ // Interrupt Status and Clear
+ // (FCMISC) offset 0x014 This
+ // register provides two functions.
+ // First it reports the cause of an
+ // interrupt by indicating which
+ // interrupt source or sources are
+ // signalling the interrupt. Second
+ // it serves as the method to clear
+ // the interrupt reporting.
+#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2)
+ // offset 0x020 When this register
+ // is written the Flash memory
+ // controller initiates the
+ // appropriate access cycle for the
+ // location specified by the Flash
+ // Memory Address (FMA) register .
+ // If the access is a write access
+ // the data contained in the Flash
+ // Write Buffer (FWB) registers is
+ // written. This register must be
+ // the final register written as it
+ // initiates the memory operation.
+#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid
+ // (FWBVAL) offset 0x030 This
+ // register provides a bitwise
+ // status of which FWBn registers
+ // have been written by the
+ // processor since the last write of
+ // the Flash memory write buffer.
+ // The entries with a 1 are written
+ // on the next write of the Flash
+ // memory write buffer. This
+ // register is cleared after the
+ // write operation by hardware. A
+ // protection violation on the write
+ // operation also clears this
+ // status. Software can program the
+ // same 32 words to various Flash
+ // memory locations by setting the
+ // FWB[n] bits after they are
+ // cleared by the write operation.
+ // The next write operation then
+ // uses the same data as the
+ // previous one. In addition if a
+ // FWBn register change should not
+ // be written to Flash memory
+ // software can clear the
+ // corresponding FWB[n] bit to
+ // preserve the existing data when
+ // the next write operation occurs.
+#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn)
+ // offset 0x100 - 0x17C These 32
+ // registers hold the contents of
+ // the data to be written into the
+ // Flash memory on a buffered Flash
+ // memory write operation. The
+ // offset selects one of the 32-bit
+ // registers. Only FWBn registers
+ // that have been updated since the
+ // preceding buffered Flash memory
+ // write operation are written into
+ // the Flash memory so it is not
+ // necessary to write the entire
+ // bank of registers in order to
+ // write 1 or 2 words. The FWBn
+ // registers are written into the
+ // Flash memory with the FWB0
+ // register corresponding to the
+ // address contained in FMA. FWB1 is
+ // written to the address FMA+0x4
+ // etc. Note that only data bits
+ // that are 0 result in the Flash
+ // memory being modified. A data bit
+ // that is 1 leaves the content of
+ // the Flash memory bit at its
+ // previous value.
+#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0
+ // This register indicates the size
+ // of the on-chip Flash memory.
+ // Important: This register should
+ // be used to determine the size of
+ // the Flash memory that is
+ // implemented on this
+ // microcontroller. However to
+ // support legacy software the DC0
+ // register is available. A read of
+ // the DC0 register correctly
+ // identifies legacy memory sizes.
+ // Software must use the FSIZE
+ // register for memory sizes that
+ // are not listed in the DC0
+ // register description.
+#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4
+ // This register indicates the size
+ // of the on-chip SRAM. Important:
+ // This register should be used to
+ // determine the size of the SRAM
+ // that is implemented on this
+ // microcontroller. However to
+ // support legacy software the DC0
+ // register is available. A read of
+ // the DC0 register correctly
+ // identifies legacy memory sizes.
+ // Software must use the SSIZE
+ // register for memory sizes that
+ // are not listed in the DC0
+ // register description.
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in
+ // Flash memory where operation is
+ // performed except for nonvolatile
+ // registers
+#define FLASH_CTRL_FMA_OFFSET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write
+ // operation.
+#define FLASH_CTRL_FMD_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This
+ // field contains a write key which
+ // is used to minimize the incidence
+ // of accidental Flash memory
+ // writes. The value 0xA442 must be
+ // written into this field for a
+ // Flash memory write to occur.
+ // Writes to the FMC register
+ // without this WRKEY value are
+ // ignored. A read of this field
+ // returns the value 0.
+#define FLASH_CTRL_FMC_WRKEY_S 16
+#define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit
+ // is used to commit writes to
+ // Flash-memory-resident registers
+ // and to monitor the progress of
+ // that process. Value Description 1
+ // Set this bit to commit (write)
+ // the register value to a
+ // Flash-memory-resident register.
+ // When read a 1 indicates that the
+ // previous commit access is not
+ // complete. 0 A write of 0 has no
+ // effect on the state of this bit.
+ // When read a 0 indicates that the
+ // previous commit access is
+ // complete.
+#define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit
+ // is used to mass erase the Flash
+ // main memory and to monitor the
+ // progress of that process. Value
+ // Description 1 Set this bit to
+ // erase the Flash main memory. When
+ // read a 1 indicates that the
+ // previous mass erase access is not
+ // complete. 0 A write of 0 has no
+ // effect on the state of this bit.
+ // When read a 0 indicates that the
+ // previous mass erase access is
+ // complete.
+#define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+ // This bit is used to erase a page
+ // of Flash memory and to monitor
+ // the progress of that process.
+ // Value Description 1 Set this bit
+ // to erase the Flash memory page
+ // specified by the contents of the
+ // FMA register. When read a 1
+ // indicates that the previous page
+ // erase access is not complete. 0 A
+ // write of 0 has no effect on the
+ // state of this bit. When read a 0
+ // indicates that the previous page
+ // erase access is complete.
+#define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+ // This bit is used to write a word
+ // into Flash memory and to monitor
+ // the progress of that process.
+ // Value Description 1 Set this bit
+ // to write the data stored in the
+ // FMD register into the Flash
+ // memory location specified by the
+ // contents of the FMA register.
+ // When read a 1 indicates that the
+ // write update access is not
+ // complete. 0 A write of 0 has no
+ // effect on the state of this bit.
+ // When read a 0 indicates that the
+ // previous write update access is
+ // complete.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FCRIS register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FCRIS_PROGRIS \
+ 0x00002000 // Program Verify Error Raw
+ // Interrupt Status Value
+ // Description 1 An interrupt is
+ // pending because the verify of a
+ // PROGRAM operation failed. 0 An
+ // interrupt has not occurred. This
+ // bit is cleared by writing a 1 to
+ // the PROGMISC bit in the FCMISC
+ // register.
+
+#define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt
+ // Status Value Description 1 An
+ // interrupt is pending because the
+ // verify of an ERASE operation
+ // failed. 0 An interrupt has not
+ // occurred. This bit is cleared by
+ // writing a 1 to the ERMISC bit in
+ // the FCMISC register.
+#define FLASH_CTRL_FCRIS_INVDRIS \
+ 0x00000400 // Invalid Data Raw Interrupt
+ // Status Value Description 1 An
+ // interrupt is pending because a
+ // bit that was previously
+ // programmed as a 0 is now being
+ // requested to be programmed as a
+ // 1. 0 An interrupt has not
+ // occurred. This bit is cleared by
+ // writing a 1 to the INVMISC bit in
+ // the FCMISC register.
+
+#define FLASH_CTRL_FCRIS_VOLTRIS \
+ 0x00000200 // Pump Voltage Raw Interrupt
+ // Status Value Description 1 An
+ // interrupt is pending because the
+ // regulated voltage of the pump
+ // went out of spec during the Flash
+ // operation and the operation was
+ // terminated. 0 An interrupt has
+ // not occurred. This bit is cleared
+ // by writing a 1 to the VOLTMISC
+ // bit in the FCMISC register.
+
+#define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This
+ // bit provides status EEPROM
+ // operation. Value Description 1 An
+ // EEPROM interrupt has occurred. 0
+ // An EEPROM interrupt has not
+ // occurred. This bit is cleared by
+ // writing a 1 to the EMISC bit in
+ // the FCMISC register.
+#define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+ // This bit provides status on
+ // programming cycles which are
+ // write or erase actions generated
+ // through the FMC or FMC2 register
+ // bits (see page 537 and page 549).
+ // Value Description 1 The
+ // programming or erase cycle has
+ // completed. 0 The programming or
+ // erase cycle has not completed.
+ // This status is sent to the
+ // interrupt controller when the
+ // PMASK bit in the FCIM register is
+ // set. This bit is cleared by
+ // writing a 1 to the PMISC bit in
+ // the FCMISC register.
+#define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+ // Value Description 1 A program or
+ // erase action was attempted on a
+ // block of Flash memory that
+ // contradicts the protection policy
+ // for that block as set in the
+ // FMPPEn registers. 0 No access has
+ // tried to improperly program or
+ // erase the Flash memory. This
+ // status is sent to the interrupt
+ // controller when the AMASK bit in
+ // the FCIM register is set. This
+ // bit is cleared by writing a 1 to
+ // the AMISC bit in the FCMISC
+ // register.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask
+ // Value Description 1 An interrupt
+ // is sent to the interrupt
+ // controller when the ILLARIS bit
+ // is set. 0 The ILLARIS interrupt
+ // is suppressed and not sent to the
+ // interrupt controller.
+#define FLASH_CTRL_FCIM_PROGMASK \
+ 0x00002000 // PROGVER Interrupt Mask Value
+ // Description 1 An interrupt is
+ // sent to the interrupt controller
+ // when the PROGRIS bit is set. 0
+ // The PROGRIS interrupt is
+ // suppressed and not sent to the
+ // interrupt controller.
+
+#define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value
+ // Description 1 An interrupt is
+ // sent to the interrupt controller
+ // when the PRERIS bit is set. 0 The
+ // PRERIS interrupt is suppressed
+ // and not sent to the interrupt
+ // controller.
+#define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value
+ // Description 1 An interrupt is
+ // sent to the interrupt controller
+ // when the ERRIS bit is set. 0 The
+ // ERRIS interrupt is suppressed and
+ // not sent to the interrupt
+ // controller.
+#define FLASH_CTRL_FCIM_INVDMASK \
+ 0x00000400 // Invalid Data Interrupt Mask
+ // Value Description 1 An interrupt
+ // is sent to the interrupt
+ // controller when the INVDRIS bit
+ // is set. 0 The INVDRIS interrupt
+ // is suppressed and not sent to the
+ // interrupt controller.
+
+#define FLASH_CTRL_FCIM_VOLTMASK \
+ 0x00000200 // VOLT Interrupt Mask Value
+ // Description 1 An interrupt is
+ // sent to the interrupt controller
+ // when the VOLTRIS bit is set. 0
+ // The VOLTRIS interrupt is
+ // suppressed and not sent to the
+ // interrupt controller.
+
+#define FLASH_CTRL_FCIM_LOCKMASK \
+ 0x00000100 // LOCK Interrupt Mask Value
+ // Description 1 An interrupt is
+ // sent to the interrupt controller
+ // when the LOCKRIS bit is set. 0
+ // The LOCKRIS interrupt is
+ // suppressed and not sent to the
+ // interrupt controller.
+
+#define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value
+ // Description 1 An interrupt is
+ // sent to the interrupt controller
+ // when the ERIS bit is set. 0 The
+ // ERIS interrupt is suppressed and
+ // not sent to the interrupt
+ // controller.
+#define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This
+ // bit controls the reporting of the
+ // programming raw interrupt status
+ // to the interrupt controller.
+ // Value Description 1 An interrupt
+ // is sent to the interrupt
+ // controller when the PRIS bit is
+ // set. 0 The PRIS interrupt is
+ // suppressed and not sent to the
+ // interrupt controller.
+#define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit
+ // controls the reporting of the
+ // access raw interrupt status to
+ // the interrupt controller. Value
+ // Description 1 An interrupt is
+ // sent to the interrupt controller
+ // when the ARIS bit is set. 0 The
+ // ARIS interrupt is suppressed and
+ // not sent to the interrupt
+ // controller.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FCMISC register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FCMISC_ILLMISC \
+ 0x00004000 // Illegal Address Masked Interrupt
+ // Status and Clear Value
+ // Description 1 When read a 1
+ // indicates that an unmasked
+ // interrupt was signaled. Writing a
+ // 1 to this bit clears ILLAMISC and
+ // also the ILLARIS bit in the FCRIS
+ // register (see page 540). 0 When
+ // read a 0 indicates that an
+ // interrupt has not occurred. A
+ // write of 0 has no effect on the
+ // state of this bit.
+
+#define FLASH_CTRL_FCMISC_PROGMISC \
+ 0x00002000 // PROGVER Masked Interrupt Status
+ // and Clear Value Description 1
+ // When read a 1 indicates that an
+ // unmasked interrupt was signaled.
+ // Writing a 1 to this bit clears
+ // PROGMISC and also the PROGRIS bit
+ // in the FCRIS register (see page
+ // 540). 0 When read a 0 indicates
+ // that an interrupt has not
+ // occurred. A write of 0 has no
+ // effect on the state of this bit.
+
+#define FLASH_CTRL_FCMISC_PREMISC \
+ 0x00001000 // PREVER Masked Interrupt Status
+ // and Clear Value Description 1
+ // When read a 1 indicates that an
+ // unmasked interrupt was signaled.
+ // Writing a 1 to this bit clears
+ // PREMISC and also the PRERIS bit
+ // in the FCRIS register . 0 When
+ // read a 0 indicates that an
+ // interrupt has not occurred. A
+ // write of 0 has no effect on the
+ // state of this bit.
+
+#define FLASH_CTRL_FCMISC_ERMISC \
+ 0x00000800 // ERVER Masked Interrupt Status
+ // and Clear Value Description 1
+ // When read a 1 indicates that an
+ // unmasked interrupt was signaled.
+ // Writing a 1 to this bit clears
+ // ERMISC and also the ERRIS bit in
+ // the FCRIS register 0 When read a
+ // 0 indicates that an interrupt has
+ // not occurred. A write of 0 has no
+ // effect on the state of this bit.
+
+#define FLASH_CTRL_FCMISC_INVDMISC \
+ 0x00000400 // Invalid Data Masked Interrupt
+ // Status and Clear Value
+ // Description 1 When read a 1
+ // indicates that an unmasked
+ // interrupt was signaled. Writing a
+ // 1 to this bit clears INVDMISC and
+ // also the INVDRIS bit in the FCRIS
+ // register (see page 540). 0 When
+ // read a 0 indicates that an
+ // interrupt has not occurred. A
+ // write of 0 has no effect on the
+ // state of this bit.
+
+#define FLASH_CTRL_FCMISC_VOLTMISC \
+ 0x00000200 // VOLT Masked Interrupt Status and
+ // Clear Value Description 1 When
+ // read a 1 indicates that an
+ // unmasked interrupt was signaled.
+ // Writing a 1 to this bit clears
+ // VOLTMISC and also the VOLTRIS bit
+ // in the FCRIS register (see page
+ // 540). 0 When read a 0 indicates
+ // that an interrupt has not
+ // occurred. A write of 0 has no
+ // effect on the state of this bit.
+
+#define FLASH_CTRL_FCMISC_LOCKMISC \
+ 0x00000100 // LOCK Masked Interrupt Status and
+ // Clear Value Description 1 When
+ // read a 1 indicates that an
+ // unmasked interrupt was signaled.
+ // Writing a 1 to this bit clears
+ // LOCKMISC and also the LOCKRIS bit
+ // in the FCRIS register (see page
+ // 540). 0 When read a 0 indicates
+ // that an interrupt has not
+ // occurred. A write of 0 has no
+ // effect on the state of this bit.
+
+#define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
+ // and Clear Value Description 1
+ // When read a 1 indicates that an
+ // unmasked interrupt was signaled.
+ // Writing a 1 to this bit clears
+ // EMISC and also the ERIS bit in
+ // the FCRIS register 0 When read a
+ // 0 indicates that an interrupt has
+ // not occurred. A write of 0 has no
+ // effect on the state of this bit.
+#define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear Value
+ // Description 1 When read a 1
+ // indicates that an unmasked
+ // interrupt was signaled because a
+ // programming cycle completed.
+ // Writing a 1 to this bit clears
+ // PMISC and also the PRIS bit in
+ // the FCRIS register 0 When read a
+ // 0 indicates that a programming
+ // cycle complete interrupt has not
+ // occurred. A write of 0 has no
+ // effect on the state of this bit.
+#define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear Value Description 1
+ // When read a 1 indicates that an
+ // unmasked interrupt was signaled
+ // because a program or erase action
+ // was attempted on a block of Flash
+ // memory that contradicts the
+ // protection policy for that block
+ // as set in the FMPPEn registers.
+ // Writing a 1 to this bit clears
+ // AMISC and also the ARIS bit in
+ // the FCRIS register 0 When read a
+ // 0 indicates that no improper
+ // accesses have occurred. A write
+ // of 0 has no effect on the state
+ // of this bit.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This
+ // field contains a write key which
+ // is used to minimize the incidence
+ // of accidental Flash memory
+ // writes. The value 0xA442 must be
+ // written into this field for a
+ // write to occur. Writes to the
+ // FMC2 register without this WRKEY
+ // value are ignored. A read of this
+ // field returns the value 0.
+#define FLASH_CTRL_FMC2_WRKEY_S 16
+#define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This
+ // bit is used to start a buffered
+ // write to Flash memory. Value
+ // Description 1 Set this bit to
+ // write the data stored in the FWBn
+ // registers to the location
+ // specified by the contents of the
+ // FMA register. When read a 1
+ // indicates that the previous
+ // buffered Flash memory write
+ // access is not complete. 0 A write
+ // of 0 has no effect on the state
+ // of this bit. When read a 0
+ // indicates that the previous
+ // buffered Flash memory write
+ // access is complete.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWBVAL register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWBVAL_FWBN_M \
+ 0xFFFFFFFF // Flash Memory Write Buffer Value
+ // Description 1 The corresponding
+ // FWBn register has been updated
+ // since the last buffer write
+ // operation and is ready to be
+ // written to Flash memory. 0 The
+ // corresponding FWBn register has
+ // no new data to be written. Bit 0
+ // corresponds to FWB0 offset 0x100
+ // and bit 31 corresponds to FWB31
+ // offset 0x13C.
+
+#define FLASH_CTRL_FWBVAL_FWBN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB1_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB2_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB3_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB4_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB5_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB6_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB7_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB8_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB9_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB10 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB10_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB11 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB11_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB12 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB12_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB13 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB13_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB14 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB14_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB15 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB15_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB16 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB16_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB17 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB17_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB18 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB18_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB19 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB19_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB20 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB20_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB21 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB21_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB22 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB22_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB23 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB23_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB24 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB24_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB25 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB25_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB26 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB26_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB27 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB27_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB28 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB28_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB29 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB29_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB30 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB30_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB31 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB31_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FWB32 register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the
+ // Flash memory.
+#define FLASH_CTRL_FWB32_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_FSIZE register.
+//
+//******************************************************************************
+#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of
+ // the on-chip Flash memory. Value
+ // Description 0x0003 8 KB of Flash
+ // 0x0007 16 KB of Flash 0x000F 32
+ // KB of Flash 0x001F 64 KB of Flash
+ // 0x002F 96 KB of Flash 0x003F 128
+ // KB of Flash 0x005F 192 KB of
+ // Flash 0x007F 256 KB of Flash
+#define FLASH_CTRL_FSIZE_SIZE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// FLASH_CTRL_O_SSIZE register.
+//
+//******************************************************************************
+#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \
+ 0x0000FFFF // SRAM Size Indicates the size of
+ // the on-chip SRAM. Value
+ // Description 0x0007 2 KB of SRAM
+ // 0x000F 4 KB of SRAM 0x0017 6 KB
+ // of SRAM 0x001F 8 KB of SRAM
+ // 0x002F 12 KB of SRAM 0x003F 16 KB
+ // of SRAM 0x004F 20 KB of SRAM
+ // 0x005F 24 KB of SRAM 0x007F 32 KB
+ // of SRAM
+
+#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0
+#define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1
+#define FLASH_ERASE_SIZE 0x00000400
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
+
+#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
+ // Enable 0
+#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
+ // Enable 1
+#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
+ // Enable 2
+#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
+ // Enable 3
+#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
+ // Enable 4
+#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
+ // Enable 5
+#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
+ // Enable 6
+#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
+ // Enable 7
+#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read
+ // Enable 8
+#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read
+ // Enable 9
+#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read
+ // Enable 10
+#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read
+ // Enable 11
+#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read
+ // Enable 12
+#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read
+ // Enable 13
+#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read
+ // Enable 14
+#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read
+ // Enable 15
+
+#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
+ // Enable 0
+#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
+ // Enable 1
+#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
+ // Enable 2
+#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
+ // Enable 3
+#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
+ // Enable 4
+#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
+ // Enable 5
+#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
+ // Enable 6
+#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
+ // Enable 7
+#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program
+ // Enable 8
+#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program
+ // Enable 9
+#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program
+ // Enable 10
+#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program
+ // Enable 11
+#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program
+ // Enable 12
+#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program
+ // Enable 13
+#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program
+ // Enable 14
+#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program
+ // Enable 15
+
+#define FLASH_USECRL 0x400FE140 // USec Reload
+#define FLASH_CTRL_ERASE_SIZE 0x00000400
+
+
+#endif // __HW_FLASH_CTRL_H__
diff --git a/cc3200/hal/inc/hw_gpio.h b/cc3200/hal/inc/hw_gpio.h
new file mode 100644
index 0000000000..2bd6e0f3ae
--- /dev/null
+++ b/cc3200/hal/inc/hw_gpio.h
@@ -0,0 +1,1349 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000
+ // 7000 0x4002 4000 GPIO Data
+ // (GPIODATA)@@ offset 0x000 The
+ // GPIODATA register is the data
+ // register. In software control
+ // mode@@ values written in the
+ // GPIODATA register are transferred
+ // onto the GPIO port pins if the
+ // respective pins have been
+ // configured as outputs through the
+ // GPIO Direction (GPIODIR) register
+ // (see page 653). In order to write
+ // to GPIODATA@@ the corresponding
+ // bits in the mask@@ resulting from
+ // the address bus bits [9:2]@@ must
+ // be set. Otherwise@@ the bit
+ // values remain unchanged by the
+ // write. Similarly@@ the values
+ // read from this register are
+ // determined for each bit by the
+ // mask bit derived from the address
+ // used to access the data
+ // register@@ bits [9:2]. Bits that
+ // are set in the address mask cause
+ // the corresponding bits in
+ // GPIODATA to be read@@ and bits
+ // that are clear in the address
+ // mask cause the corresponding bits
+ // in GPIODATA to be read as 0@@
+ // regardless of their value. A read
+ // from GPIODATA returns the last
+ // bit value written if the
+ // respective pins are configured as
+ // outputs@@ or it returns the value
+ // on the corresponding input pin
+ // when these are configured as
+ // inputs. All bits are cleared by a
+ // reset.
+#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000
+ // 7400 0x4002 4400 GPIO Direction
+ // (GPIODIR)@@ offset 0x400 The
+ // GPIODIR register is the data
+ // direction register. Setting a bit
+ // in the GPIODIR register
+ // configures the corresponding pin
+ // to be an output@@ while clearing
+ // a bit configures the
+ // corresponding pin to be an input.
+ // All bits are cleared by a reset@@
+ // meaning all GPIO pins are inputs
+ // by default.
+#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000
+ // 7404 0x4002 4404 GPIO Interrupt
+ // Sense (GPIOIS)@@ offset 0x404 The
+ // GPIOIS register is the interrupt
+ // sense register. Setting a bit in
+ // the GPIOIS register configures
+ // the corresponding pin to detect
+ // levels@@ while clearing a bit
+ // configures the corresponding pin
+ // to detect edges. All bits are
+ // cleared by a reset.
+#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000
+ // 7408 0x4002 4408 GPIO Interrupt
+ // Both Edges (GPIOIBE)@@ offset
+ // 0x408 The GPIOIBE register allows
+ // both edges to cause interrupts.
+ // When the corresponding bit in the
+ // GPIO Interrupt Sense (GPIOIS)
+ // register is set to detect edges@@
+ // setting a bit in the GPIOIBE
+ // register configures the
+ // corresponding pin to detect both
+ // rising and falling edges@@
+ // regardless of the corresponding
+ // bit in the GPIO Interrupt Event
+ // (GPIOIEV) register . Clearing a
+ // bit configures the pin to be
+ // controlled by the GPIOIEV
+ // register. All bits are cleared by
+ // a reset.
+#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000
+ // 740C 0x4002 440C GPIO Interrupt
+ // Event (GPIOIEV)@@ offset 0x40C
+ // The GPIOIEV register is the
+ // interrupt event register. Setting
+ // a bit in the GPIOIEV register
+ // configures the corresponding pin
+ // to detect rising edges or high
+ // levels@@ depending on the
+ // corresponding bit value in the
+ // GPIO Interrupt Sense (GPIOIS)
+ // register . Clearing a bit
+ // configures the pin to detect
+ // falling edges or low levels@@
+ // depending on the corresponding
+ // bit value in the GPIOIS register.
+ // All bits are cleared by a reset.
+#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000
+ // 7410 0x4002 4410 GPIO Interrupt
+ // Mask (GPIOIM)@@ offset 0x410 The
+ // GPIOIM register is the interrupt
+ // mask register. Setting a bit in
+ // the GPIOIM register allows
+ // interrupts that are generated by
+ // the corresponding pin to be sent
+ // to the interrupt controller on
+ // the combined interrupt signal.
+ // Clearing a bit prevents an
+ // interrupt on the corresponding
+ // pin from being sent to the
+ // interrupt controller. All bits
+ // are cleared by a reset.
+#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000
+ // 7414 0x4002 4414 GPIO Raw
+ // Interrupt Status (GPIORIS)@@
+ // offset 0x414 The GPIORIS register
+ // is the raw interrupt status
+ // register. A bit in this register
+ // is set when an interrupt
+ // condition occurs on the
+ // corresponding GPIO pin. If the
+ // corresponding bit in the GPIO
+ // Interrupt Mask (GPIOIM) register
+ // is set@@ the interrupt is sent to
+ // the interrupt controller. Bits
+ // read as zero indicate that
+ // corresponding input pins have not
+ // initiated an interrupt. A bit in
+ // this register can be cleared by
+ // writing a 1 to the corresponding
+ // bit in the GPIO Interrupt Clear
+ // (GPIOICR) register.
+#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000
+ // 7418 0x4002 4418 GPIO Masked
+ // Interrupt Status (GPIOMIS)@@
+ // offset 0x418 The GPIOMIS register
+ // is the masked interrupt status
+ // register. If a bit is set in this
+ // register@@ the corresponding
+ // interrupt has triggered an
+ // interrupt to the interrupt
+ // controller. If a bit is clear@@
+ // either no interrupt has been
+ // generated@@ or the interrupt is
+ // masked. If no port pin@@ other
+ // than the one that is being used
+ // as an ADC trigger@@ is being used
+ // to generate interrupts@@ the
+ // appropriate Interrupt Set Enable
+ // (ENn) register can disable the
+ // interrupts for the port@@ and the
+ // ADC interrupt can be used to read
+ // back the converted data.
+ // Otherwise@@ the port interrupt
+ // handler must ignore and clear
+ // interrupts on the port pin and
+ // wait for the ADC interrupt@@ or
+ // the ADC interrupt must be
+ // disabled in the EN0 register and
+ // the port interrupt handler must
+ // poll the ADC registers until the
+ // conversion is completed. If no
+ // port pin@@ other than the one
+ // that is being used as an ADC
+ // trigger@@ is being used to
+ // generate interrupts@@ the
+ // appropriate Interrupt Set Enable
+ // (ENn) register can disable the
+ // interrupts for the port@@ and the
+ // ADC interrupt can be used to read
+ // back the converted data.
+ // Otherwise@@ the port interrupt
+ // handler must ignore and clear
+ // interrupts on the port pin and
+ // wait for the ADC interrupt@@ or
+ // the ADC interrupt must be
+ // disabled in the EN0 register and
+ // the port interrupt handler must
+ // poll the ADC registers until the
+ // conversion is completed. Note
+ // that if the Port B GPIOADCCTL
+ // register is cleared@@ PB4 can
+ // still be used as an external
+ // trigger for the ADC. This is a
+ // legacy mode which allows code
+ // written for previous Stellaris
+ // devices to operate on this
+ // microcontroller. GPIOMIS is the
+ // state of the interrupt after
+ // masking.
+#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000
+ // 741C 0x4002 441C GPIO Interrupt
+ // Clear (GPIOICR)@@ offset 0x41C
+ // The GPIOICR register is the
+ // interrupt clear register. Writing
+ // a 1 to a bit in this register
+ // clears the corresponding
+ // interrupt bit in the GPIORIS and
+ // GPIOMIS registers. Writing a 0
+ // has no effect.
+#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000
+ // 7420 0x4002 4420 GPIO Alternate
+ // Function Select (GPIOAFSEL)@@
+ // offset 0x420 The GPIOAFSEL
+ // register is the mode control
+ // select register. If a bit is
+ // clear@@ the pin is used as a GPIO
+ // and is controlled by the GPIO
+ // registers. Setting a bit in this
+ // register configures the
+ // corresponding GPIO line to be
+ // controlled by an associated
+ // peripheral. Several possible
+ // peripheral functions are
+ // multiplexed on each GPIO. The
+ // GPIO Port Control (GPIOPCTL)
+ // register is used to select one of
+ // the possible functions.
+#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000
+ // 7500 0x4002 4500 GPIO 2-mA Drive
+ // Select (GPIODR2R)@@ offset 0x500
+ // The GPIODR2R register is the 2-mA
+ // drive control register. Each GPIO
+ // signal in the port can be
+ // individually configured without
+ // affecting the other pads. When
+ // setting the DRV2 bit for a GPIO
+ // signal@@ the corresponding DRV4
+ // bit in the GPIODR4R register and
+ // DRV8 bit in the GPIODR8R register
+ // are automatically cleared by
+ // hardware. By default@@ all GPIO
+ // pins have 2-mA drive.
+#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000
+ // 7504 0x4002 4504 GPIO 4-mA Drive
+ // Select (GPIODR4R)@@ offset 0x504
+ // The GPIODR4R register is the 4-mA
+ // drive control register. Each GPIO
+ // signal in the port can be
+ // individually configured without
+ // affecting the other pads. When
+ // setting the DRV4 bit for a GPIO
+ // signal@@ the corresponding DRV2
+ // bit in the GPIODR2R register and
+ // DRV8 bit in the GPIODR8R register
+ // are automatically cleared by
+ // hardware.
+#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000
+ // 7508 0x4002 4508 GPIO 8-mA Drive
+ // Select (GPIODR8R)@@ offset 0x508
+ // The GPIODR8R register is the 8-mA
+ // drive control register. Each GPIO
+ // signal in the port can be
+ // individually configured without
+ // affecting the other pads. When
+ // setting the DRV8 bit for a GPIO
+ // signal@@ the corresponding DRV2
+ // bit in the GPIODR2R register and
+ // DRV4 bit in the GPIODR4R register
+ // are automatically cleared by
+ // hardware. The 8-mA setting is
+ // also used for high-current
+ // operation. Note: There is no
+ // configuration difference between
+ // 8-mA and high-current operation.
+ // The additional current capacity
+ // results from a shift in the
+ // VOH/VOL levels.
+#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000
+ // 750C 0x4002 450C GPIO Open Drain
+ // Select (GPIOODR)@@ offset 0x50C
+ // The GPIOODR register is the open
+ // drain control register. Setting a
+ // bit in this register enables the
+ // open-drain configuration of the
+ // corresponding GPIO pad. When
+ // open-drain mode is enabled@@ the
+ // corresponding bit should also be
+ // set in the GPIO Digital Input
+ // Enable (GPIODEN) register .
+ // Corresponding bits in the drive
+ // strength and slew rate control
+ // registers (GPIODR2R@@ GPIODR4R@@
+ // GPIODR8R@@ and GPIOSLR) can be
+ // set to achieve the desired rise
+ // and fall times. The GPIO acts as
+ // an open-drain input if the
+ // corresponding bit in the GPIODIR
+ // register is cleared. If open
+ // drain is selected while the GPIO
+ // is configured as an input@@ the
+ // GPIO will remain an input and the
+ // open-drain selection has no
+ // effect until the GPIO is changed
+ // to an output. When using the I2C
+ // module@@ in addition to
+ // configuring the pin to open
+ // drain@@ the GPIO Alternate
+ // Function Select (GPIOAFSEL)
+ // register bits for the I2C clock
+ // and data pins should be set
+#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000
+ // 7510 0x4002 4510 GPIO Pull-Up
+ // Select (GPIOPUR)@@ offset 0x510
+ // The GPIOPUR register is the
+ // pull-up control register. When a
+ // bit is set@@ a weak pull-up
+ // resistor on the corresponding
+ // GPIO signal is enabled. Setting a
+ // bit in GPIOPUR automatically
+ // clears the corresponding bit in
+ // the GPIO Pull-Down Select
+ // (GPIOPDR) register . Write access
+ // to this register is protected
+ // with the GPIOCR register. Bits in
+ // GPIOCR that are cleared prevent
+ // writes to the equivalent bit in
+ // this register.
+#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000
+ // 7514 0x4002 4514 GPIO Pull-Down
+ // Select (GPIOPDR)@@ offset 0x514
+ // The GPIOPDR register is the
+ // pull-down control register. When
+ // a bit is set@@ a weak pull-down
+ // resistor on the corresponding
+ // GPIO signal is enabled. Setting a
+ // bit in GPIOPDR automatically
+ // clears the corresponding bit in
+ // the GPIO Pull-Up Select (GPIOPUR)
+ // register
+#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000
+ // 7518 0x4002 4518 The GPIOSLR
+ // register is the slew rate control
+ // register. Slew rate control is
+ // only available when using the
+ // 8-mA drive strength option via
+ // the GPIO 8-mA Drive Select
+ // (GPIODR8R) register
+#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000
+ // 751C 0x4002 451C GPIO Digital
+ // Enable (GPIODEN)@@ offset 0x51C
+ // Note: Pins configured as digital
+ // inputs are Schmitt-triggered. The
+ // GPIODEN register is the digital
+ // enable register. By default@@ all
+ // GPIO signals except those listed
+ // below are configured out of reset
+ // to be undriven (tristate). Their
+ // digital function is disabled;
+ // they do not drive a logic value
+ // on the pin and they do not allow
+ // the pin voltage into the GPIO
+ // receiver. To use the pin as a
+ // digital input or output (either
+ // GPIO or alternate function)@@ the
+ // corresponding GPIODEN bit must be
+ // set.
+#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000
+ // 7520 0x4002 4520 GPIO Lock
+ // (GPIOLOCK)@@ offset 0x520 The
+ // GPIOLOCK register enables write
+ // access to the GPIOCR register .
+ // Writing 0x4C4F.434B to the
+ // GPIOLOCK register unlocks the
+ // GPIOCR register. Writing any
+ // other value to the GPIOLOCK
+ // register re-enables the locked
+ // state. Reading the GPIOLOCK
+ // register returns the lock status
+ // rather than the 32-bit value that
+ // was previously written.
+ // Therefore@@ when write accesses
+ // are disabled@@ or locked@@
+ // reading the GPIOLOCK register
+ // returns 0x0000.0001. When write
+ // accesses are enabled@@ or
+ // unlocked@@ reading the GPIOLOCK
+ // register returns 0x0000.0000.
+#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000
+ // 7524 0x4002 4524 GPIO Commit
+ // (GPIOCR)@@ offset 0x524 The
+ // GPIOCR register is the commit
+ // register. The value of the GPIOCR
+ // register determines which bits of
+ // the GPIOAFSEL@@ GPIOPUR@@
+ // GPIOPDR@@ and GPIODEN registers
+ // are committed when a write to
+ // these registers is performed. If
+ // a bit in the GPIOCR register is
+ // cleared@@ the data being written
+ // to the corresponding bit in the
+ // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
+ // or GPIODEN registers cannot be
+ // committed and retains its
+ // previous value. If a bit in the
+ // GPIOCR register is set@@ the data
+ // being written to the
+ // corresponding bit of the
+ // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
+ // or GPIODEN registers is committed
+ // to the register and reflects the
+ // new value. The contents of the
+ // GPIOCR register can only be
+ // modified if the status in the
+ // GPIOLOCK register is unlocked.
+ // Writes to the GPIOCR register are
+ // ignored if the status in the
+ // GPIOLOCK register is locked.
+#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000
+ // 7528 0x4002 4528 The GPIOAMSEL
+ // register controls isolation
+ // circuits to the analog side of a
+ // unified I/O pad. Because the
+ // GPIOs may be driven by a 5-V
+ // source and affect analog
+ // operation@@ analog circuitry
+ // requires isolation from the pins
+ // when they are not used in their
+ // analog function. Each bit of this
+ // register controls the isolation
+ // circuitry for the corresponding
+ // GPIO signal.
+#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) 0x4000 552C
+ // 0x4000 652C 0x4000 752C 0x4002
+ // 452C GPIO Port Control
+ // (GPIOPCTL)@@ offset 0x52C The
+ // GPIOPCTL register is used in
+ // conjunction with the GPIOAFSEL
+ // register and selects the specific
+ // peripheral signal for each GPIO
+ // pin when using the alternate
+ // function mode. Most bits in the
+ // GPIOAFSEL register are cleared on
+ // reset@@ therefore most GPIO pins
+ // are configured as GPIOs by
+ // default. When a bit is set in the
+ // GPIOAFSEL register@@ the
+ // corresponding GPIO signal is
+ // controlled by an associated
+ // peripheral. The GPIOPCTL register
+ // selects one out of a set of
+ // peripheral functions for each
+ // GPIO@@ providing additional
+ // flexibility in signal definition.
+#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in
+ // cc3xx. ADC trigger via GPIO is
+ // not supported. 0x4000 5530 0x4000
+ // 6530 0x4000 7530 0x4002 4530 GPIO
+ // ADC Control (GPIOADCCTL)@@ offset
+ // 0x530 This register is used to
+ // configure a GPIO pin as a source
+ // for the ADC trigger. Note that if
+ // the Port B GPIOADCCTL register is
+ // cleared@@ PB4 can still be used
+ // as an external trigger for the
+ // ADC. This is a legacy mode which
+ // allows code written for previous
+ // Stellaris devices to operate on
+ // this microcontroller.
+#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000
+ // 7534 0x4002 4534 GPIO DMA Control
+ // (GPIODMACTL)@@ offset 0x534 This
+ // register is used to configure a
+ // GPIO pin as a source for the ?DMA
+ // trigger.
+#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000
+ // 7538 0x4002 4538 GPIO Select
+ // Interrupt (GPIOSI)@@ offset 0x538
+ // This register is used to enable
+ // individual interrupts for each
+ // pin. Note: This register is only
+ // available on Port P and Port Q.
+#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000
+ // 7FD0 0x4002 4FD0 GPIO Peripheral
+ // Identification 4
+ // (GPIOPeriphID4)@@ offset 0xFD0
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000
+ // 7FD4 0x4002 4FD4 GPIO Peripheral
+ // Identification 5
+ // (GPIOPeriphID5)@@ offset 0xFD4
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000
+ // 7FD8 0x4002 4FD8 GPIO Peripheral
+ // Identification 6
+ // (GPIOPeriphID6)@@ offset 0xFD8
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000
+ // 7FDC 0x4002 4FDC GPIO Peripheral
+ // Identification 7
+ // (GPIOPeriphID7)@@ offset 0xFDC
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000
+ // 7FE0 0x4002 4FE0 GPIO Peripheral
+ // Identification 0
+ // (GPIOPeriphID0)@@ offset 0xFE0
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000
+ // 7FE4 0x4002 4FE4 GPIO Peripheral
+ // Identification 1
+ // (GPIOPeriphID1)@@ offset 0xFE4
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000
+ // 7FE8 0x4002 4FE8 GPIO Peripheral
+ // Identification 2
+ // (GPIOPeriphID2)@@ offset 0xFE8
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000
+ // 7FEC 0x4002 4FEC GPIO Peripheral
+ // Identification 3
+ // (GPIOPeriphID3)@@ offset 0xFEC
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000
+ // 7FF0 0x4002 4FF0 GPIO PrimeCell
+ // Identification 0 (GPIOPCellID0)@@
+ // offset 0xFF0 The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.
+#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000
+ // 7FF4 0x4002 4FF4 GPIO PrimeCell
+ // Identification 1 (GPIOPCellID1)@@
+ // offset 0xFF4 The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.
+#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000
+ // 7FF8 0x4002 4FF8 GPIO PrimeCell
+ // Identification 2 (GPIOPCellID2)@@
+ // offset 0xFF8 The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.
+#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000
+ // 7FFC 0x4002 4FFC GPIO PrimeCell
+ // Identification 3 (GPIOPCellID3)@@
+ // offset 0xFFC The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.0xb1
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is
+ // virtually mapped to 256 locations
+ // in the address space. To
+ // facilitate the reading and
+ // writing of data to these
+ // registers by independent
+ // drivers@@ the data read from and
+ // written to the registers are
+ // masked by the eight address lines
+ // [9:2]. Reads from this register
+ // return its current state. Writes
+ // to this register only affect bits
+ // that are not masked by ADDR[9:2]
+ // and are configured as outputs.
+#define GPIO_GPIO_DATA_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value
+ // Description 0 Corresponding pin
+ // is an input. 1 Corresponding pins
+ // is an output.
+#define GPIO_GPIO_DIR_DIR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IS register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value
+ // Description 0 The edge on the
+ // corresponding pin is detected
+ // (edge-sensitive). 1 The level on
+ // the corresponding pin is detected
+ // (level-sensitive).
+#define GPIO_GPIO_IS_IS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value
+ // Description 0 Interrupt
+ // generation is controlled by the
+ // GPIO Interrupt Event (GPIOIEV)
+ // register. 1 Both edges on the
+ // corresponding pin trigger an
+ // interrupt.
+#define GPIO_GPIO_IBE_IBE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value
+ // Description 1 A falling edge or a
+ // Low level on the corresponding
+ // pin triggers an interrupt. 0 A
+ // rising edge or a High level on
+ // the corresponding pin triggers an
+ // interrupt.
+#define GPIO_GPIO_IEV_IEV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IM register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value
+ // Description 0 The interrupt from
+ // the corresponding pin is masked.
+ // 1 The interrupt from the
+ // corresponding pin is sent to the
+ // interrupt controller.
+#define GPIO_GPIO_IM_IME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register.
+//
+//******************************************************************************
+#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value
+ // Description 1 An interrupt
+ // condition has occurred on the
+ // corresponding pin. 0 interrupt
+ // condition has not occurred on the
+ // corresponding pin. A bit is
+ // cleared by writing a 1 to the
+ // corresponding bit in the GPIOICR
+ // register.
+#define GPIO_GPIO_RIS_RIS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register.
+//
+//******************************************************************************
+#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status
+ // Value Description 1 An interrupt
+ // condition on the corresponding
+ // pin has triggered an interrupt to
+ // the interrupt controller. 0 An
+ // interrupt condition on the
+ // corresponding pin is masked or
+ // has not occurred. A bit is
+ // cleared by writing a 1 to the
+ // corresponding bit in the GPIOICR
+ // register.
+#define GPIO_GPIO_MIS_MIS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value
+ // Description 1 The corresponding
+ // interrupt is cleared. 0 The
+ // corresponding interrupt is
+ // unaffected.
+#define GPIO_GPIO_ICR_IC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // 2-mA Drive Enable Value
+ // Description 1 The corresponding
+ // GPIO pin has 2-mA drive. The
+ // drive for the corresponding GPIO
+ // pin is controlled by the GPIODR4R
+ // or GPIODR8R register. 0 Setting a
+ // bit in either the GPIODR4
+ // register or the GPIODR8 register
+ // clears the corresponding 2-mA
+ // enable bit. The change is
+ // effective on the second clock
+ // cycle after the write if
+ // accessing GPIO via the APB memory
+ // aperture. If using AHB access@@
+ // the change is effective on the
+ // next clock cycle.
+#define GPIO_GPIO_DR2R_DRV2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // 4-mA Drive Enable Value
+ // Description 1 The corresponding
+ // GPIO pin has 4-mA drive. The
+ // drive for the corresponding GPIO
+ // pin is controlled by the GPIODR2R
+ // or GPIODR8R register. 0 Setting a
+ // bit in either the GPIODR2
+ // register or the GPIODR8 register
+ // clears the corresponding 4-mA
+ // enable bit. The change is
+ // effective on the second clock
+ // cycle after the write if
+ // accessing GPIO via the APB memory
+ // aperture. If using AHB access@@
+ // the change is effective on the
+ // next clock cycle.
+#define GPIO_GPIO_DR4R_DRV4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // 8-mA Drive Enable Value
+ // Description 1 The corresponding
+ // GPIO pin has 8-mA drive. The
+ // drive for the corresponding GPIO
+ // pin is controlled by the GPIODR2R
+ // or GPIODR4R register. 0 Setting a
+ // bit in either the GPIODR2
+ // register or the GPIODR4 register
+ // clears the corresponding 8-mA
+ // enable bit. The change is
+ // effective on the second clock
+ // cycle after the write if
+ // accessing GPIO via the APB memory
+ // aperture. If using AHB access@@
+ // the change is effective on the
+ // next clock cycle.
+#define GPIO_GPIO_DR8R_DRV8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // Open Drain Enable Value
+ // Description 1 The corresponding
+ // pin is configured as open drain.
+ // 0 The corresponding pin is not
+ // configured as open drain.
+#define GPIO_GPIO_ODR_ODE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Pad Weak
+ // Pull-Up Enable Value Description
+ // 1 The corresponding pin has a
+ // weak pull-up resistor. 0 The
+ // corresponding pin is not
+ // affected. Setting a bit in the
+ // GPIOPDR register clears the
+ // corresponding bit in the GPIOPUR
+ // register. The change is effective
+ // on the second clock cycle after
+ // the write if accessing GPIO via
+ // the APB memory aperture. If using
+ // AHB access@@ the change is
+ // effective on the next clock
+ // cycle.
+#define GPIO_GPIO_PUR_PUE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Pad Weak
+ // Pull-Down Enable Value
+ // Description 1 The corresponding
+ // pin has a weak pull-down
+ // resistor. 0 The corresponding pin
+ // is not affected. Setting a bit in
+ // the GPIOPUR register clears the
+ // corresponding bit in the GPIOPDR
+ // register. The change is effective
+ // on the second clock cycle after
+ // the write if accessing GPIO via
+ // the APB memory aperture. If using
+ // AHB access@@ the change is
+ // effective on the next clock
+ // cycle.
+#define GPIO_GPIO_PDR_PDE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Slew Rate
+ // Limit Enable (8-mA drive only)
+ // Value Description 1 Slew rate
+ // control is enabled for the
+ // corresponding pin. 0 Slew rate
+ // control is disabled for the
+ // corresponding pin.
+#define GPIO_GPIO_SLR_SRL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Digital Enable
+ // Value Description 0 The digital
+ // functions for the corresponding
+ // pin are disabled. 1 The digital
+ // functions for the corresponding
+ // pin are enabled.
+#define GPIO_GPIO_DEN_DEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register.
+//
+//******************************************************************************
+#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in
+ // cc3xx. GPIO Lock A write of the
+ // value 0x4C4F.434B unlocks the
+ // GPIO Commit (GPIOCR) register for
+ // write access.A write of any other
+ // value or a write to the GPIOCR
+ // register reapplies the lock@@
+ // preventing any register updates.
+ // A read of this register returns
+ // the following values: Value
+ // Description 0x1 The GPIOCR
+ // register is locked and may not be
+ // modified. 0x0 The GPIOCR register
+ // is unlocked and may be modified.
+#define GPIO_GPIO_LOCK_LOCK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_CR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) GPIO Commit
+ // Value Description The
+ // corresponding GPIOAFSEL@@
+ // GPIOPUR@@ GPIOPDR@@ or GPIODEN
+ // bits can be written. 1 The
+ // corresponding GPIOAFSEL@@
+ // GPIOPUR@@ GPIOPDR@@ or GPIODEN
+ // bits cannot be written. 0 Note:
+ // The default register type for the
+ // GPIOCR register is RO for all
+ // GPIO pins with the exception of
+ // the NMI pin and the four JTAG/SWD
+ // pins (PD7@@ PF0@@ and PC[3:0]).
+ // These six pins are the only GPIOs
+ // that are protected by the GPIOCR
+ // register. Because of this@@ the
+ // register type for GPIO Port D7@@
+ // GPIO Port F0@@ and GPIO Port
+ // C[3:0] is R/W. The default reset
+ // value for the GPIOCR register is
+ // 0x0000.00FF for all GPIO pins@@
+ // with the exception of the NMI pin
+ // and the four JTAG/SWD pins (PD7@@
+ // PF0@@ and PC[3:0]). To ensure
+ // that the JTAG port is not
+ // accidentally programmed as GPIO
+ // pins@@ the PC[3:0] pins default
+ // to non-committable. Similarly@@
+ // to ensure that the NMI pin is not
+ // accidentally programmed as a GPIO
+ // pin@@ the PD7 and PF0 pins
+ // default to non-committable.
+ // Because of this@@ the default
+ // reset value of GPIOCR for GPIO
+ // Port C is 0x0000.00F0@@ for GPIO
+ // Port D is 0x0000.007F@@ and for
+ // GPIO Port F is 0x0000.00FE.
+#define GPIO_GPIO_CR_CR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \
+ 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) GPIO Analog
+ // Mode Select Value Description 1
+ // The analog function of the pin is
+ // enabled@@ the isolation is
+ // disabled@@ and the pin is capable
+ // of analog functions. 0 The analog
+ // function of the pin is disabled@@
+ // the isolation is enabled@@ and
+ // the pin is capable of digital
+ // functions as specified by the
+ // other GPIO configuration
+ // registers. Note: This register
+ // and bits are only valid for GPIO
+ // signals that share analog
+ // function through a unified I/O
+ // pad. The reset state of this
+ // register is 0 for all signals.
+
+#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 7 This field controls the
+ // configuration for GPIO pin 7.
+#define GPIO_GPIO_PCTL_PMC7_S 28
+#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 6 This field controls the
+ // configuration for GPIO pin 6.
+#define GPIO_GPIO_PCTL_PMC6_S 24
+#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 5 This field controls the
+ // configuration for GPIO pin 5.
+#define GPIO_GPIO_PCTL_PMC5_S 20
+#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 4 This field controls the
+ // configuration for GPIO pin 4.
+#define GPIO_GPIO_PCTL_PMC4_S 16
+#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 43 This field controls
+ // the configuration for GPIO pin 3.
+#define GPIO_GPIO_PCTL_PMC3_S 12
+#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 1 This field controls the
+ // configuration for GPIO pin 1.
+#define GPIO_GPIO_PCTL_PMC1_S 8
+#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 2 This field controls the
+ // configuration for GPIO pin 2.
+#define GPIO_GPIO_PCTL_PMC2_S 4
+#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 0 This field controls the
+ // configuration for GPIO pin 0.
+#define GPIO_GPIO_PCTL_PMC0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_ADCCTL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_ADCCTL_ADCEN_M \
+ 0x000000FF // This register is not used in
+ // cc3xx. ADC trigger via GPIO is
+ // not supported. ADC Trigger Enable
+ // Value Description 1 The
+ // corresponding pin is used to
+ // trigger the ADC. 0 The
+ // corresponding pin is not used to
+ // trigger the ADC.
+
+#define GPIO_GPIO_ADCCTL_ADCEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_DMACTL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DMACTL_DMAEN_M \
+ 0x000000FF // This register is not used in the
+ // cc3xx. Alternate register to
+ // support this feature is coded in
+ // the APPS_NWP_CMN space. refer
+ // register as offset 0x400F70D8
+ // ?DMA Trigger Enable Value
+ // Description 1 The corresponding
+ // pin is used to trigger the ?DMA.
+ // 0 The corresponding pin is not
+ // used to trigger the ?DMA.
+
+#define GPIO_GPIO_DMACTL_DMAEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_SI register.
+//
+//******************************************************************************
+#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value
+ // Description 1 Each pin has its
+ // own interrupt vector. 0 All port
+ // pin interrupts are OR'ed together
+ // to produce a summary interrupt.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID4 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID4_PID4_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [7:0]
+
+#define GPIO_GPIO_PERIPHID4_PID4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID5 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID5_PID5_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [15:8]
+
+#define GPIO_GPIO_PERIPHID5_PID5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID6 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID6_PID6_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [23:16]
+
+#define GPIO_GPIO_PERIPHID6_PID6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID7 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID7_PID7_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [31:24]
+
+#define GPIO_GPIO_PERIPHID7_PID7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID0 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID0_PID0_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [7:0] Can be used by
+ // software to identify the presence
+ // of this peripheral.
+
+#define GPIO_GPIO_PERIPHID0_PID0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID1 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID1_PID1_M \
+ 0x000000FF // GPIO Peripheral ID Register
+ // [15:8] Can be used by software to
+ // identify the presence of this
+ // peripheral.
+
+#define GPIO_GPIO_PERIPHID1_PID1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID2 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID2_PID2_M \
+ 0x000000FF // This register is not used in
+ // CC3XX.v GPIO Peripheral ID
+ // Register [23:16] Can be used by
+ // software to identify the presence
+ // of this peripheral.
+
+#define GPIO_GPIO_PERIPHID2_PID2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID3 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID3_PID3_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [31:24] Can be used by
+ // software to identify the presence
+ // of this peripheral.
+
+#define GPIO_GPIO_PERIPHID3_PID3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID0 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID0_CID0_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [7:0] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID0_CID0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID1 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID1_CID1_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [15:8] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID1_CID1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID2 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID2_CID2_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [23:16] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID2_CID2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID3 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID3_CID3_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [31:24] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID3_CID3_S 0
+
+
+
+#endif // __HW_GPIO_H__
diff --git a/cc3200/hal/inc/hw_gprcm.h b/cc3200/hal/inc/hw_gprcm.h
new file mode 100644
index 0000000000..43628f4aba
--- /dev/null
+++ b/cc3200/hal/inc/hw_gprcm.h
@@ -0,0 +1,3322 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPRCM_H__
+#define __HW_GPRCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPRCM register offsets.
+//
+//*****************************************************************************
+#define GPRCM_O_APPS_SOFT_RESET 0x00000000
+#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \
+ 0x00000004
+
+#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \
+ 0x00000008
+
+#define GPRCM_O_APPS_RESET_CAUSE \
+ 0x0000000C
+
+#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \
+ 0x00000010
+
+#define GPRCM_O_APPS_SRAM_DSLP_CFG \
+ 0x00000018
+
+#define GPRCM_O_APPS_SRAM_LPDS_CFG \
+ 0x0000001C
+
+#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \
+ 0x00000020
+
+#define GPRCM_O_TOP_DIE_ENABLE 0x00000100
+#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \
+ 0x00000104
+
+#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \
+ 0x00000108
+
+#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C
+#define GPRCM_O_APPS_GPIO_WAKE_CONF \
+ 0x00000110
+
+#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \
+ 0x00000114
+
+#define GPRCM_O_MEM_HCLK_DIV_CFG \
+ 0x00000118
+
+#define GPRCM_O_MEM_SYSCLK_DIV_CFG \
+ 0x0000011C
+
+#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \
+ 0x00000120
+
+#define GPRCM_O_NWP_SOFT_RESET 0x00000400
+#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \
+ 0x00000404
+
+#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \
+ 0x00000408
+
+#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C
+#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \
+ 0x00000410
+
+#define GPRCM_O_NWP_SRAM_DSLP_CFG \
+ 0x00000418
+
+#define GPRCM_O_NWP_SRAM_LPDS_CFG \
+ 0x0000041C
+
+#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \
+ 0x00000420
+
+#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \
+ 0x00000424
+
+#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \
+ 0x00000428
+
+#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \
+ 0x0000042C
+
+#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \
+ 0x00000430
+
+#define GPRCM_O_NWP_GPIO_WAKE_CONF \
+ 0x00000434
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \
+ 0x00000438
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG5 \
+ 0x00000448
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG6 \
+ 0x0000044C
+
+#define GPRCM_O_REF_FSM_CFG0 0x00000800
+#define GPRCM_O_REF_FSM_CFG1 0x00000804
+#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \
+ 0x00000808
+
+#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \
+ 0x0000080C
+
+#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \
+ 0x00000810
+
+#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \
+ 0x00000814
+
+#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \
+ 0x00000818
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \
+ 0x0000081C
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \
+ 0x00000820
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \
+ 0x00000824
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \
+ 0x00000828
+
+#define GPRCM_O_SPARE_RW0 0x0000082C
+#define GPRCM_O_SPARE_RW1 0x00000830
+#define GPRCM_O_APLLMCS_MCU_OVERRIDES \
+ 0x00000834
+
+#define GPRCM_O_SYSCLK_SWITCH_STATUS \
+ 0x00000838
+
+#define GPRCM_O_REF_LDO_CONTROLS \
+ 0x0000083C
+
+#define GPRCM_O_REF_RTRIM_CONTROL \
+ 0x00000840
+
+#define GPRCM_O_REF_SLICER_CONTROLS0 \
+ 0x00000844
+
+#define GPRCM_O_REF_SLICER_CONTROLS1 \
+ 0x00000848
+
+#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \
+ 0x0000084C
+
+#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \
+ 0x00000850
+
+#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \
+ 0x00000854
+
+#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \
+ 0x00000858
+
+#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \
+ 0x0000085C
+
+#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \
+ 0x00000860
+
+#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \
+ 0x00000864
+
+#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868
+#define GPRCM_O_MEMSS_PWR_PS 0x0000086C
+#define GPRCM_O_REF_FSM_DEBUG 0x00000870
+#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \
+ 0x00000874
+
+#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \
+ 0x00000878
+
+#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \
+ 0x0000087C
+
+#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \
+ 0x00000880
+
+#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \
+ 0x00000884
+
+#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \
+ 0x00000888
+
+#define GPRCM_O_MEM_REF_FSM_CFG2 \
+ 0x0000088C
+
+#define GPRCM_O_TESTCTRL_POWER_CTRL \
+ 0x00000C10
+
+#define GPRCM_O_SSDIO_POWER_CTRL \
+ 0x00000C14
+
+#define GPRCM_O_MCSPI_N1_POWER_CTRL \
+ 0x00000C18
+
+#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C
+#define GPRCM_O_WL_SDIO_POWER_CTRL \
+ 0x00000C20
+
+#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \
+ 0x00000C24
+
+#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \
+ 0x00000C28
+
+#define GPRCM_O_APPS_SECURE_INIT_DONE \
+ 0x00000C30
+
+#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \
+ 0x00000C34
+
+#define GPRCM_O_EN_APPS_REBOOT 0x00000C38
+#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \
+ 0x00000C3C
+
+#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \
+ 0x00000C40
+
+#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \
+ 0x00000C44
+
+#define GPRCM_O_NWP_PWR_STATE 0x00000C48
+#define GPRCM_O_APPS_PWR_STATE 0x00000C4C
+#define GPRCM_O_MCU_PWR_STATE 0x00000C50
+#define GPRCM_O_WTOP_PM_PS 0x00000C54
+#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C58
+
+#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C5C
+
+#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C60
+
+#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C64
+
+#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C68
+
+#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C6C
+
+#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C70
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \
+ 0x00000C78
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \
+ 0x00000C7C
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \
+ 0x00000C80
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \
+ 0x00000C84
+
+#define GPRCM_O_WTOP_MEM_RET_CFG \
+ 0x00000C88
+
+#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \
+ 0x00000C8C
+
+#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \
+ 0x00000C90
+
+#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \
+ 0x00000C94
+
+#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \
+ 0x00000C98
+
+#define GPRCM_O_DCDC_CLK_GEN_CONFIG \
+ 0x00000C9C
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \
+ 0x00000CA0
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \
+ 0x00000CA4
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \
+ 0x00000CA8
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \
+ 0x00000CAC
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \
+ 0x00000CB0
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \
+ 0x00000CB4
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \
+ 0x00000CB8
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \
+ 0x00000CBC
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG0 \
+ 0x00000CC0
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG1 \
+ 0x00000CC4
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG2 \
+ 0x00000CC8
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG3 \
+ 0x00000CCC
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG4 \
+ 0x00000CD0
+
+#define GPRCM_O_APPS_SS_OVERRIDES \
+ 0x00000CD4
+
+#define GPRCM_O_NWP_SS_OVERRIDES \
+ 0x00000CD8
+
+#define GPRCM_O_SHARED_SS_OVERRIDES \
+ 0x00000CDC
+
+#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \
+ 0x00000CE0
+
+#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \
+ 0x00000CE4
+
+#define GPRCM_O_MCU_PSCON_OVERRIDES \
+ 0x00000CE8
+
+#define GPRCM_O_WTOP_PSCON_OVERRIDES \
+ 0x00000CEC
+
+#define GPRCM_O_WELP_PSCON_OVERRIDES \
+ 0x00000CF0
+
+#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \
+ 0x00000CF4
+
+#define GPRCM_O_MCSPI_PSCON_OVERRIDES \
+ 0x00000CF8
+
+#define GPRCM_O_SSDIO_PSCON_OVERRIDES \
+ 0x00000CFC
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SOFT_RESET register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \
+ 0x00000002 // Soft-reset1 for APPS : Cortex
+ // sysrstn is asserted and in
+ // addition to that the associated
+ // APPS Peripherals are also reset.
+ // This is an auto-clear bit.
+
+#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \
+ 0x00000001 // Soft-reset0 for APPS : Only
+ // sys-resetn for Cortex will be
+ // asserted. This is an auto-clear
+ // bit.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKEUP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \
+ 0x000000FF // Mask for LPDS Wakeup interrupt :
+ // [7] - Host IRQ from NWP [6] -
+ // NWP_LPDS_Wake_irq (TRUE_LPDS) [5]
+ // - NWP Wake-request to APPS [4] -
+ // GPIO [3:1] - Reserved [0] - LPDS
+ // Wakeup-timer
+
+#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKEUP_SRC register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \
+ 0x000000FF // Indicates the cause for wakeup
+ // from LPDS : [7] - Host IRQ from
+ // NWP [6] - NWP_LPDS_Wake_irq
+ // (TRUE_LPDS) [5] - NWP
+ // Wake-request to APPS [4] - GPIO
+ // [3:1] - Reserved [0] - LPDS
+ // Wakeup-timer
+
+#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_RESET_CAUSE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \
+ 0x000000FF // Indicates the reset cause for
+ // APPS : "0000" - Wake from HIB/OFF
+ // mode; "0001" - Wake from LPDS ;
+ // "0010" - Reserved ; "0011" -
+ // Soft-reset0 (Only APPS
+ // Cortex-sysrstn is asserted);
+ // "0100" - Soft-reset1 (APPS
+ // Cortex-sysrstn and APPS
+ // peripherals are reset); "0101" -
+ // WDOG0 (APPS Cortex-sysrstn and
+ // APPS peripherals are reset);
+ // "0110" - MCU Soft-reset (APPS +
+ // NWP Cortex-sysrstn + Peripherals
+ // are reset); "0111" - Secure Init
+ // done (Indication that reset has
+ // happened after DevInit); "1000" -
+ // Dev Mode Patch Init done (During
+ // development mode, patch
+ // downloading and Cortex
+ // re-vectoring is completed)
+
+#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \
+ 0xFFFFFFFF // OPP Request Configuration
+ // (Number of slow-clk cycles) for
+ // LPDS Wake-timer : This
+ // configuration implies the RTC
+ // time-stamp, which must be few
+ // slow-clks prior to
+ // APPS_LPDS_WAKETIME_WAKE_CFG, such
+ // that by the time actual wakeup is
+ // given, OPP is already switched to
+ // ACTIVE (RUN).
+
+#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SRAM_DSLP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \
+ 0x000FFFFF // Configuration of APPS Memories
+ // during Deep-sleep : 0 - SRAMs are
+ // OFF ; 1 - SRAMs are Retained.
+ // APPS SRAM Cluster information :
+ // [0] - 1st column in MEMSS
+ // (Applicable only when owned by
+ // APPS); [1] - 2nd column in MEMSS
+ // (Applicable only when owned by
+ // APPS); [2] - 3rd column in MEMSS
+ // (Applicable only when owned by
+ // APPS) ; [3] - 4th column in MEMSS
+ // (Applicable only when owned by
+ // APPS) ; [16] - MCU-PD - Apps
+ // cluster 0 (TBD); [19:18] -
+ // Reserved.
+
+#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SRAM_LPDS_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \
+ 0x000FFFFF // Configuration of APPS Memories
+ // during LPDS : 0 - SRAMs are OFF ;
+ // 1 - SRAMs are Retained. APPS SRAM
+ // Cluster information : [0] - 1st
+ // column in MEMSS (Applicable only
+ // when owned by APPS); [1] - 2nd
+ // column in MEMSS (Applicable only
+ // when owned by APPS); [2] - 3rd
+ // column in MEMSS (Applicable only
+ // when owned by APPS) ; [3] - 4th
+ // column in MEMSS (Applicable only
+ // when owned by APPS) ; [16] -
+ // MCU-PD - Apps cluster 0 (TBD);
+ // [19:18] - Reserved.
+
+#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \
+ 0xFFFFFFFF // Configuration (in no of
+ // slow_clks) which says when the
+ // actual wakeup request for
+ // removing the PD-reset be given.
+
+#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TOP_DIE_ENABLE register.
+//
+//******************************************************************************
+#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \
+ 0x00001000
+
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \
+ 0x00000F00
+
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \
+ 0x00000002 // 1 - Top-die is enabled ;
+
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \
+ 0x00000001 // 1 - Enable the top-die ; 0 -
+ // Disable the top-die
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register.
+//
+//******************************************************************************
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \
+ 0xF0000000 // Configuration (in slow_clks) for
+ // number of clks between
+ // Flash-3p3-rstn to D2D POR Resetn.
+
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \
+ 0x00FF0000 // Configuration (in slow_clks) for
+ // number of clks between Top-die
+ // Switch-Enable and Top-die Flash
+ // 3p3 Reset removal
+
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \
+ 0x000000FF // Configuration (in slow_clks) for
+ // number of clks between D2D POR
+ // Reset removal and bottom die FMC
+ // reset removal
+
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_GLOBAL_SOFT_RESET register.
+//
+//******************************************************************************
+#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \
+ 0x00000001 // 1 - Assert the global reset for
+ // MCU (APPS + NWP) ; Asserts both
+ // Cortex sysrstn and its
+ // peripherals 0 - Deassert the
+ // global reset for MCU (APPS + NWP)
+ // ; Asserts both Cortex sysrstn and
+ // its peripherals Note : Reset for
+ // shared peripherals is not
+ // affected here.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_ADC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \
+ 0x000007C0 // Configuration (in number of 38.4
+ // MHz clks) for the OFF-Time in
+ // generation of ADC_CLK
+
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \
+ 0x0000003E // Configuration (in number of 38.4
+ // MHz clks) for the ON-Time in
+ // generation of ADC_CLK
+
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the ADC_CLK ; 0 -
+ // Disable the ADC_CLK
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_GPIO_WAKE_CONF register.
+//
+//******************************************************************************
+#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \
+ 0x00000003 // "00" - Wake on Level0 on
+ // selected GPIO pin (GPIO is
+ // selected inside the HIB3p3
+ // module); "01" - Wakeup on
+ // fall-edge of GPIO pin.
+
+#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register.
+//
+//******************************************************************************
+#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \
+ 0xFFFFFFFE
+
+#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1
+#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \
+ 0x00000001 // 1 - Override the secure-mode
+ // done for booting up NWP (Wakeup
+ // NWP on its event independent of
+ // CM4 state) ; 0 - Donot override
+ // the secure-mode done for NWP boot
+ // (NWP must be enabled by CM4 only)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_HCLK_DIV_CFG register.
+//
+//******************************************************************************
+#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \
+ 0x00000007 // Division configuration for
+ // HCLKDIVOUT : "000" - Divide by 1
+ // ; "001" - Divide by 2 ; "010" -
+ // Divide by 3 ; "011" - Divide by 4
+ // ; "100" - Divide by 5 ; "101" -
+ // Divide by 6 ; "110" - Divide by 7
+ // ; "111" - Divide by 8
+
+#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_SYSCLK_DIV_CFG register.
+//
+//******************************************************************************
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \
+ 0x00000038
+
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \
+ 0x00000007
+
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_LOCK_TIME_CONF register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \
+ 0x0000FF00
+
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \
+ 0x000000FF
+
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SOFT_RESET register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \
+ 0x00000002 // Soft-reset1 for NWP - Cortex
+ // sysrstn and NWP associated
+ // peripherals are - This is an
+ // auto-clr bit.
+
+#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \
+ 0x00000001 // Soft-reset0 for NWP - Only
+ // Cortex-sysrstn is asserted - This
+ // is an auto-clear bit.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKEUP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \
+ 0x000000FF // Mask for LPDS Wakeup interrupt :
+ // 7 - WLAN Host Interrupt ; 6 -
+ // WLAN to NWP Wake request ; 5 -
+ // APPS to NWP Wake request; 4 -
+ // GPIO Wakeup ; 3 - Autonomous UART
+ // Wakeup ; 2 - SSDIO Wakeup ; 1 -
+ // Autonomous SPI Wakeup ; 0 - LPDS
+ // Wakeup-timer
+
+#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKEUP_SRC register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \
+ 0x000000FF // Indicates the cause for NWP
+ // LPDS-Wakeup : 7 - WLAN Host
+ // Interrupt ; 6 - WLAN to NWP Wake
+ // request ; 5 - APPS to NWP Wake
+ // request; 4 - GPIO Wakeup ; 3 -
+ // Autonomous UART Wakeup ; 2 -
+ // SSDIO Wakeup ; 1 - Autonomous SPI
+ // Wakeup ; 0 - LPDS Wakeup-timer
+
+#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_RESET_CAUSE register.
+//
+//******************************************************************************
+#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \
+ 0x000000FF // Indicates the reset cause for
+ // NWP : "0000" - Wake from HIB/OFF
+ // mode; "0001" - Wake from LPDS ;
+ // "0010" - Reserved ; "0011" -
+ // Soft-reset0 (Only NWP
+ // Cortex-sysrstn is asserted);
+ // "0100" - Soft-reset1 (NWP
+ // Cortex-sysrstn and NWP
+ // peripherals are reset); "0101" -
+ // WDOG0 (NWP Cortex-sysrstn and NWP
+ // peripherals are reset); "0110" -
+ // MCU Soft-reset (APPS + NWP
+ // Cortex-sysrstn + Peripherals are
+ // reset); "0111" - SSDIO Function2
+ // reset (Only Cortex-sysrstn is
+ // asserted) ; "1000" - Reset due to
+ // WDOG of APPS (NWP Cortex-sysrstn
+ // and NWP peripherals are reset);
+
+#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \
+ 0xFFFFFFFF // OPP Request Configuration
+ // (Number of slow-clk cycles) for
+ // LPDS Wake-timer
+
+#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SRAM_DSLP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \
+ 0x000FFFFF // Configuration of NWP Memories
+ // during DSLP : 0 - SRAMs are OFF ;
+ // 1 - SRAMs are Retained. NWP SRAM
+ // Cluster information : [2] - 3rd
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [3] - 4th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [4] - 5th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [5] - 6th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [6] - 7th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [7] - 8th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [8] - 9th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [9] - 10th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [10] - 11th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [11] - 12th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [12] - 13th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [13] - 14th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [14] - 15th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [19:18] -
+ // Reserved.
+
+#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SRAM_LPDS_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \
+ 0x000FFFFF // Configuration of NWP Memories
+ // during LPDS : 0 - SRAMs are OFF ;
+ // 1 - SRAMs are Retained. NWP SRAM
+ // Cluster information : [2] - 3rd
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [3] - 4th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [4] - 5th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [5] - 6th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [6] - 7th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [7] - 8th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [8] - 9th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [9] - 10th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [10] - 11th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [11] - 12th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [12] - 13th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [13] - 14th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [14] - 15th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [19:18] -
+ // Reserved.
+
+#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \
+ 0xFFFFFFFF // Wake time configuration (no of
+ // slow clks) for NWP wake from
+ // LPDS.
+
+#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register.
+//
+//******************************************************************************
+#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \
+ 0xFFFE0000
+
+#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17
+#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \
+ 0x00010000 // 0 - APPS is selected as host for
+ // Autonms SPI ; 1 - External host
+ // is selected as host for Autonms
+ // SPI
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register.
+//
+//******************************************************************************
+#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \
+ 0x00010000
+
+#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \
+ 0x00000002 // When 1 => IDLE-mode is
+ // acknowledged by the SPI-IP. (This
+ // is for MCSPI_N1)
+
+#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \
+ 0x00000001 // When 1 => Request for IDLE-mode
+ // for autonomous SPI. (This is for
+ // MCSPI_N1)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register.
+//
+//******************************************************************************
+#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \
+ 0x00000001 // 1 - Request for waking up NWP
+ // from any of its low-power modes
+ // (SLP/DSLP/LPDS)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register.
+//
+//******************************************************************************
+#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \
+ 0x00000001 // 1 - Request for wakinp up WLAN
+ // from its ELP Mode (This gets
+ // triggered to ELP-logic of WLAN)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_GPIO_WAKE_CONF register.
+//
+//******************************************************************************
+#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \
+ 0x00000003 // "00" - Wakeup on level0 of the
+ // selected GPIO (GPIO gets selected
+ // inside HIB3P3-module); "01" -
+ // Wakeup on fall-edge of selected
+ // GPIO.
+
+#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG12 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \
+ 0x0000FFFF // This corrsponds to ROW_32
+ // [31:16] of the FUSEFARM. SPARE
+
+#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG5 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \
+ 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM
+ // : [5:0] - ADC OFFSET ; [13:6] -
+ // TEMP_SENSE ; [14:14] - DFT_GSG ;
+ // [15:15] - FMC_DISABLE ; [31:16] -
+ // WLAN_MAC ID
+
+#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG6 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \
+ 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM
+ // : [31:0] : WLAN MAC ID
+
+#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_FSM_CFG0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \
+ 0x00FF0000 // ANA-BGAP Settling time (In
+ // number of slow_clks)
+
+#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16
+#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \
+ 0x0000FF00 // Slicer LDO settling time (In
+ // number of slow clks)
+
+#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8
+#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \
+ 0x000000FF // Dig-buffer settling time (In
+ // number of slow clks)
+
+#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_FSM_CFG1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \
+ 0xFF000000 // XTAL settling time (In number of
+ // slow clks)
+
+#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24
+#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \
+ 0x00FF0000 // LV Slicer settling time
+
+#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \
+ 0x0000FF00 // HV Slicer Pull-down settling
+ // time
+
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \
+ 0x000000FF // HV Slicer settling time
+
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \
+ 0x00007F00 // Configuration for WLAN APLLMCS -
+ // N[6:0], if the XTAL frequency is
+ // 40 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \
+ 0x000000FF // Configuration for WLAN APLLMCS -
+ // M[7:0], if the XTAL frequency is
+ // 40 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \
+ 0x00000010 // Configuration for WLAN APLLMCS -
+ // if the XTAL frequency if 40 MHz
+ // (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \
+ 0x00000008 // Configuration for WLAN APLLMCS -
+ // Sel96, if the XTAL frequency is
+ // 40 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \
+ 0x00000007 // Configuration for WLAN APLLMCS -
+ // Selinpfreq, if the XTAL frequency
+ // is 40 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \
+ 0x00007F00 // Configuration for WLAN APLLMCS -
+ // N[6:0], if the XTAL frequency is
+ // 26 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \
+ 0x000000FF // Configuration for WLAN APLLMCS -
+ // M[7:0], if the XTAL frequency is
+ // 26 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \
+ 0x00000010 // Configuration for WLAN APLLMCS -
+ // if the XTAL frequency if 26 MHz
+ // (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \
+ 0x00000008 // Configuration for WLAN APLLMCS -
+ // Sel96, if the XTAL frequency is
+ // 26 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \
+ 0x00000007 // Configuration for WLAN APLLMCS -
+ // Selinpfreq, if the XTAL frequency
+ // is 26 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \
+ 0x00080000
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \
+ 0x00070000
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \
+ 0x00000700
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \
+ 0x00000020 // Override control for
+ // WLAN_APLLMCS_M[8]. When set to1,
+ // M[8] will be selected by bit [3].
+ // (Else controlled from WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \
+ 0x00000010 // Override for WLAN_APLLMCS_M[8].
+ // Applicable only when bit [4] is
+ // set to 1. (Else controlled from
+ // WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \
+ 0x00000004 // Override control for
+ // WLAN_APLLMCS_N[8:7]. When set
+ // to1, N[8:7] will be selected by
+ // bits [2:1]. (Else controlled from
+ // WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \
+ 0x00000003 // Override value for
+ // WLAN_APLLMCS_N[8:7] bits.
+ // Applicable only when bit [1] is
+ // set to 1. (Else controlled from
+ // WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \
+ 0x38000000
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \
+ 0x07000000
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \
+ 0x007F0000 // Configuration for MCU-APLLMCS :
+ // N during RUN mode. Selected if
+ // the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \
+ 0x0000FF00 // Configuration for MCU-APLLMCS :
+ // M during RUN mode. Selected if
+ // the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // M[8] during RUN mode. Selected if
+ // the XTAL frequency is 38.4 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \
+ 0x00000003 // Configuration for MCU-APLLMCS :
+ // N[8:7] during RUN mode. Selected
+ // if the XTAL frequency is 38.4 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // HISPEED during RUN mode. Selected
+ // if the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \
+ 0x00000008 // Configuration for MCU-APLLMCS :
+ // SEL96 during RUN mode. Selected
+ // if the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \
+ 0x00000007 // Configuration for MCU-APLLMCS :
+ // SELINPFREQ during RUN mode.
+ // Selected if the XTAL frequency is
+ // 38.4 MHz (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \
+ 0x007F0000 // Configuration for MCU-APLLMCS :
+ // N during RUN mode. Selected if
+ // the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \
+ 0x0000FF00 // Configuration for MCU-APLLMCS :
+ // M during RUN mode. Selected if
+ // the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // M[8] during RUN mode. Selected if
+ // the XTAL frequency is 26 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \
+ 0x00000003 // Configuration for MCU-APLLMCS :
+ // N[8:7] during RUN mode. Selected
+ // if the XTAL frequency is 26 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // HISPEED during RUN mode. Selected
+ // if the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \
+ 0x00000008 // Configuration for MCU-APLLMCS :
+ // SEL96 during RUN mode. Selected
+ // if the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \
+ 0x00000007 // Configuration for MCU-APLLMCS :
+ // SELINPFREQ during RUN mode.
+ // Selected if the XTAL frequency is
+ // 26 MHz (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \
+ 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 -
+ // APLLMCS_MCU is not locked
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \
+ 0x00000200 // Override for APLLMCS_MCU Enable.
+ // Applicable if bit [8] is set
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \
+ 0x00000100 // 1 - Enable for APLLMCS_MCU comes
+ // from bit [9]. 0 - Enable for
+ // APLLMCS_MCU comes from FSM.
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \
+ 0x00000006 // Override for sysclk src
+ // (applicable only if bit [0] is
+ // set to 1. "00"- SLOW_CLK "01"-
+ // XTAL_CLK "10"- PLL_CLK
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1
+#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \
+ 0x00000001 // 1 - Sysclk src is selected from
+ // bits [2:1] of this register. 0 -
+ // Sysclk src is selected from FSM
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SYSCLK_SWITCH_STATUS register.
+//
+//******************************************************************************
+#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \
+ 0x00000001 // 1 - Sysclk switching is
+ // complete. 0 - Sysclk switching is
+ // in progress.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_LDO_CONTROLS register.
+//
+//******************************************************************************
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \
+ 0x00010000 // 1 - Enable for REF_LDO comes
+ // from bit [0] of this register ; 0
+ // - Enable for REF_LDO comes from
+ // the FSM. Note : Final REF_LDO_EN
+ // reaches on the port
+ // TOP_PM_REG2[0] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \
+ 0x0000C000 // Spare bits for REF_CTRL_FSM.
+ // Reaches directly on port
+ // TOP_PM_REG2[15:14] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14
+#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \
+ 0x00003800 // REF TLOAD Enable. Reaches
+ // directly on port
+ // TOP_PM_REG2[13:11] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \
+ 0x00000700 // REF_LDO Test-mux control.
+ // Reaches directly on port
+ // TOP_PM_REG2[10:8] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8
+#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \
+ 0x000000C0 // REF BW Control. Reaches directly
+ // on port TOP_PM_REG2[7:6] of
+ // gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6
+#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \
+ 0x0000003C // REF VTRIM Control. Reaches
+ // directly on port TOP_PM_REG2[5:2]
+ // of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \
+ 0x00000002 // REF LDO Bypass Enable. Reaches
+ // directly on port TOP_PM_REG2[1]
+ // of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \
+ 0x00000001 // Override for REF_LDO Enable.
+ // Applicable only if bit [16] of
+ // this register is set. Note :
+ // Final REF_LDO_EN reaches on the
+ // port TOP_PM_REG2[0] of gprcm.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_RTRIM_CONTROL register.
+//
+//******************************************************************************
+#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \
+ 0x18000000 // This is [5:4] bits of
+ // TOP_PM_REG0
+
+#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27
+#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \
+ 0x07FF0000 // This is [15:5] bits of
+ // TOP_CLKM_REG0
+
+#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16
+#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \
+ 0x00000100 // 1 - CLKM_RTRIM comes for
+ // bits[4:0] of this register. 0 -
+ // CLKM_RTRIM comes from Efuse
+ // (after efuse_done = 1).
+
+#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \
+ 0x0000001F // CLKM_TRIM Override. Applicable
+ // when efuse_done = 0 or bit[8] is
+ // set to 1.
+
+#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_SLICER_CONTROLS0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \
+ 0x00200000 // 1 - EN_DIG_BUF_TOP comes from
+ // bit [14] of this register. 0 -
+ // EN_DIG_BUF_TOP comes from the
+ // FSM. Note : Final EN_DIG_BUF_WLAN
+ // reaches on TOP_CLKM_REG1_IN[14]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \
+ 0x00100000 // 1 - EN_DIG_BUF_TOP comes from
+ // bit [15] of this register. 0 -
+ // EN_DIG_BUF_TOP comes from the
+ // FSM. Note : Final EN_DIG_BUF_TOP
+ // reaches on TOP_CLKM_REG1_IN[15]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \
+ 0x00080000 // 1 - EN_XTAL comes from bit [3]
+ // of this register. 0 - EN_XTAL
+ // comes from FSM. Note : Final
+ // XTAL_EN reaches on
+ // TOP_CLKM_REG1_IN[3] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \
+ 0x00040000 // 1 - Enable HV Slicer comes from
+ // bit [2] of this register. 0 -
+ // Enable HV Slicer comes from FSM.
+ // Note : Final HV_SLICER_EN reaches
+ // on port TOP_CLKM_REG1_IN[1] of
+ // gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \
+ 0x00020000 // 1 - Enable LV Slicer comes from
+ // bit[1] of this register. 0 -
+ // Enable LV Slicer comes from FSM.
+ // Note : final LV_SLICER_EN reaches
+ // on port TOP_CLKM_REG1_IN[2] of
+ // gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \
+ 0x00010000 // 1 - Enable HV Pull-down comes
+ // from bit[0] of this register. 0 -
+ // Enable HV Pull-down comes from
+ // FSM. Note : Final HV_PULL_DOWN
+ // reaches on port
+ // TOP_CLKM_REG1_IN[0] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \
+ 0x00008000 // Override for EN_DIG_BUF_TOP.
+ // Applicable if bit[20] is set to
+ // 1. Note : Final EN_DIG_BUF_TOP
+ // reaches on TOP_CLKM_REG1_IN[15]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \
+ 0x00004000 // Override for EN_DIG_BUF_WLAN.
+ // Applicable if bit[19] is set to
+ // 1. Note : Final EN_DIG_BUF_WLAN
+ // reaches on TOP_CLKM_REG1_IN[14]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \
+ 0x00002000 // CLKOUT Flip Enable. Reaches on
+ // bit[13] of TOP_CLKM_REG1_IN[13]
+ // port of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \
+ 0x00001000 // Enable divide2 in WLAN Clk-path.
+ // Reaches on TOP_CLKM_REG1_IN[12]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \
+ 0x00000800 // Enable divide3 in WLAN Clk-path.
+ // Reaches on TOP_CLKM_REG1_IN[11]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \
+ 0x00000400 // Enable divide4 in WLAN Clk-path.
+ // Reaches on TOP_CLKM_REG1_IN[10]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \
+ 0x000003C0 // CM Test-mux select. Reaches on
+ // TOP_CLMM_REG1_IN[9:6] port of
+ // gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6
+#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \
+ 0x00000030 // Slicer spare0 control. Reaches
+ // on TOP_CLKM_REG1_IN[5:4] port of
+ // gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4
+#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \
+ 0x00000008 // Enable XTAL override. Reaches on
+ // TOP_CLKM_REG1_IN[3] port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \
+ 0x00000004 // Enable HV Slicer override.
+ // Reaches on TOP_CLKM_REG1_IN[1]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \
+ 0x00000002 // Enable LV Slicer override.
+ // Reaches on TOP_CLKM_REG1_IN[2]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \
+ 0x00000001 // Enable HV Pull-down override.
+ // Reaches on TOP_CLKM_REG1_IN[0]
+ // port of gprcm
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_SLICER_CONTROLS1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \
+ 0x0000FC00 // Slicer spare1. Reaches on port
+ // TOP_CLKM_REG2_IN[15:10] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10
+#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \
+ 0x000003F0 // XOSC Trim. Reaches on port
+ // TOP_CLKM_REG2_IN[9:4] of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \
+ 0x00000008 // Slicer ITRIM Toggle. Reaches on
+ // port TOP_CLKM_REG2_IN[3] of
+ // gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \
+ 0x00000007 // LV Slicer trim. Reaches on port
+ // TOP_CLKM_REG2_IN[2:0] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \
+ 0xFF800000
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \
+ 0x00400000 // 1 - REF_MAG_TRIM comes from
+ // bit[4:0] of register
+ // REF_ANA_BGAP_CONTROLS1 [Addr :
+ // 0x0850]; 0 - REF_MAG_TRIM comes
+ // from efuse (After efc_done = 1).
+ // Note : Final REF_MAG_TRIM reaches
+ // on port TOP_PM_REG1[4:0] of gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \
+ 0x00200000 // 1 - REF_V2I_TRIM comes from
+ // bit[9:6] of this register ; 0 -
+ // REF_V2I_TRIM comes from efuse
+ // (After efc_done = 1). Note :
+ // Final REF_V2I_TRIM reaches on
+ // port TOP_PM_REG0[9:6] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \
+ 0x00100000 // 1 - REF_TEMP_TRIM comes from
+ // bit[15:10] of this register ; 0 -
+ // REF_TEMP_TRIM comes from efuse
+ // (After efc_done = 1). Note :
+ // Final REF_TEMP_TRIM reaches on
+ // port TOP_PM_REG0[15:10] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \
+ 0x00080000 // 1 - REF_STARTUP_EN comes from
+ // bit [3] of this register ; 0 -
+ // REF_STARTUP_EN comes from FSM.
+ // Note : Final REF_STARTUP_EN
+ // reaches on port TOP_PM_REG0[3] of
+ // gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \
+ 0x00040000 // 1 - REF_V2I_EN comes from bit
+ // [2] of this register ; 0 -
+ // REF_V2I_EN comes from FSM. Note :
+ // Final REF_V2I_EN reaches on port
+ // TOP_PM_REG0[2] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \
+ 0x00020000 // 1 - REF_FC_EN comes from bit [1]
+ // of this register ; 0 - REF_FC_EN
+ // comes from FSM. Note : Final
+ // REF_FC_EN reaches on port
+ // TOP_PM_REG0[1] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \
+ 0x00010000 // 1 - REF_BGAP_EN comes from bit
+ // [0] of this register ; 0 -
+ // REF_BGAP_EN comes from FSM. Note
+ // : Final REF_BGAP_EN reaches on
+ // port TOP_PM_REG0[0] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \
+ 0x0000FC00 // REF_TEMP_TRIM override.
+ // Applicable when bit [20] of this
+ // register set to 1. (or efc_done =
+ // 0) Note : Final REF_TEMP_TRIM
+ // reaches on port
+ // TOP_PM_REG0[15:10] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \
+ 0x000003C0 // REF_V2I_TRIM Override.
+ // Applicable when bit [21] of this
+ // register set to 1 . (of efc_done
+ // = 0) Note : Final REF_V2I_TRIM
+ // reaches on port TOP_PM_REG0[9:6]
+ // of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \
+ 0x00000030
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \
+ 0x00000008 // REF_STARTUP_EN override.
+ // Applicable when bit [19] of this
+ // register is set to 1. Note :
+ // Final REF_STARTUP_EN reaches on
+ // port TOP_PM_REG0[3] of gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \
+ 0x00000004 // REF_V2I_EN override. Applicable
+ // when bit [21] of this register is
+ // set to 1. Note : Final REF_V2I_EN
+ // reaches on port TOP_PM_REG0[2] of
+ // gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \
+ 0x00000002 // REF_FC_EN override. Applicable
+ // when bit [17] of this register is
+ // set to 1. Note : Final REF_FC_EN
+ // reaches on port TOP_PM_REG0[1] of
+ // gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \
+ 0x00000001 // REF_BGAP_EN override. Applicable
+ // when bit [16] of this register
+ // set to 1. Note : Final
+ // REF_BGAP_EN reaches on port
+ // TOP_PM_REG0[0] of gprcm.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \
+ 0xFFFF0000
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \
+ 0x0000C000 // REF_BGAP_SPARE. Reaches on port
+ // TOP_PM_REG1[15:14] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \
+ 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on
+ // port TOP_PM_REG1[13:9] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \
+ 0x000001E0 // REF_FILT_TRIM. Reaches on port
+ // TOP_PM_REG1[8:5] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \
+ 0x0000001F // REF_MAG_TRIM Override.
+ // Applicable when bit[22] of
+ // REF_ANA_BGAP_CONTROLS0 [0x084C]
+ // set to 1 (of efc_done = 0). Note
+ // : Final REF_MAG_TRIM reaches on
+ // port TOP_PM_REG1[4:0] of gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \
+ 0xFFFF0000
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \
+ 0x0000FFFF // Spare control. Reaches on
+ // TOP_PM_REG3 [15:0] of gprcm.
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \
+ 0xFFFF0000 // Spare control. Reaches on
+ // TOP_CLKM_REG3 [15:0] of gprcm.
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \
+ 0x0000FFFF // Spare control. Reaches on
+ // TOP_CLKM_REG4 [15:0] of gprcm.
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register.
+//
+//******************************************************************************
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \
+ 0xFFFF0000
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \
+ 0x0000FFFF
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register.
+//
+//******************************************************************************
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \
+ 0xFFFFFFC0
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \
+ 0x00000020
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \
+ 0x00000010
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \
+ 0x00000008
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \
+ 0x00000004
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \
+ 0x00000002
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_PLL_REF_LOCK_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \
+ 0xFFFFFFF8
+
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \
+ 0x00000004
+
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \
+ 0x00000002
+
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PSCON_DEBUG register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PSCON_DEBUG_reserved_M \
+ 0xFFFFFFC0
+
+#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \
+ 0x00000038 // MCU_PSCON_RTC_ON = "0000";
+ // MCU_PSCON_RTC_OFF = "0001";
+ // MCU_PSCON_RTC_RET = "0010";
+ // MCU_PSCON_RTC_OFF_TO_ON = "0011";
+ // MCU_PSCON_RTC_RET_TO_ON = "0100";
+ // MCU_PSCON_RTC_ON_TO_RET = "0101";
+ // MCU_PSCON_RTC_ON_TO_OFF = "0110";
+ // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP
+ // = "0111";
+ // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP
+ // = "1000";
+
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \
+ 0x00000007
+
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEMSS_PWR_PS register.
+//
+//******************************************************************************
+#define GPRCM_MEMSS_PWR_PS_reserved_M \
+ 0xFFFFFFF8
+
+#define GPRCM_MEMSS_PWR_PS_reserved_S 3
+#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \
+ 0x00000007 // MEMSS_PM_SLEEP = "000";
+ // MEMSS_PM_WAIT_OPP = "010";
+ // MEMSS_PM_ACTIVE = "011";
+ // MEMSS_PM_SLEEP_TO_ACTIVE = "100";
+ // MEMSS_PM_ACTIVE_TO_SLEEP = "101";
+
+#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_FSM_DEBUG register.
+//
+//******************************************************************************
+#define GPRCM_REF_FSM_DEBUG_reserved_M \
+ 0xFFFFFFC0
+
+#define GPRCM_REF_FSM_DEBUG_reserved_S 6
+#define GPRCM_REF_FSM_DEBUG_fref_mode_M \
+ 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11
+ // - XTAL Mode
+
+#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4
+#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \
+ 0x0000000F // constant FREF_CLK_OFF = "00000";
+ // constant FREF_EN_BGAP = "00001";
+ // constant FREF_EN_LDO = "00010";
+ // constant FREF_EN_SLI_HV =
+ // "00011"; constant
+ // FREF_EN_SLI_HV_PD = "00100";
+ // constant FREF_EN_DIG_BUF =
+ // "00101"; constant FREF_EN_OSC =
+ // "00110"; constant FREF_EN_SLI_LV
+ // = "00111"; constant
+ // FREF_EN_CLK_REQ = "01000";
+ // constant FREF_CLK_VALID =
+ // "01001"; constant FREF_MODE_DET0
+ // = "01010"; constant
+ // FREF_MODE_DET1 = "01011";
+ // constant FREF_MODE_DET2 =
+ // "10010"; constant FREF_MODE_DET3
+ // = "10011"; constant FREF_VALID =
+ // "01100"; constant FREF_VALID0 =
+ // "01101"; constant FREF_VALID1 =
+ // "01110"; constant FREF_VALID2 =
+ // "01111"; constant
+ // FREF_WAIT_EXT_TCXO0 = "10000";
+ // constant FREF_WAIT_EXT_TCXO1 =
+ // "10001";
+
+#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register.
+//
+//******************************************************************************
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \
+ 0xFFFFFFE0
+
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \
+ 0x00000010 // 1 - Override the sytem-opp
+ // request to ANATOP using bit0 of
+ // this register
+
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \
+ 0x0000000F // "0001" - RUN ; "0010" - DSLP ;
+ // "0100" - LPDS ; Others - NA
+
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register.
+//
+//******************************************************************************
+#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \
+ 0xFFFFFFFE
+
+#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1
+#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \
+ 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS)
+ // entry even if Test-Pd is kept ON
+ // ; 0 - Donot enable sleep-opp
+ // (DSLP/LPDS) entry with Test-Pd
+ // ON.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \
+ 0xFFFFFFF8
+
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \
+ 0x00000004 // NA
+
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \
+ 0x00000002 // NA
+
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \
+ 0x00000001 // NA
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \
+ 0x00000004 // 1 - Override the MCU-PD power
+ // modes using bits [1] & [0] ;
+
+#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \
+ 0x00000002 // 1 - Request for power-down of
+ // MCU-PD ;
+
+#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \
+ 0x00000001 // 1 - Request for retention mode
+ // of MCU-PD.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \
+ 0x00000002 // 1- Override the MCSPI
+ // (Autonomous SPI) memory state
+ // using bit [0]
+
+#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \
+ 0x00000001 // 1 - Request for power-down of
+ // Autonomous SPI 8k memory ; 0 -
+ // Donot request power-down of
+ // Autonomous SPI 8k Memory
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \
+ 0x00000100
+
+#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \
+ 0x00000002
+
+#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_REF_FSM_CFG2 register.
+//
+//******************************************************************************
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \
+ 0x00380000 // Number of RTC clocks for keeping
+ // the FC_EN asserted high
+
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \
+ 0x00070000 // Number of RTC clocks for keeping
+ // the STARTUP_EN asserted high
+
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \
+ 0x0000FFFF // Number of RTC clocks for waiting
+ // for clock to settle.
+
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TESTCTRL_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \
+ 0x00000006
+
+#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1
+#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \
+ 0x00000001 // 0 - Disable the TestCtrl-pd ; 1
+ // - Enable the TestCtrl-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SSDIO_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \
+ 0x00000006 // 1 - SSDIO-PD is ON ; 0 -
+ // SSDIO-PD is OFF
+
+#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1
+#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \
+ 0x00000001 // 0 - Disable the SSDIO-pd ; 1 -
+ // Enable the SSDIO-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCSPI_N1_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \
+ 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 -
+ // MCSPI_N1-PD if OFF
+
+#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1
+#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \
+ 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1
+ // - Enable the MCSPI_N1-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WELP_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \
+ 0x00001C00
+
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \
+ 0x00000200
+
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \
+ 0x00000100
+
+#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \
+ 0x00000006
+
+#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1
+#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \
+ 0x00000001 // 0 - Disable the WELP-pd ; 1 -
+ // Enable the WELP-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WL_SDIO_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \
+ 0x00000006
+
+#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1
+#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \
+ 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 -
+ // Enable the WL_SDIO-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register.
+//
+//******************************************************************************
+#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \
+ 0x00FFFFFF // SRAM (WTOP+DRP) state during
+ // Active-mode : 1 - SRAMs are ON ;
+ // 0 - SRAMs are OFF. Cluster
+ // information : [0] - 1st column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) [1] - 2nd column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [2] - 3rd column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [3] - 4th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [4] -
+ // 5th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [5] - 6th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [6] - 7th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [7] - 8th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [8] - 9th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [9] -
+ // 10th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [10] - 11th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [11] - 12th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [12] - 13th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [13] - 14th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [14] -
+ // 15th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [15] - 16th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [23:16] - Internal to
+ // WTOP Cluster
+
+#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register.
+//
+//******************************************************************************
+#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \
+ 0x00FFFFFF // SRAM (WTOP+DRP) state during
+ // Sleep-mode : 1 - SRAMs are RET ;
+ // 0 - SRAMs are OFF. Cluster
+ // information : [0] - 1st column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) [1] - 2nd column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [2] - 3rd column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [3] - 4th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [4] -
+ // 5th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [5] - 6th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [6] - 7th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [7] - 8th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [8] - 9th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [9] -
+ // 10th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [10] - 11th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [11] - 12th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [12] - 13th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [13] - 14th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [14] -
+ // 15th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [15] - 16th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [23:16] - Internal to
+ // WTOP Cluster
+
+#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SECURE_INIT_DONE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \
+ 0x00000002 // 1-Secure mode init is done ;
+ // 0-Secure mode init is not done
+
+#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \
+ 0x00000001 // Must be programmed 1 in order to
+ // say that secure-mode device init
+ // is done
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_DEV_MODE_INIT_DONE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \
+ 0x00000001 // 1 - Patch download and other
+ // initializations are done (before
+ // removing APPS resetn) for
+ // development mode (#3) . 0 -
+ // Development mode (#3) init is not
+ // done yet
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_EN_APPS_REBOOT register.
+//
+//******************************************************************************
+#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \
+ 0x00000001 // 1 - When 1, disable the reboot
+ // of APPS after DevInit is
+ // completed. In this case, APPS
+ // will permanantly help in reset. 0
+ // - When 0, enable the reboot of
+ // APPS after DevInit is completed.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_APPS_PERIPH_PRESENT register.
+//
+//******************************************************************************
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \
+ 0x00010000 // 1 - Enable ; 0 - Disable
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \
+ 0x00008000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \
+ 0x00004000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \
+ 0x00002000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \
+ 0x00001000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \
+ 0x00000800
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \
+ 0x00000400
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \
+ 0x00000200
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \
+ 0x00000100
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \
+ 0x00000080
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \
+ 0x00000040
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \
+ 0x00000020
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \
+ 0x00000010
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \
+ 0x00000008
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \
+ 0x00000004
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \
+ 0x00000002
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_NWP_PERIPH_PRESENT register.
+//
+//******************************************************************************
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \
+ 0x00000200
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \
+ 0x00000100
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \
+ 0x00000080
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \
+ 0x00000040
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \
+ 0x00000020
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \
+ 0x00000010
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \
+ 0x00000008
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \
+ 0x00000004
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \
+ 0x00000002
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register.
+//
+//******************************************************************************
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \
+ 0x00000040
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \
+ 0x00000020
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \
+ 0x00000010
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \
+ 0x00000008
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \
+ 0x00000004
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \
+ 0x00000002
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_PWR_STATE register.
+//
+//******************************************************************************
+#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \
+ 0x00000F00 // "0000"- PORZ :- NWP is yet to be
+ // enabled by APPS during powerup
+ // (from HIB/OFF) ; "0011"- ACTIVE
+ // :- NWP is enabled, clocks and
+ // resets to NWP-SubSystem are
+ // enabled ; "0010"- LPDS :- NWP is
+ // in LPDS-mode ; Clocks and reset
+ // to NWP-SubSystem are gated ;
+ // "0101"- WAIT_FOR_OPP :- NWP is in
+ // transition from LPDS to ACTIVE,
+ // where it is waiting for OPP to be
+ // stable ; "1000"-
+ // WAKE_TIMER_OPP_REQ :- NWP is in
+ // transition from LPDS, where the
+ // wakeup cause is LPDS_Wake timer
+ // OTHERS : NA
+
+#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8
+#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \
+ 0x00000007 // "000" - NWP_RUN : NWP is in RUN
+ // state (default) - Applicable only
+ // when NWP_PWR_STATE_PS = ACTIVE ;
+ // "001" - NWP_SLP : NWP is in SLEEP
+ // state (default) - Applicable only
+ // when NWP_PWR_STATE_PS = ACTIVE ;
+ // "010" - NWP_DSLP : NWP is in
+ // Deep-Sleep state (default) -
+ // Applicable only when
+ // NWP_PWR_STATE_PS = ACTIVE ; "011"
+ // - WAIT_FOR_ACTIVE : NWP is in
+ // transition from Deep-sleep to
+ // Run, where it is waiting for OPP
+ // to be stable ; "100" -
+ // WAIT_FOR_DSLP_TIMER_WAKE_REQ :
+ // NWP is in transition from
+ // Deep-sleep to Run, where the
+ // wakeup cause is deep-sleep
+ // wake-timer
+
+#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_PWR_STATE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \
+ 0x00000F00 // "0000"- PORZ :- APPS is waiting
+ // for PLL_clock during powerup
+ // (from HIB/OFF) ; "0011"- ACTIVE
+ // :- APPS is enabled, clocks and
+ // resets to APPS-SubSystem are
+ // enabled ; APPS might be either in
+ // Secure or Un-secure mode during
+ // this state. "1001" -
+ // SECURE_MODE_LPDS :- While in
+ // ACTIVE (Secure-mode), APPS had to
+ // program the DevInit_done bit at
+ // the end, after which it enters
+ // into this state, where the reset
+ // to APPS will be asserted. From
+ // this state APPS might either
+ // re-boot itself or enter into LPDS
+ // depending upon whether the device
+ // is 3200 or 3100. "0010"- LPDS :-
+ // APPS is in LPDS-mode ; Clocks and
+ // reset to APPS-SubSystem are gated
+ // ; "0101"- WAIT_FOR_OPP :- APPS is
+ // in transition from LPDS to
+ // ACTIVE, where it is waiting for
+ // OPP to be stable ; "1000" -
+ // WAKE_TIMER_OPP_REQ : APPS is in
+ // transition from LPDS, where the
+ // wakeup cause is LPDS_Wake timer ;
+ // "1010" - WAIT_FOR_PATCH_INIT :
+ // APPS enters into this state
+ // during development-mode #3 (SOP =
+ // 3), where it is waiting for patch
+ // download to complete and 0x4 hack
+ // is programmed. OTHERS : NA
+
+#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8
+#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \
+ 0x00000007 // "000" - APPS_RUN : APPS is in
+ // RUN state (default) - Applicable
+ // only when APPS_PWR_STATE_PS =
+ // ACTIVE ; "001" - APPS_SLP : APPS
+ // is in SLEEP state (default) -
+ // Applicable only when
+ // APPS_PWR_STATE_PS = ACTIVE ;
+ // "010" - APPS_DSLP : APPS is in
+ // Deep-Sleep state (default) -
+ // Applicable only when
+ // APPS_PWR_STATE_PS = ACTIVE ;
+ // "011" - WAIT_FOR_ACTIVE : APPS is
+ // in transition from Deep-sleep to
+ // Run, where it is waiting for OPP
+ // to be stable ; "100" -
+ // WAIT_FOR_DSLP_TIMER_WAKE_REQ :
+ // APPS is in transition from
+ // Deep-sleep to Run, where the
+ // wakeup cause is deep-sleep
+ // wake-timer
+
+#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PWR_STATE register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \
+ 0x0000001F // TBD
+
+#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_PM_PS register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \
+ 0x00000007 // "011" - WTOP_PM_ACTIVE (Default)
+ // :- WTOP_Pd is in ACTIVE mode;
+ // "100" - WTOP_PM_ACTIVE_TO_SLEEP
+ // :- WTOP_Pd is in transition from
+ // ACTIVE to SLEEP ; "000" -
+ // WTOP_PM_SLEEP : WTOP-Pd is in
+ // Sleep-state ; "100" -
+ // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd
+ // is in transition from SLEEP to
+ // ACTIVE ; "000" -
+ // WTOP_PM_WAIT_FOR_OPP : Wait for
+ // OPP to be stable ;
+
+#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for WTOP PD
+ // Resetz. When set to 1,
+ // WTOP_Resetz will be controlled by
+ // bit [0]
+
+#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for WTOP PD Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for WELP PD
+ // Resetz. When set to 1,
+ // WELP_Resetz will be controlled by
+ // bit [0]
+
+#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for WELP PD Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for WL_SDIO
+ // Resetz. When set to 1,
+ // WL_SDIO_Resetz will be controlled
+ // by bit [0]
+
+#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for WL_SDIO Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for SSDIO
+ // Resetz. When set to 1,
+ // SSDIO_Resetz will be controlled
+ // by bit [0]
+
+#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for SSDIO Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for MCSPI_N1
+ // Resetz. When set to 1,
+ // MCSPI_N1_Resetz will be
+ // controlled by bit [0]
+
+#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for MCSPI_N1 Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for TESTCTRL-PD
+ // Resetz. When set to 1,
+ // TESTCTRL_Resetz will be
+ // controlled by bit [0]
+
+#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for TESTCTRL Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for MCU-PD
+ // Resetz. When set to 1, MCU_Resetz
+ // will be controlled by bit [0]
+
+#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for MCU Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG0 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \
+ 0xFFFFFFFF // This is ROW_14 [31:0] of
+ // FUSEFARM. [0:0] : XTAL_IS_26MHZ
+ // [5:1] : TOP_CLKM_RTRIM[4:0]
+ // [10:6] : ANA_BGAP_MAG_TRIM[4:0]
+ // [16:11] : ANA_BGAP_TEMP_TRIM[5:0]
+ // [20:17] : ANA_BGAP_V2I_TRIM[3:0]
+ // [25:22] : PROCESS INDICATOR
+ // [26:26] : Reserved [31:27] :
+ // FUSEROM Version
+
+#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG1 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \
+ 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM
+ // 1. NWP Peripheral Present bits
+ // [15:8] NWP_GPT_N0_PP [15:15]
+ // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP
+ // [13:13] NWP_UDMA_PP [12:12]
+ // NWP_UART_N0_PP [11:11]
+ // NWP_UART_N1_PP [10:10]
+ // NWP_SSDIO_PP [9:9]
+ // NWP_MCSPI_N1_PP [8:8] 2. Shared
+ // Peripheral Present bits [7:0]
+ // SHARED SPI PP [6:6]
+ // SHARED I2C PP [5:5] SHARED
+ // GPIO-A PP [4:4] SHARED GPIO-B PP
+ // [3:3] SHARED GPIO-C PP [2:2]
+ // SHARED GPIO-D PP [1:1] SHARED
+ // GPIO-E PP [0:0]
+
+#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG2 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \
+ 0xFFFFFFFF // This is ROW_16[15:0] &
+ // ROW_15[31:16] of FUSEFARM.
+ // [31:21] - Reserved [20:16] -
+ // CHIP_ID [15:15] - SSBD SOP
+ // Control [14:14] - SSBD TAP
+ // Control [13:2] - APPS Peripheral
+ // Present bits : APPS_CAMERA_PP
+ // [13:13] APPS_MMCHS_PP [12:12]
+ // APPS_MCASP_PP [11:11]
+ // APPS_MCSPI_A1_PP [10:10]
+ // APPS_MCSPI_A2_PP [9:9]
+ // APPS_UDMA_PP [8:8] APPS_WDOG_PP
+ // [7:7] APPS_UART_A0_PP [6:6]
+ // APPS_UART_A1_PP [5:5]
+ // APPS_GPT_A0_PP [4:4]
+ // APPS_GPT_A1_PP [3:3]
+ // APPS_GPT_A2_PP [2:2]
+ // APPS_GPT_A3_PP [1:1] [0:0] - NWP
+ // Peripheral present bits
+ // NWP_ACSPI_PP [0:0]
+
+#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG3 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \
+ 0xFFFFFFFF // This is ROW_17[15:0] &
+ // ROW_16[31:16] of FUSEFARM :
+ // [31:16] - TEST_TAP_KEY(15:0)
+ // [15:0] - Reserved
+
+#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_MEM_RET_CFG register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \
+ 0x00000001 // 1 - Soft-compile memories in
+ // WTOP can be turned-off during
+ // WTOP-sleep mode ; 0 -
+ // Soft-compile memories in WTOP
+ // must be kept on during WTOP-sleep
+ // mode.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \
+ 0x007FFFFF // TBD
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \
+ 0x000FFFFF // TBD
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \
+ 0x00000018
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \
+ 0x00000004
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \
+ 0x00000002
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \
+ 0x00000001 // TBD
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \
+ 0x00000001 // 1 - Enable switching of sysclk
+ // to Coex-clk path ; 0 - Disable
+ // switching of sysclk to Coex-clk
+ // path.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_DCDC_CLK_GEN_CONFIG register.
+//
+//******************************************************************************
+#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the clock for DCDC
+ // (PWM-mode) ; 0 - Disable the
+ // clock for DCDC (PWM-mode)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG4 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \
+ 0x0000FFFF // This corresponds to
+ // ROW_17[31:16] of the FUSEFARM :
+ // [15:0] : TEST_TAP_KEY(31:16)
+
+#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG5 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \
+ 0xFFFFFFFF // Corresponds to ROW_18 of
+ // FUSEFARM. [29:0] -
+ // MEMSS_COLUMN_SEL_LSW ; [30:30] -
+ // WLAN GEM DISABLE ; [31:31] -
+ // SERIAL WIRE JTAG SELECT
+
+#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG6 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \
+ 0x0000FFFF // Corresponds to ROW_19[15:0] of
+ // FUSEFARM. [15:0] :
+ // MEMSS_COLUMN_SEL_MSW
+
+#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG7 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_20[15:0] &
+ // ROW_19[31:16] of FUSEFARM.
+ // FLASH_REGION0
+
+#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG8 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_21[15:0] &
+ // ROW_20[31:16] of FUSEFARM.
+ // FLASH_REGION1
+
+#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG9 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_22[15:0] &
+ // ROW_21[31:16] of FUSEFARM.
+ // FLASH_REGION2
+
+#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG10 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_23[15:0] &
+ // ROW_22[31:16] of FUSEFARM.
+ // FLASH_REGION3
+
+#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG11 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_24[15:0] &
+ // ROW_23[31:16] of FUSEFARM.
+ // FLASH_DESCRIPTOR
+
+#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG0 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \
+ 0xFFFFFFFF // Corresponds to bits [191:160] of
+ // the FUSEFARM. This is ROW_5 of
+ // FUSEFARM [191:160] : [31:0] :
+ // DIE_ID0 [31:0] : DEVX [11:0] DEVY
+ // [23:12] DEVWAF [29:24] DEV_SPARE
+ // [31:30]
+
+#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG1 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \
+ 0xFFFFFFFF // Corresponds to bits [223:192] of
+ // the FUSEFARM. This is ROW_6 of
+ // FUSEFARM :- DEVLOT [23:0] DEVFAB
+ // [28:24] DEVFABBE [31:29]
+
+#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG2 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \
+ 0xFFFFFFFF // Corresponds to bits [255:224] of
+ // the FUSEFARM. This is ROW_7 of
+ // FUSEFARM:- DEVDESREV[4:0]
+ // Memrepair[5:5] MakeDefined[16:6]
+ // CHECKSUM[30:17] Reserved :
+ // [31:31]
+
+#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG3 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \
+ 0xFFFFFFFF // Corresponds to bits [287:256] of
+ // the FUSEFARM. This is ROW_8 of
+ // FUSEFARM :- DIEID0 - DEVREG
+ // [31:0]
+
+#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG4 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \
+ 0xFFFFFFFF // Corresponds to bits [319:288] of
+ // the FUSEFARM. This is ROW_9 of
+ // FUSEFARM :- [7:0] - VBATMON ;
+ // [13:8] - BUFF_OFFSET ; [15:15] -
+ // DFT_GXG ; [14:14] - DFT_GLX ;
+ // [19:16] - PHY ROM Version ;
+ // [23:20] - MAC ROM Version ;
+ // [27:24] - NWP ROM Version ;
+ // [31:28] - APPS ROM Version
+
+#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SS_OVERRIDES_reserved_M \
+ 0xFFFFFC00
+
+#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \
+ 0x00000200
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \
+ 0x00000100
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \
+ 0x00000080
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \
+ 0x00000040
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \
+ 0x00000020
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \
+ 0x00000010
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \
+ 0x00000008
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \
+ 0x00000002
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SS_OVERRIDES_reserved_M \
+ 0xFFFFFC00
+
+#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \
+ 0x00000200
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \
+ 0x00000100
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \
+ 0x00000080
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \
+ 0x00000040
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \
+ 0x00000020
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \
+ 0x00000010
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \
+ 0x00000008
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \
+ 0x00000002
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SHARED_SS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \
+ 0xFFFFFF00
+
+#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \
+ 0x00000080
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \
+ 0x00000040
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \
+ 0x00000020
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \
+ 0x00000010
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \
+ 0x00000008
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \
+ 0x00000004
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \
+ 0x00000002
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \
+ 0xFFFFFF00
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \
+ 0x00000080
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \
+ 0x00000040
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \
+ 0x00000020
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \
+ 0x00000010
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \
+ 0x00000008
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \
+ 0x00000002
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TOP_DIE_FSM_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \
+ 0xFFFFF000
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \
+ 0x00000800
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \
+ 0x00000400
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \
+ 0x00000200
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \
+ 0x00000100
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \
+ 0x00000080
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \
+ 0x00000040
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \
+ 0x00000020
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \
+ 0x00000010
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \
+ 0x00000008
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \
+ 0x00000002
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \
+ 0xFFF00000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \
+ 0x00080000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \
+ 0x00040000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \
+ 0x00020000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \
+ 0x00010000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \
+ 0x0000FC00
+
+#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \
+ 0x00000200
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \
+ 0x00000100
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \
+ 0x000000F0
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \
+ 0x0000000F
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \
+ 0xFFC00000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \
+ 0x00200000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \
+ 0x00100000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \
+ 0x00080000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \
+ 0x00040000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \
+ 0x00020000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \
+ 0x00010000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \
+ 0x0000FF00
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \
+ 0x000000FF
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WELP_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFFFC
+
+#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2
+#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFFFC
+
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCSPI_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFF00
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \
+ 0x00000080
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \
+ 0x00000040
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \
+ 0x00000020
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \
+ 0x00000010
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \
+ 0x00000008
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \
+ 0x00000004
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SSDIO_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFFFC
+
+#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2
+#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \
+ 0x00000001
+
+
+
+
+#endif // __HW_GPRCM_H__
diff --git a/cc3200/hal/inc/hw_hib1p2.h b/cc3200/hal/inc/hw_hib1p2.h
new file mode 100644
index 0000000000..95e25ff7cf
--- /dev/null
+++ b/cc3200/hal/inc/hw_hib1p2.h
@@ -0,0 +1,1750 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIB1P2_H__
+#define __HW_HIB1P2_H__
+
+//*****************************************************************************
+//
+// The following are defines for the HIB1P2 register offsets.
+//
+//*****************************************************************************
+#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \
+ 0x00000000
+
+#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \
+ 0x00000004
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \
+ 0x00000008
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \
+ 0x0000000C
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \
+ 0x00000010
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \
+ 0x00000014
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \
+ 0x00000018
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \
+ 0x0000001C
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \
+ 0x00000020
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \
+ 0x00000024
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \
+ 0x00000028
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \
+ 0x00000064
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \
+ 0x00000068
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \
+ 0x0000006C
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \
+ 0x00000070
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \
+ 0x00000074
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \
+ 0x00000078
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \
+ 0x0000007C
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \
+ 0x00000080
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \
+ 0x00000084
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \
+ 0x00000088
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \
+ 0x0000008C
+
+#define HIB1P2_O_PMBIST_PARAMETERS0 \
+ 0x00000094
+
+#define HIB1P2_O_PMBIST_PARAMETERS1 \
+ 0x00000098
+
+#define HIB1P2_O_PMBIST_PARAMETERS2 \
+ 0x0000009C
+
+#define HIB1P2_O_PMBIST_PARAMETERS3 \
+ 0x000000A0
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \
+ 0x000000A4
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \
+ 0x000000A8
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \
+ 0x000000AC
+
+#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \
+ 0x000000B0
+
+#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \
+ 0x000000B4
+
+#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \
+ 0x000000B8
+
+#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \
+ 0x000000BC
+
+#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \
+ 0x000000C0
+
+#define HIB1P2_O_CM_OSC_16M_CONFIG \
+ 0x000000C4
+
+#define HIB1P2_O_SOP_SENSE_VALUE \
+ 0x000000C8
+
+#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \
+ 0x000000CC
+
+#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \
+ 0x000000D0
+
+#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \
+ 0x000000D4
+
+#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \
+ 0x000000D8
+
+#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \
+ 0x000000DC
+
+#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \
+ 0x000000E0
+
+#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \
+ 0x000000E4
+
+#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \
+ 0x000000E8
+
+#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \
+ 0x000000EC
+
+#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \
+ 0x000000F0
+
+#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \
+ 0x000000F4
+
+#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \
+ 0x000000F8
+
+#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \
+ 0x000000FC
+
+#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \
+ 0x00000100
+
+#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \
+ 0x00000104
+
+#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \
+ 0x00000108
+
+#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \
+ 0x0000010C
+
+#define HIB1P2_O_CM_SPARE 0x00000110
+#define HIB1P2_O_PORPOL_SPARE 0x00000114
+#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \
+ 0x00000118
+
+#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \
+ 0x0000011C
+
+#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \
+ 0x00000120
+
+#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \
+ 0x00000124
+
+#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \
+ 0x00000128
+
+#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \
+ 0x0000012C
+
+#define HIB1P2_O_MEM_HIB_FSM_DEBUG \
+ 0x00000130
+
+#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \
+ 0x00000134
+
+#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \
+ 0x00000138
+
+#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \
+ 0x0000013C
+
+#define HIB1P2_O_MEM_CM_TEST_MODE \
+ 0x00000140
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \
+ 0xC0000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \
+ 0x30000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \
+ 0x08000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \
+ 0x04000000 // FSM Override value for SLDO_EN :
+ // Applicable only when bit [4] of
+ // this register is set to 1.
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \
+ 0x02000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \
+ 0x01000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \
+ 0x00FC0000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \
+ 0x0003FF00
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \
+ 0x00000080 // FSM Override value for
+ // SKA_LDO_EN : Applicable only when
+ // bit [3] of this register is set
+ // to 1.
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \
+ 0x00000040
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \
+ 0x00000020
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \
+ 0x00000010 // When 1, bit[26] of this register
+ // will be used as SLDO_EN
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \
+ 0x00000008 // When 1, bit[26] of this register
+ // will be used as SKA_LDO_EN
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \
+ 0x00000007
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \
+ 0xFFC00000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \
+ 0x003F0000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \
+ 0x00008000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \
+ 0x00004000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \
+ 0x00002000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \
+ 0x00001000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \
+ 0x00000800
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \
+ 0x000007FF
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \
+ 0x80000000 // Override value for DCDC_DIG_EN :
+ // Applicable only when bit [31] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \
+ 0x40000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \
+ 0x20000000 // Override value for
+ // DCDC_DIG_EN_SUBREG_1P8V :
+ // Applicable only when bit [30] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \
+ 0x10000000 // Override value for
+ // DCDC_DIG_EN_SUBREG_1P2V :
+ // Applicable only when bit [29] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \
+ 0x08000000 // Override value for
+ // DCDC_DIG_SLP_EN : Applicable only
+ // when bit [28] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \
+ 0x04000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \
+ 0x02000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \
+ 0x01000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \
+ 0x00800000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \
+ 0x00400000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \
+ 0x003F0000 // Override value for
+ // DCDC_DIG_VTRIM : Applicable only
+ // when bit [27] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1.
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \
+ 0x0000C000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \
+ 0x00003000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \
+ 0x00000800
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \
+ 0x00000780
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \
+ 0x00000078
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3
+#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \
+ 0x00000007
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \
+ 0x80000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \
+ 0x40000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \
+ 0x20000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \
+ 0x10000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \
+ 0x08000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \
+ 0x04000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \
+ 0x02000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \
+ 0x01FFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS2 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \
+ 0xF0000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \
+ 0x0F000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \
+ 0x00C00000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \
+ 0x00300000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \
+ 0x000F0000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16
+#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \
+ 0x00008000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \
+ 0x00007800
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \
+ 0x00000400
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \
+ 0x000003FC
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \
+ 0x00000002
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \
+ 0x00000001 // Override value for
+ // DCDC_DIG_COT_EN : Applicable only
+ // when bit[26] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS3 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \
+ 0x80000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \
+ 0x7F800000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \
+ 0x00400000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \
+ 0x00200000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \
+ 0x001FE000 // Override value for
+ // DCDC_DIG_ILIM_TRIM : Applicable
+ // only when bit [25] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \
+ 0x00001800
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \
+ 0x00000400
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \
+ 0x00000200
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \
+ 0x000001F0
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \
+ 0x0000000C
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \
+ 0x00000002
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS4 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \
+ 0x80000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \
+ 0x40000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \
+ 0x20000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \
+ 0x1FFFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS5 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS6 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \
+ 0x80000000 // Override for ANA DCDC EN
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \
+ 0x40000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \
+ 0x20000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \
+ 0x10000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \
+ 0x08000000 // Override for ANA DCDC PWM
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \
+ 0x04000000 // Override for ANA DCDC SLP
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \
+ 0x02000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \
+ 0x01000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \
+ 0x00800000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \
+ 0x00400000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \
+ 0x00200000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \
+ 0x001E0000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \
+ 0x00018000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \
+ 0x00006000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \
+ 0x00001000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \
+ 0x00000F00
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \
+ 0x000000F0
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \
+ 0x0000000F
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \
+ 0xF0000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \
+ 0x0C000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \
+ 0x03000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \
+ 0x00F00000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \
+ 0x000F0000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \
+ 0x00008000 // (Earlier SHOOTTHRU CTRL)
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \
+ 0x00004000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \
+ 0x00003E00
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \
+ 0x00000100
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \
+ 0x00000080
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \
+ 0x00000060
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \
+ 0x00000010
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \
+ 0x0000000C
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2
+#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \
+ 0x00000003
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS16 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \
+ 0x00200000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \
+ 0x00100000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \
+ 0x000FF000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \
+ 0x00000C00
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \
+ 0x00000200
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \
+ 0x00000100
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \
+ 0x000000F8
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \
+ 0x00000006
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS17 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \
+ 0x80000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \
+ 0x40000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \
+ 0x3FFFFFFF
+
+#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS18 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS19 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \
+ 0x40000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \
+ 0x20000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \
+ 0x18000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \
+ 0x04000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \
+ 0x02000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \
+ 0x01000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \
+ 0x00800000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \
+ 0x00400000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \
+ 0x003C0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \
+ 0x00020000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \
+ 0x00010000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \
+ 0x00008000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \
+ 0x00004000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \
+ 0x00002000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \
+ 0x00001000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \
+ 0x00000800
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \
+ 0x00000400
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \
+ 0x00000200
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \
+ 0x000001E0
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \
+ 0x0000001E
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \
+ 0xF0000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \
+ 0x0F000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \
+ 0x00F00000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \
+ 0x000F0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \
+ 0x0000F000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \
+ 0x00000F00
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \
+ 0x000000C0
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \
+ 0x00000030
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \
+ 0x0000000C
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \
+ 0x00000003
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \
+ 0xC0000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \
+ 0x30000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \
+ 0x0C000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \
+ 0x03000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \
+ 0x00800000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \
+ 0x00400000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \
+ 0x00200000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \
+ 0x001F0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \
+ 0x0000F000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \
+ 0x00000800
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \
+ 0x00000400
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \
+ 0x000003FC
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \
+ 0x00000003
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \
+ 0x40000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \
+ 0x20000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \
+ 0x1F000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \
+ 0x00E00000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \
+ 0x001C0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \
+ 0x0003C000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \
+ 0x00003C00
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \
+ 0x00000300
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \
+ 0x00000080
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \
+ 0x00000040
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \
+ 0x00000020
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \
+ 0x0000001F
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \
+ 0x40000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \
+ 0x3FFFFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \
+ 0x80000000
+
+#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \
+ 0x7FFFF800
+
+#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11
+#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \
+ 0x000007FF
+
+#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \
+ 0xFFFF0000
+
+#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16
+#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \
+ 0x00008000
+
+#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \
+ 0x00007FFF
+
+#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS2 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS3 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \
+ 0xFFFF0000
+
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \
+ 0x0000E000
+
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13
+#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \
+ 0x00001000
+
+#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \
+ 0x00000FFF
+
+#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \
+ 0x7C000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \
+ 0x03E00000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \
+ 0x001FFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \
+ 0xFFFFFFC0
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \
+ 0x00000020
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \
+ 0x00000010
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \
+ 0x00000008
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \
+ 0x00000004
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \
+ 0x00000002
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \
+ 0xFFFFFFFC
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \
+ 0x00000002
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_VTRIM_CFG register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \
+ 0xFF000000
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \
+ 0x00FC0000
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \
+ 0x0003F000
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \
+ 0x00000FC0
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \
+ 0x0000003F
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \
+ 0xFFFF8000
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \
+ 0x00007000
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \
+ 0x00000E00
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \
+ 0x000001C0
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \
+ 0x00000038
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \
+ 0x00000007
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \
+ 0xFFFFFFF8
+
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \
+ 0x00000007
+
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register.
+//
+//******************************************************************************
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \
+ 0xFFFFFFC0
+
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \
+ 0x00000038
+
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \
+ 0x00000007
+
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register.
+//
+//******************************************************************************
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \
+ 0xFFFFFFF8
+
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \
+ 0x00000007
+
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_CM_OSC_16M_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \
+ 0xFFFC0000
+
+#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18
+#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \
+ 0x00020000
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \
+ 0x00010000
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \
+ 0x0000FC00
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \
+ 0x000003F0
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \
+ 0x00000008
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \
+ 0x00000007
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SOP_SENSE_VALUE register.
+//
+//******************************************************************************
+#define HIB1P2_SOP_SENSE_VALUE_reserved_M \
+ 0xFFFFFF00
+
+#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8
+#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \
+ 0x000000FF
+
+#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \
+ 0x0000FFFF
+
+#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \
+ 0xFF800000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \
+ 0x00400000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \
+ 0x003FC000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \
+ 0x00002000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \
+ 0x00001FC0
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \
+ 0x00000020
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \
+ 0x0000001F
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \
+ 0xFFFFFFFF // Corresponds to ROW_12 of
+ // FUSEFARM. [7:0] :
+ // DCDC_DIG_ILIM_TRIM_LOWV(7:0)
+ // [15:8] :
+ // DCDC_ANA_ILIM_TRIM_LOWV(7:0)
+ // [23:16] :
+ // DCDC_FLASH_ILIM_TRIM_LOWV(7:0)
+ // [24:24] : DTHE SHA DISABLE
+ // [25:25] : DTHE DES DISABLE
+ // [26:26] : DTHE AES DISABLE
+ // [31:27] : HD_BG_RTRIM (4:0)
+
+#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \
+ 0xFFFFFFFF // Corresponds to ROW_13 of the
+ // FUSEFARM. [7:0] : HD_BG_MAG_TRIM
+ // (7:0) [14:8] : HD_BG_TEMP_TRIM
+ // (6:0) [15:15] : GREYOUT ENABLE
+ // DUTY CYCLING [31:16] :
+ // Reserved/Checksum
+
+#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_POR_TEST_CTRL register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \
+ 0xFFFFFF00
+
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \
+ 0x000000FF
+
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \
+ 0xFFFF0000
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \
+ 0x0000FF00
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \
+ 0x000000FE
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \
+ 0xFFF00000
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \
+ 0x000FFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \
+ 0xFFFFFE00
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \
+ 0x00000100
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \
+ 0x000000FC
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \
+ 0x00000002
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \
+ 0xFFFF0000
+
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \
+ 0x0000FFFF
+
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \
+ 0xFFFF0000
+
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \
+ 0x0000FFFF
+
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \
+ 0xFFFFF000
+
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \
+ 0x00000FFF
+
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register.
+//
+//******************************************************************************
+#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \
+ 0xFF000000
+
+#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24
+#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \
+ 0x00FF0000
+
+#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16
+#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \
+ 0x0000FFFF
+
+#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PORPOL_SPARE register.
+//
+//******************************************************************************
+#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \
+ 0x00000002
+
+#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \
+ 0x00000002
+
+#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_HIB_FSM_DEBUG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \
+ 0x00000700
+
+#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8
+#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4
+#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \
+ 0x000FFFFF
+
+#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \
+ 0x00000002
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_CM_TEST_MODE register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \
+ 0x00000001
+
+
+
+
+#endif // __HW_HIB1P2_H__
diff --git a/cc3200/hal/inc/hw_hib3p3.h b/cc3200/hal/inc/hw_hib3p3.h
new file mode 100644
index 0000000000..9701689165
--- /dev/null
+++ b/cc3200/hal/inc/hw_hib3p3.h
@@ -0,0 +1,1138 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIB3P3_H__
+#define __HW_HIB3P3_H__
+
+//*****************************************************************************
+//
+// The following are defines for the HIB3P3 register offsets.
+//
+//*****************************************************************************
+#define HIB3P3_O_MEM_HIB_REQ 0x00000000
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \
+ 0x00000004
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \
+ 0x00000008
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \
+ 0x0000000C
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \
+ 0x00000010
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \
+ 0x00000014
+
+#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \
+ 0x00000018
+
+#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \
+ 0x0000001C
+
+#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \
+ 0x00000020
+
+#define HIB3P3_O_MEM_INT_OSC_CONF \
+ 0x0000002C
+
+#define HIB3P3_O_MEM_XTAL_OSC_CONF \
+ 0x00000034
+
+#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \
+ 0x00000038
+
+#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \
+ 0x0000003C
+
+#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \
+ 0x00000040
+
+#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \
+ 0x00000044
+
+#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050
+#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \
+ 0x00000054
+
+#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \
+ 0x00000058
+
+#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \
+ 0x0000005C
+
+#define HIB3P3_O_MEM_HIB_UART_CONF \
+ 0x00000400
+
+#define HIB3P3_O_MEM_GPIO_WAKE_EN \
+ 0x00000404
+
+#define HIB3P3_O_MEM_GPIO_WAKE_CONF \
+ 0x00000408
+
+#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \
+ 0x0000040C
+
+#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \
+ 0x00000410
+
+#define HIB3P3_O_MEM_JTAG_CONF 0x00000414
+#define HIB3P3_O_MEM_HIB_REG0 0x00000418
+#define HIB3P3_O_MEM_HIB_REG1 0x0000041C
+#define HIB3P3_O_MEM_HIB_REG2 0x00000420
+#define HIB3P3_O_MEM_HIB_REG3 0x00000424
+#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \
+ 0x0000045C
+
+#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \
+ 0x00000460
+
+#define HIB3P3_O_MEM_HIB_MISC_CONFIG \
+ 0x00000464
+
+#define HIB3P3_O_MEM_HIB_WAKE_STATUS \
+ 0x00000468
+
+#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \
+ 0x0000046C
+
+#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \
+ 0x00000470
+
+#define HIB3P3_O_HIBANA_SPARE_LOWV \
+ 0x00000474
+
+#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478
+#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \
+ 0x0000047C
+
+#define HIB3P3_O_HIB_COMP_TRIM 0x00000480
+#define HIB3P3_O_HIB_EN_TS 0x00000484
+#define HIB3P3_O_HIB_1P8V_DET_EN \
+ 0x00000488
+
+#define HIB3P3_O_HIB_VBAT_MON_EN \
+ 0x0000048C
+
+#define HIB3P3_O_HIB_NHIB_ENABLE \
+ 0x00000490
+
+#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \
+ 0x00000494
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REQ register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REQ_reserved_M \
+ 0xFFFFFE00
+
+#define HIB3P3_MEM_HIB_REQ_reserved_S 9
+#define HIB3P3_MEM_HIB_REQ_NU1_M \
+ 0x000001FC
+
+#define HIB3P3_MEM_HIB_REQ_NU1_S 2
+#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \
+ 0x00000002 // 1 - Specifies that the Hiberante
+ // mode is without clocks ; 0 -
+ // Specified that the Hibernate mode
+ // is with clocks This register will
+ // be reset during Hibernate
+ // -WO-Clks mode (but not during
+ // Hibernate-W-Clks mode).
+
+#define HIB3P3_MEM_HIB_REQ_mem_hib_req \
+ 0x00000001 // 1 - Request for hibernate mode
+ // (This is an auto-clear bit) ; 0 -
+ // Donot request for hibernate mode
+ // This register will be reset
+ // during Hibernate -WO-Clks mode
+ // (but not during Hibernate-W-Clks
+ // mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \
+ 0x00000001 // 1 - Enable the RTC timer to
+ // start running ; 0 - Keep the RTC
+ // timer disabled This register will
+ // be reset during Hibernate
+ // -WO-Clks mode (but not during
+ // Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \
+ 0x00000001 // 1 - Reset the RTC timer ; 0 -
+ // Donot reset the RTC timer. This
+ // is an auto-clear bit. This
+ // register will be reset during
+ // Hibernate -WO-Clks mode (but not
+ // during Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \
+ 0x00000001 // 1 - Latch the running RTC timer
+ // into local registers. After
+ // programming this bit to 1, the
+ // F/w can read the latched RTC
+ // timer values from
+ // MEM_HIB_RTC_TIMER_LSW and
+ // MEM_HIB_RTC_TIMER_MSW. Before the
+ // F/w (APPS or NWP) wants to read
+ // the RTC-Timer, it has to program
+ // this bit to 1, then only read the
+ // MSW and LSW values. This is an
+ // auto-clear bit. This register
+ // will be reset during Hibernate
+ // -WO-Clks mode (but not during
+ // Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \
+ 0xFFFFFFFF // Lower 32b value of the latched
+ // RTC-Timer.
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \
+ 0x0000FFFF // Upper 32b value of the latched
+ // RTC-Timer.
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \
+ 0x00000001 // 1 - Enable the RTC timer based
+ // wakeup during Hibernate mode ; 0
+ // - Disable the RTC timer based
+ // wakeup during Hibernate mode This
+ // register will be reset during
+ // Hibernate-WO-Clks mode (but not
+ // during Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \
+ 0xFFFFFFFF // Configuration for RTC-Timer
+ // Wakeup (Lower 32b word)
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \
+ 0x0000FFFF // Configuration for RTC-Timer
+ // Wakeup (Upper 16b word)
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_INT_OSC_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16
+#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \
+ 0x00008000 // 1 - Internal 32kHz Oscillator is
+ // valid ; 0 - Internal 32k
+ // oscillator clk is not valid
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \
+ 0x00007E00
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \
+ 0x00000100 // When 1, the INT_32K_OSC_EN comes
+ // from bit [0] of this register,
+ // else comes from the FSM. This
+ // register will be reset during
+ // Hibernate-WO-Clks mode (but not
+ // during Hibernate-W-Clks mode)
+
+#define HIB3P3_MEM_INT_OSC_CONF_NU1 \
+ 0x00000080
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \
+ 0x0000007E
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \
+ 0x00000001 // Override value for INT_OSC_EN.
+ // Applicable only when bit [3] of
+ // this register is set to 1.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_XTAL_OSC_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \
+ 0xFFF00000
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \
+ 0x00080000 // When 1, the SLICER_EN comes from
+ // bit [10] of this register, else
+ // comes from the FSM.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \
+ 0x00040000 // When 1, the XTAL_EN comes from
+ // bit [0] of this register, else
+ // comes from the FSM.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \
+ 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL
+ // Clk is yet to be valid.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \
+ 0x0001F800
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \
+ 0x00000400 // SLICER_EN Override value :
+ // Applicable only when bit [19] of
+ // this register is set to 1.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \
+ 0x00000380
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \
+ 0x00000070
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \
+ 0x00000008
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \
+ 0x00000006
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \
+ 0x00000001 // XTAL_EN Override value :
+ // Applicable only when bit [18] of
+ // this register is set to 1.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_BGAP_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \
+ 0xFFF80000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \
+ 0x00040000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \
+ 0x0001C000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \
+ 0x00001000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \
+ 0x00000800
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \
+ 0x00000400
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \
+ 0x000003FF
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_BGAP_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \
+ 0xE0000000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \
+ 0x1F000000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \
+ 0x00000008
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \
+ 0x00000004
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \
+ 0x00000002
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_DETECTION_STATUS register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \
+ 0xFFFFFF80
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \
+ 0x00000040 // 1 - 1.8 V supply forced mode.
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \
+ 0x00000004 // 1 - 3.3 V supply forced mode for
+ // Flash supply
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \
+ 0x00000002 // 1 - Forced clock mode
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \
+ 0x00000001 // 1 - XTAL clock mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_MISC_CONTROLS register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \
+ 0xFFFFF800
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \
+ 0x00000400
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \
+ 0x00000200
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \
+ 0x000001C0
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \
+ 0x00000020
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \
+ 0x00000010
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_CONFIG register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \
+ 0xFF000000
+
+#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \
+ 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD
+ // for digital path (SHARED4) ; 0 -
+ // Disable VDD_FLASH_INDP_PAD for
+ // digital path (SHARED4) ; Before
+ // programming this bit to 1, ensure
+ // that the device is in FORCED 3.3
+ // supply Mode, which can be
+ // inferred from the register :
+ // MEM_HIB_DETECTION_STATUS : 0x0040
+
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \
+ 0x00040000 // 1 - Enable the
+ // VDD_FB_GPIO_MUX_PAD for digital
+ // path (SHARED3) ; 0 - Disable the
+ // VDD_FB_GPIO_MUX_PAD for digital
+ // path (SHARED3) ; This pin can be
+ // used only in modes other than
+ // SOP("111")
+
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \
+ 0x00020000 // 1 - Enable the PM_TEST_PAD for
+ // digital GPIO path (SHARED2) ; 0 -
+ // Disable the PM_TEST_PAD for
+ // digital GPIO path (SHARED2) This
+ // pin can be used for digital only
+ // in modes other then SOP-111
+
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \
+ 0x00010000 // 1 - Enable the XTAL_N pin
+ // digital GPIO path (SHARED1); 0 -
+ // Disable the XTAL_N pin digital
+ // GPIO path (SHARED1). Before
+ // programming this bit to 1, ensure
+ // that the device is in FORCED CLK
+ // Mode, which can inferred from the
+ // register :
+ // MEM_HIB_DETECTION_STATUS :
+ // 0x0040.
+
+#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \
+ 0x00000100 // 1 - Enable the XTAL Clock ; 0 -
+ // Donot enable the XTAL Clock. This
+ // bit has to be programmed to 1 (by
+ // APPS Devinit F/w), during exit
+ // from OFF or Hib_wo_clks modes,
+ // after checking if the slow_clk
+ // mode is XTAL_CLK mode. Once
+ // enabled the XTAL will be disabled
+ // only after entering HIB_WO_CLKS
+ // mode. This register will be reset
+ // during Hibernate -WO-Clks mode
+ // (but not during Hibernate-W-Clks
+ // mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \
+ 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0
+ // - Disable the HIB RTC - IRQ
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \
+ 0xFFFFFFFF // Configuration for LSW of the
+ // RTC-Timestamp at which interrupt
+ // need to be generated
+
+#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \
+ 0x0000FFFF // Configuration for MSW of thr
+ // RTC-Timestamp at which the
+ // interrupt need to be generated
+
+#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_UART_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1
+#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \
+ 0x00000001 // 1 - Enable the UART-Autonomous
+ // mode wakeup during Hibernate mode
+ // ; This is an auto-clear bit, once
+ // programmed to 1, it will latched
+ // into an internal register which
+ // remain asserted until the
+ // Hib-wakeup is initiated.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_GPIO_WAKE_EN register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \
+ 0xFFFFFF00
+
+#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8
+#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \
+ 0x000000FF // 1 - Enable the GPIO-Autonomous
+ // mode wakeup during Hibernate mode
+ // ; This is an auto-clear bit, once
+ // programmed to 1, it will latched
+ // into an internal register which
+ // remain asserted until the
+ // Hib-wakeup is initiated.
+
+#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_GPIO_WAKE_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16
+#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \
+ 0x0000FFFF // Configuration to say whether the
+ // GPIO wakeup has to happen on
+ // Level0 or falling-edge for the
+ // given group. “00†– Level0 “01†–
+ // Level1 “10â€- Fall-edge “11â€-
+ // Rise-edge [1:0] – Conf for GPIO0
+ // [3:2] – Conf for GPIO1 [5:4] –
+ // Conf for GPIO2 [7:6] – Conf for
+ // GPIO3 [9:8] – Conf for GPIO4
+ // [11:10] – Conf for GPIO5 [13:12]
+ // – Conf for GPIO6
+
+#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \
+ 0x00000004 // 1 - Override the OEN33 and RET33
+ // controls of GPIOs during
+ // SOP-Bootdebug mode ; 0 - Donot
+ // override the OEN33 and RET33
+ // controls of GPIOs during
+ // SOP-Bootdebug mode
+
+#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \
+ 0x00000002
+
+#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \
+ 0x00000004 // 1 - Override the OEN33 and RET33
+ // controls of UART NRTS GPIO during
+ // SOP-Bootdebug mode ; 0 - Donot
+ // override the OEN33 and RET33
+ // controls of UART NRTS GPIO during
+ // SOP-Bootdebug mode
+
+#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \
+ 0x00000002
+
+#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_JTAG_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \
+ 0x00000200
+
+#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \
+ 0x00000100
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \
+ 0x00000008
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \
+ 0x00000004
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \
+ 0x00000002
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG0 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG1 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG2 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG3 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \
+ 0xFFFF0000 // Configuration for the number of
+ // slow-clks between de-assertion of
+ // EN_BG_3P3V to assertion of
+ // EN_BG_3P3V
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \
+ 0x00008000
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \
+ 0x00006000 // Configuration for the number of
+ // slow-clks between assertion of
+ // EN_COMP_3P3V and assertion of
+ // EN_COMP_LATCH_3P3V
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \
+ 0x00001800 // Configuration for the number of
+ // slow-clks between assertion of
+ // (EN_CAP_SW_3P3V,EN_COMP_REF) and
+ // assertion of (EN_COMP_3P3V)
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \
+ 0x00000600 // Configuration for the number of
+ // slow-clks between assertion of
+ // (EN_BG_3P3V) and assertion of
+ // (EN_CAP_SW_3P3V,
+ // EN_COMP_REF_3P3V)
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \
+ 0x00000100
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \
+ 0x00000080 // 1 - EN_VBOK4BG_REF comes from
+ // bit[10] of the register
+ // MEM_BGAP_PARAMETERS0 [0x0038]. 0
+ // - EN_VBOK4BG_REF comes directly
+ // from the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \
+ 0x00000040 // 1 - EN_VBOK4BG comes from
+ // bit[11] of the register
+ // MEM_BGAP_PARAMETERS0 [0x0038]. 0
+ // - EN_VBOK4BG comes directly from
+ // the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \
+ 0x00000020 // 1 - EN_V2I comes from bit[2] of
+ // the register MEM_BGAP_PARAMETERS1
+ // [0x003C]. 0 - EN_V2I comes
+ // directly from the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \
+ 0x00000010 // 1 - EN_POR_COMP_REF comes from
+ // bit[9] of the register
+ // MEM_HIB_MISC_CONTROLS [0x0044]. 0
+ // - EN_POR_COMP_REF comes directly
+ // from the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \
+ 0x00000008 // 1 - EN_POR_COMP comes from
+ // bit[10] of the register
+ // MEM_HIB_MISC_CONTROLS [0x044]. 0
+ // - EN_POR_COMP comes directly from
+ // the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \
+ 0x00000004 // 1 - EN_CAP_SW comes from bit[1]
+ // of the register
+ // MEM_BGAP_PARAMETERS1 [0x003C]. 0
+ // - EN_CAP_SW comes directly from
+ // Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \
+ 0x00000002 // 1 - EN_BGAP comes from bit[0] of
+ // the register MEM_BGAP_PARAMETERS1
+ // [0x003C]. 0 - EN_BGAP comes
+ // directly from Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \
+ 0x0000C000 // Configuration for number of
+ // slow-clks between de-assertion of
+ // EN_COMP_LATCH and assertion of
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \
+ 0x00003000 // Configuration for number of
+ // slow-clks between assertion of
+ // EN_COMP_REF to assertion of
+ // EN_COMP during HIB-Exit
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \
+ 0x00000C00 // TBD
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \
+ 0x00000300 // Configuration in number of
+ // slow-clks between assertion of
+ // (EN_BGAP_3P3V, EN_CAP_SW_3P3V,
+ // EN_ACT_IREF_3P3V, EN_COMP_REF) to
+ // assertion of EN_COMP_3P3V
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \
+ 0x000000C0 // Configuration in number of
+ // slow-clks between de-assertion of
+ // (EN_COMP_3P3V, EN_COMP_REF_3P3V,
+ // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V)
+ // to deassertion of EN_BGAP_3P3V.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \
+ 0x0000003F
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_MISC_CONFIG register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_WAKE_STATUS register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \
+ 0x0000001E // "0100" - GPIO ; "0010" - RTC ;
+ // "0001" - UART Others - Reserved
+
+#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1
+#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \
+ 0x00000001 // 1 - Wake from Hibernate ; 0 -
+ // Wake from OFF
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \
+ 0x00000007
+
+#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \
+ 0xFFFFF800
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \
+ 0x00000600 // Deassertion of EN_COMP_LATCH_3P3
+ // to deassertion of (EN_COMP_3P3,
+ // EN_COMP_REF_3P3, EN_ACT_IREF_3P3,
+ // EN_CAP_SW_3P3)
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \
+ 0x000001C0 // Assertion of EN_COMP_LATCH_3P3
+ // to deassertion of
+ // EN_COMP_LATCH_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \
+ 0x00000030 // Deassertion of (EN_CAP_SW_3P3,
+ // EN_COMP_REF_3P3, EN_COMP_3P3,
+ // EN_COMP_OUT_LATCH_3P3) to
+ // deassertion of EN_BGAP_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \
+ 0x0000000C // Assertion of EN_COMP_3P3 to
+ // assertion of EN_COMPOUT_LATCH_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \
+ 0x00000003 // Assertion of EN_COMP_3P3 to
+ // assertion of EN_COMPOUT_LATCH_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIBANA_SPARE_LOWV register.
+//
+//******************************************************************************
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \
+ 0xFFC00000
+
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \
+ 0x0001FFFF
+
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_TMUX_CTRL register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_TMUX_CTRL_reserved_M \
+ 0xFFFFFC00
+
+#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10
+#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \
+ 0x000003FF
+
+#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \
+ 0xFFFFF000
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \
+ 0x00000800
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \
+ 0x00000400
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \
+ 0x00000200
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \
+ 0x00000100
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \
+ 0x000000F0
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \
+ 0x0000000F
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_COMP_TRIM register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_COMP_TRIM_reserved_M \
+ 0xFFFFFFF8
+
+#define HIB3P3_HIB_COMP_TRIM_reserved_S 3
+#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \
+ 0x00000007
+
+#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_EN_TS register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_EN_TS_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_HIB_EN_TS_reserved_S 1
+#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_1P8V_DET_EN register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1
+#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_VBAT_MON_EN register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \
+ 0xFFFFFFFC
+
+#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2
+#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \
+ 0x00000002
+
+#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_NHIB_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \
+ 0x00000001
+
+
+
+
+#endif // __HW_HIB3P3_H__
diff --git a/cc3200/hal/inc/hw_i2c.h b/cc3200/hal/inc/hw_i2c.h
new file mode 100644
index 0000000000..17536d3e9c
--- /dev/null
+++ b/cc3200/hal/inc/hw_i2c.h
@@ -0,0 +1,503 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_MSA 0x00000000
+#define I2C_O_MCS 0x00000004
+#define I2C_O_MDR 0x00000008
+#define I2C_O_MTPR 0x0000000C
+#define I2C_O_MIMR 0x00000010
+#define I2C_O_MRIS 0x00000014
+#define I2C_O_MMIS 0x00000018
+#define I2C_O_MICR 0x0000001C
+#define I2C_O_MCR 0x00000020
+#define I2C_O_MCLKOCNT 0x00000024
+#define I2C_O_MBMON 0x0000002C
+#define I2C_O_MBLEN 0x00000030
+#define I2C_O_MBCNT 0x00000034
+#define I2C_O_SOAR 0x00000800
+#define I2C_O_SCSR 0x00000804
+#define I2C_O_SDR 0x00000808
+#define I2C_O_SIMR 0x0000080C
+#define I2C_O_SRIS 0x00000810
+#define I2C_O_SMIS 0x00000814
+#define I2C_O_SICR 0x00000818
+#define I2C_O_SOAR2 0x0000081C
+#define I2C_O_SACKCTL 0x00000820
+#define I2C_O_FIFODATA 0x00000F00
+#define I2C_O_FIFOCTL 0x00000F04
+#define I2C_O_FIFOSTATUS 0x00000F08
+#define I2C_O_OBSMUXSEL0 0x00000F80
+#define I2C_O_OBSMUXSEL1 0x00000F84
+#define I2C_O_MUXROUTE 0x00000F88
+#define I2C_O_PV 0x00000FB0
+#define I2C_O_PP 0x00000FC0
+#define I2C_O_PC 0x00000FC4
+#define I2C_O_CC 0x00000FC8
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//******************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_SA_S 1
+#define I2C_MSA_RS 0x00000001 // Receive not send
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//******************************************************************************
+#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status
+#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status
+#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//******************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
+#define I2C_MDR_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//******************************************************************************
+#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
+#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
+#define I2C_MTPR_TPR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//******************************************************************************
+#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask
+#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt
+ // Mask
+#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask
+#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask
+#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask
+#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask
+#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask
+#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask
+#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//******************************************************************************
+#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt
+ // Status
+#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw
+ // Interrupt Status
+#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw
+ // Interrupt Status
+#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt
+ // Status
+#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt
+ // Status
+#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt
+ // Status
+#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt
+ // Status
+#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt
+ // Status
+#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt
+ // Status
+#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status
+#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
+ // Status
+#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//******************************************************************************
+#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask
+#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask
+#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask
+#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask
+#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask
+#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask
+#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status
+#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status
+#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
+ // Status
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//******************************************************************************
+#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt
+ // Clear
+#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt
+ // Clear
+#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt
+ // Clear
+#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt
+ // Clear
+#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear
+#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear
+#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear
+#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt
+ // Clear
+#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear
+#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear
+#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//******************************************************************************
+#define I2C_MCR_MMD 0x00000040 // Multi-master Disable
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//******************************************************************************
+#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//******************************************************************************
+#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
+#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBLEN register.
+//
+//******************************************************************************
+#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length
+#define I2C_MBLEN_CNTL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBCNT register.
+//
+//******************************************************************************
+#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count
+#define I2C_MBCNT_CNTL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//******************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//******************************************************************************
+#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status
+#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status
+#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
+#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
+#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//******************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//******************************************************************************
+#define I2C_SIMR_IM 0x00000100 // Interrupt Mask
+#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt
+ // Mask
+#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask
+#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//******************************************************************************
+#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status
+#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw
+ // Interrupt Status
+#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw
+ // Interrupt Status
+#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt
+ // Status
+#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt
+ // Status
+#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//******************************************************************************
+#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask
+#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt
+ // Mask
+#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt
+ // Status
+#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt
+ // Status
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//******************************************************************************
+#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask
+#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask
+#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask
+#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear
+#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//******************************************************************************
+#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//******************************************************************************
+#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFODATA register.
+//
+//******************************************************************************
+#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte
+#define I2C_FIFODATA_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
+//
+//******************************************************************************
+#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment
+#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush
+#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable
+#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger
+#define I2C_FIFOCTL_RXTRIG_S 16
+#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment
+#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush
+#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable
+#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger
+#define I2C_FIFOCTL_TXTRIG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register.
+//
+//******************************************************************************
+#define I2C_FIFOSTATUS_RXABVTRIG \
+ 0x00040000 // RX FIFO Above Trigger Level
+
+#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full
+#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty
+#define I2C_FIFOSTATUS_TXBLWTRIG \
+ 0x00000004 // TX FIFO Below Trigger Level
+
+#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full
+#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register.
+//
+//******************************************************************************
+#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3
+#define I2C_OBSMUXSEL0_LN3_S 24
+#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2
+#define I2C_OBSMUXSEL0_LN2_S 16
+#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1
+#define I2C_OBSMUXSEL0_LN1_S 8
+#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0
+#define I2C_OBSMUXSEL0_LN0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register.
+//
+//******************************************************************************
+#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7
+#define I2C_OBSMUXSEL1_LN7_S 24
+#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6
+#define I2C_OBSMUXSEL1_LN6_S 16
+#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5
+#define I2C_OBSMUXSEL1_LN5_S 8
+#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4
+#define I2C_OBSMUXSEL1_LN4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MUXROUTE register.
+//
+//******************************************************************************
+#define I2C_MUXROUTE_LN7ROUTE_M \
+ 0x70000000 // Lane 7 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN7ROUTE_S 28
+#define I2C_MUXROUTE_LN6ROUTE_M \
+ 0x07000000 // Lane 6 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN6ROUTE_S 24
+#define I2C_MUXROUTE_LN5ROUTE_M \
+ 0x00700000 // Lane 5 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN5ROUTE_S 20
+#define I2C_MUXROUTE_LN4ROUTE_M \
+ 0x00070000 // Lane 4 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN4ROUTE_S 16
+#define I2C_MUXROUTE_LN3ROUTE_M \
+ 0x00007000 // Lane 3 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN3ROUTE_S 12
+#define I2C_MUXROUTE_LN2ROUTE_M \
+ 0x00000700 // Lane 2 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN2ROUTE_S 8
+#define I2C_MUXROUTE_LN1ROUTE_M \
+ 0x00000070 // Lane 1 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN1ROUTE_S 4
+#define I2C_MUXROUTE_LN0ROUTE_M \
+ 0x00000007 // Lane 0 output is routed to the
+ // lane pointed to by the offset in
+ // this bit field
+
+#define I2C_MUXROUTE_LN0ROUTE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PV register.
+//
+//******************************************************************************
+#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision
+#define I2C_PV_MAJOR_S 8
+#define I2C_PV_MINOR_M 0x000000FF // Minor Revision
+#define I2C_PV_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//******************************************************************************
+#define I2C_PP_HS 0x00000001 // High-Speed Capable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//******************************************************************************
+#define I2C_PC_HS 0x00000001 // High-Speed Capable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_CC register.
+//
+//******************************************************************************
+
+
+
+#endif // __HW_I2C_H__
diff --git a/cc3200/hal/inc/hw_ints.h b/cc3200/hal/inc/hw_ints.h
new file mode 100644
index 0000000000..6b40193559
--- /dev/null
+++ b/cc3200/hal/inc/hw_ints.h
@@ -0,0 +1,117 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on CC3200.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI 2 // NMI fault
+#define FAULT_HARD 3 // Hard fault
+#define FAULT_MPU 4 // MPU fault
+#define FAULT_BUS 5 // Bus fault
+#define FAULT_USAGE 6 // Usage fault
+#define FAULT_SVCALL 11 // SVCall
+#define FAULT_DEBUG 12 // Debug monitor
+#define FAULT_PENDSV 14 // PendSV
+#define FAULT_SYSTICK 15 // System Tick
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_GPIOA0 16 // GPIO Port S0
+#define INT_GPIOA1 17 // GPIO Port S1
+#define INT_GPIOA2 18 // GPIO Port S2
+#define INT_GPIOA3 19 // GPIO Port S3
+#define INT_UARTA0 21 // UART0 Rx and Tx
+#define INT_UARTA1 22 // UART1 Rx and Tx
+#define INT_I2CA0 24 // I2C controller
+#define INT_ADCCH0 30 // ADC Sequence 0
+#define INT_ADCCH1 31 // ADC Sequence 1
+#define INT_ADCCH2 32 // ADC Sequence 2
+#define INT_ADCCH3 33 // ADC Sequence 3
+#define INT_WDT 34 // Watchdog Timer0
+#define INT_TIMERA0A 35 // Timer 0 subtimer A
+#define INT_TIMERA0B 36 // Timer 0 subtimer B
+#define INT_TIMERA1A 37 // Timer 1 subtimer A
+#define INT_TIMERA1B 38 // Timer 1 subtimer B
+#define INT_TIMERA2A 39 // Timer 2 subtimer A
+#define INT_TIMERA2B 40 // Timer 2 subtimer B
+#define INT_FLASH 45 // FLASH Control
+#define INT_TIMERA3A 51 // Timer 3 subtimer A
+#define INT_TIMERA3B 52 // Timer 3 subtimer B
+#define INT_UDMA 62 // uDMA controller
+#define INT_UDMAERR 63 // uDMA Error
+#define INT_SHA 164 // SHA
+#define INT_AES 167 // AES
+#define INT_DES 169 // DES
+#define INT_MMCHS 175 // SDIO
+#define INT_I2S 177 // McAPS
+#define INT_CAMERA 179 // Camera
+#define INT_NWPIC 187 // Interprocessor communication
+#define INT_PRCM 188 // Power, Reset and Clock Module
+#define INT_SSPI 191 // Shared SPI
+#define INT_GSPI 192 // Generic SPI
+#define INT_LSPI 193 // Link SPI
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS 195 //The above number plus 2?
+
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY 8
+#define NUM_PRIORITY_BITS 3
+
+
+#endif // __HW_INTS_H__
diff --git a/cc3200/hal/inc/hw_mcasp.h b/cc3200/hal/inc/hw_mcasp.h
new file mode 100644
index 0000000000..c27a007797
--- /dev/null
+++ b/cc3200/hal/inc/hw_mcasp.h
@@ -0,0 +1,1706 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_MCASP_H__
+#define __HW_MCASP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the MCASP register offsets.
+//
+//*****************************************************************************
+#define MCASP_O_PID 0x00000000
+#define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register.
+#define MCASP_O_PFUNC 0x00000010
+#define MCASP_O_PDIR 0x00000014
+#define MCASP_O_PDOUT 0x00000018
+#define MCASP_O_PDSET 0x0000001C // The pin data set register
+ // (PDSET) is an alias of the pin
+ // data output register (PDOUT) for
+ // writes only. Writing a 1 to the
+ // PDSET bit sets the corresponding
+ // bit in PDOUT and if PFUNC = 1
+ // (GPIO function) and PDIR = 1
+ // (output) drives a logic high on
+ // the pin.
+#define MCASP_O_PDIN 0x0000001C // The pin data input register
+ // (PDIN) holds the I/O pin state of
+ // each of the McASP pins. PDIN
+ // allows the actual value of the
+ // pin to be read regardless of the
+ // state of PFUNC and PDIR.
+#define MCASP_O_PDCLR 0x00000020 // The pin data clear register
+ // (PDCLR) is an alias of the pin
+ // data output register (PDOUT) for
+ // writes only. Writing a 1 to the
+ // PDCLR bit clears the
+ // corresponding bit in PDOUT and if
+ // PFUNC = 1 (GPIO function) and
+ // PDIR = 1 (output) drives a logic
+ // low on the pin.
+#define MCASP_O_TLGC 0x00000030 // for IODFT
+#define MCASP_O_TLMR 0x00000034 // for IODFT
+#define MCASP_O_TLEC 0x00000038 // for IODFT
+#define MCASP_O_GBLCTL 0x00000044
+#define MCASP_O_AMUTE 0x00000048
+#define MCASP_O_LBCTL 0x0000004C
+#define MCASP_O_TXDITCTL 0x00000050
+#define MCASP_O_GBLCTLR 0x00000060
+#define MCASP_O_RXMASK 0x00000064
+#define MCASP_O_RXFMT 0x00000068
+#define MCASP_O_RXFMCTL 0x0000006C
+#define MCASP_O_ACLKRCTL 0x00000070
+#define MCASP_O_AHCLKRCTL 0x00000074
+#define MCASP_O_RXTDM 0x00000078
+#define MCASP_O_EVTCTLR 0x0000007C
+#define MCASP_O_RXSTAT 0x00000080
+#define MCASP_O_RXTDMSLOT 0x00000084
+#define MCASP_O_RXCLKCHK 0x00000088
+#define MCASP_O_REVTCTL 0x0000008C
+#define MCASP_O_GBLCTLX 0x000000A0
+#define MCASP_O_TXMASK 0x000000A4
+#define MCASP_O_TXFMT 0x000000A8
+#define MCASP_O_TXFMCTL 0x000000AC
+#define MCASP_O_ACLKXCTL 0x000000B0
+#define MCASP_O_AHCLKXCTL 0x000000B4
+#define MCASP_O_TXTDM 0x000000B8
+#define MCASP_O_EVTCTLX 0x000000BC
+#define MCASP_O_TXSTAT 0x000000C0
+#define MCASP_O_TXTDMSLOT 0x000000C4
+#define MCASP_O_TXCLKCHK 0x000000C8
+#define MCASP_O_XEVTCTL 0x000000CC
+#define MCASP_O_CLKADJEN 0x000000D0
+#define MCASP_O_DITCSRA0 0x00000100
+#define MCASP_O_DITCSRA1 0x00000104
+#define MCASP_O_DITCSRA2 0x00000108
+#define MCASP_O_DITCSRA3 0x0000010C
+#define MCASP_O_DITCSRA4 0x00000110
+#define MCASP_O_DITCSRA5 0x00000114
+#define MCASP_O_DITCSRB0 0x00000118
+#define MCASP_O_DITCSRB1 0x0000011C
+#define MCASP_O_DITCSRB2 0x00000120
+#define MCASP_O_DITCSRB3 0x00000124
+#define MCASP_O_DITCSRB4 0x00000128
+#define MCASP_O_DITCSRB5 0x0000012C
+#define MCASP_O_DITUDRA0 0x00000130
+#define MCASP_O_DITUDRA1 0x00000134
+#define MCASP_O_DITUDRA2 0x00000138
+#define MCASP_O_DITUDRA3 0x0000013C
+#define MCASP_O_DITUDRA4 0x00000140
+#define MCASP_O_DITUDRA5 0x00000144
+#define MCASP_O_DITUDRB0 0x00000148
+#define MCASP_O_DITUDRB1 0x0000014C
+#define MCASP_O_DITUDRB2 0x00000150
+#define MCASP_O_DITUDRB3 0x00000154
+#define MCASP_O_DITUDRB4 0x00000158
+#define MCASP_O_DITUDRB5 0x0000015C
+#define MCASP_O_XRSRCTL0 0x00000180
+#define MCASP_O_XRSRCTL1 0x00000184
+#define MCASP_O_XRSRCTL2 0x00000188
+#define MCASP_O_XRSRCTL3 0x0000018C
+#define MCASP_O_XRSRCTL4 0x00000190
+#define MCASP_O_XRSRCTL5 0x00000194
+#define MCASP_O_XRSRCTL6 0x00000198
+#define MCASP_O_XRSRCTL7 0x0000019C
+#define MCASP_O_XRSRCTL8 0x000001A0
+#define MCASP_O_XRSRCTL9 0x000001A4
+#define MCASP_O_XRSRCTL10 0x000001A8
+#define MCASP_O_XRSRCTL11 0x000001AC
+#define MCASP_O_XRSRCTL12 0x000001B0
+#define MCASP_O_XRSRCTL13 0x000001B4
+#define MCASP_O_XRSRCTL14 0x000001B8
+#define MCASP_O_XRSRCTL15 0x000001BC
+#define MCASP_O_TXBUF0 0x00000200
+#define MCASP_O_TXBUF1 0x00000204
+#define MCASP_O_TXBUF2 0x00000208
+#define MCASP_O_TXBUF3 0x0000020C
+#define MCASP_O_TXBUF4 0x00000210
+#define MCASP_O_TXBUF5 0x00000214
+#define MCASP_O_TXBUF6 0x00000218
+#define MCASP_O_TXBUF7 0x0000021C
+#define MCASP_O_TXBUF8 0x00000220
+#define MCASP_O_TXBUF9 0x00000224
+#define MCASP_O_TXBUF10 0x00000228
+#define MCASP_O_TXBUF11 0x0000022C
+#define MCASP_O_TXBUF12 0x00000230
+#define MCASP_O_TXBUF13 0x00000234
+#define MCASP_O_TXBUF14 0x00000238
+#define MCASP_O_TXBUF15 0x0000023C
+#define MCASP_O_RXBUF0 0x00000280
+#define MCASP_O_RXBUF1 0x00000284
+#define MCASP_O_RXBUF2 0x00000288
+#define MCASP_O_RXBUF3 0x0000028C
+#define MCASP_O_RXBUF4 0x00000290
+#define MCASP_O_RXBUF5 0x00000294
+#define MCASP_O_RXBUF6 0x00000298
+#define MCASP_O_RXBUF7 0x0000029C
+#define MCASP_O_RXBUF8 0x000002A0
+#define MCASP_O_RXBUF9 0x000002A4
+#define MCASP_O_RXBUF10 0x000002A8
+#define MCASP_O_RXBUF11 0x000002AC
+#define MCASP_O_RXBUF12 0x000002B0
+#define MCASP_O_RXBUF13 0x000002B4
+#define MCASP_O_RXBUF14 0x000002B8
+#define MCASP_O_RXBUF15 0x000002BC
+#define MCASP_0_WFIFOCTL 0x00001000
+#define MCASP_0_WFIFOSTS 0x00001004
+#define MCASP_0_RFIFOCTL 0x00001008
+#define MCASP_0_RFIFOSTS 0x0000100C
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_PID register.
+//
+//******************************************************************************
+#define MCASP_PID_SCHEME_M 0xC0000000
+#define MCASP_PID_SCHEME_S 30
+#define MCASP_PID_RESV_M 0x30000000
+#define MCASP_PID_RESV_S 28
+#define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP
+#define MCASP_PID_FUNCTION_S 16
+#define MCASP_PID_RTL_M 0x0000F800
+#define MCASP_PID_RTL_S 11
+#define MCASP_PID_REVMAJOR_M 0x00000700
+#define MCASP_PID_REVMAJOR_S 8
+#define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom
+#define MCASP_PID_CUSTOM_S 6
+#define MCASP_PID_REVMINOR_M 0x0000003F
+#define MCASP_PID_REVMINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// MCASP_O_ESYSCONFIG register.
+//
+//******************************************************************************
+#define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5
+#define MCASP_ESYSCONFIG_RSV_S 6
+#define MCASP_ESYSCONFIG_OTHER_M \
+ 0x0000003C // Reserved for future expansion
+
+#define MCASP_ESYSCONFIG_OTHER_S 2
+#define MCASP_ESYSCONFIG_IDLE_MODE_M \
+ 0x00000003 // Idle Mode
+
+#define MCASP_ESYSCONFIG_IDLE_MODE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_PFUNC register.
+//
+//******************************************************************************
+#define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1
+#define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1
+#define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1
+#define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1
+#define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1
+#define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1
+#define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1
+#define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved
+#define MCASP_PFUNC_RESV1_S 16
+#define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1
+#define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1
+#define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1
+#define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1
+#define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1
+#define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1
+#define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1
+#define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1
+#define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1
+#define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1
+#define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1
+#define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1
+#define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1
+#define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1
+#define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1
+#define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_PDIR register.
+//
+//******************************************************************************
+#define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1
+#define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1
+#define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1
+#define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1
+#define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1
+#define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1
+#define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1
+#define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved
+#define MCASP_PDIR_RESV_S 16
+#define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1
+#define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1
+#define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1
+#define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1
+#define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1
+#define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1
+#define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1
+#define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1
+#define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1
+#define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1
+#define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1
+#define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1
+#define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1
+#define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1
+#define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1
+#define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_PDOUT register.
+//
+//******************************************************************************
+#define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1
+#define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1
+#define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1
+#define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1
+#define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1
+#define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1
+#define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1
+#define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved
+#define MCASP_PDOUT_RESV_S 16
+#define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1
+#define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1
+#define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1
+#define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1
+#define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1
+#define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1
+#define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1
+#define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1
+#define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1
+#define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1
+#define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1
+#define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1
+#define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1
+#define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1
+#define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1
+#define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_PDSET register.
+//
+//******************************************************************************
+#define MCASP_PDSET_AFSR 0x80000000
+#define MCASP_PDSET_AHCLKR 0x40000000
+#define MCASP_PDSET_ACLKR 0x20000000
+#define MCASP_PDSET_AFSX 0x10000000
+#define MCASP_PDSET_AHCLKX 0x08000000
+#define MCASP_PDSET_ACLKX 0x04000000
+#define MCASP_PDSET_AMUTE 0x02000000
+#define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved
+#define MCASP_PDSET_RESV_S 16
+#define MCASP_PDSET_AXR15 0x00008000
+#define MCASP_PDSET_AXR14 0x00004000
+#define MCASP_PDSET_AXR13 0x00002000
+#define MCASP_PDSET_AXR12 0x00001000
+#define MCASP_PDSET_AXR11 0x00000800
+#define MCASP_PDSET_AXR10 0x00000400
+#define MCASP_PDSET_AXR9 0x00000200
+#define MCASP_PDSET_AXR8 0x00000100
+#define MCASP_PDSET_AXR7 0x00000080
+#define MCASP_PDSET_AXR6 0x00000040
+#define MCASP_PDSET_AXR5 0x00000020
+#define MCASP_PDSET_AXR4 0x00000010
+#define MCASP_PDSET_AXR3 0x00000008
+#define MCASP_PDSET_AXR2 0x00000004
+#define MCASP_PDSET_AXR1 0x00000002
+#define MCASP_PDSET_AXR0 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_PDIN register.
+//
+//******************************************************************************
+#define MCASP_PDIN_AFSR 0x80000000
+#define MCASP_PDIN_AHCLKR 0x40000000
+#define MCASP_PDIN_ACLKR 0x20000000
+#define MCASP_PDIN_AFSX 0x10000000
+#define MCASP_PDIN_AHCLKX 0x08000000
+#define MCASP_PDIN_ACLKX 0x04000000
+#define MCASP_PDIN_AMUTE 0x02000000
+#define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved
+#define MCASP_PDIN_RESV_S 16
+#define MCASP_PDIN_AXR15 0x00008000
+#define MCASP_PDIN_AXR14 0x00004000
+#define MCASP_PDIN_AXR13 0x00002000
+#define MCASP_PDIN_AXR12 0x00001000
+#define MCASP_PDIN_AXR11 0x00000800
+#define MCASP_PDIN_AXR10 0x00000400
+#define MCASP_PDIN_AXR9 0x00000200
+#define MCASP_PDIN_AXR8 0x00000100
+#define MCASP_PDIN_AXR7 0x00000080
+#define MCASP_PDIN_AXR6 0x00000040
+#define MCASP_PDIN_AXR5 0x00000020
+#define MCASP_PDIN_AXR4 0x00000010
+#define MCASP_PDIN_AXR3 0x00000008
+#define MCASP_PDIN_AXR2 0x00000004
+#define MCASP_PDIN_AXR1 0x00000002
+#define MCASP_PDIN_AXR0 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_PDCLR register.
+//
+//******************************************************************************
+#define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1
+#define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1
+#define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1
+#define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1
+#define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1
+#define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1
+#define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1
+#define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved
+#define MCASP_PDCLR_RESV_S 16
+#define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1
+#define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1
+#define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1
+#define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1
+#define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1
+#define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1
+#define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1
+#define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1
+#define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1
+#define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1
+#define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1
+#define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1
+#define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1
+#define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1
+#define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1
+#define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TLGC register.
+//
+//******************************************************************************
+#define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved
+#define MCASP_TLGC_RESV_S 16
+#define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0
+ // 0x1 0x2 0x3
+#define MCASP_TLGC_MT_S 14
+#define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved
+#define MCASP_TLGC_RESV1_S 9
+#define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1
+#define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1
+#define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1
+#define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3
+#define MCASP_TLGC_MC_S 4
+#define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4
+ // 0x5 0x6 0x7
+#define MCASP_TLGC_PC_S 1
+#define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this
+ // bit 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TLMR register.
+//
+//******************************************************************************
+#define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature.
+#define MCASP_TLMR_TLMR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TLEC register.
+//
+//******************************************************************************
+#define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during
+ // which MISR sig will be
+ // accumulated.
+#define MCASP_TLEC_TLEC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_GBLCTL register.
+//
+//******************************************************************************
+#define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1
+#define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1
+#define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1
+#define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1
+#define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1
+#define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1
+#define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1
+#define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1
+#define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1
+#define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_AMUTE register.
+//
+//******************************************************************************
+#define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1
+#define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1
+#define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1
+#define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1
+#define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1
+#define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1
+#define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1
+#define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1
+#define MCASP_AMUTE_INSTAT 0x00000010
+#define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in
+ // active 0 1
+#define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1
+#define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2
+#define MCASP_AMUTE_MUTEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_LBCTL register.
+//
+//******************************************************************************
+#define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1
+#define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator
+ // 0x0 0x1 0x2 0x3
+#define MCASP_LBCTL_MODE_S 2
+#define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1
+#define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXDITCTL register.
+//
+//******************************************************************************
+#define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1
+#define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1
+#define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_GBLCTLR register.
+//
+//******************************************************************************
+#define MCASP_GBLCTLR_XFRST 0x00001000
+#define MCASP_GBLCTLR_XSMRST 0x00000800
+#define MCASP_GBLCTLR_XSRCLR 0x00000400
+#define MCASP_GBLCTLR_XHCLKRST 0x00000200
+#define MCASP_GBLCTLR_XCLKRST 0x00000100
+#define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1
+#define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1
+#define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1
+#define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1
+#define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXMASK register.
+//
+//******************************************************************************
+#define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1
+#define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1
+#define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1
+#define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1
+#define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1
+#define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1
+#define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1
+#define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1
+#define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1
+#define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1
+#define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1
+#define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1
+#define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1
+#define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1
+#define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1
+#define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1
+#define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1
+#define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1
+#define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1
+#define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1
+#define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1
+#define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1
+#define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1
+#define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1
+#define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1
+#define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1
+#define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1
+#define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1
+#define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1
+#define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1
+#define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1
+#define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXFMT register.
+//
+//******************************************************************************
+#define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit
+ // delay 0x1 1 Bit delay 0x2 2 Bit
+ // delay
+#define MCASP_RXFMT_RDATDLY_S 16
+#define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1
+#define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2
+#define MCASP_RXFMT_RPAD_S 13
+#define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position
+#define MCASP_RXFMT_RPBIT_S 8
+#define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3
+ // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB
+ // 0xC 0xD 0xE 0xF
+#define MCASP_RXFMT_RSSZ_S 4
+#define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0
+ // DMA port access 1 CPU port Access
+#define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2
+ // 0x3 0x4 0x5 0x6 0x7
+#define MCASP_RXFMT_RROT_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXFMCTL register.
+//
+//******************************************************************************
+#define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode
+#define MCASP_RXFMCTL_RMOD_S 7
+#define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1
+#define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1
+#define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register.
+//
+//******************************************************************************
+#define MCASP_ACLKRCTL_BUSY 0x00100000
+#define MCASP_ACLKRCTL_DIVBUSY 0x00080000
+#define MCASP_ACLKRCTL_ADJBUSY 0x00040000
+#define MCASP_ACLKRCTL_CLKRADJ_M \
+ 0x00030000
+
+#define MCASP_ACLKRCTL_CLKRADJ_S 16
+#define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1
+#define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1
+#define MCASP_ACLKRCTL_CLKRDIV_M \
+ 0x0000001F // RCV clock devide ratio
+
+#define MCASP_ACLKRCTL_CLKRDIV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register.
+//
+//******************************************************************************
+#define MCASP_AHCLKRCTL_BUSY 0x00100000
+#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000
+#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000
+#define MCASP_AHCLKRCTL_HCLKRADJ_M \
+ 0x00030000
+
+#define MCASP_AHCLKRCTL_HCLKRADJ_S 16
+#define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1
+#define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before
+ // diviser 0 1
+#define MCASP_AHCLKRCTL_HCLKRDIV_M \
+ 0x00000FFF // RCV clock Divide Ratio
+
+#define MCASP_AHCLKRCTL_HCLKRDIV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXTDM register.
+//
+//******************************************************************************
+#define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31
+ // 0 1
+#define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30
+ // 0 1
+#define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29
+ // 0 1
+#define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28
+ // 0 1
+#define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27
+ // 0 1
+#define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26
+ // 0 1
+#define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25
+ // 0 1
+#define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24
+ // 0 1
+#define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23
+ // 0 1
+#define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22
+ // 0 1
+#define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21
+ // 0 1
+#define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20
+ // 0 1
+#define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19
+ // 0 1
+#define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18
+ // 0 1
+#define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17
+ // 0 1
+#define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16
+ // 0 1
+#define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15
+ // 0 1
+#define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14
+ // 0 1
+#define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13
+ // 0 1
+#define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12
+ // 0 1
+#define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11
+ // 0 1
+#define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10
+ // 0 1
+#define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9
+ // 0 1
+#define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8
+ // 0 1
+#define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7
+ // 0 1
+#define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6
+ // 0 1
+#define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5
+ // 0 1
+#define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4
+ // 0 1
+#define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3
+ // 0 1
+#define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2
+ // 0 1
+#define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1
+ // 0 1
+#define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0
+ // 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_EVTCTLR register.
+//
+//******************************************************************************
+#define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1
+#define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1
+#define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1
+#define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1
+#define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1
+#define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1
+#define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXSTAT register.
+//
+//******************************************************************************
+#define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1
+#define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1
+#define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1
+#define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1
+#define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1
+#define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1
+#define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1
+#define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0
+ // 1
+#define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register.
+//
+//******************************************************************************
+#define MCASP_RXTDMSLOT_RSLOTCNT_M \
+ 0x000003FF // Current RCV time slot count
+
+#define MCASP_RXTDMSLOT_RSLOTCNT_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register.
+//
+//******************************************************************************
+#define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value
+#define MCASP_RXCLKCHK_RCNT_S 24
+#define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary
+#define MCASP_RXCLKCHK_RMAX_S 16
+#define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary
+#define MCASP_RXCLKCHK_RMIN_S 8
+#define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0
+ // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8
+#define MCASP_RXCLKCHK_RPS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_REVTCTL register.
+//
+//******************************************************************************
+#define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable
+ // DMA Transfer 1 Disable DMA
+ // Transfer
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_GBLCTLX register.
+//
+//******************************************************************************
+#define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1
+#define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1
+#define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1
+#define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1
+#define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1
+#define MCASP_GBLCTLX_RFRST 0x00000010
+#define MCASP_GBLCTLX_RSMRST 0x00000008
+#define MCASP_GBLCTLX_RSRCLKR 0x00000004
+#define MCASP_GBLCTLX_RHCLKRST 0x00000002
+#define MCASP_GBLCTLX_RCLKRST 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXMASK register.
+//
+//******************************************************************************
+#define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1
+#define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1
+#define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1
+#define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1
+#define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1
+#define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1
+#define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1
+#define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1
+#define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1
+#define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1
+#define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1
+#define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1
+#define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1
+#define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1
+#define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1
+#define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1
+#define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1
+#define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1
+#define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1
+#define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1
+#define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1
+#define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1
+#define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1
+#define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1
+#define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1
+#define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1
+#define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1
+#define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1
+#define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1
+#define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1
+#define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1
+#define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXFMT register.
+//
+//******************************************************************************
+#define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit
+ // delay 0x1 1 Bit delay 0x2 2 Bit
+ // delay
+#define MCASP_TXFMT_XDATDLY_S 16
+#define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1
+#define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2
+#define MCASP_TXFMT_XPAD_S 13
+#define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position
+#define MCASP_TXFMT_XPBIT_S 8
+#define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3
+ // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB
+ // 0xC 0xD 0xE 0xF
+#define MCASP_TXFMT_XSSZ_S 4
+#define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0
+ // DMA port access 1 CPU port Access
+#define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2
+ // 0x3 0x4 0x5 0x6 0x7
+#define MCASP_TXFMT_XROT_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXFMCTL register.
+//
+//******************************************************************************
+#define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode
+#define MCASP_TXFMCTL_XMOD_S 7
+#define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1
+#define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1
+#define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register.
+//
+//******************************************************************************
+#define MCASP_ACLKXCTL_BUSY 0x00100000
+#define MCASP_ACLKXCTL_DIVBUSY 0x00080000
+#define MCASP_ACLKXCTL_ADJBUSY 0x00040000
+#define MCASP_ACLKXCTL_CLKXADJ_M \
+ 0x00030000
+
+#define MCASP_ACLKXCTL_CLKXADJ_S 16
+#define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1
+#define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0
+ // 1
+#define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1
+#define MCASP_ACLKXCTL_CLKXDIV_M \
+ 0x0000001F // XMT clock devide ratio
+
+#define MCASP_ACLKXCTL_CLKXDIV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register.
+//
+//******************************************************************************
+#define MCASP_AHCLKXCTL_BUSY 0x00100000
+#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000
+#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000
+#define MCASP_AHCLKXCTL_HCLKXADJ_M \
+ 0x00030000
+
+#define MCASP_AHCLKXCTL_HCLKXADJ_S 16
+#define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1
+#define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before
+ // diviser 0 1
+#define MCASP_AHCLKXCTL_HCLKXDIV_M \
+ 0x00000FFF // XMT clock Divide Ratio
+
+#define MCASP_AHCLKXCTL_HCLKXDIV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXTDM register.
+//
+//******************************************************************************
+#define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31
+ // 0 1
+#define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30
+ // 0 1
+#define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29
+ // 0 1
+#define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28
+ // 0 1
+#define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27
+ // 0 1
+#define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26
+ // 0 1
+#define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25
+ // 0 1
+#define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24
+ // 0 1
+#define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23
+ // 0 1
+#define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22
+ // 0 1
+#define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21
+ // 0 1
+#define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20
+ // 0 1
+#define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19
+ // 0 1
+#define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18
+ // 0 1
+#define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17
+ // 0 1
+#define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16
+ // 0 1
+#define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15
+ // 0 1
+#define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14
+ // 0 1
+#define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13
+ // 0 1
+#define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12
+ // 0 1
+#define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11
+ // 0 1
+#define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10
+ // 0 1
+#define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9
+ // 0 1
+#define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8
+ // 0 1
+#define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7
+ // 0 1
+#define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6
+ // 0 1
+#define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5
+ // 0 1
+#define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4
+ // 0 1
+#define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3
+ // 0 1
+#define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2
+ // 0 1
+#define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1
+ // 0 1
+#define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0
+ // 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_EVTCTLX register.
+//
+//******************************************************************************
+#define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1
+#define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1
+#define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1
+#define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1
+#define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1
+#define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1
+#define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXSTAT register.
+//
+//******************************************************************************
+#define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1
+#define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1
+#define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1
+#define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1
+#define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1
+#define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1
+#define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1
+#define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0
+ // 1
+#define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register.
+//
+//******************************************************************************
+#define MCASP_TXTDMSLOT_XSLOTCNT_M \
+ 0x000003FF // Current XMT time slot count
+ // during reset the value of this
+ // register is 0b0101111111 (0x17f)
+ // and after reset 0
+
+#define MCASP_TXTDMSLOT_XSLOTCNT_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register.
+//
+//******************************************************************************
+#define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value
+#define MCASP_TXCLKCHK_XCNT_S 24
+#define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary
+#define MCASP_TXCLKCHK_XMAX_S 16
+#define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary
+#define MCASP_TXCLKCHK_XMIN_S 8
+#define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved
+#define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0
+ // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8
+#define MCASP_TXCLKCHK_XPS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XEVTCTL register.
+//
+//******************************************************************************
+#define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable
+ // DMA Transfer 1 Disable DMA
+ // Transfer
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_CLKADJEN register.
+//
+//******************************************************************************
+#define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRA0_DITCSRA0_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRA0_DITCSRA0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRA1_DITCSRA1_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRA1_DITCSRA1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRA2_DITCSRA2_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) Channel
+ // status Register
+
+#define MCASP_DITCSRA2_DITCSRA2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRA3_DITCSRA3_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) Channel
+ // status Register
+
+#define MCASP_DITCSRA3_DITCSRA3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRA4_DITCSRA4_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRA4_DITCSRA4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRA5_DITCSRA5_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRA5_DITCSRA5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRB0_DITCSRB0_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRB0_DITCSRB0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRB1_DITCSRB1_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRB1_DITCSRB1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRB2_DITCSRB2_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRB2_DITCSRB2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRB3_DITCSRB3_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRB3_DITCSRB3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRB4_DITCSRB4_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRB4_DITCSRB4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register.
+//
+//******************************************************************************
+#define MCASP_DITCSRB5_DITCSRB5_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) Channel
+ // status
+
+#define MCASP_DITCSRB5_DITCSRB5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRA0_DITUDRA0_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) User Data
+
+#define MCASP_DITUDRA0_DITUDRA0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRA1_DITUDRA1_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) User Data
+
+#define MCASP_DITUDRA1_DITUDRA1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRA2_DITUDRA2_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) User Data
+
+#define MCASP_DITUDRA2_DITUDRA2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRA3_DITUDRA3_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) User Data
+
+#define MCASP_DITUDRA3_DITUDRA3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRA4_DITUDRA4_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) User Data
+
+#define MCASP_DITUDRA4_DITUDRA4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRA5_DITUDRA5_M \
+ 0xFFFFFFFF // Left (Even TDM slot ) User Data
+
+#define MCASP_DITUDRA5_DITUDRA5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRB0_DITUDRB0_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) User Data
+
+#define MCASP_DITUDRB0_DITUDRB0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRB1_DITUDRB1_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) User Data
+
+#define MCASP_DITUDRB1_DITUDRB1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRB2_DITUDRB2_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) User Data
+
+#define MCASP_DITUDRB2_DITUDRB2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRB3_DITUDRB3_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) User Data
+
+#define MCASP_DITUDRB3_DITUDRB3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRB4_DITUDRB4_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) User Data
+
+#define MCASP_DITUDRB4_DITUDRB4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register.
+//
+//******************************************************************************
+#define MCASP_DITUDRB5_DITUDRB5_M \
+ 0xFFFFFFFF // Right (odd TDM slot ) User Data
+
+#define MCASP_DITUDRB5_DITUDRB5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL0_RRDY 0x00000020
+#define MCASP_XRSRCTL0_XRDY 0x00000010
+#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL0_DISMOD_S 2
+#define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL0_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL1_RRDY 0x00000020
+#define MCASP_XRSRCTL1_XRDY 0x00000010
+#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL1_DISMOD_S 2
+#define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL1_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL2_RRDY 0x00000020
+#define MCASP_XRSRCTL2_XRDY 0x00000010
+#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL2_DISMOD_S 2
+#define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL2_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL3_RRDY 0x00000020
+#define MCASP_XRSRCTL3_XRDY 0x00000010
+#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL3_DISMOD_S 2
+#define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL3_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL4_RRDY 0x00000020
+#define MCASP_XRSRCTL4_XRDY 0x00000010
+#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL4_DISMOD_S 2
+#define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL4_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL5_RRDY 0x00000020
+#define MCASP_XRSRCTL5_XRDY 0x00000010
+#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL5_DISMOD_S 2
+#define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL5_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL6_RRDY 0x00000020
+#define MCASP_XRSRCTL6_XRDY 0x00000010
+#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL6_DISMOD_S 2
+#define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL6_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL7_RRDY 0x00000020
+#define MCASP_XRSRCTL7_XRDY 0x00000010
+#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL7_DISMOD_S 2
+#define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL7_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL8_RRDY 0x00000020
+#define MCASP_XRSRCTL8_XRDY 0x00000010
+#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL8_DISMOD_S 2
+#define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL8_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL9_RRDY 0x00000020
+#define MCASP_XRSRCTL9_XRDY 0x00000010
+#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+#define MCASP_XRSRCTL9_DISMOD_S 2
+#define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL9_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL10_RRDY 0x00000020
+#define MCASP_XRSRCTL10_XRDY 0x00000010
+#define MCASP_XRSRCTL10_DISMOD_M \
+ 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+
+#define MCASP_XRSRCTL10_DISMOD_S 2
+#define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL10_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL11_RRDY 0x00000020
+#define MCASP_XRSRCTL11_XRDY 0x00000010
+#define MCASP_XRSRCTL11_DISMOD_M \
+ 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+
+#define MCASP_XRSRCTL11_DISMOD_S 2
+#define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL11_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL12_RRDY 0x00000020
+#define MCASP_XRSRCTL12_XRDY 0x00000010
+#define MCASP_XRSRCTL12_DISMOD_M \
+ 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+
+#define MCASP_XRSRCTL12_DISMOD_S 2
+#define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL12_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL13_RRDY 0x00000020
+#define MCASP_XRSRCTL13_XRDY 0x00000010
+#define MCASP_XRSRCTL13_DISMOD_M \
+ 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+
+#define MCASP_XRSRCTL13_DISMOD_S 2
+#define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL13_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL14_RRDY 0x00000020
+#define MCASP_XRSRCTL14_XRDY 0x00000010
+#define MCASP_XRSRCTL14_DISMOD_M \
+ 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+
+#define MCASP_XRSRCTL14_DISMOD_S 2
+#define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL14_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register.
+//
+//******************************************************************************
+#define MCASP_XRSRCTL15_RRDY 0x00000020
+#define MCASP_XRSRCTL15_XRDY 0x00000010
+#define MCASP_XRSRCTL15_DISMOD_M \
+ 0x0000000C // Serializer drive state 0x0 Tri
+ // state 0x1 Reserved 0x2 Drive pin
+ // low 0x3 Drive pin high
+
+#define MCASP_XRSRCTL15_DISMOD_S 2
+#define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive
+ // mode 0x1 Transmit mode 0x2
+ // Receive mode
+#define MCASP_XRSRCTL15_SRMOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF0 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0
+#define MCASP_TXBUF0_XBUF0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF1 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1
+#define MCASP_TXBUF1_XBUF1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF2 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2
+#define MCASP_TXBUF2_XBUF2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF3 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3
+#define MCASP_TXBUF3_XBUF3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF4 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4
+#define MCASP_TXBUF4_XBUF4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF5 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5
+#define MCASP_TXBUF5_XBUF5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF6 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6
+#define MCASP_TXBUF6_XBUF6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF7 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7
+#define MCASP_TXBUF7_XBUF7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF8 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8
+#define MCASP_TXBUF8_XBUF8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF9 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9
+#define MCASP_TXBUF9_XBUF9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF10 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10
+#define MCASP_TXBUF10_XBUF10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF11 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11
+#define MCASP_TXBUF11_XBUF11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF12 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12
+#define MCASP_TXBUF12_XBUF12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF13 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13
+#define MCASP_TXBUF13_XBUF13_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF14 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14
+#define MCASP_TXBUF14_XBUF14_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_TXBUF15 register.
+//
+//******************************************************************************
+#define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15
+#define MCASP_TXBUF15_XBUF15_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF0 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0
+#define MCASP_RXBUF0_RBUF0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF1 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1
+#define MCASP_RXBUF1_RBUF1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF2 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2
+#define MCASP_RXBUF2_RBUF2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF3 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3
+#define MCASP_RXBUF3_RBUF3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF4 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4
+#define MCASP_RXBUF4_RBUF4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF5 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5
+#define MCASP_RXBUF5_RBUF5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF6 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6
+#define MCASP_RXBUF6_RBUF6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF7 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7
+#define MCASP_RXBUF7_RBUF7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF8 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8
+#define MCASP_RXBUF8_RBUF8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF9 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9
+#define MCASP_RXBUF9_RBUF9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF10 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10
+#define MCASP_RXBUF10_RBUF10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF11 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11
+#define MCASP_RXBUF11_RBUF11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF12 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12
+#define MCASP_RXBUF12_RBUF12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF13 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13
+#define MCASP_RXBUF13_RBUF13_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF14 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14
+#define MCASP_RXBUF14_RBUF14_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCASP_O_RXBUF15 register.
+//
+//******************************************************************************
+#define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15
+#define MCASP_RXBUF15_RBUF15_S 0
+
+
+
+#endif // __HW_MCASP_H__
diff --git a/cc3200/hal/inc/hw_mcspi.h b/cc3200/hal/inc/hw_mcspi.h
new file mode 100644
index 0000000000..079e4b6b67
--- /dev/null
+++ b/cc3200/hal/inc/hw_mcspi.h
@@ -0,0 +1,1745 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_MCSPI_H__
+#define __HW_MCSPI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the MCSPI register offsets.
+//
+//*****************************************************************************
+#define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R)
+ // Used by software to track
+ // features bugs and compatibility
+#define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP
+ // module's hardware configuration
+ // i.e. typically the module's HDL
+ // generics (if any). Actual field
+ // format and encoding is up to the
+ // module's designer to decide.
+#define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock
+ // management configuration
+#define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This
+ // register contains the hard coded
+ // RTL revision number.
+#define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This
+ // register allows controlling
+ // various parameters of the OCP
+ // interface.
+#define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This
+ // register provides status
+ // information about the module
+ // excluding the interrupt status
+ // information
+#define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The
+ // interrupt status regroups all the
+ // status of the module internal
+ // events that can generate an
+ // interrupt
+#define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This
+ // register allows to enable/disable
+ // the module internal sources of
+ // interrupt on an event-by-event
+ // basis.
+#define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The
+ // wakeup enable register allows to
+ // enable/disable the module
+ // internal sources of wakeup on
+ // event-by-event basis.
+#define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This
+ // register is used to check the
+ // correctness of the system
+ // interconnect either internally to
+ // peripheral bus or externally to
+ // device IO pads when the module is
+ // configured in system test
+ // (SYSTEST) mode.
+#define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This
+ // register is dedicated to the
+ // configuration of the serial port
+ // interface.
+#define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This
+ // register is dedicated to the
+ // configuration of the channel 0
+#define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This
+ // register provides status
+ // information about transmitter and
+ // receiver registers of channel 0
+#define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This
+ // register is dedicated to enable
+ // the channel 0
+#define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This
+ // register contains a single SPI
+ // word to transmit on the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This
+ // register contains a single SPI
+ // word received through the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This
+ // register is dedicated to the
+ // configuration of the channel.
+#define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This
+ // register provides status
+ // information about transmitter and
+ // receiver registers of channel 1
+#define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This
+ // register is dedicated to enable
+ // the channel 1
+#define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This
+ // register contains a single SPI
+ // word to transmit on the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This
+ // register contains a single SPI
+ // word received through the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This
+ // register is dedicated to the
+ // configuration of the channel 2
+#define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This
+ // register provides status
+ // information about transmitter and
+ // receiver registers of channel 2
+#define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This
+ // register is dedicated to enable
+ // the channel 2
+#define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This
+ // register contains a single SPI
+ // word to transmit on the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This
+ // register contains a single SPI
+ // word received through the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This
+ // register is dedicated to the
+ // configuration of the channel 3
+#define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This
+ // register provides status
+ // information about transmitter and
+ // receiver registers of channel 3
+#define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This
+ // register is dedicated to enable
+ // the channel 3
+#define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This
+ // register contains a single SPI
+ // word to transmit on the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This
+ // register contains a single SPI
+ // word received through the serial
+ // link what ever SPI word length
+ // is.
+#define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This
+ // register provides transfer levels
+ // needed while using FIFO buffer
+ // during transfer.
+#define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This
+ // register contains the SPI words
+ // to transmit on the serial link
+ // when FIFO used and DMA address is
+ // aligned on 256 bit.This register
+ // is an image of one of MCSPI_TX(i)
+ // register corresponding to the
+ // channel which have its FIFO
+ // enabled.
+#define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This
+ // register contains the SPI words
+ // to received on the serial link
+ // when FIFO used and DMA address is
+ // aligned on 256 bit.This register
+ // is an image of one of MCSPI_RX(i)
+ // register corresponding to the
+ // channel which have its FIFO
+ // enabled.
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_HL_REV register.
+//
+//******************************************************************************
+#define MCSPI_HL_REV_SCHEME_M 0xC0000000
+#define MCSPI_HL_REV_SCHEME_S 30
+#define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are
+ // initialized to zero and writes to
+ // them are ignored.
+#define MCSPI_HL_REV_RSVD_S 28
+#define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software
+ // compatible module family. If
+ // there is no level of software
+ // compatibility a new Func number
+ // (and hence REVISION) should be
+ // assigned.
+#define MCSPI_HL_REV_FUNC_S 16
+#define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
+ // design owner. RTL follows a
+ // numbering such as X.Y.R.Z which
+ // are explained in this table. R
+ // changes ONLY when: (1) PDS
+ // uploads occur which may have been
+ // due to spec changes (2) Bug fixes
+ // occur (3) Resets to '0' when X or
+ // Y changes. Design team has an
+ // internal 'Z' (customer invisible)
+ // number which increments on every
+ // drop that happens due to DV and
+ // RTL updates. Z resets to 0 when R
+ // increments.
+#define MCSPI_HL_REV_R_RTL_S 11
+#define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by
+ // IP specification owner. X changes
+ // ONLY when: (1) There is a major
+ // feature addition. An example
+ // would be adding Master Mode to
+ // Utopia Level2. The Func field (or
+ // Class/Type in old PID format)
+ // will remain the same. X does NOT
+ // change due to: (1) Bug fixes (2)
+ // Change in feature parameters.
+#define MCSPI_HL_REV_X_MAJOR_S 8
+#define MCSPI_HL_REV_CUSTOM_M 0x000000C0
+#define MCSPI_HL_REV_CUSTOM_S 6
+#define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by
+ // IP specification owner. Y changes
+ // ONLY when: (1) Features are
+ // scaled (up or down). Flexibility
+ // exists in that this feature
+ // scalability may either be
+ // represented in the Y change or a
+ // specific register in the IP that
+ // indicates which features are
+ // exactly available. (2) When
+ // feature creeps from Is-Not list
+ // to Is list. But this may not be
+ // the case once it sees silicon; in
+ // which case X will change. Y does
+ // NOT change due to: (1) Bug fixes
+ // (2) Typos or clarifications (3)
+ // major functional/feature
+ // change/addition/deletion. Instead
+ // these changes may be reflected
+ // via R S X as applicable. Spec
+ // owner maintains a
+ // customer-invisible number 'S'
+ // which changes due to: (1)
+ // Typos/clarifications (2) Bug
+ // documentation. Note that this bug
+ // is not due to a spec change but
+ // due to implementation.
+ // Nevertheless the spec tracks the
+ // IP bugs. An RTL release (say for
+ // silicon PG1.1) that occurs due to
+ // bug fix should document the
+ // corresponding spec number (X.Y.S)
+ // in its release notes.
+#define MCSPI_HL_REV_Y_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register.
+//
+//******************************************************************************
+#define MCSPI_HL_HWINFO_RETMODE 0x00000040
+#define MCSPI_HL_HWINFO_FFNBYTE_M \
+ 0x0000003E
+
+#define MCSPI_HL_HWINFO_FFNBYTE_S 1
+#define MCSPI_HL_HWINFO_USEFIFO 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// MCSPI_O_HL_SYSCONFIG register.
+//
+//******************************************************************************
+#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \
+ 0x0000000C // Configuration of the local
+ // target state management mode. By
+ // definition target can handle
+ // read/write transaction as long as
+ // it is out of IDLE state. 0x0
+ // Force-idle mode: local target's
+ // idle state follows (acknowledges)
+ // the system's idle requests
+ // unconditionally i.e. regardless
+ // of the IP module's internal
+ // requirements.Backup mode for
+ // debug only. 0x1 No-idle mode:
+ // local target never enters idle
+ // state.Backup mode for debug only.
+ // 0x2 Smart-idle mode: local
+ // target's idle state eventually
+ // follows (acknowledges) the
+ // system's idle requests depending
+ // on the IP module's internal
+ // requirements.IP module shall not
+ // generate (IRQ- or
+ // DMA-request-related) wakeup
+ // events. 0x3 "Smart-idle
+ // wakeup-capable mode: local
+ // target's idle state eventually
+ // follows (acknowledges) the
+ // system's idle requests depending
+ // on the IP module's internal
+ // requirements.IP module may
+ // generate (IRQ- or
+ // DMA-request-related) wakeup
+ // events when in idle state.Mode is
+ // only relevant if the appropriate
+ // IP module ""swakeup"" output(s)
+ // is (are) implemented."
+
+#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2
+#define MCSPI_HL_SYSCONFIG_FREEEMU \
+ 0x00000002 // Sensitivity to emulation (debug)
+ // suspend input signal. 0 IP module
+ // is sensitive to emulation suspend
+ // 1 IP module is not sensitive to
+ // emulation suspend
+
+#define MCSPI_HL_SYSCONFIG_SOFTRESET \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_REVISION register.
+//
+//******************************************************************************
+#define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision
+ // [3:0] Minor revision Examples:
+ // 0x10 for 1.0 0x21 for 2.1
+#define MCSPI_REVISION_REV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register.
+//
+//******************************************************************************
+#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \
+ 0x00000300 // Clocks activity during wake up
+ // mode period 0x0 OCP and
+ // Functional clocks may be switched
+ // off. 0x1 OCP clock is maintained.
+ // Functional clock may be
+ // switched-off. 0x2 Functional
+ // clock is maintained. OCP clock
+ // may be switched-off. 0x3 OCP and
+ // Functional clocks are maintained.
+
+#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8
+#define MCSPI_SYSCONFIG_SIDLEMODE_M \
+ 0x00000018 // Power management 0x0 If an idle
+ // request is detected the McSPI
+ // acknowledges it unconditionally
+ // and goes in Inactive mode.
+ // Interrupt DMA requests and wake
+ // up lines are unconditionally
+ // de-asserted and the module wakeup
+ // capability is deactivated even if
+ // the bit
+ // MCSPI_SYSCONFIG[EnaWakeUp] is
+ // set. 0x1 If an idle request is
+ // detected the request is ignored
+ // and the module does not switch to
+ // wake up mode and keeps on
+ // behaving normally. 0x2 If an idle
+ // request is detected the module
+ // will switch to idle mode based on
+ // its internal activity. The wake
+ // up capability cannot be used. 0x3
+ // If an idle request is detected
+ // the module will switch to idle
+ // mode based on its internal
+ // activity and the wake up
+ // capability can be used if the bit
+ // MCSPI_SYSCONFIG[EnaWakeUp] is
+ // set.
+
+#define MCSPI_SYSCONFIG_SIDLEMODE_S 3
+#define MCSPI_SYSCONFIG_ENAWAKEUP \
+ 0x00000004 // WakeUp feature control 0 WakeUp
+ // capability is disabled 1 WakeUp
+ // capability is enabled
+
+#define MCSPI_SYSCONFIG_SOFTRESET \
+ 0x00000002 // Software reset. During reads it
+ // always returns 0. 0 (write)
+ // Normal mode 1 (write) Set this
+ // bit to 1 to trigger a module
+ // reset.The bit is automatically
+ // reset by the hardware.
+
+#define MCSPI_SYSCONFIG_AUTOIDLE \
+ 0x00000001 // Internal OCP Clock gating
+ // strategy 0 OCP clock is
+ // free-running 1 Automatic OCP
+ // clock gating strategy is applied
+ // based on the OCP interface
+ // activity
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register.
+//
+//******************************************************************************
+#define MCSPI_SYSSTATUS_RESETDONE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register.
+//
+//******************************************************************************
+#define MCSPI_IRQSTATUS_EOW 0x00020000
+#define MCSPI_IRQSTATUS_WKS 0x00010000
+#define MCSPI_IRQSTATUS_RX3_FULL \
+ 0x00004000
+
+#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \
+ 0x00002000
+
+#define MCSPI_IRQSTATUS_TX3_EMPTY \
+ 0x00001000
+
+#define MCSPI_IRQSTATUS_RX2_FULL \
+ 0x00000400
+
+#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \
+ 0x00000200
+
+#define MCSPI_IRQSTATUS_TX2_EMPTY \
+ 0x00000100
+
+#define MCSPI_IRQSTATUS_RX1_FULL \
+ 0x00000040
+
+#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \
+ 0x00000020
+
+#define MCSPI_IRQSTATUS_TX1_EMPTY \
+ 0x00000010
+
+#define MCSPI_IRQSTATUS_RX0_OVERFLOW \
+ 0x00000008
+
+#define MCSPI_IRQSTATUS_RX0_FULL \
+ 0x00000004
+
+#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \
+ 0x00000002
+
+#define MCSPI_IRQSTATUS_TX0_EMPTY \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register.
+//
+//******************************************************************************
+#define MCSPI_IRQENABLE_EOW_ENABLE \
+ 0x00020000 // End of Word count Interrupt
+ // Enable. 0 Interrupt disabled 1
+ // Interrupt enabled
+
+#define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable
+ // in slave mode when an active
+ // control signal is detected on the
+ // SPIEN line programmed in the
+ // field MCSPI_CH0CONF[SPIENSLV] 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \
+ 0x00004000 // Receiver register Full Interrupt
+ // Enable. Ch 3 0 Interrupt disabled
+ // 1 Interrupt enabled
+
+#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \
+ 0x00002000 // Transmitter register Underflow
+ // Interrupt Enable. Ch 3 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \
+ 0x00001000 // Transmitter register Empty
+ // Interrupt Enable. Ch3 0 Interrupt
+ // disabled 1 Interrupt enabled
+
+#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \
+ 0x00000400 // Receiver register Full Interrupt
+ // Enable. Ch 2 0 Interrupt disabled
+ // 1 Interrupt enabled
+
+#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \
+ 0x00000200 // Transmitter register Underflow
+ // Interrupt Enable. Ch 2 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \
+ 0x00000100 // Transmitter register Empty
+ // Interrupt Enable. Ch 2 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \
+ 0x00000040 // Receiver register Full Interrupt
+ // Enable. Ch 1 0 Interrupt disabled
+ // 1 Interrupt enabled
+
+#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \
+ 0x00000020 // Transmitter register Underflow
+ // Interrupt Enable. Ch 1 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \
+ 0x00000010 // Transmitter register Empty
+ // Interrupt Enable. Ch 1 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \
+ 0x00000008 // Receiver register Overflow
+ // Interrupt Enable. Ch 0 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \
+ 0x00000004 // Receiver register Full Interrupt
+ // Enable. Ch 0 0 Interrupt disabled
+ // 1 Interrupt enabled
+
+#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \
+ 0x00000002 // Transmitter register Underflow
+ // Interrupt Enable. Ch 0 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \
+ 0x00000001 // Transmitter register Empty
+ // Interrupt Enable. Ch 0 0
+ // Interrupt disabled 1 Interrupt
+ // enabled
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// MCSPI_O_WAKEUPENABLE register.
+//
+//******************************************************************************
+#define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave
+ // mode when an active control
+ // signal is detected on the SPIEN
+ // line programmed in the field
+ // MCSPI_CH0CONF[SPIENSLV] 0 The
+ // event is not allowed to wakeup
+ // the system even if the global
+ // control bit
+ // MCSPI_SYSCONF[EnaWakeUp] is set.
+ // 1 The event is allowed to wakeup
+ // the system if the global control
+ // bit MCSPI_SYSCONF[EnaWakeUp] is
+ // set.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_SYST register.
+//
+//******************************************************************************
+#define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action.
+ // Writing 0 does not clear already
+ // set status bits; This bit must be
+ // cleared prior attempting to clear
+ // a status bit of the
+ // register. 1
+ // Force to 1 all status bits of
+ // MCSPI_IRQSTATUS register. Writing
+ // 1 into this bit sets to 1 all
+ // status bits contained in the
+ // register.
+#define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the
+ // SPIEN[3:0] lines and SPICLK line
+ // 0 output (as in master mode) 1
+ // input (as in slave mode)
+#define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the
+ // SPIDAT[1] 0 output 1 input
+#define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the
+ // SPIDAT[0] 0 output 1 input
+#define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data
+ // value of internal signal to
+ // system). The signal is driven
+ // high or low according to the
+ // value written into this register
+ // bit. 0 The pin is driven low. 1
+ // The pin is driven high.
+#define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value)
+ // If MCSPI_SYST[SPIENDIR] = 1
+ // (input mode direction) this bit
+ // returns the value on the CLKSPI
+ // line (high or low) and a write
+ // into this bit has no effect. If
+ // MCSPI_SYST[SPIENDIR] = 0 (output
+ // mode direction) the CLKSPI line
+ // is driven high or low according
+ // to the value written into this
+ // register.
+#define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data
+ // value) If MCSPI_SYST[SPIDATDIR1]
+ // = 0 (output mode direction) the
+ // SPIDAT[1] line is driven high or
+ // low according to the value
+ // written into this register. If
+ // MCSPI_SYST[SPIDATDIR1] = 1 (input
+ // mode direction) this bit returns
+ // the value on the SPIDAT[1] line
+ // (high or low) and a write into
+ // this bit has no effect.
+#define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data
+ // value) If MCSPI_SYST[SPIDATDIR0]
+ // = 0 (output mode direction) the
+ // SPIDAT[0] line is driven high or
+ // low according to the value
+ // written into this register. If
+ // MCSPI_SYST[SPIDATDIR0] = 1 (input
+ // mode direction) this bit returns
+ // the value on the SPIDAT[0] line
+ // (high or low) and a write into
+ // this bit has no effect.
+#define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data
+ // value) If MCSPI_SYST[SPIENDIR] =
+ // 0 (output mode direction) the
+ // SPIENT[3] line is driven high or
+ // low according to the value
+ // written into this register. If
+ // MCSPI_SYST[SPIENDIR] = 1 (input
+ // mode direction) this bit returns
+ // the value on the SPIEN[3] line
+ // (high or low) and a write into
+ // this bit has no effect.
+#define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data
+ // value) If MCSPI_SYST[SPIENDIR] =
+ // 0 (output mode direction) the
+ // SPIENT[2] line is driven high or
+ // low according to the value
+ // written into this register. If
+ // MCSPI_SYST[SPIENDIR] = 1 (input
+ // mode direction) this bit returns
+ // the value on the SPIEN[2] line
+ // (high or low) and a write into
+ // this bit has no effect.
+#define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data
+ // value) If MCSPI_SYST[SPIENDIR] =
+ // 0 (output mode direction) the
+ // SPIENT[1] line is driven high or
+ // low according to the value
+ // written into this register. If
+ // MCSPI_SYST[SPIENDIR] = 1 (input
+ // mode direction) this bit returns
+ // the value on the SPIEN[1] line
+ // (high or low) and a write into
+ // this bit has no effect.
+#define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data
+ // value) If MCSPI_SYST[SPIENDIR] =
+ // 0 (output mode direction) the
+ // SPIENT[0] line is driven high or
+ // low according to the value
+ // written into this register. If
+ // MCSPI_SYST[SPIENDIR] = 1 (input
+ // mode direction) this bit returns
+ // the value on the SPIEN[0] line
+ // (high or low) and a write into
+ // this bit has no effect.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register.
+//
+//******************************************************************************
+#define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned
+ // This register is used when a FIFO
+ // is managed by the module and DMA
+ // connected to the controller
+ // provides only 256 bit aligned
+ // address. If this bit is set the
+ // enabled channel which uses the
+ // FIFO has its datas managed
+ // through MCSPI_DAFTX and
+ // MCSPI_DAFRX registers instead of
+ // MCSPI_TX(i) and MCSPI_RX(i)
+ // registers. 0 FIFO data managed by
+ // MCSPI_TX(i) and MCSPI_RX(i)
+ // registers. 1 FIFO data managed by
+ // MCSPI_DAFTX and MCSPI_DAFRX
+ // registers.
+#define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This
+ // register can only be used when a
+ // channel is enabled using a FIFO.
+ // It allows the system to perform
+ // multiple SPI word access for a
+ // single 32-bit OCP word access.
+ // This is possible for WL < 16. 0
+ // Multiple word access disabled 1
+ // Multiple word access enabled with
+ // FIFO
+#define MCSPI_MODULCTRL_INITDLY_M \
+ 0x00000070 // Initial spi delay for first
+ // transfer: This register is an
+ // option only available in SINGLE
+ // master mode The controller waits
+ // for a delay to transmit the first
+ // spi word after channel enabled
+ // and corresponding TX register
+ // filled. This Delay is based on
+ // SPI output frequency clock No
+ // clock output provided to the
+ // boundary and chip select is not
+ // active in 4 pin mode within this
+ // period. 0x0 No delay for first
+ // spi transfer. 0x1 The controller
+ // wait 4 spi bus clock 0x2 The
+ // controller wait 8 spi bus clock
+ // 0x3 The controller wait 16 spi
+ // bus clock 0x4 The controller wait
+ // 32 spi bus clock
+
+#define MCSPI_MODULCTRL_INITDLY_S 4
+#define MCSPI_MODULCTRL_SYSTEM_TEST \
+ 0x00000008 // Enables the system test mode 0
+ // Functional mode 1 System test
+ // mode (SYSTEST)
+
+#define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The
+ // module generates the SPICLK and
+ // SPIEN[3:0] 1 Slave - The module
+ // receives the SPICLK and
+ // SPIEN[3:0]
+#define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This
+ // register is used to configure the
+ // SPI pin mode in master or slave
+ // mode. If asserted the controller
+ // only use SIMOSOMI and SPICLK
+ // clock pin for spi transfers. 0
+ // SPIEN is used as a chip select. 1
+ // SPIEN is not used.In this mode
+ // all related option to chip select
+ // have no meaning.
+#define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel
+ // (master mode only) 0 More than
+ // one channel will be used in
+ // master mode. 1 Only one channel
+ // will be used in master mode. This
+ // bit must be set in Force SPIEN
+ // mode.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH0CONF register.
+//
+//******************************************************************************
+#define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This
+ // register defines the granularity
+ // of channel clock divider: power
+ // of two or one clock cycle
+ // granularity. When this bit is set
+ // the register MCSPI_CHCTRL[EXTCLK]
+ // must be configured to reach a
+ // maximum of 4096 clock divider
+ // ratio. Then The clock divider
+ // ratio is a concatenation of
+ // MCSPI_CHCONF[CLKD] and
+ // MCSPI_CHCTRL[EXTCLK] values 0
+ // Clock granularity of power of two
+ // 1 One clock cycle ganularity
+#define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to receive data. 1 The
+ // buffer is used to receive data.
+#define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to transmit data. 1 The
+ // buffer is used to transmit data.
+#define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This
+ // 2-bits field defines the number
+ // of interface clock cycles between
+ // CS toggling and first or last
+ // edge of SPI clock. 0x0 0.5 clock
+ // cycle 0x1 1.5 clock cycle 0x2 2.5
+ // clock cycle 0x3 3.5 clock cycle
+#define MCSPI_CH0CONF_TCS0_S 25
+#define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit
+ // polarity is held to 0 during SPI
+ // transfer. 1 Start bit polarity is
+ // held to 1 during SPI transfer.
+#define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI
+ // transfer 0 Default SPI transfer
+ // length as specified by WL bit
+ // field 1 Start bit D/CX added
+ // before SPI transfer polarity is
+ // defined by MCSPI_CH0CONF[SBPOL]
+#define MCSPI_CH0CONF_SPIENSLV_M \
+ 0x00600000 // Channel 0 only and slave mode
+ // only: SPI slave select signal
+ // detection. Reserved bits for
+ // other cases. 0x0 Detection
+ // enabled only on SPIEN[0] 0x1
+ // Detection enabled only on
+ // SPIEN[1] 0x2 Detection enabled
+ // only on SPIEN[2] 0x3 Detection
+ // enabled only on SPIEN[3]
+
+#define MCSPI_CH0CONF_SPIENSLV_S 21
+#define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep
+ // SPIEN active between SPI words.
+ // (single channel master mode only)
+ // 0 Writing 0 into this bit drives
+ // low the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it high when
+ // MCSPI_CHCONF(i)[EPOL]=1. 1
+ // Writing 1 into this bit drives
+ // high the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it low when
+ // MCSPI_CHCONF(i)[EPOL]=1
+#define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is
+ // deactivated (recommended for
+ // single SPI word transfer) 1 Turbo
+ // is activated to maximize the
+ // throughput for multi SPI words
+ // transfer.
+#define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0
+ // (SPIDAT[0]) selected for
+ // reception. 1 Data Line1
+ // (SPIDAT[1]) selected for
+ // reception
+#define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data
+ // line 1 (SPIDATAGZEN[1]) 0 Data
+ // Line1 (SPIDAT[1]) selected for
+ // transmission 1 No transmission on
+ // Data Line1 (SPIDAT[1])
+#define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data
+ // line 0 (SPIDATAGZEN[0]) 0 Data
+ // Line0 (SPIDAT[0]) selected for
+ // transmission 1 No transmission on
+ // Data Line0 (SPIDAT[0])
+#define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read
+ // request line is asserted when the
+ // channel is enabled and a new data
+ // is available in the receive
+ // register of the channel. The DMA
+ // Read request line is deasserted
+ // on read completion of the receive
+ // register of the channel. 0 DMA
+ // Read Request disabled 1 DMA Read
+ // Request enabled
+#define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write
+ // request line is asserted when The
+ // channel is enabled and the
+ // transmitter register of the
+ // channel is empty. The DMA Write
+ // request line is deasserted on
+ // load completion of the
+ // transmitter register of the
+ // channel. 0 DMA Write Request
+ // disabled 1 DMA Write Request
+ // enabled
+#define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0
+ // Transmit and Receive mode 0x1
+ // Receive only mode 0x2 Transmit
+ // only mode 0x3 Reserved
+#define MCSPI_CH0CONF_TRM_S 12
+#define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved
+ // 0x01 Reserved 0x02 Reserved 0x03
+ // The SPI word is 4-bits long 0x04
+ // The SPI word is 5-bits long 0x05
+ // The SPI word is 6-bits long 0x06
+ // The SPI word is 7-bits long 0x07
+ // The SPI word is 8-bits long 0x08
+ // The SPI word is 9-bits long 0x09
+ // The SPI word is 10-bits long 0x0A
+ // The SPI word is 11-bits long 0x0B
+ // The SPI word is 12-bits long 0x0C
+ // The SPI word is 13-bits long 0x0D
+ // The SPI word is 14-bits long 0x0E
+ // The SPI word is 15-bits long 0x0F
+ // The SPI word is 16-bits long 0x10
+ // The SPI word is 17-bits long 0x11
+ // The SPI word is 18-bits long 0x12
+ // The SPI word is 19-bits long 0x13
+ // The SPI word is 20-bits long 0x14
+ // The SPI word is 21-bits long 0x15
+ // The SPI word is 22-bits long 0x16
+ // The SPI word is 23-bits long 0x17
+ // The SPI word is 24-bits long 0x18
+ // The SPI word is 25-bits long 0x19
+ // The SPI word is 26-bits long 0x1A
+ // The SPI word is 27-bits long 0x1B
+ // The SPI word is 28-bits long 0x1C
+ // The SPI word is 29-bits long 0x1D
+ // The SPI word is 30-bits long 0x1E
+ // The SPI word is 31-bits long 0x1F
+ // The SPI word is 32-bits long
+#define MCSPI_CH0CONF_WL_S 7
+#define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held
+ // high during the active state. 1
+ // SPIEN is held low during the
+ // active state.
+#define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK.
+ // (only when the module is a Master
+ // SPI device). A programmable clock
+ // divider divides the SPI reference
+ // clock (CLKSPIREF) with a 4-bit
+ // value and results in a new clock
+ // SPICLK available to shift-in and
+ // shift-out data. By default the
+ // clock divider ratio has a power
+ // of two granularity when
+ // MCSPI_CHCONF[CLKG] is cleared
+ // Otherwise this register is the 4
+ // LSB bit of a 12-bit register
+ // concatenated with clock divider
+ // extension MCSPI_CHCTRL[EXTCLK]
+ // register.The value description
+ // below defines the clock ratio
+ // when MCSPI_CHCONF[CLKG] is set to
+ // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
+ // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
+ // 512 0xA 1024 0xB 2048 0xC 4096
+ // 0xD 8192 0xE 16384 0xF 32768
+#define MCSPI_CH0CONF_CLKD_S 2
+#define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held
+ // high during the active state 1
+ // SPICLK is held low during the
+ // active state
+#define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched
+ // on odd numbered edges of SPICLK.
+ // 1 Data are latched on even
+ // numbered edges of SPICLK.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH0STAT register.
+//
+//******************************************************************************
+#define MCSPI_CH0STAT_RXFFF 0x00000040
+#define MCSPI_CH0STAT_RXFFE 0x00000020
+#define MCSPI_CH0STAT_TXFFF 0x00000010
+#define MCSPI_CH0STAT_TXFFE 0x00000008
+#define MCSPI_CH0STAT_EOT 0x00000004
+#define MCSPI_CH0STAT_TXS 0x00000002
+#define MCSPI_CH0STAT_RXS 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register.
+//
+//******************************************************************************
+#define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This
+ // register is used to concatenate
+ // with MCSPI_CHCONF[CLKD] register
+ // for clock ratio only when
+ // granularity is one clock cycle
+ // (MCSPI_CHCONF[CLKG] set to 1).
+ // Then the max value reached is
+ // 4096 clock divider ratio. 0x00
+ // Clock ratio is CLKD + 1 0x01
+ // Clock ratio is CLKD + 1 + 16 0xFF
+ // Clock ratio is CLKD + 1 + 4080
+#define MCSPI_CH0CTRL_EXTCLK_S 8
+#define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i""
+ // is not active" 1 "Channel ""i""
+ // is active"
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_TX0 register.
+//
+//******************************************************************************
+#define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit
+#define MCSPI_TX0_TDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_RX0 register.
+//
+//******************************************************************************
+#define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data
+#define MCSPI_RX0_RDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH1CONF register.
+//
+//******************************************************************************
+#define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This
+ // register defines the granularity
+ // of channel clock divider: power
+ // of two or one clock cycle
+ // granularity. When this bit is set
+ // the register MCSPI_CHCTRL[EXTCLK]
+ // must be configured to reach a
+ // maximum of 4096 clock divider
+ // ratio. Then The clock divider
+ // ratio is a concatenation of
+ // MCSPI_CHCONF[CLKD] and
+ // MCSPI_CHCTRL[EXTCLK] values 0
+ // Clock granularity of power of two
+ // 1 One clock cycle ganularity
+#define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to receive data. 1 The
+ // buffer is used to receive data.
+#define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to transmit data. 1 The
+ // buffer is used to transmit data.
+#define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This
+ // 2-bits field defines the number
+ // of interface clock cycles between
+ // CS toggling and first or last
+ // edge of SPI clock. 0x0 0.5 clock
+ // cycle 0x1 1.5 clock cycle 0x2 2.5
+ // clock cycle 0x3 3.5 clock cycle
+#define MCSPI_CH1CONF_TCS1_S 25
+#define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit
+ // polarity is held to 0 during SPI
+ // transfer. 1 Start bit polarity is
+ // held to 1 during SPI transfer.
+#define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI
+ // transfer 0 Default SPI transfer
+ // length as specified by WL bit
+ // field 1 Start bit D/CX added
+ // before SPI transfer polarity is
+ // defined by MCSPI_CH1CONF[SBPOL]
+#define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep
+ // SPIEN active between SPI words.
+ // (single channel master mode only)
+ // 0 Writing 0 into this bit drives
+ // low the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it high when
+ // MCSPI_CHCONF(i)[EPOL]=1. 1
+ // Writing 1 into this bit drives
+ // high the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it low when
+ // MCSPI_CHCONF(i)[EPOL]=1
+#define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is
+ // deactivated (recommended for
+ // single SPI word transfer) 1 Turbo
+ // is activated to maximize the
+ // throughput for multi SPI words
+ // transfer.
+#define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0
+ // (SPIDAT[0]) selected for
+ // reception. 1 Data Line1
+ // (SPIDAT[1]) selected for
+ // reception
+#define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data
+ // line 1 (SPIDATAGZEN[1]) 0 Data
+ // Line1 (SPIDAT[1]) selected for
+ // transmission 1 No transmission on
+ // Data Line1 (SPIDAT[1])
+#define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data
+ // line 0 (SPIDATAGZEN[0]) 0 Data
+ // Line0 (SPIDAT[0]) selected for
+ // transmission 1 No transmission on
+ // Data Line0 (SPIDAT[0])
+#define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read
+ // request line is asserted when the
+ // channel is enabled and a new data
+ // is available in the receive
+ // register of the channel. The DMA
+ // Read request line is deasserted
+ // on read completion of the receive
+ // register of the channel. 0 DMA
+ // Read Request disabled 1 DMA Read
+ // Request enabled
+#define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write
+ // request line is asserted when The
+ // channel is enabled and the
+ // transmitter register of the
+ // channel is empty. The DMA Write
+ // request line is deasserted on
+ // load completion of the
+ // transmitter register of the
+ // channel. 0 DMA Write Request
+ // disabled 1 DMA Write Request
+ // enabled
+#define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0
+ // Transmit and Receive mode 0x1
+ // Receive only mode 0x2 Transmit
+ // only mode 0x3 Reserved
+#define MCSPI_CH1CONF_TRM_S 12
+#define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved
+ // 0x01 Reserved 0x02 Reserved 0x03
+ // The SPI word is 4-bits long 0x04
+ // The SPI word is 5-bits long 0x05
+ // The SPI word is 6-bits long 0x06
+ // The SPI word is 7-bits long 0x07
+ // The SPI word is 8-bits long 0x08
+ // The SPI word is 9-bits long 0x09
+ // The SPI word is 10-bits long 0x0A
+ // The SPI word is 11-bits long 0x0B
+ // The SPI word is 12-bits long 0x0C
+ // The SPI word is 13-bits long 0x0D
+ // The SPI word is 14-bits long 0x0E
+ // The SPI word is 15-bits long 0x0F
+ // The SPI word is 16-bits long 0x10
+ // The SPI word is 17-bits long 0x11
+ // The SPI word is 18-bits long 0x12
+ // The SPI word is 19-bits long 0x13
+ // The SPI word is 20-bits long 0x14
+ // The SPI word is 21-bits long 0x15
+ // The SPI word is 22-bits long 0x16
+ // The SPI word is 23-bits long 0x17
+ // The SPI word is 24-bits long 0x18
+ // The SPI word is 25-bits long 0x19
+ // The SPI word is 26-bits long 0x1A
+ // The SPI word is 27-bits long 0x1B
+ // The SPI word is 28-bits long 0x1C
+ // The SPI word is 29-bits long 0x1D
+ // The SPI word is 30-bits long 0x1E
+ // The SPI word is 31-bits long 0x1F
+ // The SPI word is 32-bits long
+#define MCSPI_CH1CONF_WL_S 7
+#define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held
+ // high during the active state. 1
+ // SPIEN is held low during the
+ // active state.
+#define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK.
+ // (only when the module is a Master
+ // SPI device). A programmable clock
+ // divider divides the SPI reference
+ // clock (CLKSPIREF) with a 4-bit
+ // value and results in a new clock
+ // SPICLK available to shift-in and
+ // shift-out data. By default the
+ // clock divider ratio has a power
+ // of two granularity when
+ // MCSPI_CHCONF[CLKG] is cleared
+ // Otherwise this register is the 4
+ // LSB bit of a 12-bit register
+ // concatenated with clock divider
+ // extension MCSPI_CHCTRL[EXTCLK]
+ // register.The value description
+ // below defines the clock ratio
+ // when MCSPI_CHCONF[CLKG] is set to
+ // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
+ // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
+ // 512 0xA 1024 0xB 2048 0xC 4096
+ // 0xD 8192 0xE 16384 0xF 32768
+#define MCSPI_CH1CONF_CLKD_S 2
+#define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held
+ // high during the active state 1
+ // SPICLK is held low during the
+ // active state
+#define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched
+ // on odd numbered edges of SPICLK.
+ // 1 Data are latched on even
+ // numbered edges of SPICLK.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH1STAT register.
+//
+//******************************************************************************
+#define MCSPI_CH1STAT_RXFFF 0x00000040
+#define MCSPI_CH1STAT_RXFFE 0x00000020
+#define MCSPI_CH1STAT_TXFFF 0x00000010
+#define MCSPI_CH1STAT_TXFFE 0x00000008
+#define MCSPI_CH1STAT_EOT 0x00000004
+#define MCSPI_CH1STAT_TXS 0x00000002
+#define MCSPI_CH1STAT_RXS 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register.
+//
+//******************************************************************************
+#define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This
+ // register is used to concatenate
+ // with MCSPI_CHCONF[CLKD] register
+ // for clock ratio only when
+ // granularity is one clock cycle
+ // (MCSPI_CHCONF[CLKG] set to 1).
+ // Then the max value reached is
+ // 4096 clock divider ratio. 0x00
+ // Clock ratio is CLKD + 1 0x01
+ // Clock ratio is CLKD + 1 + 16 0xFF
+ // Clock ratio is CLKD + 1 + 4080
+#define MCSPI_CH1CTRL_EXTCLK_S 8
+#define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i""
+ // is not active" 1 "Channel ""i""
+ // is active"
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_TX1 register.
+//
+//******************************************************************************
+#define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit
+#define MCSPI_TX1_TDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_RX1 register.
+//
+//******************************************************************************
+#define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data
+#define MCSPI_RX1_RDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH2CONF register.
+//
+//******************************************************************************
+#define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This
+ // register defines the granularity
+ // of channel clock divider: power
+ // of two or one clock cycle
+ // granularity. When this bit is set
+ // the register MCSPI_CHCTRL[EXTCLK]
+ // must be configured to reach a
+ // maximum of 4096 clock divider
+ // ratio. Then The clock divider
+ // ratio is a concatenation of
+ // MCSPI_CHCONF[CLKD] and
+ // MCSPI_CHCTRL[EXTCLK] values 0
+ // Clock granularity of power of two
+ // 1 One clock cycle ganularity
+#define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to receive data. 1 The
+ // buffer is used to receive data.
+#define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to transmit data. 1 The
+ // buffer is used to transmit data.
+#define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This
+ // 2-bits field defines the number
+ // of interface clock cycles between
+ // CS toggling and first or last
+ // edge of SPI clock. 0x0 0.5 clock
+ // cycle 0x1 1.5 clock cycle 0x2 2.5
+ // clock cycle 0x3 3.5 clock cycle
+#define MCSPI_CH2CONF_TCS2_S 25
+#define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit
+ // polarity is held to 0 during SPI
+ // transfer. 1 Start bit polarity is
+ // held to 1 during SPI transfer.
+#define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI
+ // transfer 0 Default SPI transfer
+ // length as specified by WL bit
+ // field 1 Start bit D/CX added
+ // before SPI transfer polarity is
+ // defined by MCSPI_CH2CONF[SBPOL]
+#define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep
+ // SPIEN active between SPI words.
+ // (single channel master mode only)
+ // 0 Writing 0 into this bit drives
+ // low the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it high when
+ // MCSPI_CHCONF(i)[EPOL]=1. 1
+ // Writing 1 into this bit drives
+ // high the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it low when
+ // MCSPI_CHCONF(i)[EPOL]=1
+#define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is
+ // deactivated (recommended for
+ // single SPI word transfer) 1 Turbo
+ // is activated to maximize the
+ // throughput for multi SPI words
+ // transfer.
+#define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0
+ // (SPIDAT[0]) selected for
+ // reception. 1 Data Line1
+ // (SPIDAT[1]) selected for
+ // reception
+#define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data
+ // line 1 (SPIDATAGZEN[1]) 0 Data
+ // Line1 (SPIDAT[1]) selected for
+ // transmission 1 No transmission on
+ // Data Line1 (SPIDAT[1])
+#define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data
+ // line 0 (SPIDATAGZEN[0]) 0 Data
+ // Line0 (SPIDAT[0]) selected for
+ // transmission 1 No transmission on
+ // Data Line0 (SPIDAT[0])
+#define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read
+ // request line is asserted when the
+ // channel is enabled and a new data
+ // is available in the receive
+ // register of the channel. The DMA
+ // Read request line is deasserted
+ // on read completion of the receive
+ // register of the channel. 0 DMA
+ // Read Request disabled 1 DMA Read
+ // Request enabled
+#define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write
+ // request line is asserted when The
+ // channel is enabled and the
+ // transmitter register of the
+ // channel is empty. The DMA Write
+ // request line is deasserted on
+ // load completion of the
+ // transmitter register of the
+ // channel. 0 DMA Write Request
+ // disabled 1 DMA Write Request
+ // enabled
+#define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0
+ // Transmit and Receive mode 0x1
+ // Receive only mode 0x2 Transmit
+ // only mode 0x3 Reserved
+#define MCSPI_CH2CONF_TRM_S 12
+#define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved
+ // 0x01 Reserved 0x02 Reserved 0x03
+ // The SPI word is 4-bits long 0x04
+ // The SPI word is 5-bits long 0x05
+ // The SPI word is 6-bits long 0x06
+ // The SPI word is 7-bits long 0x07
+ // The SPI word is 8-bits long 0x08
+ // The SPI word is 9-bits long 0x09
+ // The SPI word is 10-bits long 0x0A
+ // The SPI word is 11-bits long 0x0B
+ // The SPI word is 12-bits long 0x0C
+ // The SPI word is 13-bits long 0x0D
+ // The SPI word is 14-bits long 0x0E
+ // The SPI word is 15-bits long 0x0F
+ // The SPI word is 16-bits long 0x10
+ // The SPI word is 17-bits long 0x11
+ // The SPI word is 18-bits long 0x12
+ // The SPI word is 19-bits long 0x13
+ // The SPI word is 20-bits long 0x14
+ // The SPI word is 21-bits long 0x15
+ // The SPI word is 22-bits long 0x16
+ // The SPI word is 23-bits long 0x17
+ // The SPI word is 24-bits long 0x18
+ // The SPI word is 25-bits long 0x19
+ // The SPI word is 26-bits long 0x1A
+ // The SPI word is 27-bits long 0x1B
+ // The SPI word is 28-bits long 0x1C
+ // The SPI word is 29-bits long 0x1D
+ // The SPI word is 30-bits long 0x1E
+ // The SPI word is 31-bits long 0x1F
+ // The SPI word is 32-bits long
+#define MCSPI_CH2CONF_WL_S 7
+#define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held
+ // high during the active state. 1
+ // SPIEN is held low during the
+ // active state.
+#define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK.
+ // (only when the module is a Master
+ // SPI device). A programmable clock
+ // divider divides the SPI reference
+ // clock (CLKSPIREF) with a 4-bit
+ // value and results in a new clock
+ // SPICLK available to shift-in and
+ // shift-out data. By default the
+ // clock divider ratio has a power
+ // of two granularity when
+ // MCSPI_CHCONF[CLKG] is cleared
+ // Otherwise this register is the 4
+ // LSB bit of a 12-bit register
+ // concatenated with clock divider
+ // extension MCSPI_CHCTRL[EXTCLK]
+ // register.The value description
+ // below defines the clock ratio
+ // when MCSPI_CHCONF[CLKG] is set to
+ // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
+ // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
+ // 512 0xA 1024 0xB 2048 0xC 4096
+ // 0xD 8192 0xE 16384 0xF 32768
+#define MCSPI_CH2CONF_CLKD_S 2
+#define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held
+ // high during the active state 1
+ // SPICLK is held low during the
+ // active state
+#define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched
+ // on odd numbered edges of SPICLK.
+ // 1 Data are latched on even
+ // numbered edges of SPICLK.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH2STAT register.
+//
+//******************************************************************************
+#define MCSPI_CH2STAT_RXFFF 0x00000040
+#define MCSPI_CH2STAT_RXFFE 0x00000020
+#define MCSPI_CH2STAT_TXFFF 0x00000010
+#define MCSPI_CH2STAT_TXFFE 0x00000008
+#define MCSPI_CH2STAT_EOT 0x00000004
+#define MCSPI_CH2STAT_TXS 0x00000002
+#define MCSPI_CH2STAT_RXS 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register.
+//
+//******************************************************************************
+#define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This
+ // register is used to concatenate
+ // with MCSPI_CHCONF[CLKD] register
+ // for clock ratio only when
+ // granularity is one clock cycle
+ // (MCSPI_CHCONF[CLKG] set to 1).
+ // Then the max value reached is
+ // 4096 clock divider ratio. 0x00
+ // Clock ratio is CLKD + 1 0x01
+ // Clock ratio is CLKD + 1 + 16 0xFF
+ // Clock ratio is CLKD + 1 + 4080
+#define MCSPI_CH2CTRL_EXTCLK_S 8
+#define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i""
+ // is not active" 1 "Channel ""i""
+ // is active"
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_TX2 register.
+//
+//******************************************************************************
+#define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit
+#define MCSPI_TX2_TDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_RX2 register.
+//
+//******************************************************************************
+#define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data
+#define MCSPI_RX2_RDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH3CONF register.
+//
+//******************************************************************************
+#define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This
+ // register defines the granularity
+ // of channel clock divider: power
+ // of two or one clock cycle
+ // granularity. When this bit is set
+ // the register MCSPI_CHCTRL[EXTCLK]
+ // must be configured to reach a
+ // maximum of 4096 clock divider
+ // ratio. Then The clock divider
+ // ratio is a concatenation of
+ // MCSPI_CHCONF[CLKD] and
+ // MCSPI_CHCTRL[EXTCLK] values 0
+ // Clock granularity of power of two
+ // 1 One clock cycle ganularity
+#define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to receive data. 1 The
+ // buffer is used to receive data.
+#define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only
+ // one channel can have this bit
+ // field set. 0 The buffer is not
+ // used to transmit data. 1 The
+ // buffer is used to transmit data.
+#define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This
+ // 2-bits field defines the number
+ // of interface clock cycles between
+ // CS toggling and first or last
+ // edge of SPI clock. 0x0 0.5 clock
+ // cycle 0x1 1.5 clock cycle 0x2 2.5
+ // clock cycle 0x3 3.5 clock cycle
+#define MCSPI_CH3CONF_TCS3_S 25
+#define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit
+ // polarity is held to 0 during SPI
+ // transfer. 1 Start bit polarity is
+ // held to 1 during SPI transfer.
+#define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI
+ // transfer 0 Default SPI transfer
+ // length as specified by WL bit
+ // field 1 Start bit D/CX added
+ // before SPI transfer polarity is
+ // defined by MCSPI_CH3CONF[SBPOL]
+#define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep
+ // SPIEN active between SPI words.
+ // (single channel master mode only)
+ // 0 Writing 0 into this bit drives
+ // low the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it high when
+ // MCSPI_CHCONF(i)[EPOL]=1. 1
+ // Writing 1 into this bit drives
+ // high the SPIEN line when
+ // MCSPI_CHCONF(i)[EPOL]=0 and
+ // drives it low when
+ // MCSPI_CHCONF(i)[EPOL]=1
+#define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is
+ // deactivated (recommended for
+ // single SPI word transfer) 1 Turbo
+ // is activated to maximize the
+ // throughput for multi SPI words
+ // transfer.
+#define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0
+ // (SPIDAT[0]) selected for
+ // reception. 1 Data Line1
+ // (SPIDAT[1]) selected for
+ // reception
+#define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data
+ // line 1 (SPIDATAGZEN[1]) 0 Data
+ // Line1 (SPIDAT[1]) selected for
+ // transmission 1 No transmission on
+ // Data Line1 (SPIDAT[1])
+#define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data
+ // line 0 (SPIDATAGZEN[0]) 0 Data
+ // Line0 (SPIDAT[0]) selected for
+ // transmission 1 No transmission on
+ // Data Line0 (SPIDAT[0])
+#define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read
+ // request line is asserted when the
+ // channel is enabled and a new data
+ // is available in the receive
+ // register of the channel. The DMA
+ // Read request line is deasserted
+ // on read completion of the receive
+ // register of the channel. 0 DMA
+ // Read Request disabled 1 DMA Read
+ // Request enabled
+#define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write
+ // request line is asserted when The
+ // channel is enabled and the
+ // transmitter register of the
+ // channel is empty. The DMA Write
+ // request line is deasserted on
+ // load completion of the
+ // transmitter register of the
+ // channel. 0 DMA Write Request
+ // disabled 1 DMA Write Request
+ // enabled
+#define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0
+ // Transmit and Receive mode 0x1
+ // Receive only mode 0x2 Transmit
+ // only mode 0x3 Reserved
+#define MCSPI_CH3CONF_TRM_S 12
+#define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved
+ // 0x01 Reserved 0x02 Reserved 0x03
+ // The SPI word is 4-bits long 0x04
+ // The SPI word is 5-bits long 0x05
+ // The SPI word is 6-bits long 0x06
+ // The SPI word is 7-bits long 0x07
+ // The SPI word is 8-bits long 0x08
+ // The SPI word is 9-bits long 0x09
+ // The SPI word is 10-bits long 0x0A
+ // The SPI word is 11-bits long 0x0B
+ // The SPI word is 12-bits long 0x0C
+ // The SPI word is 13-bits long 0x0D
+ // The SPI word is 14-bits long 0x0E
+ // The SPI word is 15-bits long 0x0F
+ // The SPI word is 16-bits long 0x10
+ // The SPI word is 17-bits long 0x11
+ // The SPI word is 18-bits long 0x12
+ // The SPI word is 19-bits long 0x13
+ // The SPI word is 20-bits long 0x14
+ // The SPI word is 21-bits long 0x15
+ // The SPI word is 22-bits long 0x16
+ // The SPI word is 23-bits long 0x17
+ // The SPI word is 24-bits long 0x18
+ // The SPI word is 25-bits long 0x19
+ // The SPI word is 26-bits long 0x1A
+ // The SPI word is 27-bits long 0x1B
+ // The SPI word is 28-bits long 0x1C
+ // The SPI word is 29-bits long 0x1D
+ // The SPI word is 30-bits long 0x1E
+ // The SPI word is 31-bits long 0x1F
+ // The SPI word is 32-bits long
+#define MCSPI_CH3CONF_WL_S 7
+#define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held
+ // high during the active state. 1
+ // SPIEN is held low during the
+ // active state.
+#define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK.
+ // (only when the module is a Master
+ // SPI device). A programmable clock
+ // divider divides the SPI reference
+ // clock (CLKSPIREF) with a 4-bit
+ // value and results in a new clock
+ // SPICLK available to shift-in and
+ // shift-out data. By default the
+ // clock divider ratio has a power
+ // of two granularity when
+ // MCSPI_CHCONF[CLKG] is cleared
+ // Otherwise this register is the 4
+ // LSB bit of a 12-bit register
+ // concatenated with clock divider
+ // extension MCSPI_CHCTRL[EXTCLK]
+ // register.The value description
+ // below defines the clock ratio
+ // when MCSPI_CHCONF[CLKG] is set to
+ // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16
+ // 0x5 32 0x6 64 0x7 128 0x8 256 0x9
+ // 512 0xA 1024 0xB 2048 0xC 4096
+ // 0xD 8192 0xE 16384 0xF 32768
+#define MCSPI_CH3CONF_CLKD_S 2
+#define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held
+ // high during the active state 1
+ // SPICLK is held low during the
+ // active state
+#define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched
+ // on odd numbered edges of SPICLK.
+ // 1 Data are latched on even
+ // numbered edges of SPICLK.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH3STAT register.
+//
+//******************************************************************************
+#define MCSPI_CH3STAT_RXFFF 0x00000040
+#define MCSPI_CH3STAT_RXFFE 0x00000020
+#define MCSPI_CH3STAT_TXFFF 0x00000010
+#define MCSPI_CH3STAT_TXFFE 0x00000008
+#define MCSPI_CH3STAT_EOT 0x00000004
+#define MCSPI_CH3STAT_TXS 0x00000002
+#define MCSPI_CH3STAT_RXS 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register.
+//
+//******************************************************************************
+#define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This
+ // register is used to concatenate
+ // with MCSPI_CHCONF[CLKD] register
+ // for clock ratio only when
+ // granularity is one clock cycle
+ // (MCSPI_CHCONF[CLKG] set to 1).
+ // Then the max value reached is
+ // 4096 clock divider ratio. 0x00
+ // Clock ratio is CLKD + 1 0x01
+ // Clock ratio is CLKD + 1 + 16 0xFF
+ // Clock ratio is CLKD + 1 + 4080
+#define MCSPI_CH3CTRL_EXTCLK_S 8
+#define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i""
+ // is not active" 1 "Channel ""i""
+ // is active"
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_TX3 register.
+//
+//******************************************************************************
+#define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit
+#define MCSPI_TX3_TDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_RX3 register.
+//
+//******************************************************************************
+#define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data
+#define MCSPI_RX3_RDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register.
+//
+//******************************************************************************
+#define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register
+ // holds the programmable value of
+ // number of SPI word to be
+ // transferred on channel which is
+ // using the FIFO buffer.When
+ // transfer had started a read back
+ // in this register returns the
+ // current SPI word transfer index.
+ // 0x0000 Counter not used 0x0001
+ // one word 0xFFFE 65534 spi word
+ // 0xFFFF 65535 spi word
+#define MCSPI_XFERLEVEL_WCNT_S 16
+#define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register
+ // holds the programmable almost
+ // full level value used to
+ // determine almost full buffer
+ // condition. If the user wants an
+ // interrupt or a DMA read request
+ // to be issued during a receive
+ // operation when the data buffer
+ // holds at least n bytes then the
+ // buffer MCSPI_MODULCTRL[AFL] must
+ // be set with n-1.The size of this
+ // register is defined by the
+ // generic parameter FFNBYTE. 0x00
+ // one byte 0x01 2 bytes 0xFE
+ // 255bytes 0xFF 256bytes
+#define MCSPI_XFERLEVEL_AFL_S 8
+#define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register
+ // holds the programmable almost
+ // empty level value used to
+ // determine almost empty buffer
+ // condition. If the user wants an
+ // interrupt or a DMA write request
+ // to be issued during a transmit
+ // operation when the data buffer is
+ // able to receive n bytes then the
+ // buffer MCSPI_MODULCTRL[AEL] must
+ // be set with n-1. 0x00 one byte
+ // 0x01 2 bytes 0xFE 255 bytes 0xFF
+ // 256bytes
+#define MCSPI_XFERLEVEL_AEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_DAFTX register.
+//
+//******************************************************************************
+#define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA
+ // 256 bit aligned address. "This
+ // Register is only is used when
+ // MCSPI_MODULCTRL[FDAA] is set to
+ // ""1"" and only one of the
+ // MCSPI_CH(i)CONF[FFEW] of enabled
+ // channels is set. If these
+ // conditions are not respected any
+ // access to this register return a
+ // null value."
+#define MCSPI_DAFTX_DAFTDATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MCSPI_O_DAFRX register.
+//
+//******************************************************************************
+#define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA
+ // 256 bit aligned address. "This
+ // Register is only is used when
+ // MCSPI_MODULCTRL[FDAA] is set to
+ // ""1"" and only one of the
+ // MCSPI_CH(i)CONF[FFEW] of enabled
+ // channels is set. If these
+ // conditions are not respected any
+ // access to this register return a
+ // null value."
+#define MCSPI_DAFRX_DAFRDATA_S 0
+
+
+
+#endif // __HW_MCSPI_H__
diff --git a/cc3200/hal/inc/hw_memmap.h b/cc3200/hal/inc/hw_memmap.h
new file mode 100644
index 0000000000..244905dd20
--- /dev/null
+++ b/cc3200/hal/inc/hw_memmap.h
@@ -0,0 +1,84 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals on the slave_1 interface.
+//
+//*****************************************************************************
+#define FLASH_BASE 0x01000000
+#define SRAM_BASE 0x20000000
+#define WDT_BASE 0x40000000
+#define GPIOA0_BASE 0x40004000
+#define GPIOA1_BASE 0x40005000
+#define GPIOA2_BASE 0x40006000
+#define GPIOA3_BASE 0x40007000
+#define GPIOA4_BASE 0x40024000
+#define UARTA0_BASE 0x4000C000
+#define UARTA1_BASE 0x4000D000
+#define I2CA0_BASE 0x40020000
+#define TIMERA0_BASE 0x40030000
+#define TIMERA1_BASE 0x40031000
+#define TIMERA2_BASE 0x40032000
+#define TIMERA3_BASE 0x40033000
+#define STACKDIE_CTRL_BASE 0x400F5000
+#define COMMON_REG_BASE 0x400F7000
+#define FLASH_CONTROL_BASE 0x400FD000
+#define SYSTEM_CONTROL_BASE 0x400FE000
+#define UDMA_BASE 0x400FF000
+#define SDHOST_BASE 0x44010000
+#define CAMERA_BASE 0x44018000
+#define I2S_BASE 0x4401C000
+#define SSPI_BASE 0x44020000
+#define GSPI_BASE 0x44021000
+#define LSPI_BASE 0x44022000
+#define ARCM_BASE 0x44025000
+#define APPS_CONFIG_BASE 0x44026000
+#define GPRCM_BASE 0x4402D000
+#define OCP_SHARED_BASE 0x4402E000
+#define ADC_BASE 0x4402E800
+#define HIB1P2_BASE 0x4402F000
+#define HIB3P3_BASE 0x4402F800
+#define DTHE_BASE 0x44030000
+#define SHAMD5_BASE 0x44035000
+#define AES_BASE 0x44037000
+#define DES_BASE 0x44039000
+
+
+#endif // __HW_MEMMAP_H__
diff --git a/cc3200/hal/inc/hw_mmchs.h b/cc3200/hal/inc/hw_mmchs.h
new file mode 100644
index 0000000000..3096d13a99
--- /dev/null
+++ b/cc3200/hal/inc/hw_mmchs.h
@@ -0,0 +1,1919 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_MMCHS_H__
+#define __HW_MMCHS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the MMCHS register offsets.
+//
+//*****************************************************************************
+#define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R)
+ // Used by software to track
+ // features bugs and compatibility
+#define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP
+ // module's hardware configuration
+ // i.e. typically the module's HDL
+ // generics (if any). Actual field
+ // format and encoding is up to the
+ // module's designer to decide.
+#define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration
+#define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register
+ // This register allows controlling
+ // various parameters of the OCP
+ // interface.
+#define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This
+ // register provides status
+ // information about the module
+ // excluding the interrupt status
+ // information
+#define MMCHS_O_CSRE 0x00000124 // Card status response error This
+ // register enables the host
+ // controller to detect card status
+ // errors of response type R1 R1b
+ // for all cards and of R5 R5b and
+ // R6 response for cards types SD or
+ // SDIO. When a bit MMCHS_CSRE[i] is
+ // set to 1 if the corresponding bit
+ // at the same position in the
+ // response MMCHS_RSP0[i] is set to
+ // 1 the host controller indicates a
+ // card error (MMCHS_STAT[CERR])
+ // interrupt status to avoid the
+ // host driver reading the response
+ // register (MMCHS_RSP0). Note: No
+ // automatic card error detection
+ // for autoCMD12 is implemented; the
+ // host system has to check
+ // autoCMD12 response register
+ // (MMCHS_RESP76) for possible card
+ // errors.
+#define MMCHS_O_SYSTEST 0x00000128 // System Test register This
+ // register is used to control the
+ // signals that connect to I/O pins
+ // when the module is configured in
+ // system test (SYSTEST) mode for
+ // boundary connectivity
+ // verification. Note: In SYSTEST
+ // mode a write into MMCHS_CMD
+ // register will not start a
+ // transfer. The buffer behaves as a
+ // stack accessible only by the
+ // local host (push and pop
+ // operations). In this mode the
+ // Transfer Block Size
+ // (MMCHS_BLK[BLEN]) and the Blocks
+ // count for current transfer
+ // (MMCHS_BLK[NBLK]) are needed to
+ // generate a Buffer write ready
+ // interrupt (MMCHS_STAT[BWR]) or a
+ // Buffer read ready interrupt
+ // (MMCHS_STAT[BRR]) and DMA
+ // requests if enabled.
+#define MMCHS_O_CON 0x0000012C // Configuration register This
+ // register is used: - to select the
+ // functional mode or the SYSTEST
+ // mode for any card. - to send an
+ // initialization sequence to any
+ // card. - to enable the detection
+ // on DAT[1] of a card interrupt for
+ // SDIO cards only. and also to
+ // configure : - specific data and
+ // command transfers for MMC cards
+ // only. - the parameters related to
+ // the card detect and write protect
+ // input signals.
+#define MMCHS_O_PWCNT 0x00000130 // Power counter register This
+ // register is used to program a mmc
+ // counter to delay command
+ // transfers after activating the
+ // PAD power this value depends on
+ // PAD characteristics and voltage.
+#define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration
+ // register MMCHS_BLK[BLEN] is the
+ // block size register.
+ // MMCHS_BLK[NBLK] is the block
+ // count register. This register
+ // shall be used for any card.
+#define MMCHS_O_ARG 0x00000208 // Command argument Register This
+ // register contains command
+ // argument specified as bit 39-8 of
+ // Command-Format These registers
+ // must be initialized prior to
+ // sending the command itself to the
+ // card (write action into the
+ // register MMCHS_CMD register).
+ // Only exception is for a command
+ // index specifying stuff bits in
+ // arguments making a write
+ // unnecessary.
+#define MMCHS_O_CMD 0x0000020C // Command and transfer mode
+ // register MMCHS_CMD[31:16] = the
+ // command register MMCHS_CMD[15:0]
+ // = the transfer mode. This
+ // register configures the data and
+ // command transfers. A write into
+ // the most significant byte send
+ // the command. A write into
+ // MMCHS_CMD[15:0] registers during
+ // data transfer has no effect. This
+ // register shall be used for any
+ // card. Note: In SYSTEST mode a
+ // write into MMCHS_CMD register
+ // will not start a transfer.
+#define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register
+ // This 32-bit register holds bits
+ // positions [31:0] of command
+ // response type
+ // R1/R1b/R2/R3/R4/R5/R5b/R6
+#define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register
+ // This 32-bit register holds bits
+ // positions [63:32] of command
+ // response type R2
+#define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register
+ // This 32-bit register holds bits
+ // positions [95:64] of command
+ // response type R2
+#define MMCHS_O_RSP76 0x0000021C // Command response[127:96]
+ // Register This 32-bit register
+ // holds bits positions [127:96] of
+ // command response type R2
+#define MMCHS_O_DATA 0x00000220 // Data Register This register is
+ // the 32-bit entry point of the
+ // buffer for read or write data
+ // transfers. The buffer size is
+ // 32bits x256(1024 bytes). Bytes
+ // within a word are stored and read
+ // in little endian format. This
+ // buffer can be used as two 512
+ // byte buffers to transfer data
+ // efficiently without reducing the
+ // throughput. Sequential and
+ // contiguous access is necessary to
+ // increment the pointer correctly.
+ // Random or skipped access is not
+ // allowed. In little endian if the
+ // local host accesses this register
+ // byte-wise or 16bit-wise the least
+ // significant byte (bits [7:0])
+ // must always be written/read
+ // first. The update of the buffer
+ // address is done on the most
+ // significant byte write for full
+ // 32-bit DATA register or on the
+ // most significant byte of the last
+ // word of block transfer. Example
+ // 1: Byte or 16-bit access
+ // Mbyteen[3:0]=0001 (1-byte) =>
+ // Mbyteen[3:0]=0010 (1-byte) =>
+ // Mbyteen[3:0]=1100 (2-bytes) OK
+ // Mbyteen[3:0]=0001 (1-byte) =>
+ // Mbyteen[3:0]=0010 (1-byte) =>
+ // Mbyteen[3:0]=0100 (1-byte) OK
+ // Mbyteen[3:0]=0001 (1-byte) =>
+ // Mbyteen[3:0]=0010 (1-byte) =>
+ // Mbyteen[3:0]=1000 (1-byte) Bad
+#define MMCHS_O_PSTATE 0x00000224 // Present state register The Host
+ // can get status of the Host
+ // Controller from this 32-bit read
+ // only register.
+#define MMCHS_O_HCTL 0x00000228 // Control register This register
+ // defines the host controls to set
+ // power wakeup and transfer
+ // parameters. MMCHS_HCTL[31:24] =
+ // Wakeup control MMCHS_HCTL[23:16]
+ // = Block gap control
+ // MMCHS_HCTL[15:8] = Power control
+ // MMCHS_HCTL[7:0] = Host control
+#define MMCHS_O_SYSCTL 0x0000022C // SD system control register This
+ // register defines the system
+ // controls to set software resets
+ // clock frequency management and
+ // data timeout. MMCHS_SYSCTL[31:24]
+ // = Software resets
+ // MMCHS_SYSCTL[23:16] = Timeout
+ // control MMCHS_SYSCTL[15:0] =
+ // Clock control
+#define MMCHS_O_STAT 0x00000230 // Interrupt status register The
+ // interrupt status regroups all the
+ // status of the module internal
+ // events that can generate an
+ // interrupt. MMCHS_STAT[31:16] =
+ // Error Interrupt Status
+ // MMCHS_STAT[15:0] = Normal
+ // Interrupt Status
+#define MMCHS_O_IE 0x00000234 // Interrupt SD enable register
+ // This register allows to
+ // enable/disable the module to set
+ // status bits on an event-by-event
+ // basis. MMCHS_IE[31:16] = Error
+ // Interrupt Status Enable
+ // MMCHS_IE[15:0] = Normal Interrupt
+ // Status Enable
+#define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register
+ // This register allows to
+ // enable/disable the module
+ // internal sources of status on an
+ // event-by-event basis.
+ // MMCHS_ISE[31:16] = Error
+ // Interrupt Signal Enable
+ // MMCHS_ISE[15:0] = Normal
+ // Interrupt Signal Enable
+#define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register
+ // The host driver may determine
+ // which of the errors cases related
+ // to Auto CMD12 has occurred by
+ // checking this MMCHS_AC12 register
+ // when an Auto CMD12 Error
+ // interrupt occurs. This register
+ // is valid only when Auto CMD12 is
+ // enabled (MMCHS_CMD[ACEN]) and
+ // Auto CMD12Error (MMCHS_STAT[ACE])
+ // is set to 1. Note: These bits are
+ // automatically reset when starting
+ // a new adtc command with data.
+#define MMCHS_O_CAPA 0x00000240 // Capabilities register This
+ // register lists the capabilities
+ // of the MMC/SD/SDIO host
+ // controller.
+#define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities
+ // Register This register indicates
+ // the maximum current capability
+ // for each voltage. The value is
+ // meaningful if the voltage support
+ // is set in the capabilities
+ // register (MMCHS_CAPA).
+ // Initialization of this register
+ // (via a write access to this
+ // register) depends on the system
+ // capabilities. The host driver
+ // shall not modify this register
+ // after the initilaization. This
+ // register is only reinitialized by
+ // a hard reset (via RESETN signal)
+#define MMCHS_O_FE 0x00000250 // Force Event Register for Error
+ // Interrupt status The force Event
+ // Register is not a physically
+ // implemented register. Rather it
+ // is an address at which the Error
+ // Interrupt Status register can be
+ // written. The effect of a write to
+ // this address will be reflected in
+ // the Error Interrupt Status
+ // Register if corresponding bit of
+ // the Error Interrupt Status Enable
+ // Register is set.
+#define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When
+ // ADMA Error Interrupt is occurred
+ // the ADMA Error States field in
+ // this register holds the ADMA
+ // state and the ADMA System Address
+ // Register holds the address around
+ // the error descriptor. For
+ // recovering the error the Host
+ // Driver requires the ADMA state to
+ // identify the error descriptor
+ // address as follows: ST_STOP:
+ // Previous location set in the ADMA
+ // System Address register is the
+ // error descriptor address ST_FDS:
+ // Current location set in the ADMA
+ // System Address register is the
+ // error descriptor address ST_CADR:
+ // This sate is never set because do
+ // not generate ADMA error in this
+ // state. ST_TFR: Previous location
+ // set in the ADMA System Address
+ // register is the error descriptor
+ // address In case of write
+ // operation the Host Driver should
+ // use ACMD22 to get the number of
+ // written block rather than using
+ // this information since unwritten
+ // data may exist in the Host
+ // Controller. The Host Controller
+ // generates the ADMA Error
+ // Interrupt when it detects invalid
+ // descriptor data (Valid=0) at the
+ // ST_FDS state. In this case ADMA
+ // Error State indicates that an
+ // error occurs at ST_FDS state. The
+ // Host Driver may find that the
+ // Valid bit is not set in the error
+ // descriptor.
+#define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits
+#define MMCHS_O_REV 0x000002FC // Versions Register This register
+ // contains the hard coded RTL
+ // vendor revision number the
+ // version number of SD
+ // specification compliancy and a
+ // slot status bit. MMCHS_REV[31:16]
+ // = Host controller version
+ // MMCHS_REV[15:0] = Slot Interrupt
+ // Status
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_HL_REV register.
+//
+//******************************************************************************
+#define MMCHS_HL_REV_SCHEME_M 0xC0000000
+#define MMCHS_HL_REV_SCHEME_S 30
+#define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software
+ // compatible module family. If
+ // there is no level of software
+ // compatibility a new Func number
+ // (and hence REVISION) should be
+ // assigned.
+#define MMCHS_HL_REV_FUNC_S 16
+#define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
+ // design owner. RTL follows a
+ // numbering such as X.Y.R.Z which
+ // are explained in this table. R
+ // changes ONLY when: (1) PDS
+ // uploads occur which may have been
+ // due to spec changes (2) Bug fixes
+ // occur (3) Resets to '0' when X or
+ // Y changes. Design team has an
+ // internal 'Z' (customer invisible)
+ // number which increments on every
+ // drop that happens due to DV and
+ // RTL updates. Z resets to 0 when R
+ // increments.
+#define MMCHS_HL_REV_R_RTL_S 11
+#define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by
+ // IP specification owner. X changes
+ // ONLY when: (1) There is a major
+ // feature addition. An example
+ // would be adding Master Mode to
+ // Utopia Level2. The Func field (or
+ // Class/Type in old PID format)
+ // will remain the same. X does NOT
+ // change due to: (1) Bug fixes (2)
+ // Change in feature parameters.
+#define MMCHS_HL_REV_X_MAJOR_S 8
+#define MMCHS_HL_REV_CUSTOM_M 0x000000C0
+#define MMCHS_HL_REV_CUSTOM_S 6
+#define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by
+ // IP specification owner. Y changes
+ // ONLY when: (1) Features are
+ // scaled (up or down). Flexibility
+ // exists in that this feature
+ // scalability may either be
+ // represented in the Y change or a
+ // specific register in the IP that
+ // indicates which features are
+ // exactly available. (2) When
+ // feature creeps from Is-Not list
+ // to Is list. But this may not be
+ // the case once it sees silicon; in
+ // which case X will change. Y does
+ // NOT change due to: (1) Bug fixes
+ // (2) Typos or clarifications (3)
+ // major functional/feature
+ // change/addition/deletion. Instead
+ // these changes may be reflected
+ // via R S X as applicable. Spec
+ // owner maintains a
+ // customer-invisible number 'S'
+ // which changes due to: (1)
+ // Typos/clarifications (2) Bug
+ // documentation. Note that this bug
+ // is not due to a spec change but
+ // due to implementation.
+ // Nevertheless the spec tracks the
+ // IP bugs. An RTL release (say for
+ // silicon PG1.1) that occurs due to
+ // bug fix should document the
+ // corresponding spec number (X.Y.S)
+ // in its release notes.
+#define MMCHS_HL_REV_Y_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register.
+//
+//******************************************************************************
+#define MMCHS_HL_HWINFO_RETMODE 0x00000040
+#define MMCHS_HL_HWINFO_MEM_SIZE_M \
+ 0x0000003C
+
+#define MMCHS_HL_HWINFO_MEM_SIZE_S 2
+#define MMCHS_HL_HWINFO_MERGE_MEM \
+ 0x00000002
+
+#define MMCHS_HL_HWINFO_MADMA_EN \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// MMCHS_O_HL_SYSCONFIG register.
+//
+//******************************************************************************
+#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \
+ 0x00000030 // Configuration of the local
+ // initiator state management mode.
+ // By definition initiator may
+ // generate read/write transaction
+ // as long as it is out of STANDBY
+ // state. 0x0 Force-standby mode:
+ // local initiator is
+ // unconditionally placed in standby
+ // state.Backup mode for debug only.
+ // 0x1 No-standby mode: local
+ // initiator is unconditionally
+ // placed out of standby
+ // state.Backup mode for debug only.
+ // 0x2 Smart-standby mode: local
+ // initiator standby status depends
+ // on local conditions i.e. the
+ // module's functional requirement
+ // from the initiator.IP module
+ // shall not generate
+ // (initiator-related) wakeup
+ // events. 0x3 "Smart-Standby
+ // wakeup-capable mode: local
+ // initiator standby status depends
+ // on local conditions i.e. the
+ // module's functional requirement
+ // from the initiator. IP module may
+ // generate (master-related) wakeup
+ // events when in standby state.Mode
+ // is only relevant if the
+ // appropriate IP module ""mwakeup""
+ // output is implemented."
+
+#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4
+#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \
+ 0x0000000C // Configuration of the local
+ // target state management mode. By
+ // definition target can handle
+ // read/write transaction as long as
+ // it is out of IDLE state. 0x0
+ // Force-idle mode: local target's
+ // idle state follows (acknowledges)
+ // the system's idle requests
+ // unconditionally i.e. regardless
+ // of the IP module's internal
+ // requirements.Backup mode for
+ // debug only. 0x1 No-idle mode:
+ // local target never enters idle
+ // state.Backup mode for debug only.
+ // 0x2 Smart-idle mode: local
+ // target's idle state eventually
+ // follows (acknowledges) the
+ // system's idle requests depending
+ // on the IP module's internal
+ // requirements.IP module shall not
+ // generate (IRQ- or
+ // DMA-request-related) wakeup
+ // events. 0x3 "Smart-idle
+ // wakeup-capable mode: local
+ // target's idle state eventually
+ // follows (acknowledges) the
+ // system's idle requests depending
+ // on the IP module's internal
+ // requirements.IP module may
+ // generate (IRQ- or
+ // DMA-request-related) wakeup
+ // events when in idle state.Mode is
+ // only relevant if the appropriate
+ // IP module ""swakeup"" output(s)
+ // is (are) implemented."
+
+#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2
+#define MMCHS_HL_SYSCONFIG_FREEEMU \
+ 0x00000002 // Sensitivity to emulation (debug)
+ // suspend input signal.
+ // Functionality NOT implemented in
+ // MMCHS. 0 IP module is sensitive
+ // to emulation suspend 1 IP module
+ // is not sensitive to emulation
+ // suspend
+
+#define MMCHS_HL_SYSCONFIG_SOFTRESET \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register.
+//
+//******************************************************************************
+#define MMCHS_SYSCONFIG_STANDBYMODE_M \
+ 0x00003000 // Master interface power
+ // Management standby/wait control.
+ // The bit field is only useful when
+ // generic parameter MADMA_EN
+ // (Master ADMA enable) is set as
+ // active otherwise it is a read
+ // only register read a '0'. 0x0
+ // Force-standby. Mstandby is forced
+ // unconditionnaly. 0x1 No-standby.
+ // Mstandby is never asserted. 0x2
+ // Smart-standby mode: local
+ // initiator standby status depends
+ // on local conditions i.e. the
+ // module's functional requirement
+ // from the initiator.IP module
+ // shall not generate
+ // (initiator-related) wakeup
+ // events. 0x3 Smart-Standby
+ // wakeup-capable mode: "local
+ // initiator standby status depends
+ // on local conditions i.e. the
+ // module's functional requirement
+ // from the initiator. IP module may
+ // generate (master-related) wakeup
+ // events when in standby state.Mode
+ // is only relevant if the
+ // appropriate IP module ""mwakeup""
+ // output is implemented."
+
+#define MMCHS_SYSCONFIG_STANDBYMODE_S 12
+#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \
+ 0x00000300 // Clocks activity during wake up
+ // mode period. Bit8: OCP interface
+ // clock Bit9: Functional clock 0x0
+ // OCP and Functional clock may be
+ // switched off. 0x1 OCP clock is
+ // maintained. Functional clock may
+ // be switched-off. 0x2 Functional
+ // clock is maintained. OCP clock
+ // may be switched-off. 0x3 OCP and
+ // Functional clocks are maintained.
+
+#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8
+#define MMCHS_SYSCONFIG_SIDLEMODE_M \
+ 0x00000018 // Power management 0x0 If an idle
+ // request is detected the MMCHS
+ // acknowledges it unconditionally
+ // and goes in Inactive mode.
+ // Interrupt and DMA requests are
+ // unconditionally de-asserted. 0x1
+ // If an idle request is detected
+ // the request is ignored and the
+ // module keeps on behaving
+ // normally. 0x2 Smart-idle mode:
+ // local target's idle state
+ // eventually follows (acknowledges)
+ // the system's idle requests
+ // depending on the IP module's
+ // internal requirements.IP module
+ // shall not generate (IRQ- or
+ // DMA-request-related) wakeup
+ // events. 0x3 Smart-idle
+ // wakeup-capable mode: "local
+ // target's idle state eventually
+ // follows (acknowledges) the
+ // system's idle requests depending
+ // on the IP module's internal
+ // requirements.IP module may
+ // generate (IRQ- or
+ // DMA-request-related) wakeup
+ // events when in idle state.Mode is
+ // only relevant if the appropriate
+ // IP module ""swakeup"" output(s)
+ // is (are) implemented."
+
+#define MMCHS_SYSCONFIG_SIDLEMODE_S 3
+#define MMCHS_SYSCONFIG_ENAWAKEUP \
+ 0x00000004 // Wakeup feature control 0 Wakeup
+ // capability is disabled 1 Wakeup
+ // capability is enabled
+
+#define MMCHS_SYSCONFIG_SOFTRESET \
+ 0x00000002
+
+#define MMCHS_SYSCONFIG_AUTOIDLE \
+ 0x00000001 // Internal Clock gating strategy 0
+ // Clocks are free-running 1
+ // Automatic clock gating strategy
+ // is applied based on the OCP and
+ // MMC interface activity
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register.
+//
+//******************************************************************************
+#define MMCHS_SYSSTATUS_RESETDONE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_CSRE register.
+//
+//******************************************************************************
+#define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error
+#define MMCHS_CSRE_CSRE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_SYSTEST register.
+//
+//******************************************************************************
+#define MMCHS_SYSTEST_OBI 0x00010000
+#define MMCHS_SYSTEST_SDCD 0x00008000
+#define MMCHS_SYSTEST_SDWP 0x00004000
+#define MMCHS_SYSTEST_WAKD 0x00002000
+#define MMCHS_SYSTEST_SSB 0x00001000
+#define MMCHS_SYSTEST_D7D 0x00000800
+#define MMCHS_SYSTEST_D6D 0x00000400
+#define MMCHS_SYSTEST_D5D 0x00000200
+#define MMCHS_SYSTEST_D4D 0x00000100
+#define MMCHS_SYSTEST_D3D 0x00000080
+#define MMCHS_SYSTEST_D2D 0x00000040
+#define MMCHS_SYSTEST_D1D 0x00000020
+#define MMCHS_SYSTEST_D0D 0x00000010
+#define MMCHS_SYSTEST_DDIR 0x00000008
+#define MMCHS_SYSTEST_CDAT 0x00000004
+#define MMCHS_SYSTEST_CDIR 0x00000002
+#define MMCHS_SYSTEST_MCKD 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_CON register.
+//
+//******************************************************************************
+#define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request:
+ // The waveform of the DMA request
+ // can be configured either edge
+ // sensitive with early de-assertion
+ // on first access to MMCHS_DATA
+ // register or late de-assertion
+ // request remains active until last
+ // allowed data written into
+ // MMCHS_DATA. 0 Slave DMA edge
+ // sensitive Early DMA de-assertion
+ // 1 Slave DMA level sensitive Late
+ // DMA de-assertion
+#define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection:
+ // When this bit is set and the
+ // controller is configured to use
+ // the DMA Ocp master interface is
+ // used to get datas from system
+ // using ADMA2 procedure (direct
+ // access to the memory).This option
+ // is only available if generic
+ // parameter MADMA_EN is asserted to
+ // '1'. 0 The controller is slave on
+ // data transfers with system. 1 The
+ // controller is master on data
+ // exchange with system controller
+ // must be configured as using DMA.
+#define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this
+ // register is set the controller
+ // uses both clock edge to emit or
+ // receive data. Odd bytes are
+ // transmitted on falling edges and
+ // even bytes are transmitted on
+ // rise edges. It only applies on
+ // Data bytes and CRC Start end bits
+ // and CRC status are kept full
+ // cycle. This bit field is only
+ // meaningful and active for even
+ // clock divider ratio of
+ // MMCHS_SYSCTL[CLKD] it is
+ // insensitive to MMCHS_HCTL[HSPE]
+ // setting. 0 Standard mode : data
+ // are transmitted on a single edge
+ // depending on MMCHS_HCTRL[HSPE]. 1
+ // Data Bytes and CRC are
+ // transmitted on both edge.
+#define MMCHS_CON_BOOT_CF0 0x00040000
+#define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When
+ // this bit is set the controller
+ // should receive a boot status on
+ // DAT0 line after next command
+ // issued. If no status is received
+ // a data timeout will be generated.
+ // 0 No acknowledge to be received 1
+ // A boot status will be received on
+ // DAT0 line after issuing a
+ // command.
+#define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running:
+ // This register is used to maintain
+ // card clock out of transfer
+ // transaction to enable slave
+ // module for example to generate a
+ // synchronous interrupt on DAT[1].
+ // The Clock will be maintain only
+ // if MMCHS_SYSCTL[CEN] is set. 0
+ // External card clock is cut off
+ // outside active transaction
+ // period. 1 External card clock is
+ // maintain even out of active
+ // transaction period only if
+ // MMCHS_SYSCTL[CEN] is set.
+#define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines:
+ // This register is only useful when
+ // MMC PADs contain power saving
+ // mechanism to minimize its leakage
+ // power. It works as a GPIO that
+ // directly control the ACTIVE pin
+ // of PADs. Excepted for DAT[1] the
+ // signal is also combine outside
+ // the module with the dedicated
+ // power control MMCHS_CON[CTPL]
+ // bit. 0 ADPIDLE module pin is not
+ // forced it is automatically
+ // generated by the MMC fsms. 1
+ // ADPIDLE module pin is forced to
+ // active state.
+#define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC
+ // cards only: This bit enables the
+ // detection of Out-of-Band
+ // Interrupt on MMCOBI input pin.
+ // The usage of the Out-of-Band
+ // signal (OBI) is optional and
+ // depends on the system
+ // integration. 0 Out-of-Band
+ // interrupt detection disabled 1
+ // Out-of-Band interrupt detection
+ // enabled
+#define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity
+ // MMC cards only: This bit selects
+ // the active level of the
+ // out-of-band interrupt coming from
+ // MMC cards. The usage of the
+ // Out-of-Band signal (OBI) is
+ // optional and depends on the
+ // system integration. 0 active high
+ // level 1 active low level
+#define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards
+ // compliant with CE-ATA:By default
+ // this bit is set to 0. It is use
+ // to indicate that next commands
+ // are considered as specific CE-ATA
+ // commands that potentially use
+ // 'command completion' features. 0
+ // Standard MMC/SD/SDIO mode. 1
+ // CE-ATA mode next commands are
+ // considered as CE-ATA commands.
+#define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line
+ // MMC and SD cards: By default this
+ // bit is set to 0 and the host
+ // controller automatically disables
+ // all the input buffers outside of
+ // a transaction to minimize the
+ // leakage current. SDIO cards: When
+ // this bit is set to 1 the host
+ // controller automatically disables
+ // all the input buffers except the
+ // buffer of DAT[1] outside of a
+ // transaction in order to detect
+ // asynchronous card interrupt on
+ // DAT[1] line and minimize the
+ // leakage current of the buffers. 0
+ // Disable all the input buffers
+ // outside of a transaction. 1
+ // Disable all the input buffers
+ // except the buffer of DAT[1]
+ // outside of a transaction.
+#define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards
+ // This register is used to define a
+ // debounce period to filter the
+ // card detect input signal (SDCD).
+ // The usage of the card detect
+ // input signal (SDCD) is optional
+ // and depends on the system
+ // integration and the type of the
+ // connector housing that
+ // accommodates the card. 0x0 33 us
+ // debounce period 0x1 231 us
+ // debounce period 0x2 1 ms debounce
+ // period 0x3 84 ms debounce period
+#define MMCHS_CON_DVAL_S 9
+#define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD
+ // and SDIO cards only This bit
+ // selects the active level of the
+ // write protect input signal
+ // (SDWP). The usage of the write
+ // protect input signal (SDWP) is
+ // optional and depends on the
+ // system integration and the type
+ // of the connector housing that
+ // accommodates the card. 0 active
+ // high level 1 active low level
+#define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards
+ // This bit selects the active level
+ // of the card detect input signal
+ // (SDCD). The usage of the card
+ // detect input signal (SDCD) is
+ // optional and depends on the
+ // system integration and the type
+ // of the connector housing that
+ // accommodates the card. 0 active
+ // high level 1 active low level
+#define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for
+ // MMC cards. This bit must be set
+ // to 1 when the next write access
+ // to the command register
+ // (MMCHS_CMD) is for writing a MMC
+ // interrupt command (CMD40)
+ // requiring the command timeout
+ // detection to be disabled for the
+ // command response. 0 Command
+ // timeout enabled 1 Command timeout
+ // disabled
+#define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For
+ // SD/SDIO cards this bit must be
+ // set to 0. For MMC card this bit
+ // must be set following a valid
+ // SWITCH command (CMD6) with the
+ // correct value and extend CSD
+ // index written in the argument.
+ // Prior to this command the MMC
+ // card configuration register (CSD
+ // and EXT_CSD) must be verified for
+ // compliancy with MMC standard
+ // specification 4.x (see section
+ // 3.6). 0 1-bit or 4-bit Data width
+ // (DAT[0] used MMC SD cards) 1
+ // 8-bit Data width (DAT[7:0] used
+ // MMC cards)
+#define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits
+ // select between Functional mode
+ // and SYSTEST mode. 0 Functional
+ // mode. Transfers to the
+ // MMC/SD/SDIO cards follow the card
+ // protocol. MMC clock is enabled.
+ // MMC/SD transfers are operated
+ // under the control of the CMD
+ // register. 1 SYSTEST mode The
+ // signal pins are configured as
+ // general-purpose input/output and
+ // the 1024-byte buffer is
+ // configured as a stack memory
+ // accessible only by the local host
+ // or system DMA. The pins retain
+ // their default type (input output
+ // or in-out). SYSTEST mode is
+ // operated under the control of the
+ // SYSTEST register.
+#define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC
+ // cards. This bit must be set to 1
+ // only for the stream data
+ // transfers (read or write) of the
+ // adtc commands. Stream read is a
+ // class 1 command (CMD11:
+ // READ_DAT_UNTIL_STOP). Stream
+ // write is a class 3 command
+ // (CMD20: WRITE_DAT_UNTIL_STOP). 0
+ // Block oriented data transfer 1
+ // Stream oriented data transfer
+#define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for
+ // MMC cards. This register is used
+ // to force the host to generate a
+ // 48-bit response for bc command
+ // type. "It can be used to
+ // terminate the interrupt mode by
+ // generating a CMD40 response by
+ // the core (see section 4.3
+ // ""Interrupt Mode"" in the MMC [1]
+ // specification). In order to have
+ // the host response to be generated
+ // in open drain mode the register
+ // MMCHS_CON[OD] must be set to 1."
+ // When MMCHS_CON[CEATA] is set to 1
+ // and MMCHS_ARG set to 0x00000000
+ // when writing 0x00000000 into
+ // MMCHS_CMD register the host
+ // controller performs a 'command
+ // completion signal disable' token
+ // i.e. CMD line held to '0' during
+ // 47 cycles followed by a 1. 0 The
+ // host does not generate a 48-bit
+ // response instead of a command. 1
+ // The host generates a 48-bit
+ // response instead of a command or
+ // a command completion signal
+ // disable token.
+#define MMCHS_CON_INIT 0x00000002 // Send initialization stream All
+ // cards. When this bit is set to 1
+ // and the card is idle an
+ // initialization sequence is sent
+ // to the card. "An initialization
+ // sequence consists of setting the
+ // CMD line to 1 during 80 clock
+ // cycles. The initialisation
+ // sequence is mandatory - but it is
+ // not required to do it through
+ // this bit - this bit makes it
+ // easier. Clock divider
+ // (MMCHS_SYSCTL[CLKD]) should be
+ // set to ensure that 80 clock
+ // periods are greater than 1ms.
+ // (see section 9.3 ""Power-Up"" in
+ // the MMC card specification [1] or
+ // section 6.4 in the SD card
+ // specification [2])." Note: in
+ // this mode there is no command
+ // sent to the card and no response
+ // is expected 0 The host does not
+ // send an initialization sequence.
+ // 1 The host sends an
+ // initialization sequence.
+#define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for
+ // MMC cards. This bit must be set
+ // to 1 for MMC card commands 1 2 3
+ // and 40 and if the MMC card bus is
+ // operating in open-drain mode
+ // during the response phase to the
+ // command sent. Typically during
+ // card identification mode when the
+ // card is either in idle ready or
+ // ident state. It is also necessary
+ // to set this bit to 1 for a
+ // broadcast host response (see
+ // Broadcast host response register
+ // MMCHS_CON[HR]) 0 No Open Drain 1
+ // Open Drain or Broadcast host
+ // response
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_PWCNT register.
+//
+//******************************************************************************
+#define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This
+ // register is used to introduce a
+ // delay between the PAD ACTIVE pin
+ // assertion and the command issued.
+ // 0x0000 No additional delay added
+ // 0x0001 TCF delay (card clock
+ // period) 0x0002 TCF x 2 delay
+ // (card clock period) 0xFFFE TCF x
+ // 65534 delay (card clock period)
+ // 0xFFFF TCF x 65535 delay (card
+ // clock period)
+#define MMCHS_PWCNT_PWRCNT_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_BLK register.
+//
+//******************************************************************************
+#define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current
+ // transfer This register is enabled
+ // when Block count Enable
+ // (MMCHS_CMD[BCE]) is set to 1 and
+ // is valid only for multiple block
+ // transfers. Setting the block
+ // count to 0 results no data blocks
+ // being transferred. Note: The host
+ // controller decrements the block
+ // count after each block transfer
+ // and stops when the count reaches
+ // zero. This register can be
+ // accessed only if no transaction
+ // is executing (i.e after a
+ // transaction has stopped). Read
+ // operations during transfers may
+ // return an invalid value and write
+ // operation will be ignored. In
+ // suspend context the number of
+ // blocks yet to be transferred can
+ // be determined by reading this
+ // register. When restoring transfer
+ // context prior to issuing a Resume
+ // command The local host shall
+ // restore the previously saved
+ // block count. 0x0000 Stop count
+ // 0x0001 1 block 0x0002 2 blocks
+ // 0xFFFF 65535 blocks
+#define MMCHS_BLK_NBLK_S 16
+#define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This
+ // register specifies the block size
+ // for block data transfers. Read
+ // operations during transfers may
+ // return an invalid value and write
+ // operations are ignored. When a
+ // CMD12 command is issued to stop
+ // the transfer a read of the BLEN
+ // field after transfer completion
+ // (MMCHS_STAT[TC] set to 1) will
+ // not return the true byte number
+ // of data length while the stop
+ // occurs but the value written in
+ // this register before transfer is
+ // launched. 0x000 No data transfer
+ // 0x001 1 byte block length 0x002 2
+ // bytes block length 0x003 3 bytes
+ // block length 0x1FF 511 bytes
+ // block length 0x200 512 bytes
+ // block length 0x7FF 2047 bytes
+ // block length 0x800 2048 bytes
+ // block length
+#define MMCHS_BLK_BLEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_ARG register.
+//
+//******************************************************************************
+#define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0]
+#define MMCHS_ARG_ARG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_CMD register.
+//
+//******************************************************************************
+#define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded
+ // value from 0 to 63 specifying the
+ // command number send to card 0x00
+ // CMD0 or ACMD0 0x01 CMD1 or ACMD1
+ // 0x02 CMD2 or ACMD2 0x03 CMD3 or
+ // ACMD3 0x04 CMD4 or ACMD4 0x05
+ // CMD5 or ACMD5 0x06 CMD6 or ACMD6
+ // 0x07 CMD7 or ACMD7 0x08 CMD8 or
+ // ACMD8 0x09 CMD9 or ACMD9 0x0A
+ // CMD10 or ACMD10 0x0B CMD11 or
+ // ACMD11 0x0C CMD12 or ACMD12 0x0D
+ // CMD13 or ACMD13 0x0E CMD14 or
+ // ACMD14 0x0F CMD15 or ACMD15 0x10
+ // CMD16 or ACMD16 0x11 CMD17 or
+ // ACMD17 0x12 CMD18 or ACMD18 0x13
+ // CMD19 or ACMD19 0x14 CMD20 or
+ // ACMD20 0x15 CMD21 or ACMD21 0x16
+ // CMD22 or ACMD22 0x17 CMD23 or
+ // ACMD23 0x18 CMD24 or ACMD24 0x19
+ // CMD25 or ACMD25 0x1A CMD26 or
+ // ACMD26 0x1B CMD27 or ACMD27 0x1C
+ // CMD28 or ACMD28 0x1D CMD29 or
+ // ACMD29 0x1E CMD30 or ACMD30 0x1F
+ // CMD31 or ACMD31 0x20 CMD32 or
+ // ACMD32 0x21 CMD33 or ACMD33 0x22
+ // CMD34 or ACMD34 0x23 CMD35 or
+ // ACMD35 0x24 CMD36 or ACMD36 0x25
+ // CMD37 or ACMD37 0x26 CMD38 or
+ // ACMD38 0x27 CMD39 or ACMD39 0x28
+ // CMD40 or ACMD40 0x29 CMD41 or
+ // ACMD41 0x2A CMD42 or ACMD42 0x2B
+ // CMD43 or ACMD43 0x2C CMD44 or
+ // ACMD44 0x2D CMD45 or ACMD45 0x2E
+ // CMD46 or ACMD46 0x2F CMD47 or
+ // ACMD47 0x30 CMD48 or ACMD48 0x31
+ // CMD49 or ACMD49 0x32 CMD50 or
+ // ACMD50 0x33 CMD51 or ACMD51 0x34
+ // CMD52 or ACMD52 0x35 CMD53 or
+ // ACMD53 0x36 CMD54 or ACMD54 0x37
+ // CMD55 or ACMD55 0x38 CMD56 or
+ // ACMD56 0x39 CMD57 or ACMD57 0x3A
+ // CMD58 or ACMD58 0x3B CMD59 or
+ // ACMD59 0x3C CMD60 or ACMD60 0x3D
+ // CMD61 or ACMD61 0x3E CMD62 or
+ // ACMD62 0x3F CMD63 or ACMD63
+#define MMCHS_CMD_INDX_S 24
+#define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register
+ // specifies three types of special
+ // command: Suspend Resume and
+ // Abort. These bits shall be set to
+ // 00b for all other commands. 0x0
+ // Others Commands 0x1 "CMD52 for
+ // writing ""Bus Suspend"" in CCCR"
+ // 0x2 "CMD52 for writing ""Function
+ // Select"" in CCCR" 0x3 "Abort
+ // command CMD12 CMD52 for writing
+ // "" I/O Abort"" in CCCR"
+#define MMCHS_CMD_CMD_TYPE_S 22
+#define MMCHS_CMD_DP 0x00200000 // Data present select This
+ // register indicates that data is
+ // present and DAT line shall be
+ // used. It must be set to 0 in the
+ // following conditions: - command
+ // using only CMD line - command
+ // with no data transfer but using
+ // busy signal on DAT[0] - Resume
+ // command 0 Command with no data
+ // transfer 1 Command with data
+ // transfer
+#define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This
+ // bit must be set to 1 to enable
+ // index check on command response
+ // to compare the index field in the
+ // response against the index of the
+ // command. If the index is not the
+ // same in the response as in the
+ // command it is reported as a
+ // command index error
+ // (MMCHS_STAT[CIE] set to1) Note:
+ // The register CICE cannot be
+ // configured for an Auto CMD12 then
+ // index check is automatically
+ // checked when this command is
+ // issued. 0 Index check disable 1
+ // Index check enable
+#define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This
+ // bit must be set to 1 to enable
+ // CRC7 check on command response to
+ // protect the response against
+ // transmission errors on the bus.
+ // If an error is detected it is
+ // reported as a command CRC error
+ // (MMCHS_STAT[CCRC] set to 1).
+ // Note: The register CCCE cannot be
+ // configured for an Auto CMD12 and
+ // then CRC check is automatically
+ // checked when this command is
+ // issued. 0 CRC7 check disable 1
+ // CRC7 check enable
+#define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines
+ // the response type of the command
+ // 0x0 No response 0x1 Response
+ // Length 136 bits 0x2 Response
+ // Length 48 bits 0x3 Response
+ // Length 48 bits with busy after
+ // response
+#define MMCHS_CMD_RSP_TYPE_S 16
+#define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This
+ // bit must be set to 1 for data
+ // transfer in case of multi block
+ // command. For any others command
+ // this bit shall be set to 0. 0
+ // Single block. If this bit is 0 it
+ // is not necessary to set the
+ // register MMCHS_BLK[NBLK]. 1 Multi
+ // block. When Block Count is
+ // disabled (MMCHS_CMD[BCE] is set
+ // to 0) in Multiple block transfers
+ // (MMCHS_CMD[MSBS] is set to 1) the
+ // module can perform infinite
+ // transfer.
+#define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select
+ // This bit defines either data
+ // transfer will be a read or a
+ // write. 0 Data Write (host to
+ // card) 1 Data Read (card to host)
+#define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only.
+ // When this bit is set to 1 the
+ // host controller issues a CMD12
+ // automatically after the transfer
+ // completion of the last block. The
+ // Host Driver shall not set this
+ // bit to issue commands that do not
+ // require CMD12 to stop data
+ // transfer. In particular secure
+ // commands do not require CMD12. 0
+ // Auto CMD12 disable 1 Auto CMD12
+ // enable or CCS detection enabled.
+#define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple
+ // block transfers only. This bit is
+ // used to enable the block count
+ // register (MMCHS_BLK[NBLK]). When
+ // Block Count is disabled
+ // (MMCHS_CMD[BCE] is set to 0) in
+ // Multiple block transfers
+ // (MMCHS_CMD[MSBS] is set to 1) the
+ // module can perform infinite
+ // transfer. 0 Block count disabled
+ // for infinite transfer. 1 Block
+ // count enabled for multiple block
+ // transfer with known number of
+ // blocks
+#define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to
+ // enable DMA mode for host data
+ // access. 0 DMA mode disable 1 DMA
+ // mode enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_RSP10 register.
+//
+//******************************************************************************
+#define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16]
+#define MMCHS_RSP10_RSP1_S 16
+#define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0]
+#define MMCHS_RSP10_RSP0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_RSP32 register.
+//
+//******************************************************************************
+#define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48]
+#define MMCHS_RSP32_RSP3_S 16
+#define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32]
+#define MMCHS_RSP32_RSP2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_RSP54 register.
+//
+//******************************************************************************
+#define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80]
+#define MMCHS_RSP54_RSP5_S 16
+#define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64]
+#define MMCHS_RSP54_RSP4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_RSP76 register.
+//
+//******************************************************************************
+#define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112]
+#define MMCHS_RSP76_RSP7_S 16
+#define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96]
+#define MMCHS_RSP76_RSP6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_DATA register.
+//
+//******************************************************************************
+#define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In
+ // functional mode (MMCHS_CON[MODE]
+ // set to the default value 0) A
+ // read access to this register is
+ // allowed only when the buffer read
+ // enable status is set to 1
+ // (MMCHS_PSTATE[BRE]) otherwise a
+ // bad access (MMCHS_STAT[BADA]) is
+ // signaled. A write access to this
+ // register is allowed only when the
+ // buffer write enable status is set
+ // to 1(MMCHS_STATE[BWE]) otherwise
+ // a bad access (MMCHS_STAT[BADA])
+ // is signaled and the data is not
+ // written.
+#define MMCHS_DATA_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_PSTATE register.
+//
+//******************************************************************************
+#define MMCHS_PSTATE_CLEV 0x01000000
+#define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level
+ // DAT[3] => bit 23 DAT[2] => bit 22
+ // DAT[1] => bit 21 DAT[0] => bit 20
+ // This status is used to check DAT
+ // line level to recover from errors
+ // and for debugging. This is
+ // especially useful in detecting
+ // the busy signal level from
+ // DAT[0]. The value of these
+ // registers after reset depends on
+ // the DAT lines level at that time.
+#define MMCHS_PSTATE_DLEV_S 20
+#define MMCHS_PSTATE_WP 0x00080000
+#define MMCHS_PSTATE_CDPL 0x00040000
+#define MMCHS_PSTATE_CSS 0x00020000
+#define MMCHS_PSTATE_CINS 0x00010000
+#define MMCHS_PSTATE_BRE 0x00000800
+#define MMCHS_PSTATE_BWE 0x00000400
+#define MMCHS_PSTATE_RTA 0x00000200
+#define MMCHS_PSTATE_WTA 0x00000100
+#define MMCHS_PSTATE_DLA 0x00000004
+#define MMCHS_PSTATE_DATI 0x00000002
+#define MMCHS_PSTATE_CMDI 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_HCTL register.
+//
+//******************************************************************************
+#define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for
+ // 'Out-of-Band' Interrupt. This bit
+ // enables wakeup events for
+ // 'Out-of-Band' assertion. Wakeup
+ // is generated if the wakeup
+ // feature is enabled
+ // (MMCHS_SYSCONFIG[ENAWAKEUP]). The
+ // write to this register is ignored
+ // when MMCHS_CON[OBIE] is not set.
+ // 0 Disable wakeup on 'Out-of-Band'
+ // Interrupt 1 Enable wakeup on
+ // 'Out-of-Band' Interrupt
+#define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card
+ // removal This bit enables wakeup
+ // events for card removal
+ // assertion. Wakeup is generated if
+ // the wakeup feature is enabled
+ // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
+ // Disable wakeup on card removal 1
+ // Enable wakeup on card removal
+#define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card
+ // insertion This bit enables wakeup
+ // events for card insertion
+ // assertion. Wakeup is generated if
+ // the wakeup feature is enabled
+ // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
+ // Disable wakeup on card insertion
+ // 1 Enable wakeup on card insertion
+#define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card
+ // interrupt This bit enables wakeup
+ // events for card interrupt
+ // assertion. Wakeup is generated if
+ // the wakeup feature is enabled
+ // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0
+ // Disable wakeup on card interrupt
+ // 1 Enable wakeup on card interrupt
+#define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit
+ // is valid only in 4-bit mode of
+ // SDIO card to enable interrupt
+ // detection in the interrupt cycle
+ // at block gap for a multiple block
+ // transfer. For MMC cards and for
+ // SD card this bit should be set to
+ // 0. 0 Disable interrupt detection
+ // at the block gap in 4-bit mode 1
+ // Enable interrupt detection at the
+ // block gap in 4-bit mode
+#define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait
+ // function is optional only for
+ // SDIO cards. If the card supports
+ // read wait this bit must be
+ // enabled then requesting a stop at
+ // block gap (MMCHS_HCTL[SBGR])
+ // generates a read wait period
+ // after the current end of block.
+ // Be careful if read wait is not
+ // supported it may cause a conflict
+ // on DAT line. 0 Disable Read Wait
+ // Control. Suspend/Resume cannot be
+ // supported. 1 Enable Read Wait
+ // Control
+#define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is
+ // used to restart a transaction
+ // that was stopped by requesting a
+ // stop at block gap
+ // (MMCHS_HCTL[SBGR]). Set this bit
+ // to 1 restarts the transfer. The
+ // bit is automatically set to 0 by
+ // the host controller when transfer
+ // has restarted i.e DAT line is
+ // active (MMCHS_PSTATE[DLA]) or
+ // transferring data
+ // (MMCHS_PSTATE[WTA]). The Stop at
+ // block gap request must be
+ // disabled (MMCHS_HCTL[SBGR]=0)
+ // before setting this bit. 0 No
+ // affect 1 transfer restart
+#define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This
+ // bit is used to stop executing a
+ // transaction at the next block
+ // gap. The transfer can restart
+ // with a continue request
+ // (MMHS_HCTL[CR]) or during a
+ // suspend/resume sequence. In case
+ // of read transfer the card must
+ // support read wait control. In
+ // case of write transfer the host
+ // driver shall set this bit after
+ // all block data written. Until the
+ // transfer completion
+ // (MMCHS_STAT[TC] set to 1) the
+ // host driver shall leave this bit
+ // set to 1. If this bit is set the
+ // local host shall not write to the
+ // data register (MMCHS_DATA). 0
+ // Transfer mode 1 Stop at block gap
+#define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards.
+ // The host driver should set to
+ // these bits to select the voltage
+ // level for the card according to
+ // the voltage supported by the
+ // system (MMCHS_CAPA[VS18VS30VS33])
+ // before starting a transfer. 0x5
+ // 1.8V (Typical) 0x6 3.0V (Typical)
+ // 0x7 3.3V (Typical)
+#define MMCHS_HCTL_SDVS_S 9
+#define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this
+ // bit the host driver shall select
+ // the SD bus voltage
+ // (MMCHS_HCTL[SDVS]). If the host
+ // controller detects the No card
+ // state this bit is automatically
+ // set to 0. If the module is power
+ // off a write in the command
+ // register (MMCHS_CMD) will not
+ // start the transfer. A write to
+ // this bit has no effect if the
+ // selected SD bus voltage
+ // MMCHS_HCTL[SDVS] is not supported
+ // according to capability register
+ // (MMCHS_CAPA[VS*]). 0 Power off 1
+ // Power on
+#define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection
+ // This bit selects source for the
+ // card detection.When the source
+ // for the card detection is
+ // switched the interrupt should be
+ // disabled during the switching
+ // period by clearing the Interrupt
+ // Status/Signal Enable register in
+ // order to mask unexpected
+ // interrupt being caused by the
+ // glitch. The Interrupt
+ // Status/Signal Enable should be
+ // disabled during over the period
+ // of debouncing. 0 SDCD# is
+ // selected (for normal use) 1 The
+ // Card Detect Test Level is
+ // selected (for test purpose)
+#define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit
+ // is enabled while the Card Detect
+ // Signal Selection is set to 1 and
+ // it indicates card inserted or
+ // not. 0 No Card 1 Card Inserted
+#define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of
+ // supported DMA modes can be
+ // selected. The host driver shall
+ // check support of DMA modes by
+ // referring the Capabilities
+ // register. Use of selected DMA is
+ // determined by DMA Enable of the
+ // Transfer Mode register. This
+ // register is only meaningful when
+ // MADMA_EN is set to 1. When
+ // MADMA_EN is set to 0 the bit
+ // field is read only and returned
+ // value is 0. 0x0 Reserved 0x1
+ // Reserved 0x2 32-bit Address ADMA2
+ // is selected 0x3 Reserved
+#define MMCHS_HCTL_DMAS_S 3
+#define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before
+ // setting this bit the Host Driver
+ // shall check the High Speed
+ // Support in the Capabilities
+ // register. If this bit is set to 0
+ // (default) the Host Controller
+ // outputs CMD line and DAT lines at
+ // the falling edge of the SD Clock.
+ // If this bit is set to 1 the Host
+ // Controller outputs CMD line and
+ // DAT lines at the rising edge of
+ // the SD Clock.This bit shall not
+ // be set when dual data rate mode
+ // is activated in MMCHS_CON[DDR]. 0
+ // Normal speed mode 1 High speed
+ // mode
+#define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card
+ // this bit must be set following a
+ // valid SWITCH command (CMD6) with
+ // the correct value and extend CSD
+ // index written in the argument.
+ // Prior to this command the MMC
+ // card configuration register (CSD
+ // and EXT_CSD) must be verified for
+ // compliance with MMC standard
+ // specification 4.x (see section
+ // 3.6). This register has no effect
+ // when the MMC 8-bit mode is
+ // selected (register MMCHS_CON[DW8]
+ // set to1 ) For SD/SDIO cards this
+ // bit must be set following a valid
+ // SET_BUS_WIDTH command (ACMD6)
+ // with the value written in bit 1
+ // of the argument. Prior to this
+ // command the SD card configuration
+ // register (SCR) must be verified
+ // for the supported bus width by
+ // the SD card. 0 1-bit Data width
+ // (DAT[0] used) 1 4-bit Data width
+ // (DAT[3:0] used)
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_SYSCTL register.
+//
+//******************************************************************************
+#define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This
+ // bit is set to 1 for reset and
+ // released to 0 when completed. DAT
+ // finite state machine in both
+ // clock domain are also reset. Here
+ // below are the registers cleared
+ // by MMCHS_SYSCTL[SRD]: #VALUE! -
+ // MMCHS_PSTATE: BRE BWE RTA WTA DLA
+ // and DATI - MMCHS_HCTL: SBGR and
+ // CR - MMCHS_STAT: BRR BWR BGE and
+ // TC OCP and MMC buffer data
+ // management is reinitialized. 0
+ // Reset completed 1 Software reset
+ // for DAT line
+#define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This
+ // bit is set to 1 for reset and
+ // released to 0 when completed. CMD
+ // finite state machine in both
+ // clock domain are also reset. Here
+ // below the registers cleared by
+ // MMCHS_SYSCTL[SRC]: -
+ // MMCHS_PSTATE: CMDI - MMCHS_STAT:
+ // CC OCP and MMC command status
+ // management is reinitialized. 0
+ // Reset completed 1 Software reset
+ // for CMD line
+#define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit
+ // is set to 1 for reset and
+ // released to 0 when completed.
+ // This reset affects the entire
+ // host controller except for the
+ // card detection circuit and
+ // capabilities registers. 0 Reset
+ // completed 1 Software reset for
+ // all the design
+#define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and
+ // busy timeout. This value
+ // determines the interval by which
+ // DAT lines timeouts are detected.
+ // The host driver needs to set this
+ // bitfield based on - the maximum
+ // read access time (NAC) (Refer to
+ // the SD Specification Part1
+ // Physical Layer) - the data read
+ // access time values (TAAC and
+ // NSAC) in the card specific data
+ // register (CSD) of the card - the
+ // timeout clock base frequency
+ // (MMCHS_CAPA[TCF]). If the card
+ // does not respond within the
+ // specified number of cycles a data
+ // timeout error occurs
+ // (MMCHS_STA[DTO]). The
+ // MMCHS_SYSCTL[DTO] register is
+ // also used to check busy duration
+ // to generate busy timeout for
+ // commands with busy response or
+ // for busy programming during a
+ // write command. Timeout on CRC
+ // status is generated if no CRC
+ // token is present after a block
+ // write. 0x0 TCF x 2^13 0x1 TCF x
+ // 2^14 0xE TCF x 2^27 0xF Reserved
+#define MMCHS_SYSCTL_DTO_S 16
+#define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These
+ // bits define the ratio between a
+ // reference clock frequency (system
+ // dependant) and the output clock
+ // frequency on the CLK pin of
+ // either the memory card (MMC SD or
+ // SDIO). 0x000 Clock Ref bypass
+ // 0x001 Clock Ref bypass 0x002
+ // Clock Ref / 2 0x003 Clock Ref / 3
+ // 0x3FF Clock Ref / 1023
+#define MMCHS_SYSCTL_CLKD_S 6
+#define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls
+ // if the clock is provided to the
+ // card or not. 0 The clock is not
+ // provided to the card . Clock
+ // frequency can be changed . 1 The
+ // clock is provided to the card and
+ // can be automatically gated when
+ // MMCHS_SYSCONFIG[AUTOIDLE] is set
+ // to 1 (default value) . The host
+ // driver shall wait to set this bit
+ // to 1 until the Internal clock is
+ // stable (MMCHS_SYSCTL[ICS]).
+#define MMCHS_SYSCTL_ICS 0x00000002
+#define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This
+ // register controls the internal
+ // clock activity. In very low power
+ // state the internal clock is
+ // stopped. Note: The activity of
+ // the debounce clock (used for
+ // wakeup events) and the OCP clock
+ // (used for reads and writes to the
+ // module register map) are not
+ // affected by this register. 0 The
+ // internal clock is stopped (very
+ // low power state). 1 The internal
+ // clock oscillates and can be
+ // automatically gated when
+ // MMCHS_SYSCONFIG[AUTOIDLE] is set
+ // to 1 (default value) .
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_STAT register.
+//
+//******************************************************************************
+#define MMCHS_STAT_BADA 0x20000000
+#define MMCHS_STAT_CERR 0x10000000
+#define MMCHS_STAT_ADMAE 0x02000000
+#define MMCHS_STAT_ACE 0x01000000
+#define MMCHS_STAT_DEB 0x00400000
+#define MMCHS_STAT_DCRC 0x00200000
+#define MMCHS_STAT_DTO 0x00100000
+#define MMCHS_STAT_CIE 0x00080000
+#define MMCHS_STAT_CEB 0x00040000
+#define MMCHS_STAT_CCRC 0x00020000
+#define MMCHS_STAT_CTO 0x00010000
+#define MMCHS_STAT_ERRI 0x00008000
+#define MMCHS_STAT_BSR 0x00000400
+#define MMCHS_STAT_OBI 0x00000200
+#define MMCHS_STAT_CIRQ 0x00000100
+#define MMCHS_STAT_CREM 0x00000080
+#define MMCHS_STAT_CINS 0x00000040
+#define MMCHS_STAT_BRR 0x00000020
+#define MMCHS_STAT_BWR 0x00000010
+#define MMCHS_STAT_DMA 0x00000008
+#define MMCHS_STAT_BGE 0x00000004
+#define MMCHS_STAT_TC 0x00000002
+#define MMCHS_STAT_CC 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_IE register.
+//
+//******************************************************************************
+#define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space
+ // Interrupt Enable 0 Masked 1
+ // Enabled
+#define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0
+ // Masked 1 Enabled
+#define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0
+ // Masked 1 Enabled
+#define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable
+ // 0 Masked 1 Enabled
+#define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt
+ // Enable 0 The data timeout
+ // detection is deactivated. The
+ // host controller provides the
+ // clock to the card until the card
+ // sends the data or the transfer is
+ // aborted. 1 The data timeout
+ // detection is enabled.
+#define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall
+ // control error interrupts using
+ // the Error Interrupt Signal Enable
+ // register. Writes to this bit are
+ // ignored
+#define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A
+ // write to this register when
+ // MMCHS_CON[BOOT_ACK] is set to 0x0
+ // is ignored. 0 Masked 1 Enabled
+#define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A
+ // write to this register when
+ // MMCHS_CON[OBIE] is set to '0' is
+ // ignored. 0 Masked 1 Enabled
+#define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of
+ // this bit also clears the
+ // corresponding status bit. During
+ // 1-bit mode if the interrupt
+ // routine doesn't remove the source
+ // of a card interrupt in the SDIO
+ // card the status bit is reasserted
+ // when this bit is set to 1. 0
+ // Masked 1 Enabled
+#define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0
+ // Masked 1 Enabled
+#define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable
+ // 0 Masked 1 Enabled
+#define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1
+ // Enabled
+#define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable
+ // 0 Masked 1 Enabled
+#define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt
+ // Enable 0 Masked 1 Enabled
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_ISE register.
+//
+//******************************************************************************
+#define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal
+ // status Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal
+ // status Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable
+ // 0 Masked 1 Enabled
+#define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal
+ // status Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal
+ // status Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal
+ // status Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall
+ // control error interrupts using
+ // the Error Interrupt Signal Enable
+ // register. Writes to this bit are
+ // ignored
+#define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status
+ // EnableA write to this register
+ // when MMCHS_CON[BOOT_ACK] is set
+ // to 0x0 is ignored. 0 Masked 1
+ // Enabled
+#define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal
+ // status Enable A write to this
+ // register when MMCHS_CON[OBIE] is
+ // set to '0' is ignored. 0 Masked 1
+ // Enabled
+#define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status
+ // enable 0 Masked 1 Enabled
+#define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status
+ // Enable 0 Masked 1 Enabled
+#define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status
+ // Enable 0 Masked 1 Enabled
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_AC12 register.
+//
+//******************************************************************************
+#define MMCHS_AC12_CNI 0x00000080
+#define MMCHS_AC12_ACIE 0x00000010
+#define MMCHS_AC12_ACEB 0x00000008
+#define MMCHS_AC12_ACCE 0x00000004
+#define MMCHS_AC12_ACTO 0x00000002
+#define MMCHS_AC12_ACNE 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_CAPA register.
+//
+//******************************************************************************
+#define MMCHS_CAPA_BIT64 0x10000000
+#define MMCHS_CAPA_VS18 0x04000000
+#define MMCHS_CAPA_VS30 0x02000000
+#define MMCHS_CAPA_VS33 0x01000000
+#define MMCHS_CAPA_SRS 0x00800000
+#define MMCHS_CAPA_DS 0x00400000
+#define MMCHS_CAPA_HSS 0x00200000
+#define MMCHS_CAPA_AD2S 0x00080000
+#define MMCHS_CAPA_MBL_M 0x00030000
+#define MMCHS_CAPA_MBL_S 16
+#define MMCHS_CAPA_BCF_M 0x00003F00
+#define MMCHS_CAPA_BCF_S 8
+#define MMCHS_CAPA_TCU 0x00000080
+#define MMCHS_CAPA_TCF_M 0x0000003F
+#define MMCHS_CAPA_TCF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register.
+//
+//******************************************************************************
+#define MMCHS_CUR_CAPA_CUR_1V8_M \
+ 0x00FF0000
+
+#define MMCHS_CUR_CAPA_CUR_1V8_S 16
+#define MMCHS_CUR_CAPA_CUR_3V0_M \
+ 0x0000FF00
+
+#define MMCHS_CUR_CAPA_CUR_3V0_S 8
+#define MMCHS_CUR_CAPA_CUR_3V3_M \
+ 0x000000FF
+
+#define MMCHS_CUR_CAPA_CUR_3V3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_FE register.
+//
+//******************************************************************************
+#define MMCHS_FE_FE_BADA 0x20000000
+#define MMCHS_FE_FE_CERR 0x10000000
+#define MMCHS_FE_FE_ADMAE 0x02000000
+#define MMCHS_FE_FE_ACE 0x01000000
+#define MMCHS_FE_FE_DEB 0x00400000
+#define MMCHS_FE_FE_DCRC 0x00200000
+#define MMCHS_FE_FE_DTO 0x00100000
+#define MMCHS_FE_FE_CIE 0x00080000
+#define MMCHS_FE_FE_CEB 0x00040000
+#define MMCHS_FE_FE_CCRC 0x00020000
+#define MMCHS_FE_FE_CTO 0x00010000
+#define MMCHS_FE_FE_CNI 0x00000080
+#define MMCHS_FE_FE_ACIE 0x00000010
+#define MMCHS_FE_FE_ACEB 0x00000008
+#define MMCHS_FE_FE_ACCE 0x00000004
+#define MMCHS_FE_FE_ACTO 0x00000002
+#define MMCHS_FE_FE_ACNE 0x00000001
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_ADMAES register.
+//
+//******************************************************************************
+#define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1)
+ // While Block Count Enable being
+ // set the total data length
+ // specified by the Descriptor table
+ // is different from that specified
+ // by the Block Count and Block
+ // Length. (2) Total data length can
+ // not be divided by the block
+ // length. 0 No Error 1 Error
+#define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field
+ // indicates the state of ADMA when
+ // error is occurred during ADMA
+ // data transfer. "This field never
+ // indicates ""10"" because ADMA
+ // never stops in this state." 0x0
+ // ST_STOP (Stop DMA)Contents of
+ // SYS_SDR register 0x1 ST_STOP
+ // (Stop DMA)Points the error
+ // descriptor 0x2 Never set this
+ // state(Not used) 0x3 ST_TFR
+ // (Transfer Data)Points the next of
+ // the error descriptor
+#define MMCHS_ADMAES_AES_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_ADMASAL register.
+//
+//******************************************************************************
+#define MMCHS_ADMASAL_ADMA_A32B_M \
+ 0xFFFFFFFF // ADMA System address 32 bits.This
+ // register holds byte address of
+ // executing command of the
+ // Descriptor table. 32-bit Address
+ // Descriptor uses lower 32-bit of
+ // this register. At the start of
+ // ADMA the Host Driver shall set
+ // start address of the Descriptor
+ // table. The ADMA increments this
+ // register address which points to
+ // next line when every fetching a
+ // Descriptor line. When the ADMA
+ // Error Interrupt is generated this
+ // register shall hold valid
+ // Descriptor address depending on
+ // the ADMA state. The Host Driver
+ // shall program Descriptor Table on
+ // 32-bit boundary and set 32-bit
+ // boundary address to this
+ // register. ADMA2 ignores lower
+ // 2-bit of this register and
+ // assumes it to be 00b.
+
+#define MMCHS_ADMASAL_ADMA_A32B_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the MMCHS_O_REV register.
+//
+//******************************************************************************
+#define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP
+ // revision [7:4] Major revision
+ // [3:0] Minor revision Examples:
+ // 0x10 for 1.0 0x21 for 2.1
+#define MMCHS_REV_VREV_S 24
+#define MMCHS_REV_SREV_M 0x00FF0000
+#define MMCHS_REV_SREV_S 16
+#define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This
+ // status bit indicates the inverted
+ // state of interrupt signal for the
+ // module. By a power on reset or by
+ // setting a software reset for all
+ // (MMCHS_HCTL[SRA]) the interrupt
+ // signal shall be de-asserted and
+ // this status shall read 0.
+
+
+
+#endif // __HW_MMCHS_H__
diff --git a/cc3200/hal/inc/hw_nvic.h b/cc3200/hal/inc/hw_nvic.h
new file mode 100644
index 0000000000..1545f22651
--- /dev/null
+++ b/cc3200/hal/inc/hw_nvic.h
@@ -0,0 +1,1710 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg
+#define NVIC_ACTLR 0xE000E008 // Auxiliary Control
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
+ // Register
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg
+
+#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
+#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable
+#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable
+#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable
+#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable
+#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable
+
+#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable
+
+#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable
+#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable
+#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable
+#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable
+
+#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending
+#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending
+
+#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending
+#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending
+#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending
+#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending
+
+#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending
+
+#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending
+#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending
+#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending
+#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending
+
+#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit
+
+#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit
+#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit
+#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit
+#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit
+
+#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority
+#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority
+#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority
+#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority
+#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority
+#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority
+#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority
+#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority
+#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority
+#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority
+#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority
+#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority
+#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority
+#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority
+
+#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority
+#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority
+#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority
+#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority
+#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority
+#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority
+#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority
+#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority
+#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority
+#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority
+#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority
+#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority
+#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority
+#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority
+#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority
+#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority
+#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority
+#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority
+#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority
+#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority
+#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority
+#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority
+#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority
+#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority
+#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority
+#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority
+#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority
+#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority
+#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority
+#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority
+#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority
+#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority
+#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority
+#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority
+#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority
+
+
+
+#define NVIC_CPUID 0xE000ED00 // CPU ID Base
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset
+#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset
+ // Control
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control
+#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1
+#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2
+#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
+#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size
+ // Alias 1
+#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size
+ // Alias 2
+#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size
+ // Alias 3
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable
+
+#undef NVIC_EN1_INT_M
+#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
+
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable
+
+#undef NVIC_DIS1_INT_M
+#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
+
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending
+
+#undef NVIC_PEND1_INT_M
+#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending
+
+#undef NVIC_UNPEND1_INT_M
+#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active
+
+#undef NVIC_ACTIVE1_INT_M
+#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
+
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S 29
+#define NVIC_PRI14_INTC_S 21
+#define NVIC_PRI14_INTB_S 13
+#define NVIC_PRI14_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S 29
+#define NVIC_PRI15_INTC_S 21
+#define NVIC_PRI15_INTB_S 13
+#define NVIC_PRI15_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S 29
+#define NVIC_PRI16_INTC_S 21
+#define NVIC_PRI16_INTB_S 13
+#define NVIC_PRI16_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S 29
+#define NVIC_PRI17_INTC_S 21
+#define NVIC_PRI17_INTB_S 13
+#define NVIC_PRI17_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S 29
+#define NVIC_PRI18_INTC_S 21
+#define NVIC_PRI18_INTB_S 13
+#define NVIC_PRI18_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S 29
+#define NVIC_PRI19_INTC_S 21
+#define NVIC_PRI19_INTB_S 13
+#define NVIC_PRI19_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S 29
+#define NVIC_PRI20_INTC_S 21
+#define NVIC_PRI20_INTB_S 13
+#define NVIC_PRI20_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S 29
+#define NVIC_PRI21_INTC_S 21
+#define NVIC_PRI21_INTB_S 13
+#define NVIC_PRI21_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S 29
+#define NVIC_PRI22_INTC_S 21
+#define NVIC_PRI22_INTB_S 13
+#define NVIC_PRI22_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S 29
+#define NVIC_PRI23_INTC_S 21
+#define NVIC_PRI23_INTB_S 13
+#define NVIC_PRI23_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S 29
+#define NVIC_PRI24_INTC_S 21
+#define NVIC_PRI24_INTB_S 13
+#define NVIC_PRI24_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S 29
+#define NVIC_PRI25_INTC_S 21
+#define NVIC_PRI25_INTB_S 13
+#define NVIC_PRI25_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S 29
+#define NVIC_PRI26_INTC_S 21
+#define NVIC_PRI26_INTB_S 13
+#define NVIC_PRI26_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S 29
+#define NVIC_PRI27_INTC_S 21
+#define NVIC_PRI27_INTB_S 13
+#define NVIC_PRI27_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S 29
+#define NVIC_PRI28_INTC_S 21
+#define NVIC_PRI28_INTB_S 13
+#define NVIC_PRI28_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S 29
+#define NVIC_PRI29_INTC_S 21
+#define NVIC_PRI29_INTB_S 13
+#define NVIC_PRI29_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S 29
+#define NVIC_PRI30_INTC_S 21
+#define NVIC_PRI30_INTB_S 13
+#define NVIC_PRI30_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S 29
+#define NVIC_PRI31_INTC_S 21
+#define NVIC_PRI31_INTB_S 13
+#define NVIC_PRI31_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S 29
+#define NVIC_PRI32_INTC_S 21
+#define NVIC_PRI32_INTB_S 13
+#define NVIC_PRI32_INTA_S 5
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor
+
+#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
+
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number
+
+#undef NVIC_INT_CTRL_VEC_PEN_M
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
+
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number
+
+#undef NVIC_INT_CTRL_VEC_ACT_M
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
+
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset
+
+#undef NVIC_VTABLE_OFFSET_M
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
+
+#define NVIC_VTABLE_OFFSET_S 9
+
+#undef NVIC_VTABLE_OFFSET_S
+#define NVIC_VTABLE_OFFSET_S 10
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
+ // State Preservation
+
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
+ // Floating-Point Lazy State
+ // Preservation
+
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID
+
+#undef NVIC_SW_TRIG_INTID_M
+#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
+
+#define NVIC_SW_TRIG_INTID_S 0
+
+#endif // __HW_NVIC_H__
diff --git a/cc3200/hal/inc/hw_ocp_shared.h b/cc3200/hal/inc/hw_ocp_shared.h
new file mode 100644
index 0000000000..a52f6901b7
--- /dev/null
+++ b/cc3200/hal/inc/hw_ocp_shared.h
@@ -0,0 +1,3445 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_OCP_SHARED_H__
+#define __HW_OCP_SHARED_H__
+
+//*****************************************************************************
+//
+// The following are defines for the OCP_SHARED register offsets.
+//
+//*****************************************************************************
+#define OCP_SHARED_O_SEMAPHORE1 0x00000000
+#define OCP_SHARED_O_SEMAPHORE2 0x00000004
+#define OCP_SHARED_O_SEMAPHORE3 0x00000008
+#define OCP_SHARED_O_SEMAPHORE4 0x0000000C
+#define OCP_SHARED_O_SEMAPHORE5 0x00000010
+#define OCP_SHARED_O_SEMAPHORE6 0x00000014
+#define OCP_SHARED_O_SEMAPHORE7 0x00000018
+#define OCP_SHARED_O_SEMAPHORE8 0x0000001C
+#define OCP_SHARED_O_SEMAPHORE9 0x00000020
+#define OCP_SHARED_O_SEMAPHORE10 \
+ 0x00000024
+
+#define OCP_SHARED_O_SEMAPHORE11 \
+ 0x00000028
+
+#define OCP_SHARED_O_SEMAPHORE12 \
+ 0x0000002C
+
+#define OCP_SHARED_O_IC_LOCKER_ID \
+ 0x00000030
+
+#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \
+ 0x00000034
+
+#define OCP_SHARED_O_WL_SEMAPHORE_PEND \
+ 0x00000038
+
+#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \
+ 0x0000003C
+
+#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \
+ 0x00000040
+
+#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \
+ 0x00000044
+
+#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \
+ 0x00000048
+
+#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \
+ 0x0000004C
+
+#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \
+ 0x00000050
+
+#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \
+ 0x00000054
+
+#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \
+ 0x00000058
+
+#define OCP_SHARED_O_SSBD_SEED 0x0000005C
+#define OCP_SHARED_O_SSBD_CHK 0x00000060
+#define OCP_SHARED_O_SSBD_POLY_SEL \
+ 0x00000064
+
+#define OCP_SHARED_O_SPARE_REG_0 \
+ 0x00000068
+
+#define OCP_SHARED_O_SPARE_REG_1 \
+ 0x0000006C
+
+#define OCP_SHARED_O_SPARE_REG_2 \
+ 0x00000070
+
+#define OCP_SHARED_O_SPARE_REG_3 \
+ 0x00000074
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \
+ 0x000000A0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \
+ 0x000000A4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \
+ 0x000000A8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \
+ 0x000000AC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \
+ 0x000000B0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \
+ 0x000000B4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \
+ 0x000000B8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \
+ 0x000000BC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \
+ 0x000000C0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \
+ 0x000000C4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \
+ 0x000000C8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \
+ 0x000000CC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \
+ 0x000000D0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \
+ 0x000000D4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \
+ 0x000000D8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \
+ 0x000000DC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \
+ 0x000000E0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \
+ 0x000000E4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \
+ 0x000000E8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \
+ 0x000000EC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \
+ 0x000000F0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \
+ 0x000000F4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \
+ 0x000000F8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \
+ 0x000000FC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \
+ 0x00000100
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \
+ 0x00000104
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \
+ 0x00000108
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \
+ 0x0000010C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \
+ 0x00000110
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \
+ 0x00000114
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \
+ 0x00000118
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \
+ 0x0000011C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \
+ 0x00000120
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \
+ 0x00000124
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \
+ 0x00000128
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \
+ 0x0000012C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \
+ 0x00000130
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \
+ 0x00000134
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \
+ 0x00000138
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \
+ 0x0000013C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \
+ 0x00000140
+
+#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \
+ 0x00000144 // This register provide control to
+ // GPIO_CC3XXV1 IO PAD. Common
+ // control signals to all bottom Die
+ // IO's are controlled via this.
+
+#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \
+ 0x00000148
+
+#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \
+ 0x0000014C
+
+#define OCP_SHARED_O_D2D_MISC_PAD_CONF \
+ 0x00000150
+
+#define OCP_SHARED_O_SOP_CONF_OVERRIDE \
+ 0x00000154
+
+#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \
+ 0x00000158
+
+#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \
+ 0x0000015C
+
+#define OCP_SHARED_O_ALT_PC_VAL_NW \
+ 0x00000160
+
+#define OCP_SHARED_O_ALT_PC_VAL_APPS \
+ 0x00000164
+
+#define OCP_SHARED_O_SPARE_REG_4 \
+ 0x00000168
+
+#define OCP_SHARED_O_SPARE_REG_5 \
+ 0x0000016C
+
+#define OCP_SHARED_O_SH_SPI_CS_MASK \
+ 0x00000170
+
+#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \
+ 0x00000174
+
+#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \
+ 0x00000178
+
+#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \
+ 0x0000017C
+
+#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \
+ 0x00000180
+
+#define OCP_SHARED_O_CC3XX_DEV_PADCONF \
+ 0x00000184
+
+#define OCP_SHARED_O_SPARE_REG_8 \
+ 0x00000188
+
+#define OCP_SHARED_O_SPARE_REG_6 \
+ 0x0000018C
+
+#define OCP_SHARED_O_SPARE_REG_7 \
+ 0x00000190
+
+#define OCP_SHARED_O_APPS_WLAN_ORBIT \
+ 0x00000194
+
+#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \
+ 0x00000198
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE1 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE2 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE3 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE4 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE5 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE6 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE7 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE8 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE9 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE10 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE11 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE12 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_IC_LOCKER_ID register.
+//
+//******************************************************************************
+#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \
+ 0x00000007 // This register is used for
+ // allowing only one master OCP to
+ // perform write transactions to the
+ // OCP slaves. Each bit represents
+ // an IP in the following format: {
+ // JTAG,WLAN, NWP mcu}. As any of
+ // the bits is set to one, the
+ // correlating IP is preventing the
+ // other IP's from performing write
+ // transactions to the slaves. As
+ // the Inter Connect is locked, the
+ // only the locking IP can write to
+ // the register and by that
+ // releasing the lock. 3'b000 => IC
+ // is not locked. 3'b001 => IC is
+ // locked by NWP mcu. 3'b010 => IC
+ // is locked by WLAN. 3'b100 => IC
+ // is locked by JTAG.
+
+#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_MCU_SEMAPHORE_PEND register.
+//
+//******************************************************************************
+#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \
+ 0x0000FFFF // This register specifies the
+ // semaphore for which the NWP mcu
+ // is waiting to be released. It is
+ // set to the serial number of a
+ // given locked semaphore after it
+ // was read by the NWP mcu. Only
+ // [11:0] is used.
+
+#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_WL_SEMAPHORE_PEND register.
+//
+//******************************************************************************
+#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \
+ 0x0000FFFF // This register specifies the
+ // semaphore for which the WLAN is
+ // waiting to be released. It is set
+ // to the serial number of a given
+ // locked semaphore after it was
+ // read by the WLAN. Only [11:0] is
+ // used.
+
+#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register.
+//
+//******************************************************************************
+#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \
+ 0x0000FFFF // This information serves the IPs
+ // for knowing in which platform are
+ // they integrated at: 0 = CC31XX.
+
+#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \
+ 0x00000FFF // Captured/released semaphores
+ // status for the 12 semaphores.
+ // Each bit of the 12 bits
+ // represents a semaphore. 0 =>
+ // Semaphore Free. 1 => Semaphore
+ // Captured.
+
+#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_CONFIG_CTRL register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \
+ 0x00000010 // This bit is used to enable
+ // timeout mechanism for top_ocp_ic
+ // (for debug puropse). When 1 value
+ // , in case any ocp slave doesn't
+ // give sresponse within 16 cylcles
+ // top_ic will give error response
+ // itself to avoid bus hange.
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \
+ 0x00000008 // 1 bit should be accessible only
+ // in devinit. This will enable 0x4
+ // hack for apps processor
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \
+ 0x00000004 // 1 bit, should be accessible only
+ // in devinit. This will enable 0x4
+ // hack for nw processor
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \
+ 0x00000002 // When set NW can take over apps
+ // rom and flash via IDCODE bus.
+ // Apps will able to access this
+ // register only during devinit and
+ // reset value should be 0.
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \
+ 0x00000001 // When this bit is set to 0 WPSI
+ // host interface wil be selected,
+ // when this bit is set to 1 , WLAN
+ // host async bridge will be
+ // selected.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \
+ 0x3FFFFFFF // This register provides memss RAM
+ // column configuration for column 0
+ // to 9. 3 bits are allocated per
+ // column. This register is required
+ // to be configured before starting
+ // RAM access. Changing register
+ // setting while code is running
+ // will result into unpredictable
+ // memory behaviour. Register is
+ // supported to configured ones
+ // after core is booted up. 3 bit
+ // encoding per column is as
+ // follows: when 000 : WLAN, 001:
+ // NWP, 010: APPS, 011: PHY, 100:
+ // OCLA column 0 select: bit [2:0]
+ // :when 000 -> WLAN,001 -> NWP,010
+ // -> APPS, 011 -> PHY, 100 -> OCLA
+ // column 1 select: bit [5:3]
+ // :column 2 select: bit [8 : 6]:
+ // column 3 select : bit [11: 9]
+ // column 4 select : bit [14:12]
+ // column 5 select : bit [17:15]
+ // column 6 select : bit [20:18]
+ // column 7 select : bit [23:21]
+ // column 8 select : bit [26:24]
+ // column 9 select : bit [29:27]
+ // column 10 select
+
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \
+ 0x00000FFF // This register provides memss RAM
+ // column configuration for column
+ // 10 to 15. 3 bits are allocated
+ // per column. This register is
+ // required to be configured before
+ // starting RAM access. Changing
+ // register setting while code is
+ // running will result into
+ // unpredictable memory behaviour.
+ // Register is supported to
+ // configured ones after core is
+ // booted up. 3 bit encoding per
+ // column is as follows: when 000 :
+ // WLAN, 001: NWP, 010: APPS, 011:
+ // PHY, 100: OCLA column 11 select :
+ // bit [2:0] column 12 select : bit
+ // [5:3] column 13 select : bit [8 :
+ // 6] column 14 select :
+
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_WLAN_ELP_WAKE_EN register.
+//
+//******************************************************************************
+#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \
+ 0x00000001 // when '1' : signal will enabled
+ // ELP power doamin when '0': ELP is
+ // not powered up.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register.
+//
+//******************************************************************************
+#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module. This register is not used
+ // , similar register availble in
+ // GPRCM space.
+
+#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register.
+//
+//******************************************************************************
+#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SSBD_SEED register.
+//
+//******************************************************************************
+#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SSBD_CHK register.
+//
+//******************************************************************************
+#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SSBD_POLY_SEL register.
+//
+//******************************************************************************
+#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \
+ 0x00000003 // 2 bit, Writable only during
+ // devinit, and whole 2 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_0 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \
+ 0xFFFFFFFF // Devinit code should look for
+ // whether corresponding fuse is
+ // blown and if blown write to the
+ // 11th bit of this register to
+ // disable flshtst interface
+
+#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_1 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_2 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_3 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \
+ 0xFFFFFFFF // APPS Software register
+
+#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." "For example in
+ // case of I2C Value gets latched at
+ // rising edge of RET33.""" """ 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \
+ 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." "For example in
+ // case of I2C Value gets latched at
+ // rising edge of RET33.""" """ 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \
+ 0x00000080 // when '1' enable ISO A control to
+ // D2D Pads else ISO is disabled.
+ // For these PADS to be functional
+ // this signals should be set 0.
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \
+ 0x00000040 // when '1' enable ISO Y control to
+ // D2D Pads else ISO is disabled.
+ // For these PADS to be functional
+ // this signals should be set 0.
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \
+ 0x00000020 // If level ‘1’ enables the PAD to
+ // ODI path for JTAG PADS [PAD 23,
+ // 24, 28, 29]. Else ODI is pulled
+ // ‘Low’ regardless of PAD level."
+ // "Value gets latched at rising
+ // edge of RET33.""" """
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \
+ 0x00000018 // 00’: hysteriris = 10% of VDDS
+ // (difference between upper and
+ // lower threshold of the schmit
+ // trigger) ‘01’: hysteriris = 20%
+ // of VDDS (difference between upper
+ // and lower threshold of the schmit
+ // trigger) ‘10’: hysteriris = 30%
+ // of VDDS (difference between upper
+ // and lower threshold of the schmit
+ // trigger) ‘11’: hysteriris = 40%
+ // of VDDS (difference between upper
+ // and lower threshold of the schmit
+ // trigger)" """
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \
+ 0x00000004 // If logic ‘0’ there is no
+ // hysteresis. Set to ‘1’ to enable
+ // hysteresis. Leave the choice to
+ // customers"""
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \
+ 0x00000002 // Normal functional operation set
+ // this to logic ‘1’ to increase the
+ // speed of the o/p buffer at the
+ // cost of 0.2uA static current
+ // consumption per IO. During IDDQ
+ // test and during Hibernate this
+ // would be forced to logic ‘0’.
+ // Value is not latched at rising
+ // edge of RET33.""
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \
+ 0x00000001 // If level ‘1’ enables the PAD to
+ // ODI path. Else ODI is pulled
+ // ‘Low’ regardless of PAD level."
+ // "Value gets latched at rising
+ // edge of RET33.""" """
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register.
+//
+//******************************************************************************
+#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \
+ 0x0000003F // this register implements common
+ // IO control to all devement mode
+ // PADs; these PADs are DEV_PAD33 to
+ // DEV_PAD39. Bit [1:0] : Drive
+ // strength control. These 2 bits
+ // are connected to DEV PAD drive
+ // strength control. possible drive
+ // stregnths are 2MA, 4MA and 6 MA
+ // for the these IO's. bit 0: when
+ // set to logic value '1' enable 2MA
+ // drive strength for DEVPAD01 to 07
+ // bit 1: when set to logic value
+ // '1' enable 4MA drive strength for
+ // DEVPAD01 to 07. bit[3:2] : WK
+ // PULL UP and PULL down control.
+ // These 2 bits provide IWKPUEN and
+ // IWKPDEN control for all DEV IO's.
+ // bit 2: when set to logic value
+ // '1' enable WKPU to DEVPAD01 to 07
+ // bit 3: when set to logic value
+ // '1' enable WKPD to DEVPAD01 to
+ // 07. bit 4: WK PULL control for
+ // DEV_PKG_DETECT pin. when '1'
+ // pullup enabled else it is
+ // disable. bit 5: when set to logic
+ // value '1' enable 8MA drive
+ // strength for DEVPAD01 to 07.
+
+#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register.
+//
+//******************************************************************************
+#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \
+ 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+ // this register control OEN2X pin
+ // of D2D TOSTACK PAD: OEN1X and
+ // OEN2X decoding is as follows:
+ // "when ""00"" :" "when ""01"" :
+ // dirve strength is '1' and output
+ // buffer enabled." "when ""10"" :
+ // drive strength is 2 and output
+ // buffer is disabled." "when ""11""
+ // : dirve strength is '3' and
+ // output buffer enabled."
+
+#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_D2D_MISC_PAD_CONF register.
+//
+//******************************************************************************
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \
+ 0x00000200 // This register provide OEN2X
+ // control to D2D PADS OEN/OEN2X
+ // control. When 0 : Act as input
+ // buffer else output buffer with
+ // drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \
+ 0x00000100 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \
+ 0x00000080 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \
+ 0x00000040 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \
+ 0x00000020 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \
+ 0x00000010 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \
+ 0x00000008 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \
+ 0x00000007 // D2D SPARE PAD OEN/OEN2X control.
+ // When 0: Act as input buffer else
+ // output buffer with drive strength
+ // 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SOP_CONF_OVERRIDE register.
+//
+//******************************************************************************
+#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \
+ 0x00000001 // when '1' : signal will ovberride
+ // SoP setting of JTAG PADS. when
+ // '0': SoP setting will control
+ // JTAG PADs [ TDI, TDO, TMS, TCK]
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \
+ 0x00000020 // This register contains debug
+ // subsystem status bits From APPS
+ // MCU status bit to indicates
+ // whether serial wire or 4 pins
+ // jtag select.
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \
+ 0x00000010 // cjtag bypass bit select
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \
+ 0x00000008 // serial wire interface bit select
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \
+ 0x00000004 // apps tap enable status
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \
+ 0x00000002 // tap enable status
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \
+ 0x00000001 // ssbd unlock status
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \
+ 0x0000FFFF // debug mux select register. Upper
+ // 8 bits are used for debug module
+ // selection. Lower 8 bit [7:0] used
+ // inside debug module for selecting
+ // module specific signals.
+ // Bits[15:8: when set x"00" : GPRCM
+ // debug bus. When "o1" : SDIO debug
+ // debug bus when x"02" :
+ // autonoumous SPI when x"03" :
+ // TOPIC when x"04": memss when
+ // x"25": mcu debug bus : APPS debug
+ // when x"45": mcu debug bus : NWP
+ // debug when x"65": mcu debug bus :
+ // AHB2VBUS debug when x"85": mcu
+ // debug bus : VBUS2HAB debug when
+ // x"95": mcu debug bus : RCM debug
+ // when x"A5": mcu debug bus :
+ // crypto debug when x"06": WLAN
+ // debug bus when x"07": debugss bus
+ // when x"08": ADC debug when x"09":
+ // SDIO PHY debug bus then "others"
+ // : no debug is selected
+
+#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_ALT_PC_VAL_NW register.
+//
+//******************************************************************************
+#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \
+ 0xFFFFFFFF // 32 bit. Program counter value
+ // for 0x4 address when Alt_pc_en_nw
+ // is set.
+
+#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_ALT_PC_VAL_APPS register.
+//
+//******************************************************************************
+#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \
+ 0xFFFFFFFF // 32 bit. Program counter value
+ // for 0x4 address when
+ // Alt_pc_en_apps is set
+
+#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_4 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \
+ 0xFFFFFFFE // HW register
+
+#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1
+#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \
+ 0x00000001 // Data to the top die launched at
+ // negative edge instead of positive
+ // edge.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_5 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \
+ 0xFFFFFFFF // HW register
+
+#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SH_SPI_CS_MASK register.
+//
+//******************************************************************************
+#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \
+ 0x0000000F // ( chip select 0 is unmasked
+ // after reset. When ‘1’ : CS is
+ // unmasked or else masked. Valid
+ // configurations are 1000, 0100,
+ // 0010 or 0001. Any other setting
+ // can lead to unpredictable
+ // behavior.
+
+#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEVICE_TYPE register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \
+ 0x00000060 // reserved bits tied off "00".
+
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \
+ 0x0000001F // CC3XX Device type information.
+
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register.
+//
+//******************************************************************************
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \
+ 0x000000F0 // [4] 1: switch between
+ // WLAN_I2C_SCL and
+ // TOP_GPIO_PORT4_I2C closes 0:
+ // switch opens [5] 1: switch
+ // between WLAN_I2C_SCL and
+ // TOP_VSENSE_PORT closes 0: switch
+ // opens [6] 1: switch between
+ // WLAN_I2C_SCL and WLAN_ANA_TP4
+ // closes 0: switch opens [7]
+ // Reserved
+
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \
+ 0x0000000F // [0] 1: switch between
+ // WLAN_I2C_SDA and
+ // TOP_GPIO_PORT3_I2C closes 0:
+ // switch opens [1] 1: switch
+ // between WLAN_I2C_SDA and
+ // TOP_IFORCE_PORT closes 0: switch
+ // opens [2] 1: switch between
+ // WLAN_I2C_SDA and WLAN_ANA_TP3
+ // closes 0: switch opens [3]
+ // Reserved
+
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \
+ 0x00000001 // when '0' indicates package type
+ // is development.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_AUTONMS_SPICLK_SEL register.
+//
+//******************************************************************************
+#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \
+ 0x00000002 // This bit is used to bypass MCPSI
+ // autonomous mode .if this bit is 1
+ // autonomous MCSPI logic will be
+ // bypassed and it will act as link
+ // SPI
+
+#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \
+ 0x00000001 // This bit is used in SPI
+ // Autonomous mode to switch clock
+ // from system clock to SPI clk that
+ // is coming from PAD. When value 1
+ // PAD SPI clk is used as system
+ // clock in LPDS mode by SPI as well
+ // as autonomous wrapper logic.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEV_PADCONF register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \
+ 0x0000FFFF
+
+#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_IDMEM_TIM_UPDATE register.
+//
+//******************************************************************************
+#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \
+ 0xFFFFFFFF
+
+#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_6 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_7 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_APPS_WLAN_ORBIT register.
+//
+//******************************************************************************
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \
+ 0xFFFFFC00 // Spare bit
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \
+ 0x00000200 // A rising edge on this bit
+ // indicates that the test case
+ // passes. This bit would be brought
+ // out on the pin interface during
+ // ORBIT.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \
+ 0x00000100 // This register bit is writable by
+ // the FW and when set to 1 it
+ // indicates the start of a test
+ // execution. A failing edge on this
+ // bit indicates that the test
+ // execution is complete. This bit
+ // would be brought out on the pin
+ // interface during ORBIT.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \
+ 0x000000FC // Implies the test case ID that
+ // needs to run.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \
+ 0x00000002 // This bit is used to trigger the
+ // execution of test cases within
+ // the (ROM based) IP.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \
+ 0x00000001 // When this bit is 1 it implies
+ // ORBIT mode of operation and the
+ // (ROM based) IP start the
+ // execution from a test case
+ // perspective
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register.
+//
+//******************************************************************************
+#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \
+ 0xFFFFFFFF // scratch pad register.
+
+#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0
+
+
+
+#endif // __HW_OCP_SHARED_H__
diff --git a/cc3200/hal/inc/hw_shamd5.h b/cc3200/hal/inc/hw_shamd5.h
new file mode 100644
index 0000000000..cf6254f5d2
--- /dev/null
+++ b/cc3200/hal/inc/hw_shamd5.h
@@ -0,0 +1,1242 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_SHAMD5_H__
+#define __HW_SHAMD5_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SHAMD5_P register offsets.
+//
+//*****************************************************************************
+#define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for
+ // MD5 [159:128] for SHA-1 [255:224]
+ // for SHA-2 / HMAC Key [31:0] for
+ // HMAC key proc READ: Outer Digest
+ // [127:96] for MD5 [159:128] for
+ // SHA-1 [255:224] for SHA-2
+#define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for
+ // MD5 [127:96] for SHA-1 [223:192]
+ // for SHA-2 / HMAC Key [63:32] for
+ // HMAC key proc READ: Outer Digest
+ // [95:64] for MD5 [127:96] for
+ // SHA-1 [223:192] for SHA-2
+#define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for
+ // MD5 [95:64] for SHA-1 [191:160]
+ // for SHA-2 / HMAC Key [95:64] for
+ // HMAC key proc READ: Outer Digest
+ // [63:32] for MD5 [95:64] for SHA-1
+ // [191:160] for SHA-2
+#define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for
+ // MD5 [63:31] for SHA-1 [159:128]
+ // for SHA-2 / HMAC Key [127:96] for
+ // HMAC key proc READ: Outer Digest
+ // [31:0] for MD5 [63:32] for SHA-1
+ // [159:128] for SHA-2
+#define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for
+ // SHA-1 [127:96] for SHA-2 / HMAC
+ // Key [159:128] for HMAC key proc
+ // READ: Outer Digest [31:0] for
+ // SHA-1 [127:96] for SHA-2
+#define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for
+ // SHA-2 / HMAC Key [191:160] for
+ // HMAC key proc READ: Outer Digest
+ // [95:64] for SHA-2
+#define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for
+ // SHA-2 / HMAC Key [223:192] for
+ // HMAC key proc READ: Outer Digest
+ // [63:32] for SHA-2
+#define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for
+ // SHA-2 / HMAC Key [255:224] for
+ // HMAC key proc READ: Outer Digest
+ // [31:0] for SHA-2
+#define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest
+ // [127:96] for MD5 [159:128] for
+ // SHA-1 [255:224] for SHA-2 / HMAC
+ // Key [287:256] for HMAC key proc
+ // READ: Intermediate / Inner Digest
+ // [127:96] for MD5 [159:128] for
+ // SHA-1 [255:224] for SHA-2 /
+ // Result Digest/MAC [127:96] for
+ // MD5 [159:128] for SHA-1 [223:192]
+ // for SHA-2 224 [255:224] for SHA-2
+ // 256
+#define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest
+ // [95:64] for MD5 [127:96] for
+ // SHA-1 [223:192] for SHA-2 / HMAC
+ // Key [319:288] for HMAC key proc
+ // READ: Intermediate / Inner Digest
+ // [95:64] for MD5 [127:96] for
+ // SHA-1 [223:192] for SHA-2 /
+ // Result Digest/MAC [95:64] for MD5
+ // [127:96] for SHA-1 [191:160] for
+ // SHA-2 224 [223:192] for SHA-2 256
+#define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest
+ // [63:32] for MD5 [95:64] for SHA-1
+ // [191:160] for SHA- 2 / HMAC Key
+ // [351:320] for HMAC key proc READ:
+ // Intermediate / Inner Digest
+ // [63:32] for MD5 [95:64] for SHA-1
+ // [191:160] for SHA-2 / Result
+ // Digest/MAC [63:32] for MD5
+ // [95:64] for SHA-1 [159:128] for
+ // SHA-2 224 [191:160] for SHA-2 256
+#define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest
+ // [31:0] for MD5 [63:32] for SHA-1
+ // [159:128] for SHA-2 / HMAC Key
+ // [383:352] for HMAC key proc READ:
+ // Intermediate / Inner Digest
+ // [31:0] for MD5 [63:32] for SHA-1
+ // [159:128] for SHA-2 / Result
+ // Digest/MAC [31:0] for MD5 [63:32]
+ // for SHA-1 [127:96] for SHA-2 224
+ // [159:128] for SHA-2 256
+#define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest
+ // [31:0] for SHA-1 [127:96] for
+ // SHA-2 / HMAC Key [415:384] for
+ // HMAC key proc READ: Intermediate
+ // / Inner Digest [31:0] for SHA-1
+ // [127:96] for SHA-2 / Result
+ // Digest/MAC [31:0] for SHA-1
+ // [95:64] for SHA-2 224 [127:96]
+ // for SHA-2 256
+#define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest
+ // [95:64] for SHA-2 / HMAC Key
+ // [447:416] for HMAC key proc READ:
+ // Intermediate / Inner Digest
+ // [95:64] for SHA-2 / Result
+ // Digest/MAC [63:32] for SHA-2 224
+ // [95:64] for SHA-2 256
+#define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest
+ // [63:32] for SHA-2 / HMAC Key
+ // [479:448] for HMAC key proc READ:
+ // Intermediate / Inner Digest
+ // [63:32] for SHA-2 / Result
+ // Digest/MAC [31:0] for SHA-2 224
+ // [63:32] for SHA-2 256
+#define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest
+ // [31:0] for SHA-2 / HMAC Key
+ // [511:480] for HMAC key proc READ:
+ // Intermediate / Inner Digest
+ // [31:0] for SHA-2 / Result
+ // Digest/MAC [31:0] for SHA-2 256
+#define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count
+ // ([31:6] only [5:0] assumed 0)
+ // READ: Result / IntermediateDigest
+ // Count The initial digest byte
+ // count for hash/HMAC continue
+ // operations (HMAC Key Processing =
+ // 0 and Use Algorithm Constants =
+ // 0) on the Secure World must be
+ // written to this register prior to
+ // starting the operation by writing
+ // to S_HASH_MODE. When either HMAC
+ // Key Processing is 1 or Use
+ // Algorithm Constants is 1 this
+ // register does not need to be
+ // written it will be overwritten
+ // with 64 (1 hash block of key XOR
+ // ipad) or 0 respectively
+ // automatically. When starting a
+ // HMAC operation from pre-computes
+ // (HMAC Key Processing is 0) then
+ // the value 64 must be written here
+ // to compensate for the appended
+ // key XOR ipad block. Note that the
+ // value written should always be a
+ // 64 byte multiple the lower 6 bits
+ // written are ignored. The updated
+ // digest byte count (initial digest
+ // byte count + bytes processed) can
+ // be read from this register when
+ // the status register indicates
+ // that the operation is done or
+ // suspended due to a context switch
+ // request or when a Secure World
+ // context out DMA is requested. In
+ // Advanced DMA mode when not
+ // suspended with a partial result
+ // reading the SHAMD5_DIGEST_COUNT
+ // register triggers the Hash/HMAC
+ // Engine to start the next context
+ // input DMA. Therefore reading the
+ // SHAMD5_DIGEST_COUNT register
+ // should always be the last
+ // context-read action if not
+ // suspended with a partial result
+ // (i.e. PartHashReady interrupt not
+ // pending).
+#define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE
+#define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining
+ // Byte Count (bytes) READ:
+ // Remaining Byte Count. The value
+ // programmed MUST be a 64-byte
+ // multiple if Close Hash is set to
+ // 0. This register is also the
+ // trigger to start processing: once
+ // this register is written the core
+ // will commence requesting input
+ // data via DMA or IRQ (if
+ // programmed length > 0) and start
+ // processing. The remaining byte
+ // count for the active operation
+ // can be read from this register
+ // when the interrupt status
+ // register indicates that the
+ // operation is suspended due to a
+ // context switch request.
+#define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0
+#define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1
+#define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2
+#define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3
+#define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4
+#define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5
+#define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6
+#define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7
+#define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8
+#define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9
+#define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10
+#define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11
+#define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12
+#define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13
+#define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14
+#define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15
+#define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV
+#define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG
+#define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS
+#define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS
+#define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The
+ // SHAMD5_IRQENABLE register contains
+ // an enable bit for each unique
+ // interrupt for the public side. An
+ // interrupt is enabled when both
+ // the global enable in
+ // SHAMD5_SYSCONFIG (PIT_en) and the
+ // bit in this register are both set
+ // to 1. An interrupt that is
+ // enabled is propagated to the
+ // SINTREQUEST_P output. Please note
+ // that the dedicated partial hash
+ // output (SINTREQUEST_PART_P) is
+ // not affected by this register it
+ // is only affected by the global
+ // enable SHAMD5_SYSCONFIG (PIT_en).
+#define SHAMD5_O_HASH512_ODIGEST_A \
+ 0x00000200
+
+#define SHAMD5_O_HASH512_ODIGEST_B \
+ 0x00000204
+
+#define SHAMD5_O_HASH512_ODIGEST_C \
+ 0x00000208
+
+#define SHAMD5_O_HASH512_ODIGEST_D \
+ 0x0000020C
+
+#define SHAMD5_O_HASH512_ODIGEST_E \
+ 0x00000210
+
+#define SHAMD5_O_HASH512_ODIGEST_F \
+ 0x00000214
+
+#define SHAMD5_O_HASH512_ODIGEST_G \
+ 0x00000218
+
+#define SHAMD5_O_HASH512_ODIGEST_H \
+ 0x0000021C
+
+#define SHAMD5_O_HASH512_ODIGEST_I \
+ 0x00000220
+
+#define SHAMD5_O_HASH512_ODIGEST_J \
+ 0x00000224
+
+#define SHAMD5_O_HASH512_ODIGEST_K \
+ 0x00000228
+
+#define SHAMD5_O_HASH512_ODIGEST_L \
+ 0x0000022C
+
+#define SHAMD5_O_HASH512_ODIGEST_M \
+ 0x00000230
+
+#define SHAMD5_O_HASH512_ODIGEST_N \
+ 0x00000234
+
+#define SHAMD5_O_HASH512_ODIGEST_O \
+ 0x00000238
+
+#define SHAMD5_O_HASH512_ODIGEST_P \
+ 0x0000023C
+
+#define SHAMD5_O_HASH512_IDIGEST_A \
+ 0x00000240
+
+#define SHAMD5_O_HASH512_IDIGEST_B \
+ 0x00000244
+
+#define SHAMD5_O_HASH512_IDIGEST_C \
+ 0x00000248
+
+#define SHAMD5_O_HASH512_IDIGEST_D \
+ 0x0000024C
+
+#define SHAMD5_O_HASH512_IDIGEST_E \
+ 0x00000250
+
+#define SHAMD5_O_HASH512_IDIGEST_F \
+ 0x00000254
+
+#define SHAMD5_O_HASH512_IDIGEST_G \
+ 0x00000258
+
+#define SHAMD5_O_HASH512_IDIGEST_H \
+ 0x0000025C
+
+#define SHAMD5_O_HASH512_IDIGEST_I \
+ 0x00000260
+
+#define SHAMD5_O_HASH512_IDIGEST_J \
+ 0x00000264
+
+#define SHAMD5_O_HASH512_IDIGEST_K \
+ 0x00000268
+
+#define SHAMD5_O_HASH512_IDIGEST_L \
+ 0x0000026C
+
+#define SHAMD5_O_HASH512_IDIGEST_M \
+ 0x00000270
+
+#define SHAMD5_O_HASH512_IDIGEST_N \
+ 0x00000274
+
+#define SHAMD5_O_HASH512_IDIGEST_O \
+ 0x00000278
+
+#define SHAMD5_O_HASH512_IDIGEST_P \
+ 0x0000027C
+
+#define SHAMD5_O_HASH512_DIGEST_COUNT \
+ 0x00000280
+
+#define SHAMD5_O_HASH512_MODE 0x00000284
+#define SHAMD5_O_HASH512_LENGTH 0x00000288
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_A_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_B_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_C_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_D_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_E_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_F_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_G_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register.
+//
+//******************************************************************************
+#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_ODIGEST_H_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_A_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_B_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_C_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_D_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_E_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_F_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_G_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register.
+//
+//******************************************************************************
+#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_IDIGEST_H_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_DIGEST_COUNT register.
+//
+//******************************************************************************
+#define SHAMD5_DIGEST_COUNT_DATA_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DIGEST_COUNT_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_MODE register.
+//
+//******************************************************************************
+#define SHAMD5_MODE_HMAC_OUTER_HASH \
+ 0x00000080 // The HMAC Outer Hash is performed
+ // on the hash digest when the inner
+ // hash hash finished (block length
+ // exhausted and final hash
+ // performed if close_hash is 1).
+ // This bit should normally be set
+ // together with close_hash to
+ // finish the inner hash first or
+ // Block Length should be zero (HMAC
+ // continue with the just outer hash
+ // to be done). Auto cleared
+ // internally when outer hash
+ // performed. 0 No operation 1 hmac
+ // processing
+
+#define SHAMD5_MODE_HMAC_KEY_PROC \
+ 0x00000020 // Performs HMAC key processing on
+ // the 512 bit HMAC key loaded into
+ // the SHAMD5_IDIGEST_{A to H} and
+ // SHAMD5_ODIGEST_{A to H} register
+ // block. Once HMAC key processing
+ // is finished this bit is
+ // automatically cleared and the
+ // resulting Inner and Outer digest
+ // is available from
+ // SHAMD5_IDIGEST_{A to H} and
+ // SHAMD5_ODIGEST_{A to H}
+ // respectively after which regular
+ // hash processing (using
+ // SHAMD5_IDIGEST_{A to H} as initial
+ // digest) will commence until the
+ // Block Length is exhausted. 0 No
+ // operation. 1 Hmac processing.
+
+#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the
+ // hash/HMAC will be 'closed' at the
+ // end of the block as per
+ // MD5/SHA-1/SHA-2 specification
+ // (i.e. appropriate padding is
+ // added) or no padding is done
+ // allowing the hash to be continued
+ // later. However if the hash/HMAC
+ // is not closed then the Block
+ // Length MUST be a multiple of 64
+ // bytes to ensure correct
+ // operation. Auto cleared
+ // internally when hash closed. 0 No
+ // padding hash computation can be
+ // contimued. 1 Last packet will be
+ // padded.
+#define SHAMD5_MODE_ALGO_CONSTANT \
+ 0x00000008 // The initial digest register will
+ // be overwritten with the algorithm
+ // constants for the selected
+ // algorithm when hashing and the
+ // initial digest count register
+ // will be reset to 0. This will
+ // start a normal hash operation.
+ // When continuing an existing hash
+ // or when performing an HMAC
+ // operation this register must be
+ // set to 0 and the
+ // intermediate/inner digest or HMAC
+ // key and digest count need to be
+ // written to the context input
+ // registers prior to writing
+ // SHAMD5_MODE. Auto cleared
+ // internally after first block
+ // processed. 0 Use pre-calculated
+ // digest (from an other operation)
+ // 1 Use constants of the selected
+ // algo.
+
+#define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash
+ // algorithm to be used for
+ // processing: 0x0 md5_128 algorithm
+ // 0x1 sha1_160 algorithm 0x2
+ // sha2_224 algorithm 0x3 sha2_256
+ // algorithm
+#define SHAMD5_MODE_ALGO_S 1
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_LENGTH register.
+//
+//******************************************************************************
+#define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data
+#define SHAMD5_LENGTH_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA0_IN_DATA0_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA0_IN_DATA0_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA1_IN_DATA1_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA1_IN_DATA1_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA2_IN_DATA2_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA2_IN_DATA2_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA3_IN_DATA3_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA3_IN_DATA3_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA4_IN_DATA4_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA4_IN_DATA4_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA5_IN_DATA5_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA5_IN_DATA5_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA6_IN_DATA6_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA6_IN_DATA6_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA7_IN_DATA7_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA7_IN_DATA7_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA8_IN_DATA8_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA8_IN_DATA8_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA9_IN_DATA9_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA9_IN_DATA9_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA10_IN_DATA10_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA10_IN_DATA10_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA11_IN_DATA11_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA11_IN_DATA11_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA12_IN_DATA12_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA12_IN_DATA12_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA13_IN_DATA13_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA13_IN_DATA13_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA14_IN_DATA14_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA14_IN_DATA14_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register.
+//
+//******************************************************************************
+#define SHAMD5_DATA15_IN_DATA15_IN_M \
+ 0xFFFFFFFF // data
+
+#define SHAMD5_DATA15_IN_DATA15_IN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_REVISION register.
+//
+//******************************************************************************
+#define SHAMD5_REVISION_SCHEME_M 0xC0000000
+#define SHAMD5_REVISION_SCHEME_S 30
+#define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
+ // compatible module family. If
+ // there is no level of software
+ // compatibility a new Func number
+ // (and hence REVISION) should be
+ // assigned.
+#define SHAMD5_REVISION_FUNC_S 16
+#define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
+ // design owner. RTL follows a
+ // numbering such as X.Y.R.Z which
+ // are explained in this table. R
+ // changes ONLY when: (1) PDS
+ // uploads occur which may have been
+ // due to spec changes (2) Bug fixes
+ // occur (3) Resets to '0' when X or
+ // Y changes. Design team has an
+ // internal 'Z' (customer invisible)
+ // number which increments on every
+ // drop that happens due to DV and
+ // RTL updates. Z resets to 0 when R
+ // increments.
+#define SHAMD5_REVISION_R_RTL_S 11
+#define SHAMD5_REVISION_X_MAJOR_M \
+ 0x00000700 // Major Revision (X) maintained by
+ // IP specification owner. X changes
+ // ONLY when: (1) There is a major
+ // feature addition. An example
+ // would be adding Master Mode to
+ // Utopia Level2. The Func field (or
+ // Class/Type in old PID format)
+ // will remain the same. X does NOT
+ // change due to: (1) Bug fixes (2)
+ // Change in feature parameters.
+
+#define SHAMD5_REVISION_X_MAJOR_S 8
+#define SHAMD5_REVISION_CUSTOM_M 0x000000C0
+#define SHAMD5_REVISION_CUSTOM_S 6
+#define SHAMD5_REVISION_Y_MINOR_M \
+ 0x0000003F // Minor Revision (Y) maintained by
+ // IP specification owner. Y changes
+ // ONLY when: (1) Features are
+ // scaled (up or down). Flexibility
+ // exists in that this feature
+ // scalability may either be
+ // represented in the Y change or a
+ // specific register in the IP that
+ // indicates which features are
+ // exactly available. (2) When
+ // feature creeps from Is-Not list
+ // to Is list. But this may not be
+ // the case once it sees silicon; in
+ // which case X will change. Y does
+ // NOT change due to: (1) Bug fixes
+ // (2) Typos or clarifications (3)
+ // major functional/feature
+ // change/addition/deletion. Instead
+ // these changes may be reflected
+ // via R S X as applicable. Spec
+ // owner maintains a
+ // customer-invisible number 'S'
+ // which changes due to: (1)
+ // Typos/clarifications (2) Bug
+ // documentation. Note that this bug
+ // is not due to a spec change but
+ // due to implementation.
+ // Nevertheless the spec tracks the
+ // IP bugs. An RTL release (say for
+ // silicon PG1.1) that occurs due to
+ // bug fix should document the
+ // corresponding spec number (X.Y.S)
+ // in its release notes.
+
+#define SHAMD5_REVISION_Y_MINOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register.
+//
+//******************************************************************************
+#define SHAMD5_SYSCONFIG_PADVANCED \
+ 0x00000080 // If set to 1 Advanced mode is
+ // enabled for the Secure World. If
+ // set to 0 Legacy mode is enabled
+ // for the Secure World.
+
+#define SHAMD5_SYSCONFIG_PCONT_SWT \
+ 0x00000040 // Finish all pending data and
+ // context DMA input requests (but
+ // will not assert any new requests)
+ // finish processing all data in the
+ // module and provide a saved
+ // context (partial hash result
+ // updated digest count remaining
+ // length updated mode information
+ // where applicable) for the last
+ // operation that was interrupted so
+ // that it can be resumed later.
+
+#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008
+#define SHAMD5_SYSCONFIG_PIT_EN 0x00000004
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register.
+//
+//******************************************************************************
+#define SHAMD5_SYSSTATUS_RESETDONE \
+ 0x00000001 // data
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register.
+//
+//******************************************************************************
+#define SHAMD5_IRQSTATUS_CONTEXT_READY \
+ 0x00000008 // indicates that the secure side
+ // context input registers are
+ // available for a new context for
+ // the next packet to be processed.
+
+#define SHAMD5_IRQSTATUS_PARTHASH_READY \
+ 0x00000004 // After a secure side context
+ // switch request this bit will read
+ // as 1 indicating that the saved
+ // context is available from the
+ // secure side context output
+ // registers. Note that if the
+ // context switch request coincides
+ // with a final hash (when hashing)
+ // or an outer hash (when doing
+ // HMAC) that PartHashReady will not
+ // become active but a regular
+ // Output Ready will occur instead
+ // (indicating that the result is
+ // final and therefore no
+ // continuation is required).
+
+#define SHAMD5_IRQSTATUS_INPUT_READY \
+ 0x00000002 // indicates that the secure side
+ // data FIFO is ready to receive the
+ // next 64 byte data block.
+
+#define SHAMD5_IRQSTATUS_OUTPUT_READY \
+ 0x00000001 // Indicates that a (partial)
+ // result or saved context is
+ // available from the secure side
+ // context output registers.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register.
+//
+//******************************************************************************
+#define SHAMD5_IRQENABLE_M_CONTEXT_READY \
+ 0x00000008 // mask for context ready
+
+#define SHAMD5_IRQENABLE_M_PARTHASH_READY \
+ 0x00000004 // mask for partial hash
+
+#define SHAMD5_IRQENABLE_M_INPUT_READY \
+ 0x00000002 // mask for input_ready
+
+#define SHAMD5_IRQENABLE_M_OUTPUT_READY \
+ 0x00000001 // mask for output_ready
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_A register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_A_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_B register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_B_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_C register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_C_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_D register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_D_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_E register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_E_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_F register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_F_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_G register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_G_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_H register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_H_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_I register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_I_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_J register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_J_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_K register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_K_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_L register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_L_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_M register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_M_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_N register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_N_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_O register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_O_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_ODIGEST_P register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_ODIGEST_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_ODIGEST_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_A register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_A_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_B register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_B_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_C register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_C_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_D register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_D_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_E register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_E_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_F register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_F_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_G register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_G_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_H register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_H_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_I register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_I_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_J register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_J_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_K register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_K_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_L register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_L_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_M register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_M_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_N register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_N_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_O register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_O_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_IDIGEST_P register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_IDIGEST_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_IDIGEST_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_DIGEST_COUNT register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_MODE register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_MODE_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_MODE_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// SHAMD5_O_HASH512_LENGTH register.
+//
+//******************************************************************************
+#define SHAMD5_HASH512_LENGTH_DATA_M \
+ 0xFFFFFFFF
+
+#define SHAMD5_HASH512_LENGTH_DATA_S 0
+
+
+
+#endif // __HW_SHAMD5_H__
diff --git a/cc3200/hal/inc/hw_stack_die_ctrl.h b/cc3200/hal/inc/hw_stack_die_ctrl.h
new file mode 100644
index 0000000000..eba31e4f07
--- /dev/null
+++ b/cc3200/hal/inc/hw_stack_die_ctrl.h
@@ -0,0 +1,764 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+
+#ifndef __HW_STACK_DIE_CTRL_H__
+#define __HW_STACK_DIE_CTRL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the STACK_DIE_CTRL register offsets.
+//
+//*****************************************************************************
+#define STACK_DIE_CTRL_O_STK_UP_RESET \
+ 0x00000000 // Can be written only by Base
+ // Processor. Writing to this
+ // register will reset the stack
+ // processor reset will be
+ // de-asserted upon clearing this
+ // register.
+
+#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \
+ 0x00000004 // This register defines who among
+ // base processor and stack
+ // processor have highest priority
+ // for Sram Access. Can be written
+ // only by Base Processor.
+
+#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \
+ 0x00000008 // In Spinlock mode this Register
+ // defines who among base processor
+ // and stack processor have access
+ // to Sram Bank2 right now. In
+ // Handshake mode this Register
+ // defines who among base processor
+ // and stack processor have access
+ // to Sram Bank2 and Bank3 right
+ // now. Its Clear only register and
+ // is set by hardware. Lower bit can
+ // be cleared only by Base Processor
+ // and Upper bit Cleared only by the
+ // Stack processor.
+
+#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \
+ 0x0000000C // In Spinlock mode whenever Base
+ // processor wants the access to
+ // Sram Bank2 it should request for
+ // it by writing into this register.
+ // It'll get interrupt whenever it
+ // is granted. In Handshake mode
+ // this bit will be set by Stack
+ // processor. Its a set only bit and
+ // is cleared by HW when the request
+ // is granted.
+
+#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \
+ 0x00000010 // In Spinlock mode Whenever Stack
+ // processor wants the access to
+ // Sram Bank2 it should request for
+ // it by writing into this register.
+ // It'll get interrupt whenever it
+ // is granted. In Handshake mode
+ // this bit will be set by the Base
+ // processor. Its a set only bit and
+ // is cleared by HW when the request
+ // is granted.
+
+#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \
+ 0x00000014 // Register defines who among base
+ // processor and stack processor
+ // have access to Sram Bank3 right
+ // now. Its Clear only register and
+ // is set by hardware. Lower bit can
+ // be cleared only by Base Processor
+ // and Upper bit Cleared only by the
+ // Stack processor.
+
+#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \
+ 0x00000018 // In Spinlock mode whenever Base
+ // processor wants the access to
+ // Sram Bank3 it should request for
+ // it by writing into this register.
+ // It'll get interrupt whenever it
+ // is granted. In Handshake mode
+ // this bit will be set by Stack
+ // processor. Its a set only bit and
+ // is cleared by HW when the request
+ // is granted.
+
+#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \
+ 0x0000001C // In Spinlock mode Whenever Stack
+ // processor wants the access to
+ // Sram Bank3 it should request for
+ // it by writing into this register.
+ // It'll get interrupt whenever it
+ // is granted. In Handshake mode
+ // this bit will be set by the Base
+ // processor. Its a set only bit and
+ // is cleared by HW when the request
+ // is granted.
+
+#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \
+ 0x00000020 // Read State Machine timing
+ // configuration register. Generally
+ // Bit 4 and 3 will be identical.
+ // For stacked die always 43 are 0
+ // and 6:5 == 1 for 120Mhz.
+
+#define STACK_DIE_CTRL_O_RDSM_CFG_EE \
+ 0x00000024 // Read State Machine timing
+ // configuration register. Generally
+ // Bit 4 and 3 will be identical.
+ // For stacked die always 43 are 0
+ // and 6:5 == 1 for 120Mhz.
+
+#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \
+ 0x00000028 // Reading this register Base
+ // procesor will able to know the
+ // reason for the interrupt. This is
+ // clear only register - set by HW
+ // upon an interrupt to Base
+ // processor and can be cleared only
+ // by BASE processor.
+
+#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \
+ 0x0000002C // Reading this register Stack
+ // procesor will able to know the
+ // reason for the interrupt. This is
+ // clear only register - set by HW
+ // upon an interrupt to Stack
+ // processor and can be cleared only
+ // by Stack processor.
+
+#define STACK_DIE_CTRL_O_STK_CLK_EN \
+ 0x00000030 // Can be written only by base
+ // processor. Controls the enable
+ // pin of the cgcs for the clocks
+ // going to CM3 dft ctrl block and
+ // Sram.
+
+#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \
+ 0x00000034 // Can be written only by the base
+ // processor. Decides the ram
+ // sharing mode :: handshake or
+ // Spinlock mode.
+
+#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \
+ 0x00000038 // Stores the last bus fault
+ // address.
+
+#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \
+ 0x0000003C // write only registers on read
+ // returns 0.W Write 1 to clear the
+ // bust fault to store the new bus
+ // fault address
+
+#define STACK_DIE_CTRL_O_RESET_CAUSE \
+ 0x00000040 // Reset cause value captured from
+ // the ICR_CLKRST block.
+
+#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \
+ 0x00000044 // Watchdog timer event value
+ // captured from the ICR_CLKRST
+ // block
+
+#define STACK_DIE_CTRL_O_DMA_REQ \
+ 0x00000048 // To send Dma Request to bottom
+ // die.
+
+#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \
+ 0x0000004C // Address offset within SRAM to
+ // which CM3 should jump after
+ // reset.
+
+#define STACK_DIE_CTRL_O_SW_REG1 \
+ 0x00000050 // These are sw registers for
+ // topdie processor and bottom die
+ // processor to communicate. Both
+ // can set and read these registers.
+ // In case of write clash bottom
+ // die's processor wins and top die
+ // processor access is ignored.
+
+#define STACK_DIE_CTRL_O_SW_REG2 \
+ 0x00000054 // These are sw registers for
+ // topdie processor and bottom die
+ // processor to communicate. Both
+ // can set and read these registers.
+ // In case of write clash bottom
+ // die's processor wins and top die
+ // processor access is ignored.
+
+#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \
+ 0x00000058 // By posting the request Flash can
+ // be put into low-power mode
+ // (Sleep) without powering down the
+ // Flash. Earlier (in Garnet) this
+ // was fully h/w controlled and the
+ // control for this was coming from
+ // SysCtl while entering into Cortex
+ // Deep-sleep mode. But for our
+ // device the D2D i/f doesnt support
+ // this. The Firmware has to program
+ // the register in the top-die for
+ // entering into this mode and wait
+ // for an interrupt.
+
+#define STACK_DIE_CTRL_O_MISC_CTL \
+ 0x0000005C // Miscellanious control register.
+
+#define STACK_DIE_CTRL_O_SW_DFT_CTL \
+ 0x000000FC // DFT control and status bits
+
+#define STACK_DIE_CTRL_O_PADN_CTL_0 \
+ 0x00000100 // Mainly for For controlling the
+ // pads OEN pins. There are total 60
+ // pads and hence 60 control registe
+ // i.e n value varies from 0 to 59.
+ // Here is the mapping for the
+ // pad_ctl register number and the
+ // functionality : 0 D2DPAD_DMAREQ1
+ // 1 D2DPAD_DMAREQ0 2
+ // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4
+ // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6
+ // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8
+ // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS
+ // 10 D2DPAD_JTAG_TDI 11-27
+ // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE
+ // -1:0] 28-56 D2DPAD_TOSTACK
+ // [D2D_TOSTACK_SIZE -1:0] 57-59
+ // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE
+ // -1:0] 0:00
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_STK_UP_RESET register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \
+ 0x00000001 // 1 :Assert Reset 0 : Deassert the
+ // Reset
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \
+ 0x00000003 // 00 : Equal Priority 01 : Stack
+ // Processor have priority 10 : Base
+ // Processor have priority 11 :
+ // Unused
+
+#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \
+ 0x00000002 // Stack Processor should clear it
+ // when it is done with the sram
+ // bank usage. Set by HW It is set
+ // when Stack Processor is granted
+ // the access to this bank
+
+#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \
+ 0x00000001 // Base Processor should clear it
+ // when it is done wth the sram
+ // usage. Set by HW It is set when
+ // Base Processor is granted the
+ // access to this bank
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \
+ 0x00000001 // Base Processor will set when
+ // Sram access is needed in Spin
+ // Lock mode. In Handshake mode
+ // Stack Processor will set to
+ // inform Base Processor that it is
+ // done with the processing of data
+ // in SRAM and is now ready to use
+ // by the base processor.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \
+ 0x00000001 // Stack Processor will set when
+ // Sram access is needed in Spin
+ // Lock mode. In Handshake mode Base
+ // Processor will set to inform
+ // Stack Processor to start
+ // processing the data in the Ram.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \
+ 0x00000002 // Stack Processor should clear it
+ // when it is done with the sram
+ // bank usage. Set by HW It is set
+ // when Stack Processor is granted
+ // the access to this bank.
+
+#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \
+ 0x00000001 // Base Processor should clear it
+ // when it is done wth the sram
+ // usage. Set by HW it is set when
+ // Base Processor is granted the
+ // access to this bank.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \
+ 0x00000001 // Base Processor will set when
+ // Sram access is needed in Spin
+ // Lock mode. Not used in handshake
+ // mode.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \
+ 0x00000001 // Stack Processor will set when
+ // Sram access is needed in Spin
+ // Lock mode.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_RDSM_CFG_CPU register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \
+ 0x000000C0 // Bank Clock Hi Time 00 : HCLK
+ // pulse 01 : 1 cycle of HCLK 10 :
+ // 1.5 cycles of HCLK 11 : 2 cycles
+ // of HCLK
+
+#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6
+#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \
+ 0x00000020 // FLCLK 0 : indicates flash clock
+ // rise aligns on HCLK rise 1 :
+ // indicates flash clock rise aligns
+ // on HCLK fall
+
+#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \
+ 0x00000010 // 0 : Always register flash rdata
+ // before sending to CPU 1 : Drive
+ // Flash rdata directly out on MISS
+ // (Both ICODE / DCODE)
+
+#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \
+ 0x0000000F // Number of wait states inserted
+
+#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_RDSM_CFG_EE register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \
+ 0x000000C0 // Bank Clock Hi Time 00 : HCLK
+ // pulse 01 : 1 cycle of HCLK 10 :
+ // 1.5 cycles of HCLK 11 : 2 cycles
+ // of HCLK
+
+#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6
+#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \
+ 0x00000020 // FLCLK 0 : indicates flash clock
+ // rise aligns on HCLK rise 1 :
+ // indicates flash clock rise aligns
+ // on HCLK fall
+
+#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \
+ 0x00000010 // 0 : Always register flash rdata
+ // before sending to CPU 1 : Drive
+ // Flash rdata directly out on MISS
+ // (Both ICODE / DCODE)
+
+#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \
+ 0x0000000F // Number of wait states inserted
+
+#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \
+ 0x00000010 // Set when Relinquish Interrupt
+ // sent to Base processor for Bank3.
+
+#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \
+ 0x00000008 // Set when Relinquish Interrupt
+ // sent to Base processor for Bank2.
+
+#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \
+ 0x00000004 // Set when Bank3 is granted to
+ // Base processor.
+
+#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \
+ 0x00000002 // Set when Bank2 is granted to
+ // BAse processor.
+
+#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \
+ 0x00000001 // Set when there Base processor do
+ // an Invalid access to Sram. Ex :
+ // Accessing the bank which is not
+ // granted for BAse processor.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \
+ 0x00000008 // Set when Relinquish Interrupt
+ // sent to Stack processor for
+ // Bank3.
+
+#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \
+ 0x00000004 // Set when Relinquish Interrupt
+ // sent to Stack processor for
+ // Bank2.
+
+#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \
+ 0x00000002 // Set when Bank3 is granted to
+ // Stack processor.
+
+#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \
+ 0x00000001 // Set when Bank2 is granted to
+ // Stack processor.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_STK_CLK_EN register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \
+ 0x00000004 // Enable the clock going to sram.
+
+#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \
+ 0x00000002 // Enable the clock going to dft
+ // control block
+
+#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \
+ 0x00000001 // Enable the clock going to Cm3
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \
+ 0x00000001 // 0 : Handshake Mode 1 : Spinlock
+ // mode.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \
+ 0xFFFFFFFF // Fault Address
+
+#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_BUS_FAULT_CLR register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \
+ 0x00000001 // When set it'll clear the bust
+ // fault address register to store
+ // the new bus fault address
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_RESET_CAUSE register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \
+ 0xFFFFFFFF
+
+#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \
+ 0xFFFFFFFF
+
+#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_DMA_REQ register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \
+ 0x00000002 // Generate DMAREQ1 on setting this
+ // bit.
+
+#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \
+ 0x00000001 // Generate DMAREQ0 on setting this
+ // bit.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \
+ 0xFFFFFFFF
+
+#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_SW_REG1 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \
+ 0xFFFFFFFF
+
+#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_SW_REG2 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \
+ 0xFFFFFFFF
+
+#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \
+ 0x00000002 // captures the status of of
+ // fmc_lpm_ack
+
+#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \
+ 0x00000001 // When set assert
+ // iflpe2fmc_lpm_req to FMC.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_MISC_CTL register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \
+ 0x00000080 // 1 : will reset the async wdog
+ // timer runing on piosc clock
+
+#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \
+ 0x00000020 // Setting this Will send to
+ // interttupt to CM3
+
+#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \
+ 0x00000010 // Setting this Will send to
+ // interttupt to CM3
+
+#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \
+ 0x00000008 // Setting this Will send to
+ // interttupt to CM3
+
+#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \
+ 0x00000004 // While testing Flash Setting this
+ // bit will Control the
+ // CE/STR/AIN/CLKIN going to flash
+ // banks 12 and 3. 0 : Control
+ // signals coming from FMC for Bank
+ // 3 goes to Bank3 1 : Control
+ // signals coming from FMC for Bank
+ // 0 goes to Bank2
+
+#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \
+ 0x00000002 // While testing Flash Setting this
+ // bit will Control the
+ // CE/STR/AIN/CLKIN going to flash
+ // banks 12 and 3. 0 : Control
+ // signals coming from FMC for Bank
+ // 2 goes to Bank2 1 : Control
+ // signals coming from FMC for Bank
+ // 0 goes to Bank2
+
+#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \
+ 0x00000001 // While testing Flash Setting this
+ // bit will Control the
+ // CE/STR/AIN/CLKIN going to flash
+ // banks 12 and 3. 0 : Control
+ // signals coming from FMC for Bank
+ // 1 goes to Bank1 1 : Control
+ // signals coming from FMC for Bank
+ // 0 goes to Bank1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_SW_DFT_CTL register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \
+ 0x20000000 // when set to '1' all flash
+ // control signals switch over to
+ // CM3 control when '0' it is under
+ // the D2D interface control
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \
+ 0x10000000 // 1 indicates in SWIF mode the
+ // control signals to flash are from
+ // FMC CPU read controls the clock
+ // and address. that is one can give
+ // address via FMC and read through
+ // IDMEM.
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \
+ 0x00800000 // 'CPU Done' bit for PBIST. Write
+ // '1' to indicate test done.
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \
+ 0x00400000 // 'CPU Fail' bit for PBIST. Write
+ // '1' to indicate test failed.
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \
+ 0x00001000 // when set to '1' flash bank 4
+ // (EEPROM) is owned by the CM3for
+ // reads over DCODE bus. When '0'
+ // access control given to D2D
+ // interface.
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \
+ 0x00000800 // when set to '1' flash bank 3 is
+ // owned by the CM3for reads over
+ // DCODE bus. When '0' access
+ // control given to D2D interface.
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \
+ 0x00000400 // when set to '1' flash bank 2 is
+ // owned by the CM3for reads over
+ // DCODE bus. When '0' access
+ // control given to D2D interface.
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \
+ 0x00000200 // when set to '1' flash bank 1 is
+ // owned by the CM3for reads over
+ // DCODE bus. When '0' access
+ // control given to D2D interface.
+
+#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \
+ 0x00000100 // when set to '1' flash bank 0 is
+ // owned by the CM3 for reads over
+ // DCODE bus. When '0' access
+ // control given to D2D interface.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// STACK_DIE_CTRL_O_PADN_CTL_0 register.
+//
+//******************************************************************************
+#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \
+ 0x00000008 // This bit is valid for only the
+ // spare pads ie for n=57 to 59.
+ // value to drive at the output of
+ // the pad
+
+#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \
+ 0x00000004 // This bit is valid for only the
+ // spare pads ie for n=57 to 59.
+ // captures the 'Y' pin of the pad
+ // which is the data being driven
+ // into the die
+
+#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \
+ 0x00000002 // OEN2X control when '1' enables
+ // the output with 1x. Total drive
+ // strength is decided bu oen1x
+ // setting + oen2x setting.
+
+#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \
+ 0x00000001 // OEN1X control when '1' enables
+ // the output with 1x . Total drive
+ // strength is decided bu oen1x
+ // setting + oen2x setting.
+
+
+
+
+#endif // __HW_STACK_DIE_CTRL_H__
diff --git a/cc3200/hal/inc/hw_timer.h b/cc3200/hal/inc/hw_timer.h
new file mode 100644
index 0000000000..b6844ec675
--- /dev/null
+++ b/cc3200/hal/inc/hw_timer.h
@@ -0,0 +1,778 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+//*****************************************************************************
+
+//##### INTERNAL BEGIN #####
+//
+// This is an auto-generated file. Do not edit by hand.
+// Created by version 6779 of DriverLib.
+//
+//##### INTERNAL END #####
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG 0x00000000 // GPTM Configuration
+#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
+#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
+#define TIMER_O_CTL 0x0000000C // GPTM Control
+//##### GARNET BEGIN #####
+#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
+//##### GARNET END #####
+#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
+#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
+#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
+#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
+#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
+#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
+#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
+#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
+#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
+#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
+#define TIMER_O_TAR 0x00000048 // GPTM Timer A
+#define TIMER_O_TBR 0x0000004C // GPTM Timer B
+#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
+#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
+#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
+#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
+#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
+#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
+#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
+#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event
+#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
+
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
+ // Operation
+#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
+ // Update
+#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
+ // Enable
+#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
+//##### GARNET END #####
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
+ // Operation
+#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
+ // Update
+#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
+ // Enable
+#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
+//##### GARNET END #####
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+//##### GARNET BEGIN #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11
+#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of
+ // GPTM11 is triggered
+#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of
+ // GPTM11 is triggered
+#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A
+ // and Timer B of GPTM11 is
+ // triggered
+#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10
+#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of
+ // GPTM10 is triggered
+#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of
+ // GPTM10 is triggered
+#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A
+ // and Timer B of GPTM10 is
+ // triggered
+#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9
+#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of
+ // GPTM9 is triggered
+#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of
+ // GPTM9 is triggered
+#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A
+ // and Timer B of GPTM9 is
+ // triggered
+#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8
+#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of
+ // GPTM8 is triggered
+#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of
+ // GPTM8 is triggered
+#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A
+ // and Timer B of GPTM8 is
+ // triggered
+#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7
+#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of
+ // GPTM7 is triggered
+#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of
+ // GPTM7 is triggered
+#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A
+ // and Timer B of GPTM7 is
+ // triggered
+#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6
+#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of
+ // GPTM6 is triggered
+#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of
+ // GPTM6 is triggered
+#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A
+ // and Timer B of GPTM6 is
+ // triggered
+#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5
+#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of
+ // GPTM5 is triggered
+#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of
+ // GPTM5 is triggered
+#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A
+ // and Timer B of GPTM5 is
+ // triggered
+#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4
+#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of
+ // GPTM4 is triggered
+#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of
+ // GPTM4 is triggered
+#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A
+ // and Timer B of GPTM4 is
+ // triggered
+#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3
+#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of
+ // GPTM3 is triggered
+#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of
+ // GPTM3 is triggered
+#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A
+ // and Timer B of GPTM3 is
+ // triggered
+#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2
+#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of
+ // GPTM2 is triggered
+#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of
+ // GPTM2 is triggered
+#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A
+ // and Timer B of GPTM2 is
+ // triggered
+#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1
+#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of
+ // GPTM1 is triggered
+#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of
+ // GPTM1 is triggered
+#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A
+ // and Timer B of GPTM1 is
+ // triggered
+#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0
+#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of
+ // GPTM0 is triggered
+#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of
+ // GPTM0 is triggered
+#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A
+ // and Timer B of GPTM0 is
+ // triggered
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Interrupt Mask
+//##### GARNET END #####
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
+ // Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt
+ // Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt
+ // Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt
+ // Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Raw Interrupt Status
+//##### GARNET END #####
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
+ // Interrupt
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
+ // Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw
+ // Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
+ // Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw
+ // Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw
+ // Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Masked Interrupt Status
+//##### GARNET END #####
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
+ // Interrupt
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
+ // Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked
+ // Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked
+ // Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked
+ // Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Interrupt Clear
+//##### GARNET END #####
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
+ // Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt
+ // Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt
+ // Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt
+ // Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
+ // Register
+//##### GARNET END #####
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
+ // Register High
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
+ // Register Low
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+//##### GARNET BEGIN #####
+#define TIMER_TAILR_S 0
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
+ // Register
+//##### GARNET END #####
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_TBILRL_S 0
+//##### GARNET BEGIN #####
+#define TIMER_TBILR_S 0
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
+//##### GARNET END #####
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+//##### GARNET BEGIN #####
+#define TIMER_TAMATCHR_TAMR_S 0
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
+//##### GARNET END #####
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
+//##### GARNET BEGIN #####
+#define TIMER_TBMATCHR_TBMR_S 0
+//##### GARNET END #####
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
+//##### GARNET END #####
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+//##### GARNET BEGIN #####
+#define TIMER_TAPR_TAPSRH_S 8
+//##### GARNET END #####
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
+//##### GARNET END #####
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+//##### GARNET BEGIN #####
+#define TIMER_TBPR_TBPSRH_S 8
+//##### GARNET END #####
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
+ // Byte
+//##### GARNET END #####
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+//##### GARNET BEGIN #####
+#define TIMER_TAPMR_TAPSMRH_S 8
+//##### GARNET END #####
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
+ // Byte
+//##### GARNET END #####
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+//##### GARNET BEGIN #####
+#define TIMER_TBPMR_TBPSMRH_S 8
+//##### GARNET END #####
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
+//##### GARNET END #####
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+//##### GARNET BEGIN #####
+#define TIMER_TAR_S 0
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
+//##### GARNET END #####
+#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
+#define TIMER_TBR_TBRL_S 0
+//##### GARNET BEGIN #####
+#define TIMER_TBR_S 0
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
+//##### GARNET END #####
+#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
+#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
+#define TIMER_TAV_TAVH_S 16
+#define TIMER_TAV_TAVL_S 0
+//##### GARNET BEGIN #####
+#define TIMER_TAV_S 0
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+//##### GARNET BEGIN #####
+#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
+//##### GARNET END #####
+#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
+#define TIMER_TBV_TBVL_S 0
+//##### GARNET BEGIN #####
+#define TIMER_TBV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start
+#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers
+#define TIMER_PP_SIZE_M 0x0000000F // Count Size
+#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are
+ // 16 bits each with an 8-bit
+ // prescale counter
+#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are
+ // 32 bits each with an 16-bit
+ // prescale counter
+//##### GARNET END #####
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CFG
+// register.
+//
+//*****************************************************************************
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CTL
+// register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_RIS
+// register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the timer
+// registers.
+//
+//*****************************************************************************
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
+#define TIMER_RV_CTL 0x00000000 // Control register RV
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
+
+#endif
+
+#endif // __HW_TIMER_H__
diff --git a/cc3200/hal/inc/hw_types.h b/cc3200/hal/inc/hw_types.h
new file mode 100644
index 0000000000..d7a6ab4fed
--- /dev/null
+++ b/cc3200/hal/inc/hw_types.h
@@ -0,0 +1,76 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Define a boolean type, and values for true and false.
+//
+//*****************************************************************************
+typedef unsigned char tBoolean;
+
+#ifndef true
+#define true 1
+#endif
+
+#ifndef false
+#define false 0
+#endif
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) \
+ (*((volatile unsigned long *)(x)))
+#define HWREGH(x) \
+ (*((volatile unsigned short *)(x)))
+#define HWREGB(x) \
+ (*((volatile unsigned char *)(x)))
+#define HWREGBITW(x, b) \
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b) \
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b) \
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+
+#endif // __HW_TYPES_H__
diff --git a/cc3200/hal/inc/hw_uart.h b/cc3200/hal/inc/hw_uart.h
new file mode 100644
index 0000000000..ae50ac381f
--- /dev/null
+++ b/cc3200/hal/inc/hw_uart.h
@@ -0,0 +1,417 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR 0x00000000
+#define UART_O_RSR 0x00000004
+#define UART_O_ECR 0x00000004
+#define UART_O_FR 0x00000018
+#define UART_O_ILPR 0x00000020
+#define UART_O_IBRD 0x00000024
+#define UART_O_FBRD 0x00000028
+#define UART_O_LCRH 0x0000002C
+#define UART_O_CTL 0x00000030
+#define UART_O_IFLS 0x00000034
+#define UART_O_IM 0x00000038
+#define UART_O_RIS 0x0000003C
+#define UART_O_MIS 0x00000040
+#define UART_O_ICR 0x00000044
+#define UART_O_DMACTL 0x00000048
+#define UART_O_LCTL 0x00000090
+#define UART_O_LSS 0x00000094
+#define UART_O_LTIM 0x00000098
+#define UART_O_9BITADDR 0x000000A4
+#define UART_O_9BITAMASK 0x000000A8
+#define UART_O_PP 0x00000FC0
+#define UART_O_CC 0x00000FC8
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//******************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//******************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//******************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//******************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect
+#define UART_FR_DSR 0x00000002 // Data Set Ready
+#define UART_FR_CTS 0x00000001 // Clear To Send
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//******************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//******************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//******************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//******************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 :
+ // UART_LCRH_WLEN_5 : 5 bits
+ // (default) 0x00000020 :
+ // UART_LCRH_WLEN_6 : 6 bits
+ // 0x00000040 : UART_LCRH_WLEN_7 : 7
+ // bits 0x00000060 :
+ // UART_LCRH_WLEN_8 : 8 bits
+#define UART_LCRH_WLEN_S 5
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//******************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
+#define UART_CTL_RI 0x00002000 // Ring Indicator
+#define UART_CTL_DCD 0x00001000 // Data Carrier Detect
+#define UART_CTL_RTS 0x00000800 // Request to Send
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable
+#define UART_CTL_EOT 0x00000010 // End of Transmission
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//******************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX_S 3
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//******************************************************************************
+#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask
+#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask
+#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
+#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
+ // Mask
+#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
+#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt
+ // Mask
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//******************************************************************************
+#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt
+ // Status
+#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status
+#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
+ // Status
+#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
+ // Status
+#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
+ // Interrupt Status
+#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw
+ // Interrupt Status
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
+ // Raw Interrupt Status
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//******************************************************************************
+#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt
+ // Status
+#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt
+ // Status
+#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
+ // Status
+#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
+ // Status
+#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
+ // Interrupt Status
+#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
+ // Status
+#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked
+ // Interrupt Status
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
+ // Masked Interrupt Status
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//******************************************************************************
+#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear
+#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear
+#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
+ // Clear
+#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
+#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt
+ // Clear
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Clear
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//******************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCTL register.
+//
+//******************************************************************************
+#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 :
+ // UART_LCTL_BLEN_13T : Sync break
+ // length is 13T bits (default)
+ // 0x00000010 : UART_LCTL_BLEN_14T :
+ // Sync break length is 14T bits
+ // 0x00000020 : UART_LCTL_BLEN_15T :
+ // Sync break length is 15T bits
+ // 0x00000030 : UART_LCTL_BLEN_16T :
+ // Sync break length is 16T bits
+#define UART_LCTL_BLEN_S 4
+#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LSS register.
+//
+//******************************************************************************
+#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
+#define UART_LSS_TSS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LTIM register.
+//
+//******************************************************************************
+#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
+#define UART_LTIM_TIMER_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// UART_O_9BITADDR register.
+//
+//******************************************************************************
+#define UART_9BITADDR_9BITEN \
+ 0x00008000 // Enable 9-Bit Mode
+
+#define UART_9BITADDR_ADDR_M \
+ 0x000000FF // Self Address for 9-Bit Mode
+
+#define UART_9BITADDR_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// UART_O_9BITAMASK register.
+//
+//******************************************************************************
+#define UART_9BITAMASK_RANGE_M \
+ 0x0000FF00 // Self Address Range for 9-Bit
+ // Mode
+
+#define UART_9BITAMASK_RANGE_S 8
+#define UART_9BITAMASK_MASK_M \
+ 0x000000FF // Self Address Mask for 9-Bit Mode
+
+#define UART_9BITAMASK_MASK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//******************************************************************************
+#define UART_PP_MSE 0x00000008 // Modem Support Extended
+#define UART_PP_MS 0x00000004 // Modem Support
+#define UART_PP_NB 0x00000002 // 9-Bit Support
+#define UART_PP_SC 0x00000001 // Smart Card Support
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//******************************************************************************
+#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
+ // 0x00000005 : UART_CC_CS_PIOSC :
+ // PIOSC 0x00000000 :
+ // UART_CC_CS_SYSCLK : The system
+ // clock (default)
+#define UART_CC_CS_S 0
+
+
+
+#endif // __HW_UART_H__
diff --git a/cc3200/hal/inc/hw_udma.h b/cc3200/hal/inc/hw_udma.h
new file mode 100644
index 0000000000..9a495baea8
--- /dev/null
+++ b/cc3200/hal/inc/hw_udma.h
@@ -0,0 +1,336 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UDMA register offsets.
+//
+//*****************************************************************************
+#define UDMA_O_STAT 0x00000000
+#define UDMA_O_CFG 0x00000004
+#define UDMA_O_CTLBASE 0x00000008
+#define UDMA_O_ALTBASE 0x0000000C
+#define UDMA_O_WAITSTAT 0x00000010
+#define UDMA_O_SWREQ 0x00000014
+#define UDMA_O_USEBURSTSET 0x00000018
+#define UDMA_O_USEBURSTCLR 0x0000001C
+#define UDMA_O_REQMASKSET 0x00000020
+#define UDMA_O_REQMASKCLR 0x00000024
+#define UDMA_O_ENASET 0x00000028
+#define UDMA_O_ENACLR 0x0000002C
+#define UDMA_O_ALTSET 0x00000030
+#define UDMA_O_ALTCLR 0x00000034
+#define UDMA_O_PRIOSET 0x00000038
+#define UDMA_O_PRIOCLR 0x0000003C
+#define UDMA_O_ERRCLR 0x0000004C
+#define UDMA_O_CHASGN 0x00000500
+#define UDMA_O_CHIS 0x00000504
+#define UDMA_O_CHMAP0 0x00000510
+#define UDMA_O_CHMAP1 0x00000514
+#define UDMA_O_CHMAP2 0x00000518
+#define UDMA_O_CHMAP3 0x0000051C
+#define UDMA_O_PV 0x00000FB0
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_STAT register.
+//
+//******************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
+#define UDMA_STAT_DMACHANS_S 16
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
+ // 0x00000090 : UDMA_STAT_STATE_DONE
+ // : Done 0x00000000 :
+ // UDMA_STAT_STATE_IDLE : Idle
+ // 0x00000010 :
+ // UDMA_STAT_STATE_RD_CTRL : Reading
+ // channel controller data
+ // 0x00000030 :
+ // UDMA_STAT_STATE_RD_DSTENDP :
+ // Reading destination end pointer
+ // 0x00000040 :
+ // UDMA_STAT_STATE_RD_SRCDAT :
+ // Reading source data 0x00000020 :
+ // UDMA_STAT_STATE_RD_SRCENDP :
+ // Reading source end pointer
+ // 0x00000080 :
+ // UDMA_STAT_STATE_STALL : Stalled
+ // 0x000000A0 :
+ // UDMA_STAT_STATE_UNDEF : Undefined
+ // 0x00000060 : UDMA_STAT_STATE_WAIT
+ // : Waiting for uDMA request to
+ // clear 0x00000070 :
+ // UDMA_STAT_STATE_WR_CTRL : Writing
+ // channel controller data
+ // 0x00000050 :
+ // UDMA_STAT_STATE_WR_DSTDAT :
+ // Writing destination data
+#define UDMA_STAT_STATE_S 4
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CFG register.
+//
+//******************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CTLBASE register.
+//
+//******************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S 10
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_ALTBASE register.
+//
+//******************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer
+#define UDMA_ALTBASE_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_WAITSTAT register.
+//
+//******************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M \
+ 0xFFFFFFFF // Channel [n] Wait Status
+
+#define UDMA_WAITSTAT_WAITREQ_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SWREQ register.
+//
+//******************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
+#define UDMA_SWREQ_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// UDMA_O_USEBURSTSET register.
+//
+//******************************************************************************
+#define UDMA_USEBURSTSET_SET_M \
+ 0xFFFFFFFF // Channel [n] Useburst Set
+
+#define UDMA_USEBURSTSET_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// UDMA_O_USEBURSTCLR register.
+//
+//******************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M \
+ 0xFFFFFFFF // Channel [n] Useburst Clear
+
+#define UDMA_USEBURSTCLR_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_REQMASKSET register.
+//
+//******************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
+#define UDMA_REQMASKSET_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register.
+//
+//******************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
+#define UDMA_REQMASKCLR_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_ENASET register.
+//
+//******************************************************************************
+#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
+#define UDMA_ENASET_CHENSET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_ENACLR register.
+//
+//******************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
+#define UDMA_ENACLR_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_ALTSET register.
+//
+//******************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
+#define UDMA_ALTSET_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_ALTCLR register.
+//
+//******************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
+#define UDMA_ALTCLR_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_PRIOSET register.
+//
+//******************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
+#define UDMA_PRIOSET_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_PRIOCLR register.
+//
+//******************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
+#define UDMA_PRIOCLR_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_ERRCLR register.
+//
+//******************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHASGN register.
+//
+//******************************************************************************
+#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
+#define UDMA_CHASGN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHIS register.
+//
+//******************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
+#define UDMA_CHIS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHMAP0 register.
+//
+//******************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH7SEL_S 28
+#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH6SEL_S 24
+#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH5SEL_S 20
+#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH4SEL_S 16
+#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH3SEL_S 12
+#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH2SEL_S 8
+#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH1SEL_S 4
+#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH0SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHMAP1 register.
+//
+//******************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH15SEL_S 28
+#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH14SEL_S 24
+#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH13SEL_S 20
+#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH12SEL_S 16
+#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH11SEL_S 12
+#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH10SEL_S 8
+#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH9SEL_S 4
+#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH8SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHMAP2 register.
+//
+//******************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH23SEL_S 28
+#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH22SEL_S 24
+#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH21SEL_S 20
+#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH20SEL_S 16
+#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH19SEL_S 12
+#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH18SEL_S 8
+#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH17SEL_S 4
+#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH16SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHMAP3 register.
+//
+//******************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH31SEL_S 28
+#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH30SEL_S 24
+#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH29SEL_S 20
+#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH28SEL_S 16
+#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH27SEL_S 12
+#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH26SEL_S 8
+#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH25SEL_S 4
+#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH24SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_PV register.
+//
+//******************************************************************************
+#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision
+#define UDMA_PV_MAJOR_S 8
+#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision
+#define UDMA_PV_MINOR_S 0
+
+
+
+#endif // __HW_UDMA_H__
diff --git a/cc3200/hal/inc/hw_wdt.h b/cc3200/hal/inc/hw_wdt.h
new file mode 100644
index 0000000000..00b14acbe3
--- /dev/null
+++ b/cc3200/hal/inc/hw_wdt.h
@@ -0,0 +1,131 @@
+//*****************************************************************************
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __HW_WDT_H__
+#define __HW_WDT_H__
+
+//*****************************************************************************
+//
+// The following are defines for the WDT register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD 0x00000000
+#define WDT_O_VALUE 0x00000004
+#define WDT_O_CTL 0x00000008
+#define WDT_O_ICR 0x0000000C
+#define WDT_O_RIS 0x00000010
+#define WDT_O_MIS 0x00000014
+#define WDT_O_TEST 0x00000418
+#define WDT_O_LOCK 0x00000C00
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//******************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//******************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//******************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete
+#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit
+ // is not used in cc3xx, WDOG shall
+ // always generate RESET to system
+ // irrespective of this bit setting.
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//******************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//******************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//******************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//******************************************************************************
+#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable
+#define WDT_TEST_STALL_EN_S 10
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+//******************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//******************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_S 0
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
+// WDT_MIS registers.
+//
+//*****************************************************************************
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
+
+
+
+
+
+#endif // __HW_WDT_H__
diff --git a/cc3200/hal/interrupt.c b/cc3200/hal/interrupt.c
new file mode 100644
index 0000000000..897ad966ae
--- /dev/null
+++ b/cc3200/hal/interrupt.c
@@ -0,0 +1,769 @@
+//*****************************************************************************
+//
+// interrupt.c
+//
+// Driver for the NVIC Interrupt Controller.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup interrupt_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "cpu.h"
+#include "debug.h"
+#include "interrupt.h"
+
+//*****************************************************************************
+//
+// This is a mapping between priority grouping encodings and the number of
+// preemption priority bits.
+//
+//*****************************************************************************
+static const unsigned long g_pulPriority[] =
+{
+ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
+ NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
+ NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number and the register that contains
+// the priority encoding for that interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulRegs[] =
+{
+ 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
+ NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
+ NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
+ NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
+ NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
+ NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
+ NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37,
+ NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43,
+ NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48
+
+};
+
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt enable for that
+// interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulEnRegs[] =
+{
+ NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt disable for that
+// interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulDisRegs[] =
+{
+ NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt pend for that interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulPendRegs[] =
+{
+ NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5
+};
+
+//*****************************************************************************
+//
+// This is a mapping between interrupt number (for the peripheral interrupts
+// only) and the register that contains the interrupt unpend for that
+// interrupt.
+//
+//*****************************************************************************
+static const unsigned long g_pulUnpendRegs[] =
+{
+ NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4,
+ NVIC_UNPEND5
+};
+
+
+//*****************************************************************************
+//
+//! \internal
+//! The default interrupt handler.
+//!
+//! This is the default interrupt handler for all interrupts. It simply loops
+//! forever so that the system state is preserved for observation by a
+//! debugger. Since interrupts should be disabled before unregistering the
+//! corresponding handler, this should never be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+static void
+IntDefaultHandler(void)
+{
+ //
+ // Go into an infinite loop.
+ //
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables the processor interrupt.
+//!
+//! Allows the processor to respond to interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include interrupt.h and call this function without
+//! having included hw_types.h. Now that the return is a
+//! tBoolean, a compiler error will occur in this case. The solution
+//! is to include hw_types.h before including interrupt.h.
+//!
+//! \return Returns \b true if interrupts were disabled when the function was
+//! called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterEnable(void)
+{
+ //
+ // Enable processor interrupts.
+ //
+ return(CPUcpsie());
+}
+
+//*****************************************************************************
+//
+//! Disables the processor interrupt.
+//!
+//! Prevents the processor from receiving interrupts. This does not affect the
+//! set of interrupts enabled in the interrupt controller; it just gates the
+//! single interrupt from the controller to the processor.
+//!
+//! \note Previously, this function had no return value. As such, it was
+//! possible to include interrupt.h and call this function without
+//! having included hw_types.h. Now that the return is a
+//! tBoolean, a compiler error will occur in this case. The solution
+//! is to include hw_types.h before including interrupt.h.
+//!
+//! \return Returns \b true if interrupts were already disabled when the
+//! function was called or \b false if they were initially enabled.
+//
+//*****************************************************************************
+tBoolean
+IntMasterDisable(void)
+{
+ //
+ // Disable processor interrupts.
+ //
+ return(CPUcpsid());
+}
+//*****************************************************************************
+//
+//! Sets the NVIC VTable base.
+//!
+//! \param ulVtableBase specifies the new base address of VTable
+//!
+//! This function is used to specify a new base address for the VTable.
+//! This function must be called before using IntRegister() for registering
+//! any interrupt handler.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntVTableBaseSet(unsigned long ulVtableBase)
+{
+ HWREG(NVIC_VTABLE) = ulVtableBase;
+}
+
+//*****************************************************************************
+//
+//! Registers a function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param pfnHandler is a pointer to the function to be called.
+//!
+//! This function is used to specify the handler function to be called when the
+//! given interrupt is asserted to the processor. When the interrupt occurs,
+//! if it is enabled (via IntEnable()), the handler function will be called in
+//! interrupt context. Since the handler function can preempt other code, care
+//! must be taken to protect memory or peripherals that are accessed by the
+//! handler and other non-handler code.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
+{
+ unsigned long *ulNvicTbl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
+ ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the function to be called when an interrupt occurs.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function is used to indicate that no handler should be called when the
+//! given interrupt is asserted to the processor. The interrupt source will be
+//! automatically disabled (via IntDisable()) if necessary.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntUnregister(unsigned long ulInterrupt)
+{
+ unsigned long *ulNvicTbl;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
+ ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler;
+}
+
+//*****************************************************************************
+//
+//! Sets the priority grouping of the interrupt controller.
+//!
+//! \param ulBits specifies the number of bits of preemptable priority.
+//!
+//! This function specifies the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification. The range of
+//! the grouping values are dependent upon the hardware implementation; on
+//! the CC3200 , three bits are available for hardware interrupt
+//! prioritization and therefore priority grouping values of three through
+//! seven have the same effect.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityGroupingSet(unsigned long ulBits)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBits < NUM_PRIORITY);
+
+ //
+ // Set the priority grouping.
+ //
+ HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
+}
+
+//*****************************************************************************
+//
+//! Gets the priority grouping of the interrupt controller.
+//!
+//! This function returns the split between preemptable priority levels and
+//! subpriority levels in the interrupt priority specification.
+//!
+//! \return The number of bits of preemptable priority.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityGroupingGet(void)
+{
+ unsigned long ulLoop, ulValue;
+
+ //
+ // Read the priority grouping.
+ //
+ ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
+
+ //
+ // Loop through the priority grouping values.
+ //
+ for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
+ {
+ //
+ // Stop looping if this value matches.
+ //
+ if(ulValue == g_pulPriority[ulLoop])
+ {
+ break;
+ }
+ }
+
+ //
+ // Return the number of priority bits.
+ //
+ return(ulLoop);
+}
+
+//*****************************************************************************
+//
+//! Sets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//! \param ucPriority specifies the priority of the interrupt.
+//!
+//! This function is used to set the priority of an interrupt. When multiple
+//! interrupts are asserted simultaneously, the ones with the highest priority
+//! are processed before the lower priority interrupts. Smaller numbers
+//! correspond to higher interrupt priorities; priority 0 is the highest
+//! interrupt priority.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3), so any prioritization must be performed in
+//! those bits. The remaining bits can be used to sub-prioritize the interrupt
+//! sources, and may be used by the hardware priority mechanism on a future
+//! part. This arrangement allows priorities to migrate to different NVIC
+//! implementations without changing the gross prioritization of the
+//! interrupts.
+//!
+//! The parameter \e ucPriority can be any one of the following
+//! -\b INT_PRIORITY_LVL_0
+//! -\b INT_PRIORITY_LVL_1
+//! -\b INT_PRIORITY_LVL_2
+//! -\b INT_PRIORITY_LVL_3
+//! -\b INT_PRIORITY_LVL_4
+//! -\b INT_PRIORITY_LVL_5
+//! -\b INT_PRIORITY_LVL_6
+//! -\b INT_PRIORITY_LVL_7
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Set the interrupt priority.
+ //
+ ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
+ ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
+ ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
+ HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the priority of an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt in question.
+//!
+//! This function gets the priority of an interrupt. See IntPrioritySet() for
+//! a definition of the priority value.
+//!
+//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
+//! specified.
+//
+//*****************************************************************************
+long
+IntPriorityGet(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
+
+ //
+ // Return the interrupt priority.
+ //
+ return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
+ 0xFF);
+}
+
+//*****************************************************************************
+//
+//! Enables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be enabled.
+//!
+//! The specified interrupt is enabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntEnable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to enable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Enable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Enable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Enable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Enable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt >= 16)
+ {
+ //
+ // Enable the general interrupt.
+ //
+ HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
+ 1 << ((ulInterrupt - 16) & 31);
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be disabled.
+//!
+//! The specified interrupt is disabled in the interrupt controller. Other
+//! enables for the interrupt (such as at the peripheral level) are unaffected
+//! by this function.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntDisable(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to disable.
+ //
+ if(ulInterrupt == FAULT_MPU)
+ {
+ //
+ // Disable the MemManage interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_BUS)
+ {
+ //
+ // Disable the bus fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_USAGE)
+ {
+ //
+ // Disable the usage fault interrupt.
+ //
+ HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Disable the System Tick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt >= 16)
+ {
+ //
+ // Disable the general interrupt.
+ //
+ HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
+ 1 << ((ulInterrupt - 16) & 31);
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+
+}
+
+//*****************************************************************************
+//
+//! Pends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be pended.
+//!
+//! The specified interrupt is pended in the interrupt controller. This will
+//! cause the interrupt controller to execute the corresponding interrupt
+//! handler at the next available time, based on the current interrupt state
+//! priorities. For example, if called by a higher priority interrupt handler,
+//! the specified interrupt handler will not be called until after the current
+//! interrupt handler has completed execution. The interrupt must have been
+//! enabled for it to be called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendSet(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to pend.
+ //
+ if(ulInterrupt == FAULT_NMI)
+ {
+ //
+ // Pend the NMI interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_PENDSV)
+ {
+ //
+ // Pend the PendSV interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Pend the SysTick interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+ else if(ulInterrupt >= 16)
+ {
+ //
+ // Pend the general interrupt.
+ //
+ HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
+ 1 << ((ulInterrupt - 16) & 31);
+ __asm(" dsb ");
+ __asm(" isb ");
+ }
+
+}
+
+//*****************************************************************************
+//
+//! Unpends an interrupt.
+//!
+//! \param ulInterrupt specifies the interrupt to be unpended.
+//!
+//! The specified interrupt is unpended in the interrupt controller. This will
+//! cause any previously generated interrupts that have not been handled yet
+//! (due to higher priority interrupts or the interrupt no having been enabled
+//! yet) to be discarded.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPendClear(unsigned long ulInterrupt)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulInterrupt < NUM_INTERRUPTS);
+
+ //
+ // Determine the interrupt to unpend.
+ //
+ if(ulInterrupt == FAULT_PENDSV)
+ {
+ //
+ // Unpend the PendSV interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
+ }
+ else if(ulInterrupt == FAULT_SYSTICK)
+ {
+ //
+ // Unpend the SysTick interrupt.
+ //
+ HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
+ }
+ else if(ulInterrupt >= 16)
+ {
+ //
+ // Unpend the general interrupt.
+ //
+ HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
+ 1 << ((ulInterrupt - 16) & 31);
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets the priority masking level
+//!
+//! \param ulPriorityMask is the priority level that will be masked.
+//!
+//! This function sets the interrupt priority masking level so that all
+//! interrupts at the specified or lesser priority level is masked. This
+//! can be used to globally disable a set of interrupts with priority below
+//! a predetermined threshold. A value of 0 disables priority
+//! masking.
+//!
+//! Smaller numbers correspond to higher interrupt priorities. So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+IntPriorityMaskSet(unsigned long ulPriorityMask)
+{
+ CPUbasepriSet(ulPriorityMask);
+}
+
+//*****************************************************************************
+//
+//! Gets the priority masking level
+//!
+//! This function gets the current setting of the interrupt priority masking
+//! level. The value returned is the priority level such that all interrupts
+//! of that and lesser priority are masked. A value of 0 means that priority
+//! masking is disabled.
+//!
+//! Smaller numbers correspond to higher interrupt priorities. So for example
+//! a priority level mask of 4 will allow interrupts of priority level 0-3,
+//! and interrupts with a numerical priority of 4 and greater will be blocked.
+//!
+//! The hardware priority mechanism will only look at the upper N bits of the
+//! priority level (where N is 3), so any
+//! prioritization must be performed in those bits.
+//!
+//! \return Returns the value of the interrupt priority level mask.
+//
+//*****************************************************************************
+unsigned long
+IntPriorityMaskGet(void)
+{
+ return(CPUbasepriGet());
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/interrupt.h b/cc3200/hal/interrupt.h
new file mode 100644
index 0000000000..941a60f5fe
--- /dev/null
+++ b/cc3200/hal/interrupt.h
@@ -0,0 +1,120 @@
+//*****************************************************************************
+//
+// interrupt.h
+//
+// Prototypes for the NVIC Interrupt Controller Driver.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// A union that describes the entries of the vector table. The union is needed
+// since the first entry is the stack pointer and the remainder are function
+// pointers.
+//
+//*****************************************************************************
+typedef union
+{
+ void (*pfnHandler)(void);
+ unsigned long ulPtr;
+}
+uVectorEntry;
+
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+// Interrupt priority levels
+//*****************************************************************************
+#define INT_PRIORITY_LVL_0 0x00
+#define INT_PRIORITY_LVL_1 0x20
+#define INT_PRIORITY_LVL_2 0x40
+#define INT_PRIORITY_LVL_3 0x60
+#define INT_PRIORITY_LVL_4 0x80
+#define INT_PRIORITY_LVL_5 0xA0
+#define INT_PRIORITY_LVL_6 0xC0
+#define INT_PRIORITY_LVL_7 0xE0
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean IntMasterEnable(void);
+extern tBoolean IntMasterDisable(void);
+extern void IntVTableBaseSet(unsigned long ulVtableBase);
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
+extern void IntUnregister(unsigned long ulInterrupt);
+extern void IntPriorityGroupingSet(unsigned long ulBits);
+extern unsigned long IntPriorityGroupingGet(void);
+extern void IntPrioritySet(unsigned long ulInterrupt,
+ unsigned char ucPriority);
+extern long IntPriorityGet(unsigned long ulInterrupt);
+extern void IntEnable(unsigned long ulInterrupt);
+extern void IntDisable(unsigned long ulInterrupt);
+extern void IntPendSet(unsigned long ulInterrupt);
+extern void IntPendClear(unsigned long ulInterrupt);
+extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
+extern unsigned long IntPriorityMaskGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
diff --git a/cc3200/hal/pin.c b/cc3200/hal/pin.c
new file mode 100644
index 0000000000..13bb80fed3
--- /dev/null
+++ b/cc3200/hal/pin.c
@@ -0,0 +1,667 @@
+//*****************************************************************************
+//
+// pin.c
+//
+// Mapping of peripherals to pins.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup pin_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_ocp_shared.h"
+#include "pin.h"
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define PAD_MODE_MASK 0x0000000F
+#define PAD_STRENGTH_MASK 0x000000E0
+#define PAD_TYPE_MASK 0x00000310
+#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \
+ OCP_SHARED_O_GPIO_PAD_CONFIG_0))
+
+//*****************************************************************************
+// PIN to PAD matrix
+//*****************************************************************************
+static const unsigned long g_ulPinToPadMap[64] =
+{
+ 10,11,12,13,14,15,16,17,255,255,18,
+ 19,20,21,22,23,24,40,28,29,25,255,
+ 255,255,255,255,255,255,255,255,255,255,255,
+ 255,255,255,255,255,255,255,255,255,255,255,
+ 31,255,255,255,255,0,255,32,30,255,1,
+ 255,2,3,4,5,6,7,8,9
+};
+
+
+//*****************************************************************************
+//
+//! Configures pin mux for the specified pin.
+//!
+//! \param ulPin is a valid pin.
+//! \param ulPinMode is one of the valid mode
+//!
+//! This function configures the pin mux that selects the peripheral function
+//! associated with a particular SOC pin. Only one peripheral function at a
+//! time can be associated with a pin, and each peripheral function should
+//! only be associated with a single pin at a time.
+//!
+//! \return none
+//
+//*****************************************************************************
+void PinModeSet(unsigned long ulPin,unsigned long ulPinMode)
+{
+
+ unsigned long ulPad;
+
+ //
+ // Get the corresponding Pad
+ //
+ ulPad = g_ulPinToPadMap[ulPin & 0x3F];
+
+ //
+ // Calculate the register address
+ //
+ ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
+
+ //
+ // Set the mode.
+ //
+ HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) | ulPinMode) & ~(3<<10));
+
+}
+
+//*****************************************************************************
+//
+//! Gets current pin mux configuration of specified pin.
+//!
+//! \param ulPin is a valid pin.
+//!
+//! This function get the current configuration of the pin mux.
+//!
+//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise.
+//
+//*****************************************************************************
+unsigned long PinModeGet(unsigned long ulPin)
+{
+
+ unsigned long ulPad;
+
+
+ //
+ // Get the corresponding Pad
+ //
+ ulPad = g_ulPinToPadMap[ulPin & 0x3F];
+
+
+ //
+ // Calculate the register address
+ //
+ ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ;
+
+ //
+ // return the mode.
+ //
+ return (HWREG(ulPad) & PAD_MODE_MASK);
+
+}
+
+//*****************************************************************************
+//
+//! Sets the direction of the specified pin(s).
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinIO is the pin direction and/or mode.
+//!
+//! This function configures the specified pin(s) as either input only or
+//! output only or it configures the pin to be under hardware control.
+//!
+//! The parameter \e ulPinIO is an enumerated data type that can be one of
+//! the following values:
+//!
+//! - \b PIN_DIR_MODE_IN
+//! - \b PIN_DIR_MODE_OUT
+//! - \b PIN_DIR_MODE_HW
+//!
+//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a
+//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is
+//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is
+//! placed under hardware control.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO)
+{
+ unsigned long ulPad;
+
+ //
+ // Get the corresponding Pad
+ //
+ ulPad = g_ulPinToPadMap[ulPin & 0x3F];
+
+ //
+ // Calculate the register address
+ //
+ ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
+
+ //
+ // Set the direction
+ //
+ HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO);
+}
+
+//*****************************************************************************
+//
+//! Gets the direction of a pin.
+//!
+//! \param ulPin is one of the valid pin.
+//!
+//! This function gets the direction and control mode for a specified pin on
+//! the selected GPIO port. The pin can be configured as either an input only
+//! or output only, or it can be under hardware control. The type of control
+//! and direction are returned as an enumerated data type.
+//!
+//! \return Returns one of the enumerated data types described for
+//! GPIODirModeSet().
+//
+//*****************************************************************************
+unsigned long PinDirModeGet(unsigned long ulPin)
+{
+ unsigned long ulPad;
+
+ //
+ // Get the corresponding Pad
+ //
+ ulPad = g_ulPinToPadMap[ulPin & 0x3F];
+
+ //
+ // Calculate the register address
+ //
+ ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
+
+ //
+ // Return the direction
+ //
+ return ((HWREG(ulPad) & 0xC00));
+}
+
+//*****************************************************************************
+//
+//! Gets Pin output drive strength and Type
+//!
+//! \param ulPin is one of the valid pin
+//! \param pulPinStrength is pointer to storage for output drive strength
+//! \param pulPinType is pinter to storage for pin type
+//!
+//! This function gets the pin type and output drive strength for the pin
+//! specified by \e ulPin parameter. Parameters \e pulPinStrength and
+//! \e pulPinType corresponds to the values used in PinConfigSet().
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
+ unsigned long *pulPinType)
+{
+
+ unsigned long ulPad;
+
+
+ //
+ // Get the corresponding Pad
+ //
+ ulPad = g_ulPinToPadMap[ulPin & 0x3F];
+
+
+ //
+ // Calculate the register address
+ //
+ ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
+
+
+ //
+ // Get the type
+ //
+ *pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK);
+
+ //
+ // Get the output drive strength
+ //
+ *pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK);
+
+}
+
+//*****************************************************************************
+//
+//! Configure Pin output drive strength and Type
+//!
+//! \param ulPin is one of the valid pin
+//! \param ulPinStrength is logical OR of valid output drive strengths.
+//! \param ulPinType is one of the valid pin type.
+//!
+//! This function sets the pin type and strength for the pin specified by
+//! \e ulPin parameter.
+//!
+//! The parameter \e ulPinStrength should be one of the following
+//! - \b PIN_STRENGTH_2MA
+//! - \b PIN_STRENGTH_4MA
+//! - \b PIN_STRENGTH_6MA
+//!
+//!
+//! The parameter \e ulPinType should be one of the following
+//! For standard type
+//!
+//! - \b PIN_TYPE_STD
+//! - \b PIN_TYPE_STD_PU
+//! - \b PIN_TYPE_STD_PD
+//!
+//! And for Open drain type
+//!
+//! - \b PIN_TYPE_OD
+//! - \b PIN_TYPE_OD_PU
+//! - \b PIN_TYPE_OD_PD
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
+ unsigned long ulPinType)
+{
+
+ unsigned long ulPad;
+
+ //
+ // Get the corresponding Pad
+ //
+ ulPad = g_ulPinToPadMap[ulPin & 0x3F];
+
+ //
+ // Write the register
+ //
+ if(ulPinType == PIN_TYPE_ANALOG)
+ {
+ //
+ // Isolate the input
+ //
+ HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8));
+
+ //
+ // Calculate the register address
+ //
+ ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
+
+ //
+ // Isolate the output
+ //
+ HWREG(ulPad) |= 0xC00;
+
+ }
+ else
+ {
+ //
+ // Enable the input
+ //
+ HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8));
+
+ //
+ // Calculate the register address
+ //
+ ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
+
+ //
+ // Write the configuration
+ //
+ HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) |
+ (ulPinStrength | ulPinType ));
+ }
+
+
+}
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by UART peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The UART pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin(s); other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//!
+//! \note This function cannot be used to turn any pin into a UART pin; it
+//! only sets the pin mode and configures it for proper UART operation.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode)
+{
+ //
+ // Set the pin to specified mode
+ //
+ PinModeSet(ulPin,ulPinMode);
+
+ //
+ // Set the pin for standard operation
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
+}
+
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by I2C peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The I2C pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! the pin.
+//!
+//!
+//! \note This function cannot be used to turn any pin into a I2C pin; it
+//! only sets the pin mode and configures it for proper I2C operation.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode)
+{
+ //
+ // Set the pin to specified mode
+ //
+ PinModeSet(ulPin,ulPinMode);
+
+ //
+ // Set the pin for open-drain operation with a weak pull-up.
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU);
+}
+
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by SPI peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The SPI pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin.
+//!
+//!
+//! \note This function cannot be used to turn any pin into a SPI pin; it
+//! only sets the pin mode and configures it for proper SPI operation.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode)
+{
+
+ //
+ // Set the pin to specified mode
+ //
+ PinModeSet(ulPin,ulPinMode);
+
+ //
+ // Set the pin for standard operation
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
+
+}
+
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by I2S peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The I2S pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin.
+//!
+//!
+//! \note This function cannot be used to turn any pin into a I2S pin; it
+//! only sets the pin mode and configures it for proper I2S operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode)
+{
+
+ //
+ // Set the pin to specified mode
+ //
+ PinModeSet(ulPin,ulPinMode);
+
+ //
+ // Set the pin for standard operation
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
+
+}
+
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by Timer peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The timer PWM pins must be properly configured for the Timer peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin; other configurations may work as well depending upon the
+//! board setup (for example, using the on-chip pull-ups).
+//!
+//!
+//! \note This function cannot be used to turn any pin into a timer PWM pin; it
+//! only sets the pin mode and configures it for proper timer PWM operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode)
+{
+
+ //
+ // Set the pin to specified mode
+ //
+ PinModeSet(ulPin,ulPinMode);
+
+ //
+ // Set the pin for standard operation
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
+}
+
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by Camera peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The Camera pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin.
+//!
+//!
+//! \note This function cannot be used to turn any pin into a Camera pin; it
+//! only sets the pin mode and configures it for proper Camera operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode)
+{
+
+ //
+ // Set the pin to specified mode
+ //
+ PinModeSet(ulPin,ulPinMode);
+
+ //
+ // Set the pin for standard operation
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
+
+}
+
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by GPIO peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//! \param bOpenDrain is one to decide either OpenDrain or STD
+//!
+//! The GPIO pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin.
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain)
+{
+
+ //
+ // Set the pin for standard push-pull operation.
+ //
+ if(bOpenDrain)
+ {
+ PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD);
+ }
+ else
+ {
+ PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD);
+ }
+
+ //
+ // Set the pin to specified mode
+ //
+ PinModeSet(ulPin, ulPinMode);
+
+}
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by ADC
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The ADC pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin.
+//!
+//!
+//! \note This function cannot be used to turn any pin into a ADC pin; it
+//! only sets the pin mode and configures it for proper ADC operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode)
+{
+ //
+ // Configure the Pin
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG);
+}
+
+//*****************************************************************************
+//
+//! Sets the pin mode and configures the pin for use by SD Host peripheral
+//!
+//! \param ulPin is one of the valid pin.
+//! \param ulPinMode is one of the valid pin mode.
+//!
+//! The MMC pins must be properly configured for the peripheral to
+//! function correctly. This function provides a typical configuration for
+//! those pin.
+//!
+//!
+//! \note This function cannot be used to turn any pin into a SD Host pin; it
+//! only sets the pin mode and configures it for proper SD Host operation.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode)
+{
+ //
+ // Set pin mode
+ //
+ PinModeSet(ulPin,ulPinMode);
+
+ //
+ // Configure the Pin
+ //
+ PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
+
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/pin.h b/cc3200/hal/pin.h
new file mode 100644
index 0000000000..11a2370e89
--- /dev/null
+++ b/cc3200/hal/pin.h
@@ -0,0 +1,176 @@
+//*****************************************************************************
+//
+// pin.h
+//
+// Defines and Macros for the pin mux module
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __PIN_H__
+#define __PIN_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+// Macros Defining Pins
+//*****************************************************************************
+
+#define PIN_01 0x00000000
+#define PIN_02 0x00000001
+#define PIN_03 0x00000002
+#define PIN_04 0x00000003
+#define PIN_05 0x00000004
+#define PIN_06 0x00000005
+#define PIN_07 0x00000006
+#define PIN_08 0x00000007
+#define PIN_11 0x0000000A
+#define PIN_12 0x0000000B
+#define PIN_13 0x0000000C
+#define PIN_14 0x0000000D
+#define PIN_15 0x0000000E
+#define PIN_16 0x0000000F
+#define PIN_17 0x00000010
+#define PIN_18 0x00000011
+#define PIN_19 0x00000012
+#define PIN_20 0x00000013
+#define PIN_21 0x00000014
+#define PIN_45 0x0000002C
+#define PIN_46 0x0000002D
+#define PIN_47 0x0000002E
+#define PIN_48 0x0000002F
+#define PIN_49 0x00000030
+#define PIN_50 0x00000031
+#define PIN_52 0x00000033
+#define PIN_53 0x00000034
+#define PIN_55 0x00000036
+#define PIN_56 0x00000037
+#define PIN_57 0x00000038
+#define PIN_58 0x00000039
+#define PIN_59 0x0000003A
+#define PIN_60 0x0000003B
+#define PIN_61 0x0000003C
+#define PIN_62 0x0000003D
+#define PIN_63 0x0000003E
+#define PIN_64 0x0000003F
+
+
+
+//*****************************************************************************
+// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet()
+//*****************************************************************************
+
+#define PIN_MODE_0 0x00000000
+#define PIN_MODE_1 0x00000001
+#define PIN_MODE_2 0x00000002
+#define PIN_MODE_3 0x00000003
+#define PIN_MODE_4 0x00000004
+#define PIN_MODE_5 0x00000005
+#define PIN_MODE_6 0x00000006
+#define PIN_MODE_7 0x00000007
+#define PIN_MODE_8 0x00000008
+#define PIN_MODE_9 0x00000009
+#define PIN_MODE_10 0x0000000A
+#define PIN_MODE_11 0x0000000B
+#define PIN_MODE_12 0x0000000C
+#define PIN_MODE_13 0x0000000D
+#define PIN_MODE_14 0x0000000E
+#define PIN_MODE_15 0x0000000F
+// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation
+// PIN_MODE_255 should never be used in any user code.
+#define PIN_MODE_255 0x000000FF
+
+//*****************************************************************************
+// Macros that can be used with PinDirModeSet() and returned from
+// PinDirModeGet().
+//*****************************************************************************
+#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input
+#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output
+#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function
+
+//*****************************************************************************
+// Macros that can be used with PinConfigSet()
+//*****************************************************************************
+#define PIN_STRENGTH_2MA 0x00000020
+#define PIN_STRENGTH_4MA 0x00000040
+#define PIN_STRENGTH_6MA 0x00000060
+
+#define PIN_TYPE_STD 0x00000000
+#define PIN_TYPE_STD_PU 0x00000100
+#define PIN_TYPE_STD_PD 0x00000200
+
+#define PIN_TYPE_OD 0x00000010
+#define PIN_TYPE_OD_PU 0x00000110
+#define PIN_TYPE_OD_PD 0x00000210
+#define PIN_TYPE_ANALOG 0x10000000
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode);
+extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO);
+extern unsigned long PinDirModeGet(unsigned long ulPin);
+extern unsigned long PinModeGet(unsigned long ulPin);
+extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
+ unsigned long *pulPinType);
+extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
+ unsigned long ulPinType);
+extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,
+ tBoolean bOpenDrain);
+extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PIN_H__
diff --git a/cc3200/hal/prcm.c b/cc3200/hal/prcm.c
new file mode 100644
index 0000000000..78b8d8276f
--- /dev/null
+++ b/cc3200/hal/prcm.c
@@ -0,0 +1,1778 @@
+//*****************************************************************************
+//
+// prcm.c
+//
+// Driver for the Power, Reset and Clock Module (PRCM)
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup PRCM_Power_Reset_Clock_Module_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_apps_rcm.h"
+#include "inc/hw_gprcm.h"
+#include "inc/hw_hib1p2.h"
+#include "inc/hw_hib3p3.h"
+#include "prcm.h"
+#include "interrupt.h"
+#include "cpu.h"
+#include "utils.h"
+#include "rom_map.h"
+
+
+//*****************************************************************************
+// Macro definition
+//*****************************************************************************
+#define PRCM_SOFT_RESET 0x00000001
+#define PRCM_ENABLE_STATUS 0x00000002
+#define SYS_CLK 80000000
+#define XTAL_CLK 40000000
+
+
+//*****************************************************************************
+// CC3200 does not have a true RTC capability. However, API(s) in this file
+// provide an effective mechanism to support RTC feature in the device.
+//
+// The implementation to support RTC has been kept very simple. A set of
+// HIB Memory Registers in conjunction with Slow Clock Counter are used
+// to render RTC information to users. Core principle of design involves
+// two steps (a) establish an association between user provided wall-clock
+// and slow clock counter. (b) store reference value of this associattion
+// in HIB Registers. This reference value and SCC value are then combined
+// to create real-world calendar time.
+//
+// Across HIB cycles, value stored in HIB Registers is retained and slow
+// clock counter continues to tick, thereby, this arragement is relevant
+// and valid as long as device has a (tickle) battery power.
+//
+// Further, provision also has been made to set an alarm. When it RTC value
+// matches that of set for alarm, an interrupt is generated.
+//
+// HIB MEM REG0 and REG1 are reserved for TI.
+//
+// If RTC feature is not used, then HIB REG2 & REG3 are available to user.
+//
+// Lower half of REG0 is used for TI HW ECO.
+//*****************************************************************************
+#define RTC_U64MSEC_MK(u32Secs, u16Msec) (((unsigned long long)u32Secs << 10)|\
+ (u16Msec & 0x3FF))
+
+#define RTC_SECS_IN_U64MSEC(u64Msec) ((unsigned long)(u64Msec >> 10))
+#define RTC_MSEC_IN_U64MSEC(u64Msec) ((unsigned short)(u64Msec & 0x3FF))
+
+#define RTC_SECS_U32_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG3)
+#define RTC_MSEC_U16_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2+2)
+
+#define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR))
+#define RTC_U16MSEC_REG (*(unsigned short*)RTC_MSEC_U16_REG_ADDR)
+
+//*****************************************************************************
+// Register Access and Updates
+//
+// Tick of SCC has a resolution of 32768Hz. Therefore, scaling SCC value by 32
+// yields ~1 msec resolution. All operations of SCC in RTC context use ms unit.
+//*****************************************************************************
+#define SCC_U64MSEC_GET() (PRCMSlowClkCtrGet() >> 5)
+#define SCC_U64MSEC_MATCH_SET(u64Msec) (PRCMSlowClkCtrMatchSet(u64Msec << 5))
+#define SCC_U64MSEC_MATCH_GET() (PRCMSlowClkCtrMatchGet() >> 5)
+
+//*****************************************************************************
+//
+// Bit: 31 is used to indicate use of RTC. If set as '1', RTC feature is used.
+// Bits: 30 to 26 are reserved, available to software for use
+// Bits: 25 to 16 are used to save millisecond part of RTC reference.
+// Bits: 15 to 0 are being used for HW Changes / ECO
+//
+//*****************************************************************************
+
+//*****************************************************************************
+// Set RTC USE Bit
+//*****************************************************************************
+static void RTCUseSet(void)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG | (1 << 15);
+
+ UtilsDelay((80*200)/3);
+
+ RTC_U16MSEC_REG = usRegValue;
+}
+
+//*****************************************************************************
+// Checks if RTC-USE bit is set
+//*****************************************************************************
+static tBoolean IsRTCUsed(void)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG;
+
+ UtilsDelay((80*200)/3);
+
+ return ((usRegValue & (1 << 15))? true : false);
+}
+
+//*****************************************************************************
+// Read 16-bit mSecs
+//*****************************************************************************
+static unsigned short RTCU16MSecRegRead(void)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG;
+
+ UtilsDelay((80*200)/3);
+
+ return (usRegValue & 0x3FF);
+}
+
+//*****************************************************************************
+// Write 16-bit mSecs
+//*****************************************************************************
+static void RTCU16MSecRegWrite(unsigned short u16Msec)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG;
+
+ UtilsDelay((80*200)/3);
+
+ RTC_U16MSEC_REG = ((usRegValue & ~0x3FF) |u16Msec);
+}
+
+//*****************************************************************************
+// Read 32-bit Secs
+//*****************************************************************************
+static unsigned long RTCU32SecRegRead(void)
+{
+ return (PRCMHIBRegRead(RTC_SECS_U32_REG_ADDR));
+}
+
+//*****************************************************************************
+// Write 32-bit Secs
+//*****************************************************************************
+static void RTCU32SecRegWrite(unsigned long u32Msec)
+{
+ PRCMHIBRegWrite(RTC_SECS_U32_REG_ADDR, u32Msec);
+}
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define IS_RTC_USED() IsRTCUsed()
+#define RTC_USE_SET() RTCUseSet()
+
+#define RTC_U16MSEC_REG_RD() RTCU16MSecRegRead()
+#define RTC_U16MSEC_REG_WR(u16Msec) RTCU16MSecRegWrite(u16Msec)
+
+#define RTC_U32SECS_REG_RD() RTCU32SecRegRead()
+#define RTC_U32SECS_REG_WR(u32Secs) RTCU32SecRegWrite(u32Secs)
+
+#define SELECT_SCC_U42BITS(u64Msec) (u64Msec & 0x3ffffffffff)
+
+//*****************************************************************************
+// Global Peripheral clock and rest Registers
+//*****************************************************************************
+static const PRCM_PeriphRegs_t PRCM_PeriphRegsList[] =
+{
+
+ {APPS_RCM_O_CAMERA_CLK_GATING, APPS_RCM_O_CAMERA_SOFT_RESET },
+ {APPS_RCM_O_MCASP_CLK_GATING, APPS_RCM_O_MCASP_SOFT_RESET },
+ {APPS_RCM_O_MMCHS_CLK_GATING, APPS_RCM_O_MMCHS_SOFT_RESET },
+ {APPS_RCM_O_MCSPI_A1_CLK_GATING, APPS_RCM_O_MCSPI_A1_SOFT_RESET },
+ {APPS_RCM_O_MCSPI_A2_CLK_GATING, APPS_RCM_O_MCSPI_A2_SOFT_RESET },
+ {APPS_RCM_O_UDMA_A_CLK_GATING, APPS_RCM_O_UDMA_A_SOFT_RESET },
+ {APPS_RCM_O_GPIO_A_CLK_GATING, APPS_RCM_O_GPIO_A_SOFT_RESET },
+ {APPS_RCM_O_GPIO_B_CLK_GATING, APPS_RCM_O_GPIO_B_SOFT_RESET },
+ {APPS_RCM_O_GPIO_C_CLK_GATING, APPS_RCM_O_GPIO_C_SOFT_RESET },
+ {APPS_RCM_O_GPIO_D_CLK_GATING, APPS_RCM_O_GPIO_D_SOFT_RESET },
+ {APPS_RCM_O_GPIO_E_CLK_GATING, APPS_RCM_O_GPIO_E_SOFT_RESET },
+ {APPS_RCM_O_WDOG_A_CLK_GATING, APPS_RCM_O_WDOG_A_SOFT_RESET },
+ {APPS_RCM_O_UART_A0_CLK_GATING, APPS_RCM_O_UART_A0_SOFT_RESET },
+ {APPS_RCM_O_UART_A1_CLK_GATING, APPS_RCM_O_UART_A1_SOFT_RESET },
+ {APPS_RCM_O_GPT_A0_CLK_GATING , APPS_RCM_O_GPT_A0_SOFT_RESET },
+ {APPS_RCM_O_GPT_A1_CLK_GATING, APPS_RCM_O_GPT_A1_SOFT_RESET },
+ {APPS_RCM_O_GPT_A2_CLK_GATING, APPS_RCM_O_GPT_A2_SOFT_RESET },
+ {APPS_RCM_O_GPT_A3_CLK_GATING, APPS_RCM_O_GPT_A3_SOFT_RESET },
+ {APPS_RCM_O_CRYPTO_CLK_GATING, APPS_RCM_O_CRYPTO_SOFT_RESET },
+ {APPS_RCM_O_MCSPI_S0_CLK_GATING, APPS_RCM_O_MCSPI_S0_SOFT_RESET },
+ {APPS_RCM_O_I2C_CLK_GATING, APPS_RCM_O_I2C_SOFT_RESET }
+
+};
+
+//*****************************************************************************
+//
+//! Performs a software reset of a SOC
+//!
+//! This function performs a software reset of a SOC
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMSOCReset(void)
+{
+ //
+ // Reset MCU
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_MCU_GLOBAL_SOFT_RESET) |= 0x1;
+
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a MCU and associated peripherals
+//!
+//! \param bIncludeSubsystem is \b true to reset associated peripherals.
+//!
+//! This function performs a software reset of a MCU and associated peripherals.
+//! To reset the associated peripheral, the parameter \e bIncludeSubsystem
+//! should be set to \b true.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMMCUReset(tBoolean bIncludeSubsystem)
+{
+ if(bIncludeSubsystem)
+ {
+ //
+ // Reset Apps processor and associated peripheral
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2;
+ }
+ else
+ {
+ //
+ // Reset Apps processor only
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the reason for a reset.
+//!
+//! This function returns the reason(s) for a reset. The reset reason are:-
+//! -\b PRCM_POWER_ON - Device is powering up.
+//! -\b PRCM_LPDS_EXIT - Device is exiting from LPDS.
+//! -\b PRCM_CORE_RESET - Device is exiting soft core only reset
+//! -\b PRCM_MCU_RESET - Device is exiting soft subsystem reset.
+//! -\b PRCM_WDT_RESET - Device was reset by watchdog.
+//! -\b PRCM_SOC_RESET - Device is exting SOC reset.
+//! -\b PRCM_HIB_EXIT - Device is exiting hibernate.
+//!
+//! \return Returns one of the cause defined above.
+//
+//*****************************************************************************
+unsigned long PRCMSysResetCauseGet()
+{
+ unsigned long ulWakeupStatus;
+
+ //
+ // Read the Reset status
+ //
+ ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF);
+
+ //
+ // For hibernate do additional chaeck.
+ //
+ if(ulWakeupStatus == PRCM_POWER_ON)
+ {
+ if(PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS) & 0x1)
+ {
+ ulWakeupStatus = PRCM_HIB_EXIT;
+ }
+ }
+
+ //
+ // Return status.
+ //
+ return ulWakeupStatus;
+}
+
+//*****************************************************************************
+//
+//! Enable clock(s) to peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripherals
+//! \param ulClkFlags are bitmask of clock(s) to be enabled.
+//!
+//! This function enables the clock for the specified peripheral. Peripherals
+//! are by default clock gated (disabled) and generates a bus fault if
+//! accessed.
+//!
+//! The parameter \e ulClkFlags can be logical OR of the following:
+//! -\b PRCM_RUN_MODE_CLK - Ungates clock to the peripheral
+//! -\b PRCM_SLP_MODE_CLK - Keeps the clocks ungated in sleep.
+//! -\b PRCM_DSLP_MODE_CLK - Keeps the clock ungated in deepsleep.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags)
+{
+ //
+ // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC
+ // as it is a dummy define for pinmux utility code generation
+ //
+ if(ulPeripheral != PRCM_ADC)
+ {
+ HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags;
+ }
+ //
+ // Set the default clock for camera
+ //
+ if(ulPeripheral == PRCM_CAMERA)
+ {
+ HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404;
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables clock(s) to peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripherals
+//! \param ulClkFlags are bitmask of clock(s) to be enabled.
+//!
+//! This function disable the clock for the specified peripheral. Peripherals
+//! are by default clock gated (disabled) and generated a bus fault if
+//! accessed.
+//!
+//! The parameter \e ulClkFlags can be logical OR bit fields as defined in
+//! PRCMEnablePeripheral().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags)
+{
+ //
+ // Disable the specified peripheral clocks
+ //
+ HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the input clock for the specified peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripherals.
+//!
+//! This function gets the input clock for the specified peripheral.
+//!
+//! The parameter \e ulPeripheral has the same definition as that in
+//! PRCMPeripheralClkEnable();
+//!
+//! \return Returns input clock frequency for specified peripheral.
+//
+//*****************************************************************************
+unsigned long
+PRCMPeripheralClockGet(unsigned long ulPeripheral)
+{
+ unsigned long ulClockFreq;
+ unsigned long ulHiPulseDiv;
+ unsigned long ulLoPulseDiv;
+
+ //
+ // Get the clock based on specified peripheral.
+ //
+ if(((ulPeripheral == PRCM_SSPI) | (ulPeripheral == PRCM_LSPI)
+ | (ulPeripheral == PRCM_GSPI)))
+ {
+ return XTAL_CLK;
+ }
+ else if(ulPeripheral == PRCM_CAMERA)
+ {
+ ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07);
+ ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN)& 0xFF);
+ }
+ else if(ulPeripheral == PRCM_SDHOST)
+ {
+ ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07);
+ ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN)& 0xFF);
+ }
+ else
+ {
+ return SYS_CLK;
+ }
+
+ //
+ // Compute the clock freq. from the divider value
+ //
+ ulClockFreq = (240000000/((ulHiPulseDiv + 1) + (ulLoPulseDiv + 1)));
+
+ //
+ // Return the clock rate.
+ //
+ return ulClockFreq;
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripheral.
+//!
+//! This assert or deassert reset to the specified peripheral based of the
+//! \e bAssert parameter.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMPeripheralReset(unsigned long ulPeripheral)
+{
+ volatile unsigned long ulDelay;
+
+ if( ulPeripheral != PRCM_DTHE)
+ {
+ //
+ // Assert the reset
+ //
+ HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg)
+ |= PRCM_SOFT_RESET;
+ //
+ // Delay for a little bit.
+ //
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)
+ {
+ }
+
+ //
+ // Deassert the reset
+ //
+ HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg)
+ &= ~PRCM_SOFT_RESET;
+ }
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is ready.
+//!
+//! \param ulPeripheral is one of the valid modules
+//!
+//! This function determines if a particular peripheral is ready to be
+//! accessed. The peripheral may be in a non-ready state if it is not enabled,
+//! is being held in reset, or is in the process of becoming ready after being
+//! enabled or taken out of reset.
+//!
+//! \return Returns \b true if the peripheral is ready, \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+PRCMPeripheralStatusGet(unsigned long ulPeripheral)
+{
+ unsigned long ReadyBit;
+
+ //
+ // Read the ready bit status
+ //
+ ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg);
+ ReadyBit = ReadyBit & PRCM_ENABLE_STATUS;
+
+ if (ReadyBit)
+ {
+ //
+ // Module is ready
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // Module is not ready
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configure I2S fracactional divider
+//!
+//! \param ulI2CClkFreq is the required input clock for McAPS module
+//!
+//! This function configures I2S fractional divider. By default this
+//! divider is set to output 24 Mhz clock to I2S module.
+//!
+//! The minimum frequency that can be obtained by configuring this divider is
+//!
+//! (240000KHz/1023.99) = 234.377 KHz
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq)
+{
+ unsigned long long ullDiv;
+ unsigned short usInteger;
+ unsigned short usFrac;
+
+ ullDiv = (((unsigned long long)240000000 * 65536)/ulI2CClkFreq);
+
+ usInteger = (ullDiv/65536);
+ usFrac = (ullDiv%65536);
+
+ HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) =
+ ((usInteger & 0x3FF) << 16 | usFrac);
+}
+
+//*****************************************************************************
+//
+//! Sets the LPDS exit PC and SP restore vlaues.
+//!
+//! \param ulStackPtr is the SP restore value.
+//! \param ulProgCntr is the PC restore value
+//!
+//! This function sets the LPDS exit PC and SP restore vlaues. Setting
+//! \e ulProgCntr to a non-zero value, forces bootloader to jump to that
+//! address with Stack Pointer initialized to \e ulStackPtr on LPDS exit,
+//! otherwise the application's vector table entries are used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr)
+{
+ //
+ // Set The SP Value
+ //
+ HWREG(0x4402E18C) = ulStackPtr;
+
+ //
+ // Set The PC Value
+ //
+ HWREG(0x4402E190) = ulProgCntr;
+}
+
+//*****************************************************************************
+//
+//! Puts the system into Low Power Deel Sleep (LPDS) power mode.
+//!
+//! This function puts the system into Low Power Deel Sleep (LPDS) power mode.
+//! A call to this function never returns and the execution starts from Reset.
+//! \sa PRCMLPDSRestoreInfoSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSEnter()
+{
+ //
+ // Disable TestPD
+ //
+ HWREG(0x4402E168) |= (1<<9);
+
+ //
+ // Set bandgap duty cycle to 1
+ //
+ HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
+
+ //
+ // Request LPDS
+ //
+ HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ)
+ = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ;
+
+ __asm(" nop\n"
+ " nop\n"
+ " nop\n"
+ " nop\n");
+}
+
+//*****************************************************************************
+//
+//! Enable the individual LPDS wakeup source(s).
+//!
+//! \param ulLpdsWakeupSrc is logical OR of wakeup sources.
+//!
+//! This function enable the individual LPDS wakeup source(s) and following
+//! three wakeup sources (\e ulLpdsWakeupSrc ) are supported by the device.
+//! -\b PRCM_LPDS_HOST_IRQ
+//! -\b PRCM_LPDS_GPIO
+//! -\b PRCM_LPDS_TIMER
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read the current wakup sources
+ //
+ ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG);
+
+ //
+ // Enable individual wakeup source
+ //
+ ulRegVal = ((ulRegVal | ulLpdsWakeupSrc) & 0x91);
+
+ //
+ // Set the configuration in the register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal;
+}
+
+//*****************************************************************************
+//
+//! Disable the individual LPDS wakeup source(s).
+//!
+//! \param ulLpdsWakeupSrc is logical OR of wakeup sources.
+//!
+//! This function enable the individual LPDS wakeup source(s) and following
+//! three wake up sources (\e ulLpdsWakeupSrc ) are supported by the device.
+//! -\b PRCM_LPDS_HOST_IRQ
+//! -\b PRCM_LPDS_GPIO
+//! -\b PRCM_LPDS_TIMER
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc)
+{
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc;
+}
+
+
+//*****************************************************************************
+//
+//! Get LPDS wakeup cause
+//!
+//! This function gets LPDS wakeup caouse
+//!
+//! \return Returns values enumerated as described in
+//! PRCMLPDSWakeupSourceEnable().
+//
+//*****************************************************************************
+unsigned long
+PRCMLPDSWakeupCauseGet()
+{
+ return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC));
+}
+
+//*****************************************************************************
+//
+//! Sets LPDS wakeup Timer
+//!
+//! \param ulTicks is number of 32.768 KHz clocks
+//!
+//! This function sets internal LPDS wakeup timer running at 32.768 KHz. The
+//! timer is only configured if the parameter \e ulTicks is in valid range i.e.
+//! from 21 to 2^32.
+//!
+//! \return Returns \b true on success, \b false otherwise.
+//
+//*****************************************************************************
+void
+PRCMLPDSIntervalSet(unsigned long ulTicks)
+{
+ //
+ // Check sleep is atleast for 21 cycles
+ // If not set the sleep time to 21 cycles
+ //
+ if( ulTicks < 21)
+ {
+ ulTicks = 21;
+ }
+
+ HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks;
+ HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20;
+}
+
+//*****************************************************************************
+//
+//! Selects the GPIO for LPDS wakeup
+//!
+//! \param ulGPIOPin is one of the valid GPIO fro LPDS wakeup.
+//! \param ulType is the wakeup trigger type.
+//!
+//! This function setects the wakeup GPIO for LPDS wakeup and can be
+//! used to select one out of 7 pre-defined GPIO(s).
+//!
+//! The parameter \e ulLpdsGPIOSel should be one of the following:-
+//! -\b PRCM_LPDS_GPIO2
+//! -\b PRCM_LPDS_GPIO4
+//! -\b PRCM_LPDS_GPIO13
+//! -\b PRCM_LPDS_GPIO17
+//! -\b PRCM_LPDS_GPIO11
+//! -\b PRCM_LPDS_GPIO24
+//! -\b PRCM_LPDS_GPIO26
+//!
+//! The parameter \e ulType sets the trigger type and can be one of the
+//! following:
+//! - \b PRCM_LPDS_LOW_LEVEL
+//! - \b PRCM_LPDS_HIGH_LEVEL
+//! - \b PRCM_LPDS_FALL_EDGE
+//! - \b PRCM_LPDS_RISE_EDGE
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType)
+{
+ //
+ // Set the wakeup GPIO
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL, ulGPIOPin);
+
+ //
+ // Set the trigger type.
+ //
+ HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3);
+}
+
+//*****************************************************************************
+//
+//! Puts the system into Sleep.
+//!
+//! This function puts the system into sleep power mode. System exits the power
+//! state on any one of the available interrupt. On exit from sleep mode the
+//! function returns to the calling function with all the processor core
+//! registers retained.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMSleepEnter()
+{
+ //
+ // Request Sleep
+ //
+ CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! Puts the system into Deep Sleep power mode.
+//!
+//! This function puts the system into Deep Sleep power mode. System exits the
+//! power state on any one of the available interrupt. On exit from deep
+//! sleep the function returns to the calling function with all the processor
+//! core registers retained.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMDeepSleepEnter()
+{
+ //
+ // Set bandgap duty cycle to 1
+ //
+ HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
+
+ //
+ // Enable DSLP in cortex
+ //
+ HWREG(0xE000ED10)|=1<<2;
+
+ //
+ // Request Deep Sleep
+ //
+ CPUwfi();
+
+ //
+ // Disable DSLP in cortex before
+ // returning to the caller
+ //
+ HWREG(0xE000ED10) &= ~(1<<2);
+
+}
+
+//*****************************************************************************
+//
+//! Enable SRAM column retention during Deep Sleep and/or LPDS Power mode(s)
+//!
+//! \param ulSramColSel is bit mask of valid SRAM columns.
+//! \param ulModeFlags is the bit mask of power modes.
+//!
+//! This functions enables the SRAM retention. The device supports configurable
+//! SRAM column retention in Low Power Deep Sleep (LPDS) and Deep Sleep power
+//! modes. Each column is of 64 KB size.
+//!
+//! The parameter \e ulSramColSel should be logical OR of the following:-
+//! -\b PRCM_SRAM_COL_1
+//! -\b PRCM_SRAM_COL_2
+//! -\b PRCM_SRAM_COL_3
+//! -\b PRCM_SRAM_COL_4
+//!
+//! The parameter \e ulModeFlags selects the power modes and sholud be logical
+//! OR of one or more of the following
+//! -\b PRCM_SRAM_DSLP_RET
+//! -\b PRCM_SRAM_LPDS_RET
+//!
+//! \return None.
+//
+//****************************************************************************
+void
+PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulModeFlags)
+{
+ if(ulModeFlags & PRCM_SRAM_DSLP_RET)
+ {
+ //
+ // Configure deep sleep SRAM retention register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_DSLP_CFG) = (ulSramColSel & 0xF);
+ }
+
+ if(ulModeFlags & PRCM_SRAM_LPDS_RET)
+ {
+ //
+ // Configure LPDS SRAM retention register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disable SRAM column retention during Deep Sleep and/or LPDS Power mode(s).
+//!
+//! \param ulSramColSel is bit mask of valid SRAM columns.
+//! \param ulFlags is the bit mask of power modes.
+//!
+//! This functions disable the SRAM retention. The device supports configurable
+//! SRAM column retention in Low Power Deep Sleep (LPDS) and Deep Sleep power
+//! modes. Each column is of 64 KB size.
+//!
+//! The parameter \e ulSramColSel should be logical OR of the following:-
+//! -\b PRCM_SRAM_COL_1
+//! -\b PRCM_SRAM_COL_2
+//! -\b PRCM_SRAM_COL_3
+//! -\b PRCM_SRAM_COL_4
+//!
+//! The parameter \e ulFlags selects the power modes and sholud be logical OR
+//! of one or more of the following
+//! -\b PRCM_SRAM_DSLP_RET
+//! -\b PRCM_SRAM_LPDS_RET
+//!
+//! \return None.
+//
+//****************************************************************************
+void
+PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags)
+{
+ if(ulFlags & PRCM_SRAM_DSLP_RET)
+ {
+ //
+ // Configure deep sleep SRAM retention register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_DSLP_CFG) &= ~(ulSramColSel & 0xF);
+ }
+
+ if(ulFlags & PRCM_SRAM_LPDS_RET)
+ {
+ //
+ // Configure LPDS SRAM retention register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF);
+ }
+}
+
+
+//*****************************************************************************
+//
+//! Enables individual HIB wakeup source(s).
+//!
+//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources.
+//!
+//! This function enables individual HIB wakeup source(s). The paramter
+//! \e ulHIBWakupSrc is the bit mask of HIB wakeup sources and should be
+//! logical OR of one or more of the follwoing :-
+//! -\b PRCM_HIB_SLOW_CLK_CTR
+//! -\b PRCM_HIB_GPIO2
+//! -\b PRCM_HIB_GPIO4
+//! -\b PRCM_HIB_GPIO13
+//! -\b PRCM_HIB_GPIO17
+//! -\b PRCM_HIB_GPIO11
+//! -\b PRCM_HIB_GPIO24
+//! -\b PRCM_HIB_GPIO26
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc)
+{
+ unsigned long ulRegValue;
+
+ //
+ // Read the RTC register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN);
+
+ //
+ // Enable the RTC as wakeup source if specified
+ //
+ ulRegValue |= (ulHIBWakupSrc & 0x1);
+
+ //
+ // Enable HIB wakeup sources
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue);
+
+ //
+ // REad the GPIO wakeup configuration register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN);
+
+ //
+ // Enable the specified GPIOs a wakeup sources
+ //
+ ulRegValue |= ((ulHIBWakupSrc>>16)&0xFF);
+
+ //
+ // Write the new register configuration
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue);
+}
+
+//*****************************************************************************
+//
+//! Disable individual HIB wakeup source(s).
+//!
+//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources.
+//!
+//! This function disable individual HIB wakeup source(s). The paramter
+//! \e ulHIBWakupSrc is same as bit fileds defined in
+//! PRCMEnableHibernateWakeupSource()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc)
+{
+ unsigned long ulRegValue;
+
+ //
+ // Read the RTC register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN);
+
+ //
+ // Disable the RTC as wakeup source if specified
+ //
+ ulRegValue &= ~(ulHIBWakupSrc & 0x1);
+
+ //
+ // Disable HIB wakeup sources
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue);
+
+ //
+ // Read the GPIO wakeup configuration register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN);
+
+ //
+ // Enable the specified GPIOs a wakeup sources
+ //
+ ulRegValue &= ~((ulHIBWakupSrc>>16)&0xFF);
+
+ //
+ // Write the new register configuration
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue);
+}
+
+
+//*****************************************************************************
+//
+//! Get hibernate wakeup cause
+//!
+//! This function gets the hibernate wakeup cause.
+//!
+//! \return Returns \b PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK or
+//! \b PRCM_HIB_WAKEUP_CAUSE_GPIO
+//
+//*****************************************************************************
+unsigned long
+PRCMHibernateWakeupCauseGet()
+{
+ return ((PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS)>>1)&0xF);
+}
+
+//*****************************************************************************
+//
+//! Sets Hibernate wakeup Timer
+//!
+//! \param ullTicks is number of 32.768 KHz clocks
+//!
+//! This function sets internal hibernate wakeup timer running at 32.768 KHz.
+//!
+//! \return Returns \b true on success, \b false otherwise.
+//
+//*****************************************************************************
+void
+PRCMHibernateIntervalSet(unsigned long long ullTicks)
+{
+ unsigned long long ullRTCVal;
+
+ //
+ // Latch the RTC vlaue
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1);
+
+ //
+ // Read latched values as 2 32-bit vlaues
+ //
+ ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW);
+ ullRTCVal = ullRTCVal << 32;
+ ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW);
+
+ //
+ // Add the interval
+ //
+ ullRTCVal = ullRTCVal + ullTicks;
+
+ //
+ // Set RTC match value
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF,
+ (unsigned long)(ullRTCVal));
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF,
+ (unsigned long)(ullRTCVal>>32));
+}
+
+
+//*****************************************************************************
+//
+//! Selects the GPIO(s) for hibernate wakeup
+//!
+//! \param ulGPIOBitMap is the bit-map of valid hibernate wakeup GPIO.
+//! \param ulType is the wakeup trigger type.
+//!
+//! This function setects the wakeup GPIO for hibernate and can be
+//! used to select any combination of 7 pre-defined GPIO(s).
+//!
+//! This function enables individual HIB wakeup source(s). The paramter
+//! \e ulGPIOBitMap should be one of the follwoing :-
+//! -\b PRCM_HIB_GPIO2
+//! -\b PRCM_HIB_GPIO4
+//! -\b PRCM_HIB_GPIO13
+//! -\b PRCM_HIB_GPIO17
+//! -\b PRCM_HIB_GPIO11
+//! -\b PRCM_HIB_GPIO24
+//! -\b PRCM_HIB_GPIO26
+//!
+//! The parameter \e ulType sets the trigger type and can be one of the
+//! following:
+//! - \b PRCM_HIB_LOW_LEVEL
+//! - \b PRCM_HIB_HIGH_LEVEL
+//! - \b PRCM_HIB_FALL_EDGE
+//! - \b PRCM_HIB_RISE_EDGE
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMHibernateWakeUpGPIOSelect(unsigned long ulGPIOBitMap, unsigned long ulType)
+{
+ unsigned char ucLoop;
+ unsigned long ulRegValue;
+
+ //
+ // Shift the bits to extract the GPIO selection
+ //
+ ulGPIOBitMap >>= 16;
+
+ //
+ // Set the configuration for each GPIO
+ //
+ for(ucLoop=0; ucLoop < 7; ucLoop++)
+ {
+ if(ulGPIOBitMap & (1<>32));
+}
+
+//*****************************************************************************
+//
+//! Gets slow clock counter match value.
+//!
+//! This function gets the match value for slow clock counter. This is use
+//! to interrupt the processor when RTC counts to the specified value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long long PRCMSlowClkCtrMatchGet()
+{
+ unsigned long long ullValue;
+
+ //
+ // Get RTC match value
+ //
+ ullValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF);
+ ullValue = ullValue<<32;
+ ullValue |= PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF);
+
+ //
+ // Return the value
+ //
+ return ullValue;
+}
+
+
+//*****************************************************************************
+//
+//! Write to On-Chip Retention (OCR) register.
+//!
+//! This function writes to On-Chip retention register. The device supports two
+//! 4-byte OCR register which are retained across all power mode.
+//!
+//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue)
+{
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2+(ucIndex << 2),ulRegValue);
+}
+
+//*****************************************************************************
+//
+//! Read from On-Chip Retention (OCR) register.
+//!
+//! This function reads from On-Chip retention register. The device supports two
+//! 4-byte OCR register which are retained across all power mode.
+//!
+//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long PRCMOCRRegisterRead(unsigned char ucIndex)
+{
+ //
+ // Return the read value.
+ //
+ return PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2 + (ucIndex << 2));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the PRCM.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller;
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_PRCM, pfnHandler);
+
+ //
+ // Enable the PRCM interrupt.
+ //
+ IntEnable(INT_PRCM);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the PRCM.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a PRCM interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIntUnregister()
+{
+ //
+ // Enable the UART interrupt.
+ //
+ IntDisable(INT_PRCM);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntUnregister(INT_PRCM);
+}
+
+//*****************************************************************************
+//
+//! Enables individual PRCM interrupt sources.
+//!
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated ARCM interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//! -\b PRCM_INT_SLOW_CLK_CTR
+//!
+//
+//*****************************************************************************
+void PRCMIntEnable(unsigned long ulIntFlags)
+{
+ unsigned long ulRegValue;
+
+ if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR )
+ {
+ //
+ // Enable PRCM interrupt
+ //
+ HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4;
+
+ //
+ // Enable RTC interrupt
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE);
+ ulRegValue |= 0x1;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables individual PRCM interrupt sources.
+//!
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated ARCM interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to PRCMEnableInterrupt().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIntDisable(unsigned long ulIntFlags)
+{
+ unsigned long ulRegValue;
+
+ if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR )
+ {
+ //
+ // Disable PRCM interrupt
+ //
+ HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4;
+
+ //
+ // Disable RTC interrupt
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE);
+ ulRegValue &= ~0x1;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! This function returns the PRCM interrupt status of interrupts that are
+//! allowed to reflect to the processor. The interrupts are cleared on read.
+//!
+//! \return Returns the current interrupt status.
+//
+//*****************************************************************************
+unsigned long PRCMIntStatus()
+{
+ return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS);
+}
+
+//*****************************************************************************
+//
+//! Mark the function of RTC as being used
+//!
+//! This function marks in HW that feature to maintain calendar time in device
+//! is being used.
+//!
+//! Specifically, this feature reserves user's HIB Register-1 accessed through
+//! PRCMOCRRegisterWrite(1) for internal work / purpose, therefore, the stated
+//! register is not available to user. Also, users must not excercise the Slow
+//! Clock Counter API(s), if RTC has been set for use.
+//!
+//! The RTC feature, if set or marked, can be only reset either through reboot
+//! or power cycle.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCInUseSet()
+{
+ RTC_USE_SET();
+ return;
+}
+
+//*****************************************************************************
+//
+//! Ascertain whether function of RTC is being used
+//!
+//! This function indicates whether function of RTC is being used on the device
+//! or not.
+//!
+//! This routine should be utilized by the application software, when returning
+//! from low-power, to confirm that RTC has been put to use and may not need to
+//! set the value of the RTC.
+//!
+//! The RTC feature, if set or marked, can be only reset either through reboot
+//! or power cycle.
+//!
+//! \return None.
+//
+//*****************************************************************************
+tBoolean PRCMRTCInUseGet()
+{
+ return IS_RTC_USED()? true : false;
+}
+
+//*****************************************************************************
+//
+//! Set the calendar time in the device.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function sets the specified calendar time in the device. The calendar
+//! time is outlined in terms of seconds and milliseconds. However, the device
+//! makes no assumption about the origin or reference of the calendar time.
+//!
+//! The device uses the indicated calendar value to update and maintain the
+//! wall-clock time across active and low power states.
+//!
+//! The function PRCMRTCInUseSet() must be invoked prior to use of this feature.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec) - SCC_U64MSEC_GET();
+
+ RTC_U32SECS_REG_WR(RTC_SECS_IN_U64MSEC(ullMsec));
+ RTC_U16MSEC_REG_WR(RTC_MSEC_IN_U64MSEC(ullMsec));
+ }
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Get the instantaneous calendar time from the device.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function fetches the instantaneous value of the ticking calendar time
+//! from the device. The calendar time is outlined in terms of seconds and
+//! milliseconds.
+//!
+//! The device provides the calendar value that has been maintained across
+//! active and low power states.
+//!
+//! The function PRCMRTCSet() must have been invoked once to set a reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
+ RTC_U16MSEC_REG_RD());
+ ullMsec += SCC_U64MSEC_GET();
+ }
+
+ *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec);
+ *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec);
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Set a calendar time alarm.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function sets an wall-clock alarm in the device to be reported for a
+//! futuristic calendar time. The calendar time is outlined in terms of seconds
+//! and milliseconds.
+//!
+//! The device provides uses the calendar value that has been maintained across
+//! active and low power states to report attainment of alarm time.
+//!
+//! The function PRCMRTCSet() must have been invoked once to set a reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec);
+ ullMsec -= RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
+ RTC_U16MSEC_REG_RD());
+ SCC_U64MSEC_MATCH_SET(SELECT_SCC_U42BITS(ullMsec));
+ }
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Get a previously set calendar time alarm.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function fetches from the device a wall-clock alarm that would have
+//! been previously set in the device. The calendar time is outlined in terms
+//! of seconds and milliseconds.
+//!
+//! If no alarm was set in the past, then this function would fetch a random
+//! information.
+//!
+//! The function PRCMRTCMatchSet() must have been invoked once to set an alarm.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = SCC_U64MSEC_MATCH_GET();
+ ullMsec += RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
+ RTC_U16MSEC_REG_RD());
+ }
+
+ *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec);
+ *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec);
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! MCU Initialization Routine
+//!
+//! This function sets mandatory configurations for the MCU
+//!
+//! \return None
+//
+//*****************************************************************************
+void PRCMCC3200MCUInit()
+{
+ unsigned long ulRegValue;
+
+ //
+ // DIG DCDC LPDS ECO Enable
+ //
+ HWREG(0x4402F064) |= 0x800000;
+
+ //
+ // Enable hibernate ECO for PG 1.32 devices only. With this ECO enabled,
+ // any hibernate wakeup source will be kept maked until the device enters
+ // hibernate completely (analog + digital)
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0);
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0, ulRegValue | (1<<4));
+
+ //
+ // Handling the clock switching (for 1.32 only)
+ //
+ HWREG(0x4402E16C) |= 0x3C;
+
+ //
+ // Enable uDMA
+ //
+ MAP_PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
+
+ //
+ // Reset uDMA
+ //
+ MAP_PRCMPeripheralReset(PRCM_UDMA);
+
+ //
+ // Disable uDMA
+ //
+ MAP_PRCMPeripheralClkDisable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
+
+ //
+ // Enable RTC
+ //
+ if(MAP_PRCMSysResetCauseGet()== PRCM_POWER_ON)
+ {
+ MAP_PRCMHIBRegWrite(0x4402F804,0x1);
+ }
+
+ //
+ // SWD mode
+ //
+ if (((HWREG(0x4402F0C8) & 0xFF) == 0x2))
+ {
+ HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
+ HWREG(0x4402E114) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
+ }
+
+ //
+ // Override JTAG mux
+ //
+ HWREG(0x4402E184) |= 0x2;
+
+ //
+ // Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1
+ //
+ if ((HWREG(0x4402E0A4) & 0xF) == 0x1)
+ {
+ HWREG(0x4402E0A4) = ((HWREG(0x4402E0A4) & ~0xF));
+ }
+
+ if ((HWREG(0x4402E0A8) & 0xF) == 0x1)
+ {
+ HWREG(0x4402E0A8) = ((HWREG(0x4402E0A8) & ~0xF));
+ }
+
+ //
+ // DIG DCDC VOUT trim settings based on PROCESS INDICATOR
+ //
+ if (((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE)
+ {
+ HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18));
+ }
+ else
+ {
+ HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18));
+ }
+
+ //
+ // Enable SOFT RESTART in case of DIG DCDC collapse
+ //
+ HWREG(0x4402FC74) &= ~(0x10000000);
+
+
+ //
+ // Disable the sleep for ANA DCDC
+ //
+ HWREG(0x4402F0A8) |= 0x00000004 ;
+}
+
+//*****************************************************************************
+//
+//! Reads 32-bit value from register at specified address
+//!
+//! \param ulRegAddr is the address of register to be read.
+//!
+//! This function reads 32-bit value from the register as specified by
+//! \e ulRegAddr.
+//!
+//! \return Return the value of the register.
+//
+//*****************************************************************************
+unsigned long PRCMHIBRegRead(unsigned long ulRegAddr)
+{
+ unsigned long ulValue;
+
+ //
+ // Read the Reg value
+ //
+ ulValue = HWREG(ulRegAddr);
+
+ //
+ // Wait for 200 uSec
+ //
+ UtilsDelay((80*200)/3);
+
+ //
+ // Return the value
+ //
+ return ulValue;
+}
+
+//*****************************************************************************
+//
+//! Writes 32-bit value to register at specified address
+//!
+//! \param ulRegAddr is the address of register to be read.
+//! \param ulValue is the 32-bit value to be written.
+//!
+//! This function writes 32-bit value passed as \e ulValue to the register as
+//! specified by \e ulRegAddr
+//!
+//! \return None
+//
+//*****************************************************************************
+void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue)
+{
+ //
+ // Read the Reg value
+ //
+ HWREG(ulRegAddr) = ulValue;
+
+ //
+ // Wait for 200 uSec
+ //
+ UtilsDelay((80*200)/3);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/prcm.h b/cc3200/hal/prcm.h
new file mode 100644
index 0000000000..067c66cba6
--- /dev/null
+++ b/cc3200/hal/prcm.h
@@ -0,0 +1,272 @@
+//*****************************************************************************
+//
+// prcm.h
+//
+// Prototypes for the PRCM control driver.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __PRCM_H__
+#define __PRCM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Peripheral clock and reset control registers
+//
+//*****************************************************************************
+typedef struct _PRCM_PeripheralRegs_
+{
+
+unsigned long ulClkReg;
+unsigned long ulRstReg;
+
+}PRCM_PeriphRegs_t;
+
+//*****************************************************************************
+// Values that can be passed to PRCMPeripheralEnable() and
+// PRCMPeripheralDisable()
+//*****************************************************************************
+#define PRCM_RUN_MODE_CLK 0x00000001
+#define PRCM_SLP_MODE_CLK 0x00000100
+#define PRCM_DSLP_MODE_CLK 0x00010000
+
+//*****************************************************************************
+// Values that can be passed to PRCMSRAMRetentionEnable() and
+// PRCMSRAMRetentionDisable() as ulSramColSel.
+//*****************************************************************************
+#define PRCM_SRAM_COL_1 0x00000001
+#define PRCM_SRAM_COL_2 0x00000002
+#define PRCM_SRAM_COL_3 0x00000004
+#define PRCM_SRAM_COL_4 0x00000008
+
+//*****************************************************************************
+// Values that can be passed to PRCMSRAMRetentionEnable() and
+// PRCMSRAMRetentionDisable() as ulModeFlags.
+//*****************************************************************************
+#define PRCM_SRAM_DSLP_RET 0x00000001
+#define PRCM_SRAM_LPDS_RET 0x00000002
+
+//*****************************************************************************
+// Values that can be passed to PRCMLPDSWakeupSourceEnable(),
+// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable().
+//*****************************************************************************
+#define PRCM_LPDS_HOST_IRQ 0x00000080
+#define PRCM_LPDS_GPIO 0x00000010
+#define PRCM_LPDS_TIMER 0x00000001
+
+//*****************************************************************************
+// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type
+//*****************************************************************************
+#define PRCM_LPDS_LOW_LEVEL 0x00000002
+#define PRCM_LPDS_HIGH_LEVEL 0x00000000
+#define PRCM_LPDS_FALL_EDGE 0x00000001
+#define PRCM_LPDS_RISE_EDGE 0x00000003
+
+//*****************************************************************************
+// Values that can be passed to PRCMLPDSWakeUpGPIOSelect()
+//*****************************************************************************
+#define PRCM_LPDS_GPIO2 0x00000000
+#define PRCM_LPDS_GPIO4 0x00000001
+#define PRCM_LPDS_GPIO13 0x00000002
+#define PRCM_LPDS_GPIO17 0x00000003
+#define PRCM_LPDS_GPIO11 0x00000004
+#define PRCM_LPDS_GPIO24 0x00000005
+#define PRCM_LPDS_GPIO26 0x00000006
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
+// PRCMHibernateWakeupSourceDisable().
+//*****************************************************************************
+#define PRCM_HIB_SLOW_CLK_CTR 0x00000001
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType
+//*****************************************************************************
+#define PRCM_HIB_LOW_LEVEL 0x00000000
+#define PRCM_HIB_HIGH_LEVEL 0x00000001
+#define PRCM_HIB_FALL_EDGE 0x00000002
+#define PRCM_HIB_RISE_EDGE 0x00000003
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
+// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect()
+//*****************************************************************************
+#define PRCM_HIB_GPIO2 0x00010000
+#define PRCM_HIB_GPIO4 0x00020000
+#define PRCM_HIB_GPIO13 0x00040000
+#define PRCM_HIB_GPIO17 0x00080000
+#define PRCM_HIB_GPIO11 0x00100000
+#define PRCM_HIB_GPIO24 0x00200000
+#define PRCM_HIB_GPIO26 0x00400000
+
+//*****************************************************************************
+// Values that will be returned from PRCMSysResetCauseGet().
+//*****************************************************************************
+#define PRCM_POWER_ON 0x00000000
+#define PRCM_LPDS_EXIT 0x00000001
+#define PRCM_CORE_RESET 0x00000003
+#define PRCM_MCU_RESET 0x00000004
+#define PRCM_WDT_RESET 0x00000005
+#define PRCM_SOC_RESET 0x00000006
+#define PRCM_HIB_EXIT 0x00000007
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeupCauseGet().
+//*****************************************************************************
+#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002
+#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004
+
+//*****************************************************************************
+// Values that can be passed to PRCMSEnableInterrupt
+//*****************************************************************************
+#define PRCM_INT_SLOW_CLK_CTR 0x00004000
+
+//*****************************************************************************
+// Values that can be passed to PRCMPeripheralClkEnable(),
+// PRCMPeripheralClkDisable(), PRCMPeripheralReset()
+//*****************************************************************************
+#define PRCM_CAMERA 0x00000000
+#define PRCM_I2S 0x00000001
+#define PRCM_SDHOST 0x00000002
+#define PRCM_GSPI 0x00000003
+#define PRCM_LSPI 0x00000004
+#define PRCM_UDMA 0x00000005
+#define PRCM_GPIOA0 0x00000006
+#define PRCM_GPIOA1 0x00000007
+#define PRCM_GPIOA2 0x00000008
+#define PRCM_GPIOA3 0x00000009
+#define PRCM_GPIOA4 0x0000000A
+#define PRCM_WDT 0x0000000B
+#define PRCM_UARTA0 0x0000000C
+#define PRCM_UARTA1 0x0000000D
+#define PRCM_TIMERA0 0x0000000E
+#define PRCM_TIMERA1 0x0000000F
+#define PRCM_TIMERA2 0x00000010
+#define PRCM_TIMERA3 0x00000011
+#define PRCM_DTHE 0x00000012
+#define PRCM_SSPI 0x00000013
+#define PRCM_I2CA0 0x00000014
+// Note : PRCM_ADC is a dummy define for pinmux utility code generation
+// PRCM_ADC should never be used in any user code.
+#define PRCM_ADC 0x000000FF
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PRCMSOCReset(void);
+extern void PRCMMCUReset(tBoolean bIncludeSubsystem);
+extern unsigned long PRCMSysResetCauseGet(void);
+
+extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral,
+ unsigned long ulClkFlags);
+extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral,
+ unsigned long ulClkFlags);
+extern void PRCMPeripheralReset(unsigned long ulPeripheral);
+extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral);
+
+extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq);
+extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral);
+
+extern void PRCMSleepEnter(void);
+extern void PRCMDeepSleepEnter(void);
+
+extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel,
+ unsigned long ulFlags);
+extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel,
+ unsigned long ulFlags);
+extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP,
+ unsigned long ulRestorePC);
+extern void PRCMLPDSEnter(void);
+extern void PRCMLPDSIntervalSet(unsigned long ulTicks);
+extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc);
+extern unsigned long PRCMLPDSWakeupCauseGet(void);
+extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin,
+ unsigned long ulType);
+extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc);
+
+extern void PRCMHibernateEnter(void);
+extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc);
+extern unsigned long PRCMHibernateWakeupCauseGet(void);
+extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap,
+ unsigned long ulType);
+extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc);
+extern void PRCMHibernateIntervalSet(unsigned long long ullTicks);
+
+extern unsigned long long PRCMSlowClkCtrGet(void);
+extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks);
+extern unsigned long long PRCMSlowClkCtrMatchGet(void);
+
+extern void PRCMOCRRegisterWrite(unsigned char ucIndex,
+ unsigned long ulRegValue);
+extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex);
+
+extern void PRCMIntRegister(void (*pfnHandler)(void));
+extern void PRCMIntUnregister(void);
+extern void PRCMIntEnable(unsigned long ulIntFlags);
+extern void PRCMIntDisable(unsigned long ulIntFlags);
+extern unsigned long PRCMIntStatus(void);
+extern void PRCMRTCInUseSet(void);
+extern tBoolean PRCMRTCInUseGet(void);
+extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec);
+extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec);
+extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec);
+extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec);
+extern void PRCMCC3200MCUInit(void);
+extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr);
+extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PRCM_H__
diff --git a/cc3200/hal/rom.h b/cc3200/hal/rom.h
new file mode 100644
index 0000000000..33a18b68fc
--- /dev/null
+++ b/cc3200/hal/rom.h
@@ -0,0 +1,2237 @@
+//*****************************************************************************
+//
+// rom.h
+//
+// Macros to facilitate calling functions in the ROM.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE ((unsigned long *)0x0000040C)
+#define ROM_VERSION (ROM_APITABLE[0])
+#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_PRCMTABLE ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_SPITABLE ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_CAMERATABLE ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_PINTABLE ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_UTILSTABLE ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[14]))
+#define ROM_HWSPINLOCKTABLE ((unsigned long *)(ROM_APITABLE[15]))
+#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[16]))
+#define ROM_AESTABLE ((unsigned long *)(ROM_APITABLE[17]))
+#define ROM_DESTABLE ((unsigned long *)(ROM_APITABLE[18]))
+#define ROM_SHAMD5TABLE ((unsigned long *)(ROM_APITABLE[19]))
+#define ROM_CRCTABLE ((unsigned long *)(ROM_APITABLE[20]))
+#define ROM_SDHOSTTABLE ((unsigned long *)(ROM_APITABLE[21]))
+#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[22]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntEnable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntMasterEnable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntMasterDisable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntDisable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPriorityGroupingSet \
+ ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPriorityGroupingGet \
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPrioritySet \
+ ((void (*)(unsigned long ulInterrupt, \
+ unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPriorityGet \
+ ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPendSet \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPendClear \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPriorityMaskSet \
+ ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntPriorityMaskGet \
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntRegister \
+ ((void (*)(unsigned long ulInterrupt, \
+ void (*pfnHandler)(void)))ROM_INTERRUPTTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntUnregister \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_IntVTableBaseSet \
+ ((void (*)(unsigned long ulVtableBase))ROM_INTERRUPTTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_TIMERTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerControlLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bInvert))ROM_TIMERTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerControlEvent \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulEvent))ROM_TIMERTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerControlStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bStall))ROM_TIMERTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerPrescaleSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerPrescaleGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerPrescaleMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerPrescaleMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerLoadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerLoadGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerValueGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ void (*pfnHandler)(void)))ROM_TIMERTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerIntUnregister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_TIMERTABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_TimerIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[20])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTParityModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulParity))ROM_UARTTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTParityModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTFIFOLevelSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulRxLevel))ROM_UARTTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTFIFOLevelGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulTxLevel, \
+ unsigned long *pulRxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long ulBaud, \
+ unsigned long ulConfig))ROM_UARTTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTConfigGetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long *pulBaud, \
+ unsigned long *pulConfig))ROM_UARTTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTDisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTFIFOEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTFIFODisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTCharsAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTCharGetNonBlocking \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTCharGet \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTCharPutNonBlocking \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTCharPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTBreakCtl \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void(*pfnHandler)(void)))ROM_UARTTABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[21])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_UARTTABLE[22])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[23])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[24])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[25])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTRxErrorGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[26])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTRxErrorClear \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[27])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTModemControlSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulControl))ROM_UARTTABLE[28])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTModemControlClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulControl))ROM_UARTTABLE[29])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTModemControlGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[30])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTModemStatusGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[31])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTFlowControlSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_UARTTABLE[32])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTFlowControlGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[33])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTTxIntModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_UARTTABLE[34])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_UARTTxIntModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[35])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the uDMA API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelTransferSet \
+ ((void (*)(unsigned long ulChannelStructIndex, \
+ unsigned long ulMode, \
+ void *pvSrcAddr, \
+ void *pvDstAddr, \
+ unsigned long ulTransferSize))ROM_UDMATABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAEnable \
+ ((void (*)(void))ROM_UDMATABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMADisable \
+ ((void (*)(void))ROM_UDMATABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAErrorStatusGet \
+ ((unsigned long (*)(void))ROM_UDMATABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAErrorStatusClear \
+ ((void (*)(void))ROM_UDMATABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelEnable \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelDisable \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelIsEnabled \
+ ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAControlBaseSet \
+ ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAControlBaseGet \
+ ((void * (*)(void))ROM_UDMATABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelRequest \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelAttributeEnable \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned long ulAttr))ROM_UDMATABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelAttributeDisable \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned long ulAttr))ROM_UDMATABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelAttributeGet \
+ ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelControlSet \
+ ((void (*)(unsigned long ulChannelStructIndex, \
+ unsigned long ulControl))ROM_UDMATABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelSizeGet \
+ ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelModeGet \
+ ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAIntStatus \
+ ((unsigned long (*)(void))ROM_UDMATABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAIntClear \
+ ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAControlAlternateBaseGet \
+ ((void * (*)(void))ROM_UDMATABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelScatterGatherSet \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned ulTaskCount, \
+ void *pvTaskList, \
+ unsigned long ulIsPeriphSG))ROM_UDMATABLE[20])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAChannelAssign \
+ ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[21])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAIntRegister \
+ ((void (*)(unsigned long ulIntChannel, \
+ void (*pfnHandler)(void)))ROM_UDMATABLE[22])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_uDMAIntUnregister \
+ ((void (*)(unsigned long ulIntChannel))ROM_UDMATABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogIntClear \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogRunning \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogLock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogUnlock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogLockState \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogReloadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulLoadVal))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogReloadGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogValueGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogStallEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogStallDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void(*pfnHandler)(void)))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_WatchdogIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CIntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(pfnHandler)(void)))ROM_I2CTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CIntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CTxFIFOConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CTxFIFOFlush \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CRxFIFOConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CRxFIFOFlush \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CFIFOStatus \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CFIFODataPut \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CFIFODataPutNonBlocking \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CFIFODataGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CFIFODataGetNonBlocking \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ uint8_t *pui8Data))ROM_I2CTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterBurstLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Length))ROM_I2CTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterBurstCountGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterGlitchFilterConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveFIFOEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveFIFODisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterBusBusy \
+ ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterBusy \
+ ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterControl \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Cmd))ROM_I2CTABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterDataGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterDataPut \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[20])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[21])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[22])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterErr \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntClear \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[24])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[25])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[26])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntStatus \
+ ((bool (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[27])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntEnableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[28])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntDisableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[29])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntStatusEx \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[30])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterIntClearEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[31])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterTimeoutSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Value))ROM_I2CTABLE[32])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveACKOverride \
+ ((void (*)(uint32_t ui32Base, \
+ bool bEnable))ROM_I2CTABLE[33])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveACKValueSet \
+ ((void (*)(uint32_t ui32Base, \
+ bool bACK))ROM_I2CTABLE[34])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterLineStateGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[35])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterSlaveAddrSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8SlaveAddr, \
+ bool bReceive))ROM_I2CTABLE[36])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveDataGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[37])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveDataPut \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[38])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[39])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveInit \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8SlaveAddr))ROM_I2CTABLE[41])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveAddressSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8AddrNum, \
+ uint8_t ui8SlaveAddr))ROM_I2CTABLE[42])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntClear \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[43])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[44])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[45])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntClearEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[46])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntDisableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[47])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntEnableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[48])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntStatus \
+ ((bool (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[49])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveIntStatusEx \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[50])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CSlaveStatus \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[51])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2CMasterInitExpClk \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32I2CClk, \
+ bool bFast))ROM_I2CTABLE[52])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SPI API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIEnable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIDisable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIReset \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSPIClk, \
+ unsigned long ulBitRate, \
+ unsigned long ulMode, \
+ unsigned long ulSubMode, \
+ unsigned long ulConfig))ROM_SPITABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long * pulData))ROM_SPITABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SPITABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SPITABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SPITABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIFIFOEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIFIFODisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIFIFOLevelSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulRxLevel))ROM_SPITABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIFIFOLevelGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulTxLevel, \
+ unsigned long *pulRxLevel))ROM_SPITABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIWordCountSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulWordCount))ROM_SPITABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void(*pfnHandler)(void)))ROM_SPITABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SPITABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SPITABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_SPITABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SPITABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIDmaEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPIDmaDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[20])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPICSEnable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[21])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPICSDisable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[22])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SPITransfer \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *ucDout, \
+ unsigned char *ucDin, \
+ unsigned long ulSize, \
+ unsigned long ulFlags))ROM_SPITABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CAM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraReset \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraParamsConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulHSPol, \
+ unsigned long ulVSPol, \
+ unsigned long ulFlags))ROM_CAMERATABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraXClkConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulCamClkIn, \
+ unsigned long ulXClk))ROM_CAMERATABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraXClkSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char bXClkFlags))ROM_CAMERATABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraDMAEnable \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraDMADisable \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraThresholdSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulThreshold))ROM_CAMERATABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void (*pfnHandler)(void)))ROM_CAMERATABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CAMERATABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CAMERATABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_CAMERATABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CAMERATABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraCaptureStop \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bImmediate))ROM_CAMERATABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraCaptureStart \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CameraBufferRead \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pBuffer, \
+ unsigned char ucSize))ROM_CAMERATABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the FLASH API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashDisable \
+ ((void (*)(void))ROM_FLASHTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashErase \
+ ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashMassErase \
+ ((long (*)(void))ROM_FLASHTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashMassEraseNonBlocking \
+ ((void (*)(void))ROM_FLASHTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashEraseNonBlocking \
+ ((void (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashProgram \
+ ((long (*)(unsigned long *pulData, \
+ unsigned long ulAddress, \
+ unsigned long ulCount))ROM_FLASHTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashProgramNonBlocking \
+ ((long (*)(unsigned long *pulData, \
+ unsigned long ulAddress, \
+ unsigned long ulCount))ROM_FLASHTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashIntRegister \
+ ((void (*)(void (*pfnHandler)(void)))ROM_FLASHTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashIntUnregister \
+ ((void (*)(void))ROM_FLASHTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_FlashProtectGet \
+ ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Pin API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinModeSet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinDirModeSet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinIO))ROM_PINTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinDirModeGet \
+ ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinModeGet \
+ ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinConfigGet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long *pulPinStrength, \
+ unsigned long *pulPinType))ROM_PINTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinConfigSet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinStrength, \
+ unsigned long ulPinType))ROM_PINTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeUART \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeI2C \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeSPI \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeI2S \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeTimer \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeCamera \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeGPIO \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode, \
+ tBoolean bOpenDrain))ROM_PINTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeADC \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PinTypeSDHost \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SYSTICK API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickIntRegister \
+ ((void (*)(void (*pfnHandler)(void)))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickIntUnregister \
+ ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickIntEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickIntDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickPeriodSet \
+ ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickPeriodGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SysTickValueGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[8])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UTILS API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_UtilsDelay \
+ ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2S API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_I2STABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long ulData))ROM_I2STABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long ulData))ROM_I2STABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long *pulData))ROM_I2STABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long *pulData))ROM_I2STABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulI2SClk, \
+ unsigned long ulBitClk, \
+ unsigned long ulConfig))ROM_I2STABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2STxFIFOEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulWordsPerTransfer))ROM_I2STABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2STxFIFODisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SRxFIFOEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRxLevel, \
+ unsigned long ulWordsPerTransfer))ROM_I2STABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SRxFIFODisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2STxFIFOStatusGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SRxFIFOStatusGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SSerializerConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long ulSerMode, \
+ unsigned long ulInActState))ROM_I2STABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void (*pfnHandler)(void)))ROM_I2STABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_I2SIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[19])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIODirModeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulPinIO))ROM_GPIOTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIODirModeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntTypeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulIntType))ROM_GPIOTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIODMATriggerEnable \
+ ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIODMATriggerDisable \
+ ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntTypeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntEnable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned long ulIntFlags))ROM_GPIOTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntDisable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned long ulIntFlags))ROM_GPIOTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntStatus \
+ ((long (*)(unsigned long ulPort, \
+ tBoolean bMasked))ROM_GPIOTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntClear \
+ ((void (*)(unsigned long ulPort, \
+ unsigned long ulIntFlags))ROM_GPIOTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntRegister \
+ ((void (*)(unsigned long ulPort, \
+ void (*pfnIntHandler)(void)))ROM_GPIOTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOIntUnregister \
+ ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOPinRead \
+ ((long (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_GPIOPinWrite \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned char ucVal))ROM_GPIOTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the AES API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_AESTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESKey1Set \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key, \
+ uint32_t ui32Keysize))ROM_AESTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESKey2Set \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key, \
+ uint32_t ui32Keysize))ROM_AESTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESKey3Set \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key))ROM_AESTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESIVSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8IVdata))ROM_AESTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESTagRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8TagData))ROM_AESTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint64_t ui64Length))ROM_AESTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESAuthDataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Length))ROM_AESTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataReadNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_AESTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_AESTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataWriteNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_AESTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_AESTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t *pui8Dest, \
+ uint32_t ui32Length))ROM_AESTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataMAC \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint32_t ui32Length, \
+ uint8_t *pui8Tag))ROM_AESTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDataProcessAE \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t *pui8Dest, \
+ uint32_t ui32Length, \
+ uint8_t *pui8AuthSrc, \
+ uint32_t ui32AuthLength, \
+ uint8_t *pui8Tag))ROM_AESTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESIntStatus \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_AESTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESIntEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_AESTABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESIntDisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_AESTABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESIntClear \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_AESTABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESIntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(*pfnHandler)(void)))ROM_AESTABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESIntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDMAEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_AESTABLE[21])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_AESDMADisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_AESTABLE[22])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the DES API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_DESTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDataRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_DESTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDataReadNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_DESTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDataProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t *pui8Dest, \
+ uint32_t ui32Length))ROM_DESTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_DESTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDataWriteNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_DESTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDMADisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_DESTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDMAEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_DESTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESIntClear \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_DESTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESIntDisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_DESTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESIntEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_DESTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESIntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(*pfnHandler)(void)))ROM_DESTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESIntStatus \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_DESTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESIntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_DESTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESIVSet \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8IVdata))ROM_DESTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESKeySet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key))ROM_DESTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_DESDataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Length))ROM_DESTABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SHAMD5 API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5ConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Mode))ROM_SHAMD5TABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5DataProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8DataSrc, \
+ uint32_t ui32DataLength, \
+ uint8_t *pui8HashResult))ROM_SHAMD5TABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5DataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5DataWriteNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5DMADisable \
+ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5DMAEnable \
+ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5DataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Length))ROM_SHAMD5TABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5HMACKeySet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5HMACPPKeyGenerate \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key, \
+ uint8_t *pui8PPKey))ROM_SHAMD5TABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5HMACPPKeySet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5HMACProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8DataSrc, \
+ uint32_t ui32DataLength, \
+ uint8_t *pui8HashResult))ROM_SHAMD5TABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5IntClear \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5IntDisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5IntEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5IntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(*pfnHandler)(void)))ROM_SHAMD5TABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5IntStatus \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_SHAMD5TABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5IntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SHAMD5ResultRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest))ROM_SHAMD5TABLE[17])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CRC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_CRCConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32CRCConfig))ROM_CRCTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CRCDataProcess \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ void *puiDataIn, \
+ uint32_t ui32DataLength, \
+ uint32_t ui32Config))ROM_CRCTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CRCDataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Data))ROM_CRCTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CRCResultRead \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_CRCTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_CRCSeedSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Seed))ROM_CRCTABLE[4])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SDHOST API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostCmdReset \
+ ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostInit \
+ ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostCmdSend \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulCmd, \
+ unsigned ulArg))ROM_SDHOSTTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void (*pfnHandler)(void)))ROM_SDHOSTTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SDHOSTTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SDHOSTTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SDHOSTTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostRespStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostRespGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRespnse[4]))ROM_SDHOSTTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostBlockSizeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned short ulBlkSize))ROM_SDHOSTTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostBlockCountSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned short ulBlkCount))ROM_SDHOSTTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostDataNonBlockingWrite \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SDHOSTTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostDataNonBlockingRead \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SDHOSTTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostDataWrite \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SDHOSTTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostDataRead \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *ulData))ROM_SDHOSTTABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_SDHostSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSDHostClk, \
+ unsigned long ulCardClk))ROM_SDHOSTTABLE[17])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PRCM API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMMCUReset \
+ ((void (*)(tBoolean bIncludeSubsystem))ROM_PRCMTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMSysResetCauseGet \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMPeripheralClkEnable \
+ ((void (*)(unsigned long ulPeripheral, \
+ unsigned long ulClkFlags))ROM_PRCMTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMPeripheralClkDisable \
+ ((void (*)(unsigned long ulPeripheral, \
+ unsigned long ulClkFlags))ROM_PRCMTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMPeripheralReset \
+ ((void (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMPeripheralStatusGet \
+ ((tBoolean (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMI2SClockFreqSet \
+ ((void (*)(unsigned long ulI2CClkFreq))ROM_PRCMTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMPeripheralClockGet \
+ ((unsigned long (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMSleepEnter \
+ ((void (*)(void))ROM_PRCMTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMDeepSleepEnter \
+ ((void (*)(void))ROM_PRCMTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMSRAMRetentionEnable \
+ ((void (*)(unsigned long ulSramColSel, \
+ unsigned long ulFlags))ROM_PRCMTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMSRAMRetentionDisable \
+ ((void (*)(unsigned long ulSramColSel, \
+ unsigned long ulFlags))ROM_PRCMTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMLPDSEnter \
+ ((void (*)(void))ROM_PRCMTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMLPDSIntervalSet \
+ ((void (*)(unsigned long ulTicks))ROM_PRCMTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMLPDSWakeupSourceEnable \
+ ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMLPDSWakeupCauseGet \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMLPDSWakeUpGPIOSelect \
+ ((void (*)(unsigned long ulGPIOPin, \
+ unsigned long ulType))ROM_PRCMTABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMLPDSWakeupSourceDisable \
+ ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMHibernateEnter \
+ ((void (*)(void))ROM_PRCMTABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMHibernateWakeupSourceEnable \
+ ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[20])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMHibernateWakeupCauseGet \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[21])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMHibernateWakeUpGPIOSelect \
+ ((void (*)(unsigned long ulMultiGPIOBitMap, \
+ unsigned long ulType))ROM_PRCMTABLE[22])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMHibernateWakeupSourceDisable \
+ ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[23])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMHibernateIntervalSet \
+ ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[24])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMSlowClkCtrGet \
+ ((unsigned long long (*)(void))ROM_PRCMTABLE[25])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMSlowClkCtrMatchSet \
+ ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[26])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMSlowClkCtrMatchGet \
+ ((unsigned long long (*)(void))ROM_PRCMTABLE[27])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMOCRRegisterWrite \
+ ((void (*)(unsigned char ucIndex, \
+ unsigned long ulRegValue))ROM_PRCMTABLE[28])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMOCRRegisterRead \
+ ((unsigned long (*)(unsigned char ucIndex))ROM_PRCMTABLE[29])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMIntRegister \
+ ((void (*)(void (*pfnHandler)(void)))ROM_PRCMTABLE[30])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMIntUnregister \
+ ((void (*)(void))ROM_PRCMTABLE[31])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[32])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[33])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMIntStatus \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[34])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMRTCInUseSet \
+ ((void (*)(void))ROM_PRCMTABLE[35])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMRTCInUseGet \
+ ((tBoolean (*)(void))ROM_PRCMTABLE[36])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMRTCSet \
+ ((void (*)(unsigned long ulSecs, \
+ unsigned short usMsec))ROM_PRCMTABLE[37])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMRTCGet \
+ ((void (*)(unsigned long *ulSecs, \
+ unsigned short *usMsec))ROM_PRCMTABLE[38])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMRTCMatchSet \
+ ((void (*)(unsigned long ulSecs, \
+ unsigned short usMsec))ROM_PRCMTABLE[39])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMRTCMatchGet \
+ ((void (*)(unsigned long *ulSecs, \
+ unsigned short *usMsec))ROM_PRCMTABLE[40])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_PRCMLPDSRestoreInfoSet \
+ ((void (*)(unsigned long ulRestoreSP, \
+ unsigned long ulRestorePC))ROM_PRCMTABLE[41])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the HWSPINLOCK API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_HwSpinLockAcquire \
+ ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_HwSpinLockTryAcquire \
+ ((int32_t (*)(uint32_t ui32LockID, \
+ uint32_t ui32Retry))ROM_HWSPINLOCKTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_HwSpinLockRelease \
+ ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_HwSpinLockTest \
+ ((uint32_t (*)(uint32_t ui32LockID, \
+ bool bCurrentStatus))ROM_HWSPINLOCKTABLE[3])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCEnable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[0])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCDisable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[1])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCChannelEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[2])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCChannelDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[3])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ void (*pfnHandler)(void)))ROM_ADCTABLE[4])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCIntUnregister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[5])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulIntFlags))ROM_ADCTABLE[6])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulIntFlags))ROM_ADCTABLE[7])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[8])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulIntFlags))ROM_ADCTABLE[9])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[10])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[11])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCChannelGainSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned char ucGain))ROM_ADCTABLE[12])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCChannleGainGet \
+ ((unsigned char (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[13])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCTimerConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulValue))ROM_ADCTABLE[14])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCTimerEnable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[15])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCTimerDisable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[16])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCTimerReset \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[17])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCTimerValueGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[18])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCFIFOLvlGet \
+ ((unsigned char (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[19])
+#endif
+#if defined(TARGET_IS_CC3200)
+#define ROM_ADCFIFORead \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[20])
+#endif
+
+#endif // __ROM_H__
diff --git a/cc3200/hal/rom_map.h b/cc3200/hal/rom_map.h
new file mode 100644
index 0000000000..86a6c75fca
--- /dev/null
+++ b/cc3200/hal/rom_map.h
@@ -0,0 +1,3177 @@
+//*****************************************************************************
+//
+// rom_map.h
+//
+// Macros to facilitate calling functions in the ROM when they are
+// available and in flash otherwise.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND.
+//
+//*****************************************************************************
+
+#ifndef __ROM_MAP_H__
+#define __ROM_MAP_H__
+#ifndef DEBUG
+#include "rom.h"
+#endif
+#include "rom_patch.h"
+
+//*****************************************************************************
+//
+// Macros for the Interrupt API.
+//
+//*****************************************************************************
+#ifdef ROM_IntEnable
+#define MAP_IntEnable \
+ ROM_IntEnable
+#else
+#define MAP_IntEnable \
+ IntEnable
+#endif
+#ifdef ROM_IntMasterEnable
+#define MAP_IntMasterEnable \
+ ROM_IntMasterEnable
+#else
+#define MAP_IntMasterEnable \
+ IntMasterEnable
+#endif
+#ifdef ROM_IntMasterDisable
+#define MAP_IntMasterDisable \
+ ROM_IntMasterDisable
+#else
+#define MAP_IntMasterDisable \
+ IntMasterDisable
+#endif
+#ifdef ROM_IntDisable
+#define MAP_IntDisable \
+ ROM_IntDisable
+#else
+#define MAP_IntDisable \
+ IntDisable
+#endif
+#ifdef ROM_IntPriorityGroupingSet
+#define MAP_IntPriorityGroupingSet \
+ ROM_IntPriorityGroupingSet
+#else
+#define MAP_IntPriorityGroupingSet \
+ IntPriorityGroupingSet
+#endif
+#ifdef ROM_IntPriorityGroupingGet
+#define MAP_IntPriorityGroupingGet \
+ ROM_IntPriorityGroupingGet
+#else
+#define MAP_IntPriorityGroupingGet \
+ IntPriorityGroupingGet
+#endif
+#ifdef ROM_IntPrioritySet
+#define MAP_IntPrioritySet \
+ ROM_IntPrioritySet
+#else
+#define MAP_IntPrioritySet \
+ IntPrioritySet
+#endif
+#ifdef ROM_IntPriorityGet
+#define MAP_IntPriorityGet \
+ ROM_IntPriorityGet
+#else
+#define MAP_IntPriorityGet \
+ IntPriorityGet
+#endif
+#ifdef ROM_IntPendSet
+#define MAP_IntPendSet \
+ ROM_IntPendSet
+#else
+#define MAP_IntPendSet \
+ IntPendSet
+#endif
+#ifdef ROM_IntPendClear
+#define MAP_IntPendClear \
+ ROM_IntPendClear
+#else
+#define MAP_IntPendClear \
+ IntPendClear
+#endif
+#ifdef ROM_IntPriorityMaskSet
+#define MAP_IntPriorityMaskSet \
+ ROM_IntPriorityMaskSet
+#else
+#define MAP_IntPriorityMaskSet \
+ IntPriorityMaskSet
+#endif
+#ifdef ROM_IntPriorityMaskGet
+#define MAP_IntPriorityMaskGet \
+ ROM_IntPriorityMaskGet
+#else
+#define MAP_IntPriorityMaskGet \
+ IntPriorityMaskGet
+#endif
+#ifdef ROM_IntRegister
+#define MAP_IntRegister \
+ ROM_IntRegister
+#else
+#define MAP_IntRegister \
+ IntRegister
+#endif
+#ifdef ROM_IntUnregister
+#define MAP_IntUnregister \
+ ROM_IntUnregister
+#else
+#define MAP_IntUnregister \
+ IntUnregister
+#endif
+#ifdef ROM_IntVTableBaseSet
+#define MAP_IntVTableBaseSet \
+ ROM_IntVTableBaseSet
+#else
+#define MAP_IntVTableBaseSet \
+ IntVTableBaseSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer API.
+//
+//*****************************************************************************
+#ifdef ROM_TimerEnable
+#define MAP_TimerEnable \
+ ROM_TimerEnable
+#else
+#define MAP_TimerEnable \
+ TimerEnable
+#endif
+#ifdef ROM_TimerDisable
+#define MAP_TimerDisable \
+ ROM_TimerDisable
+#else
+#define MAP_TimerDisable \
+ TimerDisable
+#endif
+#ifdef ROM_TimerConfigure
+#define MAP_TimerConfigure \
+ ROM_TimerConfigure
+#else
+#define MAP_TimerConfigure \
+ TimerConfigure
+#endif
+#ifdef ROM_TimerControlLevel
+#define MAP_TimerControlLevel \
+ ROM_TimerControlLevel
+#else
+#define MAP_TimerControlLevel \
+ TimerControlLevel
+#endif
+#ifdef ROM_TimerControlEvent
+#define MAP_TimerControlEvent \
+ ROM_TimerControlEvent
+#else
+#define MAP_TimerControlEvent \
+ TimerControlEvent
+#endif
+#ifdef ROM_TimerControlStall
+#define MAP_TimerControlStall \
+ ROM_TimerControlStall
+#else
+#define MAP_TimerControlStall \
+ TimerControlStall
+#endif
+#ifdef ROM_TimerPrescaleSet
+#define MAP_TimerPrescaleSet \
+ ROM_TimerPrescaleSet
+#else
+#define MAP_TimerPrescaleSet \
+ TimerPrescaleSet
+#endif
+#ifdef ROM_TimerPrescaleGet
+#define MAP_TimerPrescaleGet \
+ ROM_TimerPrescaleGet
+#else
+#define MAP_TimerPrescaleGet \
+ TimerPrescaleGet
+#endif
+#ifdef ROM_TimerPrescaleMatchSet
+#define MAP_TimerPrescaleMatchSet \
+ ROM_TimerPrescaleMatchSet
+#else
+#define MAP_TimerPrescaleMatchSet \
+ TimerPrescaleMatchSet
+#endif
+#ifdef ROM_TimerPrescaleMatchGet
+#define MAP_TimerPrescaleMatchGet \
+ ROM_TimerPrescaleMatchGet
+#else
+#define MAP_TimerPrescaleMatchGet \
+ TimerPrescaleMatchGet
+#endif
+#ifdef ROM_TimerLoadSet
+#define MAP_TimerLoadSet \
+ ROM_TimerLoadSet
+#else
+#define MAP_TimerLoadSet \
+ TimerLoadSet
+#endif
+#ifdef ROM_TimerLoadGet
+#define MAP_TimerLoadGet \
+ ROM_TimerLoadGet
+#else
+#define MAP_TimerLoadGet \
+ TimerLoadGet
+#endif
+#ifdef ROM_TimerValueGet
+#define MAP_TimerValueGet \
+ ROM_TimerValueGet
+#else
+#define MAP_TimerValueGet \
+ TimerValueGet
+#endif
+#ifdef ROM_TimerMatchSet
+#define MAP_TimerMatchSet \
+ ROM_TimerMatchSet
+#else
+#define MAP_TimerMatchSet \
+ TimerMatchSet
+#endif
+#ifdef ROM_TimerMatchGet
+#define MAP_TimerMatchGet \
+ ROM_TimerMatchGet
+#else
+#define MAP_TimerMatchGet \
+ TimerMatchGet
+#endif
+#ifdef ROM_TimerIntRegister
+#define MAP_TimerIntRegister \
+ ROM_TimerIntRegister
+#else
+#define MAP_TimerIntRegister \
+ TimerIntRegister
+#endif
+#ifdef ROM_TimerIntUnregister
+#define MAP_TimerIntUnregister \
+ ROM_TimerIntUnregister
+#else
+#define MAP_TimerIntUnregister \
+ TimerIntUnregister
+#endif
+#ifdef ROM_TimerIntEnable
+#define MAP_TimerIntEnable \
+ ROM_TimerIntEnable
+#else
+#define MAP_TimerIntEnable \
+ TimerIntEnable
+#endif
+#ifdef ROM_TimerIntDisable
+#define MAP_TimerIntDisable \
+ ROM_TimerIntDisable
+#else
+#define MAP_TimerIntDisable \
+ TimerIntDisable
+#endif
+#ifdef ROM_TimerIntStatus
+#define MAP_TimerIntStatus \
+ ROM_TimerIntStatus
+#else
+#define MAP_TimerIntStatus \
+ TimerIntStatus
+#endif
+#ifdef ROM_TimerIntClear
+#define MAP_TimerIntClear \
+ ROM_TimerIntClear
+#else
+#define MAP_TimerIntClear \
+ TimerIntClear
+#endif
+#ifdef ROM_TimerDMAEventSet
+#define MAP_TimerDMAEventSet \
+ ROM_TimerDMAEventSet
+#else
+#define MAP_TimerDMAEventSet \
+ TimerDMAEventSet
+#endif
+#ifdef ROM_TimerDMAEventGet
+#define MAP_TimerDMAEventGet \
+ ROM_TimerDMAEventGet
+#else
+#define MAP_TimerDMAEventGet \
+ TimerDMAEventGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UART API.
+//
+//*****************************************************************************
+#ifdef ROM_UARTParityModeSet
+#define MAP_UARTParityModeSet \
+ ROM_UARTParityModeSet
+#else
+#define MAP_UARTParityModeSet \
+ UARTParityModeSet
+#endif
+#ifdef ROM_UARTParityModeGet
+#define MAP_UARTParityModeGet \
+ ROM_UARTParityModeGet
+#else
+#define MAP_UARTParityModeGet \
+ UARTParityModeGet
+#endif
+#ifdef ROM_UARTFIFOLevelSet
+#define MAP_UARTFIFOLevelSet \
+ ROM_UARTFIFOLevelSet
+#else
+#define MAP_UARTFIFOLevelSet \
+ UARTFIFOLevelSet
+#endif
+#ifdef ROM_UARTFIFOLevelGet
+#define MAP_UARTFIFOLevelGet \
+ ROM_UARTFIFOLevelGet
+#else
+#define MAP_UARTFIFOLevelGet \
+ UARTFIFOLevelGet
+#endif
+#ifdef ROM_UARTConfigSetExpClk
+#define MAP_UARTConfigSetExpClk \
+ ROM_UARTConfigSetExpClk
+#else
+#define MAP_UARTConfigSetExpClk \
+ UARTConfigSetExpClk
+#endif
+#ifdef ROM_UARTConfigGetExpClk
+#define MAP_UARTConfigGetExpClk \
+ ROM_UARTConfigGetExpClk
+#else
+#define MAP_UARTConfigGetExpClk \
+ UARTConfigGetExpClk
+#endif
+#ifdef ROM_UARTEnable
+#define MAP_UARTEnable \
+ ROM_UARTEnable
+#else
+#define MAP_UARTEnable \
+ UARTEnable
+#endif
+#ifdef ROM_UARTDisable
+#define MAP_UARTDisable \
+ ROM_UARTDisable
+#else
+#define MAP_UARTDisable \
+ UARTDisable
+#endif
+#ifdef ROM_UARTFIFOEnable
+#define MAP_UARTFIFOEnable \
+ ROM_UARTFIFOEnable
+#else
+#define MAP_UARTFIFOEnable \
+ UARTFIFOEnable
+#endif
+#ifdef ROM_UARTFIFODisable
+#define MAP_UARTFIFODisable \
+ ROM_UARTFIFODisable
+#else
+#define MAP_UARTFIFODisable \
+ UARTFIFODisable
+#endif
+#ifdef ROM_UARTCharsAvail
+#define MAP_UARTCharsAvail \
+ ROM_UARTCharsAvail
+#else
+#define MAP_UARTCharsAvail \
+ UARTCharsAvail
+#endif
+#ifdef ROM_UARTSpaceAvail
+#define MAP_UARTSpaceAvail \
+ ROM_UARTSpaceAvail
+#else
+#define MAP_UARTSpaceAvail \
+ UARTSpaceAvail
+#endif
+#ifdef ROM_UARTCharGetNonBlocking
+#define MAP_UARTCharGetNonBlocking \
+ ROM_UARTCharGetNonBlocking
+#else
+#define MAP_UARTCharGetNonBlocking \
+ UARTCharGetNonBlocking
+#endif
+#ifdef ROM_UARTCharGet
+#define MAP_UARTCharGet \
+ ROM_UARTCharGet
+#else
+#define MAP_UARTCharGet \
+ UARTCharGet
+#endif
+#ifdef ROM_UARTCharPutNonBlocking
+#define MAP_UARTCharPutNonBlocking \
+ ROM_UARTCharPutNonBlocking
+#else
+#define MAP_UARTCharPutNonBlocking \
+ UARTCharPutNonBlocking
+#endif
+#ifdef ROM_UARTCharPut
+#define MAP_UARTCharPut \
+ ROM_UARTCharPut
+#else
+#define MAP_UARTCharPut \
+ UARTCharPut
+#endif
+#ifdef ROM_UARTBreakCtl
+#define MAP_UARTBreakCtl \
+ ROM_UARTBreakCtl
+#else
+#define MAP_UARTBreakCtl \
+ UARTBreakCtl
+#endif
+#ifdef ROM_UARTBusy
+#define MAP_UARTBusy \
+ ROM_UARTBusy
+#else
+#define MAP_UARTBusy \
+ UARTBusy
+#endif
+#ifdef ROM_UARTIntRegister
+#define MAP_UARTIntRegister \
+ ROM_UARTIntRegister
+#else
+#define MAP_UARTIntRegister \
+ UARTIntRegister
+#endif
+#ifdef ROM_UARTIntUnregister
+#define MAP_UARTIntUnregister \
+ ROM_UARTIntUnregister
+#else
+#define MAP_UARTIntUnregister \
+ UARTIntUnregister
+#endif
+#ifdef ROM_UARTIntEnable
+#define MAP_UARTIntEnable \
+ ROM_UARTIntEnable
+#else
+#define MAP_UARTIntEnable \
+ UARTIntEnable
+#endif
+#ifdef ROM_UARTIntDisable
+#define MAP_UARTIntDisable \
+ ROM_UARTIntDisable
+#else
+#define MAP_UARTIntDisable \
+ UARTIntDisable
+#endif
+#ifdef ROM_UARTIntStatus
+#define MAP_UARTIntStatus \
+ ROM_UARTIntStatus
+#else
+#define MAP_UARTIntStatus \
+ UARTIntStatus
+#endif
+#ifdef ROM_UARTIntClear
+#define MAP_UARTIntClear \
+ ROM_UARTIntClear
+#else
+#define MAP_UARTIntClear \
+ UARTIntClear
+#endif
+#ifdef ROM_UARTDMAEnable
+#define MAP_UARTDMAEnable \
+ ROM_UARTDMAEnable
+#else
+#define MAP_UARTDMAEnable \
+ UARTDMAEnable
+#endif
+#ifdef ROM_UARTDMADisable
+#define MAP_UARTDMADisable \
+ ROM_UARTDMADisable
+#else
+#define MAP_UARTDMADisable \
+ UARTDMADisable
+#endif
+#ifdef ROM_UARTRxErrorGet
+#define MAP_UARTRxErrorGet \
+ ROM_UARTRxErrorGet
+#else
+#define MAP_UARTRxErrorGet \
+ UARTRxErrorGet
+#endif
+#ifdef ROM_UARTRxErrorClear
+#define MAP_UARTRxErrorClear \
+ ROM_UARTRxErrorClear
+#else
+#define MAP_UARTRxErrorClear \
+ UARTRxErrorClear
+#endif
+#ifdef ROM_UARTModemControlSet
+#define MAP_UARTModemControlSet \
+ ROM_UARTModemControlSet
+#else
+#define MAP_UARTModemControlSet \
+ UARTModemControlSet
+#endif
+#ifdef ROM_UARTModemControlClear
+#define MAP_UARTModemControlClear \
+ ROM_UARTModemControlClear
+#else
+#define MAP_UARTModemControlClear \
+ UARTModemControlClear
+#endif
+#ifdef ROM_UARTModemControlGet
+#define MAP_UARTModemControlGet \
+ ROM_UARTModemControlGet
+#else
+#define MAP_UARTModemControlGet \
+ UARTModemControlGet
+#endif
+#ifdef ROM_UARTModemStatusGet
+#define MAP_UARTModemStatusGet \
+ ROM_UARTModemStatusGet
+#else
+#define MAP_UARTModemStatusGet \
+ UARTModemStatusGet
+#endif
+#ifdef ROM_UARTFlowControlSet
+#define MAP_UARTFlowControlSet \
+ ROM_UARTFlowControlSet
+#else
+#define MAP_UARTFlowControlSet \
+ UARTFlowControlSet
+#endif
+#ifdef ROM_UARTFlowControlGet
+#define MAP_UARTFlowControlGet \
+ ROM_UARTFlowControlGet
+#else
+#define MAP_UARTFlowControlGet \
+ UARTFlowControlGet
+#endif
+#ifdef ROM_UARTTxIntModeSet
+#define MAP_UARTTxIntModeSet \
+ ROM_UARTTxIntModeSet
+#else
+#define MAP_UARTTxIntModeSet \
+ UARTTxIntModeSet
+#endif
+#ifdef ROM_UARTTxIntModeGet
+#define MAP_UARTTxIntModeGet \
+ ROM_UARTTxIntModeGet
+#else
+#define MAP_UARTTxIntModeGet \
+ UARTTxIntModeGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the uDMA API.
+//
+//*****************************************************************************
+#ifdef ROM_uDMAChannelTransferSet
+#define MAP_uDMAChannelTransferSet \
+ ROM_uDMAChannelTransferSet
+#else
+#define MAP_uDMAChannelTransferSet \
+ uDMAChannelTransferSet
+#endif
+#ifdef ROM_uDMAEnable
+#define MAP_uDMAEnable \
+ ROM_uDMAEnable
+#else
+#define MAP_uDMAEnable \
+ uDMAEnable
+#endif
+#ifdef ROM_uDMADisable
+#define MAP_uDMADisable \
+ ROM_uDMADisable
+#else
+#define MAP_uDMADisable \
+ uDMADisable
+#endif
+#ifdef ROM_uDMAErrorStatusGet
+#define MAP_uDMAErrorStatusGet \
+ ROM_uDMAErrorStatusGet
+#else
+#define MAP_uDMAErrorStatusGet \
+ uDMAErrorStatusGet
+#endif
+#ifdef ROM_uDMAErrorStatusClear
+#define MAP_uDMAErrorStatusClear \
+ ROM_uDMAErrorStatusClear
+#else
+#define MAP_uDMAErrorStatusClear \
+ uDMAErrorStatusClear
+#endif
+#ifdef ROM_uDMAChannelEnable
+#define MAP_uDMAChannelEnable \
+ ROM_uDMAChannelEnable
+#else
+#define MAP_uDMAChannelEnable \
+ uDMAChannelEnable
+#endif
+#ifdef ROM_uDMAChannelDisable
+#define MAP_uDMAChannelDisable \
+ ROM_uDMAChannelDisable
+#else
+#define MAP_uDMAChannelDisable \
+ uDMAChannelDisable
+#endif
+#ifdef ROM_uDMAChannelIsEnabled
+#define MAP_uDMAChannelIsEnabled \
+ ROM_uDMAChannelIsEnabled
+#else
+#define MAP_uDMAChannelIsEnabled \
+ uDMAChannelIsEnabled
+#endif
+#ifdef ROM_uDMAControlBaseSet
+#define MAP_uDMAControlBaseSet \
+ ROM_uDMAControlBaseSet
+#else
+#define MAP_uDMAControlBaseSet \
+ uDMAControlBaseSet
+#endif
+#ifdef ROM_uDMAControlBaseGet
+#define MAP_uDMAControlBaseGet \
+ ROM_uDMAControlBaseGet
+#else
+#define MAP_uDMAControlBaseGet \
+ uDMAControlBaseGet
+#endif
+#ifdef ROM_uDMAChannelRequest
+#define MAP_uDMAChannelRequest \
+ ROM_uDMAChannelRequest
+#else
+#define MAP_uDMAChannelRequest \
+ uDMAChannelRequest
+#endif
+#ifdef ROM_uDMAChannelAttributeEnable
+#define MAP_uDMAChannelAttributeEnable \
+ ROM_uDMAChannelAttributeEnable
+#else
+#define MAP_uDMAChannelAttributeEnable \
+ uDMAChannelAttributeEnable
+#endif
+#ifdef ROM_uDMAChannelAttributeDisable
+#define MAP_uDMAChannelAttributeDisable \
+ ROM_uDMAChannelAttributeDisable
+#else
+#define MAP_uDMAChannelAttributeDisable \
+ uDMAChannelAttributeDisable
+#endif
+#ifdef ROM_uDMAChannelAttributeGet
+#define MAP_uDMAChannelAttributeGet \
+ ROM_uDMAChannelAttributeGet
+#else
+#define MAP_uDMAChannelAttributeGet \
+ uDMAChannelAttributeGet
+#endif
+#ifdef ROM_uDMAChannelControlSet
+#define MAP_uDMAChannelControlSet \
+ ROM_uDMAChannelControlSet
+#else
+#define MAP_uDMAChannelControlSet \
+ uDMAChannelControlSet
+#endif
+#ifdef ROM_uDMAChannelSizeGet
+#define MAP_uDMAChannelSizeGet \
+ ROM_uDMAChannelSizeGet
+#else
+#define MAP_uDMAChannelSizeGet \
+ uDMAChannelSizeGet
+#endif
+#ifdef ROM_uDMAChannelModeGet
+#define MAP_uDMAChannelModeGet \
+ ROM_uDMAChannelModeGet
+#else
+#define MAP_uDMAChannelModeGet \
+ uDMAChannelModeGet
+#endif
+#ifdef ROM_uDMAIntStatus
+#define MAP_uDMAIntStatus \
+ ROM_uDMAIntStatus
+#else
+#define MAP_uDMAIntStatus \
+ uDMAIntStatus
+#endif
+#ifdef ROM_uDMAIntClear
+#define MAP_uDMAIntClear \
+ ROM_uDMAIntClear
+#else
+#define MAP_uDMAIntClear \
+ uDMAIntClear
+#endif
+#ifdef ROM_uDMAControlAlternateBaseGet
+#define MAP_uDMAControlAlternateBaseGet \
+ ROM_uDMAControlAlternateBaseGet
+#else
+#define MAP_uDMAControlAlternateBaseGet \
+ uDMAControlAlternateBaseGet
+#endif
+#ifdef ROM_uDMAChannelScatterGatherSet
+#define MAP_uDMAChannelScatterGatherSet \
+ ROM_uDMAChannelScatterGatherSet
+#else
+#define MAP_uDMAChannelScatterGatherSet \
+ uDMAChannelScatterGatherSet
+#endif
+#ifdef ROM_uDMAChannelAssign
+#define MAP_uDMAChannelAssign \
+ ROM_uDMAChannelAssign
+#else
+#define MAP_uDMAChannelAssign \
+ uDMAChannelAssign
+#endif
+#ifdef ROM_uDMAIntRegister
+#define MAP_uDMAIntRegister \
+ ROM_uDMAIntRegister
+#else
+#define MAP_uDMAIntRegister \
+ uDMAIntRegister
+#endif
+#ifdef ROM_uDMAIntUnregister
+#define MAP_uDMAIntUnregister \
+ ROM_uDMAIntUnregister
+#else
+#define MAP_uDMAIntUnregister \
+ uDMAIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Watchdog API.
+//
+//*****************************************************************************
+#ifdef ROM_WatchdogIntClear
+#define MAP_WatchdogIntClear \
+ ROM_WatchdogIntClear
+#else
+#define MAP_WatchdogIntClear \
+ WatchdogIntClear
+#endif
+#ifdef ROM_WatchdogRunning
+#define MAP_WatchdogRunning \
+ ROM_WatchdogRunning
+#else
+#define MAP_WatchdogRunning \
+ WatchdogRunning
+#endif
+#ifdef ROM_WatchdogEnable
+#define MAP_WatchdogEnable \
+ ROM_WatchdogEnable
+#else
+#define MAP_WatchdogEnable \
+ WatchdogEnable
+#endif
+#ifdef ROM_WatchdogLock
+#define MAP_WatchdogLock \
+ ROM_WatchdogLock
+#else
+#define MAP_WatchdogLock \
+ WatchdogLock
+#endif
+#ifdef ROM_WatchdogUnlock
+#define MAP_WatchdogUnlock \
+ ROM_WatchdogUnlock
+#else
+#define MAP_WatchdogUnlock \
+ WatchdogUnlock
+#endif
+#ifdef ROM_WatchdogLockState
+#define MAP_WatchdogLockState \
+ ROM_WatchdogLockState
+#else
+#define MAP_WatchdogLockState \
+ WatchdogLockState
+#endif
+#ifdef ROM_WatchdogReloadSet
+#define MAP_WatchdogReloadSet \
+ ROM_WatchdogReloadSet
+#else
+#define MAP_WatchdogReloadSet \
+ WatchdogReloadSet
+#endif
+#ifdef ROM_WatchdogReloadGet
+#define MAP_WatchdogReloadGet \
+ ROM_WatchdogReloadGet
+#else
+#define MAP_WatchdogReloadGet \
+ WatchdogReloadGet
+#endif
+#ifdef ROM_WatchdogValueGet
+#define MAP_WatchdogValueGet \
+ ROM_WatchdogValueGet
+#else
+#define MAP_WatchdogValueGet \
+ WatchdogValueGet
+#endif
+#ifdef ROM_WatchdogIntStatus
+#define MAP_WatchdogIntStatus \
+ ROM_WatchdogIntStatus
+#else
+#define MAP_WatchdogIntStatus \
+ WatchdogIntStatus
+#endif
+#ifdef ROM_WatchdogStallEnable
+#define MAP_WatchdogStallEnable \
+ ROM_WatchdogStallEnable
+#else
+#define MAP_WatchdogStallEnable \
+ WatchdogStallEnable
+#endif
+#ifdef ROM_WatchdogStallDisable
+#define MAP_WatchdogStallDisable \
+ ROM_WatchdogStallDisable
+#else
+#define MAP_WatchdogStallDisable \
+ WatchdogStallDisable
+#endif
+#ifdef ROM_WatchdogIntRegister
+#define MAP_WatchdogIntRegister \
+ ROM_WatchdogIntRegister
+#else
+#define MAP_WatchdogIntRegister \
+ WatchdogIntRegister
+#endif
+#ifdef ROM_WatchdogIntUnregister
+#define MAP_WatchdogIntUnregister \
+ ROM_WatchdogIntUnregister
+#else
+#define MAP_WatchdogIntUnregister \
+ WatchdogIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2C API.
+//
+//*****************************************************************************
+#ifdef ROM_I2CIntRegister
+#define MAP_I2CIntRegister \
+ ROM_I2CIntRegister
+#else
+#define MAP_I2CIntRegister \
+ I2CIntRegister
+#endif
+#ifdef ROM_I2CIntUnregister
+#define MAP_I2CIntUnregister \
+ ROM_I2CIntUnregister
+#else
+#define MAP_I2CIntUnregister \
+ I2CIntUnregister
+#endif
+#ifdef ROM_I2CTxFIFOConfigSet
+#define MAP_I2CTxFIFOConfigSet \
+ ROM_I2CTxFIFOConfigSet
+#else
+#define MAP_I2CTxFIFOConfigSet \
+ I2CTxFIFOConfigSet
+#endif
+#ifdef ROM_I2CTxFIFOFlush
+#define MAP_I2CTxFIFOFlush \
+ ROM_I2CTxFIFOFlush
+#else
+#define MAP_I2CTxFIFOFlush \
+ I2CTxFIFOFlush
+#endif
+#ifdef ROM_I2CRxFIFOConfigSet
+#define MAP_I2CRxFIFOConfigSet \
+ ROM_I2CRxFIFOConfigSet
+#else
+#define MAP_I2CRxFIFOConfigSet \
+ I2CRxFIFOConfigSet
+#endif
+#ifdef ROM_I2CRxFIFOFlush
+#define MAP_I2CRxFIFOFlush \
+ ROM_I2CRxFIFOFlush
+#else
+#define MAP_I2CRxFIFOFlush \
+ I2CRxFIFOFlush
+#endif
+#ifdef ROM_I2CFIFOStatus
+#define MAP_I2CFIFOStatus \
+ ROM_I2CFIFOStatus
+#else
+#define MAP_I2CFIFOStatus \
+ I2CFIFOStatus
+#endif
+#ifdef ROM_I2CFIFODataPut
+#define MAP_I2CFIFODataPut \
+ ROM_I2CFIFODataPut
+#else
+#define MAP_I2CFIFODataPut \
+ I2CFIFODataPut
+#endif
+#ifdef ROM_I2CFIFODataPutNonBlocking
+#define MAP_I2CFIFODataPutNonBlocking \
+ ROM_I2CFIFODataPutNonBlocking
+#else
+#define MAP_I2CFIFODataPutNonBlocking \
+ I2CFIFODataPutNonBlocking
+#endif
+#ifdef ROM_I2CFIFODataGet
+#define MAP_I2CFIFODataGet \
+ ROM_I2CFIFODataGet
+#else
+#define MAP_I2CFIFODataGet \
+ I2CFIFODataGet
+#endif
+#ifdef ROM_I2CFIFODataGetNonBlocking
+#define MAP_I2CFIFODataGetNonBlocking \
+ ROM_I2CFIFODataGetNonBlocking
+#else
+#define MAP_I2CFIFODataGetNonBlocking \
+ I2CFIFODataGetNonBlocking
+#endif
+#ifdef ROM_I2CMasterBurstLengthSet
+#define MAP_I2CMasterBurstLengthSet \
+ ROM_I2CMasterBurstLengthSet
+#else
+#define MAP_I2CMasterBurstLengthSet \
+ I2CMasterBurstLengthSet
+#endif
+#ifdef ROM_I2CMasterBurstCountGet
+#define MAP_I2CMasterBurstCountGet \
+ ROM_I2CMasterBurstCountGet
+#else
+#define MAP_I2CMasterBurstCountGet \
+ I2CMasterBurstCountGet
+#endif
+#ifdef ROM_I2CMasterGlitchFilterConfigSet
+#define MAP_I2CMasterGlitchFilterConfigSet \
+ ROM_I2CMasterGlitchFilterConfigSet
+#else
+#define MAP_I2CMasterGlitchFilterConfigSet \
+ I2CMasterGlitchFilterConfigSet
+#endif
+#ifdef ROM_I2CSlaveFIFOEnable
+#define MAP_I2CSlaveFIFOEnable \
+ ROM_I2CSlaveFIFOEnable
+#else
+#define MAP_I2CSlaveFIFOEnable \
+ I2CSlaveFIFOEnable
+#endif
+#ifdef ROM_I2CSlaveFIFODisable
+#define MAP_I2CSlaveFIFODisable \
+ ROM_I2CSlaveFIFODisable
+#else
+#define MAP_I2CSlaveFIFODisable \
+ I2CSlaveFIFODisable
+#endif
+#ifdef ROM_I2CMasterBusBusy
+#define MAP_I2CMasterBusBusy \
+ ROM_I2CMasterBusBusy
+#else
+#define MAP_I2CMasterBusBusy \
+ I2CMasterBusBusy
+#endif
+#ifdef ROM_I2CMasterBusy
+#define MAP_I2CMasterBusy \
+ ROM_I2CMasterBusy
+#else
+#define MAP_I2CMasterBusy \
+ I2CMasterBusy
+#endif
+#ifdef ROM_I2CMasterControl
+#define MAP_I2CMasterControl \
+ ROM_I2CMasterControl
+#else
+#define MAP_I2CMasterControl \
+ I2CMasterControl
+#endif
+#ifdef ROM_I2CMasterDataGet
+#define MAP_I2CMasterDataGet \
+ ROM_I2CMasterDataGet
+#else
+#define MAP_I2CMasterDataGet \
+ I2CMasterDataGet
+#endif
+#ifdef ROM_I2CMasterDataPut
+#define MAP_I2CMasterDataPut \
+ ROM_I2CMasterDataPut
+#else
+#define MAP_I2CMasterDataPut \
+ I2CMasterDataPut
+#endif
+#ifdef ROM_I2CMasterDisable
+#define MAP_I2CMasterDisable \
+ ROM_I2CMasterDisable
+#else
+#define MAP_I2CMasterDisable \
+ I2CMasterDisable
+#endif
+#ifdef ROM_I2CMasterEnable
+#define MAP_I2CMasterEnable \
+ ROM_I2CMasterEnable
+#else
+#define MAP_I2CMasterEnable \
+ I2CMasterEnable
+#endif
+#ifdef ROM_I2CMasterErr
+#define MAP_I2CMasterErr \
+ ROM_I2CMasterErr
+#else
+#define MAP_I2CMasterErr \
+ I2CMasterErr
+#endif
+#ifdef ROM_I2CMasterIntClear
+#define MAP_I2CMasterIntClear \
+ ROM_I2CMasterIntClear
+#else
+#define MAP_I2CMasterIntClear \
+ I2CMasterIntClear
+#endif
+#ifdef ROM_I2CMasterIntDisable
+#define MAP_I2CMasterIntDisable \
+ ROM_I2CMasterIntDisable
+#else
+#define MAP_I2CMasterIntDisable \
+ I2CMasterIntDisable
+#endif
+#ifdef ROM_I2CMasterIntEnable
+#define MAP_I2CMasterIntEnable \
+ ROM_I2CMasterIntEnable
+#else
+#define MAP_I2CMasterIntEnable \
+ I2CMasterIntEnable
+#endif
+#ifdef ROM_I2CMasterIntStatus
+#define MAP_I2CMasterIntStatus \
+ ROM_I2CMasterIntStatus
+#else
+#define MAP_I2CMasterIntStatus \
+ I2CMasterIntStatus
+#endif
+#ifdef ROM_I2CMasterIntEnableEx
+#define MAP_I2CMasterIntEnableEx \
+ ROM_I2CMasterIntEnableEx
+#else
+#define MAP_I2CMasterIntEnableEx \
+ I2CMasterIntEnableEx
+#endif
+#ifdef ROM_I2CMasterIntDisableEx
+#define MAP_I2CMasterIntDisableEx \
+ ROM_I2CMasterIntDisableEx
+#else
+#define MAP_I2CMasterIntDisableEx \
+ I2CMasterIntDisableEx
+#endif
+#ifdef ROM_I2CMasterIntStatusEx
+#define MAP_I2CMasterIntStatusEx \
+ ROM_I2CMasterIntStatusEx
+#else
+#define MAP_I2CMasterIntStatusEx \
+ I2CMasterIntStatusEx
+#endif
+#ifdef ROM_I2CMasterIntClearEx
+#define MAP_I2CMasterIntClearEx \
+ ROM_I2CMasterIntClearEx
+#else
+#define MAP_I2CMasterIntClearEx \
+ I2CMasterIntClearEx
+#endif
+#ifdef ROM_I2CMasterTimeoutSet
+#define MAP_I2CMasterTimeoutSet \
+ ROM_I2CMasterTimeoutSet
+#else
+#define MAP_I2CMasterTimeoutSet \
+ I2CMasterTimeoutSet
+#endif
+#ifdef ROM_I2CSlaveACKOverride
+#define MAP_I2CSlaveACKOverride \
+ ROM_I2CSlaveACKOverride
+#else
+#define MAP_I2CSlaveACKOverride \
+ I2CSlaveACKOverride
+#endif
+#ifdef ROM_I2CSlaveACKValueSet
+#define MAP_I2CSlaveACKValueSet \
+ ROM_I2CSlaveACKValueSet
+#else
+#define MAP_I2CSlaveACKValueSet \
+ I2CSlaveACKValueSet
+#endif
+#ifdef ROM_I2CMasterLineStateGet
+#define MAP_I2CMasterLineStateGet \
+ ROM_I2CMasterLineStateGet
+#else
+#define MAP_I2CMasterLineStateGet \
+ I2CMasterLineStateGet
+#endif
+#ifdef ROM_I2CMasterSlaveAddrSet
+#define MAP_I2CMasterSlaveAddrSet \
+ ROM_I2CMasterSlaveAddrSet
+#else
+#define MAP_I2CMasterSlaveAddrSet \
+ I2CMasterSlaveAddrSet
+#endif
+#ifdef ROM_I2CSlaveDataGet
+#define MAP_I2CSlaveDataGet \
+ ROM_I2CSlaveDataGet
+#else
+#define MAP_I2CSlaveDataGet \
+ I2CSlaveDataGet
+#endif
+#ifdef ROM_I2CSlaveDataPut
+#define MAP_I2CSlaveDataPut \
+ ROM_I2CSlaveDataPut
+#else
+#define MAP_I2CSlaveDataPut \
+ I2CSlaveDataPut
+#endif
+#ifdef ROM_I2CSlaveDisable
+#define MAP_I2CSlaveDisable \
+ ROM_I2CSlaveDisable
+#else
+#define MAP_I2CSlaveDisable \
+ I2CSlaveDisable
+#endif
+#ifdef ROM_I2CSlaveEnable
+#define MAP_I2CSlaveEnable \
+ ROM_I2CSlaveEnable
+#else
+#define MAP_I2CSlaveEnable \
+ I2CSlaveEnable
+#endif
+#ifdef ROM_I2CSlaveInit
+#define MAP_I2CSlaveInit \
+ ROM_I2CSlaveInit
+#else
+#define MAP_I2CSlaveInit \
+ I2CSlaveInit
+#endif
+#ifdef ROM_I2CSlaveAddressSet
+#define MAP_I2CSlaveAddressSet \
+ ROM_I2CSlaveAddressSet
+#else
+#define MAP_I2CSlaveAddressSet \
+ I2CSlaveAddressSet
+#endif
+#ifdef ROM_I2CSlaveIntClear
+#define MAP_I2CSlaveIntClear \
+ ROM_I2CSlaveIntClear
+#else
+#define MAP_I2CSlaveIntClear \
+ I2CSlaveIntClear
+#endif
+#ifdef ROM_I2CSlaveIntDisable
+#define MAP_I2CSlaveIntDisable \
+ ROM_I2CSlaveIntDisable
+#else
+#define MAP_I2CSlaveIntDisable \
+ I2CSlaveIntDisable
+#endif
+#ifdef ROM_I2CSlaveIntEnable
+#define MAP_I2CSlaveIntEnable \
+ ROM_I2CSlaveIntEnable
+#else
+#define MAP_I2CSlaveIntEnable \
+ I2CSlaveIntEnable
+#endif
+#ifdef ROM_I2CSlaveIntClearEx
+#define MAP_I2CSlaveIntClearEx \
+ ROM_I2CSlaveIntClearEx
+#else
+#define MAP_I2CSlaveIntClearEx \
+ I2CSlaveIntClearEx
+#endif
+#ifdef ROM_I2CSlaveIntDisableEx
+#define MAP_I2CSlaveIntDisableEx \
+ ROM_I2CSlaveIntDisableEx
+#else
+#define MAP_I2CSlaveIntDisableEx \
+ I2CSlaveIntDisableEx
+#endif
+#ifdef ROM_I2CSlaveIntEnableEx
+#define MAP_I2CSlaveIntEnableEx \
+ ROM_I2CSlaveIntEnableEx
+#else
+#define MAP_I2CSlaveIntEnableEx \
+ I2CSlaveIntEnableEx
+#endif
+#ifdef ROM_I2CSlaveIntStatus
+#define MAP_I2CSlaveIntStatus \
+ ROM_I2CSlaveIntStatus
+#else
+#define MAP_I2CSlaveIntStatus \
+ I2CSlaveIntStatus
+#endif
+#ifdef ROM_I2CSlaveIntStatusEx
+#define MAP_I2CSlaveIntStatusEx \
+ ROM_I2CSlaveIntStatusEx
+#else
+#define MAP_I2CSlaveIntStatusEx \
+ I2CSlaveIntStatusEx
+#endif
+#ifdef ROM_I2CSlaveStatus
+#define MAP_I2CSlaveStatus \
+ ROM_I2CSlaveStatus
+#else
+#define MAP_I2CSlaveStatus \
+ I2CSlaveStatus
+#endif
+#ifdef ROM_I2CMasterInitExpClk
+#define MAP_I2CMasterInitExpClk \
+ ROM_I2CMasterInitExpClk
+#else
+#define MAP_I2CMasterInitExpClk \
+ I2CMasterInitExpClk
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SPI API.
+//
+//*****************************************************************************
+#ifdef ROM_SPIEnable
+#define MAP_SPIEnable \
+ ROM_SPIEnable
+#else
+#define MAP_SPIEnable \
+ SPIEnable
+#endif
+#ifdef ROM_SPIDisable
+#define MAP_SPIDisable \
+ ROM_SPIDisable
+#else
+#define MAP_SPIDisable \
+ SPIDisable
+#endif
+#ifdef ROM_SPIReset
+#define MAP_SPIReset \
+ ROM_SPIReset
+#else
+#define MAP_SPIReset \
+ SPIReset
+#endif
+#ifdef ROM_SPIConfigSetExpClk
+#define MAP_SPIConfigSetExpClk \
+ ROM_SPIConfigSetExpClk
+#else
+#define MAP_SPIConfigSetExpClk \
+ SPIConfigSetExpClk
+#endif
+#ifdef ROM_SPIDataGetNonBlocking
+#define MAP_SPIDataGetNonBlocking \
+ ROM_SPIDataGetNonBlocking
+#else
+#define MAP_SPIDataGetNonBlocking \
+ SPIDataGetNonBlocking
+#endif
+#ifdef ROM_SPIDataGet
+#define MAP_SPIDataGet \
+ ROM_SPIDataGet
+#else
+#define MAP_SPIDataGet \
+ SPIDataGet
+#endif
+#ifdef ROM_SPIDataPutNonBlocking
+#define MAP_SPIDataPutNonBlocking \
+ ROM_SPIDataPutNonBlocking
+#else
+#define MAP_SPIDataPutNonBlocking \
+ SPIDataPutNonBlocking
+#endif
+#ifdef ROM_SPIDataPut
+#define MAP_SPIDataPut \
+ ROM_SPIDataPut
+#else
+#define MAP_SPIDataPut \
+ SPIDataPut
+#endif
+#ifdef ROM_SPIFIFOEnable
+#define MAP_SPIFIFOEnable \
+ ROM_SPIFIFOEnable
+#else
+#define MAP_SPIFIFOEnable \
+ SPIFIFOEnable
+#endif
+#ifdef ROM_SPIFIFODisable
+#define MAP_SPIFIFODisable \
+ ROM_SPIFIFODisable
+#else
+#define MAP_SPIFIFODisable \
+ SPIFIFODisable
+#endif
+#ifdef ROM_SPIFIFOLevelSet
+#define MAP_SPIFIFOLevelSet \
+ ROM_SPIFIFOLevelSet
+#else
+#define MAP_SPIFIFOLevelSet \
+ SPIFIFOLevelSet
+#endif
+#ifdef ROM_SPIFIFOLevelGet
+#define MAP_SPIFIFOLevelGet \
+ ROM_SPIFIFOLevelGet
+#else
+#define MAP_SPIFIFOLevelGet \
+ SPIFIFOLevelGet
+#endif
+#ifdef ROM_SPIWordCountSet
+#define MAP_SPIWordCountSet \
+ ROM_SPIWordCountSet
+#else
+#define MAP_SPIWordCountSet \
+ SPIWordCountSet
+#endif
+#ifdef ROM_SPIIntRegister
+#define MAP_SPIIntRegister \
+ ROM_SPIIntRegister
+#else
+#define MAP_SPIIntRegister \
+ SPIIntRegister
+#endif
+#ifdef ROM_SPIIntUnregister
+#define MAP_SPIIntUnregister \
+ ROM_SPIIntUnregister
+#else
+#define MAP_SPIIntUnregister \
+ SPIIntUnregister
+#endif
+#ifdef ROM_SPIIntEnable
+#define MAP_SPIIntEnable \
+ ROM_SPIIntEnable
+#else
+#define MAP_SPIIntEnable \
+ SPIIntEnable
+#endif
+#ifdef ROM_SPIIntDisable
+#define MAP_SPIIntDisable \
+ ROM_SPIIntDisable
+#else
+#define MAP_SPIIntDisable \
+ SPIIntDisable
+#endif
+#ifdef ROM_SPIIntStatus
+#define MAP_SPIIntStatus \
+ ROM_SPIIntStatus
+#else
+#define MAP_SPIIntStatus \
+ SPIIntStatus
+#endif
+#ifdef ROM_SPIIntClear
+#define MAP_SPIIntClear \
+ ROM_SPIIntClear
+#else
+#define MAP_SPIIntClear \
+ SPIIntClear
+#endif
+#ifdef ROM_SPIDmaEnable
+#define MAP_SPIDmaEnable \
+ ROM_SPIDmaEnable
+#else
+#define MAP_SPIDmaEnable \
+ SPIDmaEnable
+#endif
+#ifdef ROM_SPIDmaDisable
+#define MAP_SPIDmaDisable \
+ ROM_SPIDmaDisable
+#else
+#define MAP_SPIDmaDisable \
+ SPIDmaDisable
+#endif
+#ifdef ROM_SPICSEnable
+#define MAP_SPICSEnable \
+ ROM_SPICSEnable
+#else
+#define MAP_SPICSEnable \
+ SPICSEnable
+#endif
+#ifdef ROM_SPICSDisable
+#define MAP_SPICSDisable \
+ ROM_SPICSDisable
+#else
+#define MAP_SPICSDisable \
+ SPICSDisable
+#endif
+#ifdef ROM_SPITransfer
+#define MAP_SPITransfer \
+ ROM_SPITransfer
+#else
+#define MAP_SPITransfer \
+ SPITransfer
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CAM API.
+//
+//*****************************************************************************
+#ifdef ROM_CameraReset
+#define MAP_CameraReset \
+ ROM_CameraReset
+#else
+#define MAP_CameraReset \
+ CameraReset
+#endif
+#ifdef ROM_CameraParamsConfig
+#define MAP_CameraParamsConfig \
+ ROM_CameraParamsConfig
+#else
+#define MAP_CameraParamsConfig \
+ CameraParamsConfig
+#endif
+#ifdef ROM_CameraXClkConfig
+#define MAP_CameraXClkConfig \
+ ROM_CameraXClkConfig
+#else
+#define MAP_CameraXClkConfig \
+ CameraXClkConfig
+#endif
+#ifdef ROM_CameraXClkSet
+#define MAP_CameraXClkSet \
+ ROM_CameraXClkSet
+#else
+#define MAP_CameraXClkSet \
+ CameraXClkSet
+#endif
+#ifdef ROM_CameraDMAEnable
+#define MAP_CameraDMAEnable \
+ ROM_CameraDMAEnable
+#else
+#define MAP_CameraDMAEnable \
+ CameraDMAEnable
+#endif
+#ifdef ROM_CameraDMADisable
+#define MAP_CameraDMADisable \
+ ROM_CameraDMADisable
+#else
+#define MAP_CameraDMADisable \
+ CameraDMADisable
+#endif
+#ifdef ROM_CameraThresholdSet
+#define MAP_CameraThresholdSet \
+ ROM_CameraThresholdSet
+#else
+#define MAP_CameraThresholdSet \
+ CameraThresholdSet
+#endif
+#ifdef ROM_CameraIntRegister
+#define MAP_CameraIntRegister \
+ ROM_CameraIntRegister
+#else
+#define MAP_CameraIntRegister \
+ CameraIntRegister
+#endif
+#ifdef ROM_CameraIntUnregister
+#define MAP_CameraIntUnregister \
+ ROM_CameraIntUnregister
+#else
+#define MAP_CameraIntUnregister \
+ CameraIntUnregister
+#endif
+#ifdef ROM_CameraIntEnable
+#define MAP_CameraIntEnable \
+ ROM_CameraIntEnable
+#else
+#define MAP_CameraIntEnable \
+ CameraIntEnable
+#endif
+#ifdef ROM_CameraIntDisable
+#define MAP_CameraIntDisable \
+ ROM_CameraIntDisable
+#else
+#define MAP_CameraIntDisable \
+ CameraIntDisable
+#endif
+#ifdef ROM_CameraIntStatus
+#define MAP_CameraIntStatus \
+ ROM_CameraIntStatus
+#else
+#define MAP_CameraIntStatus \
+ CameraIntStatus
+#endif
+#ifdef ROM_CameraIntClear
+#define MAP_CameraIntClear \
+ ROM_CameraIntClear
+#else
+#define MAP_CameraIntClear \
+ CameraIntClear
+#endif
+#ifdef ROM_CameraCaptureStop
+#define MAP_CameraCaptureStop \
+ ROM_CameraCaptureStop
+#else
+#define MAP_CameraCaptureStop \
+ CameraCaptureStop
+#endif
+#ifdef ROM_CameraCaptureStart
+#define MAP_CameraCaptureStart \
+ ROM_CameraCaptureStart
+#else
+#define MAP_CameraCaptureStart \
+ CameraCaptureStart
+#endif
+#ifdef ROM_CameraBufferRead
+#define MAP_CameraBufferRead \
+ ROM_CameraBufferRead
+#else
+#define MAP_CameraBufferRead \
+ CameraBufferRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the FLASH API.
+//
+//*****************************************************************************
+#ifdef ROM_FlashDisable
+#define MAP_FlashDisable \
+ ROM_FlashDisable
+#else
+#define MAP_FlashDisable \
+ FlashDisable
+#endif
+#ifdef ROM_FlashErase
+#define MAP_FlashErase \
+ ROM_FlashErase
+#else
+#define MAP_FlashErase \
+ FlashErase
+#endif
+#ifdef ROM_FlashMassErase
+#define MAP_FlashMassErase \
+ ROM_FlashMassErase
+#else
+#define MAP_FlashMassErase \
+ FlashMassErase
+#endif
+#ifdef ROM_FlashMassEraseNonBlocking
+#define MAP_FlashMassEraseNonBlocking \
+ ROM_FlashMassEraseNonBlocking
+#else
+#define MAP_FlashMassEraseNonBlocking \
+ FlashMassEraseNonBlocking
+#endif
+#ifdef ROM_FlashEraseNonBlocking
+#define MAP_FlashEraseNonBlocking \
+ ROM_FlashEraseNonBlocking
+#else
+#define MAP_FlashEraseNonBlocking \
+ FlashEraseNonBlocking
+#endif
+#ifdef ROM_FlashProgram
+#define MAP_FlashProgram \
+ ROM_FlashProgram
+#else
+#define MAP_FlashProgram \
+ FlashProgram
+#endif
+#ifdef ROM_FlashProgramNonBlocking
+#define MAP_FlashProgramNonBlocking \
+ ROM_FlashProgramNonBlocking
+#else
+#define MAP_FlashProgramNonBlocking \
+ FlashProgramNonBlocking
+#endif
+#ifdef ROM_FlashIntRegister
+#define MAP_FlashIntRegister \
+ ROM_FlashIntRegister
+#else
+#define MAP_FlashIntRegister \
+ FlashIntRegister
+#endif
+#ifdef ROM_FlashIntUnregister
+#define MAP_FlashIntUnregister \
+ ROM_FlashIntUnregister
+#else
+#define MAP_FlashIntUnregister \
+ FlashIntUnregister
+#endif
+#ifdef ROM_FlashIntEnable
+#define MAP_FlashIntEnable \
+ ROM_FlashIntEnable
+#else
+#define MAP_FlashIntEnable \
+ FlashIntEnable
+#endif
+#ifdef ROM_FlashIntDisable
+#define MAP_FlashIntDisable \
+ ROM_FlashIntDisable
+#else
+#define MAP_FlashIntDisable \
+ FlashIntDisable
+#endif
+#ifdef ROM_FlashIntStatus
+#define MAP_FlashIntStatus \
+ ROM_FlashIntStatus
+#else
+#define MAP_FlashIntStatus \
+ FlashIntStatus
+#endif
+#ifdef ROM_FlashIntClear
+#define MAP_FlashIntClear \
+ ROM_FlashIntClear
+#else
+#define MAP_FlashIntClear \
+ FlashIntClear
+#endif
+#ifdef ROM_FlashProtectGet
+#define MAP_FlashProtectGet \
+ ROM_FlashProtectGet
+#else
+#define MAP_FlashProtectGet \
+ FlashProtectGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Pin API.
+//
+//*****************************************************************************
+#ifdef ROM_PinModeSet
+#define MAP_PinModeSet \
+ ROM_PinModeSet
+#else
+#define MAP_PinModeSet \
+ PinModeSet
+#endif
+#ifdef ROM_PinDirModeSet
+#define MAP_PinDirModeSet \
+ ROM_PinDirModeSet
+#else
+#define MAP_PinDirModeSet \
+ PinDirModeSet
+#endif
+#ifdef ROM_PinDirModeGet
+#define MAP_PinDirModeGet \
+ ROM_PinDirModeGet
+#else
+#define MAP_PinDirModeGet \
+ PinDirModeGet
+#endif
+#ifdef ROM_PinModeGet
+#define MAP_PinModeGet \
+ ROM_PinModeGet
+#else
+#define MAP_PinModeGet \
+ PinModeGet
+#endif
+#ifdef ROM_PinConfigGet
+#define MAP_PinConfigGet \
+ ROM_PinConfigGet
+#else
+#define MAP_PinConfigGet \
+ PinConfigGet
+#endif
+#ifdef ROM_PinConfigSet
+#define MAP_PinConfigSet \
+ ROM_PinConfigSet
+#else
+#define MAP_PinConfigSet \
+ PinConfigSet
+#endif
+#ifdef ROM_PinTypeUART
+#define MAP_PinTypeUART \
+ ROM_PinTypeUART
+#else
+#define MAP_PinTypeUART \
+ PinTypeUART
+#endif
+#ifdef ROM_PinTypeI2C
+#define MAP_PinTypeI2C \
+ ROM_PinTypeI2C
+#else
+#define MAP_PinTypeI2C \
+ PinTypeI2C
+#endif
+#ifdef ROM_PinTypeSPI
+#define MAP_PinTypeSPI \
+ ROM_PinTypeSPI
+#else
+#define MAP_PinTypeSPI \
+ PinTypeSPI
+#endif
+#ifdef ROM_PinTypeI2S
+#define MAP_PinTypeI2S \
+ ROM_PinTypeI2S
+#else
+#define MAP_PinTypeI2S \
+ PinTypeI2S
+#endif
+#ifdef ROM_PinTypeTimer
+#define MAP_PinTypeTimer \
+ ROM_PinTypeTimer
+#else
+#define MAP_PinTypeTimer \
+ PinTypeTimer
+#endif
+#ifdef ROM_PinTypeCamera
+#define MAP_PinTypeCamera \
+ ROM_PinTypeCamera
+#else
+#define MAP_PinTypeCamera \
+ PinTypeCamera
+#endif
+#ifdef ROM_PinTypeGPIO
+#define MAP_PinTypeGPIO \
+ ROM_PinTypeGPIO
+#else
+#define MAP_PinTypeGPIO \
+ PinTypeGPIO
+#endif
+#ifdef ROM_PinTypeADC
+#define MAP_PinTypeADC \
+ ROM_PinTypeADC
+#else
+#define MAP_PinTypeADC \
+ PinTypeADC
+#endif
+#ifdef ROM_PinTypeSDHost
+#define MAP_PinTypeSDHost \
+ ROM_PinTypeSDHost
+#else
+#define MAP_PinTypeSDHost \
+ PinTypeSDHost
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SYSTICK API.
+//
+//*****************************************************************************
+#ifdef ROM_SysTickEnable
+#define MAP_SysTickEnable \
+ ROM_SysTickEnable
+#else
+#define MAP_SysTickEnable \
+ SysTickEnable
+#endif
+#ifdef ROM_SysTickDisable
+#define MAP_SysTickDisable \
+ ROM_SysTickDisable
+#else
+#define MAP_SysTickDisable \
+ SysTickDisable
+#endif
+#ifdef ROM_SysTickIntRegister
+#define MAP_SysTickIntRegister \
+ ROM_SysTickIntRegister
+#else
+#define MAP_SysTickIntRegister \
+ SysTickIntRegister
+#endif
+#ifdef ROM_SysTickIntUnregister
+#define MAP_SysTickIntUnregister \
+ ROM_SysTickIntUnregister
+#else
+#define MAP_SysTickIntUnregister \
+ SysTickIntUnregister
+#endif
+#ifdef ROM_SysTickIntEnable
+#define MAP_SysTickIntEnable \
+ ROM_SysTickIntEnable
+#else
+#define MAP_SysTickIntEnable \
+ SysTickIntEnable
+#endif
+#ifdef ROM_SysTickIntDisable
+#define MAP_SysTickIntDisable \
+ ROM_SysTickIntDisable
+#else
+#define MAP_SysTickIntDisable \
+ SysTickIntDisable
+#endif
+#ifdef ROM_SysTickPeriodSet
+#define MAP_SysTickPeriodSet \
+ ROM_SysTickPeriodSet
+#else
+#define MAP_SysTickPeriodSet \
+ SysTickPeriodSet
+#endif
+#ifdef ROM_SysTickPeriodGet
+#define MAP_SysTickPeriodGet \
+ ROM_SysTickPeriodGet
+#else
+#define MAP_SysTickPeriodGet \
+ SysTickPeriodGet
+#endif
+#ifdef ROM_SysTickValueGet
+#define MAP_SysTickValueGet \
+ ROM_SysTickValueGet
+#else
+#define MAP_SysTickValueGet \
+ SysTickValueGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UTILS API.
+//
+//*****************************************************************************
+#ifdef ROM_UtilsDelay
+#define MAP_UtilsDelay \
+ ROM_UtilsDelay
+#else
+#define MAP_UtilsDelay \
+ UtilsDelay
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2S API.
+//
+//*****************************************************************************
+#ifdef ROM_I2SEnable
+#define MAP_I2SEnable \
+ ROM_I2SEnable
+#else
+#define MAP_I2SEnable \
+ I2SEnable
+#endif
+#ifdef ROM_I2SDisable
+#define MAP_I2SDisable \
+ ROM_I2SDisable
+#else
+#define MAP_I2SDisable \
+ I2SDisable
+#endif
+#ifdef ROM_I2SDataPut
+#define MAP_I2SDataPut \
+ ROM_I2SDataPut
+#else
+#define MAP_I2SDataPut \
+ I2SDataPut
+#endif
+#ifdef ROM_I2SDataPutNonBlocking
+#define MAP_I2SDataPutNonBlocking \
+ ROM_I2SDataPutNonBlocking
+#else
+#define MAP_I2SDataPutNonBlocking \
+ I2SDataPutNonBlocking
+#endif
+#ifdef ROM_I2SDataGet
+#define MAP_I2SDataGet \
+ ROM_I2SDataGet
+#else
+#define MAP_I2SDataGet \
+ I2SDataGet
+#endif
+#ifdef ROM_I2SDataGetNonBlocking
+#define MAP_I2SDataGetNonBlocking \
+ ROM_I2SDataGetNonBlocking
+#else
+#define MAP_I2SDataGetNonBlocking \
+ I2SDataGetNonBlocking
+#endif
+#ifdef ROM_I2SConfigSetExpClk
+#define MAP_I2SConfigSetExpClk \
+ ROM_I2SConfigSetExpClk
+#else
+#define MAP_I2SConfigSetExpClk \
+ I2SConfigSetExpClk
+#endif
+#ifdef ROM_I2STxFIFOEnable
+#define MAP_I2STxFIFOEnable \
+ ROM_I2STxFIFOEnable
+#else
+#define MAP_I2STxFIFOEnable \
+ I2STxFIFOEnable
+#endif
+#ifdef ROM_I2STxFIFODisable
+#define MAP_I2STxFIFODisable \
+ ROM_I2STxFIFODisable
+#else
+#define MAP_I2STxFIFODisable \
+ I2STxFIFODisable
+#endif
+#ifdef ROM_I2SRxFIFOEnable
+#define MAP_I2SRxFIFOEnable \
+ ROM_I2SRxFIFOEnable
+#else
+#define MAP_I2SRxFIFOEnable \
+ I2SRxFIFOEnable
+#endif
+#ifdef ROM_I2SRxFIFODisable
+#define MAP_I2SRxFIFODisable \
+ ROM_I2SRxFIFODisable
+#else
+#define MAP_I2SRxFIFODisable \
+ I2SRxFIFODisable
+#endif
+#ifdef ROM_I2STxFIFOStatusGet
+#define MAP_I2STxFIFOStatusGet \
+ ROM_I2STxFIFOStatusGet
+#else
+#define MAP_I2STxFIFOStatusGet \
+ I2STxFIFOStatusGet
+#endif
+#ifdef ROM_I2SRxFIFOStatusGet
+#define MAP_I2SRxFIFOStatusGet \
+ ROM_I2SRxFIFOStatusGet
+#else
+#define MAP_I2SRxFIFOStatusGet \
+ I2SRxFIFOStatusGet
+#endif
+#ifdef ROM_I2SSerializerConfig
+#define MAP_I2SSerializerConfig \
+ ROM_I2SSerializerConfig
+#else
+#define MAP_I2SSerializerConfig \
+ I2SSerializerConfig
+#endif
+#ifdef ROM_I2SIntEnable
+#define MAP_I2SIntEnable \
+ ROM_I2SIntEnable
+#else
+#define MAP_I2SIntEnable \
+ I2SIntEnable
+#endif
+#ifdef ROM_I2SIntDisable
+#define MAP_I2SIntDisable \
+ ROM_I2SIntDisable
+#else
+#define MAP_I2SIntDisable \
+ I2SIntDisable
+#endif
+#ifdef ROM_I2SIntStatus
+#define MAP_I2SIntStatus \
+ ROM_I2SIntStatus
+#else
+#define MAP_I2SIntStatus \
+ I2SIntStatus
+#endif
+#ifdef ROM_I2SIntClear
+#define MAP_I2SIntClear \
+ ROM_I2SIntClear
+#else
+#define MAP_I2SIntClear \
+ I2SIntClear
+#endif
+#ifdef ROM_I2SIntRegister
+#define MAP_I2SIntRegister \
+ ROM_I2SIntRegister
+#else
+#define MAP_I2SIntRegister \
+ I2SIntRegister
+#endif
+#ifdef ROM_I2SIntUnregister
+#define MAP_I2SIntUnregister \
+ ROM_I2SIntUnregister
+#else
+#define MAP_I2SIntUnregister \
+ I2SIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Macros for the GPIO API.
+//
+//*****************************************************************************
+#ifdef ROM_GPIODirModeSet
+#define MAP_GPIODirModeSet \
+ ROM_GPIODirModeSet
+#else
+#define MAP_GPIODirModeSet \
+ GPIODirModeSet
+#endif
+#ifdef ROM_GPIODirModeGet
+#define MAP_GPIODirModeGet \
+ ROM_GPIODirModeGet
+#else
+#define MAP_GPIODirModeGet \
+ GPIODirModeGet
+#endif
+#ifdef ROM_GPIOIntTypeSet
+#define MAP_GPIOIntTypeSet \
+ ROM_GPIOIntTypeSet
+#else
+#define MAP_GPIOIntTypeSet \
+ GPIOIntTypeSet
+#endif
+#ifdef ROM_GPIODMATriggerEnable
+#define MAP_GPIODMATriggerEnable \
+ ROM_GPIODMATriggerEnable
+#else
+#define MAP_GPIODMATriggerEnable \
+ GPIODMATriggerEnable
+#endif
+#ifdef ROM_GPIODMATriggerDisable
+#define MAP_GPIODMATriggerDisable \
+ ROM_GPIODMATriggerDisable
+#else
+#define MAP_GPIODMATriggerDisable \
+ GPIODMATriggerDisable
+#endif
+#ifdef ROM_GPIOIntTypeGet
+#define MAP_GPIOIntTypeGet \
+ ROM_GPIOIntTypeGet
+#else
+#define MAP_GPIOIntTypeGet \
+ GPIOIntTypeGet
+#endif
+#ifdef ROM_GPIOIntEnable
+#define MAP_GPIOIntEnable \
+ ROM_GPIOIntEnable
+#else
+#define MAP_GPIOIntEnable \
+ GPIOIntEnable
+#endif
+#ifdef ROM_GPIOIntDisable
+#define MAP_GPIOIntDisable \
+ ROM_GPIOIntDisable
+#else
+#define MAP_GPIOIntDisable \
+ GPIOIntDisable
+#endif
+#ifdef ROM_GPIOIntStatus
+#define MAP_GPIOIntStatus \
+ ROM_GPIOIntStatus
+#else
+#define MAP_GPIOIntStatus \
+ GPIOIntStatus
+#endif
+#ifdef ROM_GPIOIntClear
+#define MAP_GPIOIntClear \
+ ROM_GPIOIntClear
+#else
+#define MAP_GPIOIntClear \
+ GPIOIntClear
+#endif
+#ifdef ROM_GPIOIntRegister
+#define MAP_GPIOIntRegister \
+ ROM_GPIOIntRegister
+#else
+#define MAP_GPIOIntRegister \
+ GPIOIntRegister
+#endif
+#ifdef ROM_GPIOIntUnregister
+#define MAP_GPIOIntUnregister \
+ ROM_GPIOIntUnregister
+#else
+#define MAP_GPIOIntUnregister \
+ GPIOIntUnregister
+#endif
+#ifdef ROM_GPIOPinRead
+#define MAP_GPIOPinRead \
+ ROM_GPIOPinRead
+#else
+#define MAP_GPIOPinRead \
+ GPIOPinRead
+#endif
+#ifdef ROM_GPIOPinWrite
+#define MAP_GPIOPinWrite \
+ ROM_GPIOPinWrite
+#else
+#define MAP_GPIOPinWrite \
+ GPIOPinWrite
+#endif
+
+//*****************************************************************************
+//
+// Macros for the AES API.
+//
+//*****************************************************************************
+#ifdef ROM_AESConfigSet
+#define MAP_AESConfigSet \
+ ROM_AESConfigSet
+#else
+#define MAP_AESConfigSet \
+ AESConfigSet
+#endif
+#ifdef ROM_AESKey1Set
+#define MAP_AESKey1Set \
+ ROM_AESKey1Set
+#else
+#define MAP_AESKey1Set \
+ AESKey1Set
+#endif
+#ifdef ROM_AESKey2Set
+#define MAP_AESKey2Set \
+ ROM_AESKey2Set
+#else
+#define MAP_AESKey2Set \
+ AESKey2Set
+#endif
+#ifdef ROM_AESKey3Set
+#define MAP_AESKey3Set \
+ ROM_AESKey3Set
+#else
+#define MAP_AESKey3Set \
+ AESKey3Set
+#endif
+#ifdef ROM_AESIVSet
+#define MAP_AESIVSet \
+ ROM_AESIVSet
+#else
+#define MAP_AESIVSet \
+ AESIVSet
+#endif
+#ifdef ROM_AESTagRead
+#define MAP_AESTagRead \
+ ROM_AESTagRead
+#else
+#define MAP_AESTagRead \
+ AESTagRead
+#endif
+#ifdef ROM_AESDataLengthSet
+#define MAP_AESDataLengthSet \
+ ROM_AESDataLengthSet
+#else
+#define MAP_AESDataLengthSet \
+ AESDataLengthSet
+#endif
+#ifdef ROM_AESAuthDataLengthSet
+#define MAP_AESAuthDataLengthSet \
+ ROM_AESAuthDataLengthSet
+#else
+#define MAP_AESAuthDataLengthSet \
+ AESAuthDataLengthSet
+#endif
+#ifdef ROM_AESDataReadNonBlocking
+#define MAP_AESDataReadNonBlocking \
+ ROM_AESDataReadNonBlocking
+#else
+#define MAP_AESDataReadNonBlocking \
+ AESDataReadNonBlocking
+#endif
+#ifdef ROM_AESDataRead
+#define MAP_AESDataRead \
+ ROM_AESDataRead
+#else
+#define MAP_AESDataRead \
+ AESDataRead
+#endif
+#ifdef ROM_AESDataWriteNonBlocking
+#define MAP_AESDataWriteNonBlocking \
+ ROM_AESDataWriteNonBlocking
+#else
+#define MAP_AESDataWriteNonBlocking \
+ AESDataWriteNonBlocking
+#endif
+#ifdef ROM_AESDataWrite
+#define MAP_AESDataWrite \
+ ROM_AESDataWrite
+#else
+#define MAP_AESDataWrite \
+ AESDataWrite
+#endif
+#ifdef ROM_AESDataProcess
+#define MAP_AESDataProcess \
+ ROM_AESDataProcess
+#else
+#define MAP_AESDataProcess \
+ AESDataProcess
+#endif
+#ifdef ROM_AESDataMAC
+#define MAP_AESDataMAC \
+ ROM_AESDataMAC
+#else
+#define MAP_AESDataMAC \
+ AESDataMAC
+#endif
+#ifdef ROM_AESDataProcessAE
+#define MAP_AESDataProcessAE \
+ ROM_AESDataProcessAE
+#else
+#define MAP_AESDataProcessAE \
+ AESDataProcessAE
+#endif
+#ifdef ROM_AESIntStatus
+#define MAP_AESIntStatus \
+ ROM_AESIntStatus
+#else
+#define MAP_AESIntStatus \
+ AESIntStatus
+#endif
+#ifdef ROM_AESIntEnable
+#define MAP_AESIntEnable \
+ ROM_AESIntEnable
+#else
+#define MAP_AESIntEnable \
+ AESIntEnable
+#endif
+#ifdef ROM_AESIntDisable
+#define MAP_AESIntDisable \
+ ROM_AESIntDisable
+#else
+#define MAP_AESIntDisable \
+ AESIntDisable
+#endif
+#ifdef ROM_AESIntClear
+#define MAP_AESIntClear \
+ ROM_AESIntClear
+#else
+#define MAP_AESIntClear \
+ AESIntClear
+#endif
+#ifdef ROM_AESIntRegister
+#define MAP_AESIntRegister \
+ ROM_AESIntRegister
+#else
+#define MAP_AESIntRegister \
+ AESIntRegister
+#endif
+#ifdef ROM_AESIntUnregister
+#define MAP_AESIntUnregister \
+ ROM_AESIntUnregister
+#else
+#define MAP_AESIntUnregister \
+ AESIntUnregister
+#endif
+#ifdef ROM_AESDMAEnable
+#define MAP_AESDMAEnable \
+ ROM_AESDMAEnable
+#else
+#define MAP_AESDMAEnable \
+ AESDMAEnable
+#endif
+#ifdef ROM_AESDMADisable
+#define MAP_AESDMADisable \
+ ROM_AESDMADisable
+#else
+#define MAP_AESDMADisable \
+ AESDMADisable
+#endif
+
+//*****************************************************************************
+//
+// Macros for the DES API.
+//
+//*****************************************************************************
+#ifdef ROM_DESConfigSet
+#define MAP_DESConfigSet \
+ ROM_DESConfigSet
+#else
+#define MAP_DESConfigSet \
+ DESConfigSet
+#endif
+#ifdef ROM_DESDataRead
+#define MAP_DESDataRead \
+ ROM_DESDataRead
+#else
+#define MAP_DESDataRead \
+ DESDataRead
+#endif
+#ifdef ROM_DESDataReadNonBlocking
+#define MAP_DESDataReadNonBlocking \
+ ROM_DESDataReadNonBlocking
+#else
+#define MAP_DESDataReadNonBlocking \
+ DESDataReadNonBlocking
+#endif
+#ifdef ROM_DESDataProcess
+#define MAP_DESDataProcess \
+ ROM_DESDataProcess
+#else
+#define MAP_DESDataProcess \
+ DESDataProcess
+#endif
+#ifdef ROM_DESDataWrite
+#define MAP_DESDataWrite \
+ ROM_DESDataWrite
+#else
+#define MAP_DESDataWrite \
+ DESDataWrite
+#endif
+#ifdef ROM_DESDataWriteNonBlocking
+#define MAP_DESDataWriteNonBlocking \
+ ROM_DESDataWriteNonBlocking
+#else
+#define MAP_DESDataWriteNonBlocking \
+ DESDataWriteNonBlocking
+#endif
+#ifdef ROM_DESDMADisable
+#define MAP_DESDMADisable \
+ ROM_DESDMADisable
+#else
+#define MAP_DESDMADisable \
+ DESDMADisable
+#endif
+#ifdef ROM_DESDMAEnable
+#define MAP_DESDMAEnable \
+ ROM_DESDMAEnable
+#else
+#define MAP_DESDMAEnable \
+ DESDMAEnable
+#endif
+#ifdef ROM_DESIntClear
+#define MAP_DESIntClear \
+ ROM_DESIntClear
+#else
+#define MAP_DESIntClear \
+ DESIntClear
+#endif
+#ifdef ROM_DESIntDisable
+#define MAP_DESIntDisable \
+ ROM_DESIntDisable
+#else
+#define MAP_DESIntDisable \
+ DESIntDisable
+#endif
+#ifdef ROM_DESIntEnable
+#define MAP_DESIntEnable \
+ ROM_DESIntEnable
+#else
+#define MAP_DESIntEnable \
+ DESIntEnable
+#endif
+#ifdef ROM_DESIntRegister
+#define MAP_DESIntRegister \
+ ROM_DESIntRegister
+#else
+#define MAP_DESIntRegister \
+ DESIntRegister
+#endif
+#ifdef ROM_DESIntStatus
+#define MAP_DESIntStatus \
+ ROM_DESIntStatus
+#else
+#define MAP_DESIntStatus \
+ DESIntStatus
+#endif
+#ifdef ROM_DESIntUnregister
+#define MAP_DESIntUnregister \
+ ROM_DESIntUnregister
+#else
+#define MAP_DESIntUnregister \
+ DESIntUnregister
+#endif
+#ifdef ROM_DESIVSet
+#define MAP_DESIVSet \
+ ROM_DESIVSet
+#else
+#define MAP_DESIVSet \
+ DESIVSet
+#endif
+#ifdef ROM_DESKeySet
+#define MAP_DESKeySet \
+ ROM_DESKeySet
+#else
+#define MAP_DESKeySet \
+ DESKeySet
+#endif
+#ifdef ROM_DESDataLengthSet
+#define MAP_DESDataLengthSet \
+ ROM_DESDataLengthSet
+#else
+#define MAP_DESDataLengthSet \
+ DESDataLengthSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SHAMD5 API.
+//
+//*****************************************************************************
+#ifdef ROM_SHAMD5ConfigSet
+#define MAP_SHAMD5ConfigSet \
+ ROM_SHAMD5ConfigSet
+#else
+#define MAP_SHAMD5ConfigSet \
+ SHAMD5ConfigSet
+#endif
+#ifdef ROM_SHAMD5DataProcess
+#define MAP_SHAMD5DataProcess \
+ ROM_SHAMD5DataProcess
+#else
+#define MAP_SHAMD5DataProcess \
+ SHAMD5DataProcess
+#endif
+#ifdef ROM_SHAMD5DataWrite
+#define MAP_SHAMD5DataWrite \
+ ROM_SHAMD5DataWrite
+#else
+#define MAP_SHAMD5DataWrite \
+ SHAMD5DataWrite
+#endif
+#ifdef ROM_SHAMD5DataWriteNonBlocking
+#define MAP_SHAMD5DataWriteNonBlocking \
+ ROM_SHAMD5DataWriteNonBlocking
+#else
+#define MAP_SHAMD5DataWriteNonBlocking \
+ SHAMD5DataWriteNonBlocking
+#endif
+#ifdef ROM_SHAMD5DMADisable
+#define MAP_SHAMD5DMADisable \
+ ROM_SHAMD5DMADisable
+#else
+#define MAP_SHAMD5DMADisable \
+ SHAMD5DMADisable
+#endif
+#ifdef ROM_SHAMD5DMAEnable
+#define MAP_SHAMD5DMAEnable \
+ ROM_SHAMD5DMAEnable
+#else
+#define MAP_SHAMD5DMAEnable \
+ SHAMD5DMAEnable
+#endif
+#ifdef ROM_SHAMD5DataLengthSet
+#define MAP_SHAMD5DataLengthSet \
+ ROM_SHAMD5DataLengthSet
+#else
+#define MAP_SHAMD5DataLengthSet \
+ SHAMD5DataLengthSet
+#endif
+#ifdef ROM_SHAMD5HMACKeySet
+#define MAP_SHAMD5HMACKeySet \
+ ROM_SHAMD5HMACKeySet
+#else
+#define MAP_SHAMD5HMACKeySet \
+ SHAMD5HMACKeySet
+#endif
+#ifdef ROM_SHAMD5HMACPPKeyGenerate
+#define MAP_SHAMD5HMACPPKeyGenerate \
+ ROM_SHAMD5HMACPPKeyGenerate
+#else
+#define MAP_SHAMD5HMACPPKeyGenerate \
+ SHAMD5HMACPPKeyGenerate
+#endif
+#ifdef ROM_SHAMD5HMACPPKeySet
+#define MAP_SHAMD5HMACPPKeySet \
+ ROM_SHAMD5HMACPPKeySet
+#else
+#define MAP_SHAMD5HMACPPKeySet \
+ SHAMD5HMACPPKeySet
+#endif
+#ifdef ROM_SHAMD5HMACProcess
+#define MAP_SHAMD5HMACProcess \
+ ROM_SHAMD5HMACProcess
+#else
+#define MAP_SHAMD5HMACProcess \
+ SHAMD5HMACProcess
+#endif
+#ifdef ROM_SHAMD5IntClear
+#define MAP_SHAMD5IntClear \
+ ROM_SHAMD5IntClear
+#else
+#define MAP_SHAMD5IntClear \
+ SHAMD5IntClear
+#endif
+#ifdef ROM_SHAMD5IntDisable
+#define MAP_SHAMD5IntDisable \
+ ROM_SHAMD5IntDisable
+#else
+#define MAP_SHAMD5IntDisable \
+ SHAMD5IntDisable
+#endif
+#ifdef ROM_SHAMD5IntEnable
+#define MAP_SHAMD5IntEnable \
+ ROM_SHAMD5IntEnable
+#else
+#define MAP_SHAMD5IntEnable \
+ SHAMD5IntEnable
+#endif
+#ifdef ROM_SHAMD5IntRegister
+#define MAP_SHAMD5IntRegister \
+ ROM_SHAMD5IntRegister
+#else
+#define MAP_SHAMD5IntRegister \
+ SHAMD5IntRegister
+#endif
+#ifdef ROM_SHAMD5IntStatus
+#define MAP_SHAMD5IntStatus \
+ ROM_SHAMD5IntStatus
+#else
+#define MAP_SHAMD5IntStatus \
+ SHAMD5IntStatus
+#endif
+#ifdef ROM_SHAMD5IntUnregister
+#define MAP_SHAMD5IntUnregister \
+ ROM_SHAMD5IntUnregister
+#else
+#define MAP_SHAMD5IntUnregister \
+ SHAMD5IntUnregister
+#endif
+#ifdef ROM_SHAMD5ResultRead
+#define MAP_SHAMD5ResultRead \
+ ROM_SHAMD5ResultRead
+#else
+#define MAP_SHAMD5ResultRead \
+ SHAMD5ResultRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CRC API.
+//
+//*****************************************************************************
+#ifdef ROM_CRCConfigSet
+#define MAP_CRCConfigSet \
+ ROM_CRCConfigSet
+#else
+#define MAP_CRCConfigSet \
+ CRCConfigSet
+#endif
+#ifdef ROM_CRCDataProcess
+#define MAP_CRCDataProcess \
+ ROM_CRCDataProcess
+#else
+#define MAP_CRCDataProcess \
+ CRCDataProcess
+#endif
+#ifdef ROM_CRCDataWrite
+#define MAP_CRCDataWrite \
+ ROM_CRCDataWrite
+#else
+#define MAP_CRCDataWrite \
+ CRCDataWrite
+#endif
+#ifdef ROM_CRCResultRead
+#define MAP_CRCResultRead \
+ ROM_CRCResultRead
+#else
+#define MAP_CRCResultRead \
+ CRCResultRead
+#endif
+#ifdef ROM_CRCSeedSet
+#define MAP_CRCSeedSet \
+ ROM_CRCSeedSet
+#else
+#define MAP_CRCSeedSet \
+ CRCSeedSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SDHOST API.
+//
+//*****************************************************************************
+#ifdef ROM_SDHostCmdReset
+#define MAP_SDHostCmdReset \
+ ROM_SDHostCmdReset
+#else
+#define MAP_SDHostCmdReset \
+ SDHostCmdReset
+#endif
+#ifdef ROM_SDHostInit
+#define MAP_SDHostInit \
+ ROM_SDHostInit
+#else
+#define MAP_SDHostInit \
+ SDHostInit
+#endif
+#ifdef ROM_SDHostCmdSend
+#define MAP_SDHostCmdSend \
+ ROM_SDHostCmdSend
+#else
+#define MAP_SDHostCmdSend \
+ SDHostCmdSend
+#endif
+#ifdef ROM_SDHostIntRegister
+#define MAP_SDHostIntRegister \
+ ROM_SDHostIntRegister
+#else
+#define MAP_SDHostIntRegister \
+ SDHostIntRegister
+#endif
+#ifdef ROM_SDHostIntUnregister
+#define MAP_SDHostIntUnregister \
+ ROM_SDHostIntUnregister
+#else
+#define MAP_SDHostIntUnregister \
+ SDHostIntUnregister
+#endif
+#ifdef ROM_SDHostIntEnable
+#define MAP_SDHostIntEnable \
+ ROM_SDHostIntEnable
+#else
+#define MAP_SDHostIntEnable \
+ SDHostIntEnable
+#endif
+#ifdef ROM_SDHostIntDisable
+#define MAP_SDHostIntDisable \
+ ROM_SDHostIntDisable
+#else
+#define MAP_SDHostIntDisable \
+ SDHostIntDisable
+#endif
+#ifdef ROM_SDHostIntStatus
+#define MAP_SDHostIntStatus \
+ ROM_SDHostIntStatus
+#else
+#define MAP_SDHostIntStatus \
+ SDHostIntStatus
+#endif
+#ifdef ROM_SDHostIntClear
+#define MAP_SDHostIntClear \
+ ROM_SDHostIntClear
+#else
+#define MAP_SDHostIntClear \
+ SDHostIntClear
+#endif
+#ifdef ROM_SDHostRespStatus
+#define MAP_SDHostRespStatus \
+ ROM_SDHostRespStatus
+#else
+#define MAP_SDHostRespStatus \
+ SDHostRespStatus
+#endif
+#ifdef ROM_SDHostRespGet
+#define MAP_SDHostRespGet \
+ ROM_SDHostRespGet
+#else
+#define MAP_SDHostRespGet \
+ SDHostRespGet
+#endif
+#ifdef ROM_SDHostBlockSizeSet
+#define MAP_SDHostBlockSizeSet \
+ ROM_SDHostBlockSizeSet
+#else
+#define MAP_SDHostBlockSizeSet \
+ SDHostBlockSizeSet
+#endif
+#ifdef ROM_SDHostBlockCountSet
+#define MAP_SDHostBlockCountSet \
+ ROM_SDHostBlockCountSet
+#else
+#define MAP_SDHostBlockCountSet \
+ SDHostBlockCountSet
+#endif
+#ifdef ROM_SDHostDataNonBlockingWrite
+#define MAP_SDHostDataNonBlockingWrite \
+ ROM_SDHostDataNonBlockingWrite
+#else
+#define MAP_SDHostDataNonBlockingWrite \
+ SDHostDataNonBlockingWrite
+#endif
+#ifdef ROM_SDHostDataNonBlockingRead
+#define MAP_SDHostDataNonBlockingRead \
+ ROM_SDHostDataNonBlockingRead
+#else
+#define MAP_SDHostDataNonBlockingRead \
+ SDHostDataNonBlockingRead
+#endif
+#ifdef ROM_SDHostDataWrite
+#define MAP_SDHostDataWrite \
+ ROM_SDHostDataWrite
+#else
+#define MAP_SDHostDataWrite \
+ SDHostDataWrite
+#endif
+#ifdef ROM_SDHostDataRead
+#define MAP_SDHostDataRead \
+ ROM_SDHostDataRead
+#else
+#define MAP_SDHostDataRead \
+ SDHostDataRead
+#endif
+#ifdef ROM_SDHostSetExpClk
+#define MAP_SDHostSetExpClk \
+ ROM_SDHostSetExpClk
+#else
+#define MAP_SDHostSetExpClk \
+ SDHostSetExpClk
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PRCM API.
+//
+//*****************************************************************************
+#ifdef ROM_PRCMMCUReset
+#define MAP_PRCMMCUReset \
+ ROM_PRCMMCUReset
+#else
+#define MAP_PRCMMCUReset \
+ PRCMMCUReset
+#endif
+#ifdef ROM_PRCMSysResetCauseGet
+#define MAP_PRCMSysResetCauseGet \
+ ROM_PRCMSysResetCauseGet
+#else
+#define MAP_PRCMSysResetCauseGet \
+ PRCMSysResetCauseGet
+#endif
+#ifdef ROM_PRCMPeripheralClkEnable
+#define MAP_PRCMPeripheralClkEnable \
+ ROM_PRCMPeripheralClkEnable
+#else
+#define MAP_PRCMPeripheralClkEnable \
+ PRCMPeripheralClkEnable
+#endif
+#ifdef ROM_PRCMPeripheralClkDisable
+#define MAP_PRCMPeripheralClkDisable \
+ ROM_PRCMPeripheralClkDisable
+#else
+#define MAP_PRCMPeripheralClkDisable \
+ PRCMPeripheralClkDisable
+#endif
+#ifdef ROM_PRCMPeripheralReset
+#define MAP_PRCMPeripheralReset \
+ ROM_PRCMPeripheralReset
+#else
+#define MAP_PRCMPeripheralReset \
+ PRCMPeripheralReset
+#endif
+#ifdef ROM_PRCMPeripheralStatusGet
+#define MAP_PRCMPeripheralStatusGet \
+ ROM_PRCMPeripheralStatusGet
+#else
+#define MAP_PRCMPeripheralStatusGet \
+ PRCMPeripheralStatusGet
+#endif
+#ifdef ROM_PRCMI2SClockFreqSet
+#define MAP_PRCMI2SClockFreqSet \
+ ROM_PRCMI2SClockFreqSet
+#else
+#define MAP_PRCMI2SClockFreqSet \
+ PRCMI2SClockFreqSet
+#endif
+#ifdef ROM_PRCMPeripheralClockGet
+#define MAP_PRCMPeripheralClockGet \
+ ROM_PRCMPeripheralClockGet
+#else
+#define MAP_PRCMPeripheralClockGet \
+ PRCMPeripheralClockGet
+#endif
+#ifdef ROM_PRCMSleepEnter
+#define MAP_PRCMSleepEnter \
+ ROM_PRCMSleepEnter
+#else
+#define MAP_PRCMSleepEnter \
+ PRCMSleepEnter
+#endif
+#ifdef ROM_PRCMDeepSleepEnter
+#define MAP_PRCMDeepSleepEnter \
+ ROM_PRCMDeepSleepEnter
+#else
+#define MAP_PRCMDeepSleepEnter \
+ PRCMDeepSleepEnter
+#endif
+#ifdef ROM_PRCMSRAMRetentionEnable
+#define MAP_PRCMSRAMRetentionEnable \
+ ROM_PRCMSRAMRetentionEnable
+#else
+#define MAP_PRCMSRAMRetentionEnable \
+ PRCMSRAMRetentionEnable
+#endif
+#ifdef ROM_PRCMSRAMRetentionDisable
+#define MAP_PRCMSRAMRetentionDisable \
+ ROM_PRCMSRAMRetentionDisable
+#else
+#define MAP_PRCMSRAMRetentionDisable \
+ PRCMSRAMRetentionDisable
+#endif
+#ifdef ROM_PRCMLPDSEnter
+#define MAP_PRCMLPDSEnter \
+ ROM_PRCMLPDSEnter
+#else
+#define MAP_PRCMLPDSEnter \
+ PRCMLPDSEnter
+#endif
+#ifdef ROM_PRCMLPDSIntervalSet
+#define MAP_PRCMLPDSIntervalSet \
+ ROM_PRCMLPDSIntervalSet
+#else
+#define MAP_PRCMLPDSIntervalSet \
+ PRCMLPDSIntervalSet
+#endif
+#ifdef ROM_PRCMLPDSWakeupSourceEnable
+#define MAP_PRCMLPDSWakeupSourceEnable \
+ ROM_PRCMLPDSWakeupSourceEnable
+#else
+#define MAP_PRCMLPDSWakeupSourceEnable \
+ PRCMLPDSWakeupSourceEnable
+#endif
+#ifdef ROM_PRCMLPDSWakeupCauseGet
+#define MAP_PRCMLPDSWakeupCauseGet \
+ ROM_PRCMLPDSWakeupCauseGet
+#else
+#define MAP_PRCMLPDSWakeupCauseGet \
+ PRCMLPDSWakeupCauseGet
+#endif
+#ifdef ROM_PRCMLPDSWakeUpGPIOSelect
+#define MAP_PRCMLPDSWakeUpGPIOSelect \
+ ROM_PRCMLPDSWakeUpGPIOSelect
+#else
+#define MAP_PRCMLPDSWakeUpGPIOSelect \
+ PRCMLPDSWakeUpGPIOSelect
+#endif
+#ifdef ROM_PRCMLPDSWakeupSourceDisable
+#define MAP_PRCMLPDSWakeupSourceDisable \
+ ROM_PRCMLPDSWakeupSourceDisable
+#else
+#define MAP_PRCMLPDSWakeupSourceDisable \
+ PRCMLPDSWakeupSourceDisable
+#endif
+#ifdef ROM_PRCMHibernateEnter
+#define MAP_PRCMHibernateEnter \
+ ROM_PRCMHibernateEnter
+#else
+#define MAP_PRCMHibernateEnter \
+ PRCMHibernateEnter
+#endif
+#ifdef ROM_PRCMHibernateWakeupSourceEnable
+#define MAP_PRCMHibernateWakeupSourceEnable \
+ ROM_PRCMHibernateWakeupSourceEnable
+#else
+#define MAP_PRCMHibernateWakeupSourceEnable \
+ PRCMHibernateWakeupSourceEnable
+#endif
+#ifdef ROM_PRCMHibernateWakeupCauseGet
+#define MAP_PRCMHibernateWakeupCauseGet \
+ ROM_PRCMHibernateWakeupCauseGet
+#else
+#define MAP_PRCMHibernateWakeupCauseGet \
+ PRCMHibernateWakeupCauseGet
+#endif
+#ifdef ROM_PRCMHibernateWakeUpGPIOSelect
+#define MAP_PRCMHibernateWakeUpGPIOSelect \
+ ROM_PRCMHibernateWakeUpGPIOSelect
+#else
+#define MAP_PRCMHibernateWakeUpGPIOSelect \
+ PRCMHibernateWakeUpGPIOSelect
+#endif
+#ifdef ROM_PRCMHibernateWakeupSourceDisable
+#define MAP_PRCMHibernateWakeupSourceDisable \
+ ROM_PRCMHibernateWakeupSourceDisable
+#else
+#define MAP_PRCMHibernateWakeupSourceDisable \
+ PRCMHibernateWakeupSourceDisable
+#endif
+#ifdef ROM_PRCMHibernateIntervalSet
+#define MAP_PRCMHibernateIntervalSet \
+ ROM_PRCMHibernateIntervalSet
+#else
+#define MAP_PRCMHibernateIntervalSet \
+ PRCMHibernateIntervalSet
+#endif
+#ifdef ROM_PRCMSlowClkCtrGet
+#define MAP_PRCMSlowClkCtrGet \
+ ROM_PRCMSlowClkCtrGet
+#else
+#define MAP_PRCMSlowClkCtrGet \
+ PRCMSlowClkCtrGet
+#endif
+#ifdef ROM_PRCMSlowClkCtrMatchSet
+#define MAP_PRCMSlowClkCtrMatchSet \
+ ROM_PRCMSlowClkCtrMatchSet
+#else
+#define MAP_PRCMSlowClkCtrMatchSet \
+ PRCMSlowClkCtrMatchSet
+#endif
+#ifdef ROM_PRCMSlowClkCtrMatchGet
+#define MAP_PRCMSlowClkCtrMatchGet \
+ ROM_PRCMSlowClkCtrMatchGet
+#else
+#define MAP_PRCMSlowClkCtrMatchGet \
+ PRCMSlowClkCtrMatchGet
+#endif
+#ifdef ROM_PRCMOCRRegisterWrite
+#define MAP_PRCMOCRRegisterWrite \
+ ROM_PRCMOCRRegisterWrite
+#else
+#define MAP_PRCMOCRRegisterWrite \
+ PRCMOCRRegisterWrite
+#endif
+#ifdef ROM_PRCMOCRRegisterRead
+#define MAP_PRCMOCRRegisterRead \
+ ROM_PRCMOCRRegisterRead
+#else
+#define MAP_PRCMOCRRegisterRead \
+ PRCMOCRRegisterRead
+#endif
+#ifdef ROM_PRCMIntRegister
+#define MAP_PRCMIntRegister \
+ ROM_PRCMIntRegister
+#else
+#define MAP_PRCMIntRegister \
+ PRCMIntRegister
+#endif
+#ifdef ROM_PRCMIntUnregister
+#define MAP_PRCMIntUnregister \
+ ROM_PRCMIntUnregister
+#else
+#define MAP_PRCMIntUnregister \
+ PRCMIntUnregister
+#endif
+#ifdef ROM_PRCMIntEnable
+#define MAP_PRCMIntEnable \
+ ROM_PRCMIntEnable
+#else
+#define MAP_PRCMIntEnable \
+ PRCMIntEnable
+#endif
+#ifdef ROM_PRCMIntDisable
+#define MAP_PRCMIntDisable \
+ ROM_PRCMIntDisable
+#else
+#define MAP_PRCMIntDisable \
+ PRCMIntDisable
+#endif
+#ifdef ROM_PRCMIntStatus
+#define MAP_PRCMIntStatus \
+ ROM_PRCMIntStatus
+#else
+#define MAP_PRCMIntStatus \
+ PRCMIntStatus
+#endif
+#ifdef ROM_PRCMRTCInUseSet
+#define MAP_PRCMRTCInUseSet \
+ ROM_PRCMRTCInUseSet
+#else
+#define MAP_PRCMRTCInUseSet \
+ PRCMRTCInUseSet
+#endif
+#ifdef ROM_PRCMRTCInUseGet
+#define MAP_PRCMRTCInUseGet \
+ ROM_PRCMRTCInUseGet
+#else
+#define MAP_PRCMRTCInUseGet \
+ PRCMRTCInUseGet
+#endif
+#ifdef ROM_PRCMRTCSet
+#define MAP_PRCMRTCSet \
+ ROM_PRCMRTCSet
+#else
+#define MAP_PRCMRTCSet \
+ PRCMRTCSet
+#endif
+#ifdef ROM_PRCMRTCGet
+#define MAP_PRCMRTCGet \
+ ROM_PRCMRTCGet
+#else
+#define MAP_PRCMRTCGet \
+ PRCMRTCGet
+#endif
+#ifdef ROM_PRCMRTCMatchSet
+#define MAP_PRCMRTCMatchSet \
+ ROM_PRCMRTCMatchSet
+#else
+#define MAP_PRCMRTCMatchSet \
+ PRCMRTCMatchSet
+#endif
+#ifdef ROM_PRCMRTCMatchGet
+#define MAP_PRCMRTCMatchGet \
+ ROM_PRCMRTCMatchGet
+#else
+#define MAP_PRCMRTCMatchGet \
+ PRCMRTCMatchGet
+#endif
+#ifdef ROM_PRCMLPDSRestoreInfoSet
+#define MAP_PRCMLPDSRestoreInfoSet \
+ ROM_PRCMLPDSRestoreInfoSet
+#else
+#define MAP_PRCMLPDSRestoreInfoSet \
+ PRCMLPDSRestoreInfoSet
+#endif
+
+#ifdef ROM_PRCMHIBRegRead
+#define MAP_PRCMHIBRegRead \
+ ROM_PRCMHIBRegRead
+#else
+#define MAP_PRCMHIBRegRead \
+ PRCMHIBRegRead
+#endif
+
+#ifdef ROM_PRCMHIBRegWrite
+#define MAP_PRCMHIBRegWrite \
+ ROM_PRCMHIBRegWrite
+#else
+#define MAP_PRCMHIBRegWrite \
+ PRCMHIBRegWrite
+#endif
+
+//*****************************************************************************
+//
+// Macros for the HWSPINLOCK API.
+//
+//*****************************************************************************
+#ifdef ROM_HwSpinLockAcquire
+#define MAP_HwSpinLockAcquire \
+ ROM_HwSpinLockAcquire
+#else
+#define MAP_HwSpinLockAcquire \
+ HwSpinLockAcquire
+#endif
+#ifdef ROM_HwSpinLockTryAcquire
+#define MAP_HwSpinLockTryAcquire \
+ ROM_HwSpinLockTryAcquire
+#else
+#define MAP_HwSpinLockTryAcquire \
+ HwSpinLockTryAcquire
+#endif
+#ifdef ROM_HwSpinLockRelease
+#define MAP_HwSpinLockRelease \
+ ROM_HwSpinLockRelease
+#else
+#define MAP_HwSpinLockRelease \
+ HwSpinLockRelease
+#endif
+#ifdef ROM_HwSpinLockTest
+#define MAP_HwSpinLockTest \
+ ROM_HwSpinLockTest
+#else
+#define MAP_HwSpinLockTest \
+ HwSpinLockTest
+#endif
+
+//*****************************************************************************
+//
+// Macros for the ADC API.
+//
+//*****************************************************************************
+#ifdef ROM_ADCEnable
+#define MAP_ADCEnable \
+ ROM_ADCEnable
+#else
+#define MAP_ADCEnable \
+ ADCEnable
+#endif
+#ifdef ROM_ADCDisable
+#define MAP_ADCDisable \
+ ROM_ADCDisable
+#else
+#define MAP_ADCDisable \
+ ADCDisable
+#endif
+#ifdef ROM_ADCChannelEnable
+#define MAP_ADCChannelEnable \
+ ROM_ADCChannelEnable
+#else
+#define MAP_ADCChannelEnable \
+ ADCChannelEnable
+#endif
+#ifdef ROM_ADCChannelDisable
+#define MAP_ADCChannelDisable \
+ ROM_ADCChannelDisable
+#else
+#define MAP_ADCChannelDisable \
+ ADCChannelDisable
+#endif
+#ifdef ROM_ADCIntRegister
+#define MAP_ADCIntRegister \
+ ROM_ADCIntRegister
+#else
+#define MAP_ADCIntRegister \
+ ADCIntRegister
+#endif
+#ifdef ROM_ADCIntUnregister
+#define MAP_ADCIntUnregister \
+ ROM_ADCIntUnregister
+#else
+#define MAP_ADCIntUnregister \
+ ADCIntUnregister
+#endif
+#ifdef ROM_ADCIntEnable
+#define MAP_ADCIntEnable \
+ ROM_ADCIntEnable
+#else
+#define MAP_ADCIntEnable \
+ ADCIntEnable
+#endif
+#ifdef ROM_ADCIntDisable
+#define MAP_ADCIntDisable \
+ ROM_ADCIntDisable
+#else
+#define MAP_ADCIntDisable \
+ ADCIntDisable
+#endif
+#ifdef ROM_ADCIntStatus
+#define MAP_ADCIntStatus \
+ ROM_ADCIntStatus
+#else
+#define MAP_ADCIntStatus \
+ ADCIntStatus
+#endif
+#ifdef ROM_ADCIntClear
+#define MAP_ADCIntClear \
+ ROM_ADCIntClear
+#else
+#define MAP_ADCIntClear \
+ ADCIntClear
+#endif
+#ifdef ROM_ADCDMAEnable
+#define MAP_ADCDMAEnable \
+ ROM_ADCDMAEnable
+#else
+#define MAP_ADCDMAEnable \
+ ADCDMAEnable
+#endif
+#ifdef ROM_ADCDMADisable
+#define MAP_ADCDMADisable \
+ ROM_ADCDMADisable
+#else
+#define MAP_ADCDMADisable \
+ ADCDMADisable
+#endif
+#ifdef ROM_ADCChannelGainSet
+#define MAP_ADCChannelGainSet \
+ ROM_ADCChannelGainSet
+#else
+#define MAP_ADCChannelGainSet \
+ ADCChannelGainSet
+#endif
+#ifdef ROM_ADCChannleGainGet
+#define MAP_ADCChannleGainGet \
+ ROM_ADCChannleGainGet
+#else
+#define MAP_ADCChannleGainGet \
+ ADCChannleGainGet
+#endif
+#ifdef ROM_ADCTimerConfig
+#define MAP_ADCTimerConfig \
+ ROM_ADCTimerConfig
+#else
+#define MAP_ADCTimerConfig \
+ ADCTimerConfig
+#endif
+#ifdef ROM_ADCTimerEnable
+#define MAP_ADCTimerEnable \
+ ROM_ADCTimerEnable
+#else
+#define MAP_ADCTimerEnable \
+ ADCTimerEnable
+#endif
+#ifdef ROM_ADCTimerDisable
+#define MAP_ADCTimerDisable \
+ ROM_ADCTimerDisable
+#else
+#define MAP_ADCTimerDisable \
+ ADCTimerDisable
+#endif
+#ifdef ROM_ADCTimerReset
+#define MAP_ADCTimerReset \
+ ROM_ADCTimerReset
+#else
+#define MAP_ADCTimerReset \
+ ADCTimerReset
+#endif
+#ifdef ROM_ADCTimerValueGet
+#define MAP_ADCTimerValueGet \
+ ROM_ADCTimerValueGet
+#else
+#define MAP_ADCTimerValueGet \
+ ADCTimerValueGet
+#endif
+#ifdef ROM_ADCFIFOLvlGet
+#define MAP_ADCFIFOLvlGet \
+ ROM_ADCFIFOLvlGet
+#else
+#define MAP_ADCFIFOLvlGet \
+ ADCFIFOLvlGet
+#endif
+#ifdef ROM_ADCFIFORead
+#define MAP_ADCFIFORead \
+ ROM_ADCFIFORead
+#else
+#define MAP_ADCFIFORead \
+ ADCFIFORead
+#endif
+
+#endif // __ROM_MAP_H__
diff --git a/cc3200/hal/rom_patch.h b/cc3200/hal/rom_patch.h
new file mode 100644
index 0000000000..4df44bd5d0
--- /dev/null
+++ b/cc3200/hal/rom_patch.h
@@ -0,0 +1,87 @@
+//*****************************************************************************
+//
+// rom_patch.h
+//
+// Macros to facilitate patching driverlib API's in the ROM.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+// List of API's in the ROM that need to be patched.
+// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut
+//*****************************************************************************
+#undef ROM_ADCIntClear
+#undef ROM_IntEnable
+#undef ROM_IntDisable
+#undef ROM_IntPendSet
+#undef ROM_PRCMHibernateWakeUpGPIOSelect
+#undef ROM_SDHostCardErrorMaskSet
+#undef ROM_SDHostCardErrorMaskGet
+#undef ROM_TimerConfigure
+#undef ROM_TimerDMAEventSet
+#undef ROM_TimerDMAEventGet
+#undef ROM_SDHostDataNonBlockingWrite
+#undef ROM_SDHostDataWrite
+#undef ROM_SDHostDataRead
+#undef ROM_SDHostDataNonBlockingRead
+#undef ROM_PRCMSysResetCauseGet
+#undef ROM_PRCMPeripheralClkEnable
+#undef ROM_PRCMLPDSWakeUpGPIOSelect
+#undef ROM_PRCMHibernateWakeupSourceEnable
+#undef ROM_PRCMHibernateWakeupSourceDisable
+#undef ROM_PRCMHibernateWakeupCauseGet
+#undef ROM_PRCMHibernateIntervalSet
+#undef ROM_PRCMHibernateWakeUpGPIOSelect
+#undef ROM_PRCMHibernateEnter
+#undef ROM_PRCMSlowClkCtrGet
+#undef ROM_PRCMSlowClkCtrMatchSet
+#undef ROM_PRCMSlowClkCtrMatchGet
+#undef ROM_PRCMOCRRegisterWrite
+#undef ROM_PRCMOCRRegisterRead
+#undef ROM_PRCMIntEnable
+#undef ROM_PRCMIntDisable
+#undef ROM_PRCMRTCInUseSet
+#undef ROM_PRCMRTCInUseGet
+#undef ROM_PRCMRTCSet
+#undef ROM_PRCMRTCGet
+#undef ROM_PRCMRTCMatchSet
+#undef ROM_PRCMRTCMatchGet
+#undef ROM_PRCMPeripheralClkDisable
+#undef ROM_PRCMPeripheralReset
+#undef ROM_PRCMPeripheralStatusGet
+#undef ROM_SPIConfigSetExpClk
+#undef ROM_GPIODirModeGet
+#undef ROM_GPIOIntTypeGet
+
diff --git a/cc3200/hal/sdhost.c b/cc3200/hal/sdhost.c
new file mode 100644
index 0000000000..daae8d2e66
--- /dev/null
+++ b/cc3200/hal/sdhost.c
@@ -0,0 +1,744 @@
+//*****************************************************************************
+//
+// sdhost.c
+//
+// Driver for the SD Host (SDHost) Interface
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup Secure_Digital_Host_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_mmchs.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_apps_config.h"
+#include "interrupt.h"
+#include "sdhost.h"
+
+
+//*****************************************************************************
+//
+//! Configures SDHost module.
+//!
+//! \param ulBase is the base address of SDHost module.
+//!
+//! This function configures the SDHost module, enabling internal sub-modules.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostInit(unsigned long ulBase)
+{
+ //
+ // Assert module reset
+ //
+ HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2;
+
+ //
+ // Wait for soft reset to complete
+ //
+ while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) )
+ {
+
+ }
+
+ //
+ // Assert internal reset
+ //
+ HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24);
+
+ //
+ // Wait for Reset to complete
+ //
+ while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) )
+ {
+
+ }
+
+ //
+ // Set capability register, 1.8 and 3.0 V
+ //
+ HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24);
+
+ //
+ // Select bus voltage, 3.0 V
+ //
+ HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9;
+
+ //
+ // Power up the bus
+ //
+ HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8;
+
+ //
+ // Wait for power on
+ //
+ while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) )
+ {
+
+ }
+
+ HWREG(ulBase + MMCHS_O_CON) |= 1 << 21;
+
+ //
+ // Un-mask all events
+ //
+ HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF;
+}
+
+
+//*****************************************************************************
+//
+//! Resets SDHost command line
+//!
+//! \param ulBase is the base address of SDHost module.
+//!
+//! This function assers a soft reset for the command line
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostCmdReset(unsigned long ulBase)
+{
+ HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25;
+ while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) )
+ {
+
+ }
+}
+
+//*****************************************************************************
+//
+//! Sends command over SDHost interface
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param ulCmd is the command to send.
+//! \param ulArg is the argument for the command.
+//!
+//! This function send command to the attached card over the SDHost interface.
+//!
+//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63.
+//! It can be logically ORed with one or more of the following:
+//! - \b SDHOST_MULTI_BLK for multi-block transfer
+//! - \b SDHOST_WR_CMD if command is followed by write data
+//! - \b SDHOST_RD_CMD if command is followed by read data
+//! - \b SDHOST_DMA_EN if SDHost need to generate DMA request.
+//! - \b SDHOST_RESP_LEN_136 if 136 bit response is expected
+//! - \b SDHOST_RESP_LEN_48 if 48 bit response is expected
+//! - \b SDHOST_RESP_LEN_48B if 48 bit response with busy bit is expected
+//!
+//! The parameter \e ulArg is the argument for the command
+//!
+//! \return Returns 0 on success, -1 otherwise.
+//
+//*****************************************************************************
+long
+SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg)
+{
+ //
+ // Set Data Timeout
+ //
+ HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000;
+
+ //
+ // Check for cmd inhabit
+ //
+ if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1))
+ {
+ return -1;
+ }
+
+ //
+ // Set the argument
+ //
+ HWREG(ulBase + MMCHS_O_ARG) = ulArg;
+
+ //
+ // Send the command
+ //
+ HWREG(ulBase + MMCHS_O_CMD) = ulCmd;
+
+ return 0;
+}
+
+//*****************************************************************************
+//
+//! Writes a data word into the SDHost write buffer.
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param ulData is data word to be transfered.
+//!
+//! This function writes a single data word into the SDHost write buffer. The
+//! function returns \b true if there was a space available in the buffer else
+//! returns \b false.
+//!
+//! \return Return \b true on success, \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData)
+{
+
+ //
+ // See if there is a space in the write buffer
+ //
+ if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
+ {
+ //
+ // Write the data into the buffer
+ //
+ HWREG(ulBase + MMCHS_O_DATA) = ulData;
+
+ //
+ // Success.
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // No free sapce, failure.
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits to write a data word into the SDHost write buffer.
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param ulData is data word to be transfered.
+//!
+//! This function writes \e ulData into the SDHost write buffer. If there is no
+//! space in the write buffer this function waits until there is a space
+//! available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostDataWrite(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Wait until space is available
+ //
+ while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
+ {
+
+ }
+
+ //
+ // Write the data
+ //
+ HWREG(ulBase + MMCHS_O_DATA) = ulData;
+}
+
+
+//*****************************************************************************
+//
+//! Waits for a data word from the SDHost read buffer
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param pulData is pointer to read data variable.
+//!
+//! This function reads a single data word from the SDHost read buffer. If there
+//! is no data available in the buffer the function will wait until a data
+//! word is received before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostDataRead(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Wait until data is available
+ //
+ while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) )
+ {
+
+ }
+
+ //
+ // Read the data
+ //
+ *pulData = HWREG(ulBase + MMCHS_O_DATA);
+}
+
+//*****************************************************************************
+//
+//! Reads single data word from the SDHost read buffer
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param pulData is pointer to read data variable.
+//!
+//! This function reads a data word from the SDHost read buffer. The
+//! function returns \b true if there was data available in to buffer else
+//! returns \b false.
+//!
+//! \return Return \b true on success, \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData)
+{
+
+ //
+ // See if there is any data in the read buffer.
+ //
+ if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<11)) )
+ {
+ //
+ // Read the data word.
+ //
+ *pulData = HWREG(ulBase + MMCHS_O_DATA);
+
+ //
+ // Success
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // No data available, failure.
+ //
+ return(false);
+ }
+}
+
+
+//*****************************************************************************
+//
+//! Registers the interrupt handler for SDHost interrupt
+//!
+//! \param ulBase is the base address of SDHost module
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SDHost interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller; specific
+//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the
+//! interrupt handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_MMCHS, pfnHandler);
+
+ //
+ // Enable the SDHost interrupt.
+ //
+ IntEnable(INT_MMCHS);
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for SDHost interrupt
+//!
+//! \param ulBase is the base address of SDHost module
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a SDHost interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostIntUnregister(unsigned long ulBase)
+{
+ //
+ // Disable the SDHost interrupt.
+ //
+ IntDisable(INT_MMCHS);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_MMCHS);
+}
+
+//*****************************************************************************
+//
+//! Enable individual interrupt source for the specified SDHost
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated SDHost interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//! - \b SDHOST_INT_CC Command Complete interrupt
+//! - \b SDHOST_INT_TC Transfer Complete interrupt
+//! - \b SDHOST_INT_BWR Buffer Write Ready interrupt
+//! - \b SDHOST_INT_BRR Buffer Read Ready interrupt
+//! - \b SDHOST_INT_ERRI Error interrupt
+//! - \b SDHOST_INT_CTO Command Timeout error interrupt
+//! - \b SDHOST_INT_CEB Command End Bit error interrupt
+//! - \b SDHOST_INT_DTO Data Timeout error interrupt
+//! - \b SDHOST_INT_DCRC Data CRC error interrupt
+//! - \b SDHOST_INT_DEB Data End Bit error
+//! - \b SDHOST_INT_CERR Cart Status Error interrupt
+//! - \b SDHOST_INT_BADA Bad Data error interrupt
+//! - \b SDHOST_INT_DMARD Read DMA done interrupt
+//! - \b SDHOST_INT_DMAWR Write DMA done interrupt
+//!
+//! Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus()
+//! and is internally logical OR of all error status bits. Setting this bit
+//! alone as \e ulIntFlags doesn't generates any interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags)
+{
+ //
+ // Enable DMA done interrupts
+ //
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) =
+ (ulIntFlags >> 30);
+
+ //
+ // Enable the individual interrupt sources
+ //
+ HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF);
+}
+
+//*****************************************************************************
+//
+//! Enable individual interrupt source for the specified SDHost
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
+//!
+//! This function disables the indicated SDHost interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to SDHostIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags)
+{
+ //
+ // Disable DMA done interrupts
+ //
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) =
+ (ulIntFlags >> 30);
+ //
+ // Disable the individual interrupt sources
+ //
+ HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of SDHost module.
+//!
+//! This function returns the interrupt status for the specified SDHost.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in SDHostIntEnable().
+//
+//*****************************************************************************
+unsigned long
+SDHostIntStatus(unsigned long ulBase)
+{
+ unsigned long ulIntStatus;
+
+ //
+ // Get DMA done interrupt status
+ //
+ ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET);
+ ulIntStatus = (ulIntStatus << 30);
+
+ //
+ // Return the status of individual interrupt sources
+ //
+ ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF);
+
+ return(ulIntStatus);
+}
+
+//*****************************************************************************
+//
+//! Clears the individual interrupt sources.
+//!
+//! \param ulBase is the base address of SDHost module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified SDHost interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to SDHostIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags)
+{
+ //
+ // Clear DMA done interrupts
+ //
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) =
+ (ulIntFlags >> 30);
+ //
+ // Clear the individual interrupt sources
+ //
+ HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF);
+}
+
+//*****************************************************************************
+//
+//! Sets the card status error mask.
+//!
+//! \param ulBase is the base address of SDHost module
+//! \param ulErrMask is the bit mask of card status errors to be enabled
+//!
+//! This function sets the card status error mask for response type R1, R1b,
+//! R5, R5b and R6 response. The parameter \ulErrMask is the bit mask of card
+//! status errors to be enabled, if the corresponding bits in the 'card status'
+//! field of a respose are set then the host controller indicates a card error
+//! interrupt status. Only bits referenced as type E (error) in status field in
+//! the response can set a card status error.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask)
+{
+ //
+ // Set the card status error mask
+ //
+ HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask;
+}
+
+
+//*****************************************************************************
+//
+//! Gets the card status error mask.
+//!
+//! \param ulBase is the base address of SDHost module
+//!
+//! This function gets the card status error mask for response type R1, R1b,
+//! R5, R5b and R6 response.
+//!
+//! \return Returns the current card status error.
+//
+//*****************************************************************************
+unsigned long
+SDHostCardErrorMaskGet(unsigned long ulBase)
+{
+ //
+ // Return the card status error mask
+ //
+ return(HWREG(ulBase + MMCHS_O_CSRE));
+}
+
+//*****************************************************************************
+//
+//! Sets the SD Card clock.
+//!
+//! \param ulBase is the base address of SDHost module
+//! \param ulSDHostClk is the rate of clock supplied to SDHost module
+//! \param ulCardClk is the required SD interface clock
+//!
+//! This function configures the SDHost interface to supply the specified clock
+//! to the connected card.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
+ unsigned long ulCardClk)
+{
+ unsigned long ulDiv;
+
+ //
+ // Disable card clock
+ //
+ HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4;
+
+ //
+ // Enable internal clock
+ //
+ HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1;
+
+ ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF);
+
+ //
+ // Set clock divider,
+ //
+ HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) &
+ ~0x0000FFC0)| (ulDiv) << 6);
+
+ //
+ // Wait for clock to stablize
+ //
+ while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) )
+ {
+
+ }
+
+ //
+ // Enable card clock
+ //
+ HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4;
+}
+
+//*****************************************************************************
+//
+//! Get the response for the last command.
+//!
+//! \param ulBase is the base address of SDHost module
+//! \param ulRespnse is 128-bit response.
+//!
+//! This function gets the response from the SD card for the last command
+//! send.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4])
+{
+
+ //
+ // Read the responses.
+ //
+ ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10);
+ ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32);
+ ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54);
+ ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76);
+
+}
+
+//*****************************************************************************
+//
+//! Set the block size for data transfer
+//!
+//! \param ulBase is the base address of SDHost module
+//! \param ulBlkSize is the transfer block size in bytes
+//!
+//! This function sets the block size the data transfer.
+//!
+//! The parameter \e ulBlkSize is size of each data block in bytes.
+//! This should be in range 0 - 2^10.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize)
+{
+ //
+ // Set the block size
+ //
+ HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)|
+ (ulBlkSize & 0xFFF));
+}
+
+//*****************************************************************************
+//
+//! Set the block size and count for data transfer
+//!
+//! \param ulBase is the base address of SDHost module
+//! \param ulBlkCount is the number of blocks
+//!
+//! This function sets block count for the data transfer. This needs to be set
+//! for each block transfer. \sa SDHostBlockSizeSet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read the current value
+ //
+ ulRegVal = HWREG(ulBase + MMCHS_O_BLK);
+
+ //
+ // Set the number of blocks
+ //
+ HWREG(ulBase + MMCHS_O_BLK) |= ((ulRegVal & 0x0000FFFF)|
+ (ulBlkCount << 16));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/sdhost.h b/cc3200/hal/sdhost.h
new file mode 100644
index 0000000000..404655535e
--- /dev/null
+++ b/cc3200/hal/sdhost.h
@@ -0,0 +1,204 @@
+//*****************************************************************************
+//
+// sdhost.h
+//
+// Defines and Macros for the SDHost.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __SDHOST_H__
+#define __SDHOST_H__
+
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+//{
+#endif
+
+
+//*****************************************************************************
+// Values that can be passed to SDHostRespGet().
+//*****************************************************************************
+#define SDHOST_RESP_10 0x00000003
+#define SDHOST_RESP_32 0x00000002
+#define SDHOST_RESP_54 0x00000001
+#define SDHOST_RESP_76 0x00000000
+
+
+//*****************************************************************************
+// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(),
+// SDHostIntClear() ,and returned from SDHostIntStatus().
+//*****************************************************************************
+#define SDHOST_INT_CC 0x00000001
+#define SDHOST_INT_TC 0x00000002
+#define SDHOST_INT_BWR 0x00000010
+#define SDHOST_INT_BRR 0x00000020
+#define SDHOST_INT_ERRI 0x00008000
+#define SDHOST_INT_CTO 0x00010000
+#define SDHOST_INT_CEB 0x00040000
+#define SDHOST_INT_DTO 0x00100000
+#define SDHOST_INT_DCRC 0x00200000
+#define SDHOST_INT_DEB 0x00300000
+#define SDHOST_INT_CERR 0x10000000
+#define SDHOST_INT_BADA 0x20000000
+#define SDHOST_INT_DMARD 0x40000000
+#define SDHOST_INT_DMAWR 0x80000000
+
+//*****************************************************************************
+// Values that can be passed to SDHostCmdSend().
+//*****************************************************************************
+#define SDHOST_CMD_0 0x00000000
+#define SDHOST_CMD_1 0x01000000
+#define SDHOST_CMD_2 0x02000000
+#define SDHOST_CMD_3 0x03000000
+#define SDHOST_CMD_4 0x04000000
+#define SDHOST_CMD_5 0x05000000
+#define SDHOST_CMD_6 0x06000000
+#define SDHOST_CMD_7 0x07000000
+#define SDHOST_CMD_8 0x08000000
+#define SDHOST_CMD_9 0x09000000
+#define SDHOST_CMD_10 0x0A000000
+#define SDHOST_CMD_11 0x0B000000
+#define SDHOST_CMD_12 0x0C000000
+#define SDHOST_CMD_13 0x0D000000
+#define SDHOST_CMD_14 0x0E000000
+#define SDHOST_CMD_15 0x0F000000
+#define SDHOST_CMD_16 0x10000000
+#define SDHOST_CMD_17 0x11000000
+#define SDHOST_CMD_18 0x12000000
+#define SDHOST_CMD_19 0x13000000
+#define SDHOST_CMD_20 0x14000000
+#define SDHOST_CMD_21 0x15000000
+#define SDHOST_CMD_22 0x16000000
+#define SDHOST_CMD_23 0x17000000
+#define SDHOST_CMD_24 0x18000000
+#define SDHOST_CMD_25 0x19000000
+#define SDHOST_CMD_26 0x1A000000
+#define SDHOST_CMD_27 0x1B000000
+#define SDHOST_CMD_28 0x1C000000
+#define SDHOST_CMD_29 0x1D000000
+#define SDHOST_CMD_30 0x1E000000
+#define SDHOST_CMD_31 0x1F000000
+#define SDHOST_CMD_32 0x20000000
+#define SDHOST_CMD_33 0x21000000
+#define SDHOST_CMD_34 0x22000000
+#define SDHOST_CMD_35 0x23000000
+#define SDHOST_CMD_36 0x24000000
+#define SDHOST_CMD_37 0x25000000
+#define SDHOST_CMD_38 0x26000000
+#define SDHOST_CMD_39 0x27000000
+#define SDHOST_CMD_40 0x28000000
+#define SDHOST_CMD_41 0x29000000
+#define SDHOST_CMD_42 0x2A000000
+#define SDHOST_CMD_43 0x2B000000
+#define SDHOST_CMD_44 0x2C000000
+#define SDHOST_CMD_45 0x2D000000
+#define SDHOST_CMD_46 0x2E000000
+#define SDHOST_CMD_47 0x2F000000
+#define SDHOST_CMD_48 0x30000000
+#define SDHOST_CMD_49 0x31000000
+#define SDHOST_CMD_50 0x32000000
+#define SDHOST_CMD_51 0x33000000
+#define SDHOST_CMD_52 0x34000000
+#define SDHOST_CMD_53 0x35000000
+#define SDHOST_CMD_54 0x36000000
+#define SDHOST_CMD_55 0x37000000
+#define SDHOST_CMD_56 0x38000000
+#define SDHOST_CMD_57 0x39000000
+#define SDHOST_CMD_58 0x3A000000
+#define SDHOST_CMD_59 0x3B000000
+#define SDHOST_CMD_60 0x3C000000
+#define SDHOST_CMD_61 0x3D000000
+#define SDHOST_CMD_62 0x3E000000
+#define SDHOST_CMD_63 0x3F000000
+
+//*****************************************************************************
+// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend().
+//*****************************************************************************
+#define SDHOST_MULTI_BLK 0x00000022
+#define SDHOST_DMA_EN 0x00000001
+#define SDHOST_WR_CMD 0x00200000
+#define SDHOST_RD_CMD 0x00200010
+#define SDHOST_RESP_LEN_136 0x00010000
+#define SDHOST_RESP_LEN_48 0x00020000
+#define SDHOST_RESP_LEN_48B 0x00030000
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void SDHostCmdReset(unsigned long ulBase);
+extern void SDHostInit(unsigned long ulBase);
+extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd,
+ unsigned ulArg);
+extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
+extern void SDHostIntUnregister(unsigned long ulBase);
+extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags);
+extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags);
+extern unsigned long SDHostIntStatus(unsigned long ulBase);
+extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags);
+extern void SDHostCardErrorMaskSet(unsigned long ulBase,
+ unsigned long ulErrMask);
+extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase);
+extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
+ unsigned long ulCardClk);
+extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]);
+extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize);
+extern void SDHostBlockCountSet(unsigned long ulBase,
+ unsigned short ulBlkCount);
+extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase,
+ unsigned long ulData);
+extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase,
+ unsigned long *pulData);
+extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData);
+extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+//}
+#endif
+
+#endif // __SDHOST_H__
diff --git a/cc3200/hal/shamd5.c b/cc3200/hal/shamd5.c
new file mode 100644
index 0000000000..6a3cc1cc30
--- /dev/null
+++ b/cc3200/hal/shamd5.c
@@ -0,0 +1,1085 @@
+//*****************************************************************************
+//
+// shamd5.c
+//
+// Driver for the SHA/MD5 module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup SHA_Secure_Hash_Algorithm_api
+//! @{
+//
+//*****************************************************************************
+
+#include
+#include
+#include "inc/hw_dthe.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_shamd5.h"
+#include "inc/hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "shamd5.h"
+#include "rom_map.h"
+
+#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5
+#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1
+#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224
+#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256
+
+//*****************************************************************************
+//
+//! Enables the uDMA requests in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//!
+//! This function configures the DMA options of the SHA/MD5 module.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5DMAEnable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Write the new configuration into the register.
+ //
+ HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |=
+ SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN;
+}
+
+//*****************************************************************************
+//
+//! Disables the uDMA requests in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//!
+//! This function configures the DMA options of the SHA/MD5 module.
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5DMADisable(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Write the new configuration into the register.
+ //
+ HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &=
+ ~(SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN);
+}
+
+//*****************************************************************************
+//
+//! Get the interrupt status of the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the current value of the IRQSTATUS register. The
+//! value will be a logical OR of the following:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//! a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return Interrupt status
+//
+//*****************************************************************************
+uint32_t
+SHAMD5IntStatus(uint32_t ui32Base, bool bMasked)
+{
+ uint32_t ui32Temp;
+ uint32_t ui32IrqEnable;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Return the value of the IRQSTATUS register.
+ //
+ if(bMasked)
+ {
+ ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS);
+ ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE);
+ return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) &
+ ui32IrqEnable) | (ui32Temp & 0x00000007) << 16);
+ }
+ else
+ {
+ ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS);
+ return(HWREG(ui32Base + SHAMD5_O_IRQSTATUS) |
+ (ui32Temp & 0x00000007) << 16);
+
+ }
+}
+
+//*****************************************************************************
+//
+//! Enable interrupt sources in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32IntFlags contains desired interrupts to enable.
+//!
+//! This function enables interrupt sources in the SHA/MD5 module.
+//! ui32IntFlags must be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//! a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+ ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
+ (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
+ (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
+ (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
+
+ //
+ // Enable the interrupt sources.
+ //
+ HWREG(DTHE_BASE + DTHE_O_SHA_IM) &= ~((ui32IntFlags & 0x00070000) >> 16);
+ HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
+
+ //
+ // Enable all interrupts.
+ //
+ HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_PIT_EN;
+}
+
+//*****************************************************************************
+//
+//! Disable interrupt sources in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32IntFlags contains desired interrupts to disable.
+//!
+//! \e ui32IntFlags must be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//! a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+ ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
+ (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
+ (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
+ (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
+
+ //
+ // Clear the corresponding flags disabling the interrupt sources.
+ //
+ HWREG(DTHE_BASE + DTHE_O_SHA_IM) |= ((ui32IntFlags & 0x00070000) >> 16);
+ HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
+
+ //
+ // If there are no interrupts enabled, then disable all interrupts.
+ //
+ if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0)
+ {
+ HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_PIT_EN;
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears interrupt sources in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32IntFlags contains desired interrupts to disable.
+//!
+//! \e ui32IntFlags must be a logical OR of one or more of the following
+//! values:
+//!
+//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready.
+//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after
+//! a context switch.
+//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data.
+//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+ ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) ||
+ (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) ||
+ (ui32IntFlags == SHAMD5_INT_INPUT_READY) ||
+ (ui32IntFlags == SHAMD5_INT_OUTPUT_READY));
+
+ //
+ // Clear the corresponding flags disabling the interrupt sources.
+ //
+ HWREG(DTHE_BASE + DTHE_O_SHA_IC) = ((ui32IntFlags & 0x00070000) >> 16);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! enabled SHA/MD5 interrupts occur.
+//!
+//! This function registers the interrupt handler in the interrupt vector
+//! table, and enables SHA/MD5 interrupts on the interrupt controller;
+//! specific SHA/MD5 interrupt sources must be enabled using
+//! SHAMD5IntEnable(). The interrupt handler being registered must clear
+//! the source of the interrupt using SHAMD5IntClear().
+//!
+//! If the application is using a static interrupt vector table stored in
+//! flash, then it is not necessary to register the interrupt handler this way.
+//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the
+//! interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_SHA, pfnHandler);
+
+ //
+ // Enable the interrupt
+ //
+ IntEnable(INT_SHA);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//!
+//! This function unregisters the previously registered interrupt handler and
+//! disables the interrupt in the interrupt controller.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5IntUnregister(uint32_t ui32Base)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(INT_SHA);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_SHA);
+}
+
+//*****************************************************************************
+//
+//! Write the hash length to the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32Length is the hash length in bytes.
+//!
+//! This function writes the length of the hash data of the current operation
+//! to the SHA/MD5 module. The value must be a multiple of 64 if the close
+//! hash is not set in the mode register.
+//!
+//! \note When this register is written, hash processing is triggered.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Set the LENGTH register and start processing.
+ //
+ HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length;
+}
+
+//*****************************************************************************
+//
+//! Writes the mode in the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param ui32Mode is the mode of the SHA/MD5 module.
+//!
+//! This function writes the mode register configuring the SHA/MD5 module.
+//!
+//! The ui32Mode paramerter is a bit-wise OR of values:
+//!
+//! - \b SHAMD5_ALGO_MD5 - Regular hash with MD5
+//! - \b SHAMD5_ALGO_SHA1 - Regular hash with SHA-1
+//! - \b SHAMD5_ALGO_SHA224 - Regular hash with SHA-224
+//! - \b SHAMD5_ALGO_SHA256 - Regular hash with SHA-256
+//! - \b SHAMD5_ALGO_HMAC_MD5 - HMAC with MD5
+//! - \b SHAMD5_ALGO_HMAC_SHA1 - HMAC with SHA-1
+//! - \b SHAMD5_ALGO_HMAC_SHA224 - HMAC with SHA-224
+//! - \b SHAMD5_ALGO_HMAC_SHA256 - HMAC with SHA-256
+//!
+//! \return None
+//
+//*****************************************************************************
+void
+SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32Mode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+ ASSERT((ui32Mode == SHAMD5_ALGO_MD5) ||
+ (ui32Mode == SHAMD5_ALGO_SHA1) ||
+ (ui32Mode == SHAMD5_ALGO_SHA224) ||
+ (ui32Mode == SHAMD5_ALGO_SHA256) ||
+ (ui32Mode == SHAMD5_ALGO_HMAC_MD5) ||
+ (ui32Mode == SHAMD5_ALGO_HMAC_SHA1) ||
+ (ui32Mode == SHAMD5_ALGO_HMAC_SHA224) ||
+ (ui32Mode == SHAMD5_ALGO_HMAC_SHA256));
+
+ //
+ // Write the value in the MODE register.
+ //
+ HWREG(ui32Base + SHAMD5_O_MODE) = ui32Mode;
+}
+
+//*****************************************************************************
+//
+//! Perform a non-blocking write of 16 words of data to the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui8Src is the pointer to the 16-word array of data that will be
+//! written.
+//!
+//! This function writes 16 words of data into the data register.
+//!
+//! \return This function returns true if the write completed successfully.
+//! It returns false if the module was not ready.
+//
+//*****************************************************************************
+bool
+SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src)
+{
+ uint32_t ui8Counter;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Check that the SHA/MD5 module is ready for data. If not, return false.
+ //
+ if((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
+ {
+ return(false);
+ }
+
+ //
+ // Write the 16 words of data.
+ //
+ for(ui8Counter = 0; ui8Counter < 64; ui8Counter += 4)
+ {
+ HWREG(ui32Base + SHAMD5_O_DATA0_IN + ui8Counter) = *((uint32_t *)(pui8Src + ui8Counter));
+ }
+
+ //
+ // Return true as a sign of successfully completing the function.
+ //
+ return(true);
+}
+
+//*****************************************************************************
+//
+//! Perform a blocking write of 64 bytes of data to the SHA/MD5 module.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui8Src is the pointer to the 64-byte array of data that will be
+//! written.
+//!
+//! This function does not return until the module is ready to accept data and
+//! the data has been written.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src)
+{
+ uint8_t ui8Counter;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Wait for the module to be ready to accept data.
+ //
+ while((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0)
+ {
+ }
+
+ //
+ // Write the 64 bytes of data.
+ //
+ for(ui8Counter = 0; ui8Counter < 64; ui8Counter += 4)
+ {
+ HWREG(ui32Base + SHAMD5_O_DATA0_IN + ui8Counter) =
+ *((uint32_t *) (pui8Src + ui8Counter));
+ }
+}
+
+
+//*****************************************************************************
+//
+//! Reads the result of a hashing operation.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui8Dest is the pointer to the byte array of data that will be
+//! written.
+//!
+//! This function does not return until the module is ready to accept data and
+//! the data has been written.
+//! -----------------------------------------
+//! | Algorithm | Number of Words in Result |
+//! -----------------------------------------
+//! | MD5 | 16 Bytes (128 bits) |
+//! | SHA-1 | 20 Bytes (160 bits) |
+//! | SHA-224 | 28 Bytes (224 bits) |
+//! | SHA-256 | 32 Bytes (256 bits) |
+//! -----------------------------------------
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5ResultRead(uint32_t ui32Base, uint8_t *pui8Dest)
+{
+ uint32_t ui32Idx, ui32Count;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ui32Base == SHAMD5_BASE);
+
+ //
+ // Determine the number of bytes in the result, based on the hash type.
+ //
+ switch(HWREG(ui32Base + SHAMD5_O_MODE) & SHAMD5_MODE_ALGO_M)
+ {
+ //
+ // The MD5 hash is being used.
+ //
+ case SHAMD5_MODE_ALGO_MD5:
+ {
+ //
+ // There are 16 bytes in the MD5 hash.
+ //
+ ui32Count = 16;
+
+ //
+ // Done.
+ //
+ break;
+ }
+
+ //
+ // The SHA-1 hash is being used.
+ //
+ case SHAMD5_MODE_ALGO_SHA1:
+ {
+ //
+ // There are 20 bytes in the SHA-1 hash.
+ //
+ ui32Count = 20;
+
+ //
+ // Done.
+ //
+ break;
+ }
+
+ //
+ // The SHA-224 hash is being used.
+ //
+ case SHAMD5_MODE_ALGO_SHA224:
+ {
+ //
+ // There are 28 bytes in the SHA-224 hash.
+ //
+ ui32Count = 28;
+
+ //
+ // Done.
+ //
+ break;
+ }
+
+ //
+ // The SHA-256 hash is being used.
+ //
+ case SHAMD5_MODE_ALGO_SHA256:
+ {
+ //
+ // There are 32 bytes in the SHA-256 hash.
+ //
+ ui32Count = 32;
+
+ //
+ // Done.
+ //
+ break;
+ }
+
+ //
+ // The hash type is not recognized.
+ //
+ default:
+ {
+ //
+ // Return without reading a result since the hardware appears to be
+ // misconfigured.
+ //
+ return;
+ }
+ }
+
+ //
+ // Read the hash result.
+ //
+ for(ui32Idx = 0; ui32Idx < ui32Count; ui32Idx += 4)
+ {
+ *((uint32_t *)(pui8Dest+ui32Idx)) =
+ HWREG(ui32Base + SHAMD5_O_IDIGEST_A + ui32Idx);
+ }
+}
+
+//*****************************************************************************
+//
+//! Writes multiple words of data into the SHA/MD5 data registers.
+//!
+//! \param ui32Base is the base address of the SHA/MD5 module.
+//! \param pui8DataSrc is a pointer to an array of data to be written.
+//! \param ui32DataLength is the length of the data to be written in bytes.
+//!
+//! This function writes a variable number of words into the SHA/MD5 data
+//! registers. The function waits for each block of data to be processed
+//! before another is written.
+//!
+//! \note This function is used by SHAMD5HashCompute(), SHAMD5HMACWithKPP(),
+//! and SHAMD5HMACNoKPP() to process data.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SHAMD5DataWriteMultiple(uint8_t *pui8DataSrc, uint32_t ui32DataLength)
+{
+ uint32_t ui32Idx, ui32Count, ui32Lastword, ui32TempData = 0;
+ uint8_t * ui8TempData;
+
+
+ //
+ // Calculate the number of blocks of data.
+ //
+ ui32Count = ui32DataLength / 64;
+
+ //
+ // Loop through all the blocks and write them into the data registers
+ // making sure to block additional operations until we can write the
+ // next 16 words.
+ //
+ for (ui32Idx = 0; ui32Idx < ui32Count; ui32Idx++)
+ {
+ //
+ // Write the block of data.
+ //
+ MAP_SHAMD5DataWrite(SHAMD5_BASE, pui8DataSrc);
+ //
+ // Increment the pointer to next block of data.
+ //
+ pui8DataSrc += 64;
+ }
+
+ //
+ // Calculate the remaining bytes of data that don't make up a full block.
+ //
+ ui32Count = ui32DataLength % 64;
+
+ //
+ // If there are bytes that do not make up a whole block, then
+ // write them separately.
+ //
+ if(ui32Count)
+ {
+ //
+ // Wait until the engine has finished processing the previous block.
+ //
+ while ((HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_INPUT_READY) == 0);
+
+ //
+ // Loop through the remaining words.
+ //
+ ui32Count = ui32Count / 4;
+ for (ui32Idx = 0; ui32Idx < ui32Count; ui32Idx ++)
+ {
+ //
+ // Write the word into the data register.
+ //
+ HWREG(SHAMD5_BASE + SHAMD5_O_DATA0_IN + (ui32Idx * 4)) =* ( (uint32_t *) pui8DataSrc);
+ pui8DataSrc +=4;
+ }
+ //
+ // Loop through the remaining bytes
+ //
+ ui32Count = ui32DataLength % 4;
+ ui8TempData = (uint8_t *) &ui32TempData;
+ if(ui32Count)
+ {
+ ui32Lastword = 0;
+ if(ui32Idx)
+ {
+ ui32Lastword = (ui32Idx-1) *4;
+ }
+ for(ui32Idx=0 ; ui32Idx
+//! Polarity Phase Sub-Mode
+//! 0 0 0
+//! 0 1 1
+//! 1 0 2
+//! 1 1 3
+//!
+//!
+//! Required sub mode can be select by setting \e ulSubMode parameter to one
+//! of the following
+//! - \b SPI_SUB_MODE_0
+//! - \b SPI_SUB_MODE_1
+//! - \b SPI_SUB_MODE_2
+//! - \b SPI_SUB_MODE_3
+//!
+//! The parameter \e ulConfig is logical OR of five values: the word length,
+//! active level for chip select, software or hardware controled chip select,
+//! 3 or 4 pin mode and turbo mode.
+//! mode.
+//!
+//! SPI support 8, 16 and 32 bit word lengths defined by:-
+//! - \b SPI_WL_8
+//! - \b SPI_WL_16
+//! - \b SPI_WL_32
+//!
+//! Active state of Chip[ Selece can be defined by:-
+//! - \b SPI_CS_ACTIVELOW
+//! - \b SPI_CS_ACTIVEHIGH
+//!
+//! SPI chip select can be configured to be controlled either by hardware or
+//! software:-
+//! - \b SPI_SW_CS
+//! - \b SPI_HW_CS
+//!
+//! The module can work in 3 or 4 pin mode defined by:-
+//! - \b SPI_3PIN_MODE
+//! - \b SPI_4PIN_MODE
+//!
+//! Turbo mode can be set on or turned off using:-
+//! - \b SPI_TURBO_MODE_ON
+//! - \b SPI_TURBO_MODE_OFF
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
+ unsigned long ulBitRate, unsigned long ulMode,
+ unsigned long ulSubMode, unsigned long ulConfig)
+{
+
+ unsigned long ulRegData;
+ unsigned long ulDivider;
+
+ //
+ // Read MODULCTRL register
+ //
+ ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL);
+
+ //
+ // Set Master mode with h/w chip select
+ //
+ ulRegData &= ~(MCSPI_MODULCTRL_MS |
+ MCSPI_MODULCTRL_SINGLE);
+
+ //
+ // Enable software control Chip Select, Init delay
+ // and 3-pin mode
+ //
+ ulRegData |= (((ulConfig >> 24) | ulMode) & 0xFF);
+
+ //
+ // Write the configuration
+ //
+ HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData;
+
+ //
+ // Set IS, DPE0, DPE1 based on master or slave mode
+ //
+ if(ulMode == SPI_MODE_MASTER)
+ {
+ ulRegData = 0x1 << 16;
+ }
+ else
+ {
+ ulRegData = 0x6 << 16;
+ }
+
+ //
+ // Mask the configurations and set clock divider granularity
+ // to 1 cycle
+ //
+ ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M |
+ MCSPI_CH0CONF_EPOL |
+ MCSPI_CH0CONF_POL |
+ MCSPI_CH0CONF_PHA |
+ MCSPI_CH0CONF_TURBO ) |
+ MCSPI_CH0CONF_CLKG));
+
+ //
+ // Get the divider value
+ //
+ ulDivider = ((ulSPIClk/ulBitRate) - 1);
+
+ //
+ // The least significant four bits of the divider is used fo configure
+ // CLKD in MCSPI_CHCONF next eight least significant bits are used to
+ // configure the EXTCLK in MCSPI_CHCTRL
+ //
+ ulRegData |= ((ulDivider & 0x0000000F) << 2);
+ HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4);
+
+ //
+ // Set the protocol, CS polarity, word length
+ // and turbo mode
+ //
+ ulRegData = ((ulRegData |
+ ulSubMode) | (ulConfig & 0x0008FFFF));
+
+ //
+ // Write back the CONF register
+ //
+ HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData;
+
+}
+
+//*****************************************************************************
+//
+//! Receives a word from the specified port.
+//!
+//! \param ulBase is the base address of the SPI module.
+//! \param pulData is pointer to receive data variable.
+//!
+//! This function gets a SPI word from the receive FIFO for the specified
+//! port.
+//!
+//! \return Returns the number of elements read from the receive FIFO.
+//
+//*****************************************************************************
+long
+SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read register status register
+ //
+ ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);
+
+ //
+ // Check is data is available
+ //
+ if(ulRegVal & MCSPI_CH0STAT_RXS)
+ {
+ *pulData = HWREG(ulBase + MCSPI_O_RX0);
+ return(1);
+ }
+
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Waits for the word to be received on the specified port.
+//!
+//! \param ulBase is the base address of the SPI module.
+//! \param pulData is pointer to receive data variable.
+//!
+//! This function gets a SPI word from the receive FIFO for the specified
+//! port. If there is no word available, this function waits until a
+//! word is received before returning.
+//!
+//! \return Returns the word read from the specified port, cast as an
+//! \e unsigned long.
+//
+//*****************************************************************************
+void
+SPIDataGet(unsigned long ulBase, unsigned long *pulData)
+{
+ //
+ // Wait for Rx data
+ //
+ while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS))
+ {
+ }
+
+ //
+ // Read the value
+ //
+ *pulData = HWREG(ulBase + MCSPI_O_RX0);
+}
+
+//*****************************************************************************
+//
+//! Transmits a word on the specified port.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulData is data to be transmitted.
+//!
+//! This function transmits a SPI word on the transmit FIFO for the specified
+//! port.
+//!
+//! \return Returns the number of elements written to the transmit FIFO.
+//!
+//*****************************************************************************
+long
+SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read status register
+ //
+ ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT);
+
+ //
+ // Write value into Tx register/FIFO
+ // if space is available
+ //
+ if(ulRegVal & MCSPI_CH0STAT_TXS)
+ {
+ HWREG(ulBase + MCSPI_O_TX0) = ulData;
+ return(1);
+ }
+
+ return(0);
+}
+
+//*****************************************************************************
+//
+//! Waits until the word is transmitted on the specified port.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulData is data to be transmitted.
+//!
+//! This function transmits a SPI word on the transmit FIFO for the specified
+//! port. This function waits until the space is available on transmit FIFO
+//!
+//! \return None
+//!
+//*****************************************************************************
+void
+SPIDataPut(unsigned long ulBase, unsigned long ulData)
+{
+ //
+ // Wait for space in FIFO
+ //
+ while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS))
+ {
+ }
+
+ //
+ // Write the data
+ //
+ HWREG(ulBase + MCSPI_O_TX0) = ulData;
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit and/or receive FIFOs.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulFlags selects the FIFO(s) to be enabled
+//!
+//! This function enables the transmit and/or receive FIFOs as specified by
+//! \e ulFlags.
+//! The parameter \e ulFlags shoulde be logical OR of one or more of the
+//! following:
+//! - \b SPI_TX_FIFO
+//! - \b SPI_RX_FIFO
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Set FIFO enable bits.
+ //
+ HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables the transmit and/or receive FIFOs.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulFlags selects the FIFO(s) to be enabled
+//!
+//! This function disables transmit and/or receive FIFOs. as specified by
+//! \e ulFlags.
+//! The parameter \e ulFlags shoulde be logical OR of one or more of the
+//! following:
+//! - \b SPI_TX_FIFO
+//! - \b SPI_RX_FIFO
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags)
+{
+ //
+ // Reset FIFO Enable bits.
+ //
+ HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags);
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which DMA requests or interrupts are generated.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulTxLevel is the Almost Empty Level for transmit FIFO.
+//! \param ulRxLevel is the Almost Full Level for the receive FIFO.
+//!
+//! This function Sets the FIFO level at which DMA requests or interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read the current configuration
+ //
+ ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
+
+ //
+ // Mask and set new FIFO thresholds.
+ //
+ ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel-1) << 8) | (ulTxLevel-1)));
+
+ //
+ // Set the transmit and receive FIFO thresholds.
+ //
+ HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal;
+
+}
+
+//*****************************************************************************
+//
+//! Gets the FIFO level at which DMA requests or interrupts are generated.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param pulTxLevel is a pointer to storage for the transmit FIFO level
+//! \param pulRxLevel is a pointer to storage for the receive FIFO level
+//!
+//! This function gets the FIFO level at which DMA requests or interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read the current configuration
+ //
+ ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
+
+ *pulTxLevel = (ulRegVal & 0xFF);
+
+ *pulRxLevel = ((ulRegVal >> 8) & 0xFF);
+
+}
+
+//*****************************************************************************
+//
+//! Sets the word count.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulWordCount is number of SPI words to be transmitted.
+//!
+//! This function sets the word count, which is the number of SPI word to
+//! be transferred on channel when using the FIFO buffer.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read the current configuration
+ //
+ ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL);
+
+ //
+ // Mask and set the word count
+ //
+ HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)|
+ (ulWordCount & 0xFFFF) << 16);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a SPI interrupt.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SPI interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller; specific
+//! SPI interrupts must be enabled via SPIIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Determine the interrupt number based on the SPI module
+ //
+ ulInt = SPIIntNumberGet(ulBase);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the SPI interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a SPI interrupt.
+//!
+//! \param ulBase is the base address of the SPI module
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a SPI interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Determine the interrupt number based on the SPI module
+ //
+ ulInt = SPIIntNumberGet(ulBase);
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual SPI interrupt sources.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated SPI interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b SPI_INT_DMATX
+//! - \b SPI_INT_DMARX
+//! - \b SPI_INT_EOW
+//! - \b SPI_INT_RX_OVRFLOW
+//! - \b SPI_INT_RX_FULL
+//! - \b SPI_INT_TX_UDRFLOW
+//! - \b SPI_INT_TX_EMPTY
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ unsigned long ulDmaMsk;
+
+ //
+ // Enable DMA Tx Interrupt
+ //
+ if(ulIntFlags & SPI_INT_DMATX)
+ {
+ ulDmaMsk = SPIDmaMaskGet(ulBase);
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
+ }
+
+ //
+ // Enable DMA Rx Interrupt
+ //
+ if(ulIntFlags & SPI_INT_DMARX)
+ {
+ ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
+ }
+
+ //
+ // Enable the specific Interrupts
+ //
+ HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F);
+}
+
+
+//*****************************************************************************
+//
+//! Disables individual SPI interrupt sources.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated SPI interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to SPIIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ unsigned long ulDmaMsk;
+
+ //
+ // Disable DMA Tx Interrupt
+ //
+ if(ulIntFlags & SPI_INT_DMATX)
+ {
+ ulDmaMsk = SPIDmaMaskGet(ulBase);
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
+ }
+
+ //
+ // Disable DMA Tx Interrupt
+ //
+ if(ulIntFlags & SPI_INT_DMARX)
+ {
+ ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
+ }
+
+ //
+ // Disable the specific Interrupts
+ //
+ HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the specified SPI.
+//! The status of interrupts that are allowed to reflect to the processor can
+//! be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in SPIIntEnable().
+//
+//*****************************************************************************
+unsigned long
+SPIIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ unsigned long ulIntStat;
+ unsigned long ulIntFlag;
+ unsigned long ulDmaMsk;
+
+ //
+ // Get SPI interrupt status
+ //
+ ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F;
+
+ if(bMasked)
+ {
+ ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE);
+ }
+
+ //
+ // Get the interrupt bit
+ //
+ ulDmaMsk = SPIDmaMaskGet(ulBase);
+
+ //
+ // Get the DMA interrupt status
+ //
+ if(bMasked)
+ {
+ ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED);
+ }
+ else
+ {
+ ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
+ }
+
+ //
+ // Get SPI Tx DMA done status
+ //
+ if(ulIntStat & ulDmaMsk)
+ {
+ ulIntFlag |= SPI_INT_DMATX;
+ }
+
+ //
+ // Get SPI Rx DMA done status
+ //
+ if(ulIntStat & (ulDmaMsk >> 1))
+ {
+ ulIntFlag |= SPI_INT_DMARX;
+ }
+
+ //
+ // Return status
+ //
+ return(ulIntFlag);
+}
+
+//*****************************************************************************
+//
+//! Clears SPI interrupt sources.
+//!
+//! \param ulBase is the base address of the SPI module
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified SPI interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to SPIIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ unsigned long ulDmaMsk;
+
+ //
+ // Disable DMA Tx Interrupt
+ //
+ if(ulIntFlags & SPI_INT_DMATX)
+ {
+ ulDmaMsk = SPIDmaMaskGet(ulBase);
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
+ }
+
+ //
+ // Disable DMA Tx Interrupt
+ //
+ if(ulIntFlags & SPI_INT_DMARX)
+ {
+ ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
+ HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
+ }
+
+ //
+ // Clear Interrupts
+ //
+ HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F);
+}
+
+//*****************************************************************************
+//
+//! Enables the chip select in software controlled mode
+//!
+//! \param ulBase is the base address of the SPI module.
+//!
+//! This function enables the Chip select in software controlled mode. The
+//! active state of CS will depend on the configuration done via
+//! \sa SPIConfigExpClkSet().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void SPICSEnable(unsigned long ulBase)
+{
+ //
+ // Set Chip Select enable bit.
+ //
+ HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
+}
+
+//*****************************************************************************
+//
+//! Disables the chip select in software controlled mode
+//!
+//! \param ulBase is the base address of the SPI module.
+//!
+//! This function disables the Chip select in software controlled mode. The
+//! active state of CS will depend on the configuration done via
+//! sa SPIConfigSetExpClk().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void SPICSDisable(unsigned long ulBase)
+{
+ //
+ // Reset Chip Select enable bit.
+ //
+ HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
+}
+
+//*****************************************************************************
+//
+//! Send/Receive data buffer over SPI channel
+//!
+//! \param ulBase is the base address of SPI module
+//! \param ucDout is the pointer to Tx data buffer or 0.
+//! \param ucDin is pointer to Rx data buffer or 0
+//! \param ulCount is the size of data in bytes.
+//! \param ulFlags controlls chip select toggling.
+//!
+//! This function transfers \e ulCount bytes of data over SPI channel. Since
+//! the API sends a SPI word at a time \e ulCount should be a multiple of
+//! word length set using SPIConfigSetExpClk().
+//!
+//! If the \e ucDout parameter is set to 0, the function will send 0xFF over
+//! the SPI MOSI line.
+//!
+//! If the \e ucDin parameter is set to 0, the function will ignore data on SPI
+//! MISO line.
+//!
+//! The parameter \e ulFlags is logical OR of one or more of the following
+//!
+//! - \b SPI_CS_ENABLE if CS needs to be enabled at start of transfer.
+//! - \b SPI_CS_DISABLE if CS need to be disabled at the end of transfer.
+//!
+//! This function will not return until data has been transmitted
+//!
+//! \return Returns 0 on success, -1 otherwise.
+//
+//*****************************************************************************
+long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
+ unsigned char *ucDin, unsigned long ulCount,
+ unsigned long ulFlags)
+{
+ unsigned long ulWordLength;
+ long lRet;
+
+ //
+ // Get the word length
+ //
+ ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M);
+
+ //
+ // Check for word length.
+ //
+ if( !((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) ||
+ (ulWordLength == SPI_WL_32)) )
+ {
+ return -1;
+ }
+
+ if( ulWordLength == SPI_WL_8 )
+ {
+ //
+ // Do byte transfer
+ //
+ lRet = SPITransfer8(ulBase,ucDout,ucDin,ulCount,ulFlags);
+ }
+ else if( ulWordLength == SPI_WL_16 )
+ {
+
+ //
+ // Do half-word transfer
+ //
+ lRet = SPITransfer16(ulBase,(unsigned short *)ucDout,
+ (unsigned short *)ucDin,ulCount,ulFlags);
+ }
+ else
+ {
+ //
+ // Do word transfer
+ //
+ lRet = SPITransfer32(ulBase,(unsigned long *)ucDout,
+ (unsigned long *)ucDin,ulCount,ulFlags);
+ }
+
+ //
+ // return
+ //
+ return lRet;
+
+}
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/spi.h b/cc3200/hal/spi.h
new file mode 100644
index 0000000000..593986bc6d
--- /dev/null
+++ b/cc3200/hal/spi.h
@@ -0,0 +1,163 @@
+//*****************************************************************************
+//
+// spi.h
+//
+// Defines and Macros for the SPI.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __SPI_H__
+#define __SPI_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter
+//*****************************************************************************
+#define SPI_MODE_MASTER 0x00000000
+#define SPI_MODE_SLAVE 0x00000004
+
+//*****************************************************************************
+// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter
+//*****************************************************************************
+#define SPI_SUB_MODE_0 0x00000000
+#define SPI_SUB_MODE_1 0x00000001
+#define SPI_SUB_MODE_2 0x00000002
+#define SPI_SUB_MODE_3 0x00000003
+
+
+//*****************************************************************************
+// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter
+//*****************************************************************************
+#define SPI_SW_CTRL_CS 0x01000000
+#define SPI_HW_CTRL_CS 0x00000000
+#define SPI_3PIN_MODE 0x02000000
+#define SPI_4PIN_MODE 0x00000000
+#define SPI_TURBO_ON 0x00080000
+#define SPI_TURBO_OFF 0x00000000
+#define SPI_CS_ACTIVEHIGH 0x00000000
+#define SPI_CS_ACTIVELOW 0x00000040
+#define SPI_WL_8 0x00000380
+#define SPI_WL_16 0x00000780
+#define SPI_WL_32 0x00000F80
+
+//*****************************************************************************
+// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable()
+//*****************************************************************************
+#define SPI_TX_FIFO 0x08000000
+#define SPI_RX_FIFO 0x10000000
+
+//*****************************************************************************
+// Values that can be passed to SPIDMAEnable() and SPIDMADisable()
+//*****************************************************************************
+#define SPI_RX_DMA 0x00008000
+#define SPI_TX_DMA 0x00004000
+
+//*****************************************************************************
+// Values that can be passed to SPIIntEnable(), SPIIntDiasble(),
+// SPIIntClear() or returned from SPIStatus()
+//*****************************************************************************
+#define SPI_INT_DMATX 0x20000000
+#define SPI_INT_DMARX 0x10000000
+#define SPI_INT_EOW 0x00020000
+#define SPI_INT_WKS 0x00010000
+#define SPI_INT_RX_OVRFLOW 0x00000008
+#define SPI_INT_RX_FULL 0x00000004
+#define SPI_INT_TX_UDRFLOW 0x00000002
+#define SPI_INT_TX_EMPTY 0x00000001
+
+//*****************************************************************************
+// Values that can be passed to SPITransfer()
+//*****************************************************************************
+#define SPI_CS_ENABLE 0x00000001
+#define SPI_CS_DISABLE 0x00000002
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void SPIEnable(unsigned long ulBase);
+extern void SPIDisable(unsigned long ulBase);
+extern void SPIReset(unsigned long ulBase);
+extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
+ unsigned long ulBitRate, unsigned long ulMode,
+ unsigned long ulSubMode, unsigned long ulConfig);
+extern long SPIDataGetNonBlocking(unsigned long ulBase,
+ unsigned long * pulData);
+extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData);
+extern long SPIDataPutNonBlocking(unsigned long ulBase,
+ unsigned long ulData);
+extern void SPIDataPut(unsigned long ulBase, unsigned long ulData);
+extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags);
+extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags);
+extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel);
+extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel);
+extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount);
+extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void SPIIntUnregister(unsigned long ulBase);
+extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags);
+extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags);
+extern void SPICSEnable(unsigned long ulBase);
+extern void SPICSDisable(unsigned long ulBase);
+extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
+ unsigned char *ucDin, unsigned long ulSize,
+ unsigned long ulFlags);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SPI_H__
diff --git a/cc3200/hal/startup_gcc.c b/cc3200/hal/startup_gcc.c
new file mode 100644
index 0000000000..30831eb889
--- /dev/null
+++ b/cc3200/hal/startup_gcc.c
@@ -0,0 +1,418 @@
+//*****************************************************************************
+// startup_gcc.c
+//
+// Startup code for use with GCC.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#include
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "fault_registers.h"
+
+//*****************************************************************************
+//
+// The following are constructs created by the linker, indicating where the
+// the "data" and "bss" segments reside in memory. The initializers for the
+// for the "data" segment resides immediately following the "text" segment.
+//
+//*****************************************************************************
+extern uint32_t _data;
+extern uint32_t _edata;
+extern uint32_t _bss;
+extern uint32_t _ebss;
+extern uint32_t _estack;
+extern uint32_t __init_data;
+
+//*****************************************************************************
+//
+// Forward declaration of the default fault handlers.
+//
+//*****************************************************************************
+void ResetISR(void);
+static void NmiSR(void) __attribute__( ( naked ) );
+static void FaultISR( void ) __attribute__( ( naked ) );
+static void IntDefaultHandler(void) __attribute__( ( naked ) );
+static void BusFaultHandler(void) __attribute__( ( naked ) );
+void HardFault_HandlerC(unsigned long *hardfault_args);
+
+//*****************************************************************************
+//
+// External declaration for the freeRTOS handlers
+//
+//*****************************************************************************
+#ifdef USE_FREERTOS
+extern void vPortSVCHandler(void);
+extern void xPortPendSVHandler(void);
+extern void xPortSysTickHandler(void);
+#endif
+
+//*****************************************************************************
+//
+// The entry point for the application.
+//
+//*****************************************************************************
+extern int main(void);
+
+//*****************************************************************************
+//
+// The vector table. Note that the proper constructs must be placed on this to
+// ensure that it ends up at physical address 0x0000.0000.
+//
+//*****************************************************************************
+__attribute__ ((section(".intvecs")))
+void (* const g_pfnVectors[256])(void) =
+{
+ (void (*)(void))((uint32_t)&_estack), // The initial stack pointer
+ ResetISR, // The reset handler
+ NmiSR, // The NMI handler
+ FaultISR, // The hard fault handler
+ IntDefaultHandler, // The MPU fault handler
+ BusFaultHandler, // The bus fault handler
+ IntDefaultHandler, // The usage fault handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+#ifdef USE_FREERTOS
+ vPortSVCHandler, // SVCall handler
+#else
+ IntDefaultHandler, // SVCall handler
+#endif
+ IntDefaultHandler, // Debug monitor handler
+ 0, // Reserved
+#ifdef USE_FREERTOS
+ xPortPendSVHandler, // The PendSV handler
+ xPortSysTickHandler, // The SysTick handler
+#else
+ IntDefaultHandler, // The PendSV handler
+ IntDefaultHandler, // The SysTick handler
+#endif
+ IntDefaultHandler, // GPIO Port A
+ IntDefaultHandler, // GPIO Port B
+ IntDefaultHandler, // GPIO Port C
+ IntDefaultHandler, // GPIO Port D
+ 0, // Reserved
+ IntDefaultHandler, // UART0 Rx and Tx
+ IntDefaultHandler, // UART1 Rx and Tx
+ 0, // Reserved
+ IntDefaultHandler, // I2C0 Master and Slave
+ 0,0,0,0,0, // Reserved
+ IntDefaultHandler, // ADC Channel 0
+ IntDefaultHandler, // ADC Channel 1
+ IntDefaultHandler, // ADC Channel 2
+ IntDefaultHandler, // ADC Channel 3
+ IntDefaultHandler, // Watchdog Timer
+ IntDefaultHandler, // Timer 0 subtimer A
+ IntDefaultHandler, // Timer 0 subtimer B
+ IntDefaultHandler, // Timer 1 subtimer A
+ IntDefaultHandler, // Timer 1 subtimer B
+ IntDefaultHandler, // Timer 2 subtimer A
+ IntDefaultHandler, // Timer 2 subtimer B
+ 0,0,0,0, // Reserved
+ IntDefaultHandler, // Flash
+ 0,0,0,0,0, // Reserved
+ IntDefaultHandler, // Timer 3 subtimer A
+ IntDefaultHandler, // Timer 3 subtimer B
+ 0,0,0,0,0,0,0,0,0, // Reserved
+ IntDefaultHandler, // uDMA Software Transfer
+ IntDefaultHandler, // uDMA Error
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ IntDefaultHandler, // SHA
+ 0,0, // Reserved
+ IntDefaultHandler, // AES
+ 0, // Reserved
+ IntDefaultHandler, // DES
+ 0,0,0,0,0, // Reserved
+ IntDefaultHandler, // SDHost
+ 0, // Reserved
+ IntDefaultHandler, // I2S
+ 0, // Reserved
+ IntDefaultHandler, // Camera
+ 0,0,0,0,0,0,0, // Reserved
+ IntDefaultHandler, // NWP to APPS Interrupt
+ IntDefaultHandler, // Power, Reset and Clock module
+ 0,0, // Reserved
+ IntDefaultHandler, // Shared SPI
+ IntDefaultHandler, // Generic SPI
+ IntDefaultHandler, // Link SPI
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0,0,0,0,0,0,0,0,0, // Reserved
+ 0,0 // Reserved
+};
+
+
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor first starts execution
+// following a reset event. Only the absolutely necessary set is performed,
+// after which the application supplied entry() routine is called. Any fancy
+// actions (such as making decisions based on the reset cause register, and
+// resetting the bits in that register) are left solely in the hands of the
+// application.
+//
+//*****************************************************************************
+
+void ResetISR(void)
+{
+#if defined(DEBUG) && !defined(BOOTLOADER)
+ //
+ // Fill the main stack with a known value so that
+ // we can measure the main stack high water mark
+ //
+ __asm volatile
+ (
+ "ldr r0, =_stack \n"
+ "ldr r1, =_estack \n"
+ "mov r2, #0x55555555 \n"
+ ".thumb_func \n"
+ "fill_loop: \n"
+ "cmp r0, r1 \n"
+ "it lt \n"
+ "strlt r2, [r0], #4 \n"
+ "blt fill_loop \n"
+ );
+#endif
+
+ // Get the initial stack pointer location from the vector table
+ // and write this value to the msp register
+ __asm volatile
+ (
+ "ldr r0, =_text \n"
+ "ldr r0, [r0] \n"
+ "msr msp, r0 \n"
+ );
+
+ {
+ uint32_t *pui32Src, *pui32Dest;
+
+ //
+ // Copy the data segment initializers
+ //
+ pui32Src = &__init_data;
+ for(pui32Dest = &_data; pui32Dest < &_edata; )
+ {
+ *pui32Dest++ = *pui32Src++;
+ }
+
+ //
+ // Zero fill the bss segment.
+ //
+ __asm volatile
+ (
+ "ldr r0, =_bss \n"
+ "ldr r1, =_ebss \n"
+ "mov r2, #0 \n"
+ ".thumb_func \n"
+ "zero_loop: \n"
+ "cmp r0, r1 \n"
+ "it lt \n"
+ "strlt r2, [r0], #4 \n"
+ "blt zero_loop \n"
+ );
+ }
+
+ //
+ // Call the application's entry point.
+ //
+ main();
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a NMI. This
+// simply enters an infinite loop, preserving the system state for examination
+// by a debugger.
+//
+//*****************************************************************************
+
+static void NmiSR(void)
+{
+#ifdef DEBUG
+ // Break into the debugger
+ __asm volatile ("bkpt #0 \n");
+#endif
+
+ //
+ // Enter an infinite loop.
+ //
+ for ( ; ; )
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives a hard fault
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+
+static void FaultISR(void)
+{
+ /*
+ * Get the appropriate stack pointer, depending on our mode,
+ * and use it as the parameter to the C handler. This function
+ * will never return
+ */
+
+ __asm volatile
+ (
+ "movs r0, #4 \n"
+ "mov r1, lr \n"
+ "tst r0, r1 \n"
+ "beq _msp \n"
+ "mrs r0, psp \n"
+ "b HardFault_HandlerC \n"
+ "_msp: \n"
+ "mrs r0, msp \n"
+ "b HardFault_HandlerC \n"
+ ) ;
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+
+static void BusFaultHandler(void)
+{
+#ifdef DEBUG
+ // Break into the debugger
+ __asm volatile ("bkpt #0 \n");
+#endif
+
+ //
+ // Enter an infinite loop.
+ //
+ for ( ; ; )
+ {
+ }
+}
+
+//*****************************************************************************
+//
+// This is the code that gets called when the processor receives an unexpected
+// interrupt. This simply enters an infinite loop, preserving the system state
+// for examination by a debugger.
+//
+//*****************************************************************************
+static void IntDefaultHandler(void)
+{
+#ifdef DEBUG
+ // Break into the debugger
+ __asm volatile ("bkpt #0 \n");
+#endif
+
+ //
+ // Enter an infinite loop.
+ //
+ for ( ; ; )
+ {
+ }
+}
+
+
+//***********************************************************************************
+// HardFaultHandler_C:
+// This is called from the HardFault_HandlerAsm with a pointer the Fault stack
+// as the parameter. We can then read the values from the stack and place them
+// into local variables for ease of reading.
+// We then read the various Fault Status and Address Registers to help decode
+// cause of the fault.
+// The function ends with a BKPT instruction to force control back into the debugger
+//***********************************************************************************
+void HardFault_HandlerC(uint32_t *pulFaultStackAddress)
+{
+ volatile uint32_t r0 ;
+ volatile uint32_t r1 ;
+ volatile uint32_t r2 ;
+ volatile uint32_t r3 ;
+ volatile uint32_t r12 ;
+ volatile uint32_t lr ;
+ volatile uint32_t pc ;
+ volatile uint32_t psr ;
+ volatile _CFSR_t _CFSR ;
+ volatile _HFSR_t _HFSR ;
+ volatile uint32_t _BFAR ;
+
+
+ r0 = pulFaultStackAddress[0];
+ r1 = pulFaultStackAddress[1];
+ r2 = pulFaultStackAddress[2];
+ r3 = pulFaultStackAddress[3];
+ r12 = pulFaultStackAddress[4];
+ lr = pulFaultStackAddress[5];
+ pc = pulFaultStackAddress[6];
+ psr = pulFaultStackAddress[7];
+
+ // Configurable Fault Status Register
+ // Consists of MMSR, BFSR and UFSR
+ _CFSR = (*((volatile _CFSR_t *)(0xE000ED28)));
+ // Hard Fault Status Register
+ _HFSR = (*((volatile _HFSR_t *)(0xE000ED2C)));
+ // Bus Fault Address Register
+ _BFAR = (*((volatile uint32_t *)(0xE000ED38)));
+
+#ifdef DEBUG
+ // Break into the debugger
+ __asm volatile ("bkpt #0 \n");
+#endif
+
+ for ( ; ; )
+ {
+ // Keep the compiler happy
+ (void)r0, (void)r1, (void)r2, (void)r3, (void)r12, (void)lr, (void)pc, (void)psr;
+ (void)_CFSR, (void)_HFSR, (void)_BFAR;
+ }
+}
+
diff --git a/cc3200/hal/systick.c b/cc3200/hal/systick.c
new file mode 100644
index 0000000000..550e3ed1d2
--- /dev/null
+++ b/cc3200/hal/systick.c
@@ -0,0 +1,275 @@
+//*****************************************************************************
+//
+// systick.c
+//
+// Driver for the SysTick timer in NVIC.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup systick_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "systick.h"
+
+//*****************************************************************************
+//
+//! Enables the SysTick counter.
+//!
+//! This function starts the SysTick counter. If an interrupt handler has been
+//! registered, it is called when the SysTick counter rolls over.
+//!
+//! \note Calling this function causes the SysTick counter to (re)commence
+//! counting from its current value. The counter is not automatically reloaded
+//! with the period as specified in a previous call to SysTickPeriodSet(). If
+//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
+//! written to force the reload. Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the supplied period on the next
+//! clock.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickEnable(void)
+{
+ //
+ // Enable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick counter.
+//!
+//! This function stops the SysTick counter. If an interrupt handler has been
+//! registered, it is not called until SysTick is restarted.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickDisable(void)
+{
+ //
+ // Disable SysTick.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the SysTick interrupt.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! SysTick interrupt occurs.
+//!
+//! This function registers the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler, returning an error if an error occurs.
+ //
+ IntRegister(FAULT_SYSTICK, pfnHandler);
+
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Unregisters the interrupt handler for the SysTick interrupt.
+//!
+//! This function unregisters the handler to be called when a SysTick interrupt
+//! occurs.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntUnregister(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(FAULT_SYSTICK);
+}
+
+//*****************************************************************************
+//
+//! Enables the SysTick interrupt.
+//!
+//! This function enables the SysTick interrupt, allowing it to be
+//! reflected to the processor.
+//!
+//! \note The SysTick interrupt handler is not required to clear the SysTick
+//! interrupt source because it is cleared automatically by the NVIC when the
+//! interrupt handler is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntEnable(void)
+{
+ //
+ // Enable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the SysTick interrupt.
+//!
+//! This function disables the SysTick interrupt, preventing it from being
+//! reflected to the processor.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickIntDisable(void)
+{
+ //
+ // Disable the SysTick interrupt.
+ //
+ HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the period of the SysTick counter.
+//!
+//! \param ulPeriod is the number of clock ticks in each period of the SysTick
+//! counter and must be between 1 and 16,777,216, inclusive.
+//!
+//! This function sets the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \note Calling this function does not cause the SysTick counter to reload
+//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
+//! register must be written. Any write to this register clears the SysTick
+//! counter to 0 and causes a reload with the \e ulPeriod supplied here on
+//! the next clock after SysTick is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+SysTickPeriodSet(unsigned long ulPeriod)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
+
+ //
+ // Set the period of the SysTick counter.
+ //
+ HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
+}
+
+//*****************************************************************************
+//
+//! Gets the period of the SysTick counter.
+//!
+//! This function returns the rate at which the SysTick counter wraps, which
+//! equates to the number of processor clocks between interrupts.
+//!
+//! \return Returns the period of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickPeriodGet(void)
+{
+ //
+ // Return the period of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_RELOAD) + 1);
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the SysTick counter.
+//!
+//! This function returns the current value of the SysTick counter, which is
+//! a value between the period - 1 and zero, inclusive.
+//!
+//! \return Returns the current value of the SysTick counter.
+//
+//*****************************************************************************
+unsigned long
+SysTickValueGet(void)
+{
+ //
+ // Return the current value of the SysTick counter.
+ //
+ return(HWREG(NVIC_ST_CURRENT));
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/systick.h b/cc3200/hal/systick.h
new file mode 100644
index 0000000000..3d1a33aaa9
--- /dev/null
+++ b/cc3200/hal/systick.h
@@ -0,0 +1,78 @@
+//*****************************************************************************
+//
+// systick.h
+//
+// Prototypes for the SysTick driver.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __SYSTICK_H__
+#define __SYSTICK_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void SysTickEnable(void);
+extern void SysTickDisable(void);
+extern void SysTickIntRegister(void (*pfnHandler)(void));
+extern void SysTickIntUnregister(void);
+extern void SysTickIntEnable(void);
+extern void SysTickIntDisable(void);
+extern void SysTickPeriodSet(unsigned long ulPeriod);
+extern unsigned long SysTickPeriodGet(void);
+extern unsigned long SysTickValueGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __SYSTICK_H__
diff --git a/cc3200/hal/timer.c b/cc3200/hal/timer.c
new file mode 100644
index 0000000000..7167dcc90b
--- /dev/null
+++ b/cc3200/hal/timer.c
@@ -0,0 +1,1067 @@
+//*****************************************************************************
+//
+// timer.c
+//
+// Driver for the timer module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup GPT_General_Purpose_Timer_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_timer.h"
+#include "inc/hw_types.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "timer.h"
+
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a timer base address.
+//!
+//! \param ulBase is the base address of the timer module.
+//!
+//! This function determines if a timer module base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+TimerBaseValid(unsigned long ulBase)
+{
+ return((ulBase == TIMERA0_BASE) || (ulBase == TIMERA1_BASE) ||
+ (ulBase == TIMERA2_BASE) || (ulBase == TIMERA3_BASE));
+}
+#else
+#define TimerBaseValid(ulBase) (ulBase)
+#endif
+
+//*****************************************************************************
+//
+//! Enables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function enables operation of the timer module. The timer must be
+//! configured before it is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerEnable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Enable the timer(s) module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+}
+
+//*****************************************************************************
+//
+//! Disables the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to disable; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function disables operation of the timer module.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDisable(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Disable the timer module.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer &
+ (TIMER_CTL_TAEN | TIMER_CTL_TBEN));
+}
+
+//*****************************************************************************
+//
+//! Configures the timer(s).
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulConfig is the configuration for the timer.
+//!
+//! This function configures the operating mode of the timer(s). The timer
+//! module is disabled before being configured, and is left in the disabled
+//! state. The 16/32-bit timer is comprised of two 16-bit timers that can
+//! operate independently or be concatenated to form a 32-bit timer.
+//!
+//! The configuration is specified in \e ulConfig as one of the following
+//! values:
+//!
+//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer
+//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer
+//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers
+//!
+//! When configured for a pair of half-width timers, each timer is separately
+//! configured. The first timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the following values
+//! and \e ulConfig:
+//!
+//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer
+//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer
+//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up
+//! instead of down (not available on all parts)
+//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture
+//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture
+//! - \b TIMER_CFG_A_PWM - Half-width PWM output
+//!
+//! Similarly, the second timer is configured by setting \e ulConfig to
+//! the result of a logical OR operation between one of the corresponding
+//! \b TIMER_CFG_B_* values and \e ulConfig.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerConfigure(unsigned long ulBase, unsigned long ulConfig)
+{
+
+ ASSERT((ulConfig == TIMER_CFG_ONE_SHOT) ||
+ (ulConfig == TIMER_CFG_ONE_SHOT_UP) ||
+ (ulConfig == TIMER_CFG_PERIODIC) ||
+ (ulConfig == TIMER_CFG_PERIODIC_UP) ||
+ ((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR));
+ ASSERT(((ulConfig & 0xff000000) != TIMER_CFG_SPLIT_PAIR) ||
+ ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) ||
+ ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) &&
+ (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) ||
+ ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))));
+
+ //
+ // Enable CCP to IO path
+ //
+ HWREG(0x440260B0) = 0xFF;
+
+ //
+ // Disable the timers.
+ //
+ HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN);
+
+ //
+ // Set the global timer configuration.
+ //
+ HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24;
+
+ //
+ // Set the configuration of the A and B timers. Note that the B timer
+ // configuration is ignored by the hardware in 32-bit modes.
+ //
+ HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255;
+ HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255;
+}
+
+//*****************************************************************************
+//
+//! Controls the output level.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param bInvert specifies the output level.
+//!
+//! This function sets the PWM output level for the specified timer. If the
+//! \e bInvert parameter is \b true, then the timer's output is made active
+//! low; otherwise, it is made active high.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the output levels as requested.
+ //
+ ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML;
+ HWREG(ulBase + TIMER_O_CTL) = (bInvert ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Controls the event type.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulEvent specifies the type of event; must be one of
+//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or
+//! \b TIMER_EVENT_BOTH_EDGES.
+//!
+//! This function sets the signal edge(s) that triggers the timer when in
+//! capture mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the event type.
+ //
+ ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M);
+ HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) &
+ ~(TIMER_CTL_TAEVENT_M |
+ TIMER_CTL_TBEVENT_M)) | ulEvent);
+}
+
+//*****************************************************************************
+//
+//! Controls the stall handling.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to be adjusted; must be one of
+//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH.
+//! \param bStall specifies the response to a stall signal.
+//!
+//! This function controls the stall response for the specified timer. If the
+//! \e bStall parameter is \b true, then the timer stops counting if the
+//! processor enters debug mode; otherwise the timer keeps running while in
+//! debug mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the stall mode.
+ //
+ ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL;
+ HWREG(ulBase + TIMER_O_CTL) = (bStall ?
+ (HWREG(ulBase + TIMER_O_CTL) | ulTimer) :
+ (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer)));
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale value which must be between 0 and 255
+//! (inclusive) for 16/32-bit timers.
+//!
+//! This function sets the value of the input clock prescaler. The prescaler
+//! is only operational when in half-width mode and is used to extend the range
+//! of the half-width timer modes.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+ ASSERT(ulValue < 256);
+
+ //
+ // Set the timer A prescaler if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAPR) = ulValue;
+ }
+
+ //
+ // Set the timer B prescaler if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBPR) = ulValue;
+ }
+}
+
+
+//*****************************************************************************
+//
+//! Get the timer prescale value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler. The prescaler
+//! is only operational when in half-width mode and is used to extend the range
+//! of the half-width timer modes.
+//!
+//! \return The value of the timer prescaler.
+//
+//*****************************************************************************
+
+unsigned long
+TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) :
+ HWREG(ulBase + TIMER_O_TBPR));
+}
+
+//*****************************************************************************
+//
+//! Set the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param ulValue is the timer prescale match value which must be between 0
+//! and 255 (inclusive) for 16/32-bit timers.
+//!
+//! This function sets the value of the input clock prescaler match value.
+//! When in a half-width mode that uses the counter match and the prescaler,
+//! the prescale match effectively extends the range of the match.
+//!
+//! \note The availability of the prescaler match varies with the
+//! part and timer mode in use. Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+ ASSERT(ulValue < 256);
+
+ //
+ // Set the timer A prescale match if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAPMR) = ulValue;
+ }
+
+ //
+ // Set the timer B prescale match if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBPMR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Get the timer prescale match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B.
+//!
+//! This function gets the value of the input clock prescaler match value.
+//! When in a half-width mode that uses the counter match and prescaler, the
+//! prescale match effectively extends the range of the match.
+//!
+//! \note The availability of the prescaler match varies with the
+//! part and timer mode in use. Please consult the datasheet for the part you
+//! are using to determine whether this support is available.
+//!
+//! \return The value of the timer prescale match.
+//
+//*****************************************************************************
+unsigned long
+TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Return the appropriate prescale match value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) :
+ HWREG(ulBase + TIMER_O_TBPMR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for full-width operation.
+//! \param ulValue is the load value.
+//!
+//! This function sets the timer load value; if the timer is running then the
+//! value is immediately loaded into the timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A load value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAILR) = ulValue;
+ }
+
+ //
+ // Set the timer B load value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBILR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer load value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for full-width operation.
+//!
+//! This function gets the currently programmed interval load value for the
+//! specified timer.
+//!
+//! \note This function can be used for both full- and half-width modes of
+//! 16/32-bit timers.
+//!
+//! \return Returns the load value for the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerLoadGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate load value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) :
+ HWREG(ulBase + TIMER_O_TBILR));
+}
+
+//*****************************************************************************
+//
+//! Gets the current timer value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function reads the current value of the specified timer.
+//!
+//! \return Returns the current value of the timer.
+//
+//*****************************************************************************
+unsigned long
+TimerValueGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate timer value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) :
+ HWREG(ulBase + TIMER_O_TBR));
+}
+
+//*****************************************************************************
+//
+//! Sets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the
+//! timer is configured for 32-bit operation.
+//! \param ulValue is the match value.
+//!
+//! This function sets the match value for a timer. This is used in capture
+//! count mode to determine when to interrupt the processor and in PWM mode to
+//! determine the duty cycle of the output signal.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Set the timer A match value if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue;
+ }
+
+ //
+ // Set the timer B match value if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue;
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the timer match value.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer; must be one of \b TIMER_A or
+//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured
+//! for 32-bit operation.
+//!
+//! This function gets the match value for the specified timer.
+//!
+//! \return Returns the match value for the timer.
+//
+//********************************************************************************
+unsigned long
+TimerMatchGet(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B));
+
+ //
+ // Return the appropriate match value.
+ //
+ return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) :
+ HWREG(ulBase + TIMER_O_TBMATCHR));
+}
+
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//! \param pfnHandler is a pointer to the function to be called when the timer
+//! interrupt occurs.
+//!
+//! This function sets the handler to be called when a timer interrupt occurs.
+//! In addition, this function enables the global interrupt in the interrupt
+//! controller; specific timer interrupts must be enabled via TimerIntEnable().
+//! It is the interrupt handler's responsibility to clear the interrupt source
+//! via TimerIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A :
+ ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A :
+ ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A)));
+
+ //
+ // Register an interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase);
+ }
+
+ //
+ // Register an interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulBase + 1, pfnHandler);
+
+ //
+ // Enable the interrupt.
+ //
+ IntEnable(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the timer interrupt.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A,
+//! \b TIMER_B, or \b TIMER_BOTH.
+//!
+//! This function clears the handler to be called when a timer interrupt
+//! occurs. This function also masks off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+ ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) ||
+ (ulTimer == TIMER_BOTH));
+
+ //
+ // Get the interrupt number for this timer module.
+ //
+
+ ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A :
+ ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A :
+ ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A)));
+
+
+
+ //
+ // Unregister the interrupt handler for timer A if requested.
+ //
+ if(ulTimer & TIMER_A)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase);
+ }
+
+ //
+ // Unregister the interrupt handler for timer B if requested.
+ //
+ if(ulTimer & TIMER_B)
+ {
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulBase + 1);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulBase + 1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Enables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! Enables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter must be the logical OR of any combination of
+//! the following:
+//!
+//! - \b TIMER_CAPB_EVENT - Capture B event interrupt
+//! - \b TIMER_CAPB_MATCH - Capture B match interrupt
+//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt
+//! - \b TIMER_CAPA_EVENT - Capture A event interrupt
+//! - \b TIMER_CAPA_MATCH - Capture A match interrupt
+//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! Disables the indicated timer interrupt sources. Only the sources that are
+//! enabled can be reflected to the processor interrupt; disabled sources have
+//! no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param bMasked is false if the raw interrupt status is required and true if
+//! the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the timer module. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return The current interrupt status, enumerated as a bit field of
+//! values described in TimerIntEnable().
+//
+//*****************************************************************************
+unsigned long
+TimerIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ return(bMasked ? HWREG(ulBase + TIMER_O_MIS) :
+ HWREG(ulBase + TIMER_O_RIS));
+}
+
+//*****************************************************************************
+//
+//! Clears timer interrupt sources.
+//!
+//! \param ulBase is the base address of the timer module.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified timer interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being triggered again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to TimerIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + TIMER_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enables the events that can trigger a DMA request.
+//!
+//! \param ui32Base is the base address of the timer module.
+//! \param ui32DMAEvent is a bit mask of the events that can trigger DMA.
+//!
+//! This function enables the timer events that can trigger the start of a DMA
+//! sequence. The DMA trigger events are specified in the \e ui32DMAEvent
+//! parameter by passing in the logical OR of the following values:
+//!
+//! - \b TIMER_DMA_MODEMATCH_B - The mode match DMA trigger for timer B is
+//! enabled.
+//! - \b TIMER_DMA_CAPEVENT_B - The capture event DMA trigger for timer B is
+//! enabled.
+//! - \b TIMER_DMA_CAPMATCH_B - The capture match DMA trigger for timer B is
+//! enabled.
+//! - \b TIMER_DMA_TIMEOUT_B - The timeout DMA trigger for timer B is enabled.
+//! - \b TIMER_DMA_MODEMATCH_A - The mode match DMA trigger for timer A is
+//! enabled.
+//! - \b TIMER_DMA_CAPEVENT_A - The capture event DMA trigger for timer A is
+//! enabled.
+//! - \b TIMER_DMA_CAPMATCH_A - The capture match DMA trigger for timer A is
+//! enabled.
+//! - \b TIMER_DMA_TIMEOUT_A - The timeout DMA trigger for timer A is enabled.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Set the DMA triggers.
+ //
+ HWREG(ulBase + TIMER_O_DMAEV) = ulDMAEvent;
+}
+
+//*****************************************************************************
+//
+//! Returns the events that can trigger a DMA request.
+//!
+//! \param ui32Base is the base address of the timer module.
+//!
+//! This function returns the timer events that can trigger the start of a DMA
+//! sequence. The DMA trigger events are the logical OR of the following
+//! values:
+//!
+//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match DMA trigger for timer
+//! B.
+//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event DMA trigger for
+//! timer B.
+//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match DMA trigger for
+//! timer B.
+//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout DMA trigger for timer B.
+//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match DMA trigger for timer
+//! A.
+//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event DMA trigger for
+//! timer A.
+//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match DMA trigger for
+//! timer A.
+//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout DMA trigger for timer A.
+//!
+//! \return The timer events that trigger the uDMA.
+//
+//*****************************************************************************
+unsigned long
+TimerDMAEventGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(TimerBaseValid(ulBase));
+
+ //
+ // Return the current DMA triggers.
+ //
+ return(HWREG(ulBase + TIMER_O_DMAEV));
+}
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/timer.h b/cc3200/hal/timer.h
new file mode 100644
index 0000000000..d16fc9a6e4
--- /dev/null
+++ b/cc3200/hal/timer.h
@@ -0,0 +1,208 @@
+//*****************************************************************************
+//
+// timer.h
+//
+// Prototypes for the timer module
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __TIMER_H__
+#define __TIMER_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerConfigure as the ulConfig parameter.
+//
+//*****************************************************************************
+
+#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
+#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
+ // timer
+#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
+#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
+ // timer
+#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
+
+#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
+#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
+#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
+#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
+#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
+#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
+#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
+#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
+#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
+#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
+#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
+#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
+#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
+#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
+#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
+#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
+#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
+#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerIntEnable, TimerIntDisable, and
+// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
+//
+//*****************************************************************************
+
+#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt
+#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
+#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
+#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
+#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
+#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt
+#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
+#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
+#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
+#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerControlEvent as the ulEvent parameter.
+//
+//*****************************************************************************
+#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
+#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
+#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
+
+//*****************************************************************************
+//
+// Values that can be passed to most of the timer APIs as the ulTimer
+// parameter.
+//
+//*****************************************************************************
+#define TIMER_A 0x000000ff // Timer A
+#define TIMER_B 0x0000ff00 // Timer B
+#define TIMER_BOTH 0x0000ffff // Timer Both
+
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerSynchronize as the ulTimers parameter.
+//
+//*****************************************************************************
+#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
+#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
+#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
+#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
+#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
+#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
+#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
+#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
+
+//*****************************************************************************
+//
+// Values that can be passed to TimerDMAEventSet() or returned from
+// TimerDMAEventGet().
+//
+//*****************************************************************************
+#define TIMER_DMA_MODEMATCH_B 0x00000800
+#define TIMER_DMA_CAPEVENT_B 0x00000400
+#define TIMER_DMA_CAPMATCH_B 0x00000200
+#define TIMER_DMA_TIMEOUT_B 0x00000100
+#define TIMER_DMA_MODEMATCH_A 0x00000010
+#define TIMER_DMA_CAPEVENT_A 0x00000004
+#define TIMER_DMA_CAPMATCH_A 0x00000002
+#define TIMER_DMA_TIMEOUT_A 0x00000001
+
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
+extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bInvert);
+extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulEvent);
+extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
+ tBoolean bStall);
+extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerPrescaleGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
+
+extern unsigned long TimerValueGet(unsigned long ulBase,
+ unsigned long ulTimer);
+
+extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
+ unsigned long ulValue);
+extern unsigned long TimerMatchGet(unsigned long ulBase,
+ unsigned long ulTimer);
+extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
+ void (*pfnHandler)(void));
+extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
+extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent);
+extern unsigned long TimerDMAEventGet(unsigned long ulBase);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __TIMER_H__
diff --git a/cc3200/hal/uart.c b/cc3200/hal/uart.c
new file mode 100644
index 0000000000..b00bbeeb18
--- /dev/null
+++ b/cc3200/hal/uart.c
@@ -0,0 +1,1518 @@
+//*****************************************************************************
+//
+// uart.c
+//
+// Driver for the UART.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup UART_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_uart.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "uart.h"
+
+
+//*****************************************************************************
+//
+// A mapping of UART base address to interupt number.
+//
+//*****************************************************************************
+static const unsigned long g_ppulUARTIntMap[][2] =
+{
+ { UARTA0_BASE, INT_UARTA0 },
+ { UARTA1_BASE, INT_UARTA1 },
+};
+
+//*****************************************************************************
+//
+//! \internal
+//! Checks a UART base address.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function determines if a UART port base address is valid.
+//!
+//! \return Returns \b true if the base address is valid and \b false
+//! otherwise.
+//
+//*****************************************************************************
+#ifdef DEBUG
+static tBoolean
+UARTBaseValid(unsigned long ulBase)
+{
+ return((ulBase == UARTA0_BASE) || (ulBase == UARTA1_BASE));
+}
+#else
+#define UARTBaseValid(ulBase) (ulBase)
+#endif
+
+//*****************************************************************************
+//
+//! \internal
+//! Gets the UART interrupt number.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Given a UART base address, returns the corresponding interrupt number.
+//!
+//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid.
+//
+//*****************************************************************************
+static long
+UARTIntNumberGet(unsigned long ulBase)
+{
+ unsigned long ulIdx;
+
+ //
+ // Loop through the table that maps UART base addresses to interrupt
+ // numbers.
+ //
+ for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) /
+ sizeof(g_ppulUARTIntMap[0])); ulIdx++)
+ {
+ //
+ // See if this base address matches.
+ //
+ if(g_ppulUARTIntMap[ulIdx][0] == ulBase)
+ {
+ //
+ // Return the corresponding interrupt number.
+ //
+ return(g_ppulUARTIntMap[ulIdx][1]);
+ }
+ }
+
+ //
+ // The base address could not be found, so return an error.
+ //
+ return(-1);
+}
+
+//*****************************************************************************
+//
+//! Sets the type of parity.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulParity specifies the type of parity to use.
+//!
+//! This function sets the type of parity to use for transmitting and expect
+//! when receiving. The \e ulParity parameter must be one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two allow
+//! direct control of the parity bit; it is always either one or zero based on
+//! the mode.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTParityModeSet(unsigned long ulBase, unsigned long ulParity)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulParity == UART_CONFIG_PAR_NONE) ||
+ (ulParity == UART_CONFIG_PAR_EVEN) ||
+ (ulParity == UART_CONFIG_PAR_ODD) ||
+ (ulParity == UART_CONFIG_PAR_ONE) ||
+ (ulParity == UART_CONFIG_PAR_ZERO));
+
+ //
+ // Set the parity mode.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) &
+ ~(UART_LCRH_SPS | UART_LCRH_EPS |
+ UART_LCRH_PEN)) | ulParity);
+}
+
+//*****************************************************************************
+//
+//! Gets the type of parity currently being used.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function gets the type of parity used for transmitting data and
+//! expected when receiving data.
+//!
+//! \return Returns the current parity settings, specified as one of
+//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD,
+//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO.
+//
+//*****************************************************************************
+unsigned long
+UARTParityModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current parity setting.
+ //
+ return(HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Sets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of
+//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8,
+//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of
+//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8,
+//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function sets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulTxLevel == UART_FIFO_TX1_8) ||
+ (ulTxLevel == UART_FIFO_TX2_8) ||
+ (ulTxLevel == UART_FIFO_TX4_8) ||
+ (ulTxLevel == UART_FIFO_TX6_8) ||
+ (ulTxLevel == UART_FIFO_TX7_8));
+ ASSERT((ulRxLevel == UART_FIFO_RX1_8) ||
+ (ulRxLevel == UART_FIFO_RX2_8) ||
+ (ulRxLevel == UART_FIFO_RX4_8) ||
+ (ulRxLevel == UART_FIFO_RX6_8) ||
+ (ulRxLevel == UART_FIFO_RX7_8));
+
+ //
+ // Set the FIFO interrupt levels.
+ //
+ HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel;
+}
+
+//*****************************************************************************
+//
+//! Gets the FIFO level at which interrupts are generated.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pulTxLevel is a pointer to storage for the transmit FIFO level,
+//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8,
+//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8.
+//! \param pulRxLevel is a pointer to storage for the receive FIFO level,
+//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8,
+//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8.
+//!
+//! This function gets the FIFO level at which transmit and receive interrupts
+//! are generated.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Read the FIFO level register.
+ //
+ ulTemp = HWREG(ulBase + UART_O_IFLS);
+
+ //
+ // Extract the transmit and receive FIFO levels.
+ //
+ *pulTxLevel = ulTemp & UART_IFLS_TX_M;
+ *pulRxLevel = ulTemp & UART_IFLS_RX_M;
+}
+
+//*****************************************************************************
+//
+//! Sets the configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param ulBaud is the desired baud rate.
+//! \param ulConfig is the data format for the port (number of data bits,
+//! number of stop bits, and parity).
+//!
+//! This function configures the UART for operation in the specified data
+//! format. The baud rate is provided in the \e ulBaud parameter and the data
+//! format in the \e ulConfig parameter.
+//!
+//! The \e ulConfig parameter is the logical OR of three values: the number of
+//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8,
+//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5
+//! select from eight to five data bits per byte (respectively).
+//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop
+//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN,
+//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO
+//! select the parity mode (no parity bit, even parity bit, odd parity bit,
+//! parity bit always one, and parity bit always zero, respectively).
+//!
+//! The peripheral clock is the same as the processor clock. The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig)
+{
+ unsigned long ulDiv;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT(ulBaud != 0);
+
+ //
+ // Stop the UART.
+ //
+ UARTDisable(ulBase);
+
+ //
+ // Is the required baud rate greater than the maximum rate supported
+ // without the use of high speed mode?
+ //
+ if((ulBaud * 16) > ulUARTClk)
+ {
+ //
+ // Enable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE;
+
+ //
+ // Half the supplied baud rate to compensate for enabling high speed
+ // mode. This allows the following code to be common to both cases.
+ //
+ ulBaud /= 2;
+ }
+ else
+ {
+ //
+ // Disable high speed mode.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE);
+ }
+
+ //
+ // Compute the fractional baud rate divider.
+ //
+ ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2;
+
+ //
+ // Set the baud rate.
+ //
+ HWREG(ulBase + UART_O_IBRD) = ulDiv / 64;
+ HWREG(ulBase + UART_O_FBRD) = ulDiv % 64;
+
+ //
+ // Set parity, data length, and number of stop bits.
+ //
+ HWREG(ulBase + UART_O_LCRH) = ulConfig;
+
+ //
+ // Clear the flags register.
+ //
+ HWREG(ulBase + UART_O_FR) = 0;
+
+ //
+ // Start the UART.
+ //
+ UARTEnable(ulBase);
+}
+
+//*****************************************************************************
+//
+//! Gets the current configuration of a UART.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulUARTClk is the rate of the clock supplied to the UART module.
+//! \param pulBaud is a pointer to storage for the baud rate.
+//! \param pulConfig is a pointer to storage for the data format.
+//!
+//! The baud rate and data format for the UART is determined, given an
+//! explicitly provided peripheral clock (hence the ExpClk suffix). The
+//! returned baud rate is the actual baud rate; it may not be the exact baud
+//! rate requested or an ``official'' baud rate. The data format returned in
+//! \e pulConfig is enumerated the same as the \e ulConfig parameter of
+//! UARTConfigSetExpClk().
+//!
+//! The peripheral clock is the same as the processor clock. The frequency of
+//! the system clock is the value returned by SysCtlClockGet(), or it can be
+//! explicitly hard coded if it is constant and known (to save the
+//! code/execution overhead of a call to SysCtlClockGet()).
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud, unsigned long *pulConfig)
+{
+ unsigned long ulInt, ulFrac;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Compute the baud rate.
+ //
+ ulInt = HWREG(ulBase + UART_O_IBRD);
+ ulFrac = HWREG(ulBase + UART_O_FBRD);
+ *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac);
+
+ //
+ // See if high speed mode enabled.
+ //
+ if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE)
+ {
+ //
+ // High speed mode is enabled so the actual baud rate is actually
+ // double what was just calculated.
+ //
+ *pulBaud *= 2;
+ }
+
+ //
+ // Get the parity, data length, and number of stop bits.
+ //
+ *pulConfig = (HWREG(ulBase + UART_O_LCRH) &
+ (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 |
+ UART_LCRH_EPS | UART_LCRH_PEN));
+}
+
+//*****************************************************************************
+//
+//! Enables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit
+//! and receive FIFOs.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+
+ //
+ // Enable RX, TX, and the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Disables transmitting and receiving.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of
+//! transmission of the current character, and flushes the transmit FIFO.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait for end of TX.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY)
+ {
+ }
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+
+ //
+ // Disable the UART.
+ //
+ HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE |
+ UART_CTL_RXE);
+}
+
+//*****************************************************************************
+//
+//! Enables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions enables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFOEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN;
+}
+
+//*****************************************************************************
+//
+//! Disables the transmit and receive FIFOs.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This functions disables the transmit and receive FIFOs in the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFIFODisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the FIFO.
+ //
+ HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN);
+}
+
+//*****************************************************************************
+//
+//! Sets the states of the RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! This function sets the states of the RTS modem handshake outputs
+//! from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlSet(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+
+ ASSERT(ulBase == UARTA1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp |= (ulControl & (UART_OUTPUT_RTS));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Clears the states of the RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulControl is a bit-mapped flag indicating which modem control bits
+//! should be set.
+//!
+//! This function clears the states of the RTS modem handshake outputs
+//! from the UART.
+//!
+//! The \e ulControl parameter is the logical OR of any of the following:
+//!
+//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTModemControlClear(unsigned long ulBase, unsigned long ulControl)
+{
+ unsigned long ulTemp;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == UARTA1_BASE);
+ ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0);
+
+ //
+ // Set the appropriate modem control output bits.
+ //
+ ulTemp = HWREG(ulBase + UART_O_CTL);
+ ulTemp &= ~(ulControl & (UART_OUTPUT_RTS));
+ HWREG(ulBase + UART_O_CTL) = ulTemp;
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the RTS modem control signals.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current states of each of the UART modem
+//! control signal, RTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signal.
+//
+//*****************************************************************************
+unsigned long
+UARTModemControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(ulBase == UARTA1_BASE);
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS));
+}
+
+//*****************************************************************************
+//
+//! Gets the states of the CTS modem status signal.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current states of the UART modem status signal,
+//! CTS.
+//!
+//! \note The availability of hardware modem handshake signals varies with the
+//! part and UART in use. Please consult the datasheet for the part
+//! you are using to determine whether this support is available.
+//!
+//! \return Returns the states of the handshake output signal
+//
+//*****************************************************************************
+unsigned long
+UARTModemStatusGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+
+ ASSERT(ulBase == UARTA1_BASE);
+
+ return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_CTS));
+}
+
+//*****************************************************************************
+//
+//! Sets the UART hardware flow control mode to be used.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode indicates the flow control modes to be used. This parameter
+//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and
+//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS)
+//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control.
+//!
+//! This function sets the required hardware flow control modes. If \e ulMode
+//! contains flag \b UART_FLOWCONTROL_TX, data is only transmitted if the
+//! incoming CTS signal is asserted. If \e ulMode contains flag
+//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is
+//! asserted only when there is space available in the receive FIFO. If no
+//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be
+//! passed.
+//!
+//! \note The availability of hardware flow control varies with the
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0);
+
+ //
+ // Set the flow control mode as requested.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the UART hardware flow control mode currently in use.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current hardware flow control mode.
+//!
+//! \note The availability of hardware flow control varies with the
+//! part and UART in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns the current flow control mode in use. This is a
+//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit
+//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS)
+//! flow control is in use. If hardware flow control is disabled,
+//! \b UART_FLOWCONTROL_NONE is returned.
+//
+//*****************************************************************************
+unsigned long
+UARTFlowControlGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+
+ ASSERT(UARTBaseValid(ulBase));
+
+ return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX |
+ UART_FLOWCONTROL_RX));
+}
+
+//*****************************************************************************
+//
+//! Sets the operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulMode is the operating mode for the transmit interrupt. It may be
+//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle
+//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO
+//! level.
+//!
+//! This function allows the mode of the UART transmit interrupt to be set. By
+//! default, the transmit interrupt is asserted when the FIFO level falls past
+//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this
+//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the
+//! transmit interrupt is asserted once the transmitter is completely idle -
+//! the transmit FIFO is empty and all bits, including any stop bits, have
+//! cleared the transmitter.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+ ASSERT((ulMode == UART_TXINT_MODE_EOT) ||
+ (ulMode == UART_TXINT_MODE_FIFO));
+
+ //
+ // Set or clear the EOT bit of the UART control register as appropriate.
+ //
+ HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) &
+ ~(UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO)) | ulMode);
+}
+
+//*****************************************************************************
+//
+//! Returns the current operating mode for the UART transmit interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current operating mode for the UART transmit
+//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit
+//! interrupt is currently set to be asserted once the transmitter is
+//! completely idle - the transmit FIFO is empty and all bits, including any
+//! stop bits, have cleared the transmitter. The return value is
+//! \b UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon
+//! the level of the transmit FIFO.
+//!
+//! \note The availability of end-of-transmission mode varies with the
+//! part in use. Please consult the datasheet for the part you are
+//! using to determine whether this support is available.
+//!
+//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT.
+//
+//*****************************************************************************
+unsigned long
+UARTTxIntModeGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current transmit interrupt mode.
+ //
+ return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT |
+ UART_TXINT_MODE_FIFO));
+}
+
+//*****************************************************************************
+//
+//! Determines if there are any characters in the receive FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is data
+//! available in the receive FIFO.
+//!
+//! \return Returns \b true if there is data in the receive FIFO or \b false
+//! if there is no data in the receive FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharsAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of characters.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Determines if there is any space in the transmit FIFO.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns a flag indicating whether or not there is space
+//! available in the transmit FIFO.
+//!
+//! \return Returns \b true if there is space available in the transmit FIFO
+//! or \b false if there is no space available in the transmit FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTSpaceAvail(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the availability of space.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true);
+}
+
+//*****************************************************************************
+//
+//! Receives a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port.
+//!
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e long. A \b -1 is returned if there are no characters present in the
+//! receive FIFO. The UARTCharsAvail() function should be called before
+//! attempting to call this function.
+//
+//*****************************************************************************
+long
+UARTCharGetNonBlocking(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there are any characters in the receive FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE))
+ {
+ //
+ // Read and return the next character.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+ }
+ else
+ {
+ //
+ // There are no characters, so return a failure.
+ //
+ return(-1);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits for a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function gets a character from the receive FIFO for the specified
+//! port. If there are no characters available, this function waits until a
+//! character is received before returning.
+//!
+//! \return Returns the character read from the specified port, cast as a
+//! \e long.
+//
+//*****************************************************************************
+long
+UARTCharGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until a char is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)
+ {
+ }
+
+ //
+ // Now get the char.
+ //
+ return(HWREG(ulBase + UART_O_DR));
+}
+
+//*****************************************************************************
+//
+//! Sends a character to the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! This function writes the character \e ucData to the transmit FIFO for the
+//! specified port. This function does not block, so if there is no space
+//! available, then a \b false is returned, and the application must retry the
+//! function later.
+//!
+//! \return Returns \b true if the character was successfully placed in the
+//! transmit FIFO or \b false if there was no space available in the transmit
+//! FIFO.
+//
+//*****************************************************************************
+tBoolean
+UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // See if there is space in the transmit FIFO.
+ //
+ if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF))
+ {
+ //
+ // Write this character to the transmit FIFO.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+
+ //
+ // Success.
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // There is no space in the transmit FIFO, so return a failure.
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Waits to send a character from the specified port.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ucData is the character to be transmitted.
+//!
+//! This function sends the character \e ucData to the transmit FIFO for the
+//! specified port. If there is no space available in the transmit FIFO, this
+//! function waits until there is space available before returning.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTCharPut(unsigned long ulBase, unsigned char ucData)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Wait until space is available.
+ //
+ while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)
+ {
+ }
+
+ //
+ // Send the char.
+ //
+ HWREG(ulBase + UART_O_DR) = ucData;
+}
+
+//*****************************************************************************
+//
+//! Causes a BREAK to be sent.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bBreakState controls the output level.
+//!
+//! Calling this function with \e bBreakState set to \b true asserts a break
+//! condition on the UART. Calling this function with \e bBreakState set to
+//! \b false removes the break condition. For proper transmission of a break
+//! command, the break must be asserted for at least two complete frames.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the break condition as requested.
+ //
+ HWREG(ulBase + UART_O_LCRH) =
+ (bBreakState ?
+ (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) :
+ (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK)));
+}
+
+//*****************************************************************************
+//
+//! Determines whether the UART transmitter is busy or not.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! Allows the caller to determine whether all transmitted bytes have cleared
+//! the transmitter hardware. If \b false is returned, the transmit FIFO is
+//! empty and all bits of the last transmitted character, including all stop
+//! bits, have left the hardware shift register.
+//!
+//! \return Returns \b true if the UART is transmitting or \b false if all
+//! transmissions are complete.
+//
+//*****************************************************************************
+tBoolean
+UARTBusy(unsigned long ulBase)
+{
+ //
+ // Check the argument.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine if the UART is busy.
+ //
+ return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! UART interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller; specific
+//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+#if 1
+ ulInt = UARTIntNumberGet(ulBase);
+#else
+
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+#endif
+
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(ulInt, pfnHandler);
+
+ //
+ // Enable the UART interrupt.
+ //
+ IntEnable(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for a UART interrupt.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a UART interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntUnregister(unsigned long ulBase)
+{
+ unsigned long ulInt;
+
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Determine the interrupt number based on the UART port.
+ //
+#if 1
+ ulInt = UARTIntNumberGet(ulBase);
+#else
+ ulInt = ((ulBase == UART0_BASE) ? INT_UART0 :
+ ((ulBase == UART1_BASE) ? INT_UART1 : INT_UART2));
+#endif
+
+ //
+ // Disable the interrupt.
+ //
+ IntDisable(ulInt);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(ulInt);
+}
+
+//*****************************************************************************
+//
+//! Enables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated UART interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//!
+//! - \b UART_INT_OE - Overrun Error interrupt
+//! - \b UART_INT_BE - Break Error interrupt
+//! - \b UART_INT_PE - Parity Error interrupt
+//! - \b UART_INT_FE - Framing Error interrupt
+//! - \b UART_INT_RT - Receive Timeout interrupt
+//! - \b UART_INT_TX - Transmit interrupt
+//! - \b UART_INT_RX - Receive interrupt
+//! - \b UART_INT_CTS - CTS interrupt
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Enable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) |= ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Disables individual UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated UART interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Disable the specified interrupts.
+ //
+ HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags);
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This function returns the interrupt status for the specified UART. Either
+//! the raw interrupt status or the status of interrupts that are allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, enumerated as a bit field of
+//! values described in UARTIntEnable().
+//
+//*****************************************************************************
+unsigned long
+UARTIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + UART_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + UART_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears UART interrupt sources.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
+//!
+//! The specified UART interrupt sources are cleared, so that they no longer
+//! assert. This function must be called in the interrupt handler to keep the
+//! interrupt from being recognized again immediately upon exit.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to UARTIntEnable().
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested interrupt sources.
+ //
+ HWREG(ulBase + UART_O_ICR) = ulIntFlags;
+}
+
+//*****************************************************************************
+//
+//! Enable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to enable.
+//!
+//! The specified UART DMA features are enabled. The UART can be
+//! configured to use DMA for transmit or receive, and to disable
+//! receive if an error occurs. The \e ulDMAFlags parameter is the
+//! logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - enable DMA for receive
+//! - UART_DMA_TX - enable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error
+//!
+//! \note The uDMA controller must also be set up before DMA can be used
+//! with the UART.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Set the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Disable UART DMA operation.
+//!
+//! \param ulBase is the base address of the UART port.
+//! \param ulDMAFlags is a bit mask of the DMA features to disable.
+//!
+//! This function is used to disable UART DMA features that were enabled
+//! by UARTDMAEnable(). The specified UART DMA features are disabled. The
+//! \e ulDMAFlags parameter is the logical OR of any of the following values:
+//!
+//! - UART_DMA_RX - disable DMA for receive
+//! - UART_DMA_TX - disable DMA for transmit
+//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Clear the requested bits in the UART DMA control register.
+ //
+ HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets current receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function returns the current state of each of the 4 receiver error
+//! sources. The returned errors are equivalent to the four error bits
+//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking()
+//! with the exception that the overrun error is set immediately the overrun
+//! occurs rather than when a character is next read.
+//!
+//! \return Returns a logical OR combination of the receiver error flags,
+//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK
+//! and \b UART_RXERROR_OVERRUN.
+//
+//*****************************************************************************
+unsigned long
+UARTRxErrorGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Return the current value of the receive status register.
+ //
+ return(HWREG(ulBase + UART_O_RSR) & 0x0000000F);
+}
+
+//*****************************************************************************
+//
+//! Clears all reported receiver errors.
+//!
+//! \param ulBase is the base address of the UART port.
+//!
+//! This function is used to clear all receiver error conditions reported via
+//! UARTRxErrorGet(). If using the overrun, framing error, parity error or
+//! break interrupts, this function must be called after clearing the interrupt
+//! to ensure that later errors of the same type trigger another interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+UARTRxErrorClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT(UARTBaseValid(ulBase));
+
+ //
+ // Any write to the Error Clear Register will clear all bits which are
+ // currently set.
+ //
+ HWREG(ulBase + UART_O_ECR) = 0;
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/uart.h b/cc3200/hal/uart.h
new file mode 100644
index 0000000000..503cd2c9e2
--- /dev/null
+++ b/cc3200/hal/uart.h
@@ -0,0 +1,234 @@
+//*****************************************************************************
+//
+// uart.h
+//
+// Defines and Macros for the UART.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __UART_H__
+#define __UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ulIntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask
+#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask
+#define UART_INT_EOT 0x800 // End of transfer interrupt Mask
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask
+#define UART_INT_RX 0x010 // Receive Interrupt Mask
+#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
+
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
+// and returned by UARTConfigGetExpClk in the pulConfig parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ulParity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
+#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
+#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulTxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulRxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN 0x00000008
+#define UART_RXERROR_BREAK 0x00000004
+#define UART_RXERROR_PARITY 0x00000002
+#define UART_RXERROR_FRAMING 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTModemControlSet()and UARTModemControlClear()
+// or returned from UARTModemControlGet().
+//
+//*****************************************************************************
+#define UART_OUTPUT_RTS 0x00000800
+
+//*****************************************************************************
+//
+// Values that can be returned from UARTModemStatusGet().
+//
+//*****************************************************************************
+#define UART_INPUT_CTS 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFlowControl() or returned from
+// UARTFlowControlGet().
+//
+//*****************************************************************************
+#define UART_FLOWCONTROL_TX 0x00008000
+#define UART_FLOWCONTROL_RX 0x00004000
+#define UART_FLOWCONTROL_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTTxIntModeSet() or returned from
+// UARTTxIntModeGet().
+//
+//*****************************************************************************
+#define UART_TXINT_MODE_FIFO 0x00000000
+#define UART_TXINT_MODE_EOT 0x00000010
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
+extern unsigned long UARTParityModeGet(unsigned long ulBase);
+extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel);
+extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel);
+extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig);
+extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud,
+ unsigned long *pulConfig);
+extern void UARTEnable(unsigned long ulBase);
+extern void UARTDisable(unsigned long ulBase);
+extern void UARTFIFOEnable(unsigned long ulBase);
+extern void UARTFIFODisable(unsigned long ulBase);
+extern tBoolean UARTCharsAvail(unsigned long ulBase);
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);
+extern long UARTCharGetNonBlocking(unsigned long ulBase);
+extern long UARTCharGet(unsigned long ulBase);
+extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
+ unsigned char ucData);
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
+extern tBoolean UARTBusy(unsigned long ulBase);
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void UARTIntUnregister(unsigned long ulBase);
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern unsigned long UARTRxErrorGet(unsigned long ulBase);
+extern void UARTRxErrorClear(unsigned long ulBase);
+extern void UARTModemControlSet(unsigned long ulBase,
+ unsigned long ulControl);
+extern void UARTModemControlClear(unsigned long ulBase,
+ unsigned long ulControl);
+extern unsigned long UARTModemControlGet(unsigned long ulBase);
+extern unsigned long UARTModemStatusGet(unsigned long ulBase);
+extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTFlowControlGet(unsigned long ulBase);
+extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UART_H__
diff --git a/cc3200/hal/utils.c b/cc3200/hal/utils.c
new file mode 100644
index 0000000000..d0b13d7bfd
--- /dev/null
+++ b/cc3200/hal/utils.c
@@ -0,0 +1,104 @@
+//*****************************************************************************
+//
+// utils.c
+//
+// Utility APIs
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup Utils_api
+//! @{
+//
+//*****************************************************************************
+#include "utils.h"
+
+
+//*****************************************************************************
+//
+//! Provides a small delay.
+//!
+//! \param ulCount is the number of delay loop iterations to perform.
+//!
+//! This function provides a means of generating a constant length delay. It
+//! is written in assembly to keep the delay consistent across tool chains,
+//! avoiding the need to tune the delay based on the tool chain in use.
+//!
+//! The loop takes 3 cycles/loop.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(DOXYGEN)
+void
+UtilsDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne.n UtilsDelay\n");
+}
+#endif
+
+#if defined(gcc)
+void __attribute__((naked))
+UtilsDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne UtilsDelay\n"
+ " bx lr");
+}
+#endif
+
+//
+// For CCS implement this function in pure assembly. This prevents the TI
+// compiler from doing funny things with the optimizer.
+//
+#if defined(ccs)
+ __asm(" .sect \".text:UtilsDelay\"\n"
+ " .clink\n"
+ " .thumbfunc UtilsDelay\n"
+ " .thumb\n"
+ " .global UtilsDelay\n"
+ "UtilsDelay:\n"
+ " subs r0, #1\n"
+ " bne.n UtilsDelay\n"
+ " bx lr\n");
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/utils.h b/cc3200/hal/utils.h
new file mode 100644
index 0000000000..a6fa78dac3
--- /dev/null
+++ b/cc3200/hal/utils.h
@@ -0,0 +1,71 @@
+//*****************************************************************************
+//
+// utils.h
+//
+// Prototypes and macros for utility APIs
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __UTILS_H__
+#define __UTILS_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UtilsDelay(unsigned long ulCount);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__UTILS_H__
diff --git a/cc3200/hal/wdt.c b/cc3200/hal/wdt.c
new file mode 100644
index 0000000000..8d8a9e9df6
--- /dev/null
+++ b/cc3200/hal/wdt.c
@@ -0,0 +1,491 @@
+//*****************************************************************************
+//
+// wdt.c
+//
+// Driver for the Watchdog Timer Module.
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup WDT_Watchdog_Timer_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_types.h"
+#include "inc/hw_wdt.h"
+#include "debug.h"
+#include "interrupt.h"
+#include "wdt.h"
+
+//*****************************************************************************
+//
+//! Determines if the watchdog timer is enabled.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This will check to see if the watchdog timer is enabled.
+//!
+//! \return Returns \b true if the watchdog timer is enabled, and \b false
+//! if it is not.
+//
+//*****************************************************************************
+tBoolean
+WatchdogRunning(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // See if the watchdog timer module is enabled, and return.
+ //
+ return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This will enable the watchdog timer counter and interrupt.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Enable the watchdog timer module.
+ //
+ HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
+}
+
+//*****************************************************************************
+//
+//! Enables the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Locks out write access to the watchdog timer configuration registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogLock(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
+ // register causes the lock to go into effect.
+ //
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
+}
+
+//*****************************************************************************
+//
+//! Disables the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Enables write access to the watchdog timer configuration registers.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogUnlock(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Unlock watchdog register writes.
+ //
+ HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
+}
+
+//*****************************************************************************
+//
+//! Gets the state of the watchdog timer lock mechanism.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! Returns the lock state of the watchdog timer registers.
+//!
+//! \return Returns \b true if the watchdog timer registers are locked, and
+//! \b false if they are not locked.
+//
+//*****************************************************************************
+tBoolean
+WatchdogLockState(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Get the lock state.
+ //
+ return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
+}
+
+//*****************************************************************************
+//
+//! Sets the watchdog timer reload value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param ulLoadVal is the load value for the watchdog timer.
+//!
+//! This function sets the value to load into the watchdog timer when the count
+//! reaches zero for the first time; if the watchdog timer is running when this
+//! function is called, then the value will be immediately loaded into the
+//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
+//! interrupt is immediately generated.
+//!
+//! \note This function will have no effect if the watchdog timer has
+//! been locked.
+//!
+//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Set the load register.
+ //
+ HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
+}
+
+//*****************************************************************************
+//
+//! Gets the watchdog timer reload value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function gets the value that is loaded into the watchdog timer when
+//! the count reaches zero for the first time.
+//!
+//! \sa WatchdogReloadSet()
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long
+WatchdogReloadGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Get the load register.
+ //
+ return(HWREG(ulBase + WDT_O_LOAD));
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer value.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function reads the current value of the watchdog timer.
+//!
+//! \return Returns the current value of the watchdog timer.
+//
+//*****************************************************************************
+unsigned long
+WatchdogValueGet(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Get the current watchdog timer register value.
+ //
+ return(HWREG(ulBase + WDT_O_VALUE));
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param pfnHandler is a pointer to the function to be called when the
+//! watchdog timer interrupt occurs.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! will enable the global interrupt in the interrupt controller; the watchdog
+//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
+//! handler's responsibility to clear the interrupt source via
+//! WatchdogIntClear().
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note This function will only register the standard watchdog interrupt
+//! handler. To register the NMI watchdog handler, use IntRegister()
+//! to register the handler for the \b FAULT_NMI interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Register the interrupt handler and
+ // Enable the watchdog timer interrupt.
+ //
+ IntRegister(INT_WDT, pfnHandler);
+ IntEnable(INT_WDT);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function does the actual unregistering of the interrupt handler. This
+//! function will clear the handler to be called when a watchdog timer
+//! interrupt occurs. This will also mask off the interrupt in the interrupt
+//! controller so that the interrupt handler no longer is called.
+//!
+//! \sa IntRegister() for important information about registering interrupt
+//! handlers.
+//!
+//! \note This function will only unregister the standard watchdog interrupt
+//! handler. To unregister the NMI watchdog handler, use IntUnregister()
+//! to unregister the handler for the \b FAULT_NMI interrupt.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntUnregister(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Disable the interrupt
+ IntDisable(INT_WDT);
+
+ //
+ // Unregister the interrupt handler.
+ //
+ IntUnregister(INT_WDT);
+}
+
+//*****************************************************************************
+//
+//! Gets the current watchdog timer interrupt status.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//! \param bMasked is \b false if the raw interrupt status is required and
+//! \b true if the masked interrupt status is required.
+//!
+//! This returns the interrupt status for the watchdog timer module. Either
+//! the raw interrupt status or the status of interrupt that is allowed to
+//! reflect to the processor can be returned.
+//!
+//! \return Returns the current interrupt status, where a 1 indicates that the
+//! watchdog interrupt is active, and a 0 indicates that it is not active.
+//
+//*****************************************************************************
+unsigned long
+WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Return either the interrupt status or the raw interrupt status as
+ // requested.
+ //
+ if(bMasked)
+ {
+ return(HWREG(ulBase + WDT_O_MIS));
+ }
+ else
+ {
+ return(HWREG(ulBase + WDT_O_RIS));
+ }
+}
+
+//*****************************************************************************
+//
+//! Clears the watchdog timer interrupt.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! The watchdog timer interrupt source is cleared, so that it no longer
+//! asserts.
+//!
+//! \note Because there is a write buffer in the Cortex-M3 processor, it may
+//! take several clock cycles before the interrupt source is actually cleared.
+//! Therefore, it is recommended that the interrupt source be cleared early in
+//! the interrupt handler (as opposed to the very last action) to avoid
+//! returning from the interrupt handler before the interrupt source is
+//! actually cleared. Failure to do so may result in the interrupt handler
+//! being immediately reentered (because the interrupt controller still sees
+//! the interrupt source asserted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogIntClear(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Clear the interrupt source.
+ //
+ HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
+}
+
+//*****************************************************************************
+//
+//! Enables stalling of the watchdog timer during debug events.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function allows the watchdog timer to stop counting when the processor
+//! is stopped by the debugger. By doing so, the watchdog is prevented from
+//! expiring (typically almost immediately from a human time perspective) and
+//! resetting the system (if reset is enabled). The watchdog will instead
+//! expired after the appropriate number of processor cycles have been executed
+//! while debugging (or at the appropriate time after the processor has been
+//! restarted).
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallEnable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Enable timer stalling.
+ //
+ HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
+}
+
+//*****************************************************************************
+//
+//! Disables stalling of the watchdog timer during debug events.
+//!
+//! \param ulBase is the base address of the watchdog timer module.
+//!
+//! This function disables the debug mode stall of the watchdog timer. By
+//! doing so, the watchdog timer continues to count regardless of the processor
+//! debug state.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+WatchdogStallDisable(unsigned long ulBase)
+{
+ //
+ // Check the arguments.
+ //
+ ASSERT((ulBase == WDT_BASE));
+
+ //
+ // Disable timer stalling.
+ //
+ HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
+}
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/cc3200/hal/wdt.h b/cc3200/hal/wdt.h
new file mode 100644
index 0000000000..2e52db42be
--- /dev/null
+++ b/cc3200/hal/wdt.h
@@ -0,0 +1,82 @@
+//*****************************************************************************
+//
+// wdt.h - Prototypes for the Watchdog Timer API
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __WATCHDOG_H__
+#define __WATCHDOG_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean WatchdogRunning(unsigned long ulBase);
+extern void WatchdogEnable(unsigned long ulBase);
+extern void WatchdogLock(unsigned long ulBase);
+extern void WatchdogUnlock(unsigned long ulBase);
+extern tBoolean WatchdogLockState(unsigned long ulBase);
+extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
+extern unsigned long WatchdogReloadGet(unsigned long ulBase);
+extern unsigned long WatchdogValueGet(unsigned long ulBase);
+extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void WatchdogIntUnregister(unsigned long ulBase);
+extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void WatchdogIntClear(unsigned long ulBase);
+extern void WatchdogStallEnable(unsigned long ulBase);
+extern void WatchdogStallDisable(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __WATCHDOG_H__
diff --git a/cc3200/main.c b/cc3200/main.c
new file mode 100644
index 0000000000..20e93d384f
--- /dev/null
+++ b/cc3200/main.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "mptask.h"
+#include "simplelink.h"
+#include "osi.h"
+#include "debug.h"
+
+/******************************************************************************
+ DECLARE PRIVATE CONSTANTS
+ ******************************************************************************/
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+
+/******************************************************************************
+ DECLARE PRIVATE DATA
+ ******************************************************************************/
+
+/******************************************************************************
+ DECLARE PUBLIC DATA
+ ******************************************************************************/
+#ifdef DEBUG
+OsiTaskHandle mpTaskHandle;
+#endif
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+int main (void) {
+
+ // Initialize the clocks and the interrupt system
+ HAL_SystemInit();
+
+#ifdef DEBUG
+ ASSERT (OSI_OK == osi_TaskCreate(TASK_Micropython,
+ (const signed char *)"MicroPy",
+ MICROPY_TASK_STACK_SIZE, NULL, MICROPY_TASK_PRIORITY, &mpTaskHandle));
+#else
+ ASSERT (OSI_OK == osi_TaskCreate(TASK_Micropython,
+ (const signed char *)"MicroPy",
+ MICROPY_TASK_STACK_SIZE, NULL, MICROPY_TASK_PRIORITY, NULL));
+#endif
+
+ osi_start();
+
+ for ( ; ; );
+}
+
+
+void stoupper (char *str) {
+ while (str && *str != '\0') {
+ *str = (char)toupper((int)(*str));
+ str++;
+ }
+}
diff --git a/cc3200/misc/FreeRTOSHooks.c b/cc3200/misc/FreeRTOSHooks.c
new file mode 100644
index 0000000000..85dc2f373e
--- /dev/null
+++ b/cc3200/misc/FreeRTOSHooks.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "inc/hw_memmap.h"
+#include "pybuart.h"
+#include "pybstdio.h"
+#include "osi.h"
+
+
+#ifdef USE_FREERTOS
+
+//*****************************************************************************
+//
+//! \brief Application defined idle task hook
+//!
+//! \param none
+//!
+//! \return none
+//!
+//*****************************************************************************
+void
+vApplicationIdleHook( void)
+{
+ //Handle Idle Hook for Profiling, Power Management etc
+ __WFI();
+}
+
+//*****************************************************************************
+//
+//! \brief Application defined malloc failed hook
+//!
+//! \param none
+//!
+//! \return none
+//!
+//*****************************************************************************
+void vApplicationMallocFailedHook()
+{
+#ifdef DEBUG
+ // Break into the debugger
+ __asm volatile ("bkpt #0 \n");
+
+ printf("\nFATAL ERROR: FreeRTOS malloc failed!\n");
+#endif
+
+ //Handle Memory Allocation Errors
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Application defined stack overflow hook
+//!
+//! \param none
+//!
+//! \return none
+//!
+//*****************************************************************************
+void vApplicationStackOverflowHook( OsiTaskHandle *pxTask, signed char *pcTaskName)
+{
+#ifdef DEBUG
+ // Break into the debugger
+ __asm volatile ("bkpt #0 \n");
+
+ printf("\nFATAL ERROR: Application: %s stack overflow!\n", pcTaskName);
+#endif
+
+ //Handle FreeRTOS Stack Overflow
+ while(1)
+ {
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief Application defined tick hook
+//!
+//! \param none
+//!
+//! \return none
+//!
+//*****************************************************************************
+void vApplicationTickHook( void )
+{
+ HAL_IncrementTick();
+}
+
+#endif //USE_FREERTOS
diff --git a/cc3200/misc/gpio_named_pins.c b/cc3200/misc/gpio_named_pins.c
new file mode 100644
index 0000000000..884a462936
--- /dev/null
+++ b/cc3200/misc/gpio_named_pins.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "mpconfig.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "pybgpio.h"
+#include "runtime.h"
+#include MICROPY_HAL_H
+
+STATIC void gpio_named_pins_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) {
+ gpio_named_pins_obj_t *self = self_in;
+ print(env, "", qstr_str(self->name));
+}
+
+const mp_obj_type_t gpio_cpu_pins_obj_type = {
+ { &mp_type_type },
+ .name = MP_QSTR_cpu,
+ .print = gpio_named_pins_obj_print,
+ .locals_dict = (mp_obj_t)&gpio_cpu_pins_locals_dict,
+};
+
+const gpio_obj_t *gpio_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name) {
+ mp_map_t *named_map = mp_obj_dict_get_map((mp_obj_t)named_pins);
+ mp_map_elem_t *named_elem = mp_map_lookup(named_map, name, MP_MAP_LOOKUP);
+ if (named_elem != NULL && named_elem->value != NULL) {
+ return named_elem->value;
+ }
+ return NULL;
+}
diff --git a/cc3200/misc/help.c b/cc3200/misc/help.c
new file mode 100644
index 0000000000..67e800e051
--- /dev/null
+++ b/cc3200/misc/help.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+
+#include "mpconfig.h"
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+
+STATIC const char help_text[] = "Welcome to Micro Python!\n"
+ "For online help please visit http://micropython.org/help/.\n"
+ "For further help on a specific object, type help(obj)\n";
+
+STATIC void pyb_help_print_info_about_object(mp_obj_t name_o, mp_obj_t value) {
+ printf(" ");
+ mp_obj_print(name_o, PRINT_STR);
+ printf(" -- ");
+ mp_obj_print(value, PRINT_STR);
+ printf("\n");
+}
+
+STATIC mp_obj_t pyb_help(uint n_args, const mp_obj_t *args) {
+ if (n_args == 0) {
+ // print a general help message
+ printf("%s", help_text);
+
+ } else {
+ // try to print something sensible about the given object
+
+ printf("object ");
+ mp_obj_print(args[0], PRINT_STR);
+ printf(" is of type %s\n", mp_obj_get_type_str(args[0]));
+
+ mp_map_t *map = NULL;
+ if (MP_OBJ_IS_TYPE(args[0], &mp_type_module)) {
+ map = mp_obj_dict_get_map(mp_obj_module_get_globals(args[0]));
+ } else {
+ mp_obj_type_t *type;
+ if (MP_OBJ_IS_TYPE(args[0], &mp_type_type)) {
+ type = args[0];
+ } else {
+ type = mp_obj_get_type(args[0]);
+ }
+ if (type->locals_dict != MP_OBJ_NULL && MP_OBJ_IS_TYPE(type->locals_dict, &mp_type_dict)) {
+ map = mp_obj_dict_get_map(type->locals_dict);
+ }
+ }
+ if (map != NULL) {
+ for (uint i = 0; i < map->alloc; i++) {
+ if (map->table[i].key != MP_OBJ_NULL) {
+ pyb_help_print_info_about_object(map->table[i].key, map->table[i].value);
+ }
+ }
+ }
+ }
+
+ return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mp_builtin_help_obj, 0, 1, pyb_help);
diff --git a/cc3200/misc/mperror.c b/cc3200/misc/mperror.c
new file mode 100644
index 0000000000..d858813406
--- /dev/null
+++ b/cc3200/misc/mperror.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "inc/hw_memmap.h"
+#include "pybuart.h"
+#include "pybstdio.h"
+#include "utils.h"
+
+
+void NORETURN __fatal_error(const char *msg) {
+ if (msg != NULL) {
+ // wait for 20ms
+ UtilsDelay(UTILS_DELAY_US_TO_COUNT(20000));
+ stdout_tx_str("\r\nFATAL ERROR:");
+ stdout_tx_str(msg);
+ stdout_tx_str("\r\n");
+ }
+ for ( ;; ) {__WFI();}
+}
+
+void __assert_func(const char *file, int line, const char *func, const char *expr) {
+ (void) func;
+ printf("Assertion failed: %s, file %s, line %d\n", expr, file, line);
+ __fatal_error(NULL);
+}
+
+void nlr_jump_fail(void *val) {
+#ifdef DEBUG
+ char msg[64];
+ snprintf(msg, sizeof(msg), "uncaught exception %p\n", val);
+ __fatal_error(msg);
+#else
+ __fatal_error(NULL);
+#endif
+}
+
diff --git a/cc3200/misc/mperror.h b/cc3200/misc/mperror.h
new file mode 100644
index 0000000000..89a2abe8ef
--- /dev/null
+++ b/cc3200/misc/mperror.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifdef DEBUG
+extern void NORETURN __fatal_error(const char *msg);
+#else
+#define __fatal_error(...) for ( ;; ) {__WFI();}
+#endif
diff --git a/cc3200/misc/mpexception.c b/cc3200/misc/mpexception.c
new file mode 100644
index 0000000000..91cd997867
--- /dev/null
+++ b/cc3200/misc/mpexception.c
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "py/mpstate.h"
+#include "mpconfig.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "runtime.h"
+#include "mpexception.h"
+
+
+/******************************************************************************
+DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+STATIC void mpexception_set_user_interrupt (int chr, void *data);
+
+/******************************************************************************
+DECLARE EXPORTED DATA
+ ******************************************************************************/
+const char mpexception_os_resource_not_avaliable[] = "resource not available";
+const char mpexception_os_operation_failed[] = "the requested operation failed";
+const char mpexception_os_request_not_possible[] = "the requested operation is not possible";
+const char mpexception_value_invalid_arguments[] = "invalid argument(s) value";
+const char mpexception_num_type_invalid_arguments[] = "invalid argument(s) num/type";
+const char mpexception_uncaught[] = "uncaught exception";
+
+int user_interrupt_char = -1;
+
+/******************************************************************************
+DECLARE PRIVATE DATA
+ ******************************************************************************/
+STATIC void *user_interrupt_data = NULL;
+
+/******************************************************************************
+DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+void mpexception_init0 (void) {
+ // Create an exception object for interrupting through the stdin uart
+ MP_STATE_PORT(mp_const_user_interrupt) = mp_obj_new_exception(&mp_type_KeyboardInterrupt);
+ mpexception_set_user_interrupt (-1, MP_STATE_PORT(mp_const_user_interrupt));
+}
+
+void mpexception_set_interrupt_char (int c) {
+ if (c != -1) {
+ mp_obj_exception_clear_traceback(MP_STATE_PORT(mp_const_user_interrupt));
+ }
+ mpexception_set_user_interrupt(c, MP_STATE_PORT(mp_const_user_interrupt));
+}
+
+// Call this function to raise a pending exception during an interrupt.
+// It will try to raise the exception "softly" by setting the
+// mp_pending_exception variable hoping that the VM will notice it.
+void mpexception_nlr_jump (void *o) {
+ if (MP_STATE_PORT(mp_pending_exception) == MP_OBJ_NULL) {
+ MP_STATE_PORT(mp_pending_exception) = o;
+ }
+}
+
+void mpexception_keyboard_nlr_jump (void) {
+ mpexception_nlr_jump (user_interrupt_data);
+}
+
+/******************************************************************************
+DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
+
+STATIC void mpexception_set_user_interrupt (int chr, void *data) {
+ user_interrupt_char = chr;
+ user_interrupt_data = data;
+}
diff --git a/cc3200/misc/mpexception.h b/cc3200/misc/mpexception.h
new file mode 100644
index 0000000000..f55aa739e0
--- /dev/null
+++ b/cc3200/misc/mpexception.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef MPEXCEPTION_H_
+#define MPEXCEPTION_H_
+
+extern const char mpexception_os_resource_not_avaliable[];
+extern const char mpexception_os_operation_failed[];
+extern const char mpexception_os_request_not_possible[];
+extern const char mpexception_value_invalid_arguments[];
+extern const char mpexception_num_type_invalid_arguments[];
+extern const char mpexception_uncaught[];
+
+extern int user_interrupt_char;
+
+
+extern void mpexception_init0 (void);
+extern void mpexception_set_interrupt_char (int c);
+extern void mpexception_nlr_jump (void *o);
+extern void mpexception_keyboard_nlr_jump (void);
+
+#endif /* MPEXCEPTION_H_ */
diff --git a/cc3200/misc/pin_defs_cc3200.c b/cc3200/misc/pin_defs_cc3200.c
new file mode 100644
index 0000000000..a9fb793c51
--- /dev/null
+++ b/cc3200/misc/pin_defs_cc3200.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mpconfig.h"
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "inc/hw_types.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "gpio.h"
+#include "pin.h"
+#include "pybgpio.h"
+#include "runtime.h"
+#include MICROPY_HAL_H
+
+
+// Returns the pin mode. This value returned by this macro should be one of:
+// GPIO_DIR_MODE_IN or GPIO_DIR_MODE_OUT
+uint32_t gpio_get_mode(const gpio_obj_t *self) {
+ return MAP_GPIODirModeGet(self->port, self->bit);
+}
+
+uint32_t gpio_get_type(const gpio_obj_t *self) {
+
+ uint32_t strenght;
+ uint32_t type;
+
+ MAP_PinConfigGet(self->pin_num, &strenght, &type);
+
+ return type;
+}
+
+uint32_t gpio_get_strenght (const gpio_obj_t *self) {
+
+ uint32_t strenght;
+ uint32_t type;
+
+ MAP_PinConfigGet(self->pin_num, &strenght, &type);
+
+ return strenght;
+}
+
diff --git a/cc3200/misc/pin_defs_cc3200.h b/cc3200/misc/pin_defs_cc3200.h
new file mode 100644
index 0000000000..6ba1640d65
--- /dev/null
+++ b/cc3200/misc/pin_defs_cc3200.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// This file contains pin definitions that are specific to the cc3200 port.
+// This file should only ever be #included by pybgpio.h and not directly.
+
+
+//*****************************************************************************
+// Define types
+//*****************************************************************************
+
+enum {
+ PORT_A0 = GPIOA0_BASE,
+ PORT_A1 = GPIOA1_BASE,
+ PORT_A2 = GPIOA2_BASE,
+ PORT_A3 = GPIOA3_BASE
+};
diff --git a/cc3200/mods/modnetwork.c b/cc3200/mods/modnetwork.c
new file mode 100644
index 0000000000..2e100aecb4
--- /dev/null
+++ b/cc3200/mods/modnetwork.c
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "objlist.h"
+#include "runtime.h"
+#include "modnetwork.h"
+#include "mpexception.h"
+#include "mpstate.h"
+
+/// \module network - network configuration
+///
+/// This module provides network drivers and routing configuration.
+
+void mod_network_init(void) {
+ mp_obj_list_init(&MP_STATE_PORT(mod_network_nic_list), 0);
+}
+
+void mod_network_register_nic(mp_obj_t nic) {
+ for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) {
+ if (MP_STATE_PORT(mod_network_nic_list).items[i] == nic) {
+ // nic already registered
+ return;
+ }
+ }
+ // nic not registered so add to list
+ mp_obj_list_append(&MP_STATE_PORT(mod_network_nic_list), nic);
+}
+
+mp_obj_t mod_network_find_nic(const uint8_t *ip) {
+ // find a NIC that is suited to given IP address
+ for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) {
+ mp_obj_t nic = MP_STATE_PORT(mod_network_nic_list).items[i];
+ return nic;
+ }
+
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_resource_not_avaliable));
+}
+
+STATIC mp_obj_t network_route(void) {
+ return &MP_STATE_PORT(mod_network_nic_list);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(network_route_obj, network_route);
+
+STATIC const mp_map_elem_t mp_module_network_globals_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_network) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_WLAN), (mp_obj_t)&mod_network_nic_type_wlan },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_route), (mp_obj_t)&network_route_obj },
+};
+
+STATIC MP_DEFINE_CONST_DICT(mp_module_network_globals, mp_module_network_globals_table);
+
+const mp_obj_module_t mp_module_network = {
+ .base = { &mp_type_module },
+ .name = MP_QSTR_network,
+ .globals = (mp_obj_dict_t*)&mp_module_network_globals,
+};
+
+/******************************************************************************/
+// Miscellaneous helpers
+
+void mod_network_convert_ipv4_endianness(uint8_t *ip) {
+ uint8_t ip0 = ip[0]; ip[0] = ip[3]; ip[3] = ip0;
+ uint8_t ip1 = ip[1]; ip[1] = ip[2]; ip[2] = ip1;
+}
+
+// Takes an address of the form '192.168.0.1' and converts it to network format
+// in out_ip (big endian, so the 192 is the first byte).
+void mod_network_parse_ipv4_addr(mp_obj_t addr_in, uint8_t *out_ip) {
+ mp_uint_t addr_len;
+ const char *addr_str = mp_obj_str_get_data(addr_in, &addr_len);
+ if (addr_len == 0) {
+ // special case of no address given
+ memset(out_ip, 0, MOD_NETWORK_IPV4ADDR_BUF_SIZE);
+ return;
+ }
+ const char *s = addr_str;
+ const char *s_top = addr_str + addr_len;
+ for (mp_uint_t i = 0;; i++) {
+ mp_uint_t val = 0;
+ for (; s < s_top && *s != '.'; s++) {
+ val = val * 10 + *s - '0';
+ }
+ out_ip[i] = val;
+ if (i == 3 && s == s_top) {
+ return;
+ } else if (i < 3 && s < s_top && *s == '.') {
+ s++;
+ } else {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+ }
+ }
+}
+
+// Takes an address of the form ('192.168.0.1', 8080), returns the port and
+// puts IP in out_ip (which must take at least IPADDR_BUF_SIZE bytes).
+mp_uint_t mod_network_parse_inet_addr(mp_obj_t addr_in, uint8_t *out_ip) {
+ mp_obj_t *addr_items;
+ mp_obj_get_array_fixed_n(addr_in, 2, &addr_items);
+ mod_network_parse_ipv4_addr(addr_items[0], out_ip);
+ return mp_obj_get_int(addr_items[1]);
+}
+
+// Takes an array with a raw IPv4 address and returns something like '192.168.0.1'.
+mp_obj_t mod_network_format_ipv4_addr(uint8_t *ip) {
+ char ip_str[16];
+ mp_uint_t ip_len = snprintf(ip_str, 16, "%u.%u.%u.%u", ip[0], ip[1], ip[2], ip[3]);
+ return mp_obj_new_str(ip_str, ip_len, false);
+}
+
+// Takes an array with a raw IP address, and a port, and returns a net-address
+// tuple such as ('192.168.0.1', 8080).
+mp_obj_t mod_network_format_inet_addr(uint8_t *ip, mp_uint_t port) {
+ mp_obj_t tuple[2] = {
+ tuple[0] = mod_network_format_ipv4_addr(ip),
+ tuple[1] = mp_obj_new_int(port),
+ };
+ return mp_obj_new_tuple(2, tuple);
+}
diff --git a/cc3200/mods/modnetwork.h b/cc3200/mods/modnetwork.h
new file mode 100644
index 0000000000..838073395d
--- /dev/null
+++ b/cc3200/mods/modnetwork.h
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define MOD_NETWORK_IPV4ADDR_BUF_SIZE (4)
+
+// Forward declaration
+struct _mod_network_socket_obj_t;
+
+typedef struct _mod_network_nic_type_t {
+ mp_obj_type_t base;
+
+ // API for non-socket operations
+ int (*gethostbyname)(mp_obj_t nic, const char *name, mp_uint_t len, uint8_t *ip_out, uint8_t family);
+
+ // API for socket operations; return -1 on error
+ int (*socket)(struct _mod_network_socket_obj_t *s, int *_errno);
+ void (*close)(struct _mod_network_socket_obj_t *socket);
+ int (*bind)(struct _mod_network_socket_obj_t *s, byte *ip, mp_uint_t port, int *_errno);
+ int (*listen)(struct _mod_network_socket_obj_t *s, mp_int_t backlog, int *_errno);
+ int (*accept)(struct _mod_network_socket_obj_t *s, struct _mod_network_socket_obj_t *s2, byte *ip, mp_uint_t *port, int *_errno);
+ int (*connect)(struct _mod_network_socket_obj_t *s, byte *ip, mp_uint_t port, int *_errno);
+ int (*send)(struct _mod_network_socket_obj_t *s, const byte *buf, mp_uint_t len, int *_errno);
+ int (*recv)(struct _mod_network_socket_obj_t *s, byte *buf, mp_uint_t len, int *_errno);
+ int (*sendto)(struct _mod_network_socket_obj_t *s, const byte *buf, mp_uint_t len, byte *ip, mp_uint_t port, int *_errno);
+ int (*recvfrom)(struct _mod_network_socket_obj_t *s, byte *buf, mp_uint_t len, byte *ip, mp_uint_t *port, int *_errno);
+ int (*setsockopt)(struct _mod_network_socket_obj_t *s, mp_uint_t level, mp_uint_t opt, const void *optval, mp_uint_t optlen, int *_errno);
+ int (*settimeout)(struct _mod_network_socket_obj_t *s, mp_uint_t timeout_ms, int *_errno);
+ int (*ioctl)(struct _mod_network_socket_obj_t *s, mp_uint_t request, mp_uint_t arg, int *_errno);
+} mod_network_nic_type_t;
+
+typedef struct _mod_network_socket_obj_t {
+ mp_obj_base_t base;
+ mp_obj_t nic;
+ mod_network_nic_type_t *nic_type;
+ union {
+ struct {
+ uint8_t domain;
+ uint8_t type;
+ uint8_t proto;
+ int8_t fileno;
+ } u_param;
+ int16_t sd;
+ bool closed;
+ };
+} mod_network_socket_obj_t;
+
+extern const mod_network_nic_type_t mod_network_nic_type_wlan;
+
+void mod_network_init(void);
+void mod_network_register_nic(mp_obj_t nic);
+mp_obj_t mod_network_find_nic(const uint8_t *ip);
+
+void mod_network_convert_ipv4_endianness(uint8_t *ip);
+void mod_network_parse_ipv4_addr(mp_obj_t addr_in, uint8_t *out_ip);
+mp_uint_t mod_network_parse_inet_addr(mp_obj_t addr_in, uint8_t *out_ip);
+mp_obj_t mod_network_format_ipv4_addr(uint8_t *ip);
+mp_obj_t mod_network_format_inet_addr(uint8_t *ip, mp_uint_t port);
diff --git a/cc3200/mods/modpyb.c b/cc3200/mods/modpyb.c
new file mode 100644
index 0000000000..f17d6a257e
--- /dev/null
+++ b/cc3200/mods/modpyb.c
@@ -0,0 +1,318 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+
+#include
+#include
+
+#include "py/mpstate.h"
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "gc.h"
+#include "gccollect.h"
+#include "irq.h"
+#include "inc/hw_types.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_uart.h"
+#include "prcm.h"
+#include "pyexec.h"
+#include "pybuart.h"
+#include "pybgpio.h"
+#include "pybstdio.h"
+#include "pybrtc.h"
+#include "pybsystick.h"
+#include "simplelink.h"
+#include "modwlan.h"
+#include "telnet.h"
+#include "ff.h"
+#include "diskio.h"
+#include "sflash_diskio.h"
+#include "FreeRTOS.h"
+#include "portable.h"
+#include "task.h"
+#include "mpexception.h"
+#include "random.h"
+#include "pybextint.h"
+
+
+#ifdef DEBUG
+extern OsiTaskHandle mpTaskHandle;
+extern OsiTaskHandle svTaskHandle;
+extern TaskHandle_t xSimpleLinkSpawnTaskHndl;
+#endif
+
+/// \module pyb - functions related to the pyboard
+///
+/// The `pyb` module contains specific functions related to the pyboard.
+
+/// \function hard_reset()
+/// Resets the pyboard in a manner similar to pushing the external RESET
+/// button.
+STATIC mp_obj_t pyb_hard_reset(void) {
+ // disable wlan services
+ wlan_servers_stop();
+ wlan_sl_disable();
+ // perform a SoC reset
+ PRCMSOCReset();
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_hard_reset_obj, pyb_hard_reset);
+
+#ifdef DEBUG
+/// \function info([dump_alloc_table])
+/// Print out some run time info which is helpful duirng development.
+STATIC mp_obj_t pyb_info(uint n_args, const mp_obj_t *args) {
+ // FreeRTOS info
+ {
+ printf("---------------------------------------------\n");
+ printf("FreeRTOS\n");
+ printf("---------------------------------------------\n");
+ printf("Total heap: %u\n", configTOTAL_HEAP_SIZE);
+ printf("Free heap: %u\n", xPortGetFreeHeapSize());
+ printf("MpTask min free stack: %u\n", (unsigned int)uxTaskGetStackHighWaterMark((TaskHandle_t)mpTaskHandle));
+ printf("ServersTask min free stack: %u\n", (unsigned int)uxTaskGetStackHighWaterMark((TaskHandle_t)svTaskHandle));
+ printf("SlTask min free stack: %u\n", (unsigned int)uxTaskGetStackHighWaterMark(xSimpleLinkSpawnTaskHndl));
+ printf("IdleTask min free stack: %u\n", (unsigned int)uxTaskGetStackHighWaterMark(xTaskGetIdleTaskHandle()));
+
+ uint32_t *pstack = (uint32_t *)&_stack;
+ while (*pstack == 0x55555555) {
+ pstack++;
+ }
+ printf("MAIN min free stack: %u\n", pstack - ((uint32_t *)&_stack));
+ printf("---------------------------------------------\n");
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_info_obj, 0, 1, pyb_info);
+#endif
+
+/// \function unique_id()
+/// Returns a string of 6 bytes (48 bits), which is the unique MAC address of the SoC
+STATIC mp_obj_t pyb_mac(void) {
+ uint8_t mac[6];
+ wlan_get_mac (mac);
+ return mp_obj_new_bytes(mac, 6);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_mac_obj, pyb_mac);
+
+/// \function freq()
+/// Returns the CPU frequency: (F_CPU).
+STATIC mp_obj_t pyb_freq(void) {
+ return mp_obj_new_int(HAL_FCPU_HZ);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_freq_obj, pyb_freq);
+
+/// \function sync()
+/// Sync all file systems.
+STATIC mp_obj_t pyb_sync(void) {
+ sflash_disk_flush();
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_sync_obj, pyb_sync);
+
+/// \function millis()
+/// Returns the number of milliseconds since the board was last reset.
+///
+/// The result is always a micropython smallint (31-bit signed number), so
+/// after 2^30 milliseconds (about 12.4 days) this will start to return
+/// negative numbers.
+STATIC mp_obj_t pyb_millis(void) {
+ // We want to "cast" the 32 bit unsigned into a small-int. This means
+ // copying the MSB down 1 bit (extending the sign down), which is
+ // equivalent to just using the MP_OBJ_NEW_SMALL_INT macro.
+ return MP_OBJ_NEW_SMALL_INT(HAL_GetTick());
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_millis_obj, pyb_millis);
+
+/// \function elapsed_millis(start)
+/// Returns the number of milliseconds which have elapsed since `start`.
+///
+/// This function takes care of counter wrap, and always returns a positive
+/// number. This means it can be used to measure periods upto about 12.4 days.
+///
+/// Example:
+/// start = pyb.millis()
+/// while pyb.elapsed_millis(start) < 1000:
+/// # Perform some operation
+STATIC mp_obj_t pyb_elapsed_millis(mp_obj_t start) {
+ uint32_t startMillis = mp_obj_get_int(start);
+ uint32_t currMillis = HAL_GetTick();
+ return MP_OBJ_NEW_SMALL_INT((currMillis - startMillis) & 0x3fffffff);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_elapsed_millis_obj, pyb_elapsed_millis);
+
+/// \function micros()
+/// Returns the number of microseconds since the board was last reset.
+///
+/// The result is always a micropython smallint (31-bit signed number), so
+/// after 2^30 microseconds (about 17.8 minutes) this will start to return
+/// negative numbers.
+STATIC mp_obj_t pyb_micros(void) {
+ // We want to "cast" the 32 bit unsigned into a small-int. This means
+ // copying the MSB down 1 bit (extending the sign down), which is
+ // equivalent to just using the MP_OBJ_NEW_SMALL_INT macro.
+ return MP_OBJ_NEW_SMALL_INT(sys_tick_get_microseconds());
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(pyb_micros_obj, pyb_micros);
+
+/// \function elapsed_micros(start)
+/// Returns the number of microseconds which have elapsed since `start`.
+///
+/// This function takes care of counter wrap, and always returns a positive
+/// number. This means it can be used to measure periods upto about 17.8 minutes.
+///
+/// Example:
+/// start = pyb.micros()
+/// while pyb.elapsed_micros(start) < 1000:
+/// # Perform some operation
+STATIC mp_obj_t pyb_elapsed_micros(mp_obj_t start) {
+ uint32_t startMicros = mp_obj_get_int(start);
+ uint32_t currMicros = sys_tick_get_microseconds();
+ return MP_OBJ_NEW_SMALL_INT((currMicros - startMicros) & 0x3fffffff);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_elapsed_micros_obj, pyb_elapsed_micros);
+
+/// \function delay(ms)
+/// Delay for the given number of milliseconds.
+STATIC mp_obj_t pyb_delay(mp_obj_t ms_in) {
+ mp_int_t ms = mp_obj_get_int(ms_in);
+ if (ms > 0) {
+ HAL_Delay(ms);
+ }
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_delay_obj, pyb_delay);
+
+/// \function udelay(us)
+/// Delay for the given number of microseconds.
+STATIC mp_obj_t pyb_udelay(mp_obj_t usec_in) {
+ mp_int_t usec = mp_obj_get_int(usec_in);
+ if (usec > 0) {
+ uint32_t count = 0;
+ const uint32_t utime = ((HAL_FCPU_HZ / 1000000) * (usec / 4));
+ while (++count <= utime) {
+ }
+ }
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_udelay_obj, pyb_udelay);
+
+STATIC mp_obj_t pyb_stop(void) {
+ return mp_const_none;
+}
+
+MP_DEFINE_CONST_FUN_OBJ_0(pyb_stop_obj, pyb_stop);
+
+STATIC mp_obj_t pyb_standby(void) {
+ return mp_const_none;
+}
+
+MP_DEFINE_CONST_FUN_OBJ_0(pyb_standby_obj, pyb_standby);
+
+/// \function repl_uart(uart)
+/// Get or set the UART object that the REPL is repeated on.
+STATIC mp_obj_t pyb_repl_uart(uint n_args, const mp_obj_t *args) {
+ if (n_args == 0) {
+ if (MP_STATE_PORT(pyb_stdio_uart) == NULL) {
+ return mp_const_none;
+ } else {
+ return MP_STATE_PORT(pyb_stdio_uart);
+ }
+ } else {
+ if (args[0] == mp_const_none) {
+ MP_STATE_PORT(pyb_stdio_uart) = NULL;
+ } else if (mp_obj_get_type(args[0]) == &pyb_uart_type) {
+ MP_STATE_PORT(pyb_stdio_uart) = args[0];
+ } else {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_num_type_invalid_arguments));
+ }
+ return mp_const_none;
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_repl_uart_obj, 0, 1, pyb_repl_uart);
+
+MP_DECLARE_CONST_FUN_OBJ(pyb_main_obj); // defined in main.c
+
+STATIC const mp_map_elem_t pyb_module_globals_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_pyb) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_hard_reset), (mp_obj_t)&pyb_hard_reset_obj },
+#ifdef DEBUG
+ { MP_OBJ_NEW_QSTR(MP_QSTR_info), (mp_obj_t)&pyb_info_obj },
+#endif
+ { MP_OBJ_NEW_QSTR(MP_QSTR_mac), (mp_obj_t)&pyb_mac_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_freq), (mp_obj_t)&pyb_freq_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_repl_info), (mp_obj_t)&pyb_set_repl_info_obj },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_wfi), (mp_obj_t)&pyb_wfi_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_disable_irq), (mp_obj_t)&pyb_disable_irq_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_enable_irq), (mp_obj_t)&pyb_enable_irq_obj },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_stop), (mp_obj_t)&pyb_stop_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_standby), (mp_obj_t)&pyb_standby_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_main), (mp_obj_t)&pyb_main_obj },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_repl_uart), (mp_obj_t)&pyb_repl_uart_obj },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_millis), (mp_obj_t)&pyb_millis_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_elapsed_millis), (mp_obj_t)&pyb_elapsed_millis_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_micros), (mp_obj_t)&pyb_micros_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_elapsed_micros), (mp_obj_t)&pyb_elapsed_micros_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_delay), (mp_obj_t)&pyb_delay_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_udelay), (mp_obj_t)&pyb_udelay_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_sync), (mp_obj_t)&pyb_sync_obj },
+
+ //{ MP_OBJ_NEW_QSTR(MP_QSTR_Timer), (mp_obj_t)&pyb_timer_type },
+
+#if MICROPY_HW_ENABLE_RNG
+ { MP_OBJ_NEW_QSTR(MP_QSTR_rng), (mp_obj_t)&pyb_rng_get_obj },
+#endif
+
+#if MICROPY_HW_ENABLE_RTC
+ { MP_OBJ_NEW_QSTR(MP_QSTR_RTC), (mp_obj_t)&pyb_rtc_type },
+#endif
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_GPIO), (mp_obj_t)&gpio_type },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ExtInt), (mp_obj_t)&extint_type },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_UART), (mp_obj_t)&pyb_uart_type },
+};
+
+STATIC MP_DEFINE_CONST_DICT(pyb_module_globals, pyb_module_globals_table);
+
+const mp_obj_module_t pyb_module = {
+ .base = { &mp_type_module },
+ .name = MP_QSTR_pyb,
+ .globals = (mp_obj_dict_t*)&pyb_module_globals,
+};
diff --git a/cc3200/mods/moduos.c b/cc3200/mods/moduos.c
new file mode 100644
index 0000000000..9058a4817b
--- /dev/null
+++ b/cc3200/mods/moduos.c
@@ -0,0 +1,337 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include "std.h"
+
+#include "mpconfig.h"
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "objtuple.h"
+#include "ff.h"
+#include "diskio.h"
+#include "sflash_diskio.h"
+#include "file.h"
+#include "modutime.h"
+#include "random.h"
+#include "sd_diskio.h"
+
+/// \module os - basic "operating system" services
+///
+/// The `os` module contains functions for filesystem access and `urandom`.
+///
+/// The filesystem has `/` as the root directory, and the available physical
+/// drives are accessible from here. They are currently:
+///
+/// /SFLASH -- the serial flash filesystem
+/// /SD -- the SD card (if it exists)
+///
+/// On boot up, the current directory is `/SFLASH` if no SD card is inserted,
+/// otherwise it is `/SD`.
+
+STATIC bool sd_in_root(void) {
+#if MICROPY_HW_HAS_SDCARD
+ return sd_disk_ready();
+#else
+ return false;
+#endif
+}
+
+/// \function chdir(path)
+/// Change current directory.
+STATIC mp_obj_t os_chdir(mp_obj_t path_in) {
+ const char *path;
+ path = mp_obj_str_get_str(path_in);
+
+ FRESULT res = f_chdrive(path);
+
+ if (res == FR_OK) {
+ res = f_chdir(path);
+ }
+ // TODO: Warn if too many open files...
+ if (res != FR_OK) {
+ // TODO should be mp_type_FileNotFoundError
+ nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "No such file or directory: '%s'", path));
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_chdir_obj, os_chdir);
+
+/// \function getcwd()
+/// Get the current directory.
+STATIC mp_obj_t os_getcwd(void) {
+ char buf[MICROPY_ALLOC_PATH_MAX + 1];
+ FRESULT res = f_getcwd(buf, sizeof buf);
+
+ if (res != FR_OK) {
+ nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(fresult_to_errno_table[res])));
+ }
+
+ return mp_obj_new_str(buf, strlen(buf), false);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_getcwd_obj, os_getcwd);
+
+/// \function listdir([dir])
+/// With no argument, list the current directory. Otherwise list the given directory.
+STATIC mp_obj_t os_listdir(mp_uint_t n_args, const mp_obj_t *args) {
+ bool is_str_type = true;
+ const char *path;
+ if (n_args == 1) {
+ if (mp_obj_get_type(args[0]) == &mp_type_bytes) {
+ is_str_type = false;
+ }
+ path = mp_obj_str_get_str(args[0]);
+ } else {
+ path = "";
+ }
+
+ // "hack" to list root directory
+ if (path[0] == '/' && path[1] == '\0') {
+ mp_obj_t dir_list = mp_obj_new_list(0, NULL);
+ mp_obj_list_append(dir_list, MP_OBJ_NEW_QSTR(MP_QSTR_SFLASH));
+ if (sd_in_root()) {
+ mp_obj_list_append(dir_list, MP_OBJ_NEW_QSTR(MP_QSTR_SD));
+ }
+ return dir_list;
+ }
+
+ FRESULT res;
+ FILINFO fno;
+ DIR dir;
+
+ res = f_opendir(&dir, path); /* Open the directory */
+ if (res != FR_OK) {
+ // TODO should be mp_type_FileNotFoundError
+ nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "No such file or directory: '%s'", path));
+ }
+
+ mp_obj_t dir_list = mp_obj_new_list(0, NULL);
+
+ for (;;) {
+ res = f_readdir(&dir, &fno); /* Read a directory item */
+ if (res != FR_OK || fno.fname[0] == 0) break; /* Break on error or end of dir */
+ if (fno.fname[0] == '.' && fno.fname[1] == 0) continue; /* Ignore . entry */
+ if (fno.fname[0] == '.' && fno.fname[1] == '.' && fno.fname[2] == 0) continue; /* Ignore .. entry */
+
+ char *fn = fno.fname;
+
+ // make a string object for this entry
+ mp_obj_t entry_o;
+ if (is_str_type) {
+ entry_o = mp_obj_new_str(fn, strlen(fn), false);
+ } else {
+ entry_o = mp_obj_new_bytes((const byte*)fn, strlen(fn));
+ }
+
+ // add the entry to the list
+ mp_obj_list_append(dir_list, entry_o);
+ }
+
+ f_closedir(&dir);
+
+ return dir_list;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(os_listdir_obj, 0, 1, os_listdir);
+
+/// \function mkdir(path)
+/// Create a new directory.
+STATIC mp_obj_t os_mkdir(mp_obj_t path_o) {
+ const char *path = mp_obj_str_get_str(path_o);
+ FRESULT res = f_mkdir(path);
+ switch (res) {
+ case FR_OK:
+ return mp_const_none;
+ case FR_EXIST:
+ // TODO should be FileExistsError
+ nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "File exists: '%s'", path));
+ default:
+ nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error creating directory '%s'", path));
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_mkdir_obj, os_mkdir);
+
+/// \function remove(path)
+/// Remove a file.
+STATIC mp_obj_t os_remove(mp_obj_t path_o) {
+ const char *path = mp_obj_str_get_str(path_o);
+ // TODO check that path is actually a file before trying to unlink it
+ FRESULT res = f_unlink(path);
+ switch (res) {
+ case FR_OK:
+ return mp_const_none;
+ default:
+ nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error removing file '%s'", path));
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_remove_obj, os_remove);
+
+/// \function rmdir(path)
+/// Remove a directory.
+STATIC mp_obj_t os_rmdir(mp_obj_t path_o) {
+ const char *path = mp_obj_str_get_str(path_o);
+ // TODO check that path is actually a directory before trying to unlink it
+ FRESULT res = f_unlink(path);
+ switch (res) {
+ case FR_OK:
+ return mp_const_none;
+ default:
+ nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_OSError, "Error removing directory '%s'", path));
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_rmdir_obj, os_rmdir);
+
+// Checks for path equality, ignoring trailing slashes:
+// path_equal(/, /) -> true
+// path_equal(/flash//, /flash) -> true
+// second argument must be in canonical form (meaning no trailing slash, unless it's just /)
+STATIC bool path_equal(const char *path, const char *path_canonical) {
+ for (; *path_canonical != '\0' && *path == *path_canonical; ++path, ++path_canonical) {
+ }
+ if (*path_canonical != '\0') {
+ return false;
+ }
+ for (; *path == '/'; ++path) {
+ }
+ return *path == '\0';
+}
+
+/// \function stat(path)
+/// Get the status of a file or directory.
+STATIC mp_obj_t os_stat(mp_obj_t path_in) {
+ const char *path = mp_obj_str_get_str(path_in);
+ stoupper((char *)path);
+
+ FILINFO fno;
+ FRESULT res;
+ if (path_equal(path, "/") || path_equal(path, "/SFLASH") || path_equal(path, "/SD")) {
+ // stat built-in directory
+ if (path[1] == 'S' && !sd_in_root()) {
+ // no /SD directory
+ res = FR_NO_PATH;
+ goto error;
+ }
+ fno.fsize = 0;
+ fno.fdate = 0;
+ fno.ftime = 0;
+ fno.fattrib = AM_DIR;
+ } else {
+ res = f_stat(path, &fno);
+ if (res != FR_OK) {
+ goto error;
+ }
+ }
+
+ mp_obj_tuple_t *t = mp_obj_new_tuple(10, NULL);
+ mp_int_t mode = 0;
+ if (fno.fattrib & AM_DIR) {
+ mode |= 0x4000; // stat.S_IFDIR
+ } else {
+ mode |= 0x8000; // stat.S_IFREG
+ }
+ mp_int_t seconds = mod_time_seconds_since_2000(
+ 1980 + ((fno.fdate >> 9) & 0x7f),
+ (fno.fdate >> 5) & 0x0f,
+ fno.fdate & 0x1f,
+ (fno.ftime >> 11) & 0x1f,
+ (fno.ftime >> 5) & 0x3f,
+ 2 * (fno.ftime & 0x1f)
+ );
+ t->items[0] = mp_obj_new_int(mode); // st_mode
+ t->items[1] = MP_OBJ_NEW_SMALL_INT(0); // st_ino
+ t->items[2] = MP_OBJ_NEW_SMALL_INT(0); // st_dev
+ t->items[3] = MP_OBJ_NEW_SMALL_INT(0); // st_nlink
+ t->items[4] = MP_OBJ_NEW_SMALL_INT(0); // st_uid
+ t->items[5] = MP_OBJ_NEW_SMALL_INT(0); // st_gid
+ t->items[6] = mp_obj_new_int(fno.fsize); // st_size
+ t->items[7] = mp_obj_new_int(seconds); // st_atime
+ t->items[8] = t->items[7]; // st_mtime
+ t->items[9] = t->items[7]; // st_ctime
+
+ return t;
+
+error:
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(fresult_to_errno_table[res])));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_stat_obj, os_stat);
+
+/// \function sync()
+/// Sync all filesystems.
+STATIC mp_obj_t os_sync(void) {
+ sflash_disk_flush();
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_0(os_sync_obj, os_sync);
+
+#if MICROPY_HW_ENABLE_RNG
+/// \function urandom(n)
+/// Return a bytes object with n random bytes, generated by the hardware
+/// random number generator.
+STATIC mp_obj_t os_urandom(mp_obj_t num) {
+ mp_int_t n = mp_obj_get_int(num);
+ vstr_t vstr;
+ vstr_init_len(&vstr, n);
+ for (int i = 0; i < n; i++) {
+ vstr.buf[i] = rng_get();
+ }
+ return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(os_urandom_obj, os_urandom);
+#endif
+
+STATIC const mp_map_elem_t os_module_globals_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_uos) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_chdir), (mp_obj_t)&os_chdir_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_getcwd), (mp_obj_t)&os_getcwd_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_listdir), (mp_obj_t)&os_listdir_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_mkdir), (mp_obj_t)&os_mkdir_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_remove), (mp_obj_t)&os_remove_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_rmdir), (mp_obj_t)&os_rmdir_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_stat), (mp_obj_t)&os_stat_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_unlink), (mp_obj_t)&os_remove_obj }, // unlink aliases to remove
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_sync), (mp_obj_t)&os_sync_obj },
+
+ /// \constant sep - separation character used in paths
+ { MP_OBJ_NEW_QSTR(MP_QSTR_sep), MP_OBJ_NEW_QSTR(MP_QSTR__slash_) },
+
+#if MICROPY_HW_ENABLE_RNG
+ { MP_OBJ_NEW_QSTR(MP_QSTR_urandom), (mp_obj_t)&os_urandom_obj },
+#endif
+};
+
+STATIC MP_DEFINE_CONST_DICT(os_module_globals, os_module_globals_table);
+
+const mp_obj_module_t mp_module_uos = {
+ .base = { &mp_type_module },
+ .name = MP_QSTR_uos,
+ .globals = (mp_obj_dict_t*)&os_module_globals,
+};
diff --git a/cc3200/mods/modusocket.c b/cc3200/mods/modusocket.c
new file mode 100644
index 0000000000..7356942f21
--- /dev/null
+++ b/cc3200/mods/modusocket.c
@@ -0,0 +1,451 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "simplelink.h"
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "objtuple.h"
+#include "objlist.h"
+#include "runtime.h"
+#include "modnetwork.h"
+#include "mpexception.h"
+#include "mpstate.h"
+
+/******************************************************************************/
+// socket class
+
+STATIC const mp_obj_type_t socket_type;
+
+// constructor socket(family=AF_INET, type=SOCK_STREAM, proto=IPPROTO_TCP, fileno=None)
+STATIC mp_obj_t socket_make_new(mp_obj_t type_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+ mp_arg_check_num(n_args, n_kw, 0, 4, false);
+
+ // create socket object (not bound to any NIC yet)
+ mod_network_socket_obj_t *s = m_new_obj_with_finaliser(mod_network_socket_obj_t);
+ s->base.type = (mp_obj_t)&socket_type;
+ s->nic = MP_OBJ_NULL;
+ s->nic_type = NULL;
+ s->u_param.domain = AF_INET;
+ s->u_param.type = SOCK_STREAM;
+ s->u_param.proto = IPPROTO_TCP;
+ s->u_param.fileno = -1;
+ if (n_args >= 1) {
+ s->u_param.domain = mp_obj_get_int(args[0]);
+ if (n_args >= 2) {
+ s->u_param.type = mp_obj_get_int(args[1]);
+ if (n_args >= 3) {
+ s->u_param.proto = mp_obj_get_int(args[2]);
+ if (n_args == 4) {
+ s->u_param.fileno = mp_obj_get_int(args[3]);
+ }
+ }
+ }
+ }
+ return s;
+}
+
+STATIC void socket_select_nic(mod_network_socket_obj_t *self, const byte *ip) {
+ if (self->nic == MP_OBJ_NULL) {
+ // select NIC based on IP
+ self->nic = mod_network_find_nic(ip);
+ self->nic_type = (mod_network_nic_type_t*)mp_obj_get_type(self->nic);
+
+ // call the NIC to open the socket
+ int _errno;
+ if (self->nic_type->socket(self, &_errno) != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+ }
+}
+// method socket.close()
+STATIC mp_obj_t socket_close(mp_obj_t self_in) {
+ mod_network_socket_obj_t *self = self_in;
+ if (self->nic != MP_OBJ_NULL) {
+ self->nic_type->close(self);
+ }
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(socket_close_obj, socket_close);
+
+// method socket.bind(address)
+STATIC mp_obj_t socket_bind(mp_obj_t self_in, mp_obj_t addr_in) {
+ mod_network_socket_obj_t *self = self_in;
+
+ // get address
+ uint8_t ip[MOD_NETWORK_IPV4ADDR_BUF_SIZE];
+ mp_uint_t port = mod_network_parse_inet_addr(addr_in, ip);
+
+ // check if we need to select a NIC
+ socket_select_nic(self, ip);
+
+ // call the NIC to bind the socket
+ int _errno;
+ if (self->nic_type->bind(self, ip, port, &_errno) != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_bind_obj, socket_bind);
+
+// method socket.listen(backlog)
+STATIC mp_obj_t socket_listen(mp_obj_t self_in, mp_obj_t backlog) {
+ mod_network_socket_obj_t *self = self_in;
+
+ if (self->nic == MP_OBJ_NULL) {
+ // not connected
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(ENOTCONN)));
+ }
+
+ int _errno;
+ if (self->nic_type->listen(self, mp_obj_get_int(backlog), &_errno) != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_listen_obj, socket_listen);
+
+// method socket.accept()
+STATIC mp_obj_t socket_accept(mp_obj_t self_in) {
+ mod_network_socket_obj_t *self = self_in;
+
+ // create new socket object
+ // starts with empty NIC so that finaliser doesn't run close() method if accept() fails
+ mod_network_socket_obj_t *socket2 = m_new_obj_with_finaliser(mod_network_socket_obj_t);
+ socket2->base.type = (mp_obj_t)&socket_type;
+ socket2->nic = MP_OBJ_NULL;
+ socket2->nic_type = NULL;
+
+ // accept incoming connection
+ uint8_t ip[MOD_NETWORK_IPV4ADDR_BUF_SIZE];
+ mp_uint_t port;
+ int _errno;
+ if (self->nic_type->accept(self, socket2, ip, &port, &_errno) != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+
+ // new socket has valid state, so set the NIC to the same as parent
+ socket2->nic = self->nic;
+ socket2->nic_type = self->nic_type;
+
+ // make the return value
+ mp_obj_tuple_t *client = mp_obj_new_tuple(2, NULL);
+ client->items[0] = socket2;
+ client->items[1] = mod_network_format_inet_addr(ip, port);
+
+ return client;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(socket_accept_obj, socket_accept);
+
+// method socket.connect(address)
+STATIC mp_obj_t socket_connect(mp_obj_t self_in, mp_obj_t addr_in) {
+ mod_network_socket_obj_t *self = self_in;
+
+ // get address
+ uint8_t ip[MOD_NETWORK_IPV4ADDR_BUF_SIZE];
+ mp_uint_t port = mod_network_parse_inet_addr(addr_in, ip);
+
+ // check if we need to select a NIC
+ socket_select_nic(self, ip);
+
+ // call the NIC to connect the socket
+ int _errno;
+ if (self->nic_type->connect(self, ip, port, &_errno) != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_connect_obj, socket_connect);
+
+// method socket.send(bytes)
+STATIC mp_obj_t socket_send(mp_obj_t self_in, mp_obj_t buf_in) {
+ mod_network_socket_obj_t *self = self_in;
+ if (self->nic == MP_OBJ_NULL) {
+ // not connected
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(EBADF)));
+ }
+ mp_buffer_info_t bufinfo;
+ mp_get_buffer_raise(buf_in, &bufinfo, MP_BUFFER_READ);
+ int _errno;
+ mp_uint_t ret = self->nic_type->send(self, bufinfo.buf, bufinfo.len, &_errno);
+ if (ret == -1) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+ return mp_obj_new_int_from_uint(ret);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_send_obj, socket_send);
+
+// method socket.recv(bufsize)
+STATIC mp_obj_t socket_recv(mp_obj_t self_in, mp_obj_t len_in) {
+ mod_network_socket_obj_t *self = self_in;
+ if (self->nic == MP_OBJ_NULL) {
+ // not connected
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(ENOTCONN)));
+ }
+ mp_int_t len = mp_obj_get_int(len_in);
+ vstr_t vstr;
+ vstr_init_len(&vstr, len);
+ int _errno;
+ mp_uint_t ret = self->nic_type->recv(self, (byte*)vstr.buf, len, &_errno);
+ if (ret == -1) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+ if (ret == 0) {
+ return mp_const_empty_bytes;
+ }
+ vstr.len = ret;
+ vstr.buf[vstr.len] = '\0';
+ return mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recv_obj, socket_recv);
+
+// method socket.sendto(bytes, address)
+STATIC mp_obj_t socket_sendto(mp_obj_t self_in, mp_obj_t data_in, mp_obj_t addr_in) {
+ mod_network_socket_obj_t *self = self_in;
+
+ // get the data
+ mp_buffer_info_t bufinfo;
+ mp_get_buffer_raise(data_in, &bufinfo, MP_BUFFER_READ);
+
+ // get address
+ uint8_t ip[MOD_NETWORK_IPV4ADDR_BUF_SIZE];
+ mp_uint_t port = mod_network_parse_inet_addr(addr_in, ip);
+
+ // check if we need to select a NIC
+ socket_select_nic(self, ip);
+
+ // call the NIC to sendto
+ int _errno;
+ mp_int_t ret = self->nic_type->sendto(self, bufinfo.buf, bufinfo.len, ip, port, &_errno);
+ if (ret == -1) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+
+ return mp_obj_new_int(ret);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_3(socket_sendto_obj, socket_sendto);
+
+// method socket.recvfrom(bufsize)
+STATIC mp_obj_t socket_recvfrom(mp_obj_t self_in, mp_obj_t len_in) {
+ mod_network_socket_obj_t *self = self_in;
+ if (self->nic == MP_OBJ_NULL) {
+ // not connected
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(ENOTCONN)));
+ }
+ vstr_t vstr;
+ vstr_init_len(&vstr, mp_obj_get_int(len_in));
+ byte ip[4];
+ mp_uint_t port;
+ int _errno;
+ mp_int_t ret = self->nic_type->recvfrom(self, (byte*)vstr.buf, vstr.len, ip, &port, &_errno);
+ if (ret == -1) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+ mp_obj_t tuple[2];
+ if (ret == 0) {
+ tuple[0] = mp_const_empty_bytes;
+ } else {
+ vstr.len = ret;
+ vstr.buf[vstr.len] = '\0';
+ tuple[0] = mp_obj_new_str_from_vstr(&mp_type_bytes, &vstr);
+ }
+ tuple[1] = mod_network_format_inet_addr(ip, port);
+ return mp_obj_new_tuple(2, tuple);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_recvfrom_obj, socket_recvfrom);
+
+// method socket.setsockopt(level, optname, value)
+STATIC mp_obj_t socket_setsockopt(mp_uint_t n_args, const mp_obj_t *args) {
+ mod_network_socket_obj_t *self = args[0];
+
+ mp_int_t level = mp_obj_get_int(args[1]);
+ mp_int_t opt = mp_obj_get_int(args[2]);
+
+ const void *optval;
+ mp_uint_t optlen;
+ mp_int_t val;
+ if (mp_obj_is_integer(args[3])) {
+ val = mp_obj_int_get_truncated(args[3]);
+ optval = &val;
+ optlen = sizeof(val);
+ } else {
+ mp_buffer_info_t bufinfo;
+ mp_get_buffer_raise(args[3], &bufinfo, MP_BUFFER_READ);
+ optval = bufinfo.buf;
+ optlen = bufinfo.len;
+ }
+
+ int _errno;
+ if (self->nic_type->setsockopt(self, level, opt, optval, optlen, &_errno) != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(socket_setsockopt_obj, 4, 4, socket_setsockopt);
+
+// method socket.settimeout(value)
+// timeout=0 means non-blocking
+// timeout=None means blocking
+// otherwise, timeout is in seconds
+STATIC mp_obj_t socket_settimeout(mp_obj_t self_in, mp_obj_t timeout_in) {
+ mod_network_socket_obj_t *self = self_in;
+ if (self->nic == MP_OBJ_NULL) {
+ // not connected
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(ENOTCONN)));
+ }
+ mp_uint_t timeout;
+ if (timeout_in == mp_const_none) {
+ timeout = -1;
+ } else {
+ timeout = 1000 * mp_obj_get_int(timeout_in);
+ }
+ int _errno;
+ if (self->nic_type->settimeout(self, timeout, &_errno) != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(_errno)));
+ }
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_settimeout_obj, socket_settimeout);
+
+// method socket.setblocking(flag)
+STATIC mp_obj_t socket_setblocking(mp_obj_t self_in, mp_obj_t blocking) {
+ if (mp_obj_is_true(blocking)) {
+ return socket_settimeout(self_in, mp_const_none);
+ } else {
+ return socket_settimeout(self_in, MP_OBJ_NEW_SMALL_INT(0));
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(socket_setblocking_obj, socket_setblocking);
+
+STATIC const mp_map_elem_t socket_locals_dict_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)&socket_close_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_close), (mp_obj_t)&socket_close_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_bind), (mp_obj_t)&socket_bind_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_listen), (mp_obj_t)&socket_listen_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_accept), (mp_obj_t)&socket_accept_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)&socket_connect_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_send), (mp_obj_t)&socket_send_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_recv), (mp_obj_t)&socket_recv_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_sendto), (mp_obj_t)&socket_sendto_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_recvfrom), (mp_obj_t)&socket_recvfrom_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_setsockopt), (mp_obj_t)&socket_setsockopt_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_settimeout), (mp_obj_t)&socket_settimeout_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_setblocking), (mp_obj_t)&socket_setblocking_obj },
+};
+
+STATIC MP_DEFINE_CONST_DICT(socket_locals_dict, socket_locals_dict_table);
+
+mp_uint_t socket_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) {
+ mod_network_socket_obj_t *self = self_in;
+ return self->nic_type->ioctl(self, request, arg, errcode);
+}
+
+STATIC const mp_stream_p_t socket_stream_p = {
+ .ioctl = socket_ioctl,
+ .is_text = false,
+};
+
+STATIC const mp_obj_type_t socket_type = {
+ { &mp_type_type },
+ .name = MP_QSTR_socket,
+ .make_new = socket_make_new,
+ .stream_p = &socket_stream_p,
+ .locals_dict = (mp_obj_t)&socket_locals_dict,
+};
+
+/******************************************************************************/
+// usocket module
+
+// function usocket.getaddrinfo(host, port)
+/// \function getaddrinfo(host, port)
+STATIC mp_obj_t mod_usocket_getaddrinfo(mp_obj_t host_in, mp_obj_t port_in) {
+ mp_uint_t hlen;
+ const char *host = mp_obj_str_get_data(host_in, &hlen);
+ mp_int_t port = mp_obj_get_int(port_in);
+
+ // find a NIC that can do a name lookup
+ for (mp_uint_t i = 0; i < MP_STATE_PORT(mod_network_nic_list).len; i++) {
+ mp_obj_t nic = MP_STATE_PORT(mod_network_nic_list).items[i];
+ mod_network_nic_type_t *nic_type = (mod_network_nic_type_t*)mp_obj_get_type(nic);
+ if (nic_type->gethostbyname != NULL) {
+ // Only IPv4 is supported
+ uint8_t out_ip[MOD_NETWORK_IPV4ADDR_BUF_SIZE];
+ int32_t result = nic_type->gethostbyname(nic, host, hlen, out_ip, AF_INET);
+ if (result != 0) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(result)));
+ }
+ mp_obj_tuple_t *tuple = mp_obj_new_tuple(5, NULL);
+ tuple->items[0] = MP_OBJ_NEW_SMALL_INT(AF_INET);
+ tuple->items[1] = MP_OBJ_NEW_SMALL_INT(SOCK_STREAM);
+ tuple->items[2] = MP_OBJ_NEW_SMALL_INT(0);
+ tuple->items[3] = MP_OBJ_NEW_QSTR(MP_QSTR_);
+ tuple->items[4] = mod_network_format_inet_addr(out_ip, port);
+ return mp_obj_new_list(1, (mp_obj_t*)&tuple);
+ }
+ }
+
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_resource_not_avaliable));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(mod_usocket_getaddrinfo_obj, mod_usocket_getaddrinfo);
+
+STATIC const mp_map_elem_t mp_module_usocket_globals_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_usocket) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_socket), (mp_obj_t)&socket_type },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_getaddrinfo), (mp_obj_t)&mod_usocket_getaddrinfo_obj },
+
+ // class constants
+ { MP_OBJ_NEW_QSTR(MP_QSTR_AF_INET), MP_OBJ_NEW_SMALL_INT(AF_INET) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_AF_INET6), MP_OBJ_NEW_SMALL_INT(AF_INET6) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_STREAM), MP_OBJ_NEW_SMALL_INT(SOCK_STREAM) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_DGRAM), MP_OBJ_NEW_SMALL_INT(SOCK_DGRAM) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_SOCK_RAW), MP_OBJ_NEW_SMALL_INT(SOCK_RAW) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_TCP), MP_OBJ_NEW_SMALL_INT(IPPROTO_TCP) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_UDP), MP_OBJ_NEW_SMALL_INT(IPPROTO_UDP) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IPPROTO_RAW), MP_OBJ_NEW_SMALL_INT(IPPROTO_RAW) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(mp_module_usocket_globals, mp_module_usocket_globals_table);
+
+const mp_obj_module_t mp_module_usocket = {
+ .base = { &mp_type_module },
+ .name = MP_QSTR_usocket,
+ .globals = (mp_obj_dict_t*)&mp_module_usocket_globals,
+};
diff --git a/cc3200/mods/modutime.c b/cc3200/mods/modutime.c
new file mode 100644
index 0000000000..9dae880e6e
--- /dev/null
+++ b/cc3200/mods/modutime.c
@@ -0,0 +1,333 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "modutime.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "pybrtc.h"
+#include "mpexception.h"
+
+
+// LEAPOCH corresponds to 2000-03-01, which is a mod-400 year, immediately
+// after Feb 29. We calculate seconds as a signed integer relative to that.
+//
+// Our timebase is relative to 2000-01-01.
+
+#define LEAPOCH ((31 + 29) * 86400)
+
+#define DAYS_PER_400Y (365*400 + 97)
+#define DAYS_PER_100Y (365*100 + 24)
+#define DAYS_PER_4Y (365*4 + 1)
+
+
+/// \module time - time related functions
+///
+/// The `time` module provides functions for getting the current time and date,
+/// and for sleeping.
+
+STATIC const uint16_t days_since_jan1[]= { 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365 };
+
+STATIC bool is_leap_year(mp_uint_t year) {
+ return (year % 4 == 0 && year % 100 != 0) || year % 400 == 0;
+}
+
+// Month is one based
+STATIC mp_uint_t mod_time_days_in_month(mp_uint_t year, mp_uint_t month) {
+ mp_uint_t mdays = days_since_jan1[month] - days_since_jan1[month - 1];
+ if (month == 2 && is_leap_year(year)) {
+ mdays++;
+ }
+ return mdays;
+}
+
+// compute the day of the year, between 1 and 366
+// month should be between 1 and 12, date should start at 1
+STATIC mp_uint_t mod_time_year_day(mp_uint_t year, mp_uint_t month, mp_uint_t date) {
+ mp_uint_t yday = days_since_jan1[month - 1] + date;
+ if (month >= 3 && is_leap_year(year)) {
+ yday += 1;
+ }
+ return yday;
+}
+
+// returns the number of seconds, as an integer, since 2000-01-01
+mp_uint_t mod_time_seconds_since_2000(mp_uint_t year, mp_uint_t month, mp_uint_t date, mp_uint_t hour, mp_uint_t minute, mp_uint_t second) {
+ return
+ second
+ + minute * 60
+ + hour * 3600
+ + (mod_time_year_day(year, month, date) - 1
+ + ((year - 2000 + 3) / 4) // add a day each 4 years starting with 2001
+ - ((year - 2000 + 99) / 100) // subtract a day each 100 years starting with 2001
+ + ((year - 2000 + 399) / 400) // add a day each 400 years starting with 2001
+ ) * 86400
+ + (year - 2000) * 31536000;
+}
+
+void mod_time_seconds_since_2000_to_struct_time(mp_uint_t t, mod_struct_time *tm) {
+ // The following algorithm was adapted from musl's __secs_to_tm and adapted
+ // for differences in Micro Python's timebase.
+
+ mp_int_t seconds = t - LEAPOCH;
+
+ mp_int_t days = seconds / 86400;
+ seconds %= 86400;
+ tm->tm_hour = seconds / 3600;
+ tm->tm_min = seconds / 60 % 60;
+ tm->tm_sec = seconds % 60;
+
+ mp_int_t wday = (days + 2) % 7; // Mar 1, 2000 was a Wednesday (2)
+ if (wday < 0) {
+ wday += 7;
+ }
+ tm->tm_wday = wday;
+
+ mp_int_t qc_cycles = days / DAYS_PER_400Y;
+ days %= DAYS_PER_400Y;
+ if (days < 0) {
+ days += DAYS_PER_400Y;
+ qc_cycles--;
+ }
+ mp_int_t c_cycles = days / DAYS_PER_100Y;
+ if (c_cycles == 4) {
+ c_cycles--;
+ }
+ days -= (c_cycles * DAYS_PER_100Y);
+
+ mp_int_t q_cycles = days / DAYS_PER_4Y;
+ if (q_cycles == 25) {
+ q_cycles--;
+ }
+ days -= q_cycles * DAYS_PER_4Y;
+
+ mp_int_t years = days / 365;
+ if (years == 4) {
+ years--;
+ }
+ days -= (years * 365);
+
+ tm->tm_year = 2000 + years + 4 * q_cycles + 100 * c_cycles + 400 * qc_cycles;
+
+ // Note: days_in_month[0] corresponds to March
+ STATIC const int8_t days_in_month[] = {31, 30, 31, 30, 31, 31, 30, 31, 30, 31, 31, 29};
+
+ mp_int_t month;
+ for (month = 0; days_in_month[month] <= days; month++) {
+ days -= days_in_month[month];
+ }
+
+ tm->tm_mon = month + 2;
+ if (tm->tm_mon >= 12) {
+ tm->tm_mon -= 12;
+ tm->tm_year++;
+ }
+ tm->tm_mday = days + 1; // Make one based
+ tm->tm_mon++; // Make one based
+
+ tm->tm_yday = mod_time_year_day(tm->tm_year, tm->tm_mon, tm->tm_mday);
+}
+
+/// \function localtime([secs])
+/// Convert a time expressed in seconds since Jan 1, 2000 into an 8-tuple which
+/// contains: (year, month, mday, hour, minute, second, weekday, yearday)
+/// If secs is not provided or None, then the current time from the RTC is used.
+/// year includes the century (for example 2014)
+/// month is 1-12
+/// mday is 1-31
+/// hour is 0-23
+/// minute is 0-59
+/// second is 0-59
+/// weekday is 0-6 for Mon-Sun.
+/// yearday is 1-366
+STATIC mp_obj_t time_localtime(mp_uint_t n_args, const mp_obj_t *args) {
+ if (n_args == 0 || args[0] == mp_const_none) {
+ mod_struct_time tm;
+ uint32_t seconds;
+ uint16_t mseconds;
+
+ // get the seconds and the milliseconds from the RTC
+ MAP_PRCMRTCGet(&seconds, &mseconds);
+ mseconds = RTC_CYCLES_U16MS(mseconds);
+ mod_time_seconds_since_2000_to_struct_time(seconds, &tm);
+
+ mp_obj_t tuple[8] = {
+ mp_obj_new_int(tm.tm_year),
+ mp_obj_new_int(tm.tm_mon),
+ mp_obj_new_int(tm.tm_mday),
+ mp_obj_new_int(tm.tm_wday),
+ mp_obj_new_int(tm.tm_hour),
+ mp_obj_new_int(tm.tm_min),
+ mp_obj_new_int(tm.tm_sec),
+ mp_obj_new_int(mseconds)
+ };
+ return mp_obj_new_tuple(8, tuple);
+ } else {
+ mp_int_t seconds = mp_obj_get_int(args[0]);
+ mod_struct_time tm;
+ mod_time_seconds_since_2000_to_struct_time(seconds, &tm);
+ mp_obj_t tuple[8] = {
+ tuple[0] = mp_obj_new_int(tm.tm_year),
+ tuple[1] = mp_obj_new_int(tm.tm_mon),
+ tuple[2] = mp_obj_new_int(tm.tm_mday),
+ tuple[3] = mp_obj_new_int(tm.tm_hour),
+ tuple[4] = mp_obj_new_int(tm.tm_min),
+ tuple[5] = mp_obj_new_int(tm.tm_sec),
+ tuple[6] = mp_obj_new_int(tm.tm_wday),
+ tuple[7] = mp_obj_new_int(tm.tm_yday),
+ };
+ return mp_obj_new_tuple(8, tuple);
+ }
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(time_localtime_obj, 0, 1, time_localtime);
+
+
+/// \function mktime()
+/// This is inverse function of localtime. It's argument is a full 8-tuple
+/// which expresses a time as per localtime. It returns an integer which is
+/// the number of seconds since Jan 1, 2000.
+STATIC mp_obj_t time_mktime(mp_obj_t tuple) {
+
+ mp_uint_t len;
+ mp_obj_t *elem;
+
+ mp_obj_get_array(tuple, &len, &elem);
+
+ // localtime generates a tuple of len 8. CPython uses 9, so we accept both.
+ if (len < 8 || len > 9) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_TypeError, mpexception_num_type_invalid_arguments));
+ }
+
+ mp_int_t year = mp_obj_get_int(elem[0]);
+ mp_int_t month = mp_obj_get_int(elem[1]);
+ mp_int_t mday = mp_obj_get_int(elem[2]);
+ mp_int_t hours = mp_obj_get_int(elem[3]);
+ mp_int_t minutes = mp_obj_get_int(elem[4]);
+ mp_int_t seconds = mp_obj_get_int(elem[5]);
+
+ // Normalize the tuple. This allows things like:
+ //
+ // tm_tomorrow = list(time.localtime())
+ // tm_tomorrow[2] += 1 # Adds 1 to mday
+ // tomorrow = time.mktime(tm_tommorrow)
+ //
+ // And not have to worry about all the weird overflows.
+ //
+ // You can subtract dates/times this way as well.
+
+ minutes += seconds / 60;
+ if ((seconds = seconds % 60) < 0) {
+ seconds += 60;
+ minutes--;
+ }
+
+ hours += minutes / 60;
+ if ((minutes = minutes % 60) < 0) {
+ minutes += 60;
+ hours--;
+ }
+
+ mday += hours / 24;
+ if ((hours = hours % 24) < 0) {
+ hours += 24;
+ mday--;
+ }
+
+ month--; // make month zero based
+ year += month / 12;
+ if ((month = month % 12) < 0) {
+ month += 12;
+ year--;
+ }
+ month++; // back to one based
+
+ while (mday < 1) {
+ if (--month == 0) {
+ month = 12;
+ year--;
+ }
+ mday += mod_time_days_in_month(year, month);
+ }
+ while (mday > mod_time_days_in_month(year, month)) {
+ mday -= mod_time_days_in_month(year, month);
+ if (++month == 13) {
+ month = 1;
+ year++;
+ }
+ }
+ return mp_obj_new_int_from_uint(mod_time_seconds_since_2000(year, month, mday, hours, minutes, seconds));
+}
+MP_DEFINE_CONST_FUN_OBJ_1(time_mktime_obj, time_mktime);
+
+
+/// \function sleep(milliseconds)
+/// Sleep for the given number of milliseconds.
+STATIC mp_obj_t time_sleep(mp_obj_t milliseconds_o) {
+ HAL_Delay(mp_obj_get_int(milliseconds_o));
+ return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_1(time_sleep_obj, time_sleep);
+
+/// \function time()
+/// Returns the number of seconds, as an integer, since 1/1/2000.
+STATIC mp_obj_t time_time(void) {
+ uint32_t seconds;
+ uint16_t mseconds;
+
+ // get the seconds and the milliseconds from the RTC
+ MAP_PRCMRTCGet(&seconds, &mseconds);
+ return mp_obj_new_int(seconds);
+}
+MP_DEFINE_CONST_FUN_OBJ_0(time_time_obj, time_time);
+
+STATIC const mp_map_elem_t time_module_globals_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_utime) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_localtime), (mp_obj_t)&time_localtime_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_mktime), (mp_obj_t)&time_mktime_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_sleep), (mp_obj_t)&time_sleep_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&time_time_obj },
+};
+
+STATIC MP_DEFINE_CONST_DICT(time_module_globals, time_module_globals_table);
+
+const mp_obj_module_t mp_module_utime = {
+ .base = { &mp_type_module },
+ .name = MP_QSTR_utime,
+ .globals = (mp_obj_dict_t*)&time_module_globals,
+};
diff --git a/cc3200/mods/modutime.h b/cc3200/mods/modutime.h
new file mode 100644
index 0000000000..5f1e8ed746
--- /dev/null
+++ b/cc3200/mods/modutime.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef struct {
+ uint16_t tm_year; // i.e. 2014
+ uint8_t tm_mon; // 1..12
+ uint8_t tm_mday; // 1..31
+ uint8_t tm_hour; // 0..23
+ uint8_t tm_min; // 0..59
+ uint8_t tm_sec; // 0..59
+ uint8_t tm_wday; // 0..6 0 = Monday
+ uint16_t tm_yday; // 1..366
+} mod_struct_time;
+
+
+extern mp_uint_t mod_time_seconds_since_2000(mp_uint_t year, mp_uint_t month, mp_uint_t date,
+ mp_uint_t hour, mp_uint_t minute, mp_uint_t second);
+
+extern void mod_time_seconds_since_2000_to_struct_time(mp_uint_t t, mod_struct_time *tm);
diff --git a/cc3200/mods/modwlan.c b/cc3200/mods/modwlan.c
new file mode 100644
index 0000000000..22b8cae9cf
--- /dev/null
+++ b/cc3200/mods/modwlan.c
@@ -0,0 +1,1199 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "std.h"
+#include
+#include
+
+#include "simplelink.h"
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "objtuple.h"
+#include "objlist.h"
+#include "runtime.h"
+#include "modnetwork.h"
+#include "modwlan.h"
+#include "pybioctl.h"
+#include "pybuart.h"
+#include "pybstdio.h"
+#include "osi.h"
+#include "debug.h"
+#include "serverstask.h"
+#include "mpexception.h"
+
+#ifdef USE_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+
+
+/******************************************************************************
+ DEFINE TYPES
+ ******************************************************************************/
+// Status bits - These are used to set/reset the corresponding bits in a given variable
+typedef enum{
+ STATUS_BIT_NWP_INIT = 0, // If this bit is set: Network Processor is
+ // powered up
+
+ STATUS_BIT_CONNECTION, // If this bit is set: the device is connected to
+ // the AP or client is connected to device (AP)
+
+ STATUS_BIT_IP_LEASED, // If this bit is set: the device has leased IP to
+ // any connected client
+
+ STATUS_BIT_IP_ACQUIRED, // If this bit is set: the device has acquired an IP
+
+ STATUS_BIT_SMARTCONFIG_START, // If this bit is set: the SmartConfiguration
+ // process is started from SmartConfig app
+
+ STATUS_BIT_P2P_DEV_FOUND, // If this bit is set: the device (P2P mode)
+ // found any p2p-device in scan
+
+ STATUS_BIT_P2P_REQ_RECEIVED, // If this bit is set: the device (P2P mode)
+ // found any p2p-negotiation request
+
+ STATUS_BIT_CONNECTION_FAILED, // If this bit is set: the device(P2P mode)
+ // connection to client(or reverse way) is failed
+
+ STATUS_BIT_PING_DONE // If this bit is set: the device has completed
+ // the ping operation
+}e_StatusBits;
+
+typedef struct _wlan_obj_t {
+ mp_obj_base_t base;
+ SlWlanMode_t mode;
+ uint32_t status;
+ uint8_t macAddr[SL_MAC_ADDR_LEN];
+ uint8_t ssid_name[33];
+ uint8_t bssid[6];
+ bool servers_enabled;
+
+ // IPVv4 data
+ uint32_t ip;
+ uint32_t gateway;
+ uint32_t dns;
+
+} wlan_obj_t;
+
+/******************************************************************************
+ DEFINE CONSTANTS
+ ******************************************************************************/
+#define CLR_STATUS_BIT_ALL(status) (status = 0)
+#define SET_STATUS_BIT(status, bit) (status |= ( 1 << (bit)))
+#define CLR_STATUS_BIT(status, bit) (status &= ~(1 << (bit)))
+#define GET_STATUS_BIT(status, bit) (0 != (status & (1 << (bit))))
+
+#define IS_NW_PROCSR_ON(status) GET_STATUS_BIT(status, STATUS_BIT_NWP_INIT)
+#define IS_CONNECTED(status) GET_STATUS_BIT(status, STATUS_BIT_CONNECTION)
+#define IS_IP_LEASED(status) GET_STATUS_BIT(status, STATUS_BIT_IP_LEASED)
+#define IS_IP_ACQUIRED(status) GET_STATUS_BIT(status, STATUS_BIT_IP_ACQUIRED)
+#define IS_SMART_CFG_START(status) GET_STATUS_BIT(status, STATUS_BIT_SMARTCONFIG_START)
+#define IS_P2P_DEV_FOUND(status) GET_STATUS_BIT(status, STATUS_BIT_P2P_DEV_FOUND)
+#define IS_P2P_REQ_RCVD(status) GET_STATUS_BIT(status, STATUS_BIT_P2P_REQ_RECEIVED)
+#define IS_CONNECT_FAILED(status) GET_STATUS_BIT(status, STATUS_BIT_CONNECTION_FAILED)
+#define IS_PING_DONE(status) GET_STATUS_BIT(status, STATUS_BIT_PING_DONE)
+
+#define MODWLAN_SL_SCAN_ENABLE 1
+#define MODWLAN_SL_SCAN_DISABLE 0
+#define MODWLAN_SL_MAX_NETWORKS 20
+
+#define MODWLAN_TIMEOUT_MS 5000
+#define MODWLAN_MAX_NETWORKS 20
+
+#define ASSERT_ON_ERROR( x ) ASSERT((x) >= 0 )
+
+#define IPV4_ADDR_STR_LEN_MAX (16)
+#define SL_STOP_TIMEOUT 500
+
+#define WLAN_MAX_RX_SIZE 16000
+
+#define MAKE_SOCKADDR(addr, ip, port) sockaddr addr; \
+ addr.sa_family = AF_INET; \
+ addr.sa_data[0] = port >> 8; \
+ addr.sa_data[1] = port; \
+ addr.sa_data[2] = ip[0]; \
+ addr.sa_data[3] = ip[1]; \
+ addr.sa_data[4] = ip[2]; \
+ addr.sa_data[5] = ip[3];
+
+#define UNPACK_SOCKADDR(addr, ip, port) port = (addr.sa_data[0] << 8) | addr.sa_data[1]; \
+ ip[0] = addr.sa_data[2]; \
+ ip[1] = addr.sa_data[3]; \
+ ip[2] = addr.sa_data[4]; \
+ ip[3] = addr.sa_data[5];
+
+/******************************************************************************
+ DECLARE PUBLIC DATA
+ ******************************************************************************/
+STATIC wlan_obj_t wlan_obj;
+
+/******************************************************************************
+ DECLARE EXPORTED DATA
+ ******************************************************************************/
+SemaphoreHandle_t xWlanSemaphore = NULL;
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+STATIC void wlan_initialize_data (void);
+STATIC void wlan_reenable (SlWlanMode_t mode);
+STATIC void wlan_get_sl_mac (void);
+STATIC modwlan_Status_t wlan_do_connect (const char* ssid, uint32_t ssid_len, const char* bssid, uint8_t sec,
+ const char* key, uint32_t key_len);
+
+
+//*****************************************************************************
+//
+//! \brief The Function Handles WLAN Events
+//!
+//! \param[in] pWlanEvent - Pointer to WLAN Event Info
+//!
+//! \return None
+//!
+//*****************************************************************************
+void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent)
+{
+ if(!pWlanEvent) {
+ return;
+ }
+
+ switch(pWlanEvent->Event)
+ {
+ case SL_WLAN_CONNECT_EVENT:
+ {
+ SET_STATUS_BIT(wlan_obj.status, STATUS_BIT_CONNECTION);
+ //
+ // Information about the connected AP (like name, MAC etc) will be
+ // available in 'slWlanConnectAsyncResponse_t'-Applications
+ // can use it if required
+ //
+ slWlanConnectAsyncResponse_t *pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected;
+
+ // Copy new connection SSID and BSSID to global parameters
+ memcpy(wlan_obj.ssid_name, pEventData->ssid_name, pEventData->ssid_len);
+ memcpy(wlan_obj.bssid, pEventData->bssid, SL_BSSID_LENGTH);
+ }
+ break;
+ case SL_WLAN_DISCONNECT_EVENT:
+ {
+ slWlanConnectAsyncResponse_t* pEventData = NULL;
+
+ CLR_STATUS_BIT(wlan_obj.status, STATUS_BIT_CONNECTION);
+ CLR_STATUS_BIT(wlan_obj.status, STATUS_BIT_IP_ACQUIRED);
+
+ pEventData = &pWlanEvent->EventData.STAandP2PModeDisconnected;
+
+ // If the user has initiated the 'Disconnect' request,
+ //'reason_code' is SL_USER_INITIATED_DISCONNECTION
+ if (SL_USER_INITIATED_DISCONNECTION == pEventData->reason_code) {
+
+ }
+ else {
+
+ }
+ memset(wlan_obj.ssid_name, 0, sizeof(wlan_obj.ssid_name));
+ memset(wlan_obj.bssid, 0, sizeof(wlan_obj.bssid));
+ }
+ break;
+ case SL_WLAN_STA_CONNECTED_EVENT:
+ break;
+ case SL_WLAN_STA_DISCONNECTED_EVENT:
+ break;
+ case SL_WLAN_P2P_DEV_FOUND_EVENT:
+ break;
+ case SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT:
+ break;
+ case SL_WLAN_CONNECTION_FAILED_EVENT:
+ break;
+ default:
+ break;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief This function handles network events such as IP acquisition, IP
+//! leased, IP released etc.
+//!
+//! \param[in] pNetAppEvent - Pointer to NetApp Event Info
+//!
+//! \return None
+//!
+//*****************************************************************************
+void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent)
+{
+ if(!pNetAppEvent) {
+ return;
+ }
+
+ switch(pNetAppEvent->Event)
+ {
+ case SL_NETAPP_IPV4_IPACQUIRED_EVENT:
+ {
+ SlIpV4AcquiredAsync_t *pEventData = NULL;
+
+ SET_STATUS_BIT(wlan_obj.status, STATUS_BIT_IP_ACQUIRED);
+
+ // Ip Acquired Event Data
+ pEventData = &pNetAppEvent->EventData.ipAcquiredV4;
+
+ // Get the IP addresses
+ wlan_obj.gateway = ntohl(pEventData->gateway);
+ wlan_obj.ip = ntohl(pEventData->ip);
+ wlan_obj.dns = ntohl(pEventData->dns);
+ }
+ break;
+ case SL_NETAPP_IPV6_IPACQUIRED_EVENT:
+ break;
+ case SL_NETAPP_IP_LEASED_EVENT:
+ break;
+ case SL_NETAPP_IP_RELEASED_EVENT:
+ break;
+ default:
+ break;
+ }
+}
+
+
+//*****************************************************************************
+//
+//! \brief This function handles HTTP server events
+//!
+//! \param[in] pServerEvent - Contains the relevant event information
+//! \param[in] pServerResponse - Should be filled by the user with the
+//! relevant response information
+//!
+//! \return None
+//!
+//****************************************************************************
+void SimpleLinkHttpServerCallback(SlHttpServerEvent_t *pHttpEvent, SlHttpServerResponse_t *pHttpResponse)
+{
+ if (!pHttpEvent) {
+ return;
+ }
+
+ switch (pHttpEvent->Event) {
+ case SL_NETAPP_HTTPGETTOKENVALUE_EVENT:
+ break;
+ case SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT:
+ break;
+ default:
+ break;
+ }
+}
+
+//*****************************************************************************
+//
+//! \brief This function handles General Events
+//!
+//! \param[in] pDevEvent - Pointer to General Event Info
+//!
+//! \return None
+//!
+//*****************************************************************************
+void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent)
+{
+ if (!pDevEvent) {
+ return;
+ }
+
+ ASSERT (false);
+}
+
+
+//*****************************************************************************
+//
+//! This function handles socket events indication
+//!
+//! \param[in] pSock - Pointer to Socket Event Info
+//!
+//! \return None
+//!
+//*****************************************************************************
+void SimpleLinkSockEventHandler(SlSockEvent_t *pSock)
+{
+ if (!pSock) {
+ return;
+ }
+
+ switch( pSock->Event ) {
+ case SL_SOCKET_TX_FAILED_EVENT:
+ break;
+ default:
+ break;
+ }
+}
+
+//*****************************************************************************
+// SimpleLink Asynchronous Event Handlers -- End
+//*****************************************************************************
+
+void wlan_init0 (void) {
+ // Set the mode to an invalid one
+ wlan_obj.mode = -1;
+ wlan_obj.base.type = NULL;
+ memset (wlan_obj.macAddr, 0, SL_MAC_ADDR_LEN);
+#ifdef USE_FREERTOS
+ if (NULL == xWlanSemaphore) {
+ xWlanSemaphore = xSemaphoreCreateBinary();
+ }
+#endif
+ wlan_initialize_data ();
+}
+
+modwlan_Status_t wlan_sl_enable (SlWlanMode_t mode, const char *ssid, uint8_t ssid_len, uint8_t sec,
+ const char *key, uint8_t key_len, uint8_t channel) {
+
+ if (mode == ROLE_STA || mode == ROLE_AP || mode == ROLE_P2P) {
+ if (wlan_obj.mode < 0) {
+ wlan_obj.mode = sl_Start(0, 0, 0);
+ #ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+ #endif
+ }
+
+ // get the mac address
+ wlan_get_sl_mac();
+
+ // stop the device if it's not in station mode
+ if (wlan_obj.mode != ROLE_STA) {
+ if (ROLE_AP == wlan_obj.mode) {
+ // if the device is in AP mode, we need to wait for this event
+ // before doing anything
+ while (!IS_IP_ACQUIRED(wlan_obj.status)) {
+ HAL_Delay (5);
+ }
+ }
+ // switch to STA mode
+ ASSERT_ON_ERROR(sl_WlanSetMode(ROLE_STA));
+ // stop and start again
+ wlan_reenable(ROLE_STA);
+ }
+
+ // Device in station-mode. Disconnect previous connection if any
+ // The function returns 0 if 'Disconnected done', negative number if already
+ // disconnected Wait for 'disconnection' event if 0 is returned, Ignore
+ // other return-codes
+ if (0 == sl_WlanDisconnect()) {
+ while (IS_CONNECTED (wlan_obj.status)) {
+ HAL_Delay (5);
+ }
+ }
+
+ // clear wlan data after checking any of the status flags
+ wlan_initialize_data ();
+
+ // Set connection policy to Auto + SmartConfig (Device's default connection policy)
+ ASSERT_ON_ERROR(sl_WlanPolicySet(SL_POLICY_CONNECTION, SL_CONNECTION_POLICY(1, 0, 0, 0, 1), NULL, 0));
+
+ // Remove all profiles
+ ASSERT_ON_ERROR(sl_WlanProfileDel(0xFF));
+
+ // Enable the DHCP client
+ uint8_t value = 1;
+ ASSERT_ON_ERROR(sl_NetCfgSet(SL_IPV4_STA_P2P_CL_DHCP_ENABLE, 1, 1, &value));
+
+ // Set PM policy to normal
+ ASSERT_ON_ERROR(sl_WlanPolicySet(SL_POLICY_PM, SL_NORMAL_POLICY, NULL, 0));
+
+ // Unregister mDNS services
+ ASSERT_ON_ERROR(sl_NetAppMDNSUnRegisterService(0, 0));
+
+ // Remove all 64 filters (8 * 8)
+ _WlanRxFilterOperationCommandBuff_t RxFilterIdMask;
+ memset ((void *)&RxFilterIdMask, 0 ,sizeof(RxFilterIdMask));
+ memset(RxFilterIdMask.FilterIdMask, 0xFF, 8);
+ ASSERT_ON_ERROR(sl_WlanRxFilterSet(SL_REMOVE_RX_FILTER, (_u8 *)&RxFilterIdMask, sizeof(_WlanRxFilterOperationCommandBuff_t)));
+
+ // Set Tx power level for station or AP mode
+ // Number between 0-15, as dB offset from max power - 0 will set max power
+ uint8_t ucPower = 0;
+ if (mode == ROLE_AP) {
+ // Disable the scanning
+ ASSERT_ON_ERROR(sl_WlanPolicySet(SL_POLICY_SCAN, MODWLAN_SL_SCAN_DISABLE, NULL, 0));
+
+ // Switch to AP mode
+ ASSERT_ON_ERROR(sl_WlanSetMode(mode));
+ ASSERT (ssid != NULL && key != NULL);
+ ASSERT_ON_ERROR(sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, WLAN_GENERAL_PARAM_OPT_AP_TX_POWER, sizeof(ucPower),
+ (unsigned char *)&ucPower));
+ ASSERT_ON_ERROR(sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_SSID, ssid_len, (unsigned char *)ssid));
+ ASSERT_ON_ERROR(sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_SECURITY_TYPE, sizeof(uint8_t), &sec));
+ ASSERT_ON_ERROR(sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_PASSWORD, key_len, (unsigned char *)key));
+ _u8* country = (_u8*)"EU";
+ ASSERT_ON_ERROR(sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE, 2, country));
+ ASSERT_ON_ERROR(sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_CHANNEL, 1, (_u8 *)&channel));
+
+ // Stop and start again
+ wlan_reenable(mode);
+ ASSERT (wlan_obj.mode == mode);
+
+ SlNetAppDhcpServerBasicOpt_t dhcpParams;
+ dhcpParams.lease_time = 4096; // lease time (in seconds) of the IP Address
+ dhcpParams.ipv4_addr_start = SL_IPV4_VAL(192,168,1,2); // first IP Address for allocation.
+ dhcpParams.ipv4_addr_last = SL_IPV4_VAL(192,168,1,254); // last IP Address for allocation.
+ ASSERT_ON_ERROR(sl_NetAppStop(SL_NET_APP_DHCP_SERVER_ID)); // Stop DHCP server before settings
+ ASSERT_ON_ERROR(sl_NetAppSet(SL_NET_APP_DHCP_SERVER_ID, NETAPP_SET_DHCP_SRV_BASIC_OPT,
+ sizeof(SlNetAppDhcpServerBasicOpt_t), (_u8* )&dhcpParams)); // set parameters
+ ASSERT_ON_ERROR(sl_NetAppStart(SL_NET_APP_DHCP_SERVER_ID)); // Start DHCP server with new settings
+
+ SlNetCfgIpV4Args_t ipV4;
+ ipV4.ipV4 = (_u32)SL_IPV4_VAL(192,168,1,1); // _u32 IP address
+ ipV4.ipV4Mask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this AP
+ ipV4.ipV4Gateway = (_u32)SL_IPV4_VAL(192,168,1,1); // _u32 Default gateway address
+ ipV4.ipV4DnsServer = (_u32)SL_IPV4_VAL(192,168,1,1); // _u32 DNS server address
+ ASSERT_ON_ERROR(sl_NetCfgSet(SL_IPV4_AP_P2P_GO_STATIC_ENABLE, IPCONFIG_MODE_ENABLE_IPV4,
+ sizeof(SlNetCfgIpV4Args_t), (_u8 *)&ipV4));
+
+ // Stop and start again
+ wlan_reenable(mode);
+ }
+ // STA and P2P modes
+ else {
+ ASSERT_ON_ERROR(sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, WLAN_GENERAL_PARAM_OPT_STA_TX_POWER,
+ sizeof(ucPower), (unsigned char *)&ucPower));
+ // Enable scanning every 60 seconds
+ uint32_t scanSeconds = 60;
+ ASSERT_ON_ERROR(sl_WlanPolicySet(SL_POLICY_SCAN , MODWLAN_SL_SCAN_ENABLE, (_u8 *)&scanSeconds, sizeof(scanSeconds)));
+
+ if (mode == ROLE_P2P) {
+ // Switch to P2P mode
+ ASSERT_ON_ERROR(sl_WlanSetMode(mode));
+ // Stop and start again
+ wlan_reenable(mode);
+ }
+ }
+ return MODWLAN_OK;
+ }
+ return MODWLAN_ERROR_INVALID_PARAMS;
+}
+
+void wlan_sl_disable (void) {
+ if (wlan_obj.mode >= 0) {
+ #ifdef USE_FREERTOS
+ xSemaphoreTake (xWlanSemaphore, portMAX_DELAY);
+ #endif
+ wlan_obj.mode = -1;
+ ASSERT_ON_ERROR (sl_Stop(SL_STOP_TIMEOUT));
+ }
+}
+
+SlWlanMode_t wlan_get_mode (void) {
+ return wlan_obj.mode;
+}
+
+void wlan_get_mac (uint8_t *macAddress) {
+ if (macAddress) {
+ memcpy (macAddress, wlan_obj.macAddr, SL_MAC_ADDR_LEN);
+ }
+}
+
+void wlan_get_ip (uint32_t *ip) {
+ if (ip) {
+ *ip = IS_IP_ACQUIRED(wlan_obj.status) ? wlan_obj.ip : 0;
+ }
+}
+
+void wlan_set_pm_policy (uint8_t policy) {
+ ASSERT_ON_ERROR(sl_WlanPolicySet(SL_POLICY_PM, policy, NULL, 0));
+}
+
+void wlan_servers_stop (void) {
+ servers_disable();
+ do {
+ HAL_Delay (2);
+ } while (servers_are_enabled());
+}
+
+//*****************************************************************************
+// DEFINE STATIC FUNCTIONS
+//*****************************************************************************
+
+STATIC void wlan_initialize_data (void) {
+ wlan_obj.status = 0;
+ wlan_obj.dns = 0;
+ wlan_obj.gateway = 0;
+ wlan_obj.ip = 0;
+ memset(wlan_obj.ssid_name, 0, sizeof(wlan_obj.ssid_name));
+ memset(wlan_obj.bssid, 0, sizeof(wlan_obj.bssid));
+}
+
+STATIC void wlan_reenable (SlWlanMode_t mode) {
+ // Stop and start again
+ wlan_obj.mode = -1;
+#ifdef USE_FREERTOS
+ xSemaphoreTake (xWlanSemaphore, portMAX_DELAY);
+#endif
+ ASSERT_ON_ERROR(sl_Stop(SL_STOP_TIMEOUT));
+ wlan_obj.mode = sl_Start(0, 0, 0);
+#ifdef USE_FREERTOS
+ xSemaphoreGive (xWlanSemaphore);
+#endif
+ ASSERT (wlan_obj.mode == mode);
+}
+
+STATIC modwlan_Status_t wlan_do_connect (const char* ssid, uint32_t ssid_len, const char* bssid, uint8_t sec, const char* key, uint32_t key_len)
+{
+ SlSecParams_t secParams;
+
+ secParams.Key = (_i8*)key;
+ secParams.KeyLen = ((key != NULL) ? key_len : 0);
+ secParams.Type = sec;
+
+ if (0 == sl_WlanConnect((_i8*)ssid, ssid_len, (_u8*)bssid, &secParams, NULL)) {
+
+ // Wait for WLAN Event
+ uint32_t waitForConnectionMs = 0;
+ while (!IS_CONNECTED(wlan_obj.status)) {
+ HAL_Delay (5);
+ if (++waitForConnectionMs >= MODWLAN_TIMEOUT_MS) {
+ return MODWLAN_ERROR_TIMEOUT;
+ }
+ }
+
+ return MODWLAN_OK;
+ }
+
+ return MODWLAN_ERROR_INVALID_PARAMS;
+}
+
+STATIC void wlan_get_sl_mac (void) {
+ // Get the MAC address
+ uint8_t macAddrLen = SL_MAC_ADDR_LEN;
+ sl_NetCfgGet(SL_MAC_ADDRESS_GET,NULL, &macAddrLen, wlan_obj.macAddr);
+}
+
+/// \method init(mode, ssid=myWlan, security=wlan.WPA_WPA2, key=myWlanKey)
+///
+/// Initialise the UART bus with the given parameters:
+///
+/// - `mode` can be ROLE_AP, ROLE_STA and ROLE_P2P.
+/// - `ssid` is the network ssid in case of AP mode
+/// - `security` is the security type for AP mode
+/// - `key` is the key when in AP mode
+/// - `channel` is the channel to use for the AP network
+STATIC const mp_arg_t wlan_init_args[] = {
+ { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = ROLE_STA} },
+ { MP_QSTR_ssid, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+ { MP_QSTR_security, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = SL_SEC_TYPE_OPEN} },
+ { MP_QSTR_key, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+ { MP_QSTR_channel, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 5} },
+};
+
+STATIC mp_obj_t wlan_init_helper(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+ // parse args
+ mp_arg_val_t args[MP_ARRAY_SIZE(wlan_init_args)];
+ mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(wlan_init_args), wlan_init_args, args);
+
+ // get the ssid
+ mp_uint_t ssid_len;
+ const char *ssid = mp_obj_str_get_data(args[1].u_obj, &ssid_len);
+
+ // get the key
+ mp_uint_t key_len;
+ const char *key = mp_obj_str_get_data(args[3].u_obj, &key_len);
+
+ if (key_len < 8) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_TypeError, mpexception_value_invalid_arguments));
+ }
+
+ // Force the channel to be between 1-11
+ uint8_t channel = args[4].u_int > 0 ? args[4].u_int % 12 : 1;
+
+ if (MODWLAN_OK != wlan_sl_enable (args[0].u_int, ssid, ssid_len, args[2].u_int, key, key_len, channel)) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_operation_failed));
+ }
+
+ return mp_const_none;
+}
+
+
+/******************************************************************************/
+// Micro Python bindings; WLAN class
+
+/// \class WLAN - driver for the WLAN functionality of the SoC
+
+/// \classmethod \constructor()
+/// Create a wlan obecjt and initialise the simplelink engine
+//
+STATIC mp_obj_t wlan_make_new (mp_obj_t type_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+ // check arguments
+ mp_arg_check_num(n_args, n_kw, 0, MP_ARRAY_SIZE(wlan_init_args), true);
+
+ if (n_args > 0) {
+ // Get the mode
+ SlWlanMode_t mode = mp_obj_get_int(args[0]);
+
+ // Stop all other processes using the wlan engine
+ if ( (wlan_obj.servers_enabled = servers_are_enabled()) ) {
+ wlan_servers_stop();
+ }
+ if (mode == ROLE_AP) {
+ // start the peripheral
+ mp_map_t kw_args;
+ mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
+ wlan_init_helper(n_args, args, &kw_args);
+ }
+ // TODO: Only STA mode supported for the moment. What if P2P?
+ else if (n_args == 1) {
+ if (MODWLAN_OK != wlan_sl_enable (mode, NULL, 0, 0, NULL, 0, 0)) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_operation_failed));
+ }
+ }
+ else {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_TypeError, mpexception_num_type_invalid_arguments));
+ }
+
+ // Start the servers again
+ if (wlan_obj.servers_enabled) {
+ servers_enable ();
+ }
+ } else if (wlan_obj.mode < 0) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_TypeError, mpexception_num_type_invalid_arguments));
+ }
+
+ wlan_obj.base.type = (mp_obj_type_t*)&mod_network_nic_type_wlan;
+ // register with the network module
+ mod_network_register_nic(&wlan_obj);
+
+ return &wlan_obj;
+}
+
+STATIC void wlan_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) {
+ wlan_obj_t *self = self_in;
+ print(env, "wlan(mode=%u, status=%u", self->mode, self->status);
+ print(env, ", mac=%02x:%02x:%02x:%02x:%02x:%02x", self->macAddr[0], self->macAddr[1], self->macAddr[2],
+ self->macAddr[3], self->macAddr[4], self->macAddr[5]);
+
+ // Only print the ssid if in station or ap mode
+ if (self->mode == ROLE_STA || self->mode == ROLE_AP) {
+ print(env, ", ssid=%s", self->ssid_name);
+
+ // Only print the bssid if in station mode
+ if (self->mode == ROLE_STA) {
+ print(env, ", bssid=%02x:%02x:%02x:%02x:%02x:%02x", self->bssid[0], self->bssid[1], self->bssid[2],
+ self->bssid[3], self->bssid[4], self->bssid[5]);
+ }
+
+ char ip_str[IPV4_ADDR_STR_LEN_MAX];
+ uint8_t *ip = (uint8_t *)&self->ip;
+ snprintf(ip_str, 16, "%u.%u.%u.%u", ip[0], ip[1], ip[2], ip[3]);
+ print(env, ", ip=%s", ip_str);
+ ip = (uint8_t *)&self->gateway;
+ snprintf(ip_str, 16, "%u.%u.%u.%u", ip[0], ip[1], ip[2], ip[3]);
+ print(env, ", gateway=%s", ip_str);
+ ip = (uint8_t *)&self->dns;
+ snprintf(ip_str, 16, "%u.%u.%u.%u", ip[0], ip[1], ip[2], ip[3]);
+ print(env, ", dns=%s)", ip_str);
+ }
+ else {
+ print(env, ")");
+ }
+}
+
+/// \method mode()
+/// Get the wlan mode:
+///
+/// - Returns the current wlan mode. Possible values are:
+/// ROLE_STA, ROLE_AP and ROLE_P2P
+///
+STATIC mp_obj_t wlan_getmode(mp_obj_t self_in) {
+ wlan_obj_t* self = self_in;
+ return mp_obj_new_int(self->mode);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_getmode_obj, wlan_getmode);
+
+STATIC mp_obj_t wlan_setpm(mp_obj_t self_in, mp_obj_t pm_mode) {
+ mp_int_t mode = mp_obj_get_int(pm_mode);
+ if (mode < SL_NORMAL_POLICY || mode > SL_LONG_SLEEP_INTERVAL_POLICY) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+ }
+ wlan_set_pm_policy((uint8_t)mode);
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(wlan_setpm_obj, wlan_setpm);
+
+/// \method connect(ssid, key=None, *, security=OPEN, bssid=None)
+STATIC mp_obj_t wlan_connect(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+ STATIC const mp_arg_t allowed_args[] = {
+ { MP_QSTR_ssid, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+ { MP_QSTR_key, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+ { MP_QSTR_security, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = SL_SEC_TYPE_OPEN} },
+ { MP_QSTR_bssid, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+ };
+
+ // parse args
+ mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
+ mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
+
+ // get ssid
+ mp_uint_t ssid_len;
+ const char *ssid = mp_obj_str_get_data(args[0].u_obj, &ssid_len);
+
+ // get key and sec
+ mp_uint_t key_len = 0;
+ const char *key = NULL;
+ mp_uint_t sec = SL_SEC_TYPE_OPEN;
+ if (args[1].u_obj != mp_const_none) {
+ key = mp_obj_str_get_data(args[1].u_obj, &key_len);
+ sec = args[2].u_int;
+ }
+
+ // get bssid
+ const char *bssid = NULL;
+ if (args[3].u_obj != mp_const_none) {
+ bssid = mp_obj_str_get_str(args[3].u_obj);
+ }
+
+ if (wlan_obj.mode != ROLE_STA) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_request_not_possible));
+ }
+ else {
+ if (GET_STATUS_BIT(wlan_obj.status, STATUS_BIT_CONNECTION)) {
+ if (0 == sl_WlanDisconnect()) {
+ while (IS_CONNECTED(wlan_obj.status)) {
+ HAL_Delay (5);
+ }
+ }
+ }
+ // connect to the requested access point
+ modwlan_Status_t status;
+ status = wlan_do_connect (ssid, ssid_len, bssid, sec, key, key_len);
+ if (status != MODWLAN_OK) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_operation_failed));
+ }
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(wlan_connect_obj, 1, wlan_connect);
+
+/// \method wlan_disconnect()
+/// Closes the current WLAN connection
+///
+STATIC mp_obj_t wlan_disconnect(mp_obj_t self_in) {
+ sl_WlanDisconnect();
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_disconnect_obj, wlan_disconnect);
+
+/// \method is_connected()
+/// Returns true if connected to the AP and an IP address has been assigned. False otherwise.
+///
+STATIC mp_obj_t wlan_isconnected(mp_obj_t self_in) {
+ if (GET_STATUS_BIT(wlan_obj.status, STATUS_BIT_CONNECTION) &&
+ GET_STATUS_BIT(wlan_obj.status, STATUS_BIT_IP_ACQUIRED)) {
+ return mp_const_true;
+ }
+ return mp_const_false;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_isconnected_obj, wlan_isconnected);
+
+/// \method getip()
+/// Get the IP
+///
+/// - Returns the acquired IP address
+///
+STATIC mp_obj_t wlan_getip(mp_obj_t self_in) {
+ return mod_network_format_ipv4_addr ((uint8_t *)&wlan_obj.ip);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_getip_obj, wlan_getip);
+
+
+/// \method wlan_netlist()
+/// Returns a list of tuples with all the acces points within range
+STATIC mp_obj_t wlan_scan(mp_obj_t self_in) {
+ Sl_WlanNetworkEntry_t wlanEntry;
+ uint8_t _index = 0;
+ mp_obj_t nets = NULL;
+
+ do {
+ if (sl_WlanGetNetworkList(_index++, 1, &wlanEntry) <= 0) {
+ break;
+ }
+ mp_obj_t tuple[4];
+
+ tuple[0] = mp_obj_new_str((const char *)wlanEntry.ssid, wlanEntry.ssid_len, false);
+ tuple[1] = mp_obj_new_str((const char *)wlanEntry.bssid, SL_BSSID_LENGTH, false);
+ // 'Normalize' the security type
+ if (wlanEntry.sec_type > 2) {
+ wlanEntry.sec_type = 2;
+ }
+ tuple[2] = mp_obj_new_int(wlanEntry.sec_type);
+ tuple[3] = mp_obj_new_int(wlanEntry.rssi);
+
+ if (_index == 1) {
+ // Initialize the set
+ nets = mp_obj_new_set(0, NULL);
+ }
+ // Add the network found to the list if it's unique
+ mp_obj_set_store(nets, mp_obj_new_tuple(4, tuple));
+
+ } while (_index < MODWLAN_SL_MAX_NETWORKS);
+
+ return (nets != NULL) ? nets : mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_scan_obj, wlan_scan);
+
+STATIC mp_obj_t wlan_serversstart(mp_obj_t self_in) {
+ servers_enable();
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_serversstart_obj, wlan_serversstart);
+
+STATIC mp_obj_t wlan_serversstop(mp_obj_t self_in) {
+ wlan_servers_stop();
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_serversstop_obj, wlan_serversstop);
+
+STATIC mp_obj_t wlan_areserversenabled(mp_obj_t self_in) {
+ return MP_BOOL(servers_are_enabled());
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(wlan_areserversenabled_obj, wlan_areserversenabled);
+
+STATIC mp_obj_t wlan_serversuserpass(mp_obj_t self_in, mp_obj_t user, mp_obj_t pass) {
+ const char *_user = mp_obj_str_get_str(user);
+ const char *_pass = mp_obj_str_get_str(pass);
+ servers_set_user_pass((char *)_user, (char *)_pass);
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_3(wlan_serversuserpass_obj, wlan_serversuserpass);
+
+STATIC const mp_map_elem_t wlan_locals_dict_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR_connect), (mp_obj_t)&wlan_connect_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_getmode), (mp_obj_t)&wlan_getmode_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_setpm), (mp_obj_t)&wlan_setpm_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_scan), (mp_obj_t)&wlan_scan_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_disconnect), (mp_obj_t)&wlan_disconnect_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_isconnected), (mp_obj_t)&wlan_isconnected_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_getip), (mp_obj_t)&wlan_getip_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_serversstart), (mp_obj_t)&wlan_serversstart_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_serversstop), (mp_obj_t)&wlan_serversstop_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_areserversenabled), (mp_obj_t)&wlan_areserversenabled_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_serversuserpass), (mp_obj_t)&wlan_serversuserpass_obj },
+
+ // class constants
+ { MP_OBJ_NEW_QSTR(MP_QSTR_OPEN), MP_OBJ_NEW_SMALL_INT(SL_SEC_TYPE_OPEN) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_WEP), MP_OBJ_NEW_SMALL_INT(SL_SEC_TYPE_WEP) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_WPA_WPA2), MP_OBJ_NEW_SMALL_INT(SL_SEC_TYPE_WPA_WPA2) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_WPA_ENT), MP_OBJ_NEW_SMALL_INT(SL_SEC_TYPE_WPA_ENT) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_WPS_PBC), MP_OBJ_NEW_SMALL_INT(SL_SEC_TYPE_WPS_PBC) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_WPS_PIN), MP_OBJ_NEW_SMALL_INT(SL_SEC_TYPE_WPS_PIN) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_STA), MP_OBJ_NEW_SMALL_INT(ROLE_STA) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_AP), MP_OBJ_NEW_SMALL_INT(ROLE_AP) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_P2P), MP_OBJ_NEW_SMALL_INT(ROLE_P2P) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_NORMAL_PM), MP_OBJ_NEW_SMALL_INT(SL_NORMAL_POLICY) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_LOW_LATENCY_PM), MP_OBJ_NEW_SMALL_INT(SL_LOW_LATENCY_POLICY) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_LOW_POWER_PM), MP_OBJ_NEW_SMALL_INT(SL_LOW_POWER_POLICY) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_ALWAYS_ON_PM), MP_OBJ_NEW_SMALL_INT(SL_ALWAYS_ON_POLICY) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_LONG_SLEEP_PM), MP_OBJ_NEW_SMALL_INT(SL_LONG_SLEEP_INTERVAL_POLICY) },
+};
+STATIC MP_DEFINE_CONST_DICT(wlan_locals_dict, wlan_locals_dict_table);
+
+
+/******************************************************************************/
+// Micro Python bindings; WLAN socket
+
+STATIC int wlan_gethostbyname(mp_obj_t nic, const char *name, mp_uint_t len, uint8_t *out_ip, uint8_t family) {
+ uint32_t ip;
+ int result = sl_NetAppDnsGetHostByName((_i8 *)name, (_u16)len, (_u32*)&ip, (_u8)family);
+
+ out_ip[0] = ip >> 24;
+ out_ip[1] = ip >> 16;
+ out_ip[2] = ip >> 8;
+ out_ip[3] = ip;
+
+ return result;
+}
+
+STATIC int wlan_socket_socket(struct _mod_network_socket_obj_t *s, int *_errno) {
+ // open the socket
+ int16_t sd = sl_Socket(s->u_param.domain, s->u_param.type, s->u_param.proto);
+ if (s->sd < 0) {
+ *_errno = s->sd;
+ return -1;
+ }
+
+ // mark the socket not closed
+ s->closed = false;
+ // save the socket descriptor
+ s->sd = sd;
+
+ // make it blocking by default
+ int32_t optval = 0;
+ sl_SetSockOpt(sd, SOL_SOCKET, SO_NONBLOCKING, &optval, (SlSocklen_t)sizeof(optval));
+
+ return 0;
+}
+
+STATIC void wlan_socket_close(mod_network_socket_obj_t *s) {
+ s->closed = true;
+ sl_Close(s->sd);
+}
+
+STATIC int wlan_socket_bind(mod_network_socket_obj_t *s, byte *ip, mp_uint_t port, int *_errno) {
+ MAKE_SOCKADDR(addr, ip, port)
+ int ret = sl_Bind(s->sd, &addr, sizeof(addr));
+ if (ret != 0) {
+ *_errno = ret;
+ return -1;
+ }
+ return 0;
+}
+
+STATIC int wlan_socket_listen(mod_network_socket_obj_t *s, mp_int_t backlog, int *_errno) {
+ int ret = sl_Listen(s->sd, backlog);
+ if (ret != 0) {
+ *_errno = ret;
+ return -1;
+ }
+ return 0;
+}
+
+STATIC int wlan_socket_accept(mod_network_socket_obj_t *s, mod_network_socket_obj_t *s2, byte *ip, mp_uint_t *port, int *_errno) {
+ // accept incoming connection
+ int16_t sd;
+ sockaddr addr;
+ socklen_t addr_len = sizeof(addr);
+ if ((sd = sl_Accept(s->sd, &addr, &addr_len)) < 0) {
+ *_errno = sd;
+ return -1;
+ }
+
+ // Mark the socket not closed and save the new descriptor
+ s2->closed = false;
+ s2->sd = sd;
+
+ // return ip and port
+ UNPACK_SOCKADDR(addr, ip, *port);
+
+ return 0;
+}
+
+STATIC int wlan_socket_connect(mod_network_socket_obj_t *s, byte *ip, mp_uint_t port, int *_errno) {
+ MAKE_SOCKADDR(addr, ip, port)
+ int ret = sl_Connect(s->sd, &addr, sizeof(addr));
+ if (ret != 0) {
+ *_errno = ret;
+ return -1;
+ }
+ return 0;
+}
+
+STATIC int wlan_socket_send(mod_network_socket_obj_t *s, const byte *buf, mp_uint_t len, int *_errno) {
+ if (s->closed) {
+ sl_Close (s->sd);
+ *_errno = EBADF;
+ return -1;
+ }
+
+ mp_int_t bytes = 0;
+ if (len > 0) {
+ bytes = sl_Send(s->sd, (const void *)buf, len, 0);
+ }
+ if (bytes <= 0) {
+ *_errno = bytes;
+ return -1;
+ }
+
+ return bytes;
+}
+
+STATIC int wlan_socket_recv(mod_network_socket_obj_t *s, byte *buf, mp_uint_t len, int *_errno) {
+ // check if the socket is open
+ if (s->closed) {
+ // socket is closed, but the CC3200 may have some data remaining in its buffer, so check
+ fd_set rfds;
+ FD_ZERO(&rfds);
+ FD_SET(s->sd, &rfds);
+ timeval tv;
+ tv.tv_sec = 0;
+ tv.tv_usec = 2;
+ int nfds = sl_Select(s->sd + 1, &rfds, NULL, NULL, &tv);
+ if (nfds == -1 || !FD_ISSET(s->sd, &rfds)) {
+ // no data waiting, so close socket and return 0 data
+ sl_Close(s->sd);
+ return 0;
+ }
+ }
+
+ // cap length at WLAN_MAX_RX_SIZE
+ len = MIN(len, WLAN_MAX_RX_SIZE);
+
+ // do the recv
+ int ret = sl_Recv(s->sd, buf, len, 0);
+ if (ret < 0) {
+ *_errno = ret;
+ return -1;
+ }
+
+ return ret;
+}
+
+STATIC int wlan_socket_sendto( mod_network_socket_obj_t *s, const byte *buf, mp_uint_t len, byte *ip, mp_uint_t port, int *_errno) {
+ MAKE_SOCKADDR(addr, ip, port)
+ int ret = sl_SendTo(s->sd, (byte*)buf, len, 0, (sockaddr*)&addr, sizeof(addr));
+ if (ret < 0) {
+ *_errno = ret;
+ return -1;
+ }
+ return ret;
+}
+
+STATIC int wlan_socket_recvfrom(mod_network_socket_obj_t *s, byte *buf, mp_uint_t len, byte *ip, mp_uint_t *port, int *_errno) {
+ sockaddr addr;
+ socklen_t addr_len = sizeof(addr);
+ mp_int_t ret = sl_RecvFrom(s->sd, buf, len, 0, &addr, &addr_len);
+ if (ret < 0) {
+ *_errno = ret;
+ return -1;
+ }
+ UNPACK_SOCKADDR(addr, ip, *port);
+ return ret;
+}
+
+STATIC int wlan_socket_setsockopt(mod_network_socket_obj_t *socket, mp_uint_t level, mp_uint_t opt, const void *optval, mp_uint_t optlen, int *_errno) {
+ int ret = sl_SetSockOpt(socket->sd, level, opt, optval, optlen);
+ if (ret < 0) {
+ *_errno = ret;
+ return -1;
+ }
+ return 0;
+}
+
+STATIC int wlan_socket_settimeout(mod_network_socket_obj_t *s, mp_uint_t timeout_ms, int *_errno) {
+ int ret;
+ if (timeout_ms == 0 || timeout_ms == -1) {
+ int optval;
+ if (timeout_ms == 0) {
+ // set non-blocking mode
+ optval = 1;
+ } else {
+ // set blocking mode
+ optval = 0;
+ }
+ ret = sl_SetSockOpt(s->sd, SOL_SOCKET, SO_NONBLOCKING, &optval, sizeof(optval));
+ } else {
+ // set timeout
+ ret = sl_SetSockOpt(s->sd, SOL_SOCKET, SO_RCVTIMEO, &timeout_ms, sizeof(timeout_ms));
+ }
+
+ if (ret != 0) {
+ *_errno = ret;
+ return -1;
+ }
+
+ return 0;
+}
+
+STATIC int wlan_socket_ioctl (mod_network_socket_obj_t *s, mp_uint_t request, mp_uint_t arg, int *_errno) {
+ mp_int_t ret;
+ if (request == MP_IOCTL_POLL) {
+ mp_uint_t flags = arg;
+ ret = 0;
+ int32_t sd = s->sd;
+
+ // init fds
+ fd_set rfds, wfds, xfds;
+ FD_ZERO(&rfds);
+ FD_ZERO(&wfds);
+ FD_ZERO(&xfds);
+
+ // set fds if needed
+ if (flags & MP_IOCTL_POLL_RD) {
+ FD_SET(sd, &rfds);
+
+ // A socked that just closed is available for reading. A call to
+ // recv() returns 0 which is consistent with BSD.
+ if (s->closed) {
+ ret |= MP_IOCTL_POLL_RD;
+ }
+ }
+ if (flags & MP_IOCTL_POLL_WR) {
+ FD_SET(sd, &wfds);
+ }
+ if (flags & MP_IOCTL_POLL_HUP) {
+ FD_SET(sd, &xfds);
+ }
+
+ // call simplelink select with minimum timeout
+ SlTimeval_t tv;
+ tv.tv_sec = 0;
+ tv.tv_usec = 1;
+ int32_t nfds = sl_Select(sd + 1, &rfds, &wfds, &xfds, &tv);
+
+ // check for error
+ if (nfds == -1) {
+ *_errno = nfds;
+ return -1;
+ }
+
+ // check return of select
+ if (FD_ISSET(sd, &rfds)) {
+ ret |= MP_IOCTL_POLL_RD;
+ }
+ if (FD_ISSET(sd, &wfds)) {
+ ret |= MP_IOCTL_POLL_WR;
+ }
+ if (FD_ISSET(sd, &xfds)) {
+ ret |= MP_IOCTL_POLL_HUP;
+ }
+ } else {
+ *_errno = EINVAL;
+ ret = -1;
+ }
+ return ret;
+}
+
+const mod_network_nic_type_t mod_network_nic_type_wlan = {
+ .base = {
+ { &mp_type_type },
+ .name = MP_QSTR_WLAN,
+ .print = wlan_print,
+ .make_new = wlan_make_new,
+ .locals_dict = (mp_obj_t)&wlan_locals_dict,
+ },
+ .gethostbyname = wlan_gethostbyname,
+ .socket = wlan_socket_socket,
+ .close = wlan_socket_close,
+ .bind = wlan_socket_bind,
+ .listen = wlan_socket_listen,
+ .accept = wlan_socket_accept,
+ .connect = wlan_socket_connect,
+ .send = wlan_socket_send,
+ .recv = wlan_socket_recv,
+ .sendto = wlan_socket_sendto,
+ .recvfrom = wlan_socket_recvfrom,
+ .setsockopt = wlan_socket_setsockopt,
+ .settimeout = wlan_socket_settimeout,
+ .ioctl = wlan_socket_ioctl,
+};
diff --git a/cc3200/mods/modwlan.h b/cc3200/mods/modwlan.h
new file mode 100644
index 0000000000..7a84f2a511
--- /dev/null
+++ b/cc3200/mods/modwlan.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef SIMPLELINKTASK_H_
+#define SIMPLELINKTASK_H_
+
+/******************************************************************************
+ DEFINE CONSTANTS
+ ******************************************************************************/
+#define SIMPLELINK_SPAWN_TASK_PRIORITY 3
+#define SIMPLELINK_TASK_STACK_SIZE 2048
+
+/******************************************************************************
+ DEFINE TYPES
+ ******************************************************************************/
+typedef enum
+{
+ MODWLAN_OK = 0,
+ MODWLAN_ERROR_INVALID_PARAMS = -1,
+ MODWLAN_ERROR_TIMEOUT = -2,
+ MODWLAN_ERROR_UNKNOWN = -3
+
+}modwlan_Status_t;
+
+/******************************************************************************
+ DECLARE PUBLIC DATA
+ ******************************************************************************/
+#ifdef USE_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+extern SemaphoreHandle_t xWlanSemaphore;
+#endif
+
+/******************************************************************************
+ DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+extern void wlan_init0 (void);
+extern modwlan_Status_t wlan_sl_enable (SlWlanMode_t mode, const char *ssid, uint8_t ssid_len, uint8_t sec,
+ const char *key, uint8_t key_len, uint8_t channel);
+extern void wlan_sl_disable (void);
+extern SlWlanMode_t wlan_get_mode (void);
+extern void wlan_get_mac (uint8_t *macAddress);
+extern void wlan_get_ip (uint32_t *ip);
+extern void wlan_set_pm_policy (uint8_t policy);
+extern void wlan_servers_stop (void);
+
+#endif /* SIMPLELINKTASK_H_ */
diff --git a/cc3200/mods/pybextint.c b/cc3200/mods/pybextint.c
new file mode 100644
index 0000000000..abfec5572d
--- /dev/null
+++ b/cc3200/mods/pybextint.c
@@ -0,0 +1,357 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "py/nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "py/runtime.h"
+#include "py/gc.h"
+#include "py/pfenv.h"
+#include "py/objlist.h"
+#include "inc/hw_types.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "pin.h"
+#include "gpio.h"
+#include "pybgpio.h"
+#include "pybextint.h"
+#include "mpexception.h"
+#include "interrupt.h"
+#include "mpstate.h"
+#include "cc3200_asm.h"
+
+/// \moduleref pyb
+/// \class ExtInt - configure I/O pins to interrupt on external events
+///
+/// There are a maximum of 25 GPIO interrupt lines.
+///
+/// Example callback:
+///
+/// def callback(line):
+/// print(line.pin())
+///
+/// Note: ExtInt will automatically configure the gpio line as an input.
+///
+/// extint = pyb.ExtInt('GPIO10', pyb.ExtInt.IRQ_FALLING, pyb.GPIO.STD_PU, callback)
+///
+/// Now every time a falling edge is seen on the gpio pin, the callback will be
+/// called. Caution: mechanical pushbuttons have "bounce" and pushing or
+/// releasing a switch will often generate multiple edges.
+/// See: http://www.eng.utah.edu/~cs5780/debouncing.pdf for a detailed
+/// explanation, along with various techniques for debouncing.
+///
+/// All gpio objects go through the gpio mapper to come up with one of the
+/// gpio pins.
+///
+/// extint = pyb.ExtInt(gpio, mode, pull, callback)
+///
+/// There is also a C API, so that drivers which require EXTI interrupt lines
+/// can also use this code. See pybextint.h for the available functions.
+
+STATIC void ExecuteIntCallback (extint_obj_t *self);
+STATIC void GPIOA0IntHandler (void);
+STATIC void GPIOA1IntHandler (void);
+STATIC void GPIOA2IntHandler (void);
+STATIC void GPIOA3IntHandler (void);
+STATIC void EXTI_Handler(uint port);
+
+STATIC extint_obj_t* extint_add (uint pin_num, uint port, uint bit) {
+ extint_obj_t *self = m_new_obj(extint_obj_t);
+
+ self->port = port;
+ self->bit = bit;
+ self->callback = NULL;
+ self->pin_num = pin_num;
+ // add it to the list
+ mp_obj_list_append(&MP_STATE_PORT(pyb_extint_list), self);
+
+ return self;
+}
+
+STATIC extint_obj_t* extint_find (uint port, uint8_t bit) {
+ for (mp_uint_t i = 0; i < MP_STATE_PORT(pyb_extint_list).len; i++) {
+ extint_obj_t *self = (extint_obj_t *)MP_STATE_PORT(pyb_extint_list).items[i];
+ if (self->port == port && self->bit == bit) {
+ return self;
+ }
+ }
+ return NULL;
+}
+
+/// \method line()
+/// Return the pin number to which this external interrupt is mapped to.
+STATIC mp_obj_t extint_obj_pin(mp_obj_t self_in) {
+ extint_obj_t *self = self_in;
+ return MP_OBJ_NEW_SMALL_INT(self->pin_num);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_pin_obj, extint_obj_pin);
+
+/// \method enable()
+/// Enable a disabled interrupt.
+STATIC mp_obj_t extint_obj_enable(mp_obj_t self_in) {
+ extint_obj_t *self = self_in;
+ extint_enable(self);
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_enable_obj, extint_obj_enable);
+
+/// \method disable()
+/// Disable the interrupt associated with the ExtInt object.
+/// This could be useful for debouncing.
+STATIC mp_obj_t extint_obj_disable(mp_obj_t self_in) {
+ extint_obj_t *self = self_in;
+ extint_disable(self);
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_disable_obj, extint_obj_disable);
+
+/// \method swint()
+/// Trigger the callback from software.
+STATIC mp_obj_t extint_obj_swint(mp_obj_t self_in) {
+ extint_obj_t *self = self_in;
+ extint_swint(self);
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_swint_obj, extint_obj_swint);
+
+/// \classmethod \constructor(pin, mode, pull, callback)
+/// Create an ExtInt object:
+///
+/// - `gpio` is the gpio on which to enable the interrupt (can be a gpio object or any valid gpio name).
+/// - `mode` can be one of:
+/// - `ExtInt.IRQ_RISING` - trigger on a rising edge;
+/// - `ExtInt.IRQ_FALLING` - trigger on a falling edge;
+/// - `ExtInt.IRQ_RISING_FALLING` - trigger on a rising or falling edge.
+/// - `pull` can be one of:
+/// - `pyb.Pin.PULL_NONE` - no pull up or down resistors;
+/// - `pyb.Pin.PULL_UP` - enable the pull-up resistor;
+/// - `pyb.Pin.PULL_DOWN` - enable the pull-down resistor.
+/// - `callback` is the function to call when the interrupt triggers. The
+/// callback function must accept exactly 1 argument, which is the line that
+/// triggered the interrupt.
+STATIC const mp_arg_t pyb_extint_make_new_args[] = {
+ { MP_QSTR_gpio, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+ { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
+ { MP_QSTR_pull, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
+ { MP_QSTR_callback, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} },
+};
+#define PYB_EXTINT_MAKE_NEW_NUM_ARGS MP_ARRAY_SIZE(pyb_extint_make_new_args)
+
+STATIC mp_obj_t extint_make_new(mp_obj_t type_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+ // parse args
+ mp_arg_val_t vals[PYB_EXTINT_MAKE_NEW_NUM_ARGS];
+ mp_arg_parse_all_kw_array(n_args, n_kw, args, PYB_EXTINT_MAKE_NEW_NUM_ARGS, pyb_extint_make_new_args, vals);
+
+ extint_obj_t *self = extint_register(vals[0].u_obj, vals[1].u_int, vals[2].u_int, vals[3].u_obj);
+ self->base.type = type_in;
+
+ return self;
+}
+
+STATIC void extint_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) {
+ extint_obj_t *self = self_in;
+ print(env, "", self->pin_num);
+}
+
+STATIC const mp_map_elem_t extint_locals_dict_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR_pin), (mp_obj_t)&extint_obj_pin_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_enable), (mp_obj_t)&extint_obj_enable_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_disable), (mp_obj_t)&extint_obj_disable_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_swint), (mp_obj_t)&extint_obj_swint_obj },
+
+ // class constants
+ /// \constant IRQ_RISING - interrupt on a rising edge
+ /// \constant IRQ_FALLING - interrupt on a falling edge
+ /// \constant IRQ_RISING_FALLING - interrupt on a rising or falling edge
+ /// \constant IRQ_LOW_LEVEL - interrupt on a low level
+ /// \constant IRQ_HIGH_LEVEL - interrupt on a high level
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_FALLING), MP_OBJ_NEW_SMALL_INT(GPIO_FALLING_EDGE) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_RISING), MP_OBJ_NEW_SMALL_INT(GPIO_RISING_EDGE) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_RISING_FALLING), MP_OBJ_NEW_SMALL_INT(GPIO_BOTH_EDGES) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_LOW_LEVEL), MP_OBJ_NEW_SMALL_INT(GPIO_LOW_LEVEL) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IRQ_HIGH_LEVEL), MP_OBJ_NEW_SMALL_INT(GPIO_HIGH_LEVEL) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(extint_locals_dict, extint_locals_dict_table);
+
+STATIC void ExecuteIntCallback (extint_obj_t *self) {
+ if (self->callback != mp_const_none) {
+ // disable interrupts to avoid nesting
+ uint primsk = disable_irq();
+ // when executing code within a handler we must lock the GC to prevent
+ // any memory allocations. We must also catch any exceptions.
+ gc_lock();
+ nlr_buf_t nlr;
+ if (nlr_push(&nlr) == 0) {
+ mp_call_function_1(self->callback, self);
+ nlr_pop();
+ } else {
+ // uncaught exception; disable the callback so it doesn't run again
+ self->callback = mp_const_none;
+ extint_disable(self);
+ // printing an exception here will cause a stack overflow that ends up in a
+ // hard fault so, is better to signal the uncaught (probably non-recoverable)
+ // exception by blinkg the BLD
+ // TODO: Blink the BLD
+ }
+ gc_unlock();
+ enable_irq(primsk);
+ }
+}
+
+STATIC void GPIOA0IntHandler (void) {
+ EXTI_Handler(GPIOA0_BASE);
+}
+
+STATIC void GPIOA1IntHandler (void) {
+ EXTI_Handler(GPIOA1_BASE);
+}
+
+STATIC void GPIOA2IntHandler (void) {
+ EXTI_Handler(GPIOA2_BASE);
+}
+
+STATIC void GPIOA3IntHandler (void) {
+ EXTI_Handler(GPIOA3_BASE);
+}
+
+// common interrupt handler
+STATIC void EXTI_Handler(uint port) {
+ extint_obj_t *self;
+ uint32_t bit = MAP_GPIOIntStatus(port, true);
+
+ MAP_GPIOIntClear(port, bit);
+ if (NULL != (self = extint_find(port, bit))) {
+ ExecuteIntCallback(self);
+ }
+}
+
+const mp_obj_type_t extint_type = {
+ { &mp_type_type },
+ .name = MP_QSTR_ExtInt,
+ .print = extint_obj_print,
+ .make_new = extint_make_new,
+ .locals_dict = (mp_obj_t)&extint_locals_dict,
+};
+
+void extint_init0(void) {
+ mp_obj_list_init(&MP_STATE_PORT(pyb_extint_list), 0);
+}
+
+extint_obj_t* extint_register(mp_obj_t pin_obj, uint32_t intmode, uint32_t pull, mp_obj_t callback) {
+ const gpio_obj_t *gpio = NULL;
+ extint_obj_t* self;
+ void *handler;
+ uint32_t intnum;
+
+ gpio = gpio_find(pin_obj);
+
+ if (intmode != GPIO_FALLING_EDGE &&
+ intmode != GPIO_RISING_EDGE &&
+ intmode != GPIO_BOTH_EDGES &&
+ intmode != GPIO_LOW_LEVEL &&
+ intmode != GPIO_HIGH_LEVEL) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_value_invalid_arguments));
+ }
+ if (pull != PIN_TYPE_STD &&
+ pull != PIN_TYPE_STD_PU &&
+ pull != PIN_TYPE_STD_PD &&
+ pull != PIN_TYPE_OD &&
+ pull != PIN_TYPE_OD_PU &&
+ pull != PIN_TYPE_OD_PD) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_value_invalid_arguments));
+ }
+
+ if (NULL == (self = extint_find(gpio->port, gpio->bit))) {
+ self = extint_add(gpio->pin_num, gpio->port, gpio->bit);
+ }
+ else {
+ // we need to update the callback atomically, so we disable the line
+ // before we update anything.
+ extint_disable(self);
+ }
+
+ // invalidate the callback
+ self->callback = NULL;
+
+ // before enabling the interrupt, configure the gpio pin
+ gpio_config(gpio, PIN_MODE_0, GPIO_DIR_MODE_IN, pull, PIN_STRENGTH_4MA);
+
+ MAP_GPIOIntTypeSet(gpio->port, gpio->bit, intmode);
+ switch (gpio->port) {
+ case GPIOA0_BASE:
+ handler = GPIOA0IntHandler;
+ intnum = INT_GPIOA0;
+ break;
+ case GPIOA1_BASE:
+ handler = GPIOA1IntHandler;
+ intnum = INT_GPIOA1;
+ break;
+ case GPIOA2_BASE:
+ handler = GPIOA2IntHandler;
+ intnum = INT_GPIOA2;
+ break;
+ case GPIOA3_BASE:
+ default:
+ handler = GPIOA3IntHandler;
+ intnum = INT_GPIOA3;
+ break;
+ }
+
+ MAP_GPIOIntRegister(gpio->port, handler);
+ // set the interrupt to the lowest priority, to make sure that no ther
+ // isr will be preemted by this one
+ MAP_IntPrioritySet(intnum, INT_PRIORITY_LVL_7);
+
+ // set the new callback
+ self->callback = callback;
+ // enable the interrupt just before leaving
+ extint_enable(self);
+
+ return self;
+}
+
+void extint_enable(extint_obj_t *self) {
+ MAP_GPIOIntClear(self->port, self->bit);
+ MAP_GPIOIntEnable(self->port, self->bit);
+}
+
+void extint_disable(extint_obj_t *self) {
+ MAP_GPIOIntDisable(self->port, self->bit);
+}
+
+void extint_swint(extint_obj_t *self) {
+ ExecuteIntCallback(self);
+}
diff --git a/cc3200/mods/pybextint.h b/cc3200/mods/pybextint.h
new file mode 100644
index 0000000000..b479403b29
--- /dev/null
+++ b/cc3200/mods/pybextint.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef PYBEXTINT_H_
+#define PYBEXTINT_H_
+
+typedef struct {
+ mp_obj_base_t base;
+ mp_obj_t callback;
+ uint32_t port;
+ uint8_t pin_num;
+ uint8_t bit;
+} extint_obj_t;
+
+extern const mp_obj_type_t extint_type;
+
+void extint_init0(void);
+extint_obj_t* extint_register(mp_obj_t pin_obj, uint32_t intmode, uint32_t pull, mp_obj_t callback);
+void extint_enable(extint_obj_t *self);
+void extint_disable(extint_obj_t *self);
+void extint_swint(extint_obj_t *self);
+
+#endif /* PYBEXTINT_H_ */
diff --git a/cc3200/mods/pybgpio.c b/cc3200/mods/pybgpio.c
new file mode 100644
index 0000000000..cf52b501db
--- /dev/null
+++ b/cc3200/mods/pybgpio.c
@@ -0,0 +1,529 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include "py/mpstate.h"
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "runtime.h"
+#include "inc/hw_types.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "pin.h"
+#include "prcm.h"
+#include "gpio.h"
+#include "pybgpio.h"
+#include "mpexception.h"
+
+
+/// \moduleref pyb
+/// \class GPIO - control I/O pins
+///
+/// A pin is the basic object to control I/O pins. It has methods to set
+/// the mode of the pin (input or output) and methods to get and set the
+/// digital logic level. For analog control of a pin, see the ADC class.
+///
+/// Usage Model:
+///
+/// All CPU Pins are predefined as pyb.GPIO.cpu.Name
+///
+/// GPIO9_pin = pyb.GPIO.cpu.GPIO9
+///
+/// g = pyb.GPIO(pyb.GPIO.cpu.GPIO9, 0, pyb.GPIO.IN)
+///
+/// CPU pins which correspond to the board pins are available
+/// as `pyb.cpu.Name`.
+///
+/// You can also use strings:
+///
+/// g = pyb.GPIO('GPIO9', 0)
+///
+/// Users can add their own names:
+///
+/// MyMapperDict = { 'LeftMotorDir' : pyb.GPIO.cpu.GPIO11 }
+/// pyb.GPIO.dict(MyMapperDict)
+/// g = pyb.GPIO("LeftMotorDir", 0)
+///
+/// and can query mappings
+///
+/// g = pyb.GPIO("LeftMotorDir")
+///
+/// Users can also add their own mapping function:
+///
+/// def MyMapper(gpio_name):
+/// if gpio_name == "LeftMotorDir":
+/// return pyb.GPIO.cpu.GPIO11
+///
+/// pyb.GPIO.mapper(MyMapper)
+///
+/// So, if you were to call: `pyb.GPIO("LeftMotorDir", pyb.GPIO.OUT)`
+/// then `"LeftMotorDir"` is passed directly to the mapper function.
+///
+/// To summarise, the following order determines how things get mapped into
+/// an ordinal pin number:
+///
+/// 1. Directly specify a GPIO object
+/// 2. User supplied mapping function
+/// 3. User supplied mapping (object must be usable as a dictionary key)
+/// 4. Supply a string which matches a CPU port/pin
+
+void gpio_init0(void) {
+ MP_STATE_PORT(gpio_class_mapper) = mp_const_none;
+ MP_STATE_PORT(gpio_class_map_dict) = mp_const_none;
+}
+
+// C API used to convert a user-supplied pin name into an ordinal pin number.
+const gpio_obj_t *gpio_find(mp_obj_t user_obj) {
+ const gpio_obj_t *gpio_obj;
+
+ // If a pin was provided, then use it
+ if (MP_OBJ_IS_TYPE(user_obj, &gpio_type)) {
+ gpio_obj = user_obj;
+ return gpio_obj;
+ }
+
+ if (MP_STATE_PORT(gpio_class_mapper) != mp_const_none) {
+ gpio_obj = mp_call_function_1(MP_STATE_PORT(gpio_class_mapper), user_obj);
+ if (gpio_obj != mp_const_none) {
+ if (!MP_OBJ_IS_TYPE(gpio_obj, &gpio_type)) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_resource_not_avaliable));
+ }
+ return gpio_obj;
+ }
+ // The pin mapping function returned mp_const_none, fall through to
+ // other lookup methods.
+ }
+
+ if (MP_STATE_PORT(gpio_class_map_dict) != mp_const_none) {
+ mp_map_t *gpio_map_map = mp_obj_dict_get_map(MP_STATE_PORT(gpio_class_map_dict));
+ mp_map_elem_t *elem = mp_map_lookup(gpio_map_map, user_obj, MP_MAP_LOOKUP);
+ if (elem != NULL && elem->value != NULL) {
+ gpio_obj = elem->value;
+ return gpio_obj;
+ }
+ }
+
+ // See if the pin name matches a cpu pin
+ gpio_obj = gpio_find_named_pin(&gpio_cpu_pins_locals_dict, user_obj);
+ if (gpio_obj) {
+ return gpio_obj;
+ }
+
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+}
+
+void gpio_config(const gpio_obj_t *self, uint af, uint mode, uint type, uint strength) {
+ // PIN_MODE_0 means it stays as a GPIO, else, another peripheral will take control of it
+ if (af == PIN_MODE_0) {
+ // enable the peripheral clock for the GPIO port of this pin
+ switch (self->port) {
+ case PORT_A0:
+ MAP_PRCMPeripheralClkEnable(PRCM_GPIOA0, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+ break;
+ case PORT_A1:
+ MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+ break;
+ case PORT_A2:
+ MAP_PRCMPeripheralClkEnable(PRCM_GPIOA2, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+ break;
+ case PORT_A3:
+ MAP_PRCMPeripheralClkEnable(PRCM_GPIOA3, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+ break;
+ default:
+ break;
+ }
+ // configure the direction
+ MAP_GPIODirModeSet(self->port, self->bit, mode);
+ }
+
+ // now set the alternate function, strenght and type
+ MAP_PinModeSet (self->pin_num, af);
+ MAP_PinConfigSet(self->pin_num, strength, type);
+}
+
+/// \method print()
+/// Return a string describing the pin object.
+STATIC void gpio_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) {
+ gpio_obj_t *self = self_in;
+ uint32_t af = MAP_PinModeGet(self->pin_num);
+ uint32_t type = gpio_get_type(self);
+ uint32_t strength = gpio_get_strenght(self);
+
+ // pin name
+ print(env, "GPIO(GPIO.cpu.%s, af=%u", qstr_str(self->name), af);
+
+ if (af == PIN_MODE_0) {
+ // IO mode
+ qstr mode_qst;
+ uint32_t mode = gpio_get_mode(self);
+ if (mode == GPIO_DIR_MODE_IN) {
+ mode_qst = MP_QSTR_IN;
+ } else {
+ mode_qst = MP_QSTR_OUT;
+ }
+ print(env, ", mode=GPIO.%s", qstr_str(mode_qst)); // safe because mode_qst has no formatting chars
+ }
+
+ // pin type
+ qstr type_qst;
+ if (type == PIN_TYPE_STD) {
+ type_qst = MP_QSTR_STD;
+ } else if (type == PIN_TYPE_STD_PU) {
+ type_qst = MP_QSTR_STD_PU;
+ } else if (type == PIN_TYPE_STD_PD) {
+ type_qst = MP_QSTR_STD_PD;
+ } else if (type == PIN_TYPE_OD) {
+ type_qst = MP_QSTR_OD;
+ } else if (type == PIN_TYPE_OD_PU) {
+ type_qst = MP_QSTR_OD_PU;
+ } else {
+ type_qst = MP_QSTR_OD_PD;
+ }
+ print(env, ", pull=GPIO.%s", qstr_str(type_qst));
+
+ // Strength
+ qstr str_qst;
+ if (strength == PIN_STRENGTH_2MA) {
+ str_qst = MP_QSTR_S2MA;
+ } else if (strength == PIN_STRENGTH_4MA) {
+ str_qst = MP_QSTR_S4MA;
+ } else {
+ str_qst = MP_QSTR_S6MA;
+ }
+ print(env, ", strength=GPIO.%s)", qstr_str(str_qst));
+}
+
+STATIC mp_obj_t gpio_obj_init_helper(const gpio_obj_t *pin, mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args);
+
+/// \classmethod \constructor(id, ...)
+/// Create a new GPIO object associated with the id. If additional arguments are given,
+/// they are used to initialise the pin. See `init`.
+STATIC mp_obj_t gpio_make_new(mp_obj_t self_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+ mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
+
+ // Run an argument through the mapper and return the result.
+ const gpio_obj_t *pin = gpio_find(args[0]);
+
+ if (n_args > 1) {
+ // pin af given, so configure it
+ mp_map_t kw_args;
+ mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
+ gpio_obj_init_helper(pin, n_args - 1, args + 1, &kw_args);
+ }
+
+ return (mp_obj_t)pin;
+}
+
+/// \classmethod mapper([fun])
+/// Get or set the pin mapper function.
+STATIC mp_obj_t gpio_mapper(mp_uint_t n_args, const mp_obj_t *args) {
+ if (n_args > 1) {
+ MP_STATE_PORT(gpio_class_mapper) = args[1];
+ return mp_const_none;
+ }
+ return MP_STATE_PORT(gpio_class_mapper);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(gpio_mapper_fun_obj, 1, 2, gpio_mapper);
+STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(gpio_mapper_obj, (mp_obj_t)&gpio_mapper_fun_obj);
+
+/// \classmethod dict([dict])
+/// Get or set the pin mapper dictionary.
+STATIC mp_obj_t gpio_map_dict(mp_uint_t n_args, const mp_obj_t *args) {
+ if (n_args > 1) {
+ MP_STATE_PORT(gpio_class_map_dict) = args[1];
+ return mp_const_none;
+ }
+ return MP_STATE_PORT(gpio_class_map_dict);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(gpio_map_dict_fun_obj, 1, 2, gpio_map_dict);
+STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(gpio_map_dict_obj, (mp_obj_t)&gpio_map_dict_fun_obj);
+
+/// \method init(mode, pull=Pin.PULL_NONE, af=-1)
+/// Initialise the pin:
+///
+/// - `af` can be in range 0-15, please check the CC3200 datasheet
+/// for the details on the AFs availables on each pin (af=0, keeps it as a gpio pin).
+/// - `mode` can be one of:
+/// - `Pin.IN` - configure the pin for input;
+/// - `Pin.OUT` - configure the pin for output;
+/// - `type` can be one of:
+/// - `Pin.STD` - standard without pull-up or pull-down;
+/// - `Pin.STD_PU` - standard with pull-up resistor;
+/// - `Pin.STD_PD` - standard with pull-down resistor.
+/// - `Pin.OD` - standard without pull up or pull down;
+/// - `Pin.OD_PU` - open drain with pull-up resistor;
+/// - `Pin.OD_PD` - open drain with pull-down resistor.
+/// - `Pin.ANALOG` - configured in analog (adc) mode
+/// - `strength` can be one of:
+/// - `Pin.2MA` - 2ma drive strength;
+/// - `Pin.4MA` - 4ma drive strength;
+/// - `Pin.6MA` - 6ma drive strength;
+///
+/// Returns: `None`.
+STATIC const mp_arg_t gpio_init_args[] = {
+ { MP_QSTR_af, MP_ARG_REQUIRED | MP_ARG_INT },
+ { MP_QSTR_mode, MP_ARG_INT, {.u_int = GPIO_DIR_MODE_OUT} },
+ { MP_QSTR_type, MP_ARG_INT, {.u_int = PIN_TYPE_STD} },
+ { MP_QSTR_str, MP_ARG_INT, {.u_int = PIN_STRENGTH_4MA} },
+};
+#define gpio_INIT_NUM_ARGS MP_ARRAY_SIZE(gpio_init_args)
+
+STATIC mp_obj_t gpio_obj_init_helper(const gpio_obj_t *self, mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+ // parse args
+ mp_arg_val_t vals[gpio_INIT_NUM_ARGS];
+ mp_arg_parse_all(n_args, args, kw_args, gpio_INIT_NUM_ARGS, gpio_init_args, vals);
+
+ // get the af
+ uint af = vals[0].u_int;
+ if (af < PIN_MODE_0 || af > PIN_MODE_15) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+ }
+ // get the io mode
+ uint mode = vals[1].u_int;
+ if (mode != GPIO_DIR_MODE_IN && mode != GPIO_DIR_MODE_OUT) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+ }
+ // get the type
+ uint type = vals[2].u_int;
+ if (type != PIN_TYPE_STD && type != PIN_TYPE_STD_PU && type != PIN_TYPE_STD_PD &&
+ type != PIN_TYPE_OD && type != PIN_TYPE_OD_PU && type != PIN_TYPE_OD_PD) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+ }
+ // get the strenght
+ uint strength = vals[3].u_int;
+ if (strength != PIN_STRENGTH_2MA && strength != PIN_STRENGTH_4MA && strength != PIN_STRENGTH_6MA) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+ }
+
+ // configure the pin as requested
+ gpio_config (self, af, mode, type, strength);
+
+ return mp_const_none;
+}
+
+STATIC mp_obj_t gpio_obj_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+ return gpio_obj_init_helper(args[0], n_args - 1, args + 1, kw_args);
+}
+MP_DEFINE_CONST_FUN_OBJ_KW(gpio_init_obj, 1, gpio_obj_init);
+
+/// \method value([value])
+/// Get or set the digital logic level of the pin:
+///
+/// - With no argument, return 0 or 1 depending on the logic level of the pin.
+/// - With `value` given, set the logic level of the pin. `value` can be
+/// anything that converts to a boolean. If it converts to `True`, the pin
+/// is set high, otherwise it is set low.
+STATIC mp_obj_t gpio_value(mp_uint_t n_args, const mp_obj_t *args) {
+ gpio_obj_t *self = args[0];
+ if (n_args == 1) {
+ // get the pin value
+ return MP_OBJ_NEW_SMALL_INT(MAP_GPIOPinRead(self->port, self->bit) ? 1 : 0);
+ } else {
+ // set the pin value
+ if (mp_obj_is_true(args[1])) {
+ MAP_GPIOPinWrite(self->port, self->bit, self->bit);
+ } else {
+ MAP_GPIOPinWrite(self->port, self->bit, 0);
+ }
+ return mp_const_none;
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(gpio_value_obj, 1, 2, gpio_value);
+
+/// \method low()
+/// Set the pin to a low logic level.
+STATIC mp_obj_t gpio_low(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ MAP_GPIOPinWrite(self->port, self->bit, 0);
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_low_obj, gpio_low);
+
+/// \method high()
+/// Set the pin to a high logic level.
+STATIC mp_obj_t gpio_high(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ MAP_GPIOPinWrite(self->port, self->bit, self->bit);
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_high_obj, gpio_high);
+
+/// \method toggle()
+/// Toggles the value of the pin
+STATIC mp_obj_t gpio_toggle(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ MAP_GPIOPinWrite(self->port, self->bit, ~MAP_GPIOPinRead(self->port, self->bit));
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_toggle_obj, gpio_toggle);
+
+/// \method name()
+/// Get the pin name.
+STATIC mp_obj_t gpio_name(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ return MP_OBJ_NEW_QSTR(self->name);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_name_obj, gpio_name);
+
+/// \method name()
+/// Returns the cpu name for this pin.
+STATIC mp_obj_t gpio_cpu_name(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ mp_obj_t result = mp_obj_new_list(0, NULL);
+ mp_obj_list_append(result, MP_OBJ_NEW_QSTR(self->name));
+
+ mp_map_t *map = mp_obj_dict_get_map((mp_obj_t)&gpio_cpu_pins_locals_dict);
+ mp_map_elem_t *elem = map->table;
+
+ for (mp_uint_t i = 0; i < map->used; i++, elem++) {
+ if (elem->value == self) {
+ mp_obj_list_append(result, elem->key);
+ }
+ }
+ return result;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_cpu_name_obj, gpio_cpu_name);
+
+/// \method port()
+/// Get the pin port.
+STATIC mp_obj_t gpio_port(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ return mp_obj_new_int(self->port);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_port_obj, gpio_port);
+
+/// \method pin()
+/// Get the pin number.
+STATIC mp_obj_t gpio_pin(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ return MP_OBJ_NEW_SMALL_INT(self->pin_num);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_pin_obj, gpio_pin);
+
+/// \method mode()
+/// Returns the currently configured mode of the gpio pin. The integer returned
+/// will match one of the allowed constants for the mode argument to the init
+/// function.
+STATIC mp_obj_t gpio_mode(mp_obj_t self_in) {
+ return MP_OBJ_NEW_SMALL_INT(gpio_get_mode(self_in));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_mode_obj, gpio_mode);
+
+/// \method type()
+/// Returns the currently configured type of the pin. The integer returned
+/// will match one of the allowed constants for the type argument to the init
+/// function.
+STATIC mp_obj_t gpio_type_get(mp_obj_t self_in) {
+ return MP_OBJ_NEW_SMALL_INT(gpio_get_type(self_in));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_type_obj, gpio_type_get);
+
+/// \method strength()
+/// Returns the currently configured drive strength of the pin. The integer returned
+/// will match one of the allowed constants for the strength argument to the init
+/// function.
+STATIC mp_obj_t gpio_strength(mp_obj_t self_in) {
+ return MP_OBJ_NEW_SMALL_INT(gpio_get_strenght(self_in));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_strenght_obj, gpio_strength);
+
+/// \method af()
+/// Returns the currently configured alternate function of the gpio pin. The integer returned
+/// will match one of the allowed constants for the af argument to the init function.
+STATIC mp_obj_t gpio_af(mp_obj_t self_in) {
+ gpio_obj_t *self = self_in;
+ return MP_OBJ_NEW_SMALL_INT(MAP_PinModeGet(self->pin_num));
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(gpio_af_obj, gpio_af);
+
+STATIC const mp_map_elem_t gpio_locals_dict_table[] = {
+ // instance methods
+ { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&gpio_init_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_value), (mp_obj_t)&gpio_value_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_low), (mp_obj_t)&gpio_low_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_high), (mp_obj_t)&gpio_high_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_toggle), (mp_obj_t)&gpio_toggle_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_name), (mp_obj_t)&gpio_name_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_names), (mp_obj_t)&gpio_cpu_name_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_port), (mp_obj_t)&gpio_port_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_pin), (mp_obj_t)&gpio_pin_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_mode), (mp_obj_t)&gpio_mode_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_type), (mp_obj_t)&gpio_type_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_strength), (mp_obj_t)&gpio_strenght_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_af), (mp_obj_t)&gpio_af_obj },
+
+ // class methods
+ { MP_OBJ_NEW_QSTR(MP_QSTR_mapper), (mp_obj_t)&gpio_mapper_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_dict), (mp_obj_t)&gpio_map_dict_obj },
+
+ // class attributes
+ { MP_OBJ_NEW_QSTR(MP_QSTR_cpu), (mp_obj_t)&gpio_cpu_pins_obj_type },
+
+ // class constants
+ /// \constant IN - set the pin to input mode
+ /// \constant OUT - set the pin to output mode
+ /// \constant STD - set the pin to standard mode without pull-up or pull-down
+ /// \constant STD_PU - set the pin to standard mode with pull-up
+ /// \constant STD_PD - set the pin to standard mode with pull-down
+ /// \constant OD - set the pin to open drain mode without pull-up or pull-down
+ /// \constant OD_PU - set the pin to open drain mode with pull-up
+ /// \constant OD_PD - set the pin to open drain mode with pull-down
+ /// \constant 2MA - set the drive strength to 2ma
+ /// \constant 4MA - set the drive strength to 4ma
+ /// \constant 6MA - set the drive strength to 6ma
+ { MP_OBJ_NEW_QSTR(MP_QSTR_IN), MP_OBJ_NEW_SMALL_INT(GPIO_DIR_MODE_IN) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_OUT), MP_OBJ_NEW_SMALL_INT(GPIO_DIR_MODE_OUT) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_STD), MP_OBJ_NEW_SMALL_INT(PIN_TYPE_STD) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_STD_PU), MP_OBJ_NEW_SMALL_INT(PIN_TYPE_STD_PU) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_STD_PD), MP_OBJ_NEW_SMALL_INT(PIN_TYPE_STD_PD) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_OD), MP_OBJ_NEW_SMALL_INT(PIN_TYPE_OD) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_OD_PU), MP_OBJ_NEW_SMALL_INT(PIN_TYPE_OD_PU) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_OD_PD), MP_OBJ_NEW_SMALL_INT(PIN_TYPE_OD_PD) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_S2MA), MP_OBJ_NEW_SMALL_INT(PIN_STRENGTH_2MA) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_S4MA), MP_OBJ_NEW_SMALL_INT(PIN_STRENGTH_4MA) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_S6MA), MP_OBJ_NEW_SMALL_INT(PIN_STRENGTH_6MA) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(gpio_locals_dict, gpio_locals_dict_table);
+
+const mp_obj_type_t gpio_type = {
+ { &mp_type_type },
+ .name = MP_QSTR_GPIO,
+ .print = gpio_print,
+ .make_new = gpio_make_new,
+ .locals_dict = (mp_obj_t)&gpio_locals_dict,
+};
diff --git a/cc3200/mods/pybgpio.h b/cc3200/mods/pybgpio.h
new file mode 100644
index 0000000000..08a495803e
--- /dev/null
+++ b/cc3200/mods/pybgpio.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// This file requires pin_defs_xxx.h (which has port specific enums and
+// defines, so we include it here. It should never be included directly
+
+#include MICROPY_PIN_DEFS_PORT_H
+
+typedef struct {
+ mp_obj_base_t base;
+ qstr name;
+ uint32_t port;
+ uint32_t bit : 8;
+ uint32_t pin_num : 7;
+} gpio_obj_t;
+
+extern const mp_obj_type_t gpio_type;
+
+typedef struct {
+ const char *name;
+ const gpio_obj_t *gpio;
+} gpio_named_pin_t;
+
+extern const gpio_named_pin_t gpio_cpu_pins[];
+
+typedef struct {
+ mp_obj_base_t base;
+ qstr name;
+ const gpio_named_pin_t *named_pins;
+} gpio_named_pins_obj_t;
+
+extern const mp_obj_type_t gpio_cpu_pins_obj_type;
+extern const mp_obj_dict_t gpio_cpu_pins_locals_dict;
+
+MP_DECLARE_CONST_FUN_OBJ(gpio_init_obj);
+
+void gpio_init0(void);
+void gpio_config(const gpio_obj_t *self, uint af, uint mode, uint type, uint strength);
+const gpio_obj_t *gpio_find(mp_obj_t user_obj);
+const gpio_obj_t *gpio_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name);
+uint32_t gpio_get_mode(const gpio_obj_t *self);
+uint32_t gpio_get_type(const gpio_obj_t *self);
+uint32_t gpio_get_strenght(const gpio_obj_t *self);
+
diff --git a/cc3200/mods/pybrtc.c b/cc3200/mods/pybrtc.c
new file mode 100644
index 0000000000..8d43830680
--- /dev/null
+++ b/cc3200/mods/pybrtc.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "runtime.h"
+#include "modutime.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "pybrtc.h"
+
+/// \moduleref pyb
+/// \class RTC - real time clock
+///
+/// The RTC is and independent clock that keeps track of the date
+/// and time.
+///
+/// Example usage:
+///
+/// rtc = pyb.RTC()
+/// rtc.datetime((2014, 5, 1, 4, 13, 0, 0, 0))
+/// print(rtc.datetime())
+
+void pybrtc_init(void) {
+ // if RTC was previously set leave it alone
+ if (MAP_PRCMSysResetCauseGet() == PRCM_POWER_ON) {
+ // fresh reset; configure RTC Calendar
+ // set the date to 1st Jan 2015
+ // set the time to 00:00:00
+ uint32_t seconds = mod_time_seconds_since_2000(2015, 1, 1, 0, 0, 0);
+
+ MAP_PRCMRTCSet(seconds, 0);
+
+ // Mark that the RTC is in use
+ MAP_PRCMRTCInUseSet();
+ }
+}
+
+/******************************************************************************/
+// Micro Python bindings
+
+typedef struct _pyb_rtc_obj_t {
+ mp_obj_base_t base;
+} pyb_rtc_obj_t;
+
+STATIC const pyb_rtc_obj_t pyb_rtc_obj = {{&pyb_rtc_type}};
+
+/// \classmethod \constructor()
+/// Create an RTC object.
+STATIC mp_obj_t pyb_rtc_make_new(mp_obj_t type_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+ // check arguments
+ mp_arg_check_num(n_args, n_kw, 0, 0, false);
+
+ // return constant object
+ return (mp_obj_t)&pyb_rtc_obj;
+}
+
+/// \method datetime([datetimetuple])
+/// Get or set the date and time of the RTC.
+///
+/// With no arguments, this method returns an 8-tuple with the current
+/// date and time. With 1 argument (being an 8-tuple) it sets the date
+/// and time.
+///
+/// The 8-tuple has the following format:
+///
+/// (year, month, day, weekday, hours, minutes, seconds, milliseconds)
+///
+/// `weekday` is 1-7 for Monday through Sunday.
+///
+mp_obj_t pyb_rtc_datetime(mp_uint_t n_args, const mp_obj_t *args) {
+ mod_struct_time tm;
+ uint32_t seconds;
+ uint16_t mseconds;
+
+ if (n_args == 1) {
+ // get the seconds and the milliseconds from the RTC
+ MAP_PRCMRTCGet(&seconds, &mseconds);
+ mseconds = RTC_CYCLES_U16MS(mseconds);
+ mod_time_seconds_since_2000_to_struct_time(seconds, &tm);
+
+ mp_obj_t tuple[8] = {
+ mp_obj_new_int(tm.tm_year),
+ mp_obj_new_int(tm.tm_mon),
+ mp_obj_new_int(tm.tm_mday),
+ mp_obj_new_int(tm.tm_wday),
+ mp_obj_new_int(tm.tm_hour),
+ mp_obj_new_int(tm.tm_min),
+ mp_obj_new_int(tm.tm_sec),
+ mp_obj_new_int(mseconds)
+ };
+ return mp_obj_new_tuple(8, tuple);
+ } else {
+ // set date and time
+ mp_obj_t *items;
+ mp_obj_get_array_fixed_n(args[1], 8, &items);
+
+ tm.tm_year = mp_obj_get_int(items[0]);
+ tm.tm_mon = mp_obj_get_int(items[1]);
+ tm.tm_mday = mp_obj_get_int(items[2]);
+ // Skip the weekday
+ tm.tm_hour = mp_obj_get_int(items[4]);
+ tm.tm_min = mp_obj_get_int(items[5]);
+ tm.tm_sec = mp_obj_get_int(items[6]);
+ mseconds = mp_obj_get_int(items[7]);
+
+ seconds = mod_time_seconds_since_2000(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
+ mseconds = RTC_U16MS_CYCLES(mseconds);
+ MAP_PRCMRTCSet(seconds, mseconds);
+
+ return mp_const_none;
+ }
+}
+MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_datetime_obj, 1, 2, pyb_rtc_datetime);
+
+STATIC const mp_map_elem_t pyb_rtc_locals_dict_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR_datetime), (mp_obj_t)&pyb_rtc_datetime_obj },
+};
+STATIC MP_DEFINE_CONST_DICT(pyb_rtc_locals_dict, pyb_rtc_locals_dict_table);
+
+const mp_obj_type_t pyb_rtc_type = {
+ { &mp_type_type },
+ .name = MP_QSTR_RTC,
+ .make_new = pyb_rtc_make_new,
+ .locals_dict = (mp_obj_t)&pyb_rtc_locals_dict,
+};
diff --git a/cc3200/mods/pybrtc.h b/cc3200/mods/pybrtc.h
new file mode 100644
index 0000000000..abe38cc380
--- /dev/null
+++ b/cc3200/mods/pybrtc.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#define RTC_U16MS_CYCLES(msec) ((msec * 1024) / 1000)
+#define RTC_CYCLES_U16MS(cycles) ((cycles * 1000) / 1024)
+
+extern const mp_obj_type_t pyb_rtc_type;
+
+void pybrtc_init(void);
diff --git a/cc3200/mods/pybstdio.c b/cc3200/mods/pybstdio.c
new file mode 100644
index 0000000000..2d6a1c07ba
--- /dev/null
+++ b/cc3200/mods/pybstdio.c
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "py/mpstate.h"
+#include "mpconfig.h"
+#include "misc.h"
+#include "qstr.h"
+#include "misc.h"
+#include "obj.h"
+#include "stream.h"
+#include MICROPY_HAL_H
+#include "pybuart.h"
+#include "telnet.h"
+#include "pybstdio.h"
+
+// TODO make stdin, stdout and stderr writable objects so they can
+// be changed by Python code. This requires some changes, as these
+// objects are in a read-only module (py/modsys.c).
+
+void stdout_tx_str(const char *str) {
+ stdout_tx_strn(str, strlen(str));
+}
+
+void stdout_tx_strn(const char *str, mp_uint_t len) {
+ if (MP_STATE_PORT(pyb_stdio_uart) != NULL) {
+ uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len);
+ }
+ // and also to telnet
+ if (telnet_is_active()) {
+ telnet_tx_strn(str, len);
+ }
+}
+
+void stdout_tx_strn_cooked(const char *str, mp_uint_t len) {
+ // send stdout to UART
+ if (MP_STATE_PORT(pyb_stdio_uart) != NULL) {
+ uart_tx_strn_cooked(MP_STATE_PORT(pyb_stdio_uart), str, len);
+ }
+ // and also to telnet
+ if (telnet_is_active()) {
+ telnet_tx_strn_cooked(str, len);
+ }
+}
+
+int stdin_rx_chr(void) {
+ for ( ;; ) {
+ if (telnet_rx_any()) {
+ return telnet_rx_char();
+ }
+ else if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) {
+ return uart_rx_char(MP_STATE_PORT(pyb_stdio_uart));
+ }
+ HAL_Delay(1);
+ }
+}
+
+/******************************************************************************/
+// Micro Python bindings
+
+#define STDIO_FD_IN (0)
+#define STDIO_FD_OUT (1)
+#define STDIO_FD_ERR (2)
+
+typedef struct _pyb_stdio_obj_t {
+ mp_obj_base_t base;
+ int fd;
+} pyb_stdio_obj_t;
+
+void stdio_obj_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) {
+ pyb_stdio_obj_t *self = self_in;
+ print(env, "", self->fd);
+}
+
+STATIC mp_uint_t stdio_read(mp_obj_t self_in, void *buf, mp_uint_t size, int *errcode) {
+ pyb_stdio_obj_t *self = self_in;
+ if (self->fd == STDIO_FD_IN) {
+ for (uint i = 0; i < size; i++) {
+ int c = stdin_rx_chr();
+ if (c == '\r') {
+ c = '\n';
+ }
+ ((byte*)buf)[i] = c;
+ }
+ return size;
+ } else {
+ *errcode = EPERM;
+ return MP_STREAM_ERROR;
+ }
+}
+
+STATIC mp_uint_t stdio_write(mp_obj_t self_in, const void *buf, mp_uint_t size, int *errcode) {
+ pyb_stdio_obj_t *self = self_in;
+ if (self->fd == STDIO_FD_OUT || self->fd == STDIO_FD_ERR) {
+ stdout_tx_strn_cooked(buf, size);
+ return size;
+ } else {
+ *errcode = EPERM;
+ return MP_STREAM_ERROR;
+ }
+}
+
+mp_obj_t stdio_obj___exit__(mp_uint_t n_args, const mp_obj_t *args) {
+ return mp_const_none;
+}
+static MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(stdio_obj___exit___obj, 4, 4, stdio_obj___exit__);
+
+// TODO gc hook to close the file if not already closed
+
+STATIC const mp_map_elem_t stdio_locals_dict_table[] = {
+ { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_stream_read_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_readall), (mp_obj_t)&mp_stream_readall_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_readline), (mp_obj_t)&mp_stream_unbuffered_readline_obj},
+ { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)&mp_stream_write_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_close), (mp_obj_t)&mp_identity_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR___del__), (mp_obj_t)&mp_identity_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR___enter__), (mp_obj_t)&mp_identity_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR___exit__), (mp_obj_t)&stdio_obj___exit___obj },
+};
+
+STATIC MP_DEFINE_CONST_DICT(stdio_locals_dict, stdio_locals_dict_table);
+
+STATIC const mp_stream_p_t stdio_obj_stream_p = {
+ .read = stdio_read,
+ .write = stdio_write,
+ .is_text = true,
+};
+
+STATIC const mp_obj_type_t stdio_obj_type = {
+ { &mp_type_type },
+ .name = MP_QSTR_FileIO,
+ // TODO .make_new?
+ .print = stdio_obj_print,
+ .getiter = mp_identity,
+ .iternext = mp_stream_unbuffered_iter,
+ .stream_p = &stdio_obj_stream_p,
+ .locals_dict = (mp_obj_t)&stdio_locals_dict,
+};
+
+/// \moduleref sys
+/// \constant stdin - standard input (connected to UART0, or to telnet, configurable)
+/// \constant stdout - standard output (connected to UART0, and optionally to telnet)
+/// \constant stderr - standard error (connected to UART0, and optionally to telnet)
+const pyb_stdio_obj_t mp_sys_stdin_obj = {{&stdio_obj_type}, .fd = STDIO_FD_IN};
+const pyb_stdio_obj_t mp_sys_stdout_obj = {{&stdio_obj_type}, .fd = STDIO_FD_OUT};
+const pyb_stdio_obj_t mp_sys_stderr_obj = {{&stdio_obj_type}, .fd = STDIO_FD_ERR};
diff --git a/cc3200/mods/pybstdio.h b/cc3200/mods/pybstdio.h
new file mode 100644
index 0000000000..f987e8bc4a
--- /dev/null
+++ b/cc3200/mods/pybstdio.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+void stdout_tx_str(const char *str);
+void stdout_tx_strn(const char *str, mp_uint_t len);
+void stdout_tx_strn_cooked(const char *str, mp_uint_t len);
+int stdin_rx_chr(void);
diff --git a/cc3200/mods/pybsystick.c b/cc3200/mods/pybsystick.c
new file mode 100644
index 0000000000..e934ab7dd4
--- /dev/null
+++ b/cc3200/mods/pybsystick.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "irq.h"
+#include "pybsystick.h"
+#include "systick.h"
+#include "inc/hw_types.h"
+#include "inc/hw_nvic.h"
+
+#ifdef USE_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#endif
+
+
+bool sys_tick_has_passed(uint32_t start_tick, uint32_t delay_ms) {
+ return HAL_GetTick() - start_tick >= delay_ms;
+}
+
+// waits until at least delay_ms milliseconds have passed from the sampling of
+// startTick. Handles overflow properly. Assumes stc was taken from
+// HAL_GetTick() some time before calling this function.
+void sys_tick_wait_at_least(uint32_t start_tick, uint32_t delay_ms) {
+#ifdef USE_FREERTOS
+ vTaskDelay (delay_ms / portTICK_PERIOD_MS);
+#else
+ while (!sys_tick_has_passed(start_tick, delay_ms)) {
+ __WFI(); // enter sleep mode, waiting for interrupt
+ }
+#endif
+}
+
+// The SysTick timer counts down at HAL_FCPU_HZ, so we can use that knowledge
+// to grab a microsecond counter.
+//
+// We assume that HAL_GetTick returns milliseconds.
+uint32_t sys_tick_get_microseconds(void) {
+ mp_uint_t irq_state = disable_irq();
+ uint32_t counter = SysTickValueGet();
+ uint32_t milliseconds = HAL_GetTick();
+ uint32_t status = (HWREG(NVIC_ST_CTRL));
+ enable_irq(irq_state);
+
+ // It's still possible for the countflag bit to get set if the counter was
+ // reloaded between reading VAL and reading CTRL. With interrupts disabled
+ // it definitely takes less than 50 HCLK cycles between reading VAL and
+ // reading CTRL, so the test (counter > 50) is to cover the case where VAL
+ // is +ve and very close to zero, and the COUNTFLAG bit is also set.
+ if ((status & NVIC_ST_CTRL_COUNT) && counter > 50) {
+ // This means that the HW reloaded VAL between the time we read VAL and the
+ // time we read CTRL, which implies that there is an interrupt pending
+ // to increment the tick counter.
+ milliseconds++;
+ }
+ uint32_t load = (HWREG(NVIC_ST_RELOAD));
+ counter = load - counter; // Convert from decrementing to incrementing
+
+ // ((load + 1) / 1000) is the number of counts per microsecond.
+ //
+ // counter / ((load + 1) / 1000) scales from the systick clock to microseconds
+ // and is the same thing as (counter * 1000) / (load + 1)
+ return milliseconds * 1000 + (counter * 1000) / (load + 1);
+}
diff --git a/cc3200/mods/pybsystick.h b/cc3200/mods/pybsystick.h
new file mode 100644
index 0000000000..abc61939b3
--- /dev/null
+++ b/cc3200/mods/pybsystick.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+void sys_tick_wait_at_least(uint32_t stc, uint32_t delay_ms);
+bool sys_tick_has_passed(uint32_t stc, uint32_t delay_ms);
+uint32_t sys_tick_get_microseconds(void);
diff --git a/cc3200/mods/pybuart.c b/cc3200/mods/pybuart.c
new file mode 100644
index 0000000000..8fad7eaa48
--- /dev/null
+++ b/cc3200/mods/pybuart.c
@@ -0,0 +1,682 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "py/mpstate.h"
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "runtime.h"
+#include "stream.h"
+#include "inc/hw_types.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_uart.h"
+#include "rom_map.h"
+#include "interrupt.h"
+#include "prcm.h"
+#include "gpio.h"
+#include "uart.h"
+#include "pin.h"
+#include "pybuart.h"
+#include "pybgpio.h"
+#include "pybioctl.h"
+#include "pybstdio.h"
+#include "mpexception.h"
+#include "osi.h"
+
+
+/// \moduleref pyb
+/// \class UART - duplex serial communication bus
+///
+/// UART implements the standard UART/USART duplex serial communications protocol. At
+/// the physical level it consists of 2 lines: RX and TX.
+///
+/// UART objects can be created and initialised using:
+///
+/// from pyb import UART
+///
+/// uart = UART(1, 9600) # init with given baudrate
+/// uart.init(9600, bits=8, stop=1, parity=None) # init with given parameters
+///
+/// Bits can be 5, 6, 7, 8, parity can be None, 0 (even), 1 (odd). Stop can be 1 or 2.
+///
+/// A UART object acts like a stream object and reading and writing is done
+/// using the standard stream methods:
+///
+/// uart.read(10) # read 10 characters, returns a bytes object
+/// uart.readall() # read all available characters
+/// uart.readline() # read a line
+/// uart.readinto(buf) # read and store into the given buffer
+/// uart.write('abc') # write the 3 characters
+///
+/// Individual characters can be read/written using:
+///
+/// uart.readchar() # read 1 character and returns it as an integer
+/// uart.writechar(42) # write 1 character
+///
+/// To check if there is anything to be read, use:
+///
+/// uart.any() # returns True if any characters waiting
+
+
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+STATIC void UARTGenericIntHandler(uint32_t uart_id);
+STATIC void UART0IntHandler(void);
+STATIC void UART1IntHandler(void);
+STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in);
+
+/******************************************************************************
+ DEFINE PRIVATE TYPES
+ ******************************************************************************/
+
+struct _pyb_uart_obj_t {
+ mp_obj_base_t base;
+ pyb_uart_t uart_id;
+ uint reg;
+ uint baudrate;
+ uint config;
+ uint flowcontrol;
+ byte *read_buf; // read buffer pointer
+ uint16_t timeout; // timeout waiting for first char
+ uint16_t timeout_char; // timeout waiting between chars
+ uint16_t read_buf_len; // len in chars; buf can hold len-1 chars
+ volatile uint16_t read_buf_head; // indexes first empty slot
+ uint16_t read_buf_tail; // indexes first full slot (not full if equals head)
+ bool enabled;
+};
+
+#define PYBUART_TX_WAIT_MS 1
+#define PYBUART_TX_MAX_TIMEOUT_MS 5
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+void uart_init0 (void) {
+ for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) {
+ MP_STATE_PORT(pyb_uart_obj_all)[i] = NULL;
+ }
+}
+
+// unregister all interrupt sources
+void uart_deinit(void) {
+ for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) {
+ pyb_uart_obj_t *self = MP_STATE_PORT(pyb_uart_obj_all)[i];
+ if (self != NULL) {
+ pyb_uart_deinit(self);
+ }
+ }
+}
+
+// assumes Init parameters have been set up correctly
+bool uart_init2(pyb_uart_obj_t *self) {
+ uint uartPerh;
+
+ switch (self->uart_id) {
+ case PYB_UART_1:
+ self->reg = UARTA0_BASE;
+ uartPerh = PRCM_UARTA0;
+ MAP_PinTypeUART(PIN_55, PIN_MODE_3);
+ MAP_PinTypeUART(PIN_57, PIN_MODE_3);
+ MAP_UARTIntRegister(UARTA0_BASE, UART0IntHandler);
+ MAP_IntPrioritySet(INT_UARTA0, INT_PRIORITY_LVL_7);
+ break;
+ case PYB_UART_2:
+ self->reg = UARTA1_BASE;
+ uartPerh = PRCM_UARTA1;
+ MAP_PinTypeUART(PIN_58, PIN_MODE_6);
+ MAP_PinTypeUART(PIN_59, PIN_MODE_6);
+ MAP_UARTIntRegister(UARTA1_BASE, UART1IntHandler);
+ MAP_IntPrioritySet(INT_UARTA1, INT_PRIORITY_LVL_7);
+ break;
+ default:
+ return false;
+ }
+
+ // Enable the peripheral clock
+ MAP_PRCMPeripheralClkEnable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+
+ // Reset the uart
+ MAP_PRCMPeripheralReset(uartPerh);
+
+ // Initialize the UART
+ MAP_UARTConfigSetExpClk(self->reg, MAP_PRCMPeripheralClockGet(uartPerh),
+ self->baudrate, self->config);
+
+ // Enbale the FIFO
+ MAP_UARTFIFOEnable(self->reg);
+
+ // Configure the FIFO interrupt levels
+ MAP_UARTFIFOLevelSet(self->reg, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
+
+ // Configure the flow control mode
+ UARTFlowControlSet(self->reg, self->flowcontrol);
+
+ // Enable the RX and RX timeout interrupts
+ MAP_UARTIntEnable(self->reg, UART_INT_RX | UART_INT_RT);
+
+ self->enabled = true;
+
+ return true;
+}
+
+bool uart_init(pyb_uart_obj_t *self, uint baudrate) {
+ self->baudrate = baudrate;
+ self->config = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE;
+ self->flowcontrol = UART_FLOWCONTROL_NONE;
+ return uart_init2(self);
+}
+
+bool uart_rx_any(pyb_uart_obj_t *self) {
+ return (self->read_buf_tail != self->read_buf_head || MAP_UARTCharsAvail(self->reg));
+}
+
+// Waits at most timeout milliseconds for at least 1 char to become ready for
+// reading (from buf or for direct reading).
+// Returns true if something available, false if not.
+STATIC bool uart_rx_wait(pyb_uart_obj_t *self, uint32_t timeout) {
+ for (;;) {
+ if (uart_rx_any(self)) {
+ return true; // have at least 1 char ready for reading
+ }
+ if (timeout > 0) {
+ HAL_Delay (1);
+ timeout--;
+ }
+ else {
+ return false;
+ }
+ }
+}
+
+int uart_rx_char(pyb_uart_obj_t *self) {
+ if (self->read_buf_tail != self->read_buf_head) {
+ // buffering via IRQ
+ int data = self->read_buf[self->read_buf_tail];
+ self->read_buf_tail = (self->read_buf_tail + 1) % self->read_buf_len;
+ return data;
+ } else {
+ // no buffering
+ return MAP_UARTCharGetNonBlocking(self->reg);
+ }
+}
+
+bool uart_tx_char(pyb_uart_obj_t *self, int c) {
+ uint32_t timeout = 0;
+
+ while (!MAP_UARTCharPutNonBlocking(self->reg, c)) {
+ if (timeout++ > (PYBUART_TX_MAX_TIMEOUT_MS / PYBUART_TX_WAIT_MS)) {
+ return false;
+ }
+ HAL_Delay (PYBUART_TX_WAIT_MS);
+ }
+ return true;
+}
+
+bool uart_tx_strn(pyb_uart_obj_t *self, const char *str, uint len) {
+ for (const char *top = str + len; str < top; str++) {
+ if (!uart_tx_char(self, *str)) {
+ return false;
+ }
+ }
+ return true;
+}
+
+void uart_tx_strn_cooked(pyb_uart_obj_t *self, const char *str, uint len) {
+ for (const char *top = str + len; str < top; str++) {
+ if (*str == '\n') {
+ uart_tx_char(self, '\r');
+ }
+ uart_tx_char(self, *str);
+ }
+}
+
+/******************************************************************************
+ DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
+
+STATIC void UARTGenericIntHandler(uint32_t uart_id) {
+ pyb_uart_obj_t *self = MP_STATE_PORT(pyb_uart_obj_all)[uart_id];
+ uint32_t status;
+
+ if (self == NULL) {
+ // UART object has not been set, so we can't do anything, not
+ // even disable the IRQ. This should never happen.
+ return;
+ }
+
+ status = MAP_UARTIntStatus(self->reg, true);
+
+ // Receive interrupt
+ if (status & (UART_INT_RX | UART_INT_RT)) {
+ MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
+ while (UARTCharsAvail(self->reg)) {
+ int data = MAP_UARTCharGetNonBlocking(self->reg);
+ if (MICROPY_STDIO_UART == self->uart_id && data == user_interrupt_char) {
+ // raise exception when interrupts are finished
+ mpexception_keyboard_nlr_jump();
+ }
+ else if (self->read_buf_len != 0) {
+ uint16_t next_head = (self->read_buf_head + 1) % self->read_buf_len;
+ if (next_head != self->read_buf_tail) {
+ // only store data if room in buf
+ self->read_buf[self->read_buf_head] = data;
+ self->read_buf_head = next_head;
+ }
+ }
+ }
+ }
+}
+
+STATIC void UART0IntHandler(void) {
+ UARTGenericIntHandler(0);
+}
+
+STATIC void UART1IntHandler(void) {
+ UARTGenericIntHandler(1);
+}
+
+/******************************************************************************/
+/* Micro Python bindings */
+
+STATIC void pyb_uart_print(void (*print)(void *env, const char *fmt, ...), void *env, mp_obj_t self_in, mp_print_kind_t kind) {
+ pyb_uart_obj_t *self = self_in;
+ if (!self->enabled) {
+ print(env, "UART(%u)", self->uart_id);
+ } else {
+ print(env, "UART(%u, baudrate=%u, bits=", self->uart_id, self->baudrate);
+ switch (self->config & UART_CONFIG_WLEN_MASK) {
+ case UART_CONFIG_WLEN_5:
+ print(env, "5");
+ break;
+ case UART_CONFIG_WLEN_6:
+ print(env, "6");
+ break;
+ case UART_CONFIG_WLEN_7:
+ print(env, "7");
+ break;
+ case UART_CONFIG_WLEN_8:
+ print(env, "8");
+ break;
+ default:
+ break;
+ }
+ if ((self->config & UART_CONFIG_PAR_MASK) == UART_CONFIG_PAR_NONE) {
+ print(env, ", parity=None");
+ } else {
+ print(env, ", parity=%u", (self->config & UART_CONFIG_PAR_MASK) == UART_CONFIG_PAR_EVEN ? 0 : 1);
+ }
+ print(env, ", stop=%u, timeout=%u, timeout_char=%u, read_buf_len=%u)",
+ (self->config & UART_CONFIG_STOP_MASK) == UART_CONFIG_STOP_ONE ? 1 : 2,
+ self->timeout, self->timeout_char, self->read_buf_len);
+ }
+}
+
+/// \method init(baudrate, bits=8, parity=None, stop=1, *, timeout=1000, timeout_char=0, read_buf_len=64)
+///
+/// Initialise the UART bus with the given parameters:
+///
+/// - `baudrate` is the clock rate.
+/// - `bits` is the number of bits per byte, 7, 8 or 9.
+/// - `parity` is the parity, `None`, 0 (even) or 1 (odd).
+/// - `stop` is the number of stop bits, 1 or 2.
+/// - `flowcontrol` is the flow control mode, `None`, `UART.FLOW_TX`,
+/// `UART.FLOW_RX', 'UART.FLOW_TXRX`.
+/// - `timeout` is the timeout in milliseconds to wait for the first character.
+/// - `timeout_char` is the timeout in milliseconds to wait between characters.
+/// - `read_buf_len` is the character length of the read buffer (0 to disable).
+STATIC const mp_arg_t pyb_uart_init_args[] = {
+ { MP_QSTR_baudrate, MP_ARG_REQUIRED | MP_ARG_INT, },
+ { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} },
+ { MP_QSTR_parity, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = mp_const_none} },
+ { MP_QSTR_stop, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} },
+ { MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_int = UART_FLOWCONTROL_NONE} },
+ { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} },
+ { MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} },
+ { MP_QSTR_read_buf_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 64} },
+};
+
+STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
+ bool success;
+
+ // parse args
+ mp_arg_val_t args[MP_ARRAY_SIZE(pyb_uart_init_args)];
+ mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(pyb_uart_init_args), pyb_uart_init_args, args);
+
+ // set the UART configuration values
+ if (n_args > 1) {
+ self->baudrate = args[0].u_int;
+ switch (args[1].u_int) {
+ case 5:
+ self->config = UART_CONFIG_WLEN_5;
+ break;
+ case 6:
+ self->config = UART_CONFIG_WLEN_6;
+ break;
+ case 7:
+ self->config = UART_CONFIG_WLEN_7;
+ break;
+ case 8:
+ self->config = UART_CONFIG_WLEN_8;
+ break;
+ default:
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_ValueError, mpexception_value_invalid_arguments));
+ break;
+ }
+ // Parity
+ if (args[2].u_obj == mp_const_none) {
+ self->config |= UART_CONFIG_PAR_NONE;
+ } else {
+ self->config |= ((mp_obj_get_int(args[2].u_obj) & 1) ? UART_CONFIG_PAR_ODD : UART_CONFIG_PAR_EVEN);
+ }
+ // Stop bits
+ self->config |= (args[3].u_int == 1 ? UART_CONFIG_STOP_ONE : UART_CONFIG_STOP_TWO);
+
+ // Flow control
+ self->flowcontrol = args[4].u_int;
+ success = uart_init2(self);
+ } else {
+ success = uart_init(self, args[0].u_int);
+ }
+
+ // init UART (if it fails, something weird happened)
+ if (!success) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_operation_failed));
+ }
+
+ // set timeouts
+ self->timeout = args[5].u_int;
+ self->timeout_char = args[6].u_int;
+
+ // setup the read buffer
+ m_del(byte, self->read_buf, self->read_buf_len);
+ self->read_buf_head = 0;
+ self->read_buf_tail = 0;
+
+ if (args[7].u_int <= 0) {
+ // no read buffer
+ self->read_buf_len = 0;
+ self->read_buf = NULL;
+ MAP_UARTIntDisable(self->reg, UART_INT_RX | UART_INT_RT);
+ } else {
+ // read buffer using interrupts
+ self->read_buf_len = args[7].u_int;
+ self->read_buf = m_new(byte, args[7].u_int);
+ }
+
+ return mp_const_none;
+}
+
+/// \classmethod \constructor(bus, ...)
+///
+/// Construct a UART object on the given bus. `bus` can be 1-2
+/// With no additional parameters, the UART object is created but not
+/// initialised (it has the settings from the last initialisation of
+/// the bus, if any).
+/// When only the baud rate is given the UART object is created and
+/// initialized with the default configuration of: 8 bit transfers,
+/// 1 stop bit, no parity and flow control disabled.
+/// See `init` for parameters of initialisation.
+/// If extra arguments are given, the bus is initialised with these arguments
+/// See `init` for parameters of initialisation.
+///
+STATIC mp_obj_t pyb_uart_make_new(mp_obj_t type_in, mp_uint_t n_args, mp_uint_t n_kw, const mp_obj_t *args) {
+ // check arguments
+ mp_arg_check_num(n_args, n_kw, 1, MP_ARRAY_SIZE(pyb_uart_init_args), true);
+
+ // work out port
+ pyb_uart_t uart_id = mp_obj_get_int(args[0]);
+
+ if (uart_id < PYB_UART_1 || uart_id > MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all))) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, mpexception_os_resource_not_avaliable));
+ }
+
+ // create object
+ pyb_uart_obj_t *self;
+ if (MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] == NULL) {
+ // create new UART object
+ self = m_new0(pyb_uart_obj_t, 1);
+ self->base.type = &pyb_uart_type;
+ self->uart_id = uart_id;
+ self->enabled = false;
+ MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1] = self;
+ } else {
+ // reference existing UART object
+ self = MP_STATE_PORT(pyb_uart_obj_all)[uart_id - 1];
+ }
+
+ if (n_args > 1 || n_kw > 0) {
+ // start the peripheral
+ mp_map_t kw_args;
+ mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
+ pyb_uart_init_helper(self, n_args - 1, args + 1, &kw_args);
+ } else if (!self->enabled) {
+ nlr_raise(mp_obj_new_exception_msg(&mp_type_TypeError, mpexception_num_type_invalid_arguments));
+ }
+
+ return self;
+}
+
+STATIC mp_obj_t pyb_uart_init(mp_uint_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
+ return pyb_uart_init_helper(args[0], n_args - 1, args + 1, kw_args);
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_uart_init_obj, 1, pyb_uart_init);
+
+/// \method deinit()
+/// Turn off the UART bus.
+STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) {
+ pyb_uart_obj_t *self = self_in;
+ uint uartPerh;
+
+ switch (self->uart_id) {
+
+ case PYB_UART_1:
+ uartPerh = PRCM_UARTA0;
+ break;
+
+ case PYB_UART_2:
+ uartPerh = PRCM_UARTA1;
+ break;
+
+ default:
+ return mp_const_none;
+ }
+
+ self->enabled = false;
+ MAP_UARTIntDisable(self->reg, UART_INT_RX | UART_INT_RT);
+ MAP_UARTIntClear(self->reg, UART_INT_RX | UART_INT_RT);
+ MAP_UARTIntUnregister(self->reg);
+ MAP_UARTDisable(self->reg);
+ MAP_PRCMPeripheralClkDisable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_deinit_obj, pyb_uart_deinit);
+
+/// \method any()
+/// Return `True` if any characters waiting, else `False`.
+STATIC mp_obj_t pyb_uart_any(mp_obj_t self_in) {
+ pyb_uart_obj_t *self = self_in;
+ if (uart_rx_any(self)) {
+ return mp_const_true;
+ } else {
+ return mp_const_false;
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_any_obj, pyb_uart_any);
+
+/// \method writechar(char)
+/// Write a single character on the bus. `char` is an integer to write.
+/// Return value: `None`.
+STATIC mp_obj_t pyb_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) {
+ pyb_uart_obj_t *self = self_in;
+
+ // get the character to write
+ uint8_t data = mp_obj_get_int(char_in);
+
+ // send the character
+ if (!uart_tx_char(self, data)) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(ETIMEDOUT)));
+ }
+
+ return mp_const_none;
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_uart_writechar_obj, pyb_uart_writechar);
+
+/// \method readchar()
+/// Receive a single character on the bus.
+/// Return value: The character read, as an integer. Returns -1 on timeout.
+STATIC mp_obj_t pyb_uart_readchar(mp_obj_t self_in) {
+ pyb_uart_obj_t *self = self_in;
+ if (uart_rx_wait(self, self->timeout)) {
+ return mp_obj_new_int(uart_rx_char(self));
+ } else {
+ // return -1 on timeout
+ return MP_OBJ_NEW_SMALL_INT(-1);
+ }
+}
+STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_readchar_obj, pyb_uart_readchar);
+
+STATIC const mp_map_elem_t pyb_uart_locals_dict_table[] = {
+ // instance methods
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_init), (mp_obj_t)&pyb_uart_init_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_deinit), (mp_obj_t)&pyb_uart_deinit_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_any), (mp_obj_t)&pyb_uart_any_obj },
+
+ /// \method read([nbytes])
+ { MP_OBJ_NEW_QSTR(MP_QSTR_read), (mp_obj_t)&mp_stream_read_obj },
+ /// \method readall()
+ { MP_OBJ_NEW_QSTR(MP_QSTR_readall), (mp_obj_t)&mp_stream_readall_obj },
+ /// \method readline()
+ { MP_OBJ_NEW_QSTR(MP_QSTR_readline), (mp_obj_t)&mp_stream_unbuffered_readline_obj},
+ /// \method readinto(buf[, nbytes])
+ { MP_OBJ_NEW_QSTR(MP_QSTR_readinto), (mp_obj_t)&mp_stream_readinto_obj },
+ /// \method write(buf)
+ { MP_OBJ_NEW_QSTR(MP_QSTR_write), (mp_obj_t)&mp_stream_write_obj },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_writechar), (mp_obj_t)&pyb_uart_writechar_obj },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_readchar), (mp_obj_t)&pyb_uart_readchar_obj },
+
+ // class constants
+ { MP_OBJ_NEW_QSTR(MP_QSTR_UART1), MP_OBJ_NEW_SMALL_INT(PYB_UART_1) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_UART2), MP_OBJ_NEW_SMALL_INT(PYB_UART_2) },
+
+ { MP_OBJ_NEW_QSTR(MP_QSTR_FLOW_NONE), MP_OBJ_NEW_SMALL_INT(UART_FLOWCONTROL_NONE) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_FLOW_TX), MP_OBJ_NEW_SMALL_INT(UART_FLOWCONTROL_TX) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_FLOW_RX), MP_OBJ_NEW_SMALL_INT(UART_FLOWCONTROL_RX) },
+ { MP_OBJ_NEW_QSTR(MP_QSTR_FLOW_TXRX), MP_OBJ_NEW_SMALL_INT(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX) },
+};
+
+STATIC MP_DEFINE_CONST_DICT(pyb_uart_locals_dict, pyb_uart_locals_dict_table);
+
+STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) {
+ pyb_uart_obj_t *self = self_in;
+ byte *buf = buf_in;
+
+ // make sure we want at least 1 char
+ if (size == 0) {
+ return 0;
+ }
+
+ // wait for first char to become available
+ if (!uart_rx_wait(self, self->timeout)) {
+ // we can either return 0 to indicate EOF (then read() method returns b'')
+ // or return EAGAIN error to indicate non-blocking (then read() method returns None)
+ return 0;
+ }
+
+ // read the data
+ byte *orig_buf = buf;
+ for (;;) {
+ *buf++ = uart_rx_char(self);
+ if (--size == 0 || !uart_rx_wait(self, self->timeout_char)) {
+ // return number of bytes read
+ return buf - orig_buf;
+ }
+ }
+}
+
+STATIC mp_uint_t pyb_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) {
+ pyb_uart_obj_t *self = self_in;
+ const char *buf = buf_in;
+
+ // write the data
+ if (!uart_tx_strn(self, buf, size)) {
+ nlr_raise(mp_obj_new_exception_arg1(&mp_type_OSError, MP_OBJ_NEW_SMALL_INT(ETIMEDOUT)));
+ }
+ return size;
+}
+
+STATIC mp_uint_t pyb_uart_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) {
+ pyb_uart_obj_t *self = self_in;
+ mp_uint_t ret;
+ if (request == MP_IOCTL_POLL) {
+ mp_uint_t flags = arg;
+ ret = 0;
+ if ((flags & MP_IOCTL_POLL_RD) && uart_rx_any(self)) {
+ ret |= MP_IOCTL_POLL_RD;
+ }
+ if ((flags & MP_IOCTL_POLL_WR) && MAP_UARTSpaceAvail(self->reg)) {
+ ret |= MP_IOCTL_POLL_WR;
+ }
+ } else {
+ *errcode = EINVAL;
+ ret = MP_STREAM_ERROR;
+ }
+ return ret;
+}
+
+STATIC const mp_stream_p_t uart_stream_p = {
+ .read = pyb_uart_read,
+ .write = pyb_uart_write,
+ .ioctl = pyb_uart_ioctl,
+ .is_text = false,
+};
+
+const mp_obj_type_t pyb_uart_type = {
+ { &mp_type_type },
+ .name = MP_QSTR_UART,
+ .print = pyb_uart_print,
+ .make_new = pyb_uart_make_new,
+ .getiter = mp_identity,
+ .iternext = mp_stream_unbuffered_iter,
+ .stream_p = &uart_stream_p,
+ .locals_dict = (mp_obj_t)&pyb_uart_locals_dict,
+};
diff --git a/cc3200/mods/pybuart.h b/cc3200/mods/pybuart.h
new file mode 100644
index 0000000000..74298a83f2
--- /dev/null
+++ b/cc3200/mods/pybuart.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef enum {
+ PYB_UART_NONE = 0,
+ PYB_UART_1 = 1,
+ PYB_UART_2 = 2
+} pyb_uart_t;
+
+typedef struct _pyb_uart_obj_t pyb_uart_obj_t;
+extern const mp_obj_type_t pyb_uart_type;
+
+void uart_init0(void);
+bool uart_init(pyb_uart_obj_t *uart_obj, uint baudrate);
+void uart_deinit (void);
+bool uart_rx_any(pyb_uart_obj_t *uart_obj);
+int uart_rx_char(pyb_uart_obj_t *uart_obj);
+bool uart_tx_char(pyb_uart_obj_t *self, int c);
+bool uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len);
+void uart_tx_strn_cooked(pyb_uart_obj_t *uart_obj, const char *str, uint len);
+
diff --git a/cc3200/mpconfigport.h b/cc3200/mpconfigport.h
new file mode 100644
index 0000000000..02afef0ba8
--- /dev/null
+++ b/cc3200/mpconfigport.h
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __INCLUDED_MPCONFIGPORT_H
+#define __INCLUDED_MPCONFIGPORT_H
+
+#include
+
+// options to control how Micro Python is built
+
+#define MICROPY_ALLOC_PATH_MAX (128)
+#define MICROPY_EMIT_THUMB (0)
+#define MICROPY_EMIT_INLINE_THUMB (1)
+#define MICROPY_COMP_MODULE_CONST (1)
+#define MICROPY_ENABLE_GC (1)
+#define MICROPY_ENABLE_FINALISER (1)
+#define MICROPY_STACK_CHECK (0)
+#define MICROPY_HELPER_REPL (1)
+#define MICROPY_ENABLE_SOURCE_LINE (1)
+#define MICROPY_ENABLE_DOC_STRING (0)
+#define MICROPY_ERROR_REPORTING (MICROPY_ERROR_REPORTING_TERSE)
+#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ)
+#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_NONE)
+#define MICROPY_OPT_COMPUTED_GOTO (1)
+#define MICROPY_OPT_CACHE_MAP_LOOKUP_IN_BYTECODE (0)
+
+/* Enable FatFS LFNs
+ 0: Disable LFN feature.
+ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
+ 2: Enable LFN with dynamic working buffer on the STACK.
+ 3: Enable LFN with dynamic working buffer on the HEAP.
+*/
+#define MICROPY_ENABLE_LFN (0)
+#define MICROPY_LFN_CODE_PAGE (1)
+#define MICROPY_STREAMS_NON_BLOCK (1)
+#define MICROPY_MODULE_WEAK_LINKS (0)
+#define MICROPY_CAN_OVERRIDE_BUILTINS (0)
+#define MICROPY_PY_BUILTINS_STR_UNICODE (1)
+#define MICROPY_PY_BUILTINS_MEMORYVIEW (1)
+#define MICROPY_PY_BUILTINS_FROZENSET (1)
+#define MICROPY_PY_BUILTINS_EXECFILE (1)
+#define MICROPY_PY_MICROPYTHON_MEM_INFO (0)
+#define MICROPY_PY_SYS_EXIT (1)
+#define MICROPY_PY_SYS_STDFILES (1)
+#define MICROPY_PY_CMATH (0)
+#define MICROPY_PY_IO (1)
+#define MICROPY_PY_IO_FILEIO (1)
+#define MICROPY_PY_UCTYPES (1)
+#define MICROPY_PY_UZLIB (0)
+#define MICROPY_PY_UJSON (1)
+#define MICROPY_PY_URE (1)
+#define MICROPY_PY_UHEAPQ (1)
+#define MICROPY_PY_UHASHLIB (0)
+
+#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1)
+#define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0)
+
+// extra built in names to add to the global namespace
+extern const struct _mp_obj_fun_builtin_t mp_builtin_help_obj;
+extern const struct _mp_obj_fun_builtin_t mp_builtin_input_obj;
+extern const struct _mp_obj_fun_builtin_t mp_builtin_open_obj;
+#define MICROPY_PORT_BUILTINS \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_help), (mp_obj_t)&mp_builtin_help_obj }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_input), (mp_obj_t)&mp_builtin_input_obj }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_open), (mp_obj_t)&mp_builtin_open_obj }, \
+
+// extra built in modules to add to the list of known ones
+extern const struct _mp_obj_module_t pyb_module;
+extern const struct _mp_obj_module_t mp_module_ure;
+extern const struct _mp_obj_module_t mp_module_ujson;
+extern const struct _mp_obj_module_t mp_module_uheapq;
+extern const struct _mp_obj_module_t mp_module_uos;
+extern const struct _mp_obj_module_t mp_module_utime;
+extern const struct _mp_obj_module_t mp_module_uselect;
+extern const struct _mp_obj_module_t mp_module_usocket;
+extern const struct _mp_obj_module_t mp_module_network;
+
+#define MICROPY_PORT_BUILTIN_MODULES \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_os), (mp_obj_t)&mp_module_uos }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&mp_module_utime }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_select), (mp_obj_t)&mp_module_uselect }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_socket), (mp_obj_t)&mp_module_usocket }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_network), (mp_obj_t)&mp_module_network }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_re), (mp_obj_t)&mp_module_ure }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_json), (mp_obj_t)&mp_module_ujson }, \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_heapq), (mp_obj_t)&mp_module_uheapq }, \
+
+// extra constants
+#define MICROPY_PORT_CONSTANTS \
+ { MP_OBJ_NEW_QSTR(MP_QSTR_pyb), (mp_obj_t)&pyb_module }, \
+
+// vm state and root pointers for the gc
+#define MP_STATE_PORT MP_STATE_VM
+#define MICROPY_PORT_ROOT_POINTERS \
+ const char *readline_hist[8]; \
+ mp_obj_t mp_const_user_interrupt; \
+ mp_obj_t pyb_config_main; \
+ mp_obj_t gpio_class_mapper; \
+ mp_obj_t gpio_class_map_dict; \
+ mp_obj_list_t pyb_extint_list; \
+ struct _pyb_uart_obj_t *pyb_stdio_uart; \
+ struct _pyb_uart_obj_t *pyb_uart_obj_all[2]; \
+ mp_obj_list_t mod_network_nic_list; \
+
+
+// type definitions for the specific machine
+#define BYTES_PER_WORD (4)
+#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void*)((mp_uint_t)(p) | 1))
+
+#define UINT_FMT "%u"
+#define INT_FMT "%d"
+
+typedef int32_t mp_int_t; // must be pointer size
+typedef unsigned int mp_uint_t; // must be pointer size
+typedef void *machine_ptr_t; // must be of pointer size
+typedef const void *machine_const_ptr_t; // must be of pointer size
+typedef long mp_off_t;
+
+#define MICROPY_BEGIN_ATOMIC_SECTION() disable_irq()
+#define MICROPY_END_ATOMIC_SECTION(state) enable_irq(state)
+
+// assembly functions to handle critical sections, interrupt
+// disabling/enabling and sleep mode enter/exit
+#include "cc3200_asm.h"
+
+// There is no classical C heap in bare-metal ports, only Python
+// garbage-collected heap. For completeness, emulate C heap via
+// GC heap. Note that MicroPython core never uses malloc() and friends,
+// so these defines are mostly to help extension module writers.
+#define malloc gc_alloc
+#define free gc_free
+#define realloc gc_realloc
+
+// We need to provide a declaration/definition of alloca()
+#include
+
+// Include board specific configurations
+#include "mpconfigboard.h"
+
+#define MICROPY_HAL_H "cc3200_hal.h"
+#define MICROPY_PIN_DEFS_PORT_H "pin_defs_cc3200.h"
+
+#endif // __INCLUDED_MPCONFIGPORT_H
diff --git a/cc3200/mptask.c b/cc3200/mptask.c
new file mode 100644
index 0000000000..21067a2138
--- /dev/null
+++ b/cc3200/mptask.c
@@ -0,0 +1,341 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "nlr.h"
+#include "misc.h"
+#include "qstr.h"
+#include "lexer.h"
+#include "parse.h"
+#include "obj.h"
+#include "parsehelper.h"
+#include "compile.h"
+#include "runtime0.h"
+#include "runtime.h"
+#include "repl.h"
+#include "inc/hw_memmap.h"
+#include "pybuart.h"
+#include "pybgpio.h"
+#include "pybrtc.h"
+#include "pybstdio.h"
+#include "pyexec.h"
+#include "gccollect.h"
+#include "gchelper.h"
+#include "readline.h"
+#include "gc.h"
+#include "osi.h"
+#include "mptask.h"
+#include "mperror.h"
+#include "simplelink.h"
+#include "modnetwork.h"
+#include "modwlan.h"
+#include "serverstask.h"
+#include "telnet.h"
+#include "debug.h"
+#include "ff.h"
+#include "diskio.h"
+#include "sflash_diskio.h"
+#include "mpexception.h"
+#include "random.h"
+#include "pybextint.h"
+
+/******************************************************************************
+ DECLARE PRIVATE CONSTANTS
+ ******************************************************************************/
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+STATIC void main_init_sflash_filesystem (void);
+STATIC void main_enter_ap_mode (void);
+STATIC void main_create_main_py (void);
+
+/******************************************************************************
+ DECLARE PUBLIC DATA
+ ******************************************************************************/
+#ifdef DEBUG
+OsiTaskHandle svTaskHandle;
+#endif
+
+/******************************************************************************
+ DECLARE PRIVATE DATA
+ ******************************************************************************/
+static FATFS *sflash_fatfs;
+#if MICROPY_HW_HAS_SDCARD
+static FATFS *sd_fatfs;
+#endif
+
+static const char fresh_main_py[] = "# main.py -- put your code here!\r\n";
+static const char fresh_boot_py[] = "# boot.py -- run on boot-up\r\n"
+ "# can run arbitrary Python, but best to keep it minimal\r\n";
+
+/******************************************************************************
+ DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+void TASK_Micropython (void *pvParameters) {
+ // Initialize the garbage collector with the top of our stack
+ uint32_t sp = gc_helper_get_sp();
+ gc_collect_init (sp);
+ FRESULT res;
+
+#if MICROPY_HW_ENABLE_RTC
+ pybrtc_init();
+#endif
+
+ // Create the simple link spawn task
+ ASSERT (OSI_OK == VStartSimpleLinkSpawnTask(SIMPLELINK_SPAWN_TASK_PRIORITY));
+
+ // Allocate memory for the flash file system
+ ASSERT ((sflash_fatfs = mem_Malloc(sizeof(FATFS))) != NULL);
+#if MICROPY_HW_HAS_SDCARD
+ // Allocate memory for the sd file system
+ ASSERT ((sd_fatfs = mem_Malloc(sizeof(FATFS))) != NULL);
+#endif
+
+#ifdef DEBUG
+ ASSERT (OSI_OK == osi_TaskCreate(TASK_Servers,
+ (const signed char *)"Servers",
+ SERVERS_STACK_SIZE, NULL, SERVERS_PRIORITY, &svTaskHandle));
+#else
+ ASSERT (OSI_OK == osi_TaskCreate(TASK_Servers,
+ (const signed char *)"Servers",
+ SERVERS_STACK_SIZE, NULL, SERVERS_PRIORITY, NULL));
+#endif
+
+soft_reset:
+
+ // GC init
+ gc_init(&_heap, &_eheap);
+
+ // Micro Python init
+ mp_init();
+ mp_obj_list_init(mp_sys_path, 0);
+ mp_obj_list_init(mp_sys_argv, 0);
+ mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script)
+
+ mpexception_init0();
+ uart_init0();
+
+ // Instantiate the stdio uart
+ mp_obj_t args[2] = {
+ mp_obj_new_int(MICROPY_STDIO_UART),
+ mp_obj_new_int(MICROPY_STDIO_UART_BAUD),
+ };
+ MP_STATE_PORT(pyb_stdio_uart) = pyb_uart_type.make_new((mp_obj_t)&pyb_uart_type, MP_ARRAY_SIZE(args), 0, args);
+
+ readline_init0();
+ gpio_init0();
+ extint_init0();
+ mod_network_init();
+ wlan_init0();
+#if MICROPY_HW_ENABLE_RNG
+ rng_init0();
+#endif
+
+ main_enter_ap_mode();
+
+ // enable telnet and ftp servers
+ servers_enable();
+
+ // initialize the serial flash file system
+ main_init_sflash_filesystem();
+
+#if MICROPY_HW_HAS_SDCARD
+ // try to mount the sd card on /SD
+ res = f_mount(sd_fatfs, "/SD", 1);
+ if (res == FR_OK) {
+ // use the SD card as the current directory
+ f_chdrive("/SD");
+ mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_SD));
+ mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_SD_slash_LIB));
+ }
+#endif
+
+ // append the SFLASH paths to the system path
+ mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_SFLASH));
+ mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_SFLASH_slash_LIB));
+
+ // reset config variables; they should be set by boot.py
+ MP_STATE_PORT(pyb_config_main) = MP_OBJ_NULL;
+
+ // run boot.py, if it exists
+ const char *boot_py = "BOOT.PY";
+ res = f_stat(boot_py, NULL);
+ if (res == FR_OK) {
+ int ret = pyexec_file(boot_py);
+ if (ret & PYEXEC_FORCED_EXIT) {
+ goto soft_reset_exit;
+ }
+ if (!ret) {
+ // TODO: Flash some LEDs
+ }
+ }
+
+ // Now we initialise sub-systems that need configuration from boot.py,
+ // or whose initialisation can be safely deferred until after running
+ // boot.py.
+
+ // At this point everything is fully configured and initialised.
+
+ // Run the main script from the current directory.
+ if (pyexec_mode_kind == PYEXEC_MODE_FRIENDLY_REPL) {
+ const char *main_py;
+ if (MP_STATE_PORT(pyb_config_main) == MP_OBJ_NULL) {
+ main_py = "MAIN.PY";
+ } else {
+ main_py = mp_obj_str_get_str(MP_STATE_PORT(pyb_config_main));
+ }
+ res = f_stat(main_py, NULL);
+ if (res == FR_OK) {
+ int ret = pyexec_file(main_py);
+ if (ret & PYEXEC_FORCED_EXIT) {
+ goto soft_reset_exit;
+ }
+ if (!ret) {
+ // TODO: Flash some LEDs
+ }
+ }
+ }
+
+ // Main script is finished, so now go into REPL mode.
+ // The REPL mode can change, or it can request a soft reset.
+ for (;;) {
+ if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) {
+ if (pyexec_raw_repl() != 0) {
+ break;
+ }
+ } else {
+ if (pyexec_friendly_repl() != 0) {
+ break;
+ }
+ }
+ }
+
+soft_reset_exit:
+
+ // soft reset
+
+ sflash_disk_flush();
+
+ printf("PYB: soft rebooting...\n");
+
+ // Disable wlan services
+ wlan_servers_stop();
+ wlan_sl_disable();
+
+ // Wait for all bus transfers to complete
+ HAL_Delay(50);
+
+ uart_deinit();
+
+ goto soft_reset;
+}
+
+/******************************************************************************
+ DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
+
+STATIC void main_init_sflash_filesystem (void) {
+ // Initialise the local flash filesystem.
+ // Create it if needed, and mount in on /sflash.
+ // try to mount the flash
+ FRESULT res = f_mount(sflash_fatfs, "/SFLASH", 1);
+ if (res == FR_NO_FILESYSTEM) {
+ // no filesystem, so create a fresh one
+ res = f_mkfs("/SFLASH", 1, 0);
+ if (res == FR_OK) {
+ // success creating fresh LFS
+ } else {
+ __fatal_error("could not create /SFLASH file system");
+ }
+ // create empty main.py
+ main_create_main_py();
+ } else if (res == FR_OK) {
+ // mount sucessful
+ FILINFO fno;
+ if (FR_OK != f_stat("/SFLASH/MAIN.PY", &fno)) {
+ // create empty main.py
+ main_create_main_py();
+ }
+ } else {
+ __fatal_error("could not create /SFLASH file system");
+ }
+
+ // The current directory is used as the boot up directory.
+ // It is set to the internal flash filesystem by default.
+ f_chdrive("/SFLASH");
+
+ // Make sure we have a /flash/boot.py. Create it if needed.
+ FILINFO fno;
+ res = f_stat("/SFLASH/BOOT.PY", &fno);
+ if (res == FR_OK) {
+ if (fno.fattrib & AM_DIR) {
+ // exists as a directory
+ // TODO handle this case
+ // see http://elm-chan.org/fsw/ff/img/app2.c for a "rm -rf" implementation
+ } else {
+ // exists as a file, good!
+ }
+ } else {
+ // doesn't exist, create fresh file
+ FIL fp;
+ f_open(&fp, "/SFLASH/BOOT.PY", FA_WRITE | FA_CREATE_ALWAYS);
+ UINT n;
+ f_write(&fp, fresh_boot_py, sizeof(fresh_boot_py) - 1 /* don't count null terminator */, &n);
+ // TODO check we could write n bytes
+ f_close(&fp);
+ }
+}
+
+STATIC void main_enter_ap_mode (void) {
+ // Enable simplelink in low power mode
+ wlan_sl_enable (ROLE_AP, SERVERS_DEF_AP_SSID, strlen(SERVERS_DEF_AP_SSID), SL_SEC_TYPE_WPA_WPA2,
+ SERVERS_DEF_AP_KEY, strlen(SERVERS_DEF_AP_KEY), SERVERS_DEF_AP_CHANNEL);
+ wlan_set_pm_policy (SL_NORMAL_POLICY);
+}
+
+STATIC void main_create_main_py (void) {
+ // create empty main.py
+ FIL fp;
+ f_open(&fp, "/SFLASH/MAIN.PY", FA_WRITE | FA_CREATE_ALWAYS);
+ UINT n;
+ f_write(&fp, fresh_main_py, sizeof(fresh_main_py) - 1 /* don't count null terminator */, &n);
+ f_close(&fp);
+}
+
+STATIC mp_obj_t pyb_main(mp_obj_t main) {
+ if (MP_OBJ_IS_STR(main)) {
+ MP_STATE_PORT(pyb_config_main) = main;
+ }
+ return mp_const_none;
+}
+MP_DEFINE_CONST_FUN_OBJ_1(pyb_main_obj, pyb_main);
diff --git a/cc3200/mptask.h b/cc3200/mptask.h
new file mode 100644
index 0000000000..6ac419b9d6
--- /dev/null
+++ b/cc3200/mptask.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef MPTASK_H_
+#define MPTASK_H_
+
+/******************************************************************************
+ DEFINE CONSTANTS
+ ******************************************************************************/
+#define MICROPY_TASK_PRIORITY (2)
+#define MICROPY_TASK_STACK_SIZE ((6 * 1024) + 512)
+
+/******************************************************************************
+ DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+extern void TASK_Micropython (void *pvParameters);
+
+#endif /* MPTASK_H_ */
diff --git a/cc3200/qstrdefsport.h b/cc3200/qstrdefsport.h
new file mode 100644
index 0000000000..cfc07105c1
--- /dev/null
+++ b/cc3200/qstrdefsport.h
@@ -0,0 +1,224 @@
+// qstrs specific to this port
+Q(__name__)
+Q(help)
+Q(pyb)
+Q(info)
+Q(hard_reset)
+Q(stop)
+Q(standby)
+Q(main)
+Q(sync)
+Q(gc)
+Q(rng)
+Q(delay)
+Q(time)
+Q(open)
+Q(on)
+Q(off)
+Q(toggle)
+Q(write)
+Q(read)
+Q(readall)
+Q(readline)
+Q(input)
+Q(os)
+Q(mac)
+Q(freq)
+Q(repl_info)
+Q(wfi)
+Q(disable_irq)
+Q(enable_irq)
+Q(millis)
+Q(micros)
+Q(elapsed_millis)
+Q(elapsed_micros)
+Q(udelay)
+Q(SD)
+Q(SDcard)
+Q(FileIO)
+Q(flush)
+// Entries for sys.path
+Q(/SFLASH)
+Q(/SFLASH/LIB)
+Q(/SD)
+Q(/SD/LIB)
+
+// for module weak links
+Q(re)
+Q(json)
+Q(heapq)
+
+// for os module
+Q(uos)
+Q(os)
+Q(/)
+Q(SFLASH)
+Q(SD)
+Q(chdir)
+Q(getcwd)
+Q(listdir)
+Q(mkdir)
+Q(remove)
+Q(rmdir)
+Q(unlink)
+Q(sep)
+Q(stat)
+Q(urandom)
+
+// for file class
+Q(seek)
+Q(tell)
+
+// for GPIO class
+Q(GPIO)
+Q(init)
+Q(value)
+Q(low)
+Q(high)
+Q(name)
+Q(names)
+Q(port)
+Q(pin)
+Q(gpio)
+Q(mapper)
+Q(dict)
+Q(cpu)
+Q(mode)
+Q(pull)
+Q(index)
+Q(strength)
+Q(af)
+Q(IN)
+Q(OUT)
+Q(STD)
+Q(STD_PU)
+Q(STD_PD)
+Q(OD)
+Q(OD_PU)
+Q(OD_PD)
+Q(S2MA)
+Q(S4MA)
+Q(S6MA)
+
+// for ExtInt class
+Q(ExtInt)
+Q(pin)
+Q(mode)
+Q(pull)
+Q(callback)
+Q(enable)
+Q(disable)
+Q(swint)
+Q(IRQ_RISING)
+Q(IRQ_FALLING)
+Q(IRQ_RISING_FALLING)
+Q(IRQ_LOW_LEVEL)
+Q(IRQ_HIGH_LEVEL)
+
+
+// for UART class
+Q(UART)
+Q(UART1)
+Q(UART2)
+Q(baudrate)
+Q(bits)
+Q(stop)
+Q(parity)
+Q(init)
+Q(deinit)
+Q(all)
+Q(writechar)
+Q(readchar)
+Q(readinto)
+Q(read_buf_len)
+Q(timeout)
+Q(timeout_char)
+Q(repl_uart)
+Q(flow)
+Q(FLOW_NONE)
+Q(FLOW_TX)
+Q(FLOW_RX)
+Q(FLOW_TXRX)
+
+// for RTC class
+Q(RTC)
+Q(datetime)
+
+// for time class
+Q(utime)
+Q(localtime)
+Q(mktime)
+Q(sleep)
+Q(time)
+
+// for select class
+Q(select)
+Q(uselect)
+Q(register)
+Q(unregister)
+Q(modify)
+Q(poll)
+
+// for socket class
+Q(socket)
+Q(usocket)
+Q(getaddrinfo)
+Q(family)
+Q(type)
+Q(send)
+Q(sendto)
+Q(recv)
+Q(recvfrom)
+Q(listen)
+Q(accept)
+Q(bind)
+Q(settimeout)
+Q(setblocking)
+Q(setsockopt)
+Q(close)
+Q(protocol)
+Q(AF_INET)
+Q(AF_INET6)
+Q(SOCK_STREAM)
+Q(SOCK_DGRAM)
+Q(SOCK_RAW)
+Q(IPPROTO_TCP)
+Q(IPPROTO_UDP)
+Q(IPPROTO_RAW)
+
+// for network class
+Q(network)
+Q(route)
+
+// for wlan class
+Q(WLAN)
+Q(key)
+Q(security)
+Q(ssid)
+Q(bssid)
+Q(scan)
+Q(connect)
+Q(isconnected)
+Q(disconnect)
+Q(getmode)
+Q(channel)
+Q(getip)
+Q(setpm)
+Q(serversstart)
+Q(serversstop)
+Q(areserversenabled)
+Q(serversuserpass)
+Q(STA)
+Q(AP)
+Q(P2P)
+Q(OPEN)
+Q(WEP)
+Q(WPA_WPA2)
+Q(WPA_ENT)
+Q(WPS_PBC)
+Q(WPS_PIN)
+Q(NORMAL_PM)
+Q(LOW_LATENCY_PM)
+Q(LOW_POWER_PM)
+Q(ALWAYS_ON_PM)
+Q(LONG_SLEEP_PM)
diff --git a/cc3200/serverstask.c b/cc3200/serverstask.c
new file mode 100644
index 0000000000..44e3ee1915
--- /dev/null
+++ b/cc3200/serverstask.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "osi.h"
+#include "simplelink.h"
+#include "serverstask.h"
+#include "modwlan.h"
+#include "debug.h"
+#include "mpexception.h"
+#include "telnet.h"
+#include "ftp.h"
+
+
+/******************************************************************************
+ DECLARE PRIVATE DEFINITIONS
+ ******************************************************************************/
+
+#define SERVERS_DEF_USER "micro"
+#define SERVERS_DEF_PASS "python"
+
+/******************************************************************************
+ DEFINE PRIVATE TYPES
+ ******************************************************************************/
+typedef struct {
+ volatile bool enabled;
+ volatile bool do_disable;
+ volatile bool do_enable;
+}servers_Data_t;
+
+/******************************************************************************
+ DECLARE PRIVATE DATA
+ ******************************************************************************/
+static servers_Data_t servers_data = {.enabled = false, .do_disable = false, .do_enable = false};
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+
+/******************************************************************************
+ DECLARE PUBLIC DATA
+ ******************************************************************************/
+char *servers_user;
+char *servers_pass;
+
+/******************************************************************************
+ DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+
+void TASK_Servers (void *pvParameters) {
+
+ bool cycle = false;
+
+ ASSERT ((servers_user = mem_Malloc(SERVERS_USER_LEN_MAX + 1)) != NULL);
+ ASSERT ((servers_pass = mem_Malloc(SERVERS_PASS_LEN_MAX + 1)) != NULL);
+ strcpy (servers_user, SERVERS_DEF_USER);
+ strcpy (servers_pass, SERVERS_DEF_PASS);
+
+ telnet_init();
+ ftp_init();
+
+ for ( ;; ) {
+
+ if (servers_data.enabled) {
+ if (servers_data.do_disable) {
+ servers_data.do_disable = false;
+ // disable all net processes
+ telnet_disable();
+ ftp_disable();
+
+ // now clear the flag
+ servers_data.enabled = false;
+ }
+ else {
+ if (cycle) {
+ telnet_run();
+ }
+ else {
+ ftp_run();
+ }
+ }
+ }
+ else if (servers_data.do_enable) {
+ servers_data.do_enable = false;
+
+ telnet_enable();
+ ftp_enable();
+
+ // now set the flag
+ servers_data.enabled = true;
+ }
+
+ cycle = cycle ? false : true;
+ HAL_Delay(SERVERS_CYCLE_TIME_MS);
+ }
+}
+
+void servers_enable (void) {
+ servers_data.do_disable = false;
+ servers_data.do_enable = true;
+}
+
+void servers_disable (void) {
+ servers_data.do_enable = false;
+ servers_data.do_disable = true;
+}
+
+bool servers_are_enabled (void) {
+ return servers_data.enabled;
+}
+
+void servers_close_socket (_i16 *sd) {
+ if (*sd > 0) {
+ sl_Close(*sd);
+ *sd = -1;
+ }
+}
+
+void servers_set_user_pass (char *user, char *pass) {
+ memcpy(servers_user, user, SERVERS_USER_LEN_MAX);
+ memcpy(servers_pass, pass, SERVERS_PASS_LEN_MAX);
+}
+
+/******************************************************************************
+ DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
diff --git a/cc3200/serverstask.h b/cc3200/serverstask.h
new file mode 100644
index 0000000000..264a328a87
--- /dev/null
+++ b/cc3200/serverstask.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef SERVERSTASK_H_
+#define SERVERSTASK_H_
+
+/******************************************************************************
+ DEFINE CONSTANTS
+ ******************************************************************************/
+#define SERVERS_PRIORITY 2
+#define SERVERS_STACK_SIZE 960
+
+#define SERVERS_SSID_LEN_MAX 16
+#define SERVERS_KEY_LEN_MAX 16
+
+#define SERVERS_USER_LEN_MAX 16
+#define SERVERS_PASS_LEN_MAX 16
+
+#define SERVERS_DEF_AP_SSID "micropy-wlan"
+#define SERVERS_DEF_AP_KEY "micropython"
+#define SERVERS_DEF_AP_CHANNEL 6
+
+#define SERVERS_CYCLE_TIME_MS 5
+
+/******************************************************************************
+ DEFINE TYPES
+ ******************************************************************************/
+
+/******************************************************************************
+ EXPORTED DATA
+ ******************************************************************************/
+extern char *servers_user;
+extern char *servers_pass;
+
+/******************************************************************************
+ DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+extern void TASK_Servers (void *pvParameters);
+extern void servers_enable (void);
+extern void servers_disable (void);
+extern bool servers_are_enabled (void);
+extern void servers_close_socket (_i16 *sd);
+extern void servers_set_user_pass (char *user, char *pass);
+
+#endif /* SERVERSTASK_H_ */
diff --git a/cc3200/simplelink/cc_pal.c b/cc3200/simplelink/cc_pal.c
new file mode 100644
index 0000000000..5043d50a03
--- /dev/null
+++ b/cc3200/simplelink/cc_pal.c
@@ -0,0 +1,519 @@
+//*****************************************************************************
+// cc_pal.c
+//
+// simplelink abstraction file for CC3200
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+//Simplelink includes
+#include
+#include
+
+//Driverlib includes
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+//OSLib includes
+#if defined(SL_PLATFORM_MULTI_THREADED)
+#include
+#endif
+
+
+#define REG_INT_MASK_SET 0x400F7088
+#define REG_INT_MASK_CLR 0x400F708C
+#define APPS_SOFT_RESET_REG 0x4402D000
+#define OCP_SHARED_MAC_RESET_REG 0x4402E168
+
+#define SPI_RATE_20M 20000000
+
+#define UNUSED(x) (x = x)
+
+//
+// GLOBAL VARIABLES -- Start
+//
+volatile Fd_t g_SpiFd =0;
+P_EVENT_HANDLER g_pHostIntHdl = NULL;
+
+//
+// GLOBAL VARIABLES -- End
+//
+
+
+//****************************************************************************
+// LOCAL FUNCTION PROTOTYPES
+//****************************************************************************
+static int spi_Read_CPU(unsigned char *pBuff, int len);
+static int spi_Write_CPU(unsigned char *pBuff, int len);
+
+//****************************************************************************
+// LOCAL FUNCTION DEFINITIONS
+//****************************************************************************
+
+/*!
+ \brief attempts to read up to len bytes from SPI channel into a buffer starting at pBuff.
+
+ \param pBuff - points to first location to start writing the data
+
+ \param len - number of bytes to read from the SPI channel
+
+ \return upon successful completion, the function shall return Read Size.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Read_CPU , spi_Write_CPU
+ \note
+ \warning
+*/
+int spi_Read_CPU(unsigned char *pBuff, int len)
+{
+ unsigned long ulCnt;
+ unsigned long ulStatusReg;
+ unsigned long *ulDataIn;
+ unsigned long ulTxReg;
+ unsigned long ulRxReg;
+
+ MAP_SPICSEnable(LSPI_BASE);
+
+ //
+ // Initialize local variable.
+ //
+ ulDataIn = (unsigned long *)pBuff;
+ ulCnt = (len + 3) >> 2;
+ ulStatusReg = LSPI_BASE+MCSPI_O_CH0STAT;
+ ulTxReg = LSPI_BASE + MCSPI_O_TX0;
+ ulRxReg = LSPI_BASE + MCSPI_O_RX0;
+
+ //
+ // Reading loop
+ //
+ while(ulCnt--)
+ {
+ while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_TXS ));
+ HWREG(ulTxReg) = 0xFFFFFFFF;
+ while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_RXS ));
+ *ulDataIn = HWREG(ulRxReg);
+ ulDataIn++;
+ }
+
+ MAP_SPICSDisable(LSPI_BASE);
+
+ return len;
+}
+
+/*!
+ \brief attempts to write up to len bytes to the SPI channel
+
+ \param pBuff - points to first location to start getting the data from
+
+ \param len - number of bytes to write to the SPI channel
+
+ \return upon successful completion, the function shall return write size.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Read_CPU , spi_Write_CPU
+ \note This function could be implemented as zero copy and return only upon successful completion
+ of writing the whole buffer, but in cases that memory allocation is not too tight, the
+ function could copy the data to internal buffer, return back and complete the write in
+ parallel to other activities as long as the other SPI activities would be blocked untill
+ the entire buffer write would be completed
+ \warning
+*/
+int spi_Write_CPU(unsigned char *pBuff, int len)
+{
+ unsigned long ulCnt;
+ unsigned long ulStatusReg;
+ unsigned long *ulDataOut;
+ unsigned long ulDataIn;
+ unsigned long ulTxReg;
+ unsigned long ulRxReg;
+
+
+ MAP_SPICSEnable(LSPI_BASE);
+
+ //
+ // Initialize local variable.
+ //
+ ulDataOut = (unsigned long *)pBuff;
+ ulCnt = (len +3 ) >> 2;
+ ulStatusReg = LSPI_BASE+MCSPI_O_CH0STAT;
+ ulTxReg = LSPI_BASE + MCSPI_O_TX0;
+ ulRxReg = LSPI_BASE + MCSPI_O_RX0;
+
+ //
+ // Writing Loop
+ //
+ while(ulCnt--)
+ {
+ while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_TXS ));
+ HWREG(ulTxReg) = *ulDataOut;
+ while(!( HWREG(ulStatusReg)& MCSPI_CH0STAT_RXS ));
+ ulDataIn = HWREG(ulRxReg);
+ ulDataOut++;
+ }
+
+ MAP_SPICSDisable(LSPI_BASE);
+
+ UNUSED(ulDataIn);
+ return len;
+}
+
+/*!
+ \brief open spi communication port to be used for communicating with a SimpleLink device
+
+ Given an interface name and option flags, this function opens the spi communication port
+ and creates a file descriptor. This file descriptor can be used afterwards to read and
+ write data from and to this specific spi channel.
+ The SPI speed, clock polarity, clock phase, chip select and all other attributes are all
+ set to hardcoded values in this function.
+
+ \param ifName - points to the interface name/path. The interface name is an
+ optional attributes that the simple link driver receives
+ on opening the device. in systems that the spi channel is
+ not implemented as part of the os device drivers, this
+ parameter could be NULL.
+ \param flags - option flags
+
+ \return upon successful completion, the function shall open the spi channel and return
+ a non-negative integer representing the file descriptor.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Close , spi_Read , spi_Write
+ \note
+ \warning
+*/
+
+Fd_t spi_Open(char *ifName, unsigned long flags)
+{
+ unsigned long ulBase;
+ unsigned long ulSpiBitRate = SPI_RATE_20M;
+
+ //NWP master interface
+ ulBase = LSPI_BASE;
+
+ //Enable MCSPIA2
+ MAP_PRCMPeripheralClkEnable(PRCM_LSPI,PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+
+ //Disable Chip Select
+ MAP_SPICSDisable(ulBase);
+
+ //Disable SPI Channel
+ MAP_SPIDisable(ulBase);
+
+ // Reset SPI
+ MAP_SPIReset(ulBase);
+
+ //
+ // Configure SPI interface
+ //
+
+ MAP_SPIConfigSetExpClk(ulBase,MAP_PRCMPeripheralClockGet(PRCM_LSPI),
+ ulSpiBitRate,SPI_MODE_MASTER,SPI_SUB_MODE_0,
+ (SPI_SW_CTRL_CS |
+ SPI_4PIN_MODE |
+ SPI_TURBO_OFF |
+ SPI_CS_ACTIVEHIGH |
+ SPI_WL_32));
+
+ MAP_SPIEnable(ulBase);
+
+ g_SpiFd = 1;
+ return g_SpiFd;
+}
+/*!
+ \brief closes an opened spi communication port
+
+ \param fd - file descriptor of an opened SPI channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Open
+ \note
+ \warning
+*/
+int spi_Close(Fd_t fd)
+{
+ unsigned long ulBase = LSPI_BASE;
+
+ g_SpiFd = 0;
+
+ //Disable Chip Select
+ MAP_SPICSDisable(LSPI_BASE);
+
+
+ //Disable SPI Channel
+ MAP_SPIDisable(ulBase);
+
+ // Reset SPI
+ MAP_SPIReset(ulBase);
+
+ // Disable SPI Peripheral
+ MAP_PRCMPeripheralClkDisable(PRCM_LSPI,PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+
+ return 0;
+}
+
+/*!
+ \brief closes an opened spi communication port
+
+ \param fd - file descriptor of an opened SPI channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Open
+ \note
+ \warning
+*/
+
+int spi_Read(Fd_t fd, unsigned char *pBuff, int len)
+{
+ if (fd != 1 || g_SpiFd != 1) {
+ return -1;
+ }
+
+ return spi_Read_CPU(pBuff, len);
+}
+
+/*!
+ \brief attempts to write up to len bytes to the SPI channel
+
+ \param fd - file descriptor of an opened SPI channel
+
+ \param pBuff - points to first location to start getting the data from
+
+ \param len - number of bytes to write to the SPI channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Open , spi_Read
+ \note This function could be implemented as zero copy and return only upon successful completion
+ of writing the whole buffer, but in cases that memory allocation is not too tight, the
+ function could copy the data to internal buffer, return back and complete the write in
+ parallel to other activities as long as the other SPI activities would be blocked untill
+ the entire buffer write would be completed
+ \warning
+*/
+int spi_Write(Fd_t fd, unsigned char *pBuff, int len)
+{
+ if (fd != 1 || g_SpiFd != 1) {
+ return -1;
+ }
+
+ return spi_Write_CPU(pBuff,len);
+}
+
+/*!
+ \brief register an interrupt handler for the host IRQ
+
+ \param InterruptHdl - pointer to interrupt handler function
+
+ \param pValue - pointer to a memory strcuture that is passed to the interrupt handler.
+
+ \return upon successful registration, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa
+ \note If there is already registered interrupt handler, the function should overwrite the old handler
+ with the new one
+ \warning
+*/
+
+int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue)
+{
+
+ if(InterruptHdl == NULL)
+ {
+ //De-register Interprocessor communication interrupt between App and NWP
+ #ifdef SL_PLATFORM_MULTI_THREADED
+ osi_InterruptDeRegister(INT_NWPIC);
+ #else
+ MAP_IntDisable(INT_NWPIC);
+ MAP_IntUnregister(INT_NWPIC);
+ MAP_IntPendClear(INT_NWPIC);
+ #endif
+ }
+ else
+ {
+ #ifdef SL_PLATFORM_MULTI_THREADED
+ MAP_IntPendClear(INT_NWPIC);
+ osi_InterruptRegister(INT_NWPIC, (P_OSI_INTR_ENTRY)InterruptHdl,INT_PRIORITY_LVL_1);
+ #else
+ MAP_IntRegister(INT_NWPIC, InterruptHdl);
+ MAP_IntPrioritySet(INT_NWPIC, INT_PRIORITY_LVL_1);
+ MAP_IntPendClear(INT_NWPIC);
+ MAP_IntEnable(INT_NWPIC);
+ #endif
+ }
+
+ return 0;
+}
+
+
+/*!
+ \brief Masks host IRQ
+
+
+ \sa NwpUnMaskInterrupt
+
+ \warning
+*/
+void NwpMaskInterrupt()
+{
+ (*(unsigned long *)REG_INT_MASK_SET) = 0x1;
+}
+
+
+/*!
+ \brief Unmasks host IRQ
+
+
+ \sa NwpMaskInterrupt
+
+ \warning
+*/
+void NwpUnMaskInterrupt()
+{
+ (*(unsigned long *)REG_INT_MASK_CLR) = 0x1;
+}
+
+/*!
+ \brief Preamble to the enabling the Network Processor.
+ Placeholder to implement any pre-process operations
+ before enabling networking operations.
+
+ \sa sl_DeviceEnable
+
+ \note belongs to \ref ported_sec
+
+*/
+void NwpPowerOnPreamble(void)
+{
+ #define MAX_RETRY_COUNT 1000
+
+ unsigned int sl_stop_ind, apps_int_sts_raw, nwp_lpds_wake_cfg;
+ unsigned int retry_count;
+ /* Perform the sl_stop equivalent to ensure network services
+ are turned off if active */
+ HWREG(0x400F70B8) = 1; /* APPs to NWP interrupt */
+ UtilsDelay(800000/5);
+
+ retry_count = 0;
+ nwp_lpds_wake_cfg = HWREG(0x4402D404);
+ sl_stop_ind = HWREG(0x4402E16C);
+
+ if((nwp_lpds_wake_cfg != 0x20) && /* Check for NWP POR condition */
+ !(sl_stop_ind & 0x2)) /* Check if sl_stop was executed */
+ {
+ /* Loop until APPs->NWP interrupt is cleared or timeout */
+ while(retry_count < MAX_RETRY_COUNT)
+ {
+ apps_int_sts_raw = HWREG(0x400F70C0);
+ if(apps_int_sts_raw & 0x1)
+ {
+ UtilsDelay(800000/5);
+ retry_count++;
+ }
+ else
+ {
+ break;
+ }
+ }
+ }
+ HWREG(0x400F70B0) = 1; /* Clear APPs to NWP interrupt */
+ UtilsDelay(800000/5);
+
+ /* Stop the networking services */
+ NwpPowerOff();
+}
+
+/*!
+ \brief Enable the Network Processor
+
+ \sa sl_DeviceDisable
+
+ \note belongs to \ref ported_sec
+
+*/
+void NwpPowerOn(void)
+{
+ //bring the 1.32 eco out of reset
+ HWREG(0x4402E16C) &= 0xFFFFFFFD;
+
+ //NWP Wakeup
+ HWREG(0x44025118) = 1;
+
+ UtilsDelay(8000000);
+
+ //UnMask Host Interrupt
+ NwpUnMaskInterrupt();
+}
+
+
+/*!
+ \brief Disable the Network Processor
+
+ \sa sl_DeviceEnable
+
+ \note belongs to \ref ported_sec
+*/
+void NwpPowerOff(void)
+{
+ //Must delay 300 usec to enable the NWP to finish all sl_stop activities
+ UtilsDelay(300*80/3);
+
+ //Mask Host Interrupt
+ NwpMaskInterrupt();
+
+ //Switch to PFM Mode
+ HWREG(0x4402F024) &= 0xF7FFFFFF;
+
+ //sl_stop eco for PG1.32 devices
+ HWREG(0x4402E16C) |= 0x2;
+
+ UtilsDelay(800000);
+}
diff --git a/cc3200/simplelink/cc_pal.h b/cc3200/simplelink/cc_pal.h
new file mode 100644
index 0000000000..1cf83e7710
--- /dev/null
+++ b/cc3200/simplelink/cc_pal.h
@@ -0,0 +1,202 @@
+//*****************************************************************************
+// cc_pal.h
+//
+// Simplelink abstraction header file for CC3200
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __CC31xx_PAL_H__
+#define __CC31xx_PAL_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+/*!
+ \brief type definition for the spi channel file descriptor
+
+ \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc.
+*/
+typedef int Fd_t;
+
+
+/*!
+ \brief type definition for the host interrupt handler
+
+ \param pValue - pointer to any memory strcuture. The value of this pointer is givven on
+ registration of a new interrupt handler
+
+ \note
+*/
+
+typedef void (*SL_P_EVENT_HANDLER)(void);
+
+#define P_EVENT_HANDLER SL_P_EVENT_HANDLER
+
+/*!
+ \brief open spi communication port to be used for communicating with a SimpleLink device
+
+ Given an interface name and option flags, this function opens the spi communication port
+ and creates a file descriptor. This file descriptor can be used afterwards to read and
+ write data from and to this specific spi channel.
+ The SPI speed, clock polarity, clock phase, chip select and all other attributes are all
+ set to hardcoded values in this function.
+
+ \param ifName - points to the interface name/path. The interface name is an
+ optional attributes that the simple link driver receives
+ on opening the device. in systems that the spi channel is
+ not implemented as part of the os device drivers, this
+ parameter could be NULL.
+ \param flags - option flags
+
+ \return upon successful completion, the function shall open the spi channel and return
+ a non-negative integer representing the file descriptor.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Close , spi_Read , spi_Write
+ \note
+ \warning
+*/
+Fd_t spi_Open(char *ifName, unsigned long flags);
+
+/*!
+ \brief closes an opened spi communication port
+
+ \param fd - file descriptor of an opened SPI channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Open
+ \note
+ \warning
+*/
+int spi_Close(Fd_t fd);
+
+/*!
+ \brief attempts to read up to len bytes from SPI channel into a buffer starting at pBuff.
+
+ \param fd - file descriptor of an opened SPI channel
+
+ \param pBuff - points to first location to start writing the data
+
+ \param len - number of bytes to read from the SPI channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Open , spi_Write
+ \note
+ \warning
+*/
+int spi_Read(Fd_t fd, unsigned char *pBuff, int len);
+
+/*!
+ \brief attempts to write up to len bytes to the SPI channel
+
+ \param fd - file descriptor of an opened SPI channel
+
+ \param pBuff - points to first location to start getting the data from
+
+ \param len - number of bytes to write to the SPI channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa spi_Open , spi_Read
+ \note This function could be implemented as zero copy and return only upon successful completion
+ of writing the whole buffer, but in cases that memory allocation is not too tight, the
+ function could copy the data to internal buffer, return back and complete the write in
+ parallel to other activities as long as the other SPI activities would be blocked untill
+ the entire buffer write would be completed
+ \warning
+*/
+int spi_Write(Fd_t fd, unsigned char *pBuff, int len);
+
+/*!
+ \brief register an interrupt handler for the host IRQ
+
+ \param InterruptHdl - pointer to interrupt handler function
+
+ \param pValue - pointer to a memory strcuture that is passed to the interrupt handler.
+
+ \return upon successful registration, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa
+ \note If there is already registered interrupt handler, the function should overwrite the old handler
+ with the new one
+ \warning
+*/
+int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue);
+
+
+/*!
+ \brief Masks host IRQ
+
+
+ \sa NwpUnMaskInterrupt
+
+ \warning
+*/
+void NwpMaskInterrupt();
+
+
+/*!
+ \brief Unmasks host IRQ
+
+
+ \sa NwpMaskInterrupt
+
+ \warning
+*/
+void NwpUnMaskInterrupt();
+
+void NwpPowerOnPreamble(void);
+
+void NwpPowerOff(void);
+
+void NwpPowerOn(void);
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+
+#endif
+
diff --git a/cc3200/simplelink/include/device.h b/cc3200/simplelink/include/device.h
new file mode 100644
index 0000000000..3f505c94d6
--- /dev/null
+++ b/cc3200/simplelink/include/device.h
@@ -0,0 +1,635 @@
+/*
+ * device.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __DEVICE_H__
+#define __DEVICE_H__
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/*!
+
+ \addtogroup device
+ @{
+
+*/
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+
+/* SL internal Error codes */
+
+/* Receive this error in case there are no resources to issue the command
+ If possible, increase the number of MAX_CUNCURENT_ACTIONS (result in memory increase)
+ If not, try again later */
+#define SL_POOL_IS_EMPTY (-2000)
+
+/* Receive this error in case a given length for RX buffer was too small.
+ Receive payload was bigger than the given buffer size. Therefore, payload is cut according to receive size
+ Recommend to increase buffer size */
+#define SL_ESMALLBUF (-2001)
+
+/* Receive this error in case zero length is supplied to a "get" API
+ Recommend to supply length according to requested information (view options defines for help) */
+#define SL_EZEROLEN (-2002)
+
+/* User supplied invalid parameter */
+#define SL_INVALPARAM (-2003)
+
+/* End of SL internal Error codes */
+
+
+
+/*****************************************************************************/
+/* Errors returned from the general error async event */
+/*****************************************************************************/
+
+/* Send types */
+typedef enum
+{
+ SL_ERR_SENDER_HEALTH_MON,
+ SL_ERR_SENDER_CLI_UART,
+ SL_ERR_SENDER_SUPPLICANT,
+ SL_ERR_SENDER_NETWORK_STACK,
+ SL_ERR_SENDER_WLAN_DRV_IF,
+ SL_ERR_SENDER_WILINK,
+ SL_ERR_SENDER_INIT_APP,
+ SL_ERR_SENDER_NETX,
+ SL_ERR_SENDER_HOST_APD,
+ SL_ERR_SENDER_MDNS,
+ SL_ERR_SENDER_HTTP_SERVER,
+ SL_ERR_SENDER_DHCP_SERVER,
+ SL_ERR_SENDER_DHCP_CLIENT,
+ SL_ERR_DISPATCHER,
+ SL_ERR_NUM_SENDER_LAST=0xFF
+}SlErrorSender_e;
+
+
+/* Error codes */
+#define SL_ERROR_STATIC_ADDR_SUBNET_ERROR (-60) /* network stack error*/
+#define SL_ERROR_ILLEGAL_CHANNEL (-61) /* supplicant error */
+#define SL_ERROR_SUPPLICANT_ERROR (-72) /* init error code */
+#define SL_ERROR_HOSTAPD_INIT_FAIL (-73) /* init error code */
+#define SL_ERROR_HOSTAPD_INIT_IF_FAIL (-74) /* init error code */
+#define SL_ERROR_WLAN_DRV_INIT_FAIL (-75) /* init error code */
+#define SL_ERROR_WLAN_DRV_START_FAIL (-76) /* wlan start error */
+#define SL_ERROR_FS_FILE_TABLE_LOAD_FAILED (-77) /* init file system failed */
+#define SL_ERROR_PREFERRED_NETWORKS_FILE_LOAD_FAILED (-78) /* init file system failed */
+#define SL_ERROR_HOSTAPD_BSSID_VALIDATION_ERROR (-79) /* Ap configurations BSSID error */
+#define SL_ERROR_HOSTAPD_FAILED_TO_SETUP_INTERFACE (-80) /* Ap configurations interface error */
+#define SL_ERROR_MDNS_ENABLE_FAIL (-81) /* mDNS enable failed */
+#define SL_ERROR_HTTP_SERVER_ENABLE_FAILED (-82) /* HTTP server enable failed */
+#define SL_ERROR_DHCP_SERVER_ENABLE_FAILED (-83) /* DHCP server enable failed */
+#define SL_ERROR_PREFERRED_NETWORK_LIST_FULL (-93) /* supplicant error */
+#define SL_ERROR_PREFERRED_NETWORKS_FILE_WRITE_FAILED (-94) /* supplicant error */
+#define SL_ERROR_DHCP_CLIENT_RENEW_FAILED (-100) /* DHCP client error */
+/* WLAN Connection management status */
+#define SL_ERROR_CON_MGMT_STATUS_UNSPECIFIED (-102)
+#define SL_ERROR_CON_MGMT_STATUS_AUTH_REJECT (-103)
+#define SL_ERROR_CON_MGMT_STATUS_ASSOC_REJECT (-104)
+#define SL_ERROR_CON_MGMT_STATUS_SECURITY_FAILURE (-105)
+#define SL_ERROR_CON_MGMT_STATUS_AP_DEAUTHENTICATE (-106)
+#define SL_ERROR_CON_MGMT_STATUS_AP_DISASSOCIATE (-107)
+#define SL_ERROR_CON_MGMT_STATUS_ROAMING_TRIGGER (-108)
+#define SL_ERROR_CON_MGMT_STATUS_DISCONNECT_DURING_CONNECT (-109)
+#define SL_ERROR_CON_MGMT_STATUS_SG_RESELECT (-110)
+#define SL_ERROR_CON_MGMT_STATUS_ROC_FAILURE (-111)
+#define SL_ERROR_CON_MGMT_STATUS_MIC_FAILURE (-112)
+/* end of WLAN connection management error statuses */
+#define SL_ERROR_WAKELOCK_ERROR_PREFIX (-115) /* Wake lock expired */
+#define SL_ERROR_LENGTH_ERROR_PREFIX (-116) /* Uart header length error */
+#define SL_ERROR_MDNS_CREATE_FAIL (-121) /* mDNS create failed */
+#define SL_ERROR_GENERAL_ERROR (-127)
+
+
+
+#define SL_DEVICE_GENERAL_CONFIGURATION (1)
+#define SL_DEVICE_GENERAL_CONFIGURATION_DATE_TIME (11)
+#define SL_DEVICE_GENERAL_VERSION (12)
+#define SL_DEVICE_STATUS (2)
+
+/*
+ Declare the different event group classifications
+ The SimpleLink device send asynchronous events. Each event has a group
+ classification according to its nature.
+*/
+/* SL_EVENT_CLASS_WLAN connection user events */
+#define SL_WLAN_CONNECT_EVENT (1)
+#define SL_WLAN_DISCONNECT_EVENT (2)
+/* WLAN Smart Config user events */
+#define SL_WLAN_SMART_CONFIG_COMPLETE_EVENT (3)
+#define SL_WLAN_SMART_CONFIG_STOP_EVENT (4)
+/* WLAN AP user events */
+#define SL_WLAN_STA_CONNECTED_EVENT (5)
+#define SL_WLAN_STA_DISCONNECTED_EVENT (6)
+/* WLAN P2P user events */
+#define SL_WLAN_P2P_DEV_FOUND_EVENT (7)
+#define SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT (8)
+#define SL_WLAN_CONNECTION_FAILED_EVENT (9)
+/* SL_EVENT_CLASS_DEVICE user events */
+#define SL_DEVICE_FATAL_ERROR_EVENT (1)
+/* SL_EVENT_CLASS_BSD user events */
+#define SL_SOCKET_TX_FAILED_EVENT (1)
+#define SL_SOCKET_ASYNC_EVENT (2)
+/* SL_EVENT_CLASS_NETAPP user events */
+#define SL_NETAPP_IPV4_IPACQUIRED_EVENT (1)
+#define SL_NETAPP_IPV6_IPACQUIRED_EVENT (2)
+#define SL_NETAPP_IP_LEASED_EVENT (3)
+#define SL_NETAPP_IP_RELEASED_EVENT (4)
+
+/* Server Events */
+#define SL_NETAPP_HTTPGETTOKENVALUE_EVENT (1)
+#define SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT (2)
+
+
+/*
+ Declare the different event group classifications for sl_DevGet
+ for getting status indications
+ */
+
+/* Events list to mask/unmask*/
+#define SL_EVENT_CLASS_GLOBAL (0)
+#define SL_EVENT_CLASS_DEVICE (1)
+#define SL_EVENT_CLASS_WLAN (2)
+#define SL_EVENT_CLASS_BSD (3)
+#define SL_EVENT_CLASS_NETAPP (4)
+#define SL_EVENT_CLASS_NETCFG (5)
+#define SL_EVENT_CLASS_FS (6)
+
+
+/****************** DEVICE CLASS status ****************/
+#define EVENT_DROPPED_DEVICE_ASYNC_GENERAL_ERROR (0x00000001L)
+#define STATUS_DEVICE_SMART_CONFIG_ACTIVE (0x80000000L)
+
+/****************** WLAN CLASS status ****************/
+#define EVENT_DROPPED_WLAN_WLANASYNCONNECTEDRESPONSE (0x00000001L)
+#define EVENT_DROPPED_WLAN_WLANASYNCDISCONNECTEDRESPONSE (0x00000002L)
+#define EVENT_DROPPED_WLAN_STA_CONNECTED (0x00000004L)
+#define EVENT_DROPPED_WLAN_STA_DISCONNECTED (0x00000008L)
+#define STATUS_WLAN_STA_CONNECTED (0x80000000L)
+
+/****************** NETAPP CLASS status ****************/
+#define EVENT_DROPPED_NETAPP_IPACQUIRED (0x00000001L)
+#define EVENT_DROPPED_NETAPP_IPACQUIRED_V6 (0x00000002L)
+#define EVENT_DROPPED_NETAPP_IP_LEASED (0x00000004L)
+#define EVENT_DROPPED_NETAPP_IP_RELEASED (0x00000008L)
+
+/****************** BSD CLASS status ****************/
+#define EVENT_DROPPED_SOCKET_TXFAILEDASYNCRESPONSE (0x00000001L)
+
+/****************** FS CLASS ****************/
+
+
+
+/*****************************************************************************/
+/* Structure/Enum declarations */
+/*****************************************************************************/
+
+#ifdef SL_IF_TYPE_UART
+typedef struct
+{
+ _u32 BaudRate;
+ _u8 FlowControlEnable;
+ _u8 CommPort;
+} SlUartIfParams_t;
+#endif
+
+typedef struct
+{
+ _u32 ChipId;
+ _u32 FwVersion[4];
+ _u8 PhyVersion[4];
+}_SlPartialVersion;
+
+typedef struct
+{
+ _SlPartialVersion ChipFwAndPhyVersion;
+ _u32 NwpVersion[4];
+ _u16 RomVersion;
+ _u16 Padding;
+}SlVersionFull;
+
+typedef struct
+{
+ _i8 status;
+ SlErrorSender_e sender;
+}sl_DeviceReport;
+
+typedef union
+{
+ sl_DeviceReport deviceEvent;
+} _SlDeviceEventData_u;
+
+typedef struct
+{
+ _u32 Event;
+ _SlDeviceEventData_u EventData;
+} SlDeviceEvent_t;
+
+typedef struct
+{
+ /* time */
+ _u32 sl_tm_sec;
+ _u32 sl_tm_min;
+ _u32 sl_tm_hour;
+ /* date */
+ _u32 sl_tm_day; /* 1-31 */
+ _u32 sl_tm_mon; /* 1-12 */
+ _u32 sl_tm_year; /* YYYY 4 digits */
+ _u32 sl_tm_week_day; /* not required */
+ _u32 sl_tm_year_day; /* not required */
+ _u32 reserved[3];
+}SlDateTime_t;
+
+
+/******************************************************************************/
+/* Type declarations */
+/******************************************************************************/
+typedef void (*P_INIT_CALLBACK)(_u32 Status);
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+
+/*!
+ \brief Start the SimpleLink device
+
+ This function initialize the communication interface, set the enable pin
+ of the device, and call to the init complete callback.
+
+ \param[in] pIfHdl Opened Interface Object. In case the interface
+ must be opened outside the SimpleLink Driver, the
+ user might give the handler to be used in \n
+ any access of the communication interface with the
+ device (UART/SPI). \n
+ The SimpleLink driver will open an interface port
+ only if this parameter is null! \n
+ \param[in] pDevName The name of the device to open. Could be used when
+ the pIfHdl is null, to transfer information to the
+ open interface function \n
+ This pointer could be used to pass additional information to
+ sl_IfOpen in case it is required (e.g. UART com port name)
+ \param[in] pInitCallBack Pointer to function that would be called
+ on completion of the initialization process.\n
+ If this parameter is NULL the function is
+ blocked until the device initialization
+ is completed, otherwise the function returns
+ immediately.
+
+ \return Returns the current active role (STA/AP/P2P) or an error code:
+ - ROLE_STA, ROLE_AP, ROLE_P2P in case of success,
+ otherwise in failure one of the following is return:
+ - ROLE_STA_ERR (Failure to load MAC/PHY in STA role)
+ - ROLE_AP_ERR (Failure to load MAC/PHY in AP role)
+ - ROLE_P2P_ERR (Failure to load MAC/PHY in P2P role)
+
+
+ \sa sl_Stop
+
+ \note belongs to \ref basic_api
+
+ \warning This function must be called before any other SimpleLink API is used, or after sl_Stop is called for reinit the device
+ \par Example:
+ \code
+ An example for open interface without callback routine. The interface name and handler are
+ handled by the sl_IfOpen routine:
+
+ if( sl_Start(NULL, NULL, NULL) < 0 )
+ {
+ LOG("Error opening interface to device\n");
+ }
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_Start)
+_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack);
+#endif
+
+/*!
+ \brief Stop the SimpleLink device
+
+ This function clears the enable pin of the device, closes the communication \n
+ interface and invokes the stop complete callback
+
+ \param[in] timeout Stop timeout in msec. Should be used to give the device time to finish \n
+ any transmission/reception that is not completed when the function was called. \n
+ Additional options:
+ - 0 Enter to hibernate immediately \n
+ - 0xFFFF Host waits for device's response before \n
+ hibernating, without timeout protection \n
+ - 0 < Timeout[msec] < 0xFFFF Host waits for device's response before \n
+ hibernating, with a defined timeout protection \n
+ This timeout defines the max time to wait. The NWP \n
+ response can be sent earlier than this timeout.
+
+ \return On success, zero is returned. On error, -1 is returned
+
+ \sa sl_Start
+
+ \note This API will shutdown the device and invoke the "i/f close" function regardless \n
+ if it was opened implicitly or explicitly. \n
+ It is up to the platform interface library to properly handle interface close \n
+ routine \n
+ belongs to \ref basic_api \n
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Stop)
+_i16 sl_Stop(_u16 timeout);
+#endif
+
+
+/*!
+ \brief Internal function for setting device configurations
+
+ \return On success, zero is returned. On error, -1 is
+ returned
+
+ \param[in] DeviceSetId configuration id
+ \param[in] Option configurations option
+ \param[in] ConfigLen configurations len
+ \param[in] pValues configurations values
+
+ \sa
+ \note
+ \warning
+ \par Examples:
+ \code
+ Setting device time and date example:
+
+ SlDateTime_t dateTime= {0};
+ dateTime.sl_tm_day = (_u32)23; // Day of month (DD format) range 1-13
+ dateTime.sl_tm_mon = (_u32)6; // Month (MM format) in the range of 1-12
+ dateTime.sl_tm_year = (_u32)2014; // Year (YYYY format)
+ dateTime.sl_tm_hour = (_u32)17; // Hours in the range of 0-23
+ dateTime.sl_tm_min = (_u32)55; // Minutes in the range of 0-59
+ dateTime.sl_tm_sec = (_u32)22; // Seconds in the range of 0-59
+ sl_DevSet(SL_DEVICE_GENERAL_CONFIGURATION,
+ SL_DEVICE_GENERAL_CONFIGURATION_DATE_TIME,
+ sizeof(SlDateTime_t),
+ (_u8 *)(&dateTime));
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_DevSet)
+_i32 sl_DevSet(_u8 DeviceSetId ,_u8 Option,_u8 ConfigLen, _u8 *pValues);
+#endif
+
+/*!
+ \brief Internal function for getting device configurations
+ \return On success, zero is returned. On error, -1 is
+ returned
+ \param[in] DeviceGetId configuration id - example SL_DEVICE_STATUS
+ \param[out] pOption Get configurations option, example for get status options
+ - SL_EVENT_CLASS_GLOBAL
+ - SL_EVENT_CLASS_DEVICE
+ - SL_EVENT_CLASS_WLAN
+ - SL_EVENT_CLASS_BSD
+ - SL_EVENT_CLASS_NETAPP
+ - SL_EVENT_CLASS_NETCFG
+ - SL_EVENT_CLASS_FS
+ \param[out] pConfigLen The length of the allocated memory as input, when the
+ function complete, the value of this parameter would be
+ the len that actually read from the device.\n
+ If the device return length that is longer from the input
+ value, the function will cut the end of the returned structure
+ and will return SL_ESMALLBUF
+ \param[out] pValues Get configurations values
+ \sa
+ \note
+ \warning
+ \par Examples:
+ \code
+ Example for getting WLAN class status:
+ _u32 statusWlan;
+ _u8 pConfigOpt;
+ _u8 pConfigLen;
+ pConfigOpt = SL_EVENT_CLASS_WLAN;
+ sl_DevGet(SL_DEVICE_STATUS,&pConfigOpt,&pConfigLen,(_u8 *)(&statusWlan));
+ Example for getting version:
+ SlVersionFull ver;
+ pConfigOpt = SL_DEVICE_GENERAL_VERSION;
+ sl_DevGet(SL_DEVICE_GENERAL_CONFIGURATION,&pConfigOpt,&pConfigLen,(_u8 *)(&ver));
+ printf("CHIP %d\nMAC 31.%d.%d.%d.%d\nPHY %d.%d.%d.%d\nNWP %d.%d.%d.%d\nROM %d\nHOST %d.%d.%d.%d\n",
+ ver.ChipFwAndPhyVersion.ChipId,
+ ver.ChipFwAndPhyVersion.FwVersion[0],ver.ChipFwAndPhyVersion.FwVersion[1],
+ ver.ChipFwAndPhyVersion.FwVersion[2],ver.ChipFwAndPhyVersion.FwVersion[3],
+ ver.ChipFwAndPhyVersion.PhyVersion[0],ver.ChipFwAndPhyVersion.PhyVersion[1],
+ ver.ChipFwAndPhyVersion.PhyVersion[2],ver.ChipFwAndPhyVersion.PhyVersion[3],
+ ver.NwpVersion[0],ver.NwpVersion[1],ver.NwpVersion[2],ver.NwpVersion[3],
+ ver.RomVersion,
+ SL_MAJOR_VERSION_NUM,SL_MINOR_VERSION_NUM,SL_VERSION_NUM,SL_SUB_VERSION_NUM);
+
+ \endcode
+ \code
+ Getting Device time and date example:
+
+ SlDateTime_t dateTime = {0};
+ _i8 configLen = sizeof(SlDateTime_t);
+ _i8 configOpt = SL_DEVICE_GENERAL_CONFIGURATION_DATE_TIME;
+ sl_DevGet(SL_DEVICE_GENERAL_CONFIGURATION,&configOpt, &configLen,(_u8 *)(&dateTime));
+
+ printf("Day %d,Mon %d,Year %d,Hour %,Min %d,Sec %d\n",dateTime.sl_tm_day,dateTime.sl_tm_mon,dateTime.sl_tm_year
+ dateTime.sl_tm_hour,dateTime.sl_tm_min,dateTime.sl_tm_sec);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_DevGet)
+_i32 sl_DevGet(_u8 DeviceGetId, _u8 *pOption,_u8 *pConfigLen, _u8 *pValues);
+#endif
+
+
+/*!
+ \brief Set asynchronous event mask
+
+ Mask asynchronous events from the device. Masked events do not
+ generate asynchronous messages from the device.
+ By default - all events are active
+
+ \param[in] EventClass The classification groups that the
+ mask is referred to. Need to be one of
+ the following:
+ - SL_EVENT_CLASS_GLOBAL
+ - SL_EVENT_CLASS_DEVICE
+ - SL_EVENT_CLASS_WLAN
+ - SL_EVENT_CLASS_BSD
+ - SL_EVENT_CLASS_NETAPP
+ - SL_EVENT_CLASS_NETCFG
+ - SL_EVENT_CLASS_FS
+
+
+ \param[in] Mask Event Mask bitmap. Valid mask are (per group):
+ - SL_EVENT_CLASS_WLAN user events
+ - SL_WLAN_CONNECT_EVENT
+ - SL_WLAN_DISCONNECT_EVENT
+ - SL_EVENT_CLASS_DEVICE user events
+ - SL_DEVICE_FATAL_ERROR_EVENT
+ - SL_EVENT_CLASS_BSD user events
+ - SL_SOCKET_TX_FAILED_EVENT
+ - SL_SOCKET_ASYNC_EVENT
+ - SL_EVENT_CLASS_NETAPP user events
+ - SL_NETAPP_IPV4_IPACQUIRED_EVENT
+ - SL_NETAPP_IPV6_IPACQUIRED_EVENT
+
+ \return On success, zero is returned. On error, -1 is returned
+
+ \sa sl_EventMaskGet
+
+ \note belongs to \ref ext_api
+
+ \warning
+ \par Example:
+ \code
+
+ An example of masking connection/disconnection async events from WLAN class:
+ sl_EventMaskSet(SL_EVENT_CLASS_WLAN, (SL_WLAN_CONNECT_EVENT | SL_WLAN_DISCONNECT_EVENT) );
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_EventMaskSet)
+_i16 sl_EventMaskSet(_u8 EventClass , _u32 Mask);
+#endif
+
+/*!
+ \brief Get current event mask of the device
+
+ return the events bit mask from the device. In case that event is
+ masked, the device is not sending this event.
+
+ \param[in] EventClass The classification groups that the
+ mask is referred to. Need to be one of
+ the following:
+ - SL_EVENT_CLASS_GLOBAL
+ - SL_EVENT_CLASS_DEVICE
+ - SL_EVENT_CLASS_WLAN
+ - SL_EVENT_CLASS_BSD
+ - SL_EVENT_CLASS_NETAPP
+ - SL_EVENT_CLASS_NETCFG
+ - SL_EVENT_CLASS_FS
+
+ \param[out] pMask Pointer to Mask bitmap where the
+ value should be stored. Bitmasks are the same as in \ref sl_EventMaskSet
+
+ \return On success, zero is returned. On error, -1 is returned
+
+ \sa sl_EventMaskSet
+
+ \note belongs to \ref ext_api
+
+ \warning
+ \par Example:
+ \code
+
+ An example of getting an event mask for WLAN class
+ _u32 maskWlan;
+ sl_StatusGet(SL_EVENT_CLASS_WLAN,&maskWlan);
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_EventMaskGet)
+_i16 sl_EventMaskGet(_u8 EventClass, _u32 *pMask);
+#endif
+
+
+/*!
+ \brief the simple link task entry
+
+ \Param
+ This function must be called from the main loop or from dedicated thread in
+ the following cases:
+ - Non-Os Platform - should be called from the mail loop
+ - Multi Threaded Platform when the user does not implement the external spawn functions -
+ should be called from dedicated thread allocated to the simplelink driver.
+ In this mode the function never return.
+
+ \return None
+
+ \sa sl_Stop
+
+ \note belongs to \ref basic_api
+
+ \warning This function must be called from a thread that is start running before
+ any call to other simple link API
+*/
+#if _SL_INCLUDE_FUNC(sl_Task)
+void sl_Task(void);
+#endif
+
+
+/*!
+ \brief Setting the internal uart mode
+
+ \param[in] pUartParams Pointer to the uart configuration parameter set:
+ baudrate - up to 711 Kbps
+ flow control - enable/disable
+ comm port - the comm port number
+
+ \return On success zero is returned, otherwise - Failed.
+
+ \sa sl_Stop
+
+ \note belongs to \ref basic_api
+
+ \warning This function must consider the host uart capability
+*/
+#ifdef SL_IF_TYPE_UART
+#if _SL_INCLUDE_FUNC(sl_UartSetMode)
+_i16 sl_UartSetMode(const SlUartIfParams_t* pUartParams);
+#endif
+#endif
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __DEVICE_H__ */
+
+
diff --git a/cc3200/simplelink/include/fs.h b/cc3200/simplelink/include/fs.h
new file mode 100644
index 0000000000..094b038138
--- /dev/null
+++ b/cc3200/simplelink/include/fs.h
@@ -0,0 +1,380 @@
+/*
+ * fs.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __FS_H__
+#define __FS_H__
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+
+#include "simplelink.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+
+ \addtogroup FileSystem
+ @{
+
+*/
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+/* FS error codes */
+#define SL_FS_OK (0)
+#define SL_FS_ERR_EMPTY_SFLASH (-67)
+#define SL_FS_ERR_FILE_IS_NOT_SECURE_AND_SIGN (-66)
+#define SL_FS_ERASING_FLASH (-65)
+#define SL_FS_FILE_HAS_NOT_BEEN_CLOSE_CORRECTLY (-64)
+#define SL_FS_WRONG_SIGNATURE (-63)
+#define SL_FS_WRONG_SIGNATURE_OR_CERTIFIC_NAME_LENGTH (-62)
+#define SL_FS_NOT_16_ALIGNED (-61)
+#define SL_FS_CERT_CHAIN_ERROR (-60)
+#define SL_FS_FILE_NAME_EXIST (-59)
+#define SL_FS_SECURITY_BUF_ALREADY_ALLOC (-58)
+#define SL_FS_SECURE_FILE_MUST_BE_COMMIT (-57)
+#define SL_FS_ERR_INCORRECT_OFFSET_ALIGNMENT (-56)
+#define SL_FS_ERR_FAILED_READ_NVMEM_HEADER (-55)
+#define SL_FS_WRONG_FILE_NAME (-54)
+#define SL_FS_FILE_SYSTEM_IS_LOCKED (-53)
+#define SL_FS_SECURITY_ALLERT (-52)
+#define SL_FS_FILE_UNVALID_FILE_SIZE (-51)
+#define SL_FS_ERR_TOKEN_IS_NOT_VALID (-50)
+#define SL_FS_NO_DEVICE_IS_LOADED (-49)
+#define SL_FS_DATA_ADDRESS_SHOUD_BE_IN_DATA_RAM (-48)
+#define SL_FS_DATA_IS_NOT_ALIGNED (-47)
+#define SL_FS_ERR_OVERLAP_DETECTION_THRESHHOLD (-46)
+#define SL_FS_FILE_HAS_RESERVED_NV_INDEX (-45)
+#define SL_FS_ERR_MAX_FS_FILES_IS_LARGER (-44)
+#define SL_FS_ERR_MAX_FS_FILES_IS_SMALLER (-43)
+#define SL_FS_FILE_MAX_SIZE_EXCEEDED (-42)
+#define SL_FS_INVALID_BUFFER_FOR_READ (-41)
+#define SL_FS_INVALID_BUFFER_FOR_WRITE (-40)
+#define SL_FS_ERR_FILE_IMAGE_IS_CORRUPTED (-39)
+#define SL_FS_ERR_SIZE_OF_FILE_EXT_EXCEEDED (-38)
+#define SL_FS_WARNING_FILE_NAME_NOT_KEPT (-37)
+#define SL_FS_ERR_DEVICE_IS_NOT_FORMATTED (-36)
+#define SL_FS_ERR_FAILED_WRITE_NVMEM_HEADER (-35)
+#define SL_FS_ERR_NO_AVAILABLE_NV_INDEX (-34)
+#define SL_FS_ERR_FAILED_TO_ALLOCATE_MEM (-33)
+#define SL_FS_ERR_FAILED_TO_READ_INTEGRITY_HEADER_2 (-32)
+#define SL_FS_ERR_FAILED_TO_READ_INTEGRITY_HEADER_1 (-31)
+#define SL_FS_ERR_NO_AVAILABLE_BLOCKS (-30)
+#define SL_FS_ERR_FILE_MAX_SIZE_BIGGER_THAN_EXISTING_FILE (-29)
+#define SL_FS_ERR_FILE_EXISTS_ON_DIFFERENT_DEVICE_ID (-28)
+#define SL_FS_ERR_INVALID_ACCESS_TYPE (-27)
+#define SL_FS_ERR_FILE_ALREADY_EXISTS (-26)
+#define SL_FS_ERR_PROGRAM (-25)
+#define SL_FS_ERR_NO_ENTRIES_AVAILABLE (-24)
+#define SL_FS_ERR_FILE_ACCESS_IS_DIFFERENT (-23)
+#define SL_FS_ERR_BAD_FILE_MODE (-22)
+#define SL_FS_ERR_FAILED_READ_NVFILE (-21)
+#define SL_FS_ERR_FAILED_INIT_STORAGE (-20)
+#define SL_FS_ERR_CONTINUE_WRITE_MUST_BE_MOD_4 (-19)
+#define SL_FS_ERR_FAILED_LOAD_FILE (-18)
+#define SL_FS_ERR_INVALID_HANDLE (-17)
+#define SL_FS_ERR_FAILED_TO_WRITE (-16)
+#define SL_FS_ERR_OFFSET_OUT_OF_RANGE (-15)
+#define SL_FS_ERR_ALLOC (-14)
+#define SL_FS_ERR_READ_DATA_LENGTH (-13)
+#define SL_FS_ERR_INVALID_FILE_ID (-12)
+#define SL_FS_ERR_FILE_NOT_EXISTS (-11)
+#define SL_FS_ERR_EMPTY_ERROR (-10)
+#define SL_FS_ERR_INVALID_ARGS (-9)
+#define SL_FS_ERR_FAILED_TO_CREATE_FILE (-8)
+#define SL_FS_ERR_FS_ALREADY_LOADED (-7)
+#define SL_FS_ERR_UNKNOWN (-6)
+#define SL_FS_ERR_FAILED_TO_CREATE_LOCK_OBJ (-5)
+#define SL_FS_ERR_DEVICE_NOT_LOADED (-4)
+#define SL_FS_ERR_INVALID_MAGIC_NUM (-3)
+#define SL_FS_ERR_FAILED_TO_READ (-2)
+#define SL_FS_ERR_NOT_SUPPORTED (-1)
+/* end of error codes */
+
+#define _FS_MODE_ACCESS_RESERVED_OFFSET (24)
+#define _FS_MODE_ACCESS_RESERVED_MASK (0xFF)
+#define _FS_MODE_ACCESS_FLAGS_OFFSET (16)
+#define _FS_MODE_ACCESS_FLAGS_MASK (0xFF)
+#define _FS_MODE_ACCESS_OFFSET (12)
+#define _FS_MODE_ACCESS_MASK (0xF)
+#define _FS_MODE_OPEN_SIZE_GRAN_OFFSET (8)
+#define _FS_MODE_OPEN_SIZE_GRAN_MASK (0xF)
+#define _FS_MODE_OPEN_SIZE_OFFSET (0)
+#define _FS_MODE_OPEN_SIZE_MASK (0xFF)
+#define MAX_MODE_SIZE (0xFF)
+#define _FS_MODE(Access, SizeGran, Size,Flags) (_u32)(((_u32)((Access) & _FS_MODE_ACCESS_MASK)<<_FS_MODE_ACCESS_OFFSET) | \
+ ((_u32)((SizeGran) & _FS_MODE_OPEN_SIZE_GRAN_MASK)<<_FS_MODE_OPEN_SIZE_GRAN_OFFSET) | \
+ ((_u32)((Size) & _FS_MODE_OPEN_SIZE_MASK)<<_FS_MODE_OPEN_SIZE_OFFSET) | \
+ ((_u32)((Flags) & _FS_MODE_ACCESS_FLAGS_MASK)<<_FS_MODE_ACCESS_FLAGS_OFFSET))
+
+
+/* sl_FsOpen options */
+/* Open for Read */
+#define FS_MODE_OPEN_READ _FS_MODE(_FS_MODE_OPEN_READ,0,0,0)
+/* Open for Write (in case file exist) */
+#define FS_MODE_OPEN_WRITE _FS_MODE(_FS_MODE_OPEN_WRITE,0,0,0)
+/* Open for Creating a new file */
+#define FS_MODE_OPEN_CREATE(maxSizeInBytes,accessModeFlags) _sl_GetCreateFsMode(maxSizeInBytes,accessModeFlags)
+
+/*****************************************************************************/
+/* Structure/Enum declarations */
+/*****************************************************************************/
+typedef struct
+{
+ _u16 flags;
+ _u32 FileLen;
+ _u32 AllocatedLen;
+ _u32 Token[4];
+}SlFsFileInfo_t;
+
+typedef enum
+{
+ _FS_MODE_OPEN_READ = 0,
+ _FS_MODE_OPEN_WRITE,
+ _FS_MODE_OPEN_CREATE,
+ _FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST
+}SlFsFileOpenAccessType_e;
+
+typedef enum
+{
+ _FS_FILE_OPEN_FLAG_COMMIT = 0x1, /* MIRROR - for fail safe */
+ _FS_FILE_OPEN_FLAG_SECURE = 0x2, /* SECURE */
+ _FS_FILE_OPEN_FLAG_NO_SIGNATURE_TEST = 0x4, /* Relevant to secure file only */
+ _FS_FILE_OPEN_FLAG_STATIC = 0x8, /* Relevant to secure file only */
+ _FS_FILE_OPEN_FLAG_VENDOR = 0x10, /* Relevant to secure file only */
+ _FS_FILE_PUBLIC_WRITE = 0x20, /* Relevant to secure file only, the file can be opened for write without Token */
+ _FS_FILE_PUBLIC_READ = 0x40 /* Relevant to secure file only, the file can be opened for read without Token */
+}SlFileOpenFlags_e;
+
+typedef enum
+{
+ _FS_MODE_SIZE_GRAN_256B = 0, /* MAX_SIZE = 64K */
+ _FS_MODE_SIZE_GRAN_1KB, /* MAX_SIZE = 256K */
+ _FS_MODE_SIZE_GRAN_4KB, /* MAX_SZIE = 1M */
+ _FS_MODE_SIZE_GRAN_16KB, /* MAX_SIZE = 4M */
+ _FS_MODE_SIZE_GRAN_64KB, /* MAX_SIZE = 16M */
+ _FS_MAX_MODE_SIZE_GRAN
+}_SlFsFileOpenMaxSizeGran_e;
+
+/*****************************************************************************/
+/* Internal Function prototypes */
+/*****************************************************************************/
+_u32 _sl_GetCreateFsMode(_u32 maxSizeInBytes,_u32 accessFlags);
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+
+/*!
+ \brief open file for read or write from/to storage device
+
+ \param[in] pFileName File Name buffer pointer
+ \param[in] AccessModeAndMaxSize Options: As described below
+ \param[in] pToken Reserved for future use. Use NULL for this field
+ \param[out] pFileHandle Pointing on the file and used for read and write commands to the file
+
+ AccessModeAndMaxSize possible input \n
+ FS_MODE_OPEN_READ - Read a file \n
+ FS_MODE_OPEN_WRITE - Open for write for an existing file \n
+ FS_MODE_OPEN_CREATE(maxSizeInBytes,accessModeFlags) - Open for creating a new file. Max file size is defined in bytes. \n
+ For optimal FS size, use max size in 4K-512 bytes steps (e.g. 3584,7680,117760) \n
+ Several access modes bits can be combined together from SlFileOpenFlags_e enum
+
+ \return On success, zero is returned. On error, an error code is returned
+
+ \sa sl_FsRead sl_FsWrite sl_FsClose
+ \note belongs to \ref basic_api
+ \warning
+ \par Example:
+ \code
+ char* DeviceFileName = "MyFile.txt";
+ unsigned long MaxSize = 63 * 1024; //62.5K is max file size
+ long DeviceFileHandle = -1;
+ long RetVal; //negative retval is an error
+ unsigned long Offset = 0;
+ unsigned char InputBuffer[100];
+
+ // Create a file and write data. The file in this example is secured, without signature and with a fail safe commit
+ RetVal = sl_FsOpen((unsigned char *)DeviceFileName,
+ FS_MODE_OPEN_CREATE(MaxSize , _FS_FILE_OPEN_FLAG_NO_SIGNATURE_TEST | _FS_FILE_OPEN_FLAG_COMMIT ),
+ NULL, &DeviceFileHandle);
+
+ Offset = 0;
+ //Preferred in secure file that the Offset and the length will be aligned to 16 bytes.
+ RetVal = sl_FsWrite( DeviceFileHandle, Offset, (unsigned char *)"HelloWorld", strlen("HelloWorld"));
+
+ RetVal = sl_FsClose(DeviceFileHandle, NULL, NULL , 0);
+
+ // open the same file for read, using the Token we got from the creation procedure above
+ RetVal = sl_FsOpen((unsigned char *)DeviceFileName,
+ FS_MODE_OPEN_READ,
+ NULL, &DeviceFileHandle);
+
+ Offset = 0;
+ RetVal = sl_FsRead( DeviceFileHandle, Offset, (unsigned char *)InputBuffer, strlen("HelloWorld"));
+
+ RetVal = sl_FsClose(DeviceFileHandle, NULL, NULL , 0);
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_FsOpen)
+_i32 sl_FsOpen(_u8 *pFileName,_u32 AccessModeAndMaxSize,_u32 *pToken,_i32 *pFileHandle);
+#endif
+
+/*!
+ \brief close file in storage device
+
+ \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen)
+ \param[in] pCeritificateFileName Reserved for future use. Use NULL.
+ \param[in] pSignature Reserved for future use. Use NULL.
+ \param[in] SignatureLen Reserved for future use. Use 0.
+
+
+ \return On success, zero is returned. On error, an error code is returned
+
+ \sa sl_FsRead sl_FsWrite sl_FsOpen
+ \note Call the fs_Close with signature = 'A' signature len = 1 for activating an abort action
+ \warning
+ \par Example:
+ \code
+ sl_FsClose(FileHandle,0,0,0);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_FsClose)
+_i16 sl_FsClose(_i32 FileHdl,_u8* pCeritificateFileName,_u8* pSignature,_u32 SignatureLen);
+#endif
+
+/*!
+ \brief Read block of data from a file in storage device
+
+ \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen)
+ \param[in] Offset Offset to specific read block
+ \param[out] pData Pointer for the received data
+ \param[in] Len Length of the received data
+
+ \return On success, returns the number of read bytes. On error, negative number is returned
+
+ \sa sl_FsClose sl_FsWrite sl_FsOpen
+ \note belongs to \ref basic_api
+ \warning
+ \par Example:
+ \code
+ Status = sl_FsRead(FileHandle, 0, &readBuff[0], readSize);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_FsRead)
+_i32 sl_FsRead(_i32 FileHdl,_u32 Offset ,_u8* pData,_u32 Len);
+#endif
+
+/*!
+ \brief write block of data to a file in storage device
+
+ \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen)
+ \param[in] Offset Offset to specific block to be written
+ \param[in] pData Pointer the transmitted data to the storage device
+ \param[in] Len Length of the transmitted data
+
+ \return On success, returns the number of written bytes. On error, an error code is returned
+
+ \sa
+ \note belongs to \ref basic_api
+ \warning
+ \par Example:
+ \code
+ Status = sl_FsWrite(FileHandle, 0, &buff[0], readSize);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_FsWrite)
+_i32 sl_FsWrite(_i32 FileHdl,_u32 Offset,_u8* pData,_u32 Len);
+#endif
+
+/*!
+ \brief get info on a file
+
+ \param[in] pFileName File name
+ \param[in] Token Reserved for future use. Use 0
+ \param[out] pFsFileInfo Returns the File's Information: flags,file size, allocated size and Tokens
+
+ \return On success, zero is returned. On error, an error code is returned
+
+ \sa sl_FsOpen
+ \note belongs to \ref basic_api
+ \warning
+ \par Example:
+ \code
+ Status = sl_FsGetInfo("FileName.html",0,&FsFileInfo);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_FsGetInfo)
+_i16 sl_FsGetInfo(_u8 *pFileName,_u32 Token,SlFsFileInfo_t* pFsFileInfo);
+#endif
+
+/*!
+ \brief Delete specific file from a storage or all files from a storage (format)
+
+ \param[in] pFileName File Name
+ \param[in] Token Reserved for future use. Use 0
+ \return On success, zero is returned. On error, an error code is returned
+
+ \sa
+ \note belongs to \ref basic_api
+ \warning
+ \par Example:
+ \code
+ Status = sl_FsDel("FileName.html",0);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_FsDel)
+_i16 sl_FsDel(_u8 *pFileName,_u32 Token);
+#endif
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __FS_H__ */
+
diff --git a/cc3200/simplelink/include/netapp.h b/cc3200/simplelink/include/netapp.h
new file mode 100644
index 0000000000..f14fd21a1a
--- /dev/null
+++ b/cc3200/simplelink/include/netapp.h
@@ -0,0 +1,845 @@
+/*
+ * netapp.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __NETAPP_H__
+#define __NETAPP_H__
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+
+#include "simplelink.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+
+ \addtogroup netapp
+ @{
+
+*/
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+/*ERROR code*/
+#define SL_ERROR_NETAPP_RX_BUFFER_LENGTH_ERROR (-230)
+
+/* Http Server interface */
+#define MAX_INPUT_STRING (64) /* because of WPA */
+
+#define MAX_AUTH_NAME_LEN (20)
+#define MAX_AUTH_PASSWORD_LEN (20)
+#define MAX_AUTH_REALM_LEN (20)
+
+#define MAX_DEVICE_URN_LEN (15+1)
+#define MAX_DOMAIN_NAME_LEN (24+1)
+
+#define MAX_ACTION_LEN (30)
+/* Important: in case the max len is changed, make sure the struct sl_NetAppHttpServerSendToken_t in protocol.h is padded correctly! */
+#define MAX_TOKEN_NAME_LEN (20)
+#define MAX_TOKEN_VALUE_LEN MAX_INPUT_STRING
+
+#define NETAPP_MAX_SERVICE_TEXT_SIZE (256)
+#define NETAPP_MAX_SERVICE_NAME_SIZE (60)
+#define NETAPP_MAX_SERVICE_HOST_NAME_SIZE (64)
+
+
+/* Server Responses */
+#define SL_NETAPP_RESPONSE_NONE (0)
+#define SL_NETAPP_HTTPSETTOKENVALUE (1)
+
+#define SL_NETAPP_FAMILY_MASK (0x80)
+
+/* mDNS types */
+#define SL_NET_APP_MASK_IPP_TYPE_OF_SERVICE (0x00000001)
+#define SL_NET_APP_MASK_DEVICE_INFO_TYPE_OF_SERVICE (0x00000002)
+#define SL_NET_APP_MASK_HTTP_TYPE_OF_SERVICE (0x00000004)
+#define SL_NET_APP_MASK_HTTPS_TYPE_OF_SERVICE (0x00000008)
+#define SL_NET_APP_MASK_WORKSATION_TYPE_OF_SERVICE (0x00000010)
+#define SL_NET_APP_MASK_GUID_TYPE_OF_SERVICE (0x00000020)
+#define SL_NET_APP_MASK_H323_TYPE_OF_SERVICE (0x00000040)
+#define SL_NET_APP_MASK_NTP_TYPE_OF_SERVICE (0x00000080)
+#define SL_NET_APP_MASK_OBJECITVE_TYPE_OF_SERVICE (0x00000100)
+#define SL_NET_APP_MASK_RDP_TYPE_OF_SERVICE (0x00000200)
+#define SL_NET_APP_MASK_REMOTE_TYPE_OF_SERVICE (0x00000400)
+#define SL_NET_APP_MASK_RTSP_TYPE_OF_SERVICE (0x00000800)
+#define SL_NET_APP_MASK_SIP_TYPE_OF_SERVICE (0x00001000)
+#define SL_NET_APP_MASK_SMB_TYPE_OF_SERVICE (0x00002000)
+#define SL_NET_APP_MASK_SOAP_TYPE_OF_SERVICE (0x00004000)
+#define SL_NET_APP_MASK_SSH_TYPE_OF_SERVICE (0x00008000)
+#define SL_NET_APP_MASK_TELNET_TYPE_OF_SERVICE (0x00010000)
+#define SL_NET_APP_MASK_TFTP_TYPE_OF_SERVICE (0x00020000)
+#define SL_NET_APP_MASK_XMPP_CLIENT_TYPE_OF_SERVICE (0x00040000)
+#define SL_NET_APP_MASK_RAOP_TYPE_OF_SERVICE (0x00080000)
+#define SL_NET_APP_MASK_ALL_TYPE_OF_SERVICE (0xFFFFFFFF)
+
+/********************************************************************************************************/
+/* sl_NetAppDnsGetHostByName error codes */
+
+#define SL_NET_APP_DNS_QUERY_NO_RESPONSE (-159) /* DNS query failed, no response */
+#define SL_NET_APP_DNS_NO_SERVER (-161) /* No DNS server was specified */
+#define SL_NET_APP_DNS_PARAM_ERROR (-162) /* mDNS parameters error */
+#define SL_NET_APP_DNS_QUERY_FAILED (-163) /* DNS query failed; no DNS server sent an 'answer' */
+#define SL_NET_APP_DNS_INTERNAL_1 (-164)
+#define SL_NET_APP_DNS_INTERNAL_2 (-165)
+#define SL_NET_APP_DNS_MALFORMED_PACKET (-166) /* Improperly formed or corrupted DNS packet received */
+#define SL_NET_APP_DNS_INTERNAL_3 (-167)
+#define SL_NET_APP_DNS_INTERNAL_4 (-168)
+#define SL_NET_APP_DNS_INTERNAL_5 (-169)
+#define SL_NET_APP_DNS_INTERNAL_6 (-170)
+#define SL_NET_APP_DNS_INTERNAL_7 (-171)
+#define SL_NET_APP_DNS_INTERNAL_8 (-172)
+#define SL_NET_APP_DNS_INTERNAL_9 (-173)
+#define SL_NET_APP_DNS_MISMATCHED_RESPONSE (-174) /* Server response type does not match the query request*/
+#define SL_NET_APP_DNS_INTERNAL_10 (-175)
+#define SL_NET_APP_DNS_INTERNAL_11 (-176)
+#define SL_NET_APP_DNS_NO_ANSWER (-177) /* No response for one-shot query */
+#define SL_NET_APP_DNS_NO_KNOWN_ANSWER (-178) /* No known answer for query */
+#define SL_NET_APP_DNS_NAME_MISMATCH (-179) /* Illegal service name according to the RFC */
+#define SL_NET_APP_DNS_NOT_STARTED (-180) /* mDNS is not running */
+#define SL_NET_APP_DNS_HOST_NAME_ERROR (-181) /* Host name error. Host name format is not allowed according to RFC 1033,1034,1035, 6763 */
+#define SL_NET_APP_DNS_NO_MORE_ENTRIES (-182) /* No more entries be found. */
+
+#define SL_NET_APP_DNS_MAX_SERVICES_ERROR (-200) /* Maximum advertise services are already configured */
+#define SL_NET_APP_DNS_IDENTICAL_SERVICES_ERROR (-201) /* Trying to register a service that is already exists */
+#define SL_NET_APP_DNS_NOT_EXISTED_SERVICE_ERROR (-203) /* Trying to delete service that does not existed */
+#define SL_NET_APP_DNS_ERROR_SERVICE_NAME_ERROR (-204) /* Illegal service name according to the RFC */
+#define SL_NET_APP_DNS_RX_PACKET_ALLOCATION_ERROR (-205) /* Retry request */
+#define SL_NET_APP_DNS_BUFFER_SIZE_ERROR (-206) /* List size buffer is bigger than internally allowed in the NWP */
+#define SL_NET_APP_DNS_NET_APP_SET_ERROR (-207) /* Illegal length of one of the mDNS Set functions */
+#define SL_NET_APP_DNS_GET_SERVICE_LIST_FLAG_ERROR (-208)
+#define SL_NET_APP_DNS_NO_CONFIGURATION_ERROR (-209)
+
+/* Set Dev name error codes (NETAPP_SET_GET_DEV_CONF_OPT_DEVICE_URN) */
+#define SL_ERROR_DEVICE_NAME_LEN_ERR (-117)
+#define SL_ERROR_DEVICE_NAME_INVALID (-118)
+/* Set domain name error codes (NETAPP_SET_GET_DEV_CONF_OPT_DOMAIN_NAME) */
+#define SL_ERROR_DOMAIN_NAME_LEN_ERR (-119)
+#define SL_ERROR_DOMAIN_NAME_INVALID (-120)
+
+/********************************************************************************************************/
+
+/* NetApp application IDs */
+#define SL_NET_APP_HTTP_SERVER_ID (1)
+#define SL_NET_APP_DHCP_SERVER_ID (2)
+#define SL_NET_APP_MDNS_ID (4)
+#define SL_NET_APP_DNS_SERVER_ID (8)
+#define SL_NET_APP_DEVICE_CONFIG_ID (16)
+/* NetApp application set/get options */
+#define NETAPP_SET_DHCP_SRV_BASIC_OPT (0)
+/* HTTP server set/get options */
+#define NETAPP_SET_GET_HTTP_OPT_PORT_NUMBER (0)
+#define NETAPP_SET_GET_HTTP_OPT_AUTH_CHECK (1)
+#define NETAPP_SET_GET_HTTP_OPT_AUTH_NAME (2)
+#define NETAPP_SET_GET_HTTP_OPT_AUTH_PASSWORD (3)
+#define NETAPP_SET_GET_HTTP_OPT_AUTH_REALM (4)
+#define NETAPP_SET_GET_HTTP_OPT_ROM_PAGES_ACCESS (5)
+
+#define NETAPP_SET_GET_MDNS_CONT_QUERY_OPT (1)
+#define NETAPP_SET_GET_MDNS_QEVETN_MASK_OPT (2)
+#define NETAPP_SET_GET_MDNS_TIMING_PARAMS_OPT (3)
+
+/* DNS server set/get options */
+#define NETAPP_SET_GET_DNS_OPT_DOMAIN_NAME (0)
+
+/* Device Config set/get options */
+#define NETAPP_SET_GET_DEV_CONF_OPT_DEVICE_URN (0)
+#define NETAPP_SET_GET_DEV_CONF_OPT_DOMAIN_NAME (1)
+
+
+/*****************************************************************************/
+/* Structure/Enum declarations */
+/*****************************************************************************/
+
+typedef struct
+{
+ _u32 PacketsSent;
+ _u32 PacketsReceived;
+ _u16 MinRoundTime;
+ _u16 MaxRoundTime;
+ _u16 AvgRoundTime;
+ _u32 TestTime;
+}SlPingReport_t;
+
+typedef struct
+{
+ _u32 PingIntervalTime; /* delay between pings, in milliseconds */
+ _u16 PingSize; /* ping packet size in bytes */
+ _u16 PingRequestTimeout; /* timeout time for every ping in milliseconds */
+ _u32 TotalNumberOfAttempts; /* max number of ping requests. 0 - forever */
+ _u32 Flags; /* flag - 0 report only when finished, 1 - return response for every ping, 2 - stop after 1 successful ping. */
+ _u32 Ip; /* IPv4 address or IPv6 first 4 bytes */
+ _u32 Ip1OrPaadding;
+ _u32 Ip2OrPaadding;
+ _u32 Ip3OrPaadding;
+}SlPingStartCommand_t;
+
+typedef struct _slHttpServerString_t
+{
+ _u8 len;
+ _u8 *data;
+} slHttpServerString_t;
+
+typedef struct _slHttpServerData_t
+{
+ _u8 value_len;
+ _u8 name_len;
+ _u8 *token_value;
+ _u8 *token_name;
+} slHttpServerData_t;
+
+typedef struct _slHttpServerPostData_t
+{
+ slHttpServerString_t action;
+ slHttpServerString_t token_name;
+ slHttpServerString_t token_value;
+}slHttpServerPostData_t;
+
+typedef union
+{
+ slHttpServerString_t httpTokenName; /* SL_NETAPP_HTTPGETTOKENVALUE */
+ slHttpServerPostData_t httpPostData; /* SL_NETAPP_HTTPPOSTTOKENVALUE */
+} SlHttpServerEventData_u;
+
+typedef union
+{
+ slHttpServerString_t token_value;
+} SlHttpServerResponsedata_u;
+
+typedef struct
+{
+ _u32 Event;
+ SlHttpServerEventData_u EventData;
+}SlHttpServerEvent_t;
+
+typedef struct
+{
+ _u32 Response;
+ SlHttpServerResponsedata_u ResponseData;
+}SlHttpServerResponse_t;
+
+
+typedef struct
+{
+ _u32 lease_time;
+ _u32 ipv4_addr_start;
+ _u32 ipv4_addr_last;
+}SlNetAppDhcpServerBasicOpt_t;
+
+/*mDNS parameters*/
+typedef enum
+{
+ SL_NET_APP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE = 1,
+ SL_NET_APP_FULL_SERVICE_IPV4_TYPE,
+ SL_NET_APP_SHORT_SERVICE_IPV4_TYPE
+
+} SlNetAppGetServiceListType_e;
+
+typedef struct
+{
+ _u32 service_ipv4;
+ _u16 service_port;
+ _u16 Reserved;
+}SlNetAppGetShortServiceIpv4List_t;
+
+typedef struct
+{
+ _u32 service_ipv4;
+ _u16 service_port;
+ _u16 Reserved;
+ _u8 service_name[NETAPP_MAX_SERVICE_NAME_SIZE];
+ _u8 service_host[NETAPP_MAX_SERVICE_HOST_NAME_SIZE];
+}SlNetAppGetFullServiceIpv4List_t;
+
+typedef struct
+{
+ _u32 service_ipv4;
+ _u16 service_port;
+ _u16 Reserved;
+ _u8 service_name[NETAPP_MAX_SERVICE_NAME_SIZE];
+ _u8 service_host[NETAPP_MAX_SERVICE_HOST_NAME_SIZE];
+ _u8 service_text[NETAPP_MAX_SERVICE_TEXT_SIZE];
+}SlNetAppGetFullServiceWithTextIpv4List_t;
+
+typedef struct
+{
+ /*The below parameters are used to configure the advertise times and interval
+ For example:
+ If:
+ Period is set to T
+ Repetitions are set to P
+ Telescopic factor is K=2
+ The transmission shall be:
+ advertise P times
+ wait T
+ advertise P times
+ wait 4 * T
+ advertise P time
+ wait 16 * T ... (till max time reached / configuration changed / query issued)
+ */
+ _u32 t; /* Number of ticks for the initial period. Default is 100 ticks for 1 second. */
+ _u32 p; /* Number of repetitions. Default value is 1 */
+ _u32 k; /* Telescopic factor. Default value is 2. */
+ _u32 RetransInterval;/* Announcing retransmission interval */
+ _u32 Maxinterval; /* Announcing max period interval */
+ _u32 max_time; /* Announcing max time */
+}SlNetAppServiceAdvertiseTimingParameters_t;
+
+/*****************************************************************************/
+/* Types declarations */
+/*****************************************************************************/
+typedef void (*P_SL_DEV_PING_CALLBACK)(SlPingReport_t*);
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+
+
+/*!
+ \brief Starts a network application
+
+ Gets and starts network application for the current WLAN mode
+
+ \param[in] AppBitMap application bitmap, could be one or combination of the following: \n
+ - SL_NET_APP_HTTP_SERVER_ID
+ - SL_NET_APP_DHCP_SERVER_ID
+ - SL_NET_APP_MDNS_ID
+
+ \return On error, negative number is returned
+
+ \sa Stop one or more the above started applications using sl_NetAppStop
+ \note This command activates the application for the current WLAN mode (AP or STA)
+ \warning
+ \par Example:
+ \code
+ For example: Starting internal HTTP server + DHCP server:
+ sl_NetAppStart(SL_NET_APP_HTTP_SERVER_ID | SL_NET_APP_DHCP_SERVER_ID)
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppStart)
+_i16 sl_NetAppStart(_u32 AppBitMap);
+#endif
+/*!
+ \brief Stops a network application
+
+ Gets and stops network application for the current WLAN mode
+
+ \param[in] AppBitMap application id, could be one of the following: \n
+ - SL_NET_APP_HTTP_SERVER_ID
+ - SL_NET_APP_DHCP_SERVER_ID
+ - SL_NET_APP_MDNS_ID
+
+ \return On error, negative number is returned
+
+ \sa
+ \note This command disables the application for the current active WLAN mode (AP or STA)
+ \warning
+ \par Example:
+ \code
+
+ For example: Stopping internal HTTP server:
+ sl_NetAppStop(SL_NET_APP_HTTP_SERVER_ID);
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppStop)
+_i16 sl_NetAppStop(_u32 AppBitMap);
+#endif
+
+/*!
+ \brief Get host IP by name
+
+ Obtain the IP Address of machine on network, by machine name.
+
+ \param[in] hostname host name
+ \param[in] usNameLen name length
+ \param[out] out_ip_addr This parameter is filled in with
+ host IP address. In case that host name is not
+ resolved, out_ip_addr is zero.
+ \param[in] family protocol family
+
+ \return On success, 0 is returned.
+ On error, negative is returned
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+ Possible DNS error codes:
+ - SL_NET_APP_DNS_QUERY_NO_RESPONSE
+ - SL_NET_APP_DNS_NO_SERVER
+ - SL_NET_APP_DNS_QUERY_FAILED
+ - SL_NET_APP_DNS_MALFORMED_PACKET
+ - SL_NET_APP_DNS_MISMATCHED_RESPONSE
+
+ \sa
+ \note Only one sl_NetAppDnsGetHostByName can be handled at a time.
+ Calling this API while the same command is called from another thread, may result
+ in one of the two scenarios:
+ 1. The command will wait (internal) until the previous command finish, and then be executed.
+ 2. There are not enough resources and POOL_IS_EMPTY error will return.
+ In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try
+ again later to issue the command.
+ \warning
+ \par Example:
+ \code
+ _u32 DestinationIP;
+ sl_NetAppDnsGetHostByName("www.google.com", strlen("www.google.com"), &DestinationIP,SL_AF_INET);
+
+ Addr.sin_family = SL_AF_INET;
+ Addr.sin_port = sl_Htons(80);
+ Addr.sin_addr.s_addr = sl_Htonl(DestinationIP);
+ AddrSize = sizeof(SlSockAddrIn_t);
+ SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName)
+_i16 sl_NetAppDnsGetHostByName(_i8 * hostname, _u16 usNameLen, _u32* out_ip_addr,_u8 family );
+#endif
+
+/*!
+ \brief Return service attributes like IP address, port and text according to service name
+ \par
+ The user sets a service name Full/Part (see example below), and should get:
+ - IP of service
+ - The port of service
+ - The text of service
+
+ Hence it can make a connection to the specific service and use it.
+ It is similar to get host by name method.
+ It is done by a single shot query with PTR type on the service name.
+ The command that is sent is from constant parameters and variables parameters.
+
+ \param[in] pService Service name can be full or partial. \n
+ Example for full service name:
+ 1. PC1._ipp._tcp.local
+ 2. PC2_server._ftp._tcp.local \n
+ .
+ Example for partial service name:
+ 1. _ipp._tcp.local
+ 2. _ftp._tcp.local
+
+ \param[in] ServiceLen The length of the service name (in_pService).
+ \param[in] Family IPv4 or IPv6 (SL_AF_INET , SL_AF_INET6).
+ \param[out] pAddr Contains the IP address of the service.
+ \param[out] pPort Contains the port of the service.
+ \param[out] pTextLen Has 2 options. One as Input field and the other one as output:
+ - Input: \n
+ Contains the max length of the text that the user wants to get.\n
+ It means that if the text len of service is bigger that its value than
+ the text is cut to inout_TextLen value.
+ - Output: \n
+ Contain the length of the text that is returned. Can be full text or part of the text (see above).
+
+ \param[out] pOut_pText Contains the text of the service full or partial
+
+ \return On success, zero is returned
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+ In case No service is found error SL_NET_APP_DNS_NO_ANSWER will be returned
+
+ \note The returns attributes belongs to the first service found.
+ There may be other services with the same service name that will response to the query.
+ The results of these responses are saved in the peer cache of the Device and should be read by another API.
+
+ Only one sl_NetAppDnsGetHostByService can be handled at a time.
+ Calling this API while the same command is called from another thread, may result
+ in one of the two scenarios:
+ 1. The command will wait (internal) until the previous command finish, and then be executed.
+ 2. There are not enough resources and SL_POOL_IS_EMPTY error will return.
+ In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try
+ again later to issue the command.
+
+ \warning Text length can be 120 bytes only
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService)
+_i32 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */
+ _u8 ServiceLen,
+ _u8 Family, /* 4-IPv4 , 16-IPv6 */
+ _u32 pAddr[],
+ _u32 *pPort,
+ _u16 *pTextLen, /* in: max len , out: actual len */
+ _i8 *pText
+ );
+
+#endif
+
+/*!
+ \brief Get service List
+ Insert into out pBuffer a list of peer's services that are the NWP.
+ The list is in a form of service struct. The user should chose the type
+ of the service struct like:
+ - Full service parameters with text.
+ - Full service parameters.
+ - Short service parameters (port and IP only) especially for tiny hosts.
+
+ The different types of struct are made to give the
+ Possibility to save memory in the host
+
+
+ The user also chose how many max services to get and start point index
+ NWP peer cache.
+ For example:
+ 1. Get max of 3 full services from index 0.Up to 3 full services
+ from index 0 are inserted into pBuffer (services that are in indexes 0,1,2).
+ 2. Get max of 4 full services from index 3.Up to 4 full services
+ from index 3 are inserted into pBuffer (services that are in indexes 3,4,5,6).
+ 3. Get max of 2 int services from index 6.Up to 2 int services
+ from index 6 are inserted into pBuffer (services that are in indexes 6,7).
+
+ See below - command parameters.
+
+ \param[in] indexOffset - The start index in the peer cache that from it the first service is returned.
+ \param[in] MaxServiceCount - The Max services that can be returned if existed or if not exceed the max index
+ in the peer cache
+ \param[in] Flags - an ENUM number that means which service struct to use (means which types of service to fill)
+ - use SlNetAppGetFullServiceWithTextIpv4List_t
+ - use SlNetAppGetFullServiceIpv4List_t
+ - use SlNetAppGetShortServiceIpv4List_t
+
+ \param[out] Buffer - The Services are inserted into this buffer. In the struct form according to the bit that is set in the Flags
+ input parameter.
+
+ \return ServiceFoundCount - The number of the services that were inserted into the buffer. zero means no service is found
+ negative number means an error
+ \sa sl_NetAppMDNSRegisterService
+ \note
+ \warning
+ if the out pBuffer size is bigger than an RX packet(1480), than
+ an error is returned because there
+ is no place in the RX packet.
+ The size is a multiply of MaxServiceCount and size of service struct(that is set
+ according to flag value).
+*/
+
+#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList)
+_i16 sl_NetAppGetServiceList(_u8 IndexOffest,
+ _u8 MaxServiceCount,
+ _u8 Flags,
+ _i8 *pBuffer,
+ _u32 RxBufferLength
+ );
+
+#endif
+
+/*!
+ \brief Unregister mDNS service
+ This function deletes the mDNS service from the mDNS package and the database.
+
+ The mDNS service that is to be unregistered is a service that the application no longer wishes to provide. \n
+ The service name should be the full service name according to RFC
+ of the DNS-SD - meaning the value in name field in the SRV answer.
+
+ Examples for service names:
+ 1. PC1._ipp._tcp.local
+ 2. PC2_server._ftp._tcp.local
+
+ \param[in] pServiceName Full service name. \n
+ Example for service name:
+ 1. PC1._ipp._tcp.local
+ 2. PC2_server._ftp._tcp.local
+ \param[in] ServiceLen The length of the service.
+ \return On success, zero is returned
+ \sa sl_NetAppMDNSRegisterService
+ \note
+ \warning
+ The size of the service length should be smaller than 255.
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService)
+_i16 sl_NetAppMDNSUnRegisterService(const _i8 *pServiceName,_u8 ServiceNameLen);
+#endif
+
+/*!
+ \brief Register a new mDNS service
+ \par
+ This function registers a new mDNS service to the mDNS package and the DB.
+
+ This registered service is a service offered by the application.
+ The service name should be full service name according to RFC
+ of the DNS-SD - meaning the value in name field in the SRV answer.
+ Example for service name:
+ 1. PC1._ipp._tcp.local
+ 2. PC2_server._ftp._tcp.local
+
+ If the option is_unique is set, mDNS probes the service name to make sure
+ it is unique before starting to announce the service on the network.
+ Instance is the instance portion of the service name.
+
+ \param[in] ServiceLen The length of the service.
+ \param[in] TextLen The length of the service should be smaller than 64.
+ \param[in] port The port on this target host port.
+ \param[in] TTL The TTL of the service
+ \param[in] Options bitwise parameters: \n
+ - bit 0 - service is unique (means that the service needs to be unique)
+ - bit 31 - for internal use if the service should be added or deleted (set means ADD).
+ - bit 1-30 for future.
+
+ \param[in] pServiceName The service name.
+ Example for service name: \n
+ 1. PC1._ipp._tcp.local
+ 2. PC2_server._ftp._tcp.local
+
+ \param[in] pText The description of the service.
+ should be as mentioned in the RFC
+ (according to type of the service IPP,FTP...)
+
+ \return On success, zero is returned
+ Possible error codes:
+ - Maximum advertise services are already configured.
+ Delete another existed service that is registered and then register again the new service
+ - Trying to register a service that is already exists
+ - Trying to delete service that does not existed
+ - Illegal service name according to the RFC
+ - Retry request
+ - Illegal length of one of the mDNS Set functions
+ - mDNS is not operational as the device has no IP.Connect the device to an AP to get an IP address.
+ - mDNS parameters error
+ - mDNS internal cache error
+ - mDNS internal error
+ - Adding a service is not allowed as it is already exist (duplicate service)
+ - mDNS is not running
+ - Host name error. Host name format is not allowed according to RFC 1033,1034,1035, 6763
+ - List size buffer is bigger than internally allowed in the NWP (API get service list),
+ change the APIs’ parameters to decrease the size of the list
+
+
+ \sa sl_NetAppMDNSUnRegisterService
+
+ \warning 1) Temporary - there is an allocation on stack of internal buffer.
+ Its size is NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. \n
+ It means that the sum of the text length and service name length cannot be bigger than
+ NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.\n
+ If it is - An error is returned. \n
+ 2) According to now from certain constraints the variables parameters are set in the
+ attribute part (contain constant parameters)
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService)
+_i16 sl_NetAppMDNSRegisterService( const _i8* pServiceName,
+ _u8 ServiceNameLen,
+ const _i8* pText,
+ _u8 TextLen,
+ _u16 Port,
+ _u32 TTL,
+ _u32 Options);
+#endif
+
+/*!
+ \brief send ICMP ECHO_REQUEST to network hosts
+
+ Ping uses the ICMP protocol's mandatory ECHO_REQUEST
+
+ \param[in] pPingParams Pointer to the ping request structure: \n
+ - if flags parameter is set to 0, ping will report back once all requested pings are done (as defined by TotalNumberOfAttempts). \n
+ - if flags parameter is set to 1, ping will report back after every ping, for TotalNumberOfAttempts.
+ - if flags parameter is set to 2, ping will stop after the first successful ping, and report back for the successful ping, as well as any preceding failed ones.
+ For stopping an ongoing ping activity, set parameters IP address to 0
+
+ \param[in] family SL_AF_INET or SL_AF_INET6
+ \param[out] pReport Ping pReport
+ \param[out] pCallback Callback function upon completion.
+ If callback is NULL, the API is blocked until data arrives
+
+
+ \return On success, zero is returned. On error, -1 is returned
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+
+ \sa sl_NetAppPingReport
+ \note Only one sl_NetAppPingStart can be handled at a time.
+ Calling this API while the same command is called from another thread, may result
+ in one of the two scenarios:
+ 1. The command will wait (internal) until the previous command finish, and then be executed.
+ 2. There are not enough resources and SL_POOL_IS_EMPTY error will return.
+ In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try
+ again later to issue the command.
+ \warning
+ \par Example:
+ \code
+
+ An example of sending 20 ping requests and reporting results to a callback routine when
+ all requests are sent:
+
+ // callback routine
+ void pingRes(SlPingReport_t* pReport)
+ {
+ // handle ping results
+ }
+
+ // ping activation
+ void PingTest()
+ {
+ SlPingReport_t report;
+ SlPingStartCommand_t pingCommand;
+
+ pingCommand.Ip = SL_IPV4_VAL(10,1,1,200); // destination IP address is 10.1.1.200
+ pingCommand.PingSize = 150; // size of ping, in bytes
+ pingCommand.PingIntervalTime = 100; // delay between pings, in milliseconds
+ pingCommand.PingRequestTimeout = 1000; // timeout for every ping in milliseconds
+ pingCommand.TotalNumberOfAttempts = 20; // max number of ping requests. 0 - forever
+ pingCommand.Flags = 0; // report only when finished
+
+ sl_NetAppPingStart( &pingCommand, SL_AF_INET, &report, pingRes ) ;
+ }
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppPingStart)
+_i16 sl_NetAppPingStart(SlPingStartCommand_t* pPingParams,_u8 family,SlPingReport_t *pReport,const P_SL_DEV_PING_CALLBACK pPingCallback);
+#endif
+
+/*!
+ \brief Internal function for setting network application configurations
+
+ \return On success, zero is returned. On error, -1 is
+ returned
+
+ \param[in] AppId Application id, could be one of the following: \n
+ - SL_NET_APP_HTTP_SERVER_ID
+ - SL_NET_APP_DHCP_SERVER_ID
+ - SL_NET_APP_DHCP_SERVER_ID
+
+ \param[in] SetOptions set option, could be one of the following: \n
+ NETAPP_SET_BASIC_OPT
+
+ \param[in] OptionLen option structure length
+
+ \param[in] pOptionValues pointer to the option structure
+ \sa
+ \note
+ \warning
+ \par
+ \code
+ Set DHCP Server (AP mode) parameters example:
+
+ SlNetAppDhcpServerBasicOpt_t dhcpParams;
+ _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t);
+ dhcpParams.lease_time = 4096; // lease time (in seconds) of the IP Address
+ dhcpParams.ipv4_addr_start = SL_IPV4_VAL(192,168,1,10); // first IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1)
+ dhcpParams.ipv4_addr_last = SL_IPV4_VAL(192,168,1,16); // last IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1)
+ sl_NetAppStop(SL_NET_APP_DHCP_SERVER_ID); // Stop DHCP server before settings
+ sl_NetAppSet(SL_NET_APP_DHCP_SERVER_ID, NETAPP_SET_DHCP_SRV_BASIC_OPT, outLen, (_u8* )&dhcpParams); // set parameters
+ sl_NetAppStart(SL_NET_APP_DHCP_SERVER_ID); // Start DHCP server with new settings
+ \endcode
+ \code
+ Set Device URN name example:
+
+ Device name, maximum length of 33 characters
+ Device name affects URN name, own SSID name in AP mode, and WPS file "device name" in WPS I.E (STA-WPS / P2P)
+ In case no device URN name set, the default name is "mysimplelink"
+ Allowed characters in device name are: 'a - z' , 'A - Z' , '0-9' and '-'
+
+ _u8 *my_device = "MY-SIMPLELINK-DEV";
+ sl_NetAppSet (SL_NET_APP_DEVICE_CONFIG_ID, NETAPP_SET_GET_DEV_CONF_OPT_DEVICE_URN, strlen(my_device), (_u8 *) my_device);
+ \endcode
+
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppSet)
+_i32 sl_NetAppSet(_u8 AppId ,_u8 Option,_u8 OptionLen, _u8 *pOptionValue);
+#endif
+
+/*!
+ \brief Internal function for getting network applications configurations
+
+ \return On success, zero is returned. On error, -1 is
+ returned
+
+ \param[in] AppId Application id, could be one of the following: \n
+ - SL_NET_APP_HTTP_SERVER_ID
+ - SL_NET_APP_DHCP_SERVER_ID
+
+ \param[in] Options Get option, could be one of the following: \n
+ NETAPP_SET_BASIC_OPT
+
+ \param[in] OptionLen The length of the allocated memory as input, when the
+ function complete, the value of this parameter would be
+ the len that actually read from the device.
+ If the device return length that is longer from the input
+ value, the function will cut the end of the returned structure
+ and will return ESMALLBUF
+
+ \param[out] pValues pointer to the option structure which will be filled with the response from the device
+
+ \sa
+ \note
+ \warning
+ \par
+ \code
+ Get DHCP Server parameters example:
+
+ SlNetAppDhcpServerBasicOpt_t dhcpParams;
+ _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t);
+ sl_NetAppGet(SL_NET_APP_DHCP_SERVER_ID, NETAPP_SET_DHCP_SRV_BASIC_OPT, &outLen, (_u8* )&dhcpParams);
+
+ printf("DHCP Start IP %d.%d.%d.%d End IP %d.%d.%d.%d Lease time seconds %d\n",
+ SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,2),
+ SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,0),
+ SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,2),
+ SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,0),
+ dhcpParams.lease_time);
+ \endcode
+ \code
+ Get Device URN name example:
+ Maximum length of 33 characters of device name.
+ Device name affects URN name, own SSID name in AP mode, and WPS file "device name" in WPS I.E (STA-WPS / P2P)
+ in case no device URN name set, the default name is "mysimplelink"
+
+ _u8 my_device_name[35];
+ sl_NetAppGet (SL_NET_APP_DEVICE_CONFIG_ID, NETAPP_SET_GET_DEV_CONF_OPT_DEVICE_URN, strlen(my_device_name), (_u8 *)my_device_name);
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_NetAppGet)
+_i32 sl_NetAppGet(_u8 AppId, _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue);
+#endif
+
+
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __NETAPP_H__ */
+
diff --git a/cc3200/simplelink/include/netcfg.h b/cc3200/simplelink/include/netcfg.h
new file mode 100644
index 0000000000..8014f062a1
--- /dev/null
+++ b/cc3200/simplelink/include/netcfg.h
@@ -0,0 +1,281 @@
+/*
+ * netcfg.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __NETCFG_H__
+#define __NETCFG_H__
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/*!
+
+ \addtogroup netcfg
+ @{
+
+*/
+
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+#define SL_MAC_ADDR_LEN (6)
+#define SL_IPV4_VAL(add_3,add_2,add_1,add_0) ((((_u32)add_3 << 24) & 0xFF000000) | (((_u32)add_2 << 16) & 0xFF0000) | (((_u32)add_1 << 8) & 0xFF00) | ((_u32)add_0 & 0xFF) )
+#define SL_IPV4_BYTE(val,index) ( (val >> (index*8)) & 0xFF )
+
+#define IPCONFIG_MODE_DISABLE_IPV4 (0)
+#define IPCONFIG_MODE_ENABLE_IPV4 (1)
+
+/*****************************************************************************/
+/* Structure/Enum declarations */
+/*****************************************************************************/
+typedef enum
+{
+ SL_MAC_ADDRESS_SET = 1,
+ SL_MAC_ADDRESS_GET = 2,
+ SL_IPV4_STA_P2P_CL_GET_INFO = 3,
+ SL_IPV4_STA_P2P_CL_DHCP_ENABLE = 4,
+ SL_IPV4_STA_P2P_CL_STATIC_ENABLE = 5,
+ SL_IPV4_AP_P2P_GO_GET_INFO = 6,
+ SL_IPV4_AP_P2P_GO_STATIC_ENABLE = 7,
+ SL_SET_HOST_RX_AGGR = 8,
+ MAX_SETTINGS = 0xFF
+}Sl_NetCfg_e;
+
+
+typedef struct
+{
+ _u32 ipV4;
+ _u32 ipV4Mask;
+ _u32 ipV4Gateway;
+ _u32 ipV4DnsServer;
+}SlNetCfgIpV4Args_t;
+
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+
+/*!
+ \brief Internal function for setting network configurations
+
+ \return On success, zero is returned. On error, -1 is
+ returned
+
+ \param[in] ConfigId configuration id
+ \param[in] ConfigOpt configurations option
+ \param[in] ConfigLen configurations len
+ \param[in] pValues configurations values
+
+ \sa
+ \note
+ \warning
+
+ \par Examples:
+ \code
+ SL_MAC_ADDRESS_SET:
+
+ Setting MAC address to the Device.
+ The new MAC address will override the default MAC address and it be saved in the FileSystem.
+ Requires restarting the device for updating this setting.
+
+ _u8 MAC_Address[6];
+ MAC_Address[0] = 0x8;
+ MAC_Address[1] = 0x0;
+ MAC_Address[2] = 0x28;
+ MAC_Address[3] = 0x22;
+ MAC_Address[4] = 0x69;
+ MAC_Address[5] = 0x31;
+ sl_NetCfgSet(SL_MAC_ADDRESS_SET,1,SL_MAC_ADDR_LEN,(_u8 *)newMacAddress);
+ sl_Stop(0);
+ sl_Start(NULL,NULL,NULL);
+ \endcode
+
+ \code
+ SL_IPV4_STA_P2P_CL_STATIC_ENABLE:
+
+ Setting a static IP address to the device working in STA mode or P2P client.
+ The IP address will be stored in the FileSystem.
+ In order to disable the static IP and get the address assigned from DHCP one should use SL_STA_P2P_CL_IPV4_DHCP_SET
+
+ SlNetCfgIpV4Args_t ipV4;
+ ipV4.ipV4 = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address
+ ipV4.ipV4Mask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this STA/P2P
+ ipV4.ipV4Gateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address
+ ipV4.ipV4DnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address
+
+ sl_NetCfgSet(SL_IPV4_STA_P2P_CL_STATIC_ENABLE,IPCONFIG_MODE_ENABLE_IPV4,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4);
+ sl_Stop(0);
+ sl_Start(NULL,NULL,NULL);
+ \endcode
+
+ \code
+ SL_IPV4_STA_P2P_CL_DHCP_ENABLE:
+
+ Setting IP address by DHCP to FileSystem using WLAN sta mode or P2P client.
+ This should be done once if using Serial Flash.
+ This is the system's default mode for acquiring an IP address after WLAN connection.
+ _u8 val = 1;
+ sl_NetCfgSet(SL_IPV4_STA_P2P_CL_DHCP_ENABLE,IPCONFIG_MODE_ENABLE_IPV4,1,&val);
+ sl_Stop(0);
+ sl_Start(NULL,NULL,NULL);
+ \endcode
+
+ \code
+ SL_IPV4_AP_P2P_GO_STATIC_ENABLE:
+
+ Setting a static IP address to the device working in AP mode or P2P go.
+ The IP address will be stored in the FileSystem. Requires restart.
+
+ SlNetCfgIpV4Args_t ipV4;
+ ipV4.ipV4 = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address
+ ipV4.ipV4Mask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this AP/P2P
+ ipV4.ipV4Gateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address
+ ipV4.ipV4DnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address
+
+ sl_NetCfgSet(SL_IPV4_AP_P2P_GO_STATIC_ENABLE,IPCONFIG_MODE_ENABLE_IPV4,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4);
+ sl_Stop(0);
+ sl_Start(NULL,NULL,NULL);
+ \endcode
+
+
+*/
+#if _SL_INCLUDE_FUNC(sl_NetCfgSet)
+_i32 sl_NetCfgSet(_u8 ConfigId ,_u8 ConfigOpt, _u8 ConfigLen, _u8 *pValues);
+#endif
+
+
+/*!
+ \brief Internal function for getting network configurations
+
+ \return On success, zero is returned. On error, -1 is
+ returned
+
+ \param[in] ConfigId configuration id
+
+ \param[out] pConfigOpt Get configurations option
+
+ \param[out] pConfigLen The length of the allocated memory as input, when the
+ function complete, the value of this parameter would be
+ the len that actually read from the device.\n
+ If the device return length that is longer from the input
+ value, the function will cut the end of the returned structure
+ and will return ESMALLBUF
+
+ \param[out] pValues - get configurations values
+
+ \sa
+ \note
+ \warning
+ \par Examples:
+ \code
+ SL_MAC_ADDRESS_GET:
+
+ Get the device MAC address.
+ The returned MAC address is taken from FileSystem first. If the MAC address was not set by SL_MAC_ADDRESS_SET, the default MAC address
+ is retrieved from HW.
+
+ _u8 macAddressVal[SL_MAC_ADDR_LEN];
+ _u8 macAddressLen = SL_MAC_ADDR_LEN;
+ sl_NetCfgGet(SL_MAC_ADDRESS_GET,NULL,&macAddressLen,(_u8 *)macAddressVal);
+
+ \endcode
+
+ \code
+ SL_IPV4_STA_P2P_CL_GET_INFO:
+
+ Get IP address from WLAN station or P2P client. A DHCP flag is returned to indicate if the IP address is static or from DHCP.
+
+ _u8 len = sizeof(SlNetCfgIpV4Args_t);
+ _u8 dhcpIsOn = 0;
+ SlNetCfgIpV4Args_t ipV4 = {0};
+ sl_NetCfgGet(SL_IPV4_STA_P2P_CL_GET_INFO,&dhcpIsOn,&len,(_u8 *)&ipV4);
+
+ printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n",
+ (dhcpIsOn > 0) ? "ON" : "OFF",
+ SL_IPV4_BYTE(ipV4.ipV4,3),SL_IPV4_BYTE(ipV4.ipV4,2),SL_IPV4_BYTE(ipV4.ipV4,1),SL_IPV4_BYTE(ipV4.ipV4,0),
+ SL_IPV4_BYTE(ipV4.ipV4Mask,3),SL_IPV4_BYTE(ipV4.ipV4Mask,2),SL_IPV4_BYTE(ipV4.ipV4Mask,1),SL_IPV4_BYTE(ipV4.ipV4Mask,0),
+ SL_IPV4_BYTE(ipV4.ipV4Gateway,3),SL_IPV4_BYTE(ipV4.ipV4Gateway,2),SL_IPV4_BYTE(ipV4.ipV4Gateway,1),SL_IPV4_BYTE(ipV4.ipV4Gateway,0),
+ SL_IPV4_BYTE(ipV4.ipV4DnsServer,3),SL_IPV4_BYTE(ipV4.ipV4DnsServer,2),SL_IPV4_BYTE(ipV4.ipV4DnsServer,1),SL_IPV4_BYTE(ipV4.ipV4DnsServer,0));
+
+ \endcode
+
+ \code
+ SL_IPV4_AP_P2P_GO_GET_INFO:
+
+ Get static IP address for AP or P2P go.
+
+ _u8 len = sizeof(SlNetCfgIpV4Args_t);
+ _u8 dhcpIsOn = 0; // this flag is meaningless on AP/P2P go.
+ SlNetCfgIpV4Args_t ipV4 = {0};
+ sl_NetCfgGet(SL_IPV4_AP_P2P_GO_GET_INFO,&dhcpIsOn,&len,(_u8 *)&ipV4);
+
+ printf("IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n",
+ SL_IPV4_BYTE(ipV4.ipV4,3),SL_IPV4_BYTE(ipV4.ipV4,2),SL_IPV4_BYTE(ipV4.ipV4,1),SL_IPV4_BYTE(ipV4.ipV4,0),
+ SL_IPV4_BYTE(ipV4.ipV4Mask,3),SL_IPV4_BYTE(ipV4.ipV4Mask,2),SL_IPV4_BYTE(ipV4.ipV4Mask,1),SL_IPV4_BYTE(ipV4.ipV4Mask,0),
+ SL_IPV4_BYTE(ipV4.ipV4Gateway,3),SL_IPV4_BYTE(ipV4.ipV4Gateway,2),SL_IPV4_BYTE(ipV4.ipV4Gateway,1),SL_IPV4_BYTE(ipV4.ipV4Gateway,0),
+ SL_IPV4_BYTE(ipV4.ipV4DnsServer,3),SL_IPV4_BYTE(ipV4.ipV4DnsServer,2),SL_IPV4_BYTE(ipV4.ipV4DnsServer,1),SL_IPV4_BYTE(ipV4.ipV4DnsServer,0));
+
+ \endcode
+
+
+*/
+#if _SL_INCLUDE_FUNC(sl_NetCfgGet)
+_i32 sl_NetCfgGet(_u8 ConfigId ,_u8 *pConfigOpt, _u8 *pConfigLen, _u8 *pValues);
+#endif
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __NETCFG_H__ */
+
diff --git a/cc3200/simplelink/include/simplelink.h b/cc3200/simplelink/include/simplelink.h
new file mode 100644
index 0000000000..4467e3214c
--- /dev/null
+++ b/cc3200/simplelink/include/simplelink.h
@@ -0,0 +1,596 @@
+/*
+ * simplelink.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+/*!
+ \mainpage SimpleLink Driver
+
+ \section intro_sec Introduction
+
+ The SimpleLink CC31xx/CC2xx family allows to add Wi-Fi and networking capabilities
+ to low-cost embedded products without having prior Wi-Fi, RF or networking expertise.
+ The CC31xx/CC32xx is an ideal solution for microcontroller-based sensor and control
+ applications such as home appliances, home automation and smart metering.
+ The CC31xx/CC32xx has integrated a comprehensive TCP/IP network stack, Wi-Fi driver and
+ security supplicant leading to easier portability to microcontrollers, to an
+ ultra-low memory footprint, all without compromising the capabilities and robustness
+ of the final application.
+
+
+
+ \section modules_sec Module Names
+ To make it simple, TI's SimpleLink CC31xx/CC32xx platform capabilities were divided into modules by topic (Silo).
+ These capabilities range from basic device management through wireless
+ network configuration, standard BSD socket and much more.
+ Listed below are the various modules in the SimpleLink CC31xx/CC32xx driver:
+ -# \ref device - controls the behaviour of the CC31xx/CC32xx device (start/stop, events masking and obtaining specific device status)
+ -# \ref wlan - controls the use of the WiFi WLAN module including:
+ - Connection features, such as: profiles, policies, SmartConfig™
+ - Advanced WLAN features, such as: scans, rx filters and rx statistics collection
+ -# \ref socket - controls standard client/server sockets programming options and capabilities
+ -# \ref netapp - activates networking applications, such as: HTTP Server, DHCP Server, Ping, DNS and mDNS.
+ -# \ref netcfg - controls the configuration of the device addresses (i.e. IP and MAC addresses)
+ -# \ref FileSystem - provides file system capabilities to TI's CC31XX that can be used by both the CC31XX device and the user.
+
+
+ \section proting_sec Porting Guide
+
+ The porting of the SimpleLink driver to any new platform is based on few simple steps.
+ This guide takes you through this process step by step. Please follow the instructions
+ carefully to avoid any problems during this process and to enable efficient and proper
+ work with the device.
+ Please notice that all modifications and porting adjustments of the driver should be
+ made in the user.h header file only.
+ Keep making any of the changes only in this file will ensure smoothly transaction to
+ new versions of the driver at the future!
+
+
+ \subsection porting_step1 Step 1 - Create your own user.h file
+
+ The first step is to create a user.h file that will include your configurations and
+ adjustments. You can use the empty template provided as part of this driver or
+ you can choose to base your file on file from one of the wide range of examples
+ applications provided by Texas Instruments
+
+
+ \subsection porting_step2 Step 2 - Select the capabilities set required for your application
+
+ Texas Instruments made a lot of efforts to build set of predefined capability sets that would
+ fit most of the target application.
+ It is recommended to try and choose one of this predefined capabilities set before going to
+ build your own customized set. If you find compatible set you can skip the rest of this step.
+
+ The available sets are:
+ -# SL_TINY - Compatible to be used on platforms with very limited resources. Provides
+ the best in class foot print in terms of Code and Data consumption.
+ -# SL_SMALL - Compatible to most common networking applications. Provide the most
+ common APIs with decent balance between code size, data size, functionality
+ and performances
+ -# SL_FULL - Provide access to all SimpleLink functionalities
+
+
+ \subsection porting_step3 Step 3 - Bind the device enable/disable output line
+
+ The enable/disable line (nHib) provide mechanism to enter the device into the least current
+ consumption mode. This mode could be used when no traffic is required (tx/rx).
+ when this line is not connected to any IO of the host this define should be left empty.
+ Not connecting this line results in ability to start the driver only once.
+
+
+ \subsection porting_step4 Step 4 - Writing your interface communication driver
+
+ The SimpleLink device support several standard communication protocol among SPI and
+ UART. Depending on your needs and your hardware design, you should choose the
+ communication channel type.
+ The interface for this communication channel should include 4 simple access functions:
+ -# open
+ -# close
+ -# read
+ -# write
+
+ The way this driver would be implemented is directly effecting the efficiency and
+ the performances of the SimpleLink device on this platform.
+ If your system has DMA you should consider to use it in order to increase the utilization
+ of the communication channel
+ If you have enough memory resources you should consider using a buffer to increase the
+ efficiency of the write operations.
+
+
+ \subsection porting_step5 Step 5 - Choose your memory management model
+
+ The SimpleLink driver support two memory models:
+ -# Static (default)
+ -# Dynamic
+
+ If you choose to work in dynamic model you will have to provide alloc and free functions
+ to be used by the Simple Link driver otherwise nothing need to be done.
+
+
+ \subsection porting_step6 Step 6 - OS adaptation
+
+ The SimpleLink driver could run on two kind of platforms:
+ -# Non-Os / Single Threaded (default)
+ -# Multi-Threaded
+
+ If you choose to work in multi-threaded environment under operating system you will have to
+ provide some basic adaptation routines to allow the driver to protect access to resources
+ for different threads (locking object) and to allow synchronization between threads (sync objects).
+ In additional the driver support running without dedicated thread allocated solely to the simple
+ link driver. If you choose to work in this mode, you should also supply a spawn method that
+ will enable to run function on a temporary context.
+
+
+ \subsection porting_step7 Step 7 - Set your asynchronous event handlers routines
+
+ The SimpleLink device generate asynchronous events in several situations.
+ These asynchronous events could be masked.
+ In order to catch these events you have to provide handler routines.
+ Please notice that if you not provide a handler routine and the event is received,
+ the driver will drop this event without any indication of this drop.
+
+
+ \subsection porting_step8 Step 8 - Run diagnostic tools to validate the correctness of your porting
+
+ The driver is delivered with some porting diagnostic tools to simplify the porting validation process
+ and to reduce issues latter. It is very important to follow carefully this process.
+
+ The diagnostic process include:
+ -# Validating Interface Communication Driver
+ -# Validating OS adaptation layer
+ -# Validating HW integrity
+ -# Validating basic work with the device
+
+
+ \section sw_license License
+
+ *
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+#ifndef __SIMPLELINK_H__
+#define __SIMPLELINK_H__
+
+#include "user.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/*! \attention Async event activation notes
+ Function prototypes for event callback handlers
+ Event handler function names should be defined in the user.h file
+ e.g.
+ "#define sl_WlanEvtHdlr SLWlanEventHandler"
+ Indicates all WLAN events are handled by User func "SLWlanEventHandler"
+ Important notes:
+ 1. Event handlers cannot activate another SimpleLink API from the event's context
+ 2. Event's data is valid during event's context. Any application data
+ which is required for the user application should be copied or marked
+ into user's variables
+ 3. It is not recommended to delay the execution of the event callback handler
+
+*/
+
+/*!
+
+ \addtogroup UserEvents
+ @{
+
+*/
+
+
+/*****************************************************************************/
+/* Macro declarations for Host Driver version */
+/*****************************************************************************/
+#define SL_DRIVER_VERSION "1.0.0.1"
+#define SL_MAJOR_VERSION_NUM 1L
+#define SL_MINOR_VERSION_NUM 0L
+#define SL_VERSION_NUM 0L
+#define SL_SUB_VERSION_NUM 1L
+
+
+/*****************************************************************************/
+/* Macro declarations for predefined configurations */
+/*****************************************************************************/
+
+#ifdef SL_TINY
+#undef SL_INC_ARG_CHECK
+#undef SL_INC_EXT_API
+#undef SL_INC_SOCK_CLIENT_SIDE_API
+#undef SL_INC_SOCK_SEND_API
+#undef SL_INC_WLAN_PKG
+#undef SL_INC_NET_APP_PKG
+#undef SL_INC_NET_CFG_PKG
+#undef SL_INC_FS_PKG
+#define SL_INC_SOCK_SERVER_SIDE_API
+#define SL_INC_SOCK_RECV_API
+#define SL_INC_SOCKET_PKG
+#endif
+
+#ifdef SL_SMALL
+#undef SL_INC_EXT_API
+#undef SL_INC_NET_APP_PKG
+#undef SL_INC_NET_CFG_PKG
+#undef SL_INC_FS_PKG
+#define SL_INC_ARG_CHECK
+#define SL_INC_WLAN_PKG
+#define SL_INC_SOCKET_PKG
+#define SL_INC_SOCK_CLIENT_SIDE_API
+#define SL_INC_SOCK_SERVER_SIDE_API
+#define SL_INC_SOCK_RECV_API
+#define SL_INC_SOCK_SEND_API
+#endif
+
+#ifdef SL_FULL
+#define SL_INC_EXT_API
+#define SL_INC_NET_APP_PKG
+#define SL_INC_NET_CFG_PKG
+#define SL_INC_FS_PKG
+#if defined(DEBUG) && !defined(BOOTLOADER)
+#define SL_INC_ARG_CHECK
+#else
+#undef SL_INC_ARG_CHECK
+#endif
+#define SL_INC_WLAN_PKG
+#define SL_INC_SOCKET_PKG
+#define SL_INC_SOCK_CLIENT_SIDE_API
+#define SL_INC_SOCK_SERVER_SIDE_API
+#define SL_INC_SOCK_RECV_API
+#define SL_INC_SOCK_SEND_API
+#endif
+
+#define SL_RET_CODE_OK (0)
+#define SL_RET_CODE_INVALID_INPUT (-2)
+#define SL_RET_CODE_SELF_ERROR (-3)
+#define SL_RET_CODE_NWP_IF_ERROR (-4)
+#define SL_RET_CODE_MALLOC_ERROR (-5)
+
+#define sl_Memcpy memcpy
+#define sl_Memset memset
+
+#define sl_SyncObjClear(pObj) sl_SyncObjWait(pObj,SL_OS_NO_WAIT)
+
+#define SL_MAX_SOCKETS (8)
+
+
+/*****************************************************************************/
+/* Types definitions */
+/*****************************************************************************/
+typedef void (*_SlSpawnEntryFunc_t)(void* pValue);
+
+#ifndef NULL
+#define NULL (0)
+#endif
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+#ifndef TRUE
+#define TRUE (!FALSE)
+#endif
+
+#ifndef OK
+#define OK (0)
+#endif
+
+#ifndef _SL_USER_TYPES
+ #define _u8 unsigned char
+ #define _i8 signed char
+
+ #define _u16 unsigned short
+ #define _i16 signed short
+
+ #define _u32 unsigned long
+ #define _i32 signed long
+ #define _volatile volatile
+ #define _const const
+#endif
+
+typedef _u16 _SlOpcode_t;
+typedef _u8 _SlArgSize_t;
+typedef _i16 _SlDataSize_t;
+typedef _i16 _SlReturnVal_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+
+#ifdef SL_PLATFORM_MULTI_THREADED
+ #include "../source/spawn.h"
+#else
+ #include "../source/nonos.h"
+#endif
+
+
+/*
+ objInclusion.h and user.h must be included before all api header files
+ objInclusion.h must be the last arrangement just before including the API header files
+ since it based on the other configurations to decide which object should be included
+*/
+#include "../source/objInclusion.h"
+#include "trace.h"
+#include "fs.h"
+#include "socket.h"
+#include "netapp.h"
+#include "wlan.h"
+#include "device.h"
+#include "netcfg.h"
+#include "wlan_rx_filters.h"
+
+
+
+/* Async functions description*/
+
+/*!
+ \brief General async event for inspecting general events
+
+ \param[out] pSlDeviceEvent pointer to SlDeviceEvent_t
+
+ \par
+ Parameters: \n
+ pSlDeviceEvent->Event = SL_DEVICE_FATAL_ERROR_EVENT
+ - pSlDeviceEvent->EventData.deviceEvent fields:
+ - status: An error code indication from the device
+ - sender: The sender originator which is based on SlErrorSender_e enum
+
+ \par Example:
+ \code
+ printf(General Event Handler - ID=%d Sender=%d\n\n",
+ pSlDeviceEvent->EventData.deviceEvent.status, // status of the general event
+ pSlDeviceEvent->EventData.deviceEvent.sender); // sender type
+ \endcode
+*/
+#if (defined(sl_GeneralEvtHdlr))
+extern void sl_GeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent);
+#endif
+
+
+/*!
+ \brief WLAN Async event handler
+
+ \param[out] pSlWlanEvent pointer to SlWlanEvent_t data
+
+ \par
+ Parameters:
+
+ - pSlWlanEvent->Event = SL_WLAN_CONNECT_EVENT , STA or P2P client connection indication event
+ - pSlWlanEvent->EventData.STAandP2PModeWlanConnected main fields:
+ - ssid_name
+ - ssid_len
+ - bssid
+ - go_peer_device_name
+ - go_peer_device_name_len
+
+ - pSlWlanEvent->Event = SL_WLAN_DISCONNECT_EVENT , STA or P2P client disconnection event
+ - pSlWlanEvent->EventData.STAandP2PModeDisconnected main fields:
+ - ssid_name
+ - ssid_len
+ - reason_code
+
+ - pSlWlanEvent->Event = SL_WLAN_STA_CONNECTED_EVENT , AP/P2P(Go) connected STA/P2P(Client)
+ - pSlWlanEvent->EventData.APModeStaConnected fields:
+ - go_peer_device_name
+ - mac
+ - go_peer_device_name_len
+ - wps_dev_password_id
+ - own_ssid: relevant for event sta-connected only
+ - own_ssid_len: relevant for event sta-connected only
+
+ - pSlWlanEvent->Event = SL_WLAN_STA_DISCONNECTED_EVENT , AP/P2P(Go) disconnected STA/P2P(Client)
+ - pSlWlanEvent->EventData.APModestaDisconnected fields:
+ - go_peer_device_name
+ - mac
+ - go_peer_device_name_len
+ - wps_dev_password_id
+ - own_ssid: relevant for event sta-connected only
+ - own_ssid_len: relevant for event sta-connected only
+
+ - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_COMPLETE_EVENT
+ - pSlWlanEvent->EventData.smartConfigStartResponse fields:
+ - status
+ - ssid_len
+ - ssid
+ - private_token_len
+ - private_token
+
+ - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_STOP_EVENT
+ - pSlWlanEvent->EventData.smartConfigStopResponse fields:
+ - status
+
+ - pSlWlanEvent->Event = SL_WLAN_P2P_DEV_FOUND_EVENT
+ - pSlWlanEvent->EventData.P2PModeDevFound fields:
+ - go_peer_device_name
+ - mac
+ - go_peer_device_name_len
+ - wps_dev_password_id
+ - own_ssid: relevant for event sta-connected only
+ - own_ssid_len: relevant for event sta-connected only
+
+ - pSlWlanEvent->Event = SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT
+ - pSlWlanEvent->EventData.P2PModeNegReqReceived fields
+ - go_peer_device_name
+ - mac
+ - go_peer_device_name_len
+ - wps_dev_password_id
+ - own_ssid: relevant for event sta-connected only
+
+ - pSlWlanEvent->Event = SL_WLAN_CONNECTION_FAILED_EVENT , P2P only
+ - pSlWlanEvent->EventData.P2PModewlanConnectionFailure fields:
+ - status
+*/
+#if (defined(sl_WlanEvtHdlr))
+extern void sl_WlanEvtHdlr(SlWlanEvent_t *pSlWlanEvent);
+#endif
+
+
+/*!
+ \brief NETAPP Async event handler
+
+ \param[out] pSlNetApp pointer to SlNetAppEvent_t data
+
+ \par
+ Parameters:
+ - pSlWlanEvent->Event = SL_NETAPP_IPV4_IPACQUIRED_EVENT, IPV4 acquired event
+ - pSlWlanEvent->EventData.ipAcquiredV4 fields:
+ - ip
+ - gateway
+ - dns
+
+ - pSlWlanEvent->Event = SL_NETAPP_IP_LEASED_EVENT, AP or P2P go dhcp lease event
+ - pSlWlanEvent->EventData.ipLeased fields:
+ - ip_address
+ - lease_time
+ - mac
+
+ - pSlWlanEvent->Event = SL_NETAPP_IP_RELEASED_EVENT, AP or P2P go dhcp ip release event
+ - pSlWlanEvent->EventData.ipReleased fields
+ - ip_address
+ - mac
+ - reason
+
+*/
+#if (defined(sl_NetAppEvtHdlr))
+extern void sl_NetAppEvtHdlr(SlNetAppEvent_t *pSlNetApp);
+#endif
+
+/*!
+ \brief Socket Async event handler
+
+ \param[out] pSlSockEvent pointer to SlSockEvent_t data
+
+ \par
+ Parameters:\n
+ - pSlSockEvent->Event = SL_SOCKET_TX_FAILED_EVENT
+ - pSlSockEvent->EventData fields:
+ - sd
+ - status
+ - pSlSockEvent->Event = SL_SOCKET_ASYNC_EVENT
+ - pSlSockEvent->EventData fields:
+ - sd
+ - type: SSL_ACCEPT or RX_FRAGMENTATION_TOO_BIG or OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED
+ - val
+
+*/
+#if (defined(sl_SockEvtHdlr))
+extern void sl_SockEvtHdlr(SlSockEvent_t *pSlSockEvent);
+#endif
+
+/*!
+ \brief HTTP server async event
+
+ \param[out] pSlHttpServerEvent pointer to SlHttpServerEvent_t
+ \param[in] pSlHttpServerResponse pointer to SlHttpServerResponse_t
+
+ \par
+ Parameters: \n
+
+ - pSlHttpServerEvent->Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT
+ - pSlHttpServerEvent->EventData fields:
+ - httpTokenName
+ - data
+ - len
+ - pSlHttpServerResponse->ResponseData fields:
+ - data
+ - len
+
+ - pSlHttpServerEvent->Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT
+ - pSlHttpServerEvent->EventData.httpPostData fields:
+ - action
+ - token_name
+ - token_value
+ - pSlHttpServerResponse->ResponseData fields:
+ - data
+ - len
+
+*/
+#if (defined(sl_HttpServerCallback))
+extern void sl_HttpServerCallback(SlHttpServerEvent_t *pSlHttpServerEvent, SlHttpServerResponse_t *pSlHttpServerResponse);
+#endif
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __SIMPLELINK_H__ */
+
diff --git a/cc3200/simplelink/include/socket.h b/cc3200/simplelink/include/socket.h
new file mode 100644
index 0000000000..9293be4d4b
--- /dev/null
+++ b/cc3200/simplelink/include/socket.h
@@ -0,0 +1,1498 @@
+/*
+ * socket.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __SL_SOCKET_H__
+#define __SL_SOCKET_H__
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+
+ \addtogroup socket
+ @{
+
+*/
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+#define SL_FD_SETSIZE SL_MAX_SOCKETS /* Number of sockets to select on - same is max sockets! */
+#define BSD_SOCKET_ID_MASK (0x0F) /* Index using the LBS 4 bits for socket id 0-7 */
+/* Define some BSD protocol constants. */
+#define SL_SOCK_STREAM (1) /* TCP Socket */
+#define SL_SOCK_DGRAM (2) /* UDP Socket */
+#define SL_SOCK_RAW (3) /* Raw socket */
+#define SL_IPPROTO_TCP (6) /* TCP Raw Socket */
+#define SL_IPPROTO_UDP (17) /* UDP Raw Socket */
+#define SL_IPPROTO_RAW (255) /* Raw Socket */
+#define SL_SEC_SOCKET (100) /* Secured Socket Layer (SSL,TLS) */
+
+/* Address families. */
+#define SL_AF_INET (2) /* IPv4 socket (UDP, TCP, etc) */
+#define SL_AF_INET6 (3) /* IPv6 socket (UDP, TCP, etc) */
+#define SL_AF_INET6_EUI_48 (9)
+#define SL_AF_RF (6) /* data include RF parameter, All layer by user (Wifi could be disconnected) */
+#define SL_AF_PACKET (17)
+/* Protocol families, same as address families. */
+#define SL_PF_INET AF_INET
+#define SL_PF_INET6 AF_INET6
+#define SL_INADDR_ANY (0) /* bind any address */
+
+/* error codes */
+#define SL_SOC_ERROR (-1) /* Failure. */
+#define SL_SOC_OK ( 0) /* Success. */
+#define SL_INEXE (-8) /* socket command in execution */
+#define SL_EBADF (-9) /* Bad file number */
+#define SL_ENSOCK (-10) /* The system limit on the total number of open socket, has been reached */
+#define SL_EAGAIN (-11) /* Try again */
+#define SL_EWOULDBLOCK SL_EAGAIN
+#define SL_ENOMEM (-12) /* Out of memory */
+#define SL_EACCES (-13) /* Permission denied */
+#define SL_EFAULT (-14) /* Bad address */
+#define SL_ECLOSE (-15) /* close socket operation failed to transmit all queued packets */
+#define SL_EALREADY_ENABLED (-21) /* Transceiver - Transceiver already ON. there could be only one */
+#define SL_EINVAL (-22) /* Invalid argument */
+#define SL_EAUTO_CONNECT_OR_CONNECTING (-69) /* Transceiver - During connection, connected or auto mode started */
+#define SL_CONNECTION_PENDING (-72) /* Transceiver - Device is connected, disconnect first to open transceiver */
+#define SL_EUNSUPPORTED_ROLE (-86) /* Transceiver - Trying to start when WLAN role is AP or P2P GO */
+#define SL_EDESTADDRREQ (-89) /* Destination address required */
+#define SL_EPROTOTYPE (-91) /* Protocol wrong type for socket */
+#define SL_ENOPROTOOPT (-92) /* Protocol not available */
+#define SL_EPROTONOSUPPORT (-93) /* Protocol not supported */
+#define SL_ESOCKTNOSUPPORT (-94) /* Socket type not supported */
+#define SL_EOPNOTSUPP (-95) /* Operation not supported on transport endpoint */
+#define SL_EAFNOSUPPORT (-97) /* Address family not supported by protocol */
+#define SL_EADDRINUSE (-98) /* Address already in use */
+#define SL_EADDRNOTAVAIL (-99) /* Cannot assign requested address */
+#define SL_ENETUNREACH (-101) /* Network is unreachable */
+#define SL_ENOBUFS (-105) /* No buffer space available */
+#define SL_EOBUFF SL_ENOBUFS
+#define SL_EISCONN (-106) /* Transport endpoint is already connected */
+#define SL_ENOTCONN (-107) /* Transport endpoint is not connected */
+#define SL_ETIMEDOUT (-110) /* Connection timed out */
+#define SL_ECONNREFUSED (-111) /* Connection refused */
+#define SL_EALREADY (-114) /* Non blocking connect in progress, try again */
+
+#define SL_ESEC_RSA_WRONG_TYPE_E (-130) /* RSA wrong block type for RSA function */
+#define SL_ESEC_RSA_BUFFER_E (-131) /* RSA buffer error, output too small or */
+#define SL_ESEC_BUFFER_E (-132) /* output buffer too small or input too large */
+#define SL_ESEC_ALGO_ID_E (-133) /* setting algo id error */
+#define SL_ESEC_PUBLIC_KEY_E (-134) /* setting public key error */
+#define SL_ESEC_DATE_E (-135) /* setting date validity error */
+#define SL_ESEC_SUBJECT_E (-136) /* setting subject name error */
+#define SL_ESEC_ISSUER_E (-137) /* setting issuer name error */
+#define SL_ESEC_CA_TRUE_E (-138) /* setting CA basic constraint true error */
+#define SL_ESEC_EXTENSIONS_E (-139) /* setting extensions error */
+#define SL_ESEC_ASN_PARSE_E (-140) /* ASN parsing error, invalid input */
+#define SL_ESEC_ASN_VERSION_E (-141) /* ASN version error, invalid number */
+#define SL_ESEC_ASN_GETINT_E (-142) /* ASN get big _i16 error, invalid data */
+#define SL_ESEC_ASN_RSA_KEY_E (-143) /* ASN key init error, invalid input */
+#define SL_ESEC_ASN_OBJECT_ID_E (-144) /* ASN object id error, invalid id */
+#define SL_ESEC_ASN_TAG_NULL_E (-145) /* ASN tag error, not null */
+#define SL_ESEC_ASN_EXPECT_0_E (-146) /* ASN expect error, not zero */
+#define SL_ESEC_ASN_BITSTR_E (-147) /* ASN bit string error, wrong id */
+#define SL_ESEC_ASN_UNKNOWN_OID_E (-148) /* ASN oid error, unknown sum id */
+#define SL_ESEC_ASN_DATE_SZ_E (-149) /* ASN date error, bad size */
+#define SL_ESEC_ASN_BEFORE_DATE_E (-150) /* ASN date error, current date before */
+#define SL_ESEC_ASN_AFTER_DATE_E (-151) /* ASN date error, current date after */
+#define SL_ESEC_ASN_SIG_OID_E (-152) /* ASN signature error, mismatched oid */
+#define SL_ESEC_ASN_TIME_E (-153) /* ASN time error, unknown time type */
+#define SL_ESEC_ASN_INPUT_E (-154) /* ASN input error, not enough data */
+#define SL_ESEC_ASN_SIG_CONFIRM_E (-155) /* ASN sig error, confirm failure */
+#define SL_ESEC_ASN_SIG_HASH_E (-156) /* ASN sig error, unsupported hash type */
+#define SL_ESEC_ASN_SIG_KEY_E (-157) /* ASN sig error, unsupported key type */
+#define SL_ESEC_ASN_DH_KEY_E (-158) /* ASN key init error, invalid input */
+#define SL_ESEC_ASN_NTRU_KEY_E (-159) /* ASN ntru key decode error, invalid input */
+#define SL_ESEC_ECC_BAD_ARG_E (-170) /* ECC input argument of wrong type */
+#define SL_ESEC_ASN_ECC_KEY_E (-171) /* ASN ECC bad input */
+#define SL_ESEC_ECC_CURVE_OID_E (-172) /* Unsupported ECC OID curve type */
+#define SL_ESEC_BAD_FUNC_ARG (-173) /* Bad function argument provided */
+#define SL_ESEC_NOT_COMPILED_IN (-174) /* Feature not compiled in */
+#define SL_ESEC_UNICODE_SIZE_E (-175) /* Unicode password too big */
+#define SL_ESEC_NO_PASSWORD (-176) /* no password provided by user */
+#define SL_ESEC_ALT_NAME_E (-177) /* alt name size problem, too big */
+#define SL_ESEC_AES_GCM_AUTH_E (-180) /* AES-GCM Authentication check failure */
+#define SL_ESEC_AES_CCM_AUTH_E (-181) /* AES-CCM Authentication check failure */
+/* ssl tls security start with -300 offset */
+#define SL_ESEC_CLOSE_NOTIFY (-300) /* ssl/tls alerts */
+#define SL_ESEC_UNEXPECTED_MESSAGE (-310) /* ssl/tls alerts */
+#define SL_ESEC_BAD_RECORD_MAC (-320) /* ssl/tls alerts */
+#define SL_ESEC_DECRYPTION_FAILED (-321) /* ssl/tls alerts */
+#define SL_ESEC_RECORD_OVERFLOW (-322) /* ssl/tls alerts */
+#define SL_ESEC_DECOMPRESSION_FAILURE (-330) /* ssl/tls alerts */
+#define SL_ESEC_HANDSHAKE_FAILURE (-340) /* ssl/tls alerts */
+#define SL_ESEC_NO_CERTIFICATE (-341) /* ssl/tls alerts */
+#define SL_ESEC_BAD_CERTIFICATE (-342) /* ssl/tls alerts */
+#define SL_ESEC_UNSUPPORTED_CERTIFICATE (-343) /* ssl/tls alerts */
+#define SL_ESEC_CERTIFICATE_REVOKED (-344) /* ssl/tls alerts */
+#define SL_ESEC_CERTIFICATE_EXPIRED (-345) /* ssl/tls alerts */
+#define SL_ESEC_CERTIFICATE_UNKNOWN (-346) /* ssl/tls alerts */
+#define SL_ESEC_ILLEGAL_PARAMETER (-347) /* ssl/tls alerts */
+#define SL_ESEC_UNKNOWN_CA (-348) /* ssl/tls alerts */
+#define SL_ESEC_ACCESS_DENIED (-349) /* ssl/tls alerts */
+#define SL_ESEC_DECODE_ERROR (-350) /* ssl/tls alerts */
+#define SL_ESEC_DECRYPT_ERROR (-351) /* ssl/tls alerts */
+#define SL_ESEC_EXPORT_RESTRICTION (-360) /* ssl/tls alerts */
+#define SL_ESEC_PROTOCOL_VERSION (-370) /* ssl/tls alerts */
+#define SL_ESEC_INSUFFICIENT_SECURITY (-371) /* ssl/tls alerts */
+#define SL_ESEC_INTERNAL_ERROR (-380) /* ssl/tls alerts */
+#define SL_ESEC_USER_CANCELLED (-390) /* ssl/tls alerts */
+#define SL_ESEC_NO_RENEGOTIATION (-400) /* ssl/tls alerts */
+#define SL_ESEC_UNSUPPORTED_EXTENSION (-410) /* ssl/tls alerts */
+#define SL_ESEC_CERTIFICATE_UNOBTAINABLE (-411) /* ssl/tls alerts */
+#define SL_ESEC_UNRECOGNIZED_NAME (-412) /* ssl/tls alerts */
+#define SL_ESEC_BAD_CERTIFICATE_STATUS_RESPONSE (-413) /* ssl/tls alerts */
+#define SL_ESEC_BAD_CERTIFICATE_HASH_VALUE (-414) /* ssl/tls alerts */
+/* propierty secure */
+#define SL_ESECGENERAL (-450) /* error secure level general error */
+#define SL_ESECDECRYPT (-451) /* error secure level, decrypt recv packet fail */
+#define SL_ESECCLOSED (-452) /* secure layrer is closed by other size , tcp is still connected */
+#define SL_ESECSNOVERIFY (-453) /* Connected without server verification */
+#define SL_ESECNOCAFILE (-454) /* error secure level CA file not found*/
+#define SL_ESECMEMORY (-455) /* error secure level No memory space available */
+#define SL_ESECBADCAFILE (-456) /* error secure level bad CA file */
+#define SL_ESECBADCERTFILE (-457) /* error secure level bad Certificate file */
+#define SL_ESECBADPRIVATEFILE (-458) /* error secure level bad private file */
+#define SL_ESECBADDHFILE (-459) /* error secure level bad DH file */
+#define SL_ESECT00MANYSSLOPENED (-460) /* MAX SSL Sockets are opened */
+#define SL_ESECDATEERROR (-461) /* connected with certificate date verification error */
+#define SL_ESECHANDSHAKETIMEDOUT (-462) /* connection timed out due to handshake time */
+
+/* end error codes */
+
+/* Max payload size by protocol */
+#define SL_SOCKET_PAYLOAD_TYPE_MASK (0xF0) /*4 bits type, 4 bits sockets id */
+#define SL_SOCKET_PAYLOAD_TYPE_UDP_IPV4 (0x00) /* 1472 bytes */
+#define SL_SOCKET_PAYLOAD_TYPE_TCP_IPV4 (0x10) /* 1460 bytes */
+#define SL_SOCKET_PAYLOAD_TYPE_UDP_IPV6 (0x20) /* 1452 bytes */
+#define SL_SOCKET_PAYLOAD_TYPE_TCP_IPV6 (0x30) /* 1440 bytes */
+#define SL_SOCKET_PAYLOAD_TYPE_UDP_IPV4_SECURE (0x40) /* */
+#define SL_SOCKET_PAYLOAD_TYPE_TCP_IPV4_SECURE (0x50) /* */
+#define SL_SOCKET_PAYLOAD_TYPE_UDP_IPV6_SECURE (0x60) /* */
+#define SL_SOCKET_PAYLOAD_TYPE_TCP_IPV6_SECURE (0x70) /* */
+#define SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER (0x80) /* 1536 bytes */
+#define SL_SOCKET_PAYLOAD_TYPE_RAW_PACKET (0x90) /* 1536 bytes */
+#define SL_SOCKET_PAYLOAD_TYPE_RAW_IP4 (0xa0)
+#define SL_SOCKET_PAYLOAD_TYPE_RAW_IP6 (SL_SOCKET_PAYLOAD_TYPE_RAW_IP4 )
+
+
+
+#define SL_SOL_SOCKET (1) /* Define the socket option category. */
+#define SL_IPPROTO_IP (2) /* Define the IP option category. */
+#define SL_SOL_PHY_OPT (3) /* Define the PHY option category. */
+
+#define SL_SO_RCVBUF (8) /* Setting TCP receive buffer size */
+#define SL_SO_KEEPALIVE (9) /* Connections are kept alive with periodic messages */
+#define SL_SO_RCVTIMEO (20) /* Enable receive timeout */
+#define SL_SO_NONBLOCKING (24) /* Enable . disable nonblocking mode */
+#define SL_SO_SECMETHOD (25) /* security metohd */
+#define SL_SO_SECURE_MASK (26) /* security mask */
+#define SL_SO_SECURE_FILES (27) /* security files */
+#define SL_SO_CHANGE_CHANNEL (28) /* This option is available only when transceiver started */
+#define SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME (30) /* This option used to configue secure file */
+#define SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME (31) /* This option used to configue secure file */
+#define SL_SO_SECURE_FILES_CA_FILE_NAME (32) /* This option used to configue secure file */
+#define SL_SO_SECURE_FILES_DH_KEY_FILE_NAME (33) /* This option used to configue secure file */
+
+#define SL_IP_MULTICAST_IF (60) /* Specify outgoing multicast interface */
+#define SL_IP_MULTICAST_TTL (61) /* Specify the TTL value to use for outgoing multicast packet. */
+#define SL_IP_ADD_MEMBERSHIP (65) /* Join IPv4 multicast membership */
+#define SL_IP_DROP_MEMBERSHIP (66) /* Leave IPv4 multicast membership */
+#define SL_IP_HDRINCL (67) /* Raw socket IPv4 header included. */
+#define SL_IP_RAW_RX_NO_HEADER (68) /* Proprietary socket option that does not includeIPv4/IPv6 header (and extension headers) on received raw sockets*/
+#define SL_IP_RAW_IPV6_HDRINCL (69) /* Transmitted buffer over IPv6 socket contains IPv6 header. */
+
+#define SL_SO_PHY_RATE (100) /* WLAN Transmit rate */
+#define SL_SO_PHY_TX_POWER (101) /* TX Power level */
+#define SL_SO_PHY_NUM_FRAMES_TO_TX (102) /* Number of frames to transmit */
+#define SL_SO_PHY_PREAMBLE (103) /* Preamble for transmission */
+
+#define SL_SO_SEC_METHOD_SSLV3 (0) /* security metohd SSL v3*/
+#define SL_SO_SEC_METHOD_TLSV1 (1) /* security metohd TLS v1*/
+#define SL_SO_SEC_METHOD_TLSV1_1 (2) /* security metohd TLS v1_1*/
+#define SL_SO_SEC_METHOD_TLSV1_2 (3) /* security metohd TLS v1_2*/
+#define SL_SO_SEC_METHOD_SSLv3_TLSV1_2 (4) /* use highest possible version from SSLv3 - TLS 1.2*/
+#define SL_SO_SEC_METHOD_DLSV1 (5) /* security metohd DTL v1 */
+
+#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA (1 << 0)
+#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5 (1 << 1)
+#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA (1 << 2)
+#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA (1 << 3)
+#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA (1 << 4)
+#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA (1 << 5)
+#define SL_SEC_MASK_SECURE_DEFAULT ((SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA << 1) - 1)
+
+#define SL_MSG_DONTWAIT (0x00000008) /* Nonblocking IO */
+
+/* AP DHCP Server - IP Release reason code */
+#define SL_IP_LEASE_PEER_RELEASE (0)
+#define SL_IP_LEASE_PEER_DECLINE (1)
+#define SL_IP_LEASE_EXPIRED (2)
+
+/* possible types when receiving SL_SOCKET_ASYNC_EVENT*/
+#define SSL_ACCEPT (1) /* accept failed due to ssl issue ( tcp pass) */
+#define RX_FRAGMENTATION_TOO_BIG (2) /* connection less mode, rx packet fragmentation > 16K, packet is being released */
+#define OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED (3) /* remote side down from secure to unsecure */
+
+
+
+#ifdef SL_INC_STD_BSD_API_NAMING
+
+#define FD_SETSIZE SL_FD_SETSIZE
+
+#define SOCK_STREAM SL_SOCK_STREAM
+#define SOCK_DGRAM SL_SOCK_DGRAM
+#define SOCK_RAW SL_SOCK_RAW
+#define IPPROTO_TCP SL_IPPROTO_TCP
+#define IPPROTO_UDP SL_IPPROTO_UDP
+#define IPPROTO_RAW SL_IPPROTO_RAW
+
+#define AF_INET SL_AF_INET
+#define AF_INET6 SL_AF_INET6
+#define AF_INET6_EUI_48 SL_AF_INET6_EUI_48
+#define AF_RF SL_AF_RF
+#define AF_PACKET SL_AF_PACKET
+
+#define PF_INET SL_PF_INET
+#define PF_INET6 SL_PF_INET6
+
+#define INADDR_ANY SL_INADDR_ANY
+#define ERROR SL_SOC_ERROR
+#define INEXE SL_INEXE
+#define EBADF SL_EBADF
+#define ENSOCK SL_ENSOCK
+#define EAGAIN SL_EAGAIN
+#define EWOULDBLOCK SL_EWOULDBLOCK
+#define ENOMEM SL_ENOMEM
+#define EACCES SL_EACCES
+#define EFAULT SL_EFAULT
+#define EINVAL SL_EINVAL
+#define EDESTADDRREQ SL_EDESTADDRREQ
+#define EPROTOTYPE SL_EPROTOTYPE
+#define ENOPROTOOPT SL_ENOPROTOOPT
+#define EPROTONOSUPPORT SL_EPROTONOSUPPORT
+#define ESOCKTNOSUPPORT SL_ESOCKTNOSUPPORT
+#define EOPNOTSUPP SL_EOPNOTSUPP
+#define EAFNOSUPPORT SL_EAFNOSUPPORT
+#define EADDRINUSE SL_EADDRINUSE
+#define EADDRNOTAVAIL SL_EADDRNOTAVAIL
+#define ENETUNREACH SL_ENETUNREACH
+#define ENOBUFS SL_ENOBUFS
+#define EOBUFF SL_EOBUFF
+#define EISCONN SL_EISCONN
+#define ENOTCONN SL_ENOTCONN
+#define ETIMEDOUT SL_ETIMEDOUT
+#define ECONNREFUSED SL_ECONNREFUSED
+
+#define SOL_SOCKET SL_SOL_SOCKET
+#define IPPROTO_IP SL_IPPROTO_IP
+#define SO_KEEPALIVE SL_SO_KEEPALIVE
+
+#define SO_RCVTIMEO SL_SO_RCVTIMEO
+#define SO_NONBLOCKING SL_SO_NONBLOCKING
+
+#define IP_MULTICAST_IF SL_IP_MULTICAST_IF
+#define IP_MULTICAST_TTL SL_IP_MULTICAST_TTL
+#define IP_ADD_MEMBERSHIP SL_IP_ADD_MEMBERSHIP
+#define IP_DROP_MEMBERSHIP SL_IP_DROP_MEMBERSHIP
+
+#define socklen_t SlSocklen_t
+#define timeval SlTimeval_t
+#define sockaddr SlSockAddr_t
+#define in6_addr SlIn6Addr_t
+#define sockaddr_in6 SlSockAddrIn6_t
+#define in_addr SlInAddr_t
+#define sockaddr_in SlSockAddrIn_t
+
+#define MSG_DONTWAIT SL_MSG_DONTWAIT
+
+#define FD_SET SL_FD_SET
+#define FD_CLR SL_FD_CLR
+#define FD_ISSET SL_FD_ISSET
+#define FD_ZERO SL_FD_ZERO
+#define fd_set SlFdSet_t
+
+#define socket sl_Socket
+#define close sl_Close
+#define accept sl_Accept
+#define bind sl_Bind
+#define listen sl_Listen
+#define connect sl_Connect
+#define select sl_Select
+#define setsockopt sl_SetSockOpt
+#define getsockopt sl_GetSockOpt
+#define recv sl_Recv
+#define recvfrom sl_RecvFrom
+#define write sl_Write
+#define send sl_Send
+#define sendto sl_SendTo
+#define gethostbyname sl_NetAppDnsGetHostByName
+#define htonl sl_Htonl
+#define ntohl sl_Ntohl
+#define htons sl_Htons
+#define ntohs sl_Ntohs
+#endif
+
+/*****************************************************************************/
+/* Structure/Enum declarations */
+/*****************************************************************************/
+
+/* Internet address */
+typedef struct SlInAddr_t
+{
+#ifndef s_addr
+ _u32 s_addr; /* Internet address 32 bits */
+#else
+ union S_un {
+ struct { _u8 s_b1,s_b2,s_b3,s_b4; } S_un_b;
+ struct { _u8 s_w1,s_w2; } S_un_w;
+ _u32 S_addr;
+ } S_un;
+#endif
+}SlInAddr_t;
+
+
+/* sockopt */
+typedef struct
+{
+ _u32 KeepaliveEnabled; /* 0 = disabled;1 = enabled; default = 1*/
+}SlSockKeepalive_t;
+
+typedef struct
+{
+ _u32 ReuseaddrEnabled; /* 0 = disabled; 1 = enabled; default = 1*/
+}SlSockReuseaddr_t;
+
+typedef struct
+{
+ _u32 Winsize; /* receive window size for tcp sockets */
+}SlSockWinsize_t;
+
+typedef struct
+{
+ _u32 NonblockingEnabled;/* 0 = disabled;1 = enabled;default = 1*/
+}SlSockNonblocking_t;
+
+typedef struct
+{
+ _u8 sd;
+ _u8 type;
+ _u16 val;
+} SlSocketAsyncEvent_t;
+
+typedef struct
+{
+ _i16 status;
+ _u16 sd;
+ SlSocketAsyncEvent_t socketAsyncEvent;
+} SlSockEventData_t;
+
+
+typedef struct
+{
+ _u32 Event;
+ SlSockEventData_t EventData;
+} SlSockEvent_t;
+
+
+typedef struct
+{
+ _u32 secureMask;
+} SlSockSecureMask;
+
+typedef struct
+{
+ _u8 secureMethod;
+} SlSockSecureMethod;
+
+typedef enum
+{
+ SL_BSD_SECURED_PRIVATE_KEY_IDX = 0,
+ SL_BSD_SECURED_CERTIFICATE_IDX,
+ SL_BSD_SECURED_CA_IDX,
+ SL_BSD_SECURED_DH_IDX
+}slBsd_secureSocketFilesIndex_e;
+
+typedef struct
+{
+ SlInAddr_t imr_multiaddr; /* The IPv4 multicast address to join */
+ SlInAddr_t imr_interface; /* The interface to use for this group */
+} SlSockIpMreq;
+
+
+/* sockopt */
+typedef _u32 SlTime_t;
+typedef _u32 SlSuseconds_t;
+
+typedef struct SlTimeval_t
+{
+ SlTime_t tv_sec; /* Seconds */
+ SlSuseconds_t tv_usec; /* Microseconds */
+}SlTimeval_t;
+
+typedef _u16 SlSocklen_t;
+
+/* IpV4 socket address */
+typedef struct SlSockAddr_t
+{
+ _u16 sa_family; /* Address family (e.g. , AF_INET) */
+ _u8 sa_data[14]; /* Protocol- specific address information*/
+}SlSockAddr_t;
+
+
+/* IpV6 or Ipv6 EUI64 */
+typedef struct SlIn6Addr_t
+{
+ union
+ {
+ _u8 _S6_u8[16];
+ _u32 _S6_u32[4];
+ } _S6_un;
+}SlIn6Addr_t;
+
+typedef struct SlSockAddrIn6_t
+{
+ _u16 sin6_family; /* AF_INET6 || AF_INET6_EUI_48*/
+ _u16 sin6_port; /* Transport layer port. */
+ _u32 sin6_flowinfo; /* IPv6 flow information. */
+ SlIn6Addr_t sin6_addr; /* IPv6 address. */
+ _u32 sin6_scope_id; /* set of interfaces for a scope. */
+}SlSockAddrIn6_t;
+
+/* Socket address, Internet style. */
+
+typedef struct SlSockAddrIn_t
+{
+ _u16 sin_family; /* Internet Protocol (AF_INET). */
+ _u16 sin_port; /* Address port (16 bits). */
+ SlInAddr_t sin_addr; /* Internet address (32 bits). */
+ _i8 sin_zero[8]; /* Not used. */
+}SlSockAddrIn_t;
+
+typedef struct
+{
+ _u32 ip;
+ _u32 gateway;
+ _u32 dns;
+}SlIpV4AcquiredAsync_t;
+
+typedef struct
+{
+ _u32 type;
+ _u32 ip[4];
+ _u32 gateway[4];
+ _u32 dns[4];
+}SlIpV6AcquiredAsync_t;
+
+typedef struct
+{
+ _u32 ip_address;
+ _u32 lease_time;
+ _u8 mac[6];
+ _u16 padding;
+}SlIpLeasedAsync_t;
+
+typedef struct
+{
+ _u32 ip_address;
+ _u8 mac[6];
+ _u16 reason;
+}SlIpReleasedAsync_t;
+
+
+typedef union
+{
+ SlIpV4AcquiredAsync_t ipAcquiredV4; /*SL_NETAPP_IPV4_IPACQUIRED_EVENT*/
+ SlIpV6AcquiredAsync_t ipAcquiredV6; /*SL_NETAPP_IPV6_IPACQUIRED_EVENT*/
+ _u32 sd; /*SL_SOCKET_TX_FAILED_EVENT*/
+ SlIpLeasedAsync_t ipLeased; /* SL_NETAPP_IP_LEASED_EVENT */
+ SlIpReleasedAsync_t ipReleased; /* SL_NETAPP_IP_RELEASED_EVENT */
+} SlNetAppEventData_u;
+
+typedef struct
+{
+ _u32 Event;
+ SlNetAppEventData_u EventData;
+}SlNetAppEvent_t;
+
+
+typedef struct sock_secureFiles
+{
+ _u8 secureFiles[4];
+}SlSockSecureFiles_t;
+
+
+typedef struct SlFdSet_t /* The select socket array manager */
+{
+ _u32 fd_array[(SL_FD_SETSIZE + 31)/32]; /* Bit map of SOCKET Descriptors */
+} SlFdSet_t;
+
+typedef struct
+{
+ _u8 rate; /* Recevied Rate */
+ _u8 channel; /* The received channel*/
+ _i8 rssi; /* The computed RSSI value in db of current frame */
+ _u8 padding; /* pad to align to 32 bits */
+ _u32 timestamp; /* Timestamp in microseconds, */
+}SlTransceiverRxOverHead_t;
+
+
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+
+/*!
+
+ \brief create an endpoint for communication
+
+ The socket function creates a new socket of a certain socket type, identified
+ by an integer number, and allocates system resources to it.
+ This function is called by the application layer to obtain a socket handle.
+
+ \param[in] domain specifies the protocol family of the created socket.
+ For example:
+ AF_INET for network protocol IPv4
+ AF_RF for starting transceiver mode. Notes:
+ - sending and receiving any packet overriding 802.11 header
+ - for optimized power consumption the socket will be started in TX
+ only mode until receive command is activated
+ AF_INET6 for IPv6
+
+
+ \param[in] type specifies the communication semantic, one of:
+ SOCK_STREAM (reliable stream-oriented service or Stream Sockets)
+ SOCK_DGRAM (datagram service or Datagram Sockets)
+ SOCK_RAW (raw protocols atop the network layer)
+ when used with AF_RF:
+ SOCK_DGRAM - L2 socket
+ SOCK_RAW - L1 socket - bypass WLAN CCA (Clear Channel Assessment)
+
+ \param[in] protocol specifies a particular transport to be used with
+ the socket.
+ The most common are IPPROTO_TCP, IPPROTO_SCTP, IPPROTO_UDP,
+ IPPROTO_DCCP.
+ The value 0 may be used to select a default
+ protocol from the selected domain and type
+
+
+ \return On success, socket handle that is used for consequent socket operations.
+ A successful return code should be a positive number (int16)
+ On error, a negative (int16) value will be returned specifying the error code.
+ SL_EAFNOSUPPORT - illegal domain parameter
+ SL_EPROTOTYPE - illegal type parameter
+ SL_EACCES - permission denied
+ SL_ENSOCK - exceeded maximal number of socket
+ SL_ENOMEM - memory allocation error
+ SL_EINVAL - error in socket configuration
+ SL_EPROTONOSUPPORT - illegal protocol parameter
+ SL_EOPNOTSUPP - illegal combination of protocol and type parameters
+
+
+ \sa sl_Close
+ \note belongs to \ref basic_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Socket)
+_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol);
+#endif
+
+/*!
+ \brief gracefully close socket
+
+ This function causes the system to release resources allocated to a socket. \n
+ In case of TCP, the connection is terminated.
+
+ \param[in] sd socket handle (received in sl_Socket)
+
+ \return On success, zero is returned.
+ On error, a negative number is returned.
+
+ \sa sl_Socket
+ \note belongs to \ref ext_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Close)
+_i16 sl_Close(_i16 sd);
+#endif
+
+/*!
+ \brief Accept a connection on a socket
+
+ This function is used with connection-based socket types (SOCK_STREAM).
+ It extracts the first connection request on the queue of pending
+ connections, creates a new connected socket, and returns a new file
+ descriptor referring to that socket.
+ The newly created socket is not in the listening state. The
+ original socket sd is unaffected by this call.
+ The argument sd is a socket that has been created with
+ sl_Socket(), bound to a local address with sl_Bind(), and is
+ listening for connections after a sl_Listen(). The argument \b
+ \e addr is a pointer to a sockaddr structure. This structure
+ is filled in with the address of the peer socket, as known to
+ the communications layer. The exact format of the address
+ returned addr is determined by the socket's address family.
+ The \b \e addrlen argument is a value-result argument: it
+ should initially contain the size of the structure pointed to
+ by addr, on return it will contain the actual length (in
+ bytes) of the address returned.
+
+ \param[in] sd socket descriptor (handle)
+ \param[out] addr the argument addr is a pointer
+ to a sockaddr structure. This
+ structure is filled in with the
+ address of the peer socket, as
+ known to the communications
+ layer. The exact format of the
+ address returned addr is
+ determined by the socket's
+ address\n
+ sockaddr:\n - code for the
+ address format. On this version
+ only AF_INET is supported.\n -
+ socket address, the length
+ depends on the code format
+ \param[out] addrlen the addrlen argument is a value-result
+ argument: it should initially contain the
+ size of the structure pointed to by addr
+
+ \return On success, a socket handle.
+ On a non-blocking accept a possible negative value is SL_EAGAIN.
+ On failure, negative value.
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+
+ \sa sl_Socket sl_Bind sl_Listen
+ \note belongs to \ref server_side
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Accept)
+_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen);
+#endif
+
+/*!
+ \brief assign a name to a socket
+
+ This function gives the socket the local address addr.
+ addr is addrlen bytes long. Traditionally, this is called
+ When a socket is created with socket, it exists in a name
+ space (address family) but has no name assigned.
+ It is necessary to assign a local address before a SOCK_STREAM
+ socket may receive connections.
+
+ \param[in] sd socket descriptor (handle)
+ \param[in] addr specifies the destination
+ addrs\n sockaddr:\n - code for
+ the address format. On this
+ version only AF_INET is
+ supported.\n - socket address,
+ the length depends on the code
+ format
+ \param[in] addrlen contains the size of the structure pointed to by addr
+
+ \return On success, zero is returned. On error, a negative error code is returned.
+
+ \sa sl_Socket sl_Accept sl_Listen
+ \note belongs to \ref basic_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Bind)
+_i16 sl_Bind(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen);
+#endif
+
+/*!
+ \brief listen for connections on a socket
+
+ The willingness to accept incoming connections and a queue
+ limit for incoming connections are specified with listen(),
+ and then the connections are accepted with accept.
+ The listen() call applies only to sockets of type SOCK_STREAM
+ The backlog parameter defines the maximum length the queue of
+ pending connections may grow to.
+
+ \param[in] sd socket descriptor (handle)
+ \param[in] backlog specifies the listen queue depth.
+
+
+ \return On success, zero is returned. On error, a negative error code is returned.
+
+ \sa sl_Socket sl_Accept sl_Bind
+ \note belongs to \ref server_side
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Listen)
+_i16 sl_Listen(_i16 sd, _i16 backlog);
+#endif
+
+/*!
+ \brief Initiate a connection on a socket
+
+ Function connects the socket referred to by the socket
+ descriptor sd, to the address specified by addr. The addrlen
+ argument specifies the size of addr. The format of the
+ address in addr is determined by the address space of the
+ socket. If it is of type SOCK_DGRAM, this call specifies the
+ peer with which the socket is to be associated; this address
+ is that to which datagrams are to be sent, and the only
+ address from which datagrams are to be received. If the
+ socket is of type SOCK_STREAM, this call attempts to make a
+ connection to another socket. The other socket is specified
+ by address, which is an address in the communications space
+ of the socket.
+
+
+ \param[in] sd socket descriptor (handle)
+ \param[in] addr specifies the destination addr\n
+ sockaddr:\n - code for the
+ address format. On this version
+ only AF_INET is supported.\n -
+ socket address, the length
+ depends on the code format
+
+ \param[in] addrlen contains the size of the structure pointed
+ to by addr
+
+ \return On success, a socket handle.
+ On a non-blocking connect a possible negative value is SL_EALREADY.
+ On failure, negative value.
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+
+ \sa sl_Socket
+ \note belongs to \ref client_side
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Connect)
+_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen);
+#endif
+
+/*!
+ \brief Monitor socket activity
+
+ Select allow a program to monitor multiple file descriptors,
+ waiting until one or more of the file descriptors become
+ "ready" for some class of I/O operation
+
+
+ \param[in] nfds the highest-numbered file descriptor in any of the
+ three sets, plus 1.
+ \param[out] readsds socket descriptors list for read monitoring and accept monitoring
+ \param[out] writesds socket descriptors list for connect monitoring only, write monitoring is not supported
+ \param[out] exceptsds socket descriptors list for exception monitoring, not supported.
+ \param[in] timeout is an upper bound on the amount of time elapsed
+ before select() returns. Null or above 0xffff seconds means
+ infinity timeout. The minimum timeout is 10 milliseconds,
+ less than 10 milliseconds will be set automatically to 10 milliseconds.
+ Max microseconds supported is 0xfffc00.
+
+ \return On success, select() returns the number of
+ file descriptors contained in the three returned
+ descriptor sets (that is, the total number of bits that
+ are set in readfds, writefds, exceptfds) which may be
+ zero if the timeout expires before anything interesting
+ happens. On error, a negative value is returned.
+ readsds - return the sockets on which Read request will
+ return without delay with valid data.
+ writesds - return the sockets on which Write request
+ will return without delay.
+ exceptsds - return the sockets closed recently.
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+
+ \sa sl_Socket
+ \note If the timeout value set to less than 5ms it will automatically set
+ to 5ms to prevent overload of the system
+ belongs to \ref basic_api
+
+ Only one sl_Select can be handled at a time.
+ Calling this API while the same command is called from another thread, may result
+ in one of the two scenarios:
+ 1. The command will wait (internal) until the previous command finish, and then be executed.
+ 2. There are not enough resources and SL_POOL_IS_EMPTY error will return.
+ In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try
+ again later to issue the command.
+
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Select)
+_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout);
+
+
+/*!
+ \brief Select's SlFdSet_t SET function
+
+ Sets current socket descriptor on SlFdSet_t container
+*/
+void SL_FD_SET(_i16 fd, SlFdSet_t *fdset);
+
+/*!
+ \brief Select's SlFdSet_t CLR function
+
+ Clears current socket descriptor on SlFdSet_t container
+*/
+void SL_FD_CLR(_i16 fd, SlFdSet_t *fdset);
+
+
+/*!
+ \brief Select's SlFdSet_t ISSET function
+
+ Checks if current socket descriptor is set (TRUE/FALSE)
+
+ \return Returns TRUE if set, FALSE if unset
+
+*/
+_i16 SL_FD_ISSET(_i16 fd, SlFdSet_t *fdset);
+
+/*!
+ \brief Select's SlFdSet_t ZERO function
+
+ Clears all socket descriptors from SlFdSet_t
+*/
+void SL_FD_ZERO(SlFdSet_t *fdset);
+
+
+
+#endif
+
+/*!
+ \brief set socket options
+
+ This function manipulate the options associated with a socket.
+ Options may exist at multiple protocol levels; they are always
+ present at the uppermost socket level.
+
+ When manipulating socket options the level at which the option resides
+ and the name of the option must be specified. To manipulate options at
+ the socket level, level is specified as SOL_SOCKET. To manipulate
+ options at any other level the protocol number of the appropriate proto-
+ col controlling the option is supplied. For example, to indicate that an
+ option is to be interpreted by the TCP protocol, level should be set to
+ the protocol number of TCP;
+
+ The parameters optval and optlen are used to access optval -
+ ues for setsockopt(). For getsockopt() they identify a
+ buffer in which the value for the requested option(s) are to
+ be returned. For getsockopt(), optlen is a value-result
+ parameter, initially containing the size of the buffer
+ pointed to by option_value, and modified on return to
+ indicate the actual size of the value returned. If no option
+ value is to be supplied or returned, option_value may be
+ NULL.
+
+ \param[in] sd socket handle
+ \param[in] level defines the protocol level for this option
+ - SL_SOL_SOCKET Socket level configurations (L4, transport layer)
+ - SL_IPPROTO_IP IP level configurations (L3, network layer)
+ - SL_SOL_PHY_OPT Link level configurations (L2, link layer)
+ \param[in] optname defines the option name to interrogate
+ - SL_SOL_SOCKET
+ - SL_SO_KEEPALIVE \n
+ Enable/Disable periodic keep alive.
+ Keeps TCP connections active by enabling the periodic transmission of messages \n
+ Timeout is 5 minutes.\n
+ Default: Enabled \n
+ This options takes SlSockKeepalive_t struct as parameter
+ - SL_SO_RCVTIMEO \n
+ Sets the timeout value that specifies the maximum amount of time an input function waits until it completes. \n
+ Default: No timeout \n
+ This options takes SlTimeval_t struct as parameter
+ - SL_SO_RCVBUF \n
+ Sets tcp max recv window size. \n
+ This options takes SlSockWinsize_t struct as parameter
+ - SL_SO_NONBLOCKING \n
+ Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n
+ Default: Blocking.
+ This options takes SlSockNonblocking_t struct as parameter
+ - SL_SO_SECMETHOD \n
+ Sets method to tcp secured socket (SL_SEC_SOCKET) \n
+ Default: SL_SO_SEC_METHOD_SSLv3_TLSV1_2 \n
+ This options takes SlSockSecureMethod struct as parameter
+ - SL_SO_SEC_MASK \n
+ Sets specific cipher to tcp secured socket (SL_SEC_SOCKET) \n
+ Default: "Best" cipher suitable to method \n
+ This options takes SlSockSecureMask struct as parameter
+ - SL_SO_SECURE_FILES_CA_FILE_NAME \n
+ Map secured socket to CA file by name \n
+ This options takes _u8 buffer as parameter
+ - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME \n
+ Map secured socket to private key by name \n
+ This options takes _u8 buffer as parameter
+ - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME \n
+ Map secured socket to certificate file by name \n
+ This options takes _u8 buffer as parameter
+ - SL_SO_SECURE_FILES_DH_KEY_FILE_NAME \n
+ Map secured socket to Diffie Hellman file by name \n
+ This options takes _u8 buffer as parameter
+ - SL_SO_CHANGE_CHANNEL \n
+ Sets channel in transceiver mode.
+ This options takes _u32 as channel number parameter
+ - SL_IPPROTO_IP
+ - SL_IP_MULTICAST_TTL \n
+ Set the time-to-live value of outgoing multicast packets for this socket. \n
+ This options takes _u8 as parameter
+ - SL_IP_ADD_MEMBERSHIP \n
+ UDP socket, Join a multicast group. \n
+ This options takes SlSockIpMreq struct as parameter
+ - SL_IP_DROP_MEMBERSHIP \n
+ UDP socket, Leave a multicast group \n
+ This options takes SlSockIpMreq struct as parameter
+ - SL_IP_RAW_RX_NO_HEADER \n
+ Raw socket remove IP header from received data. \n
+ Default: data includes ip header \n
+ This options takes _u32 as parameter
+ - SL_IP_HDRINCL \n
+ RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n
+ the IP_HDRINCL socket option is enabled on the socket. \n
+ When it is enabled, the packet must contain an IP header. \n
+ Default: disabled, IPv4 header generated by Network Stack \n
+ This options takes _u32 as parameter
+ - SL_IP_RAW_IPV6_HDRINCL (inactive) \n
+ RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n
+ the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n
+ Default: disabled, IPv4 header generated by Network Stack \n
+ This options takes _u32 as parameter
+ - SL_SOL_PHY_OPT
+ - SL_SO_PHY_RATE \n
+ RAW socket, set WLAN PHY transmit rate \n
+ The values are based on RateIndex_e \n
+ This options takes _u32 as parameter
+ - SL_SO_PHY_TX_POWER \n
+ RAW socket, set WLAN PHY TX power \n
+ Valid rage is 1-15 \n
+ This options takes _u32 as parameter
+ - SL_SO_PHY_NUM_FRAMES_TO_TX \n
+ RAW socket, set number of frames to transmit in transceiver mode.
+ Default: 1 packet
+ This options takes _u32 as parameter
+ - SL_SO_PHY_PREAMBLE \n
+ RAW socket, set WLAN PHY preamble for Long/Short\n
+ This options takes _u32 as parameter
+
+ \param[in] optval specifies a value for the option
+ \param[in] optlen specifies the length of the
+ option value
+
+ \return On success, zero is returned.
+ On error, a negative value is returned.
+ \sa sl_getsockopt
+ \note belongs to \ref basic_api
+ \warning
+ \par Examples:
+ \par
+ SL_SO_KEEPALIVE: (disable Keepalive)
+ \code
+ SlSockKeepalive_t enableOption;
+ enableOption.KeepaliveEnabled = 0;
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_KEEPALIVE, (_u8 *)&enableOption,sizeof(enableOption));
+ \endcode
+ \par
+ SL_SO_RCVTIMEO:
+ \code
+ struct SlTimeval_t timeVal;
+ timeVal.tv_sec = 1; // Seconds
+ timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVTIMEO, (_u8 *)&timeVal, sizeof(timeVal)); // Enable receive timeout
+ \endcode
+ \par
+ SL_SO_RCVBUF:
+ \code
+ SlSockWinsize_t size;
+ size.Winsize = 3000; // bytes
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVBUF, (_u8 *)&size, sizeof(size));
+ \endcode
+ \par
+ SL_SO_NONBLOCKING:
+ \code
+ SlSockNonblocking_t enableOption;
+ enableOption.NonblockingEnabled = 1;
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_NONBLOCKING, (_u8 *)&enableOption,sizeof(enableOption)); // Enable/disable nonblocking mode
+ \endcode
+ \par
+ SL_SO_SECMETHOD:
+ \code
+ SlSockSecureMethod method;
+ method.secureMethod = SL_SO_SEC_METHOD_SSLV3; // security method we want to use
+ SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET);
+ sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECMETHOD, (_u8 *)&method, sizeof(method));
+ \endcode
+ \par
+ SL_SO_SECURE_MASK:
+ \code
+ SlSockSecureMask cipher;
+ cipher.secureMask = SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA; // cipher type
+ SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET);
+ sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SEC_MASK,(_u8 *)&cipher, sizeof(cipher));
+ \endcode
+ \par
+ SL_SO_SECURE_FILES_CA_FILE_NAME:
+ \code
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CA_FILE_NAME,"exuifaxCaCert.der",strlen("exuifaxCaCert.der"));
+ \endcode
+
+ \par
+ SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME:
+ \code
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME,"myPrivateKey.der",strlen("myPrivateKey.der"));
+ \endcode
+
+ \par
+ SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME:
+ \code
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME,"myCertificate.der",strlen("myCertificate.der"));
+ \endcode
+
+ \par
+ SL_SO_SECURE_FILES_DH_KEY_FILE_NAME:
+ \code
+ sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_DH_KEY_FILE_NAME,"myDHinServerMode.der",strlen("myDHinServerMode.der"));
+ \endcode
+
+ \par
+ SL_IP_MULTICAST_TTL:
+ \code
+ _u8 ttl = 20;
+ sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_MULTICAST_TTL, &ttl, sizeof(ttl));
+ \endcode
+
+ \par
+ SL_IP_ADD_MEMBERSHIP:
+ \code
+ SlSockIpMreq mreq;
+ sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_ADD_MEMBERSHIP, &mreq, sizeof(mreq));
+ \endcode
+
+ \par
+ SL_IP_DROP_MEMBERSHIP:
+ \code
+ SlSockIpMreq mreq;
+ sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_DROP_MEMBERSHIP, &mreq, sizeof(mreq));
+ \endcode
+
+ \par
+ SL_SO_CHANGE_CHANNEL:
+ \code
+ _u32 newChannel = 6; // range is 1-13
+ sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_CHANGE_CHANNEL, &newChannel, sizeof(newChannel));
+ \endcode
+
+ \par
+ SL_IP_RAW_RX_NO_HEADER:
+ \code
+ _u32 header = 1; // remove ip header
+ sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_RX_NO_HEADER, &header, sizeof(header));
+ \endcode
+
+ \par
+ SL_IP_HDRINCL:
+ \code
+ _u32 header = 1;
+ sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_HDRINCL, &header, sizeof(header));
+ \endcode
+ \par
+ SL_IP_RAW_IPV6_HDRINCL:
+ \code
+ _u32 header = 1;
+ sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_IPV6_HDRINCL, &header, sizeof(header));
+ \endcode
+
+ \par
+ SL_SO_PHY_RATE:
+ \code
+ _u32 rate = 6; // see wlan.h RateIndex_e for values
+ sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_RATE, &rate, sizeof(rate));
+ \endcode
+
+ \par
+ SL_SO_PHY_TX_POWER:
+ \code
+ _u32 txpower = 1; // valid range is 1-15
+ sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_POWER, &txpower, sizeof(txpower));
+ \endcode
+
+ \par
+ SL_SO_PHY_NUM_FRAMES_TO_TX:
+ \code
+ _u32 numframes = 1;
+ sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes));
+ \endcode
+
+ \par
+ SL_SO_PHY_PREAMBLE:
+ \code
+ _u32 preamble = 1;
+ sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_PREAMBLE, &preamble, sizeof(preamble));
+ \endcode
+
+*/
+#if _SL_INCLUDE_FUNC(sl_SetSockOpt)
+_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen);
+#endif
+
+/*!
+ \brief Get socket options
+
+ This function manipulate the options associated with a socket.
+ Options may exist at multiple protocol levels; they are always
+ present at the uppermost socket level.
+
+ When manipulating socket options the level at which the option resides
+ and the name of the option must be specified. To manipulate options at
+ the socket level, level is specified as SOL_SOCKET. To manipulate
+ options at any other level the protocol number of the appropriate proto-
+ col controlling the option is supplied. For example, to indicate that an
+ option is to be interpreted by the TCP protocol, level should be set to
+ the protocol number of TCP;
+
+ The parameters optval and optlen are used to access optval -
+ ues for setsockopt(). For getsockopt() they identify a
+ buffer in which the value for the requested option(s) are to
+ be returned. For getsockopt(), optlen is a value-result
+ parameter, initially containing the size of the buffer
+ pointed to by option_value, and modified on return to
+ indicate the actual size of the value returned. If no option
+ value is to be supplied or returned, option_value may be
+ NULL.
+
+
+ \param[in] sd socket handle
+ \param[in] level defines the protocol level for this option
+ \param[in] optname defines the option name to interrogate
+ \param[out] optval specifies a value for the option
+ \param[out] optlen specifies the length of the
+ option value
+
+ \return On success, zero is returned.
+ On error, a negative value is returned.
+ \sa sl_SetSockOpt
+ \note See sl_SetSockOpt
+ belongs to \ref ext_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_GetSockOpt)
+_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen);
+#endif
+
+/*!
+ \brief read data from TCP socket
+
+ function receives a message from a connection-mode socket
+
+ \param[in] sd socket handle
+ \param[out] buf Points to the buffer where the
+ message should be stored.
+ \param[in] Len Specifies the length in bytes of
+ the buffer pointed to by the buffer argument.
+ Range: 1-16000 bytes
+ \param[in] flags Specifies the type of message
+ reception. On this version, this parameter is not
+ supported.
+
+ \return return the number of bytes received,
+ or a negative value if an error occurred.
+ using a non-blocking recv a possible negative value is SL_EAGAIN.
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+
+ \sa sl_RecvFrom
+ \note belongs to \ref recv_api
+ \warning
+ \par Examples:
+ \code An example of receiving data using TCP socket:
+
+ SlSockAddrIn_t Addr;
+ SlSockAddrIn_t LocalAddr;
+ _i16 AddrSize = sizeof(SlSockAddrIn_t);
+ _i16 SockID, newSockID;
+ _i16 Status;
+ _i8 Buf[RECV_BUF_LEN];
+
+ LocalAddr.sin_family = SL_AF_INET;
+ LocalAddr.sin_port = sl_Htons(5001);
+ LocalAddr.sin_addr.s_addr = 0;
+
+ Addr.sin_family = SL_AF_INET;
+ Addr.sin_port = sl_Htons(5001);
+ Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200));
+
+ SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0);
+ Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize);
+ Status = sl_Listen(SockID, 0);
+ newSockID = sl_Accept(SockID, (SlSockAddr_t*)&Addr, (SlSocklen_t*) &AddrSize);
+ Status = sl_Recv(newSockID, Buf, 1460, 0);
+ \endcode
+ \code Example code for Rx transceiver mode using a raw socket
+ _i8 buffer[1536];
+ _i16 sd;
+ _u16 size;
+ SlTransceiverRxOverHead_t *transHeader;
+ sd = sl_Socket(SL_AF_RF,SL_SOCK_RAW,11); // channel 11
+ while(1)
+ {
+ size = sl_Recv(sd,buffer,1536,0);
+ transHeader = (SlTransceiverRxOverHead_t *)buffer;
+ printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlTransceiverRxOverHead_t)],size);
+ }
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_Recv)
+_i16 sl_Recv(_i16 sd, void *buf, _i16 Len, _i16 flags);
+#endif
+
+/*!
+ \brief read data from socket
+
+ function receives a message from a connection-mode or
+ connectionless-mode socket
+
+ \param[in] sd socket handle
+ \param[out] buf Points to the buffer where the message should be stored.
+ \param[in] Len Specifies the length in bytes of the buffer pointed to by the buffer argument.
+ Range: 1-16000 bytes
+ \param[in] flags Specifies the type of message
+ reception. On this version, this parameter is not
+ supported.
+ \param[in] from pointer to an address structure
+ indicating the source
+ address.\n sockaddr:\n - code
+ for the address format. On this
+ version only AF_INET is
+ supported.\n - socket address,
+ the length depends on the code
+ format
+ \param[in] fromlen source address structure
+ size. This parameter MUST be set to the size of the structure pointed to by addr.
+
+
+ \return return the number of bytes received,
+ or a negative value if an error occurred.
+ using a non-blocking recv a possible negative value is SL_EAGAIN.
+ SL_RET_CODE_INVALID_INPUT (-2) will be returned if fromlen has incorrect length.
+ SL_POOL_IS_EMPTY may be return in case there are no resources in the system
+ In this case try again later or increase MAX_CONCURRENT_ACTIONS
+
+ \sa sl_Recv
+ \note belongs to \ref recv_api
+ \warning
+ \par Example:
+ \code An example of receiving data:
+
+ SlSockAddrIn_t Addr;
+ SlSockAddrIn_t LocalAddr;
+ _i16 AddrSize = sizeof(SlSockAddrIn_t);
+ _i16 SockID;
+ _i16 Status;
+ _i8 Buf[RECV_BUF_LEN];
+
+ LocalAddr.sin_family = SL_AF_INET;
+ LocalAddr.sin_port = sl_Htons(5001);
+ LocalAddr.sin_addr.s_addr = 0;
+
+ SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0);
+ Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize);
+ Status = sl_RecvFrom(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, (SlSocklen_t*)&AddrSize);
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_RecvFrom)
+_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 Len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen);
+#endif
+
+/*!
+ \brief write data to TCP socket
+
+ This function is used to transmit a message to another socket.
+ Returns immediately after sending data to device.
+ In case of TCP failure an async event SL_SOCKET_TX_FAILED_EVENT is going to
+ be received.
+ In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the
+ frame data buffer for WLAN FCS
+
+ \param[in] sd socket handle
+ \param[in] buf Points to a buffer containing
+ the message to be sent
+ \param[in] Len message size in bytes. Range: 1-1460 bytes
+ \param[in] flags Specifies the type of message
+ transmission. On this version, this parameter is not
+ supported for TCP.
+ For transceiver mode, the SL_RAW_RF_TX_PARAMS macro can be used to determine
+ transmission parameters (channel,rate,tx_power,preamble)
+
+
+ \return Return the number of bytes transmitted,
+ or -1 if an error occurred
+
+ \sa sl_SendTo
+ \note belongs to \ref send_api
+ \warning
+ \par Example:
+ \code An example of sending data:
+
+ SlSockAddrIn_t Addr;
+ _i16 AddrSize = sizeof(SlSockAddrIn_t);
+ _i16 SockID;
+ _i16 Status;
+ _i8 Buf[SEND_BUF_LEN];
+
+ Addr.sin_family = SL_AF_INET;
+ Addr.sin_port = sl_Htons(5001);
+ Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200));
+
+ SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0);
+ Status = sl_Connect(SockID, (SlSockAddr_t *)&Addr, AddrSize);
+ Status = sl_Send(SockID, Buf, 1460, 0 );
+
+ \endcode
+ */
+#if _SL_INCLUDE_FUNC(sl_Send )
+_i16 sl_Send(_i16 sd, const void *buf, _i16 Len, _i16 flags);
+#endif
+
+/*!
+ \brief write data to socket
+
+ This function is used to transmit a message to another socket
+ (connection less socket SOCK_DGRAM, SOCK_RAW).
+ Returns immediately after sending data to device.
+ In case of transmission failure an async event SL_SOCKET_TX_FAILED_EVENT is going to
+ be received.
+
+ \param[in] sd socket handle
+ \param[in] buf Points to a buffer containing
+ the message to be sent
+ \param[in] Len message size in bytes. Range: 1-1460 bytes
+ \param[in] flags Specifies the type of message
+ transmission. On this version, this parameter is not
+ supported
+ \param[in] to pointer to an address structure
+ indicating the destination
+ address.\n sockaddr:\n - code
+ for the address format. On this
+ version only AF_INET is
+ supported.\n - socket address,
+ the length depends on the code
+ format
+ \param[in] tolen destination address structure size
+
+ \return Return the number of transmitted bytes,
+ or -1 if an error occurred
+
+ \sa sl_Send
+ \note belongs to \ref send_api
+ \warning
+ \par Example:
+ \code An example of sending data:
+
+ SlSockAddrIn_t Addr;
+ _i16 AddrSize = sizeof(SlSockAddrIn_t);
+ _i16 SockID;
+ _i16 Status;
+ _i8 Buf[SEND_BUF_LEN];
+
+ Addr.sin_family = SL_AF_INET;
+ Addr.sin_port = sl_Htons(5001);
+ Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200));
+
+ SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0);
+ Status = sl_SendTo(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, AddrSize);
+
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_SendTo)
+_i16 sl_SendTo(_i16 sd, const void *buf, _i16 Len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen);
+#endif
+
+/*!
+ \brief Reorder the bytes of a 32-bit unsigned value
+
+ This function is used to Reorder the bytes of a 32-bit unsigned value from processor order to network order.
+
+ \param[in] var variable to reorder
+
+ \return Return the reorder variable,
+
+ \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept
+ \note belongs to \ref send_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Htonl )
+_u32 sl_Htonl( _u32 val );
+
+#define sl_Ntohl sl_Htonl /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */
+#endif
+
+/*!
+ \brief Reorder the bytes of a 16-bit unsigned value
+
+ This function is used to Reorder the bytes of a 16-bit unsigned value from processor order to network order.
+
+ \param[in] var variable to reorder
+
+ \return Return the reorder variable,
+
+ \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept
+ \note belongs to \ref send_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_Htons )
+_u16 sl_Htons( _u16 val );
+
+#define sl_Ntohs sl_Htons /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */
+#endif
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __SOCKET_H__ */
+
+
diff --git a/cc3200/simplelink/include/trace.h b/cc3200/simplelink/include/trace.h
new file mode 100644
index 0000000000..9e5ac519c1
--- /dev/null
+++ b/cc3200/simplelink/include/trace.h
@@ -0,0 +1,202 @@
+/*
+ * trace.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+#include "simplelink.h"
+#include "debug.h"
+
+#ifndef __SIMPLELINK_TRACE_H__
+#define __SIMPLELINK_TRACE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+#define SL_SYNC_SCAN_THRESHOLD (( _u32 )2000)
+
+#define _SL_ASSERT(expr) { ASSERT(expr); }
+#define _SL_ERROR(expr, error) { if(!(expr)){return (error); } }
+
+#define SL_HANDLING_ASSERT 2
+#define SL_HANDLING_ERROR 1
+#define SL_HANDLING_NONE 0
+
+#if defined(DEBUG) && !defined(BOOTLOADER)
+#define SL_SELF_COND_HANDLING SL_HANDLING_ASSERT
+#define SL_PROTOCOL_HANDLING SL_HANDLING_ASSERT
+#define SL_DRV_RET_CODE_HANDLING SL_HANDLING_ASSERT
+#define SL_NWP_IF_HANDLING SL_HANDLING_ASSERT
+#define SL_OSI_RET_OK_HANDLING SL_HANDLING_ASSERT
+#define SL_MALLOC_OK_HANDLING SL_HANDLING_ASSERT
+#define SL_USER_ARGS_HANDLING SL_HANDLING_ASSERT
+#else
+#define SL_SELF_COND_HANDLING SL_HANDLING_NONE
+#define SL_PROTOCOL_HANDLING SL_HANDLING_NONE
+#define SL_DRV_RET_CODE_HANDLING SL_HANDLING_NONE
+#define SL_NWP_IF_HANDLING SL_HANDLING_NONE
+#define SL_OSI_RET_OK_HANDLING SL_HANDLING_NONE
+#define SL_MALLOC_OK_HANDLING SL_HANDLING_NONE
+#define SL_USER_ARGS_HANDLING SL_HANDLING_NONE
+#endif
+
+#if (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ASSERT)
+#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)}
+#elif (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ERROR)
+#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return _RetVal;}
+#else
+#define VERIFY_RET_OK(Func) (Func);
+#endif
+
+#if (SL_PROTOCOL_HANDLING == SL_HANDLING_ASSERT)
+#define VERIFY_PROTOCOL(expr) _SL_ASSERT(expr)
+#elif (SL_PROTOCOL_HANDLING == SL_HANDLING_ERROR)
+#define VERIFY_PROTOCOL(expr) _SL_ERROR(expr, SL_RET_CODE_PROTOCOL_ERROR)
+#else
+#define VERIFY_PROTOCOL(expr)
+#endif
+
+#if (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ASSERT))
+#define VERIFY_SOCKET_CB(expr) _SL_ASSERT(expr)
+#elif (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ERROR))
+#define VERIFY_SOCKET_CB(expr) _SL_ERROR(expr, SL_RET_CODE_SELF_ERROR)
+#else
+#define VERIFY_SOCKET_CB(expr)
+#endif
+
+#if (SL_NWP_IF_HANDLING == SL_HANDLING_ASSERT)
+#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (len); RetSize = sl_IfWrite((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)}
+#define NWP_IF_READ_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (len); RetSize = sl_IfRead((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)}
+#elif (SL_NWP_IF_HANDLING == SL_HANDLING_ERROR)
+#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfWrite((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);}
+#define NWP_IF_READ_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfRead((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);}
+#else
+#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { sl_IfWrite((fd),(pBuff),(len));}
+#define NWP_IF_READ_CHECK(fd,pBuff,len) { sl_IfRead((fd),(pBuff),(len));}
+#endif
+
+#if (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ASSERT)
+#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)}
+#elif (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ERROR)
+#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return _RetVal;}
+#else
+#define OSI_RET_OK_CHECK(Func) (Func);
+#endif
+
+#if (SL_MALLOC_OK_HANDLING == SL_HANDLING_ASSERT)
+#define MALLOC_OK_CHECK(Ptr) _SL_ASSERT(NULL != Ptr)
+#elif (SL_MALLOC_OK_HANDLING == SL_HANDLING_ERROR)
+#define MALLOC_OK_CHECK(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_MALLOC_ERROR)
+#else
+#define MALLOC_OK_CHECK(Ptr)
+#endif
+
+#ifdef SL_INC_ARG_CHECK
+
+#if (SL_USER_ARGS_HANDLING == SL_HANDLING_ASSERT)
+#define ARG_CHECK_PTR(Ptr) _SL_ASSERT(NULL != Ptr)
+#elif (SL_USER_ARGS_HANDLING == SL_HANDLING_ERROR)
+#define ARG_CHECK_PTR(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_INVALID_INPUT)
+#else
+#define ARG_CHECK_PTR(Ptr)
+#endif
+
+#else
+#define ARG_CHECK_PTR(Ptr)
+#endif
+
+#if defined(DEBUG) && !defined(BOOTLOADER)
+#include "std.h"
+#define SL_DBG_TRACE_ENABLE
+#endif
+#ifdef SL_DBG_TRACE_ENABLE
+#define SL_TRACE0(level,msg_id,str)
+#define SL_TRACE1(level,msg_id,str,p1)
+#define SL_TRACE2(level,msg_id,str,p1,p2)
+#define SL_TRACE3(level,msg_id,str,p1,p2,p3)
+#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4)
+#define SL_ERROR_TRACE(msg_id,str) printf(str)
+#define SL_ERROR_TRACE1(msg_id,str,p1) printf(str,(p1))
+#define SL_ERROR_TRACE2(msg_id,str,p1,p2) printf(str,(p1),(p2))
+#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3) printf(str,(p1),(p2),(p3))
+#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4) printf(str,(p1),(p2),(p3),(p4))
+#define SL_TRACE_FLUSH()
+#else
+#define SL_TRACE0(level,msg_id,str)
+#define SL_TRACE1(level,msg_id,str,p1)
+#define SL_TRACE2(level,msg_id,str,p1,p2)
+#define SL_TRACE3(level,msg_id,str,p1,p2,p3)
+#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4)
+#define SL_ERROR_TRACE(msg_id,str)
+#define SL_ERROR_TRACE1(msg_id,str,p1)
+#define SL_ERROR_TRACE2(msg_id,str,p1,p2)
+#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3)
+#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4)
+#define SL_TRACE_FLUSH()
+#endif
+
+/* #define SL_DBG_CNT_ENABLE */
+#ifdef SL_DBG_CNT_ENABLE
+#define _SL_DBG_CNT_INC(Cnt) g_DbgCnt. ## Cnt++
+#define _SL_DBG_SYNC_LOG(index,value) {if(index < SL_DBG_SYNC_LOG_SIZE){*(_u32 *)&g_DbgCnt.SyncLog[index] = *(_u32 *)(value);}}
+
+#else
+#define _SL_DBG_CNT_INC(Cnt)
+#define _SL_DBG_SYNC_LOG(index,value)
+#endif
+
+#define SL_DBG_LEVEL_1 1
+#define SL_DBG_LEVEL_2 2
+#define SL_DBG_LEVEL_3 4
+#define SL_DBG_LEVEL_MASK (SL_DBG_LEVEL_2|SL_DBG_LEVEL_3)
+
+#define SL_INCLUDE_DBG_FUNC(Name) ((Name ## _DBG_LEVEL) & SL_DBG_LEVEL_MASK)
+
+#define _SlDrvPrintStat_DBG_LEVEL SL_DBG_LEVEL_3
+#define _SlDrvOtherFunc_DBG_LEVEL SL_DBG_LEVEL_1
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /*__SIMPLELINK_TRACE_H__*/
+
diff --git a/cc3200/simplelink/include/wlan.h b/cc3200/simplelink/include/wlan.h
new file mode 100644
index 0000000000..a0c73d1926
--- /dev/null
+++ b/cc3200/simplelink/include/wlan.h
@@ -0,0 +1,1320 @@
+/*
+ * wlan.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __WLAN_H__
+#define __WLAN_H__
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+/*!
+
+ \addtogroup wlan
+ @{
+
+*/
+
+#define SL_BSSID_LENGTH (6)
+#define MAXIMAL_SSID_LENGTH (32)
+
+#define NUM_OF_RATE_INDEXES (20)
+#define SIZE_OF_RSSI_HISTOGRAM (6)
+
+/* WLAN Disconnect Reason Codes */
+#define SL_DISCONNECT_RESERVED_0 (0)
+#define SL_DISCONNECT_UNSPECIFIED_REASON (1)
+#define SL_PREVIOUS_AUTHENTICATION_NO_LONGER_VALID (2)
+#define SL_DEAUTHENTICATED_BECAUSE_SENDING_STATION_IS_LEAVING (3)
+#define SL_DISASSOCIATED_DUE_TO_INACTIVITY (4)
+#define SL_DISASSOCIATED_BECAUSE_AP_IS_UNABLE_TO_HANDLE_ALL_CURRENTLY_ASSOCIATED_STATIONS (5)
+#define SL_CLASS_2_FRAME_RECEIVED_FROM_NONAUTHENTICATED_STATION (6)
+#define SL_CLASS_3_FRAME_RECEIVED_FROM_NONASSOCIATED_STATION (7)
+#define SL_DISASSOCIATED_BECAUSE_SENDING_STATION_IS_LEAVING_BSS (8)
+#define SL_STATION_REQUESTING_ASSOCIATION_IS_NOT_AUTHENTICATED_WITH_RESPONDING_STATION (9)
+#define SL_DISASSOCIATED_BECAUSE_THE_INFORMATION_IN_THE_POWER_CAPABILITY_ELEMENT_IS_UNACCEPTABLE (10)
+#define SL_DISASSOCIATED_BECAUSE_THE_INFORMATION_IN_THE_SUPPORTED_CHANNELS_ELEMENT_IS_UNACCEPTABLE (11)
+#define SL_DISCONNECT_RESERVED_1 (12)
+#define SL_INVALID_INFORMATION_ELEMENT (13)
+#define SL_MESSAGE_INTEGRITY_CODE_MIC_FAILURE (14)
+#define SL_FOUR_WAY_HANDSHAKE_TIMEOUT (15)
+#define SL_GROUP_KEY_HANDSHAKE_TIMEOUT (16)
+#define SL_RE_ASSOCIATION_REQUEST_PROBE_RESPONSE_BEACON_FRAME (17)
+#define SL_INVALID_GROUP_CIPHER (18)
+#define SL_INVALID_PAIRWISE_CIPHER (19)
+#define SL_INVALID_AKMP (20)
+#define SL_UNSUPPORTED_RSN_INFORMATION_ELEMENT_VERSION (21)
+#define SL_INVALID_RSN_INFORMATION_ELEMENT_CAPABILITIES (22)
+#define SL_IEEE_802_1X_AUTHENTICATION_FAILED (23)
+#define SL_CIPHER_SUITE_REJECTED_BECAUSE_OF_THE_SECURITY_POLICY (24)
+#define SL_DISCONNECT_RESERVED_2 (25)
+#define SL_DISCONNECT_RESERVED_3 (26)
+#define SL_DISCONNECT_RESERVED_4 (27)
+#define SL_DISCONNECT_RESERVED_5 (28)
+#define SL_DISCONNECT_RESERVED_6 (29)
+#define SL_DISCONNECT_RESERVED_7 (30)
+#define SL_DISCONNECT_RESERVED_8 (31)
+#define SL_DISASSOCIATED_FOR_UNSPECIFIED_QOS_RELATED_REASON (32)
+#define SL_DISASSOCIATED_BECAUSE_QAP_LACKS_SUFFICIENT_BANDWIDTH_FOR_THIS_QSTA (33)
+#define SL_DISASSOCIATED_BECAUSE_EXCESSIVE_NUMBER_OF_FRAMES_NEED_TO_BE_ACKNOWLEDGED (34)
+#define SL_DISASSOCIATED_BECAUSE_QSTA_IS_TRANSMITTING_OUTSIDE_THE_LIMITS_OF_ITS_TXOPS (35)
+#define SL_REQUESTED_FROM_PEER_QSTA_AS_THE_QSTA_IS_LEAVING_THE_QBSS (36)
+#define SL_REQUESTED_FROM_PEER_QSTA_AS_IT_DOES_NO_WANT_TO_USE_THE_MECHANISM (37)
+#define SL_REQUESTED_FROM_PEER_QSTA_AS_THE_QSTA_RECEIVED_FRAMES_SETUP_IS_REQUIRED (38)
+#define SL_REQUESTED_FROM_PEER_QSTA_DUE_TO_TIMEOUT (39)
+#define SL_PEER_QSTA_DOES_NOT_SUPPORT_THE_REQUESTED_CIPHER_SUITE (40)
+#define SL_CISCO_DEFINED (98)
+#define SL_CISCO_DEFINED_1 (99)
+#define SL_ROAMING_TRIGGER_NONE (100)
+#define SL_ROAMING_TRIGGER_LOW_QUALITY_FOR_BG_SCAN (101)
+#define SL_ROAMING_TRIGGER_HIGH_QUALITY_FOR_BG_SCAN (102)
+#define SL_ROAMING_TRIGGER_NORMAL_QUALITY_FOR_BG_SCAN (103)
+#define SL_ROAMING_TRIGGER_LOW_TX_RATE (104)
+#define SL_ROAMING_TRIGGER_LOW_SNR (105)
+#define SL_ROAMING_TRIGGER_LOW_QUALITY (106)
+#define SL_ROAMING_TRIGGER_TSPEC_REJECTED (107)
+#define SL_ROAMING_TRIGGER_MAX_TX_RETRIES (108)
+#define SL_ROAMING_TRIGGER_BSS_LOSS (109)
+#define SL_ROAMING_TRIGGER_BSS_LOSS_DUE_TO_MAX_TX_RETRY (110)
+#define SL_ROAMING_TRIGGER_SWITCH_CHANNEL (111)
+#define SL_ROAMING_TRIGGER_AP_DISCONNECT (112)
+#define SL_ROAMING_TRIGGER_SECURITY_ATTACK (113)
+#define SL_ROAMING_TRIGGER_MAX (114)
+#define SL_USER_INITIATED_DISCONNECTION (200)
+
+/* Wlan error codes */
+#define SL_ERROR_KEY_ERROR (-3)
+#define SL_ERROR_INVALID_ROLE (-71)
+#define SL_ERROR_INVALID_SECURITY_TYPE (-84)
+#define SL_ERROR_PASSPHRASE_TOO_LONG (-85)
+#define SL_ERROR_WPS_NO_PIN_OR_WRONG_PIN_LEN (-87)
+#define SL_ERROR_EAP_WRONG_METHOD (-88)
+#define SL_ERROR_PASSWORD_ERROR (-89)
+#define SL_ERROR_EAP_ANONYMOUS_LEN_ERROR (-90)
+#define SL_ERROR_SSID_LEN_ERROR (-91)
+#define SL_ERROR_USER_ID_LEN_ERROR (-92)
+#define SL_ERROR_ILLEGAL_WEP_KEY_INDEX (-95)
+#define SL_ERROR_INVALID_DWELL_TIME_VALUES (-96)
+#define SL_ERROR_INVALID_POLICY_TYPE (-97)
+#define SL_ERROR_PM_POLICY_INVALID_OPTION (-98)
+#define SL_ERROR_PM_POLICY_INVALID_PARAMS (-99)
+#define SL_ERROR_WIFI_ALREADY_DISCONNECTED (-129)
+#define SL_ERROR_WIFI_NOT_CONNECTED (-59)
+
+
+
+#define SL_SEC_TYPE_OPEN (0)
+#define SL_SEC_TYPE_WEP (1)
+#define SL_SEC_TYPE_WPA (2) /* deprecated */
+#define SL_SEC_TYPE_WPA_WPA2 (2)
+#define SL_SEC_TYPE_WPS_PBC (3)
+#define SL_SEC_TYPE_WPS_PIN (4)
+#define SL_SEC_TYPE_WPA_ENT (5)
+#define SL_SEC_TYPE_P2P_PBC (6)
+#define SL_SEC_TYPE_P2P_PIN_KEYPAD (7)
+#define SL_SEC_TYPE_P2P_PIN_DISPLAY (8)
+#define SL_SEC_TYPE_P2P_PIN_AUTO (9) /* NOT Supported yet */
+
+
+
+#define SL_SCAN_SEC_TYPE_OPEN (0)
+#define SL_SCAN_SEC_TYPE_WEP (1)
+#define SL_SCAN_SEC_TYPE_WPA (2)
+#define SL_SCAN_SEC_TYPE_WPA2 (3)
+
+
+
+#define TLS (0x1)
+#define MSCHAP (0x0)
+#define PSK (0x2)
+#define TTLS (0x10)
+#define PEAP0 (0x20)
+#define PEAP1 (0x40)
+#define FAST (0x80)
+
+#define FAST_AUTH_PROVISIONING (0x02)
+#define FAST_UNAUTH_PROVISIONING (0x01)
+#define FAST_NO_PROVISIONING (0x00)
+
+#define EAPMETHOD_PHASE2_SHIFT (8)
+#define EAPMETHOD_PAIRWISE_CIPHER_SHIFT (19)
+#define EAPMETHOD_GROUP_CIPHER_SHIFT (27)
+
+#define WPA_CIPHER_CCMP (0x1)
+#define WPA_CIPHER_TKIP (0x2)
+#define CC31XX_DEFAULT_CIPHER (WPA_CIPHER_CCMP | WPA_CIPHER_TKIP)
+
+#define EAPMETHOD(phase1,phase2,pairwise_cipher,group_cipher) \
+((phase1) | \
+ ((phase2) << EAPMETHOD_PHASE2_SHIFT ) |\
+ ((_u32)(pairwise_cipher) << EAPMETHOD_PAIRWISE_CIPHER_SHIFT ) |\
+ ((_u32)(group_cipher) << EAPMETHOD_GROUP_CIPHER_SHIFT ))
+
+/* phase1 phase2 pairwise_cipher group_cipher */
+#define SL_ENT_EAP_METHOD_TLS EAPMETHOD(TLS , 0 , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_TTLS_TLS EAPMETHOD(TTLS , TLS , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_TTLS_MSCHAPv2 EAPMETHOD(TTLS , MSCHAP , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_TTLS_PSK EAPMETHOD(TTLS , PSK , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_PEAP0_TLS EAPMETHOD(PEAP0 , TLS , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_PEAP0_MSCHAPv2 EAPMETHOD(PEAP0 , MSCHAP , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_PEAP0_PSK EAPMETHOD(PEAP0 , PSK , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_PEAP1_TLS EAPMETHOD(PEAP1 , TLS , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_PEAP1_MSCHAPv2 EAPMETHOD(PEAP1 , MSCHAP , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_PEAP1_PSK EAPMETHOD(PEAP1 , PSK , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_FAST_AUTH_PROVISIONING EAPMETHOD(FAST , FAST_AUTH_PROVISIONING , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_FAST_UNAUTH_PROVISIONING EAPMETHOD(FAST , FAST_UNAUTH_PROVISIONING , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+#define SL_ENT_EAP_METHOD_FAST_NO_PROVISIONING EAPMETHOD(FAST , FAST_NO_PROVISIONING , CC31XX_DEFAULT_CIPHER , CC31XX_DEFAULT_CIPHER)
+
+#define SL_LONG_PREAMBLE (0)
+#define SL_SHORT_PREAMBLE (1)
+
+#define SL_RAW_RF_TX_PARAMS_CHANNEL_SHIFT (0)
+#define SL_RAW_RF_TX_PARAMS_RATE_SHIFT (6)
+#define SL_RAW_RF_TX_PARAMS_POWER_SHIFT (11)
+#define SL_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT (15)
+
+#define SL_RAW_RF_TX_PARAMS(chan,rate,power,preamble) \
+ ((chan << SL_RAW_RF_TX_PARAMS_CHANNEL_SHIFT) | \
+ (rate << SL_RAW_RF_TX_PARAMS_RATE_SHIFT) | \
+ (power << SL_RAW_RF_TX_PARAMS_POWER_SHIFT) | \
+ (preamble << SL_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT))
+
+
+/* wlan config application IDs */
+#define SL_WLAN_CFG_AP_ID (0)
+#define SL_WLAN_CFG_GENERAL_PARAM_ID (1)
+#define SL_WLAN_CFG_P2P_PARAM_ID (2)
+
+/* wlan AP Config set/get options */
+#define WLAN_AP_OPT_SSID (0)
+#define WLAN_AP_OPT_CHANNEL (3)
+#define WLAN_AP_OPT_HIDDEN_SSID (4)
+#define WLAN_AP_OPT_SECURITY_TYPE (6)
+#define WLAN_AP_OPT_PASSWORD (7)
+#define WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE (9)
+#define WLAN_GENERAL_PARAM_OPT_STA_TX_POWER (10)
+#define WLAN_GENERAL_PARAM_OPT_AP_TX_POWER (11)
+
+#define WLAN_P2P_OPT_DEV_NAME (12)
+#define WLAN_P2P_OPT_DEV_TYPE (13)
+#define WLAN_P2P_OPT_CHANNEL_N_REGS (14)
+#define WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT (16)
+#define WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS (18) /* change the scan channels and RSSI threshold using this configuration option */
+
+/* SmartConfig CIPHER options */
+#define SMART_CONFIG_CIPHER_SFLASH (0) /* password is not delivered by the application. The Simple Manager should */
+ /* check if the keys are stored in the Flash. */
+#define SMART_CONFIG_CIPHER_AES (1) /* AES (other types are not supported) */
+#define SMART_CONFIG_CIPHER_NONE (0xFF) /* do not check in the flash */
+
+
+#define SL_POLICY_CONNECTION (0x10)
+#define SL_POLICY_SCAN (0x20)
+#define SL_POLICY_PM (0x30)
+#define SL_POLICY_P2P (0x40)
+
+#define VAL_2_MASK(position,value) ((1 & (value))<<(position))
+#define MASK_2_VAL(position,mask) (((1 << position) & (mask)) >> (position))
+
+#define SL_CONNECTION_POLICY(Auto,Fast,Open,anyP2P,autoSmartConfig) (VAL_2_MASK(0,Auto) | VAL_2_MASK(1,Fast) | VAL_2_MASK(2,Open) | VAL_2_MASK(3,anyP2P) | VAL_2_MASK(4,autoSmartConfig))
+#define SL_SCAN_POLICY_EN(policy) (MASK_2_VAL(0,policy))
+#define SL_SCAN_POLICY(Enable) (VAL_2_MASK(0,Enable))
+
+
+#define SL_NORMAL_POLICY (0)
+#define SL_LOW_LATENCY_POLICY (1)
+#define SL_LOW_POWER_POLICY (2)
+#define SL_ALWAYS_ON_POLICY (3)
+#define SL_LONG_SLEEP_INTERVAL_POLICY (4)
+
+#define SL_P2P_ROLE_NEGOTIATE (3)
+#define SL_P2P_ROLE_GROUP_OWNER (15)
+#define SL_P2P_ROLE_CLIENT (0)
+
+#define SL_P2P_NEG_INITIATOR_ACTIVE (0)
+#define SL_P2P_NEG_INITIATOR_PASSIVE (1)
+#define SL_P2P_NEG_INITIATOR_RAND_BACKOFF (2)
+
+#define POLICY_VAL_2_OPTIONS(position,mask,policy) ((mask & policy) << position )
+
+#define SL_P2P_POLICY(p2pNegType,p2pNegInitiator) (POLICY_VAL_2_OPTIONS(0,0xF,(p2pNegType > SL_P2P_ROLE_GROUP_OWNER ? SL_P2P_ROLE_GROUP_OWNER : p2pNegType)) | \
+ POLICY_VAL_2_OPTIONS(4,0x1,(p2pNegType > SL_P2P_ROLE_GROUP_OWNER ? 1:0)) | \
+ POLICY_VAL_2_OPTIONS(5,0x3, p2pNegInitiator))
+
+
+/* Info elements */
+
+#define INFO_ELEMENT_DEFAULT_ID (0) /* 221 will be used */
+
+/* info element size is up to 252 bytes (+ 3 bytes of OUI). */
+#define INFO_ELEMENT_MAX_SIZE (252)
+
+/* For AP - the total length of all info elements is 300 bytes (for example - 4 info elements of 75 bytes each) */
+#define INFO_ELEMENT_MAX_TOTAL_LENGTH_AP (300)
+/* For P2P - the total length of all info elements is 150 bytes (for example - 4 info elements of 40 bytes each) */
+#define INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO (160)
+
+#define INFO_ELEMENT_AP_ROLE (0)
+#define INFO_ELEMENT_P2P_GO_ROLE (1)
+
+/* we support up to 4 info elements per Role. */
+#define MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED (4)
+
+#define INFO_ELEMENT_DEFAULT_OUI_0 (0x08)
+#define INFO_ELEMENT_DEFAULT_OUI_1 (0x00)
+#define INFO_ELEMENT_DEFAULT_OUI_2 (0x28)
+
+#define INFO_ELEMENT_DEFAULT_OUI (0x000000) /* 08, 00, 28 will be used */
+
+/*****************************************************************************/
+/* Structure/Enum declarations */
+/*****************************************************************************/
+
+typedef enum
+{
+ RATE_1M = 1,
+ RATE_2M = 2,
+ RATE_5_5M = 3,
+ RATE_11M = 4,
+ RATE_6M = 6,
+ RATE_9M = 7,
+ RATE_12M = 8,
+ RATE_18M = 9,
+ RATE_24M = 10,
+ RATE_36M = 11,
+ RATE_48M = 12,
+ RATE_54M = 13,
+ RATE_MCS_0 = 14,
+ RATE_MCS_1 = 15,
+ RATE_MCS_2 = 16,
+ RATE_MCS_3 = 17,
+ RATE_MCS_4 = 18,
+ RATE_MCS_5 = 19,
+ RATE_MCS_6 = 20,
+ RATE_MCS_7 = 21,
+ MAX_NUM_RATES = 0xFF
+}SlRateIndex_e;
+
+typedef enum {
+ DEV_PW_DEFAULT=0,
+ DEV_PW_PIN_KEYPAD=1,
+ DEV_PW_PUSH_BUTTON=4,
+ DEV_PW_PIN_DISPLAY=5
+} sl_p2p_dev_password_method;
+
+
+typedef struct
+{
+ _u32 status;
+ _u32 ssid_len;
+ _u8 ssid[32];
+ _u32 private_token_len;
+ _u8 private_token[32];
+}slSmartConfigStartAsyncResponse_t;
+
+typedef struct
+{
+ _u16 status;
+ _u16 padding;
+}slSmartConfigStopAsyncResponse_t;
+
+typedef struct
+{
+ _u16 status;
+ _u16 padding;
+}slWlanConnFailureAsyncResponse_t;
+
+typedef struct
+{
+ _u8 connection_type;/* 0-STA,3-P2P_CL */
+ _u8 ssid_len;
+ _u8 ssid_name[32];
+ _u8 go_peer_device_name_len;
+ _u8 go_peer_device_name[32];
+ _u8 bssid[6];
+ _u8 reason_code;
+ _u8 padding[2];
+} slWlanConnectAsyncResponse_t;
+
+typedef struct
+{
+ _u8 go_peer_device_name[32];
+ _u8 mac[6];
+ _u8 go_peer_device_name_len;
+ _u8 wps_dev_password_id;
+ _u8 own_ssid[32];/* relevant for event sta-connected only */
+ _u8 own_ssid_len;/* relevant for event sta-connected only */
+ _u8 padding[3];
+}slPeerInfoAsyncResponse_t;
+
+
+typedef union
+{
+ slSmartConfigStartAsyncResponse_t smartConfigStartResponse; /*SL_WLAN_SMART_CONFIG_COMPLETE_EVENT*/
+ slSmartConfigStopAsyncResponse_t smartConfigStopResponse; /*SL_WLAN_SMART_CONFIG_STOP_EVENT */
+ slPeerInfoAsyncResponse_t APModeStaConnected; /* SL_WLAN_STA_CONNECTED_EVENT - relevant only in AP mode - holds information regarding a new STA connection */
+ slPeerInfoAsyncResponse_t APModestaDisconnected; /* SL_WLAN_STA_DISCONNECTED_EVENT - relevant only in AP mode - holds information regarding a STA disconnection */
+ slWlanConnectAsyncResponse_t STAandP2PModeWlanConnected; /* SL_WLAN_CONNECT_EVENT - relevant only in STA and P2P mode - holds information regarding a new connection */
+ slWlanConnectAsyncResponse_t STAandP2PModeDisconnected; /* SL_WLAN_DISCONNECT_EVENT - relevant only in STA and P2P mode - holds information regarding a disconnection */
+ slPeerInfoAsyncResponse_t P2PModeDevFound; /* SL_WLAN_P2P_DEV_FOUND_EVENT - relevant only in P2P mode */
+ slPeerInfoAsyncResponse_t P2PModeNegReqReceived; /* SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT - relevant only in P2P mode */
+ slWlanConnFailureAsyncResponse_t P2PModewlanConnectionFailure; /* SL_WLAN_CONNECTION_FAILED_EVENT - relevant only in P2P mode */
+
+} SlWlanEventData_u;
+
+typedef struct
+{
+ _u32 Event;
+ SlWlanEventData_u EventData;
+} SlWlanEvent_t;
+
+
+typedef struct
+{
+ _u32 ReceivedValidPacketsNumber; /* sum of the packets that been received OK (include filtered) */
+ _u32 ReceivedFcsErrorPacketsNumber; /* sum of the packets that been dropped due to FCS error */
+ _u32 ReceivedPlcpErrorPacketsNumber; /* sum of the packets that been dropped due to PLCP error */
+ _i16 AvarageDataCtrlRssi; /* average RSSI for all valid data packets received */
+ _i16 AvarageMgMntRssi; /* average RSSI for all valid management packets received */
+ _u16 RateHistogram[NUM_OF_RATE_INDEXES]; /* rate histogram for all valid packets received */
+ _u16 RssiHistogram[SIZE_OF_RSSI_HISTOGRAM]; /* RSSI histogram from -40 until -87 (all below and above\n RSSI will appear in the first and last cells */
+ _u32 StartTimeStamp; /* the time stamp started collecting the statistics in uSec */
+ _u32 GetTimeStamp; /* the time stamp called the get statistics command */
+}SlGetRxStatResponse_t;
+
+
+typedef struct
+{
+ _u8 ssid[MAXIMAL_SSID_LENGTH];
+ _u8 ssid_len;
+ _u8 sec_type;
+ _u8 bssid[SL_BSSID_LENGTH];
+ _i8 rssi;
+ _i8 reserved[3];
+}Sl_WlanNetworkEntry_t;
+
+
+typedef struct
+{
+ _u8 Type;
+ _i8* Key;
+ _u8 KeyLen;
+}SlSecParams_t;
+
+typedef struct
+{
+ _i8* User;
+ _u8 UserLen;
+ _i8* AnonUser;
+ _u8 AnonUserLen;
+ _u8 CertIndex; /* not supported */
+ _u32 EapMethod;
+}SlSecParamsExt_t;
+
+typedef struct
+{
+ _i8 User[32];
+ _u8 UserLen;
+ _i8 AnonUser[32];
+ _u8 AnonUserLen;
+ _u8 CertIndex; //not supported
+ _u32 EapMethod;
+}SlGetSecParamsExt_t;
+
+typedef enum
+{
+ ROLE_STA = 0,
+ ROLE_AP = 2,
+ ROLE_P2P = 3,
+ ROLE_STA_ERR = -1, /* Failure to load MAC/PHY in STA role */
+ ROLE_AP_ERR = -ROLE_AP, /* Failure to load MAC/PHY in AP role */
+ ROLE_P2P_ERR = -ROLE_P2P /* Failure to load MAC/PHY in P2P role */
+}SlWlanMode_t;
+
+typedef struct
+{
+ _u32 G_Channels_mask;
+ _i32 rssiThershold;
+}slWlanScanParamCommand_t;
+
+
+typedef struct
+{
+ _u8 id;
+ _u8 oui[3];
+ _u16 length;
+ _u8 data[252];
+} sl_protocol_InfoElement_t;
+
+typedef struct
+{
+ _u8 index; /* 0 - MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED */
+ _u8 role; /* bit0: AP = 0, GO = 1 */
+ sl_protocol_InfoElement_t ie;
+} sl_protocol_WlanSetInfoElement_t;
+
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+
+
+/*!
+ \brief Connect to wlan network as a station
+
+ \param[in] sec_type security types options: \n
+ - SL_SEC_TYPE_OPEN
+ - SL_SEC_TYPE_WEP
+ - SL_SEC_TYPE_WPA_WPA2
+ - SL_SEC_TYPE_WPA_ENT
+ - SL_SEC_TYPE_WPS_PBC
+ - SL_SEC_TYPE_WPS_PIN
+
+ \param[in] pName up to 32 bytes in case of STA the name is the SSID of the Access Point
+ \param[in] NameLen name length
+ \param[in] pMacAddr 6 bytes for MAC address
+ \param[in] pSecParams Security parameters (use NULL key for SL_SEC_TYPE_OPEN)
+ \param[in] pSecExtParams Enterprise parameters (set NULL in case Enterprise parameters is not in use)
+
+ \return On success, zero is returned. On error, negative is returned
+ In case error number (-71) is returned, it indicates a connection was activated while the device it running in AP role
+
+ \sa sl_WlanDisconnect
+ \note belongs to \ref ext_api
+ \warning In this version only single enterprise mode could be used
+ SL_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_SEC_TYPE_WPA_WPA2
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanConnect)
+_i16 sl_WlanConnect(_i8* pName, _i16 NameLen, _u8 *pMacAddr, SlSecParams_t* pSecParams , SlSecParamsExt_t* pSecExtParams);
+#endif
+
+/*!
+ \brief wlan disconnect
+
+ Disconnect connection
+
+ \return 0 disconnected done, other already disconnected
+
+ \sa sl_WlanConnect
+ \note belongs to \ref ext_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanDisconnect)
+_i16 sl_WlanDisconnect(void);
+#endif
+
+/*!
+ \brief add profile
+
+ When auto start is enabled, the device connects to a
+ station from the profiles table. Up to 7 profiles are
+ supported. If several profiles configured the device chose
+ the highest priority profile, within each priority group,
+ device will chose profile based on security policy, signal
+ strength, etc parameters.
+
+
+ \param[in] pName up to 32 bytes in case of STA the name is the
+ SSID of the Access Point
+ in case of P2P the name is the remote device name
+ \param[in] NameLen name length
+ \param[in] pMacAddr 6 bytes for MAC address
+ \param[in] pSecParams Security parameters - security type
+ (SL_SEC_TYPE_OPEN,SL_SEC_TYPE_WEP,SL_SEC_TYPE_WPA_WPA2,
+ SL_SEC_TYPE_P2P_PBC,SL_SEC_TYPE_P2P_PIN_KEYPAD,SL_SEC_TYPE_P2P_PIN_DISPLAY, SL_SEC_TYPE_WPA_ENT), key, and key length
+ in case of p2p security type pin the key refers to pin code
+ \param[in] pSecExtParams Enterprise parameters - identity, identity length,
+ Anonymous, Anonymous length, CertIndex (not supported,
+ certificates need to be placed in a specific file ID),
+ EapMethod.Use NULL in case Enterprise parameters is not in use
+
+ \param[in] Priority profile priority. Lowest priority: 0
+ \param[in] Options Not supported
+
+ \return On success, profile stored index is returned. On error, negative value is returned
+
+ \sa sl_WlanProfileGet , sl_WlanProfileDel
+ \note belongs to \ref ext_api
+ \warning Only one Enterprise profile is supported.
+ Please Note that in case of adding an existing profile (compared by pName,pMACAddr and security type)
+ the old profile will be deleted and the same index will be returned.
+ SL_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_SEC_TYPE_WPA_WPA2
+
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd)
+_i16 sl_WlanProfileAdd(_i8* pName, _i16 NameLen, _u8 *pMacAddr, SlSecParams_t* pSecParams , SlSecParamsExt_t* pSecExtParams, _u32 Priority, _u32 Options);
+#endif
+
+/*!
+ \brief get profile
+
+ read profile from the device
+
+ \param[in] Index profile stored index, if index does not exists
+ error is return
+ \param[out] pName up to 32 bytes, in case of sta mode the name of the Access Point
+ in case of p2p mode the name of the Remote Device
+ \param[out] pNameLen name length
+ \param[out] pMacAddr 6 bytes for MAC address
+ \param[out] pSecParams security parameters - security type
+ (LAN_SEC_UNSEC, WLAN_SEC_WEP, WLAN_SEC_WPA or
+ WLAN_SEC_WPA2, WLAN_SEC_P2P_PBC, WLAN_SEC_P2P_PIN_KEYPAD or WLAN_SEC_P2P_DISPLAY), key and key length are not
+ in case of p2p security type pin the key refers to pin code
+ return due to security reasons.
+ \param[out] pSecExtParams enterprise parameters - identity, identity
+ length, Anonymous, Anonymous length
+ CertIndex (not supported), EapMethod.
+ \param[out] Priority profile priority
+
+ \return On success, Profile security type is returned (0 or positive number). On error, -1 is
+ returned
+
+ \sa sl_WlanProfileAdd , sl_WlanProfileDel
+ \note belongs to \ref ext_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanProfileGet)
+_i16 sl_WlanProfileGet(_i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlSecParams_t* pSecParams, SlGetSecParamsExt_t* pSecExtParams, _u32 *pPriority);
+#endif
+
+/*!
+ \brief Delete WLAN profile
+
+ Delete WLAN profile
+
+ \param[in] index number of profile to delete.Possible values are 0 to 6.
+ Index value 255 will delete all saved profiles
+
+ \return On success, zero is returned. On error, -1 is
+ returned
+
+ \sa sl_WlanProfileAdd , sl_WlanProfileGet
+ \note belongs to \ref ext_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanProfileDel)
+_i16 sl_WlanProfileDel(_i16 Index);
+#endif
+
+/*!
+ \brief Set policy values
+
+ \param[in] Type Type of policy to be modified. The Options are:\n
+ - SL_POLICY_CONNECTION
+ - SL_POLICY_SCAN
+ - SL_POLICY_PM
+ - SL_POLICY_P2P
+ \param[in] Policy The option value which depends on action type
+ \param[in] pVal An optional value pointer
+ \param[in] ValLen An optional value length, in bytes
+ \return On success, zero is returned. On error, -1 is
+ returned
+ \sa sl_WlanPolicyGet
+ \note belongs to \ref ext_api
+ \warning
+ \par
+ SL_POLICY_CONNECTION type defines three options available to connect the CC31xx device to the AP: \n
+
+ - If Auto Connect is set, the CC31xx device tries to automatically reconnect to one of its stored profiles, each time the connection fails or the device is rebooted.\n
+ To set this option, use: \n
+ sl_WlanPolicySet(SL_POLICY_CONNECTION,SL_CONNECTION_POLICY(1,0,0,0,0),NULL,0)
+ - If Fast Connect is set, the CC31xx device tries to establish a fast connection to AP. \n
+ To set this option, use: \n
+ sl_WlanPolicySet(SL_POLICY_CONNECTION,SL_CONNECTION_POLICY(0,1,0,0,0),NULL,0)
+ - (relevant for P2P mode only) - If Any P2P is set, CC31xx/CC32xx device tries to automatically connect to the first P2P device available, \n
+ supporting push button only. To set this option, use: \n
+ sl_WlanPolicySet(SL_POLICY_CONNECTION,SL_CONNECTION_POLICY(0,0,0,1,0),NULL,0)
+ - For auto smart config upon restart (any command from Host will end this state) use: \n
+ sl_WlanPolicySet(SL_POLICY_CONNECTION,SL_CONNECTION_POLICY(0,0,0,0,1),NULL,0) \n
+ The options above could be combined to a single action, if more than one action is required. \n
+ \par
+ SL_POLICY_SCAN defines system scan time interval in case there is no connection. Default interval is 10 minutes. \n
+ After settings scan interval, an immediate scan is activated. The next scan will be based on the interval settings. \n
+ - For example, setting scan interval to 1 minute interval use: \n
+ _u32 intervalInSeconds = 60; \n
+ #define SL_SCAN_ENABLE 1 \n
+ sl_WlanPolicySet(SL_POLICY_SCAN,SL_SCAN_ENABLE, (_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); \n
+
+ - For example, disable scan: \n
+ #define SL_SCAN_DISABLE 0 \n
+ sl_WlanPolicySet(SL_POLICY_SCAN,SL_SCAN_DISABLE,0,0); \n
+ \par
+ SL_POLICY_PM defines a power management policy for Station mode only:
+ - For setting normal power management (default) policy use: sl_WlanPolicySet(SL_POLICY_PM , SL_NORMAL_POLICY, NULL,0)
+ - For setting low latency power management policy use: sl_WlanPolicySet(SL_POLICY_PM , SL_LOW_LATENCY_POLICY, NULL,0)
+ - For setting low power management policy use: sl_WlanPolicySet(SL_POLICY_PM , SL_LOW_POWER_POLICY, NULL,0)
+ - For setting always on power management policy use: sl_WlanPolicySet(SL_POLICY_PM , SL_ALWAYS_ON_POLICY, NULL,0)
+ - For setting Long Sleep Interval policy use: \n
+ _u16 PolicyBuff[4] = {0,0,800,0}; // PolicyBuff[2] is max sleep time in mSec \n
+ sl_WlanPolicySet(SL_POLICY_PM , SL_LONG_SLEEP_INTERVAL_POLICY, (_u8*)PolicyBuff,sizeof(PolicyBuff)); \n
+
+ SL_POLICY_P2P defines p2p negotiation policy parameters for P2P role:
+ - To set intent negotiation value, set on of the following:
+ SL_P2P_ROLE_NEGOTIATE - intent 3
+ SL_P2P_ROLE_GROUP_OWNER - intent 15
+ SL_P2P_ROLE_CLIENT - intent 0
+ - To set negotiation initiator value (initiator policy of first negotiation action frame), set on of the following:
+ SL_P2P_NEG_INITIATOR_ACTIVE
+ SL_P2P_NEG_INITIATOR_PASSIVE
+ SL_P2P_NEG_INITIATOR_RAND_BACKOFF
+ For example: \n
+ sl_WlanPolicySet(SL_POLICY_P2P, SL_P2P_POLICY(SL_P2P_ROLE_NEGOTIATE,SL_P2P_NEG_INITIATOR_RAND_BACKOFF),NULL,0)
+
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanPolicySet)
+_i16 sl_WlanPolicySet(_u8 Type , const _u8 Policy, _u8 *pVal,_u8 ValLen);
+#endif
+/*!
+ \brief get policy values
+
+ \param[in] Type SL_POLICY_CONNECTION, SL_POLICY_SCAN, SL_POLICY_PM,SL_POLICY_P2P \n
+
+ \param[in] Policy argument may be set to any value \n
+
+ \param[out] The returned values, depends on each policy type, will be stored in the allocated buffer pointed by pVal
+ with a maximum buffer length set by the calling function and pointed to by argument *pValLen
+
+ \return On success, zero is returned. On error, -1 is returned
+
+ \sa sl_WlanPolicySet
+
+ \note belongs to \ref ext_api
+
+ \warning The value pointed by the argument *pValLen should be set to a value different from 0 and
+ greater than the buffer length returned from the SL device. Otherwise, an error will be returned.
+
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet)
+_i16 sl_WlanPolicyGet(_u8 Type , _u8 Policy,_u8 *pVal,_u8 *pValLen);
+#endif
+/*!
+ \brief Gets the WLAN scan operation results
+
+ Gets scan results , gets entry from scan result table
+
+ \param[in] Index - Starting index identifier (range 0-19) for getting scan results
+ \param[in] Count - How many entries to fetch. Max is (20-"Index").
+ \param[out] pEntries - pointer to an allocated Sl_WlanNetworkEntry_t.
+ the number of array items should match "Count"
+ sec_type: SL_SCAN_SEC_TYPE_OPEN, SL_SCAN_SEC_TYPE_WEP, SL_SCAN_SEC_TYPE_WPA or SL_SCAN_SEC_TYPE_WPA2
+
+
+ \return Number of valid networks list items
+
+ \sa
+ \note belongs to \ref ext_api
+ \warning This command do not initiate any active scanning action
+ \par Example:
+ \code An example of fetching max 10 results:
+
+ Sl_WlanNetworkEntry_t netEntries[10];
+ _i16 resultsCount = sl_WlanGetNetworkList(0,10,&netEntries[0]);
+ for(i=0; i< resultsCount; i++)
+ {
+ printf("%s\n",netEntries[i].ssid);
+ }
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList)
+_i16 sl_WlanGetNetworkList(_u8 Index, _u8 Count, Sl_WlanNetworkEntry_t *pEntries);
+#endif
+
+/*!
+ \brief Start collecting wlan RX statistics, for unlimited time.
+
+ \return On success, zero is returned. On error, -1 is returned
+
+ \sa sl_WlanRxStatStop sl_WlanRxStatGet
+ \note belongs to \ref ext_api
+ \warning This API is deprecated and should be removed for next release
+ \par Example:
+ \code Getting wlan RX statistics:
+
+ void RxStatCollectTwice()
+ {
+ SlGetRxStatResponse_t rxStat;
+ _i16 rawSocket;
+ _i8 DataFrame[200];
+ struct SlTimeval_t timeval;
+ timeval.tv_sec = 0; // Seconds
+ timeval.tv_usec = 20000; // Microseconds. 10000 microseconds resolution
+
+ sl_WlanRxStatStart(); // set statistics mode
+
+ rawSocket = sl_Socket(SL_AF_RF, SL_SOCK_RAW, eChannel);
+ // set timeout - in case we have no activity for the specified channel
+ sl_SetSockOpt(rawSocket,SL_SOL_SOCKET,SL_SO_RCVTIMEO, &timeval, sizeof(timeval)); // Enable receive timeout
+ status = sl_Recv(rawSocket, DataFrame, sizeof(DataFrame), 0);
+
+ Sleep(1000); // sleep for 1 sec
+ sl_WlanRxStatGet(&rxStat,0); // statistics has been cleared upon read
+ Sleep(1000); // sleep for 1 sec
+ sl_WlanRxStatGet(&rxStat,0);
+
+ }
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart)
+_i16 sl_WlanRxStatStart(void);
+#endif
+
+
+/*!
+ \brief Stop collecting wlan RX statistic, (if previous called sl_WlanRxStatStart)
+
+ \return On success, zero is returned. On error, -1 is returned
+
+ \sa sl_WlanRxStatStart sl_WlanRxStatGet
+ \note belongs to \ref ext_api
+ \warning This API is deprecated and should be removed for next release
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop)
+_i16 sl_WlanRxStatStop(void);
+#endif
+
+
+/*!
+ \brief Get wlan RX statistics. upon calling this command, the statistics counters will be cleared.
+
+ \param[in] Flags should be 0 ( not applicable right now, will be added the future )
+ \param[in] pRxStat a pointer to SlGetRxStatResponse_t filled with Rx statistics results
+ \return On success, zero is returned. On error, -1 is returned
+
+ \sa sl_WlanRxStatStart sl_WlanRxStatStop
+ \note belongs to \ref ext_api
+ \warning
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet)
+_i16 sl_WlanRxStatGet(SlGetRxStatResponse_t *pRxStat,_u32 Flags);
+#endif
+
+
+/*!
+ \brief Stop Smart Config procedure. Once Smart Config will be stopped,
+ Asynchronous event will be received - SL_OPCODE_WLAN_SMART_CONFIG_STOP_ASYNC_RESPONSE.
+
+ \param[in] none
+ \param[out] none
+
+ \return 0 - if Stop Smart Config is about to be executed without errors.
+
+ \sa sl_WlanSmartConfigStart
+ \note belongs to \ref ext_api
+ \warning This API is deprecated and should be removed for next release
+
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanSmartConfigStop)
+_i16 sl_WlanSmartConfigStop(void);
+#endif
+
+/*!
+ \brief Start Smart Config procedure
+ \par
+ The target of the procedure is to let the \n
+ device to gain the network parameters: SSID and Password (if network is secured) \n
+ and to connect to it once located in the network range. \n
+ An external application should be used on a device connected to any mobile network. \n
+ The external application will transmit over the air the network parameters in secured manner.\n
+ The Password may be decrypted using a Key. \n
+ The decryption method may be decided in the command or embedded in the Flash. \n
+ The procedure can be activated for 1-3 group ID in the range of BIT_0 - BIT_15 where the default group ID id 0 (BIT_0) \n
+ Once Smart Config has ended successfully, Asynchronous event will be received - \n
+ SL_OPCODE_WLAN_SMART_CONFIG_START_ASYNC_RESPONSE. \n
+ The Event will hold the SSID and an extra field that might have been delivered as well (i.e. - device name)
+
+ \param[in] groupIdBitmask - each bit represent a group ID that should be searched.
+ The Default group ID id BIT_0. 2 more group can be searched
+ in addition. The range is BIT_0 - BIT_15.
+ \param[in] chiper - 0: check in flash, 1 - AES, 0xFF - do not check in flash
+ \param[in] publicKeyLen - public key len (used for the default group ID - BIT_0)
+ \param[in] group1KeyLen - group ID1 length
+ \param[in] group2KeyLen - group ID2 length
+ \param[in] publicKey - public key (used for the default group ID - BIT_0)
+ \param[in] group1Key - group ID1 key
+ \param[in] group2Key - group ID2 key
+
+ \param[out] none
+
+ \return 0 - if Smart Config started successfully.
+
+ \sa sl_WlanSmartConfigStop
+ \note belongs to \ref ext_api
+ \warning
+ \par
+ \code An example of starting smart Config on group ID's 0 + 1 + 2
+
+ sl_WlanSmartConfigStart(7, //group ID's (BIT_0 | BIT_1 | BIT_2)
+ 1, //decrypt key by AES method
+ 16, //decryption key length for group ID0
+ 16, //decryption key length for group ID1
+ 16, //decryption key length for group ID2
+ "Key0Key0Key0Key0", //decryption key for group ID0
+ "Key1Key1Key1Key1", //decryption key for group ID1
+ "Key2Key2Key2Key2" //decryption key for group ID2
+ );
+ \endcode
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanSmartConfigStart)
+_i16 sl_WlanSmartConfigStart(const _u32 groupIdBitmask,
+ const _u8 cipher,
+ const _u8 publicKeyLen,
+ const _u8 group1KeyLen,
+ const _u8 group2KeyLen,
+ const _u8* publicKey,
+ const _u8* group1Key,
+ const _u8* group2Key);
+#endif
+
+
+/*!
+ \brief Wlan set mode
+
+ Setting WLAN mode
+
+ \param[in] mode - WLAN mode to start the CC31xx device. Possible options are:
+ - ROLE_STA - for WLAN station mode
+ - ROLE_AP - for WLAN AP mode
+ - ROLE_P2P -for WLAN P2P mode
+ \return 0 - if mode was set correctly
+ \sa sl_Start sl_Stop
+ \note belongs to \ref ext_api
+ \warning After setting the mode the system must be restarted for activating the new mode
+ \par Example:
+ \code
+ //Switch from any role to STA:
+ sl_WlanSetMode(ROLE_STA);
+ sl_Stop(0);
+ sl_Start(NULL,NULL,NULL);
+ \endcode
+
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanSetMode)
+_i16 sl_WlanSetMode(const _u8 mode);
+#endif
+
+
+/*!
+ \brief Internal function for setting WLAN configurations
+
+ \return On success, zero is returned. On error one of the following error codes returned:
+ - CONF_ERROR (-1)
+ - CONF_NVMEM_ACCESS_FAILED (-2)
+ - CONF_OLD_FILE_VERSION (-3)
+ - CONF_ERROR_NO_SUCH_COUNTRY_CODE (-4)
+
+
+ \param[in] ConfigId - configuration id
+ - SL_WLAN_CFG_AP_ID
+ - SL_WLAN_CFG_GENERAL_PARAM_ID
+ - SL_WLAN_CFG_P2P_PARAM_ID
+
+ \param[in] ConfigOpt - configurations option
+ - SL_WLAN_CFG_AP_ID
+ - WLAN_AP_OPT_SSID \n
+ Set SSID for AP mode. \n
+ This options takes _u8 buffer as parameter
+ - WLAN_AP_OPT_CHANNEL \n
+ Set channel for AP mode. \n
+ The channel is dependant on the country code which is set. i.e. for "US" the channel should be in the range of [1-11] \n
+ This option takes _u8 as a parameter
+ - WLAN_AP_OPT_HIDDEN_SSID \n
+ Set Hidden SSID Mode for AP mode.Hidden options: \n
+ 0: disabled \n
+ 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n
+ 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n
+ clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n
+ This option takes _u8 as a parameter
+ - WLAN_AP_OPT_SECURITY_TYPE \n
+ Set Security type for AP mode. Security options are:
+ - Open security: SL_SEC_TYPE_OPEN
+ - WEP security: SL_SEC_TYPE_WEP
+ - WPA security: SL_SEC_TYPE_WPA_WPA2 \n
+ This option takes _u8 pointer as a parameter
+ - WLAN_AP_OPT_PASSWORD \n
+ Set Password for for AP mode (for WEP or for WPA): \n
+ Password - for WPA: 8 - 63 characters \n
+ for WEP: 5 / 13 characters (ascii) \n
+ This options takes _u8 buffer as parameter
+ - SL_WLAN_CFG_GENERAL_PARAM_ID
+ - WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n
+ Set Country Code for AP mode \n
+ This options takes _u8 2 bytes buffer as parameter
+ - WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n
+ Set STA mode Tx power level \n
+ Number between 0-15, as dB offset from max power (0 will set MAX power) \n
+ This options takes _u8 as parameter
+ - WLAN_GENERAL_PARAM_OPT_AP_TX_POWER
+ Set AP mode Tx power level \n
+ Number between 0-15, as dB offset from max power (0 will set MAX power) \n
+ This options takes _u8 as parameter
+ - WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT
+ Set Info Element for AP mode. \n
+ The Application can set up to MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED info elements per Role (AP / P2P GO). \n
+ To delete an info element use the relevant index and length = 0. \n
+ The Application can set up to MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED to the same role. \n
+ However, for AP - no more than INFO_ELEMENT_MAX_TOTAL_LENGTH_AP bytes can be stored for all info elements. \n
+ For P2P GO - no more than INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO bytes can be stored for all info elements. \n
+ This option takes sl_protocol_WlanSetInfoElement_t as parameter
+ - SL_WLAN_CFG_P2P_PARAM_ID
+ - WLAN_P2P_OPT_DEV_TYPE \n
+ Set P2P Device type.Maximum length of 17 characters. Device type is published under P2P I.E, \n
+ allows to make devices easier to recognize. \n
+ In case no device type is set, the default type is "1-0050F204-1" \n
+ This options takes _u8 buffer as parameter
+ - WLAN_P2P_OPT_CHANNEL_N_REGS \n
+ Set P2P Channels. \n
+ listen channel (either 1/6/11 for 2.4GHz) \n
+ listen regulatory class (81 for 2.4GHz) \n
+ oper channel (either 1/6/11 for 2.4GHz) \n
+ oper regulatory class (81 for 2.4GHz) \n
+ listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n
+ oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n
+ channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected.
+ This option takes pointer to _u8[4] as parameter
+
+ \param[in] ConfigLen - configurations len
+
+ \param[in] pValues - configurations values
+
+ \sa
+ \note
+ \warning
+ \par Examples:
+ \par
+ WLAN_AP_OPT_SSID:
+ \code
+ _u8 str[33];
+ memset(str, 0, 33);
+ memcpy(str, ssid, len); // ssid string of 32 characters
+ sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_SSID, strlen(ssid), str);
+ \endcode
+ \par
+ WLAN_AP_OPT_CHANNEL:
+ \code
+ _u8 val = channel;
+ sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_CHANNEL, 1, (_u8 *)&val);
+ \endcode
+ \par
+ WLAN_AP_OPT_HIDDEN_SSID:
+ \code
+ _u8 val = hidden;
+ sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_HIDDEN_SSID, 1, (_u8 *)&val);
+ \endcode
+ \par
+ WLAN_AP_OPT_SECURITY_TYPE:
+ \code
+ _u8 val = SL_SEC_TYPE_WPA_WPA2;
+ sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_SECURITY_TYPE, 1, (_u8 *)&val);
+ \endcode
+ \par
+ WLAN_AP_OPT_PASSWORD:
+ \code
+ _u8 str[65];
+ _u16 len = strlen(password);
+ memset(str, 0, 65);
+ memcpy(str, password, len);
+ sl_WlanSet(SL_WLAN_CFG_AP_ID, WLAN_AP_OPT_PASSWORD, len, (_u8 *)str);
+ \endcode
+ \par
+ WLAN_GENERAL_PARAM_OPT_STA_TX_POWER:
+ \code
+ _u8 stapower=(_u8)power;
+ sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, WLAN_GENERAL_PARAM_OPT_STA_TX_POWER,1,(_u8 *)&stapower);
+ \endcode
+ \par
+ WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE:
+ \code
+ _u8* str = (_u8 *) country; // string of 2 characters. i.e. - "US"
+ sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE, 2, str);
+ \endcode
+ \par
+ WLAN_GENERAL_PARAM_OPT_AP_TX_POWER:
+ \code
+ _u8 appower=(_u8)power;
+ sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, WLAN_GENERAL_PARAM_OPT_AP_TX_POWER,1,(_u8 *)&appower);
+ \endcode
+ \par
+ WLAN_P2P_OPT_DEV_TYPE:
+ \code
+ _u8 str[17];
+ _u16 len = strlen(device_type);
+ memset(str, 0, 17);
+ memcpy(str, device_type, len);
+ sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, WLAN_P2P_OPT_DEV_TYPE, len, str);
+ \endcode
+ \par
+ WLAN_P2P_OPT_CHANNEL_N_REGS:
+ \code
+ _u8 str[4];
+ str[0] = (_u8)11; // listen channel
+ str[1] = (_u8)81; // listen regulatory class
+ str[2] = (_u8)6; // oper channel
+ str[3] = (_u8)81; // oper regulatory class
+ sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, WLAN_P2P_OPT_CHANNEL_N_REGS, 4, str);
+ \endcode
+ \par
+ WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT:
+ \code
+ sl_protocol_WlanSetInfoElement_t infoele;
+ infoele.index = Index; // Index of the info element. range: 0 - MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED
+ infoele.role = Role; // INFO_ELEMENT_AP_ROLE (0) or INFO_ELEMENT_P2P_GO_ROLE (1)
+ infoele.ie.id = Id; // Info element ID. if INFO_ELEMENT_DEFAULT_ID (0) is set, ID will be set to 221.
+ // Organization unique ID. If all 3 bytes are zero - it will be replaced with 08,00,28.
+ infoele.ie.oui[0] = Oui0; // Organization unique ID first Byte
+ infoele.ie.oui[1] = Oui1; // Organization unique ID second Byte
+ infoele.ie.oui[2] = Oui2; // Organization unique ID third Byte
+ infoele.ie.length = Len; // Length of the info element. must be smaller than 253 bytes
+ memset(infoele.ie.data, 0, INFO_ELEMENT_MAX_SIZE);
+ if ( Len <= INFO_ELEMENT_MAX_SIZE )
+ {
+ memcpy(infoele.ie.data, IE, Len); // Info element. length of the info element is [0-252]
+ sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT,sizeof(sl_protocol_WlanSetInfoElement_t),(_u8* ) &infoele);
+ }
+ sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT,sizeof(sl_protocol_WlanSetInfoElement_t),(_u8* ) &infoele);
+ \endcode
+
+*/
+#if _SL_INCLUDE_FUNC(sl_WlanSet)
+_i16 sl_WlanSet(_u16 ConfigId ,_u16 ConfigOpt,_u16 ConfigLen, _u8 *pValues);
+#endif
+
+/*!
+ \brief Internal function for getting WLAN configurations
+
+ \return On success, zero is returned. On error, -1 is
+ returned
+
+ \param[in] ConfigId - configuration id
+ - SL_WLAN_CFG_AP_ID
+ - SL_WLAN_CFG_GENERAL_PARAM_ID
+ - SL_WLAN_CFG_P2P_PARAM_ID
+
+ \param[out] pConfigOpt - get configurations option
+ - SL_WLAN_CFG_AP_ID
+ - WLAN_AP_OPT_SSID \n
+ Get SSID for AP mode. \n
+ Get up to 32 characters of SSID \n
+ This options takes _u8 as parameter
+ - WLAN_AP_OPT_CHANNEL \n
+ Get channel for AP mode. \n
+ This option takes _u8 as a parameter
+ - WLAN_AP_OPT_HIDDEN_SSID \n
+ Get Hidden SSID Mode for AP mode.Hidden options: \n
+ 0: disabled \n
+ 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n
+ 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n
+ clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n
+ This option takes _u8 as a parameter
+ - WLAN_AP_OPT_SECURITY_TYPE \n
+ Get Security type for AP mode. Security options are:
+ - Open security: SL_SEC_TYPE_OPEN
+ - WEP security: SL_SEC_TYPE_WEP
+ - WPA security: SL_SEC_TYPE_WPA_WPA2 \n
+ This option takes _u8 as a parameter
+ - WLAN_AP_OPT_PASSWORD \n
+ Get Password for for AP mode (for WEP or for WPA): \n
+ Returns password - string, fills up to 64 characters. \n
+ This options takes _u8 buffer as parameter
+ - SL_WLAN_CFG_GENERAL_PARAM_ID
+ - WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS \n
+ Get scan parameters.
+ This option uses slWlanScanParamCommand_t as parameter
+ - WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n
+ Get Country Code for AP mode \n
+ This options takes _u8 buffer as parameter
+ - WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n
+ Get STA mode Tx power level \n
+ Number between 0-15, as dB offset from max power (0 indicates MAX power) \n
+ This options takes _u8 as parameter
+ - WLAN_GENERAL_PARAM_OPT_AP_TX_POWER
+ Get AP mode Tx power level \n
+ Number between 0-15, as dB offset from max power (0 indicates MAX power) \n
+ This options takes _u8 as parameter
+ - SL_WLAN_CFG_P2P_PARAM_ID
+ - WLAN_P2P_OPT_CHANNEL_N_REGS \n
+ Get P2P Channels. \n
+ listen channel (either 1/6/11 for 2.4GHz) \n
+ listen regulatory class (81 for 2.4GHz) \n
+ oper channel (either 1/6/11 for 2.4GHz) \n
+ oper regulatory class (81 for 2.4GHz) \n
+ listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n
+ oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n
+ channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected. \n
+ This option takes pointer to _u8[4] as parameter
+
+ \param[out] pConfigLen - The length of the allocated memory as input, when the
+ function complete, the value of this parameter would be
+ the len that actually read from the device.
+ If the device return length that is longer from the input
+ value, the function will cut the end of the returned structure
+ and will return SL_ESMALLBUF.
+
+
+ \param[out] pValues - get configurations values
+
+ \sa sl_WlanSet
+
+ \note
+
+ \warning
+
+ \par Examples:
+ \par
+ WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS:
+ \code
+ slWlanScanParamCommand_t ScanParamConfig;
+ _u16 Option = WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS;
+ _u16 OptionLen = sizeof(slWlanScanParamCommand_t);
+ sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&ScanParamConfig);
+ \endcode
+ \par
+ WLAN_GENERAL_PARAM_OPT_AP_TX_POWER:
+ \code
+ _i16 TXPower = 0;
+ _u16 Option = WLAN_GENERAL_PARAM_OPT_AP_TX_POWER;
+ _u16 OptionLen = sizeof(_i16);
+ sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower);
+ \endcode
+ \par
+ WLAN_GENERAL_PARAM_OPT_STA_TX_POWER:
+ \code
+ _i16 TXPower = 0;
+ _u16 Option = WLAN_GENERAL_PARAM_OPT_STA_TX_POWER;
+ _u16 OptionLen = sizeof(_i16);
+
+ sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower);
+ \endcode
+ \par
+ WLAN_P2P_OPT_DEV_TYPE:
+ \code
+ _i8 device_type[18];
+ _u16 len = 18;
+ _u16 config_opt = WLAN_P2P_OPT_DEV_TYPE;
+ sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt , &len, (_u8* )device_type);
+ \endcode
+ \par
+ WLAN_AP_OPT_SSID:
+ \code
+ _i8 ssid[32];
+ _u16 len = 32;
+ _u16 config_opt = WLAN_AP_OPT_SSID;
+ sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt , &len, (_u8* )ssid);
+ \endcode
+ \par
+ WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE:
+ \code
+ _i8 country[3];
+ _u16 len = 3;
+ _u16 config_opt = WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE;
+ sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID, &config_opt, &len, (_u8* )country);
+ \endcode
+ \par
+ WLAN_AP_OPT_CHANNEL:
+ \code
+ _i8 channel;
+ _u16 len = 1;
+ _u16 config_opt = WLAN_AP_OPT_CHANNEL;
+ sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&channel);
+ \endcode
+ \par
+ WLAN_AP_OPT_HIDDEN_SSID:
+ \code
+ _u8 hidden;
+ _u16 len = 1;
+ _u16 config_opt = WLAN_AP_OPT_HIDDEN_SSID;
+ sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&hidden);
+ \endcode
+ \par
+ WLAN_AP_OPT_SECURITY_TYPE:
+ \code
+ _u8 sec_type;
+ _u16 len = 1;
+ _u16 config_opt = WLAN_AP_OPT_SECURITY_TYPE;
+ sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&sec_type);
+ \endcode
+ \par
+ WLAN_AP_OPT_PASSWORD:
+ \code
+ _u8 password[64];
+ _u16 len = 64;
+ memset(password,0,64);
+ _u16 config_opt = WLAN_AP_OPT_PASSWORD;
+ sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )password);
+
+ \endcode
+ \par
+ WLAN_P2P_OPT_CHANNEL_N_REGS:
+ \code
+ _u16 listen_channel,listen_reg,oper_channel,oper_reg;
+ _u16 len = 4;
+ _u16 config_opt = WLAN_P2P_OPT_CHANNEL_N_REGS;
+ _u8 channel_n_regs[4];
+ sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt, &len, (_u8* )channel_n_regs);
+ listen_channel = channel_n_regs[0];
+ listen_reg = channel_n_regs[1];
+ oper_channel = channel_n_regs[2];
+ oper_reg = channel_n_regs[3];
+ \endcode
+*/
+
+#if _SL_INCLUDE_FUNC(sl_WlanGet)
+_i16 sl_WlanGet(_u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues);
+#endif
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __WLAN_H__ */
+
diff --git a/cc3200/simplelink/include/wlan_rx_filters.h b/cc3200/simplelink/include/wlan_rx_filters.h
new file mode 100644
index 0000000000..df48ff5602
--- /dev/null
+++ b/cc3200/simplelink/include/wlan_rx_filters.h
@@ -0,0 +1,930 @@
+/*
+ * wlan_rx_filters.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef RX_FILTERS_PREPROCESSOR_CLI_IF_H_
+#define RX_FILTERS_PREPROCESSOR_CLI_IF_H_
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+/*!
+ * \def SL_RX_FILTER_MAX_FILTERS
+ * The Max number of filters for 64 filters
+ */
+#define SL_RX_FILTER_MAX_FILTERS 64
+
+/*!
+ * \def SL_RX_FILTER_MAX_PRE_PREPARED_FILTERS_SETS
+ * The Max number of software filters
+ */
+#define SL_RX_FILTER_MAX_PRE_PREPARED_FILTERS_SETS (32)
+/*!
+ * \def SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ *
+ */
+#define SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS (2)
+/*!
+ * \def SL_RX_FILTER_NUM_OF_FILTER_PAYLOAD_ARGS
+ *
+ */
+#define SL_RX_FILTER_NUM_OF_FILTER_PAYLOAD_ARGS (2)
+/*!
+ * \def SL_RX_FILTER_NUM_OF_FILTER_PAYLOAD_ARGS
+ *
+ */
+#define SL_RX_FILTER_NUM_OF_COMBINATION_TYPE_ARGS (2)
+/*!
+ * \def SL_RX_FILTER_LENGTH_OF_REGX_PATTERN_LENGTH
+ *
+ */
+#define SL_RX_FILTER_LENGTH_OF_REGX_PATTERN_LENGTH (32)
+
+
+/* List of possible error numbers */
+#define RXFL_OK (0) /* O.K */
+#define RXFL_OUTPUT_OR_INPUT_BUFFER_LENGTH_TOO_SMALL (76) /* ! The output buffer length is smaller than required for that operation */
+#define RXFL_DEPENDENT_FILTER_SOFTWARE_FILTER_NOT_FIT (75) /* Node filter can't be child of software filter and vice_versa */
+#define RXFL_DEPENDENCY_IS_NOT_PERSISTENT (74) /* Dependency filter is not persistent */
+#define RXFL_SYSTEM_STATE_NOT_SUPPORTED_FOR_THIS_FILTER (72) /* System state is not supported */
+#define RXFL_TRIGGER_USE_REG5_TO_REG8 (71) /* Only counters 5 - 8 are allowed, for Tigger */
+#define RXFL_TRIGGER_USE_REG1_TO_REG4 (70) /* Only counters 1 - 4 are allowed, for trigger */
+#define RXFL_ACTION_USE_REG5_TO_REG8 (69) /* Only counters 5 - 8 are allowed, for action */
+#define RXFL_ACTION_USE_REG1_TO_REG4 (68) /* Only counters 1 - 4 are allowed, for action */
+#define RXFL_FIELD_SUPPORT_ONLY_EQUAL_AND_NOTEQUAL (67) /* Rule compare function Id is out of range */
+#define RXFL_WRONG_MULTICAST_BROADCAST_ADDRESS (66) /* The address should be of type mutlicast or broadcast */
+#define RXFL_THE_FILTER_IS_NOT_OF_HEADER_TYPE (65) /* The filter should be of header type */
+#define RXFL_WRONG_COMPARE_FUNC_FOR_BROADCAST_ADDRESS (64) /* The compare funcion is not suitable for broadcast address */
+#define RXFL_WRONG_MULTICAST_ADDRESS (63) /* The address should be of muticast type */
+#define RXFL_DEPENDENT_FILTER_IS_NOT_PERSISTENT (62) /* The dependency filter is not persistent */
+#define RXFL_DEPENDENT_FILTER_IS_NOT_ENABLED (61) /* The dependency filter is not enabled */
+#define RXFL_FILTER_HAS_CHILDS (60) /* The filter has childs and can't be removed */
+#define RXFL_CHILD_IS_ENABLED (59) /* Can't disable filter while the child is enabled */
+#define RXFL_DEPENDENCY_IS_DISABLED (58) /* Can't enable filetr in case its depndency filter is disabled */
+#define RXFL_NUMBER_OF_CONNECTION_POINTS_EXCEEDED (52) /* Number of connection points exceeded */
+#define RXFL_DEPENDENT_FILTER_DEPENDENCY_ACTION_IS_DROP (51) /* The dependent filter has Drop action, thus the filter can't be created */
+#define RXFL_FILTER_DO_NOT_EXISTS (50) /* The filter doesn't exists */
+#define RXFL_DEPEDENCY_NOT_ON_THE_SAME_LAYER (49) /* The filter and its dependency must be on the same layer */
+#define RXFL_NUMBER_OF_ARGS_EXCEEDED (48) /* Number of arguments excceded */
+#define RXFL_ACTION_NO_REG_NUMBER (47) /* Action require counter number */
+#define RXFL_DEPENDENT_FILTER_LAYER_DO_NOT_FIT (46) /* the filter and its dependency should be from the same layer */
+#define RXFL_DEPENDENT_FILTER_SYSTEM_STATE_DO_NOT_FIT (45) /* The filter and its dependency system state don't fit */
+#define RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_2 (44) /* The parent filter don't exist */
+#define RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_1 (43) /* The parent filter is null */
+#define RXFL_RULE_HEADER_ACTION_TYPE_NOT_SUPPORTED (42) /* The action type is not supported */
+#define RXFL_RULE_HEADER_TRIGGER_COMPARE_FUNC_OUT_OF_RANGE (41) /* The Trigger comparision function is out of range */
+#define RXFL_RULE_HEADER_TRIGGER_OUT_OF_RANGE (40) /* The Trigger is out of range */
+#define RXFL_RULE_HEADER_COMPARE_FUNC_OUT_OF_RANGE (39) /* The rule compare function is out of range */
+#define RXFL_FRAME_TYPE_NOT_SUPPORTED (38) /* ASCII frame type string is illegal */
+#define RXFL_RULE_FIELD_ID_NOT_SUPPORTED (37) /* Rule field ID is out of range */
+#define RXFL_RULE_HEADER_FIELD_ID_ASCII_NOT_SUPPORTED (36) /* This ASCII field ID is not supported */
+#define RXFL_RULE_HEADER_NOT_SUPPORTED (35) /* The header rule is not supported on current release */
+#define RXFL_RULE_HEADER_OUT_OF_RANGE (34) /* The header rule is out of range */
+#define RXFL_RULE_HEADER_COMBINATION_OPERATOR_OUT_OF_RANGE (33) /* Combination function Id is out of ramge */
+#define RXFL_RULE_HEADER_FIELD_ID_OUT_OF_RANGE (32) /* rule field Id is out of range */
+#define RXFL_UPDATE_NOT_SUPPORTED (31) /* Update not supported */
+#define RXFL_NO_FILTERS_ARE_DEFINED (24) /* No filters are defined in the system */
+#define RXFL_NUMBER_OF_FILTER_EXCEEDED (23) /* Number of max filters excceded */
+
+
+/******************************************************************************/
+/* Type declarations */
+/******************************************************************************/
+
+/*!
+
+
+ * \typedef SlrxFilterID_t
+ * Unique filter ID which is allocated by the system , negative number means error
+ */
+typedef _i8 SlrxFilterID_t;
+
+
+/*!
+ * \typedef SlrxFilterCompareMask_t
+ * The mask is used for the rule comparison function
+ */
+typedef _u8 SlrxFilterCompareMask_t;
+
+/*!
+ * \typedef SlrxFilterIdMask_t
+ * Representation of filters Id as a bit field
+ * The bit field is used to declare which filters are involved
+ * in operation. Number of filter can be up to 128 filters. i.e. 128 bits are needed.
+ * On the current release, up to 64 filters can be defined.
+ */
+typedef _u8 SlrxFilterIdMask_t[128/8];
+
+/*!
+ * \typedef SlrxFilterPrePreparedFilters_t
+ * Describes the supported software filter sets,
+ */
+typedef _u8 SlrxFilterPrePreparedFilters_t;
+#define SL_ARP_AUTO_REPLY_PRE_PREPARED_FILTERS (0)
+#define SL_MULTICASTSIPV4_DROP_PREPREPARED_FILTERS (1)
+#define SL_MULTICASTSIPV6_DROP_PREPREPARED_FILTERS (2)
+#define SL_MULTICASTSWIFI_DROP_PREPREPARED_FILTERS (3)
+
+
+
+/*!
+ * \typedef SlrxFilterPrePreparedFiltersMask_t
+ * Describes the supported software filter sets,
+ * each bit represents different software filter set
+ * The filter sets are defined at SlrxFilterPrePreparedFilters_t
+ */
+typedef _u8 SlrxFilterPrePreparedFiltersMask_t[SL_RX_FILTER_MAX_PRE_PREPARED_FILTERS_SETS/8];
+
+
+/*! \typedef SlrxFilterRegxPattern_t
+ * The struct contains the regular expression pattern which is used in case of payload rule.
+ * Not supported in the current release
+ */
+typedef struct SlrxFilterRegxPattern_t
+{
+ _u8 x[SL_RX_FILTER_LENGTH_OF_REGX_PATTERN_LENGTH];
+}SlrxFilterRegxPattern_t;
+
+
+/*! \typedef SlrxFilterAsciiArg_t
+ * The buffer is used to provide container for ASCII argument, which may be used in case of HEADER rule.
+ * example for ASCII argument can be : IP = 256.0.67.1
+ */
+typedef _u8 SlrxFilterAsciiArg_t;
+
+
+/*! \typedef SlrxFilterBinaryArg_t
+ * The buffer provides container for binary argument, which may be used in case of HEADER rule
+ */
+typedef _u8 SlrxFilterBinaryArg_t ;
+
+
+/*! \typedef SlrxFilterActionArg_t
+ * Provides container for the filter action argument.
+ * for example: in case action is to send automatic response , the argument is the template to be used for the automatic response.
+ *
+ *
+ */
+typedef _u8 SlrxFilterActionArg_t ;
+
+
+
+/*! \typedef SlrxFilterOffset_t
+ * The offset relative to the packet payload start location.
+ * Not supported on current release
+ */
+typedef _u32 SlrxFilterOffset_t;
+
+
+
+/*! \typedef SlrxFilterRuleType_t
+ * Enumerates the different filter types.
+ * On the current release only HEADER and COMBINATION are supported.
+ */
+typedef _u8 SlrxFilterRuleType_t;
+/* possible values for SlrxFilterRuleType_t */
+#define HEADER (0)
+#define COMBINATION (1)
+#define EXACT_PATTERN (2)
+#define LIKELIHOOD_PATTERN (3)
+#define ALWAYS_TRUE (4)
+#define NUM_OF_FILTER_TYPES (5)
+
+
+/*! \typedef SlrxFilterFlags_t
+ * Bit field which sets the behaviour of the RX filter
+ *
+ */
+
+#define RX_FILTER_BINARY (0x1)
+#define RX_FILTER_PERSISTENT (0x8)
+#define RX_FILTER_ENABLE (0x10)
+
+typedef union SlrxFilterFlags_t
+{
+
+ /* struct
+ { */
+ /*!
+ * The filter argument can be set as binary argument or ASCII arguments.
+ * When the bit is on the argument are binary.
+ */
+ /* _u8 Binary: 1; */
+ /*!
+ *
+ */
+ /* _u8 AutoSort : 1; */
+ /*!
+ *
+ */
+ /* _u8 AutoFaultDetect : 1; */
+ /*!
+ * When the bit is on it means the the node is enabled .
+ */
+ /* _u8 Enabled : 1; */
+ /* _u8 padding : 3; */
+ /*
+ };*/
+
+ _u8 IntRepresentation;
+
+}SlrxFilterFlags_t;
+
+/*! \typedef SlrxFilterCompareFunction_t
+ * Used as comparison function for the header type arguments
+ *
+ */
+typedef _u8 SlrxFilterCompareFunction_t;
+/* Possible values for SlrxFilterCompareFunction_t */
+#define COMPARE_FUNC_IN_BETWEEN (0)
+#define COMPARE_FUNC_EQUAL (1)
+#define COMPARE_FUNC_NOT_EQUAL_TO (2)
+#define COMPARE_FUNC_NOT_IN_BETWEEN (3)
+#define COMPARE_FUNC_NUM_OF_FILTER_COMPARE_FUNC (4)
+
+/*! \typedef SlrxFilterCompareFunction_t
+ * Used as comparison function for the header type arguments
+ *
+ */
+typedef _u8 SlrxTriggerCompareFunction_t;
+/* Possible values for SlrxTriggerCompareFunction_t */
+#define TRIGGER_COMPARE_FUNC_EQUAL (0)
+/* arg1 == protocolVal ,not supported in current release */
+#define TRIGGER_COMPARE_FUNC_NOT_EQUAL_TO (1)
+/* arg1 == protocolVal */
+#define TRIGGER_COMPARE_FUNC_SMALLER_THAN (2)
+/* arg1 == protocolVal */
+#define TRIGGER_COMPARE_FUNC_BIGGER_THAN (3)
+/* definition */
+#define TRIGGER_COMPARE_FUNC_NUM_OF_FILTER_COMPARE_FUNC (4)
+
+
+/*! \typedef SlrxFilterHdrField_t
+ * Provides list of possible header types which may be defined as part of the rule
+ *
+ */
+typedef _u8 SlrxFilterHdrField_t;
+/* Possible values for SlrxFilterHdrField_t */
+#define NULL_FIELD_ID_TYPE (0)
+/* 802.11 control\data\management */
+#define FRAME_TYPE_FIELD (1)
+/* 802.11 beacon\probe\.. */
+#define FRAME_SUBTYPE_FIELD (2)
+ /* 802.11 bssid type */
+#define BSSID_FIELD (3)
+ /* */
+#define MAC_SRC_ADDRESS_FIELD (4)
+ /* */
+#define MAC_DST_ADDRESS_FIELD (5)
+/* */
+#define FRAME_LENGTH_FIELD (6)
+/* */
+#define PROTOCOL_TYPE_FIELD (7)
+ /* */
+#define IP_VERSION_FIELD (8)
+ /* TCP / UDP */
+#define IP_PROTOCOL_FIELD (9)
+ /* */
+#define IPV4_SRC_ADRRESS_FIELD (10)
+/* */
+#define IPV4_DST_ADDRESS_FIELD (11)
+/* */
+#define IPV6_SRC_ADRRESS_FIELD (12)
+/* */
+#define IPV6_DST_ADDRESS_FIELD (13)
+ /* */
+#define SRC_PORT_FIELD (14)
+ /* */
+#define DST_PORT_FIELD (15)
+ /* Definition */
+#define NUM_OF_FIELD_NAME_FIELD (16)
+
+/*! \union SlrxFilterHeaderArg_t
+ * The structure holds the header ARGS which are used in case of HDR rule.
+ */
+/* -- 36 bytes */
+typedef union SlrxFilterHeaderArg_t
+{
+ /*----------------------------- Large size ---------------------------------*/
+ /*! buffer for binary arguments, number of argument may be up to SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ * example : IPV6 16 bytes, 39 characters
+ * ipv6 Ascii address: 2001:0db8:3c4d:0015:0000:0000:abcd:ef12
+ */
+
+ SlrxFilterBinaryArg_t RxFilterDB16BytesRuleArgs[SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][16 ]; /* Binary Values for comparition */
+ /*! buffer for ASCII arguments, number of argument may be up to SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ * example : IPV6 16 bytes, 39 characters
+ * ipv6 Ascii address: 2001:0db8:3c4d:0015:0000:0000:abcd:ef12
+ * Ascii format for ipV6 is not supported
+ */
+ /*----------------------------- Medium size ---------------------------------*/
+ /*! buffer for binary arguments, number of argument may be up to SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ * MAC address: 6 bytes, 17 chars
+ */
+ SlrxFilterBinaryArg_t RxFilterDB6BytesRuleArgs[SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][6]; /* Binary Values for comparition */
+ /*!
+ * ! buffer for ASCII arguments, number of argument may be up to SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ * IP address: 4 bytes, 15 chars
+ * 2 bytes are added for padding
+ */
+ SlrxFilterAsciiArg_t RxFilterDB18BytesAsciiRuleArgs[SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][18]; /* Ascii Values for comparison */
+ /*----------------------------- Small size ---------------------------------*/
+ /*! buffer for binary arguments, number of argument may be up to SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ * IP address: 4 bytes, 15 chars
+ * Port: 2 bytes, chars: 5 chars
+ */
+ SlrxFilterBinaryArg_t RxFilterDB4BytesRuleArgs[SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][4]; /* Binary Values for comparison */
+ /*! buffer for ASCII arguments, number of argument may be up to SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ * Port: 2 bytes, chars: 5 chars
+ */
+ SlrxFilterAsciiArg_t RxFilterDB5BytesRuleAsciiArgs[SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][5]; /* Ascii Values for comparison */
+ /*----------------------------- 1 byte size ---------------------------------*/
+ /*! buffer for binary arguments, number of argument may be up to SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS
+ */
+ SlrxFilterBinaryArg_t RxFilterDB1BytesRuleArgs[SL_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][1]; /* Binary Values for comparison */
+}SlrxFilterHeaderArg_t;
+
+
+
+/*! \typedef SlrxFilterRuleHeaderArgsAndMask_t
+ * Structure which defines the Header Args and mask
+ */
+/* -- 52 bytes */
+typedef struct SlrxFilterRuleHeaderArgsAndMask_t
+{
+ /*! Argument for the comparison function */
+ /* -- 36 byte */
+ SlrxFilterHeaderArg_t RuleHeaderArgs;
+
+ /*! the mask is used in order to enable partial comparison,
+ * Use the 0xFFFFFFFF in case you don't want to use mask
+ */
+ /* -- 16 bytes */
+ SlrxFilterCompareMask_t RuleHeaderArgsMask[16];
+
+}SlrxFilterRuleHeaderArgsAndMask_t;
+
+/*! \typedef SlrxFilterHeaderType_t
+ * Structure which defines the Header rule
+ * The header rule defines compare function on the protocol header
+ * For example destMacAddre is between ( 12:6::78:77, 12:6::78:90 )
+ *
+ */
+/* -- 56 byte */
+typedef struct SlrxFilterHeaderType_t
+{
+ /*! see :: SlrxFilterRuleHeaderArgsAndMask_t */
+ /* -- 52 bytes */
+ SlrxFilterRuleHeaderArgsAndMask_t RuleHeaderArgsAndMask;
+
+ /*! Packet HDR field which will be compared to the argument */
+ /* -- 1 byte */
+ SlrxFilterHdrField_t RuleHeaderfield;
+
+ /* -- 1 byte */
+ /*! type of the comparison function
+ * see :: SlrxFilterCompareFunction_t
+ */
+ SlrxFilterCompareFunction_t RuleCompareFunc;
+
+ /*! padding */
+ /* -- 2 bytes */
+ _u8 RulePadding[2];
+
+}SlrxFilterHeaderType_t;
+
+/*! \typedef SlrxFilterPayloadType_t
+ * Structure which defines payload rule.
+ * Not supported on current release.
+ */
+/* -- 40 byte */
+typedef struct SlrxFilterPayloadType_t
+{
+ /*! Not supported on current release */
+ /* -- 32 byte */
+ SlrxFilterRegxPattern_t RegxPattern;
+ /*! Not supported on current release */
+ /* -- 4 byte */
+ SlrxFilterOffset_t LowerOffset;
+ /*! Not supported on current release */
+ /* -- 4 byte */
+ SlrxFilterOffset_t UpperOffset;
+}SlrxFilterPayloadType_t;
+
+/*! \typedef SlrxFilterCombinationTypeOperator_t
+ * Enumerate the optional operators for the combination type
+ * filterID1 is located in the first arg , filterId2 is the second arg,see ::SlrxFilterCombinationType_t.CombinationFilterId
+ */
+typedef _u8 SlrxFilterCombinationTypeOperator_t;
+/* Possible values for SlrxFilterCombinationTypeOperator_t */
+/*! !filterID1 */
+#define COMBINED_FUNC_NOT (0)
+/*! filterID1 && filterID2 */
+#define COMBINED_FUNC_AND (1)
+/*! filterID1 && filterID2 */
+#define COMBINED_FUNC_OR (2)
+
+/*! \typedef SlrxFilterCombinationType_t
+ * Defines the structure which define the combination type filter
+ * The combined filter enable to make operation on one or two filter,
+ * for example !filterId1 or and(filterId2,filterId3).
+ *
+ */
+/* -- 4 byte */
+typedef struct SlrxFilterCombinationType_t
+{
+ /* ! combination operator */
+ /* -- 1 byte */
+ SlrxFilterCombinationTypeOperator_t CombinationTypeOperator;
+ /* ! filterID, may be one or two depends on the combination operator type */
+ /* -- 2 byte */
+ SlrxFilterID_t CombinationFilterId[SL_RX_FILTER_NUM_OF_COMBINATION_TYPE_ARGS];
+ /* ! Padding */
+ /* -- 1 byte */
+ _u8 Padding;
+}SlrxFilterCombinationType_t;
+
+
+/*! \typedef SlrxFilterRule_t
+ * Rule structure composed of behavioral flags and the filter rule definitions
+ *
+ */
+/* -- 56 byte */
+typedef union SlrxFilterRule_t
+{
+ /* ! Header type rule , see explanation on the ::SlrxFilterHeaderType_t structure */
+ /* -- 56 byte */
+ SlrxFilterHeaderType_t HeaderType;
+ /* ! Payload rule, not supported in current release */
+ /* -- 40 byte */
+ SlrxFilterPayloadType_t PayLoadHeaderType; /* future for exact pattern or like hood pattern */
+ /* ! Combined type rule , see explanation in ::SlrxFilterCombinationType_t structure */
+ /* -- 4 byte */
+ SlrxFilterCombinationType_t CombinationType;
+}SlrxFilterRule_t;
+
+/*! \typedef SlrxFilterTriggerRoles_t
+ * Bit field which represents the roleId possible values
+ * In the current release only Station/AP roles are supported.
+ */
+#define RX_FILTER_ROLE_AP (1)
+#define RX_FILTER_ROLE_STA (2)
+#define RX_FILTER_ROLE_PROMISCUOUS (4)
+#define RX_FILTER_ROLE_NULL (0)
+
+typedef union SlrxFilterTriggerRoles_t
+{
+/* struct */
+/* { */
+/* _u8 RoleAP :1; */
+/* _u8 RoleStation :1; */
+ /* The filter is activated only in Promiscuous mode */
+/* _u8 PromiscuousMode :1; */
+/* _u8 RoleReserved :5; */
+/* }; */
+ /* ! Bit fiels of the Filter role */
+ _u8 IntRepresentation;
+
+}SlrxFilterTriggerRoles_t;
+
+/*! \typedef SlrxFilterTriggerConnectionStates_t
+ * Bit field representing the possible values of the When section of the rule
+ *
+ */
+#define RX_FILTER_CONNECTION_STATE_STA_CONNECTED (1)
+#define RX_FILTER_CONNECTION_STATE_STA_NOT_CONNECTED (2)
+#define RX_FILTER_CONNECTION_STATE_STA_HAS_IP (4)
+#define RX_FILTER_CONNECTION_STATE_STA_HAS_NO_IP (8)
+
+typedef union SlrxFilterTriggerConnectionStates_t
+{
+/* struct */
+/* { */
+/* _u8 RoleStationWiFiConnected :1; */
+/* _u8 RoleStationWiFiDisconneted:1; */
+/* _u8 RoleStationWiFiHasIp:1; */
+/* _u8 RoleStationWiFiHasNoIp:1; */
+/* _u8 RoleStationWiFiSocketOpened:1; */
+/* _u8 RoleStationWiFiSocketclosed:1; */
+/* }; */
+/* */
+ /* ! */
+ _u8 IntRepresentation;
+
+}SlrxFilterTriggerConnectionStates_t;
+
+/*! \typedef SlrxFilterDBTriggerArg_t
+ * Provides container for entering the filter 'when' argument.
+ * The current release support 'When rules' which has no arguments.
+ * For example :
+ * When connect to specific AP -- the AP bssid is the argument.
+ *
+ */
+typedef _u32 SlrxFilterDBTriggerArg_t;
+
+
+
+/*! \typedef SlrxFilterCounterId_t
+ * the counter ID we have 4 counters
+ */
+typedef _u8 SlrxFilterCounterId_t;
+/* Possible values for SlrxFilterCounterId_t */
+#define NO_TRIGGER (0)
+#define RX_FILTER_COUNTER1 (1)
+#define RX_FILTER_COUNTER2 (2)
+#define RX_FILTER_COUNTER3 (3)
+#define RX_FILTER_COUNTER4 (4)
+#define RX_FILTER_COUNTER5 (5)
+#define RX_FILTER_COUNTER6 (6)
+#define RX_FILTER_COUNTER7 (7)
+#define RX_FILTER_COUNTER8 (8)
+#define MAX_RX_FILTER_COUNTER (9)
+
+
+
+/*! \typedef SlrxFilterActionArgs_t
+ * Possible value for filter action args
+ *
+ */
+
+typedef _u8 SlrxFilterActionArgs_t;
+/* Possible values for SlrxFilterActionArgs_t */
+#define ACTION_ARG_REG_1_4 (0)
+ /* ! Can be use as counter */
+#define ACTION_ARG_TEMPLATE (1)
+ /* ! Can be use as counter */
+#define ACTION_ARG_EVENT (2)
+
+/* ! GPIO number */
+#define ACTION_ARG_GPIO (4)
+/*!
+ * \def SL_RX_FILTER_NUM_OF_BYTES_FOR_ACTIONS_ARGS
+ *
+ */
+#define SL_RX_FILTER_NUM_OF_BYTES_FOR_ACTIONS_ARGS (5)
+
+
+
+
+/*! \typedef SlrxFilterTrigger_t
+ * The filter trigger, determine when the filter is triggered,
+ * The filter is triggered in the following condition :\n
+ * 1. The filter parent is triggered\n
+ * 2. The requested connection type exists, i.e. wlan_connect\n
+ * 3. The filter role is the same as the system role\n
+ *
+ */
+/* -- 12 byte */
+typedef struct SlrxFilterTrigger_t
+{
+ /*! The parent filter ID, this is the way to build filter tree. */
+ /* NULL value means tree root.
+ */
+ /* -- 1 byte */
+ SlrxFilterID_t ParentFilterID;
+ /* ! See ::SlrxFilterCounterId_t explanation */
+ /* -- 1 byte */
+ SlrxFilterCounterId_t Trigger;
+ /* ! See :: SlrxFilterTriggerConnectionStates_t */
+ /* -- 1 byte */
+ SlrxFilterTriggerConnectionStates_t TriggerArgConnectionState;
+ /* ! See ::SlrxFilterTriggerRoles_t */
+ /* -- 1 byte */
+ SlrxFilterTriggerRoles_t TriggerArgRoleStatus;
+ /* ! The Trigger arguments are in the same order as the Trigger bit field order. */
+ /* -- 4 byte */
+ SlrxFilterDBTriggerArg_t TriggerArg;
+ /** The compare function which will be operate for each bit that is turned on in the ::SlrxFilterTrigger_t.Trigger field,
+ * for example , in case the second bit in the Trigger function is on the second function in the list will be executed.
+ *
+ */
+ /* -- 1 byte */
+ SlrxTriggerCompareFunction_t TriggerCompareFunction;
+
+ /* ! padding */
+ /* -- 3 byte */
+ _u8 Padding[3];
+} SlrxFilterTrigger_t;
+
+/*! \typedef SlrxFilterActionType_t
+ * The actions are executed only if the filter is matched,\n
+ * In case of false match the packet is transfered to the HOST. \n
+ * The action is composed of bit field structure,
+ * up to 2 actions can be defined per filter.
+ *
+ */
+#define RX_FILTER_ACTION_NULL (0x0)
+#define RX_FILTER_ACTION_DROP (0x1)
+#define RX_FILTER_ACTION_GPIO (0x2)
+#define RX_FILTER_ACTION_ON_REG_INCREASE (0x4)
+#define RX_FILTER_ACTION_ON_REG_DECREASE (0x8)
+#define RX_FILTER_ACTION_ON_REG_RESET (0x10)
+#define RX_FILTER_ACTION_SEND_TEMPLATE (0x20) /* unsupported */
+#define RX_FILTER_ACTION_EVENT_TO_HOST (0x40) /* unsupported */
+
+typedef union SlrxFilterActionType_t
+{
+/* struct */
+/* { */
+ /* ! No action to execute the packet is dropped,drop is always on leaf. */
+ /* ! If not dropped ,The packet is passed to the next filter or in case it is the last filter to the host */
+/* _u8 ActionDrop : 1; */
+ /* ! Not Supported in the current release */
+/* _u8 ActionGpio : 1; */
+ /*! action can increase counter registers.
+ * 1 = Increase
+ * 2 = decrease
+ * 3 = reset
+ */
+/* _u8 ActionOnREGIncrease : 1; */
+/* _u8 ActionOnREGDecrease : 1; */
+/* _u8 ActionOnREGReset : 1; */
+
+ /* ! Not Supported in the current release */
+/* _u8 ActionSendTemplate : 1; */
+ /* ! Not Supported in the current release */
+/* _u8 ActionEventToHost: 1; */
+/* _u8 padding: 1; */
+/* }; */
+
+ _u8 IntRepresentation;
+
+}SlrxFilterActionType_t;
+
+/*! \typedef SlrxFilterAction_t
+ * Several actions can be defined,\n
+ * The action is executed in case the filter rule is matched.
+ */
+/* -- 8 byte */
+typedef struct SlrxFilterAction_t
+{
+ /* -- 1 byte */
+ /* ! Determine which actions are supported */
+ SlrxFilterActionType_t ActionType;
+ /* ! Buffer for the action arguments */
+ /**
+ * location 0 - The counter to increase
+ * In case the action is of type "increase" the arg will contain the counter number,
+ * The counter number values are as in ::SlrxFilterCounterId_t.\n
+ * location 1 - The template arg.\n
+ * location 2 - The event arg.\n
+ *
+ */
+ /* -- 5 byte */
+ SlrxFilterActionArg_t ActionArg[SL_RX_FILTER_NUM_OF_BYTES_FOR_ACTIONS_ARGS];
+
+ /* ! Padding */
+ /* - 2 Bytes */
+ _u8 Padding[2];
+
+} SlrxFilterAction_t;
+
+
+/*! \struct _WlanRxFilterOperationCommandBuff_t
+ * The structure is used for the interface HOST NWP.\n
+ * The supported operation : \n
+ * ::ENABLE_DISABLE_RX_FILTER,\n
+ * ::REMOVE_RX_FILTER,\n
+ *
+ */
+/* 20 bytes */
+typedef struct _WlanRxFilterOperationCommandBuff_t
+{
+ /* -- 16 bytes */
+ SlrxFilterIdMask_t FilterIdMask;
+ /* 4 bytes */
+ _u8 Padding[4];
+}_WlanRxFilterOperationCommandBuff_t;
+
+
+
+/* -- 56 bytes */
+typedef struct _WlanRxFilterUpdateArgsCommandBuff_t
+{
+ /* -- 1 bytes */
+ _u8 FilterId;
+
+ /* -- 1 bytes */
+ /* ! the args representation */
+ _u8 BinaryRepresentation;
+
+ /* -- 52 byte */
+ SlrxFilterRuleHeaderArgsAndMask_t FilterRuleHeaderArgsAndMask;
+
+ /* -- 2 bytes */
+ _u8 Padding[2];
+}_WlanRxFilterUpdateArgsCommandBuff_t;
+
+
+/*! \typedef _WlanRxFilterRetrieveEnableStatusCommandResponseBuff_t
+ * The structure is used for the interface HOST NWP.\n
+ *
+ */
+/* -- 16 bytes */
+typedef struct _WlanRxFilterRetrieveEnableStatusCommandResponseBuff_t
+{
+
+ /* ! the filter set bit map */
+ /* -- 16 bytes */
+ SlrxFilterIdMask_t FilterIdMask;
+
+}_WlanRxFilterRetrieveEnableStatusCommandResponseBuff_t;
+
+
+/*! \struct _WlanRxFilterPrePreparedFiltersCommandBuff_t
+ * The function enables to perform operations on pre-prepared filters
+ *
+ */
+typedef struct _WlanRxFilterPrePreparedFiltersCommandBuff_t
+{
+ /* ! the filter set bit map */
+ /* -- 4 bytes */
+ SlrxFilterPrePreparedFiltersMask_t FilterPrePreparedFiltersMask;
+
+}_WlanRxFilterPrePreparedFiltersCommandBuff_t;
+
+
+/*! \typedef sl_protocol_WlanRxFilterPrePreparedFiltersCommandResponseBuff_t
+ *
+ */
+/*-- 4 bytes */
+typedef struct _WlanRxFilterPrePreparedFiltersCommandResponseBuff_t
+{
+ /* -- 4 bytes */
+ /* ! the filter set bit map */
+ SlrxFilterPrePreparedFiltersMask_t FilterPrePreparedFiltersMask;
+
+}_WlanRxFilterPrePreparedFiltersCommandResponseBuff_t;
+
+
+
+typedef _u8 SLrxFilterOperation_t;
+#define SL_ENABLE_DISABLE_RX_FILTER (0)
+#define SL_REMOVE_RX_FILTER (1)
+#define SL_STORE_RX_FILTERS (2)
+#define SL_UPDATE_RX_FILTER_ARGS (3)
+#define SL_FILTER_RETRIEVE_ENABLE_STATE (4)
+#define SL_FILTER_PRE_PREPARED_RETRIEVE_CREATE_REMOVE_STATE (5)
+#define SL_FILTER_PRE_PREPARED_SET_CREATE_REMOVE_STATE (6)
+
+
+/* Bit manipulation for 8 bit */
+#define ISBITSET8(x,i) ((x[i>>3] & (0x80>>(i&7)))!=0) /* < Is bit set, 8 bit unsigned numbers = x , location = i */
+#define SETBIT8(x,i) x[i>>3]|=(0x80>>(i&7)); /* < Set bit,8 bit unsigned numbers = x , location = i */
+#define CLEARBIT8(x,i) x[i>>3]&=(0x80>>(i&7))^0xFF; /* < Clear bit,8 bit unsigned numbers = x , location = i */
+
+
+/*********************************************************************************************/
+/* Function prototypes */
+/*********************************************************************************************/
+
+/*!
+
+ \addtogroup wlan
+ @{
+
+*/
+
+
+/*!
+ \brief Adds new filter rule to the system
+
+ \param[in] RuleType The rule type
+ \param[in] FilterFlags Flags which set the type of header rule Args and sets the persistent flag
+ \param[in] pRule Determine the filter rule logic
+ \param[in] pTrigger Determine when the rule is triggered also sets rule parent.
+ \param[in] pAction Sets the action to be executed in case the match functions pass
+ \param[out] pFilterId The filterId which was created
+
+ \return On success, zero is returned. Otherwise error code is returned
+ */
+#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd)
+SlrxFilterID_t sl_WlanRxFilterAdd( SlrxFilterRuleType_t RuleType,
+ SlrxFilterFlags_t FilterFlags,
+ const SlrxFilterRule_t* const Rule,
+ const SlrxFilterTrigger_t* const Trigger,
+ const SlrxFilterAction_t* const Action,
+ SlrxFilterID_t* pFilterId);
+
+#endif
+
+
+
+
+
+/*!
+ \brief Sets parameters to Rx filters
+
+ \param[in] RxFilterOperation
+ possible operations :
+ - SL_ENABLE_DISABLE_RX_FILTER - Enables\disables filter in a filter list
+ - SL_REMOVE_RX_FILTER - Removes filter from memory ( to remove from flash call SL_STORE_RX_FILTERS after this command)
+ - SL_STORE_RX_FILTERS - Save the filters for persistent
+ - SL_UPDATE_RX_FILTER_ARGS - Update the arguments of existing filter
+ - SL_FILTER_PRE_PREPARED_SET_CREATE_REMOVE_STATE - Change the default creation of the pre-prepared filters
+
+ \param[in] pInputBuffer options:
+ The buffer input is _WlanRxFilterOperationCommandBuff_t:
+ - SL_ENABLE_DISABLE_RX_FILTER
+ - SL_REMOVE_RX_FILTER
+ - SL_STORE_RX_FILTERS
+ The buffer input is _WlanRxFilterUpdateArgsCommandBuff_t:
+ - SL_UPDATE_RX_FILTER_ARGS
+ The buffer input is _WlanRxFilterPrePreparedFiltersCommandBuff_t:
+ - SL_FILTER_PRE_PREPARED_SET_CREATE_REMOVE_STATE
+
+ \param[in] InputbufferLength The length in byte of the input buffer
+
+ \return On success, zero is returned. Otherwise error code is returned
+ */
+
+#if _SL_INCLUDE_FUNC(sl_WlanRxFilterSet)
+_i16 sl_WlanRxFilterSet( const SLrxFilterOperation_t RxFilterOperation,
+ const _u8* const pInputBuffer,
+ _u16 InputbufferLength);
+#endif
+
+/*!
+ \brief Gets parameters of Rx filters
+
+ \param[in] RxFilterOperation
+ possible operations :
+ - SL_FILTER_RETRIEVE_ENABLE_STATE - Retrieves the enable disable status
+ - SL_FILTER_PRE_PREPARED_RETRIEVE_CREATE_REMOVE_STATE - Retrieves the pre-prepared filters creation status
+
+ \param[in] pOutputBuffer
+ The buffer input is _WlanRxFilterRetrieveEnableStatusCommandResponseBuff_t:
+ - SL_FILTER_RETRIEVE_ENABLE_STATE
+ The buffer input is _WlanRxFilterPrePreparedFiltersCommandResponseBuff_t:
+ - SL_FILTER_PRE_PREPARED_RETRIEVE_CREATE_REMOVE_STATE
+
+ \param[in] OutputbufferLength The length in byte of the output buffer
+
+ \return On success, zero is returned. Otherwise error code is returned
+*/
+
+#if _SL_INCLUDE_FUNC(sl_WlanRxFilterGet)
+_i16 sl_WlanRxFilterGet(const SLrxFilterOperation_t RxFilterOperation,
+ _u8* pOutputBuffer,
+ _u16 OutputbufferLength);
+#endif
+
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RX_FILTERS_PREPROCESSOR_CLI_IF_H_ */
+
+
diff --git a/cc3200/simplelink/oslib/osi.h b/cc3200/simplelink/oslib/osi.h
new file mode 100644
index 0000000000..637f92eee4
--- /dev/null
+++ b/cc3200/simplelink/oslib/osi.h
@@ -0,0 +1,580 @@
+//*****************************************************************************
+// osi.h
+//
+// MACRO and Function prototypes for TI-RTOS and Free-RTOS API calls
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list zof conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+#ifndef __OSI_H__
+#define __OSI_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OSI_WAIT_FOREVER (0xFFFFFFFF)
+
+#define OSI_NO_WAIT (0)
+
+typedef enum
+{
+ OSI_OK = 0,
+ OSI_FAILURE = -1,
+ OSI_OPERATION_FAILED = -2,
+ OSI_ABORTED = -3,
+ OSI_INVALID_PARAMS = -4,
+ OSI_MEMORY_ALLOCATION_FAILURE = -5,
+ OSI_TIMEOUT = -6,
+ OSI_EVENTS_IN_USE = -7,
+ OSI_EVENT_OPEARTION_FAILURE = -8
+}OsiReturnVal_e;
+
+
+//#define ENTER_CRITICAL_SECTION osi_EnterCritical()
+//#define EXIT_CRITICAL_SECTION osi_ExitCritical()
+
+typedef void* OsiMsgQ_t;
+
+ /*!
+ \brief type definition for a time value
+
+ \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc.
+*/
+//typedef unsigned int OsiTime_t;
+typedef unsigned int OsiTime_t;
+/*!
+ \brief type definition for a sync object container
+
+ Sync object is object used to synchronize between two threads or thread and interrupt handler.
+ One thread is waiting on the object and the other thread send a signal, which then
+ release the waiting thread.
+ The signal must be able to be sent from interrupt context.
+ This object is generally implemented by binary semaphore or events.
+
+ \note On each porting or platform the type could be whatever is needed - integer, structure etc.
+*/
+//typedef unsigned int OsiSyncObj_t;
+typedef void * OsiSyncObj_t;
+
+/*!
+ \brief type definition for a locking object container
+
+ Locking object are used to protect a resource from mutual accesses of two or more threads.
+ The locking object should support re-entrant locks by a signal thread.
+ This object is generally implemented by mutex semaphore
+
+ \note On each porting or platform the type could be whatever is needed - integer, structure etc.
+*/
+//typedef unsigned int OsiLockObj_t;
+typedef void * OsiLockObj_t;
+
+/*!
+ \brief type definition for a spawn entry callback
+
+ the spawn mechanism enable to run a function on different context.
+ This mechanism allow to transfer the execution context from interrupt context to thread context
+ or changing the context from an unknown user thread to general context.
+ The implementation of the spawn mechanism depends on the user's system requirements and could varies
+ from implementation of serialized execution using single thread to creating thread per call
+
+ \note The stack size of the execution thread must be at least of TBD bytes!
+*/
+typedef void (*P_OSI_SPAWN_ENTRY)(void* pValue);
+
+typedef void (*P_OSI_EVENT_HANDLER)(void* pValue);
+
+typedef void (*P_OSI_TASK_ENTRY)(void* pValue);
+
+typedef void (*P_OSI_INTR_ENTRY)(void);
+
+typedef void* OsiTaskHandle;
+
+/*!
+ \brief This function registers an interrupt in NVIC table
+
+ The sync object is used for synchronization between different thread or ISR and
+ a thread.
+
+ \param iIntrNum - Interrupt number to register
+ \param pEntry - Pointer to the interrupt handler
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_InterruptRegister(int iIntrNum,P_OSI_INTR_ENTRY pEntry,unsigned char ucPriority);
+
+/*!
+ \brief This function De-registers an interrupt in NVIC table
+
+ \param iIntrNum - Interrupt number to register
+ \param pEntry - Pointer to the interrupt handler
+
+ \return upon successful creation the function should return Positive number
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+void osi_InterruptDeRegister(int iIntrNum);
+
+
+/*!
+ \brief This function creates a sync object
+
+ The sync object is used for synchronization between different thread or ISR and
+ a thread.
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjCreate(OsiSyncObj_t* pSyncObj);
+
+
+/*!
+ \brief This function deletes a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjDelete(OsiSyncObj_t* pSyncObj);
+
+/*!
+ \brief This function generates a sync signal for the object.
+
+ All suspended threads waiting on this sync object are resumed
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signalling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function could be called from ISR context
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjSignal(OsiSyncObj_t* pSyncObj);
+
+/*!
+ \brief This function generates a sync signal for the object.
+ from ISR context.
+
+ All suspended threads waiting on this sync object are resumed
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signalling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function is called from ISR context
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjSignalFromISR(OsiSyncObj_t* pSyncObj);
+
+/*!
+ \brief This function waits for a sync signal of the specific sync object
+
+ \param pSyncObj - pointer to the sync object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the sync signal
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+ \return upon successful reception of the signal within the timeout window return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjWait(OsiSyncObj_t* pSyncObj , OsiTime_t Timeout);
+
+/*!
+ \brief This function clears a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful clearing the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjClear(OsiSyncObj_t* pSyncObj);
+
+/*!
+ \brief This function creates a locking object.
+
+ The locking object is used for protecting a shared resources between different
+ threads.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjCreate(OsiLockObj_t* pLockObj);
+
+/*!
+ \brief This function deletes a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjDelete(OsiLockObj_t* pLockObj);
+
+/*!
+ \brief This function locks a locking object.
+
+ All other threads that call this function before this thread calls
+ the osi_LockObjUnlock would be suspended
+
+ \param pLockObj - pointer to the locking object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the locking object
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+
+ \return upon successful reception of the locking object the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjLock(OsiLockObj_t* pLockObj , OsiTime_t Timeout);
+
+/*!
+ \brief This function unlock a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful unlocking the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjUnlock(OsiLockObj_t* pLockObj);
+
+
+/*!
+ \brief This function call the pEntry callback from a different context
+
+ \param pEntry - pointer to the entry callback function
+
+ \param pValue - pointer to any type of memory structure that would be
+ passed to pEntry callback from the execution thread.
+
+ \param flags - execution flags - reserved for future usage
+
+ \return upon successful registration of the spawn the function should return 0
+ (the function is not blocked till the end of the execution of the function
+ and could be returned before the execution is actually completed)
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+/*!
+ \brief This function creates a Task.
+
+ Creates a new Task and add it to the last of tasks that are ready to run
+
+ \param pEntry - pointer to the Task Function
+ \param pcName - Task Name String
+ \param usStackDepth - Stack Size Stack Size in 32-bit long words
+ \param pvParameters - pointer to structure to be passed to the Task Function
+ \param uxPriority - Task Priority
+
+ \return upon successful unlocking the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_TaskCreate(P_OSI_TASK_ENTRY pEntry,const signed char * const pcName,unsigned short usStackDepth,void *pvParameters,unsigned long uxPriority,OsiTaskHandle *pTaskHandle);
+
+/*!
+ \brief This function Deletes a Task.
+
+ Deletes a Task and remove it from list of running task
+
+ \param pTaskHandle - Task Handle
+
+ \note
+ \warning
+*/
+void osi_TaskDelete(OsiTaskHandle* pTaskHandle);
+
+/*!
+ \brief This function call the pEntry callback from a different context
+
+ \param pEntry - pointer to the entry callback function
+
+ \param pValue - pointer to any type of memory structure that would be
+ passed to pEntry callback from the execution thread.
+
+ \param flags - execution flags - reserved for future usage
+
+ \return upon successful registration of the spawn the function should return 0
+ (the function is not blocked till the end of the execution of the function
+ and could be returned before the execution is actually completed)
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_Spawn(P_OSI_SPAWN_ENTRY pEntry , void* pValue , unsigned long flags);
+
+
+/*******************************************************************************
+
+This function creates a message queue that is typically used for inter thread
+communication.
+
+Parameters:
+
+ pMsgQ - pointer to the message queue control block
+ pMsgQName - pointer to the name of the message queue
+ MsgSize - the size of the message.
+
+ NOTICE: THE MESSGAE SIZE MUST BE SMALLER THAN 16
+
+ MaxMsgs - maximum number of messages.
+
+Please note that this function allocates the entire memory required
+for the maximum number of messages (MsgSize * MaxMsgs).
+
+********************************************************************************/
+OsiReturnVal_e osi_MsgQCreate(OsiMsgQ_t* pMsgQ ,
+ char* pMsgQName,
+ unsigned long MsgSize,
+ unsigned long MaxMsgs);
+
+/*******************************************************************************
+
+This function deletes a specific message queue.
+All threads suspended waiting for a message from this queue are resumed with
+an error return value.
+
+Parameters:
+
+ pMsgQ - pointer to the message queue control block
+
+********************************************************************************/
+OsiReturnVal_e osi_MsgQDelete(OsiMsgQ_t* pMsgQ);
+
+
+/*******************************************************************************
+
+This function writes a message to a specific message queue.
+
+Notice that the message is copied to the queue from the memory area specified
+by pMsg pointer.
+
+--------------------------------------------------------------------------------
+THIS FUNCTION COULD BE CALLED FROM ISR AS LONG AS THE TIMEOUT PARAMETER IS
+SET TO "OSI_NO_WAIT"
+--------------------------------------------------------------------------------
+
+Parameters:
+
+ pMsgQ - pointer to the message queue control block
+ pMsg - pointer to the message
+ Timeout - numeric value specifies the maximum number of mSec to stay
+ suspended while waiting for available space for the message
+
+********************************************************************************/
+OsiReturnVal_e osi_MsgQWrite(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout);
+
+
+/*******************************************************************************
+
+This function retrieves a message from the specified message queue. The
+retrieved message is copied from the queue into the memory area specified by
+the pMsg pointer
+
+Parameters:
+
+ pMsgQ - pointer to the message queue control block
+ pMsg - pointer that specify the location where to copy the message
+ Timeout - numeric value specifies the maximum number of mSec to stay
+ suspended while waiting for a message to be available
+
+********************************************************************************/
+OsiReturnVal_e osi_MsgQRead(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout);
+
+/*!
+ \brief This function starts the OS Scheduler
+ \param - void
+ \return - void
+ \note
+ \warning
+*/
+void osi_start();
+
+/*!
+ \brief Allocates Memory on Heap
+ \param Size - Size of the Buffer to be allocated
+ \sa
+ \note
+ \warning
+*/
+void * mem_Malloc(unsigned long Size);
+
+
+/*!
+ \brief Deallocates Memory
+ \param pMem - Pointer to the Buffer to be freed
+ \return void
+ \sa
+ \note
+ \warning
+*/
+void mem_Free(void *pMem);
+
+
+/*!
+ \brief Set Memory
+ \param pBuf - Pointer to the Buffer
+ \param Val - Value to be set
+ \param Size - Size of the memory to be set
+ \sa
+ \note
+ \warning
+*/
+void mem_set(void *pBuf,int Val,size_t Size);
+
+/*!
+ \brief Copy Memory
+ \param pDst - Pointer to the Destination Buffer
+ \param pSrc - Pointer to the Source Buffer
+ \param Size - Size of the memory to be copied
+ \return void
+ \note
+ \warning
+*/
+void mem_copy(void *pDst, void *pSrc,size_t Size);
+
+/*!
+ \brief Enter Critical Section
+ \sa
+ \note
+ \warning
+*/
+void osi_EnterCritical(void);
+
+/*!
+ \brief Exit Critical Section
+ \sa
+ \note
+ \warning
+*/
+void osi_ExitCritical(void);
+
+/*!
+ \brief This function used to save the os context before sleep
+ \param void
+ \return void
+ \note
+ \warning
+*/
+void osi_ContextSave();
+/*!
+ \brief This function used to retrieve the context after sleep
+ \param void
+ \return void
+ \note
+ \warning
+*/
+void osi_ContextRestore();
+
+/*!
+ \brief This function used to suspend the task for the specified number of milli secs
+ \param MilliSecs - Time in millisecs to suspend the task
+ \return void
+ \note
+ \warning
+*/
+void osi_Sleep(unsigned int MilliSecs);
+
+/*!
+ \brief This function used to disable the tasks
+ \param - void
+ \return - Key with the suspended tasks
+ \note
+ \warning
+*/
+unsigned long osi_TaskDisable(void);
+
+/*!
+ \brief This function used to enable all tasks
+ \param unsigned long
+ \return - void
+ \note
+ \warning
+*/
+void osi_TaskEnable(unsigned long);
+/*!
+ \brief structure definition for simple link spawn message
+
+ \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc.
+*/
+
+typedef struct
+{
+ P_OSI_SPAWN_ENTRY pEntry;
+ void* pValue;
+}tSimpleLinkSpawnMsg;
+
+/* The queue used to send message to simple link spawn task. */
+extern void* xSimpleLinkSpawnQueue;
+
+/* API for SL Task*/
+OsiReturnVal_e VStartSimpleLinkSpawnTask(unsigned long uxPriority);
+void VDeleteSimpleLinkSpawnTask( void );
+
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif
diff --git a/cc3200/simplelink/oslib/osi_freertos.c b/cc3200/simplelink/oslib/osi_freertos.c
new file mode 100644
index 0000000000..e8b617f846
--- /dev/null
+++ b/cc3200/simplelink/oslib/osi_freertos.c
@@ -0,0 +1,839 @@
+//*****************************************************************************
+// osi_freertos.c
+//
+// Interface APIs for free-rtos function calls
+//
+// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+//
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//*****************************************************************************
+
+
+#include
+#include
+#include
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#include "portmacro.h"
+#include
+
+#include "rom.h"
+#include "rom_map.h"
+#include "inc/hw_types.h"
+#include "interrupt.h"
+
+portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
+//Local function definition
+static void vSimpleLinkSpawnTask( void *pvParameters );
+//Queue Handler
+QueueHandle_t xSimpleLinkSpawnQueue = NULL;
+TaskHandle_t xSimpleLinkSpawnTaskHndl = NULL;
+// Queue size
+#define slQUEUE_SIZE ( 3 )
+
+
+/*!
+ \brief This function registers an interrupt in NVIC table
+
+ The sync object is used for synchronization between different thread or ISR and
+ a thread.
+
+ \param iIntrNum - Interrupt number to register
+ \param pEntry - Pointer to the interrupt handler
+ \param ucPriority - priority of the interrupt
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_InterruptRegister(int iIntrNum,P_OSI_INTR_ENTRY pEntry,unsigned char ucPriority)
+{
+ MAP_IntRegister(iIntrNum,(void(*)(void))pEntry);
+ MAP_IntPrioritySet(iIntrNum, ucPriority);
+ MAP_IntEnable(iIntrNum);
+ return OSI_OK;
+}
+
+/*!
+ \brief This function De registers an interrupt in NVIC table
+
+
+ \param iIntrNum - Interrupt number to De register
+
+ \return none
+ \note
+ \warning
+*/
+
+void osi_InterruptDeRegister(int iIntrNum)
+{
+ MAP_IntDisable(iIntrNum);
+ MAP_IntUnregister(iIntrNum);
+}
+
+/*!
+ \brief This function creates a sync object
+
+ The sync object is used for synchronization between different thread or ISR and
+ a thread.
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjCreate(OsiSyncObj_t* pSyncObj)
+{
+ //Check for NULL
+ if(NULL == pSyncObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ SemaphoreHandle_t *pl_SyncObj = (SemaphoreHandle_t *)pSyncObj;
+
+ *pl_SyncObj = xSemaphoreCreateBinary();
+
+ if((SemaphoreHandle_t)(*pSyncObj) != NULL)
+ {
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+
+/*!
+ \brief This function deletes a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjDelete(OsiSyncObj_t* pSyncObj)
+{
+ //Check for NULL
+ if(NULL == pSyncObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ vSemaphoreDelete(*pSyncObj );
+ return OSI_OK;
+}
+
+/*!
+ \brief This function generates a sync signal for the object.
+
+ All suspended threads waiting on this sync object are resumed
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signaling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function could be called from ISR context
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjSignal(OsiSyncObj_t* pSyncObj)
+{
+ //Check for NULL
+ if(NULL == pSyncObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+
+ if(pdTRUE != xSemaphoreGive( *pSyncObj ))
+ {
+ //In case of Semaphore, you are expected to get this if multiple sem
+ // give is called before sem take
+ return OSI_OK;
+ }
+
+ return OSI_OK;
+}
+/*!
+ \brief This function generates a sync signal for the object
+ from ISR context.
+
+ All suspended threads waiting on this sync object are resumed
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signalling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function is called from ISR context
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjSignalFromISR(OsiSyncObj_t* pSyncObj)
+{
+ //Check for NULL
+ if(NULL == pSyncObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ xHigherPriorityTaskWoken = pdFALSE;
+ if(pdTRUE == xSemaphoreGiveFromISR( *pSyncObj, &xHigherPriorityTaskWoken ))
+ {
+ if( xHigherPriorityTaskWoken )
+ {
+ taskYIELD ();
+ }
+ return OSI_OK;
+ }
+ else
+ {
+ //In case of Semaphore, you are expected to get this if multiple sem
+ // give is called before sem take
+ return OSI_OK;
+ }
+}
+
+/*!
+ \brief This function waits for a sync signal of the specific sync object
+
+ \param pSyncObj - pointer to the sync object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the sync signal
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+ \return upon successful reception of the signal within the timeout window return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjWait(OsiSyncObj_t* pSyncObj , OsiTime_t Timeout)
+{
+ //Check for NULL
+ if(NULL == pSyncObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ if(pdTRUE == xSemaphoreTake( (SemaphoreHandle_t)*pSyncObj, ( TickType_t )(Timeout/portTICK_PERIOD_MS) ))
+ {
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+
+/*!
+ \brief This function clears a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful clearing the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_SyncObjClear(OsiSyncObj_t* pSyncObj)
+{
+ //Check for NULL
+ if(NULL == pSyncObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+
+ if (OSI_OK == osi_SyncObjWait(pSyncObj,0) )
+ {
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+
+/*!
+ \brief This function creates a locking object.
+
+ The locking object is used for protecting a shared resources between different
+ threads.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjCreate(OsiLockObj_t* pLockObj)
+{
+ //Check for NULL
+ if(NULL == pLockObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ *pLockObj = (OsiLockObj_t)xSemaphoreCreateMutex();
+ if(pLockObj != NULL)
+ {
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+
+/*!
+ \brief This function creates a Task.
+
+ Creates a new Task and add it to the last of tasks that are ready to run
+
+ \param pEntry - pointer to the Task Function
+ \param pcName - Task Name String
+ \param usStackDepth - Stack Size in bytes
+ \param pvParameters - pointer to structure to be passed to the Task Function
+ \param uxPriority - Task Priority
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_TaskCreate(P_OSI_TASK_ENTRY pEntry,const signed char * const pcName,
+ unsigned short usStackDepth, void *pvParameters,
+ unsigned long uxPriority,OsiTaskHandle* pTaskHandle)
+{
+ if(pdPASS == xTaskCreate( pEntry, (char const*)pcName,
+ (usStackDepth/(sizeof( portSTACK_TYPE ))),
+ pvParameters,(unsigned portBASE_TYPE)uxPriority,
+ (TaskHandle_t*)pTaskHandle ))
+ {
+ return OSI_OK;
+ }
+
+ return OSI_OPERATION_FAILED;
+}
+
+
+/*!
+ \brief This function Deletes a Task.
+
+ Deletes a Task and remove it from list of running task
+
+ \param pTaskHandle - Task Handle
+
+ \note
+ \warning
+*/
+void osi_TaskDelete(OsiTaskHandle* pTaskHandle)
+{
+ vTaskDelete((TaskHandle_t)*pTaskHandle);
+}
+
+
+
+/*!
+ \brief This function deletes a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjDelete(OsiLockObj_t* pLockObj)
+{
+ vSemaphoreDelete((SemaphoreHandle_t)*pLockObj );
+ return OSI_OK;
+}
+
+/*!
+ \brief This function locks a locking object.
+
+ All other threads that call this function before this thread calls
+ the osi_LockObjUnlock would be suspended
+
+ \param pLockObj - pointer to the locking object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the locking object
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+
+ \return upon successful reception of the locking object the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjLock(OsiLockObj_t* pLockObj , OsiTime_t Timeout)
+{
+ //Check for NULL
+ if(NULL == pLockObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ //Take Semaphore
+ if(pdTRUE == xSemaphoreTake( *pLockObj, ( TickType_t ) (Timeout/portTICK_PERIOD_MS) ))
+ {
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+
+/*!
+ \brief This function unlock a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful unlocking the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_LockObjUnlock(OsiLockObj_t* pLockObj)
+{
+ //Check for NULL
+ if(NULL == pLockObj)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ //Release Semaphore
+ if(pdTRUE == xSemaphoreGive( *pLockObj ))
+ {
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+
+
+/*!
+ \brief This function call the pEntry callback from a different context
+
+ \param pEntry - pointer to the entry callback function
+
+ \param pValue - pointer to any type of memory structure that would be
+ passed to pEntry callback from the execution thread.
+
+ \param flags - execution flags - reserved for future usage
+
+ \return upon successful registration of the spawn the function should return 0
+ (the function is not blocked till the end of the execution of the function
+ and could be returned before the execution is actually completed)
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+
+OsiReturnVal_e osi_Spawn(P_OSI_SPAWN_ENTRY pEntry , void* pValue , unsigned long flags)
+{
+
+ tSimpleLinkSpawnMsg Msg;
+ Msg.pEntry = pEntry;
+ Msg.pValue = pValue;
+ xHigherPriorityTaskWoken = pdFALSE;
+
+ if(pdTRUE == xQueueSendFromISR( xSimpleLinkSpawnQueue, &Msg, &xHigherPriorityTaskWoken ))
+ {
+ if( xHigherPriorityTaskWoken )
+ {
+ taskYIELD ();
+ }
+
+ return OSI_OK;
+ }
+ return OSI_OPERATION_FAILED;
+}
+
+
+/*!
+ \brief This is the simplelink spawn task to call SL callback from a different context
+
+ \param pvParameters - pointer to the task parameter
+
+ \return void
+ \note
+ \warning
+*/
+void vSimpleLinkSpawnTask(void *pvParameters)
+{
+ tSimpleLinkSpawnMsg Msg;
+ portBASE_TYPE ret=pdFAIL;
+
+ for(;;)
+ {
+ ret = xQueueReceive( xSimpleLinkSpawnQueue, &Msg, portMAX_DELAY );
+ if(ret == pdPASS)
+ {
+ Msg.pEntry(Msg.pValue);
+ }
+ }
+}
+
+/*!
+ \brief This is the API to create SL spawn task and create the SL queue
+
+ \param uxPriority - task priority
+
+ \return void
+ \note
+ \warning
+*/
+OsiReturnVal_e VStartSimpleLinkSpawnTask(unsigned portBASE_TYPE uxPriority)
+{
+ xSimpleLinkSpawnQueue = xQueueCreate( slQUEUE_SIZE, sizeof( tSimpleLinkSpawnMsg ) );
+ if(0 == xSimpleLinkSpawnQueue)
+ {
+ return OSI_OPERATION_FAILED;
+ }
+ if(pdPASS == xTaskCreate( vSimpleLinkSpawnTask, ( portCHAR * ) "SLSPAWN",\
+ 768 / sizeof(portSTACK_TYPE), NULL, uxPriority, &xSimpleLinkSpawnTaskHndl ))
+ {
+ return OSI_OK;
+ }
+
+ return OSI_OPERATION_FAILED;
+}
+
+/*!
+ \brief This is the API to delete SL spawn task and delete the SL queue
+
+ \param none
+
+ \return void
+ \note
+ \warning
+*/
+void VDeleteSimpleLinkSpawnTask( void )
+{
+ if(0 != xSimpleLinkSpawnTaskHndl)
+ {
+ vTaskDelete( xSimpleLinkSpawnTaskHndl );
+ xSimpleLinkSpawnTaskHndl = 0;
+ }
+
+ if(0 !=xSimpleLinkSpawnQueue)
+ {
+ vQueueDelete( xSimpleLinkSpawnQueue );
+ xSimpleLinkSpawnQueue = 0;
+ }
+}
+
+/*!
+ \brief This function is used to create the MsgQ
+
+ \param pMsgQ - pointer to the message queue
+ \param pMsgQName - msg queue name
+ \param MsgSize - size of message on the queue
+ \param MaxMsgs - max. number of msgs that the queue can hold
+
+ \return - OsiReturnVal_e
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_MsgQCreate(OsiMsgQ_t* pMsgQ ,
+ char* pMsgQName,
+ unsigned long MsgSize,
+ unsigned long MaxMsgs)
+{
+ //Check for NULL
+ if(NULL == pMsgQ)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+
+ QueueHandle_t handle =0;
+
+ //Create Queue
+ handle = xQueueCreate( MaxMsgs, MsgSize );
+ if (handle==0)
+ {
+ return OSI_OPERATION_FAILED;
+ }
+
+ *pMsgQ = (OsiMsgQ_t)handle;
+ return OSI_OK;
+}
+/*!
+ \brief This function is used to delete the MsgQ
+
+ \param pMsgQ - pointer to the message queue
+
+ \return - OsiReturnVal_e
+ \note
+ \warning
+*/
+OsiReturnVal_e osi_MsgQDelete(OsiMsgQ_t* pMsgQ)
+{
+ //Check for NULL
+ if(NULL == pMsgQ)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+ vQueueDelete((QueueHandle_t) *pMsgQ );
+ return OSI_OK;
+}
+/*!
+ \brief This function is used to write data to the MsgQ
+
+ \param pMsgQ - pointer to the message queue
+ \param pMsg - pointer to the Msg strut to read into
+ \param Timeout - timeout to wait for the Msg to be available
+
+ \return - OsiReturnVal_e
+ \note
+ \warning
+*/
+
+OsiReturnVal_e osi_MsgQWrite(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout)
+{
+ //Check for NULL
+ if(NULL == pMsgQ)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+
+ if(pdPASS == xQueueSendFromISR((QueueHandle_t) *pMsgQ, pMsg, &xHigherPriorityTaskWoken ))
+ {
+ taskYIELD ();
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+/*!
+ \brief This function is used to read data from the MsgQ
+
+ \param pMsgQ - pointer to the message queue
+ \param pMsg - pointer to the Msg strut to read into
+ \param Timeout - timeout to wait for the Msg to be available
+
+ \return - OsiReturnVal_e
+ \note
+ \warning
+*/
+
+OsiReturnVal_e osi_MsgQRead(OsiMsgQ_t* pMsgQ, void* pMsg , OsiTime_t Timeout)
+{
+ //Check for NULL
+ if(NULL == pMsgQ)
+ {
+ return OSI_INVALID_PARAMS;
+ }
+
+ if ( Timeout == OSI_WAIT_FOREVER )
+ {
+ Timeout = portMAX_DELAY ;
+ }
+
+ //Receive Item from Queue
+ if( pdTRUE == xQueueReceive((QueueHandle_t)*pMsgQ,pMsg,Timeout) )
+ {
+ return OSI_OK;
+ }
+ else
+ {
+ return OSI_OPERATION_FAILED;
+ }
+}
+
+/*!
+ \brief This function to call the memory de-allocation function of the FREERTOS
+
+ \param Size - size of memory to alloc in bytes
+
+ \return - void *
+ \note
+ \warning
+*/
+
+void * mem_Malloc(unsigned long Size)
+{
+
+ return ( void * ) pvPortMalloc( (size_t)Size );
+}
+
+/*!
+ \brief This function to call the memory de-allocation function of the FREERTOS
+
+ \param pMem - pointer to the memory which needs to be freed
+
+ \return - void
+ \note
+ \warning
+*/
+void mem_Free(void *pMem)
+{
+ vPortFree( pMem );
+}
+
+/*!
+ \brief This function call the memset function
+ \param pBuf - pointer to the memory to be fill
+ \param Val - Value to be fill
+ \param Size - Size of the memory which needs to be fill
+ \return - void
+ \note
+ \warning
+*/
+
+void mem_set(void *pBuf,int Val,size_t Size)
+{
+ memset( pBuf,Val,Size);
+
+}
+
+/*!
+ \brief This function call the memcopy function
+ \param pDst - pointer to the destination
+ \param pSrc - pointer to the source
+ \param Size - Size of the memory which needs to be copy
+
+ \return - void
+ \note
+ \warning
+*/
+void mem_copy(void *pDst, void *pSrc,size_t Size)
+{
+ memcpy(pDst,pSrc,Size);
+}
+
+
+/*!
+ \brief This function use to entering into critical section
+ \param void
+ \return - void
+ \note
+ \warning
+*/
+
+void osi_EnterCritical(void)
+{
+ vPortEnterCritical();
+}
+
+/*!
+ \brief This function use to exit critical section
+ \param void
+ \return - void
+ \note
+ \warning
+*/
+
+void osi_ExitCritical(void)
+{
+ vPortExitCritical();
+}
+/*!
+ \brief This function used to start the scheduler
+ \param void
+ \return - void
+ \note
+ \warning
+*/
+void osi_start()
+{
+ vTaskStartScheduler();
+}
+/*!
+ \brief This function used to suspend the task for the specified number of milli secs
+ \param MilliSecs - Time in millisecs to suspend the task
+ \return - void
+ \note
+ \warning
+*/
+void osi_Sleep(unsigned int MilliSecs)
+{
+ TickType_t xDelay = MilliSecs / portTICK_PERIOD_MS;
+ vTaskDelay(xDelay);
+}
+
+
+/*!
+ \brief This function used to disable the tasks
+ \param - void
+ \return - Key with the suspended tasks
+ \note
+ \warning
+*/
+unsigned long osi_TaskDisable(void)
+{
+ vTaskSuspendAll();
+
+ return OSI_OK;
+}
+
+
+/*!
+ \brief This function used to resume all the tasks
+ \param key - returned from suspend tasks
+ \return - void
+ \note
+ \warning
+*/
+void osi_TaskEnable(unsigned long key)
+{
+ xTaskResumeAll();
+}
+
+/*!
+ \brief This function used to save the OS context before sleep
+ \param void
+ \return - void
+ \note
+ \warning
+*/
+void osi_ContextSave()
+{
+
+}
+/*!
+ \brief This function used to restore the OS context after sleep
+ \param void
+ \return - void
+ \note
+ \warning
+*/
+void osi_ContextRestore()
+{
+
+}
diff --git a/cc3200/simplelink/source/device.c b/cc3200/simplelink/source/device.c
new file mode 100644
index 0000000000..a77e8335ec
--- /dev/null
+++ b/cc3200/simplelink/source/device.c
@@ -0,0 +1,535 @@
+/*
+* device.c - CC31xx/CC32xx Host Driver Implementation
+*
+* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "flowcont.h"
+#include "driver.h"
+
+
+/*****************************************************************************/
+/* Internal functions */
+/*****************************************************************************/
+
+_i16 _sl_GetStartResponseConvert(_u32 Status)
+{
+ switch(Status)
+ {
+ case INIT_STA_OK:
+ return ROLE_STA;
+ case INIT_STA_ERR:
+ return ROLE_STA_ERR;
+ case INIT_AP_OK:
+ return ROLE_AP;
+ case INIT_AP_ERR:
+ return ROLE_AP_ERR;
+ case INIT_P2P_OK:
+ return ROLE_P2P;
+ case INIT_P2P_ERR:
+ return ROLE_P2P_ERR;
+ default:
+ return (_i16)Status;
+ }
+}
+
+/*****************************************************************************/
+/* API Functions */
+/*****************************************************************************/
+
+
+
+/*****************************************************************************/
+/* sl_Task */
+/*****************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_Task)
+void sl_Task(void)
+{
+#ifdef _SlTaskEntry
+ _SlTaskEntry();
+#endif
+}
+#endif
+
+/*****************************************************************************/
+/* sl_Start */
+/*****************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_Start)
+_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack)
+{
+ _i16 ObjIdx = MAX_CONCURRENT_ACTIONS;
+ InitComplete_t AsyncRsp;
+
+ /* Perform any preprocessing before enable networking services */
+ sl_DeviceEnablePreamble();
+
+ /* ControlBlock init */
+ _SlDrvDriverCBInit();
+
+ /* open the interface: usually SPI or UART */
+ if (NULL == pIfHdl)
+ {
+ g_pCB->FD = sl_IfOpen((void *)pDevName, 0);
+ }
+ else
+ {
+ g_pCB->FD = (_SlFd_t)pIfHdl;
+ }
+ /* Use Obj to issue the command, if not available try later */
+ ObjIdx = _SlDrvWaitForPoolObj(START_STOP_ID,SL_MAX_SOCKETS);
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp;
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+
+ if( g_pCB->FD >= 0)
+ {
+ sl_DeviceDisable();
+
+ sl_IfRegIntHdlr((SL_P_EVENT_HANDLER)_SlDrvRxIrqHandler, NULL);
+
+ if(NULL != pInitCallBack)
+ {
+ g_pCB->pInitCallback = pInitCallBack;
+ }
+ sl_DeviceEnable();
+
+ if (NULL == pInitCallBack)
+ {
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+ /*release Pool Object*/
+ _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex);
+ return _sl_GetStartResponseConvert(AsyncRsp.Status);
+ }
+ }
+
+ return (_i16)g_pCB->FD;
+
+}
+#endif
+
+/***************************************************************************
+_sl_HandleAsync_InitComplete - handles init complete signalling to
+a waiting object
+****************************************************************************/
+void _sl_HandleAsync_InitComplete(void *pVoidBuf)
+{
+ InitComplete_t *pMsgArgs = (InitComplete_t *)_SL_RESP_ARGS_START(pVoidBuf);
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ if(g_pCB->pInitCallback)
+ {
+ g_pCB->pInitCallback(_sl_GetStartResponseConvert(pMsgArgs->Status));
+ }
+ else
+ {
+ sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(InitComplete_t));
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj));
+ }
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+
+ if(g_pCB->pInitCallback)
+ {
+ _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex);
+ }
+
+}
+
+/***************************************************************************
+_sl_HandleAsync_Stop - handles stop signalling to
+a waiting object
+****************************************************************************/
+void _sl_HandleAsync_Stop(void *pVoidBuf)
+{
+ _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pVoidBuf);
+
+ VERIFY_SOCKET_CB(NULL != g_pCB->StopCB.pAsyncRsp);
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_BasicResponse_t));
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj));
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ return;
+}
+
+
+/*****************************************************************************
+sl_stop
+******************************************************************************/
+typedef union
+{
+ _DevStopCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlStopMsg_u;
+
+const _SlCmdCtrl_t _SlStopCmdCtrl =
+{
+ SL_OPCODE_DEVICE_STOP_COMMAND,
+ sizeof(_DevStopCommand_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_Stop)
+_i16 sl_Stop(_u16 timeout)
+{
+ _i16 RetVal=0;
+ _SlStopMsg_u Msg;
+ _BasicResponse_t AsyncRsp;
+ _i16 ObjIdx = MAX_CONCURRENT_ACTIONS;
+ /* if timeout is 0 the shutdown is forced immediately */
+ if( 0 == timeout )
+ {
+ sl_IfRegIntHdlr(NULL, NULL);
+ sl_DeviceDisable();
+ RetVal = sl_IfClose(g_pCB->FD);
+
+ }
+ else
+ {
+ /* let the device make the shutdown using the defined timeout */
+ Msg.Cmd.Timeout = timeout;
+ /* Use Obj to issue the command, if not available try later */
+ ObjIdx = _SlDrvWaitForPoolObj(START_STOP_ID,SL_MAX_SOCKETS);
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp;
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlStopCmdCtrl, &Msg, NULL));
+
+ if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status)
+ {
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+ Msg.Rsp.status = AsyncRsp.status;
+ RetVal = Msg.Rsp.status;
+ }
+
+ _SlDrvReleasePoolObj((_u8)ObjIdx);
+
+ sl_IfRegIntHdlr(NULL, NULL);
+ sl_DeviceDisable();
+ sl_IfClose(g_pCB->FD);
+ }
+ _SlDrvDriverCBDeinit();
+
+ return RetVal;
+}
+#endif
+
+
+/*****************************************************************************
+sl_EventMaskSet
+*****************************************************************************/
+typedef union
+{
+ _DevMaskEventSetCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlEventMaskSetMsg_u;
+
+const _SlCmdCtrl_t _SlEventMaskSetCmdCtrl =
+{
+ SL_OPCODE_DEVICE_EVENTMASKSET,
+ sizeof(_DevMaskEventSetCommand_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_EventMaskSet)
+_i16 sl_EventMaskSet(_u8 EventClass , _u32 Mask)
+{
+ _SlEventMaskSetMsg_u Msg;
+
+ Msg.Cmd.group = EventClass;
+ Msg.Cmd.mask = Mask;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskSetCmdCtrl, &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+/******************************************************************************
+sl_EventMaskGet
+******************************************************************************/
+typedef union
+{
+ _DevMaskEventGetCommand_t Cmd;
+ _DevMaskEventGetResponse_t Rsp;
+}_SlEventMaskGetMsg_u;
+
+const _SlCmdCtrl_t _SlEventMaskGetCmdCtrl =
+{
+ SL_OPCODE_DEVICE_EVENTMASKGET,
+ sizeof(_DevMaskEventGetCommand_t),
+ sizeof(_DevMaskEventGetResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_EventMaskGet)
+_i16 sl_EventMaskGet(_u8 EventClass, _u32 *pMask)
+{
+ _SlEventMaskGetMsg_u Msg;
+
+ Msg.Cmd.group = EventClass;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskGetCmdCtrl, &Msg, NULL));
+
+ *pMask = Msg.Rsp.mask;
+ return SL_RET_CODE_OK;
+}
+#endif
+
+
+
+/******************************************************************************
+sl_DevGet
+******************************************************************************/
+
+typedef union
+{
+ _DeviceSetGet_t Cmd;
+ _DeviceSetGet_t Rsp;
+}_SlDeviceMsgGet_u;
+
+const _SlCmdCtrl_t _SlDeviceGetCmdCtrl =
+{
+ SL_OPCODE_DEVICE_DEVICEGET,
+ sizeof(_DeviceSetGet_t),
+ sizeof(_DeviceSetGet_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_DevGet)
+_i32 sl_DevGet(_u8 DeviceGetId, _u8 *pOption,_u8 *pConfigLen, _u8 *pValues)
+{
+ _SlDeviceMsgGet_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (*pConfigLen == 0)
+ {
+ return SL_EZEROLEN;
+ }
+
+ if( pOption )
+ {
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = *pConfigLen;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)pValues;
+ CmdExt.ActualRxPayloadLen = 0;
+
+ Msg.Cmd.DeviceSetId = DeviceGetId;
+
+ Msg.Cmd.Option = (_u16)*pOption;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceGetCmdCtrl, &Msg, &CmdExt));
+
+ if( pOption )
+ {
+ *pOption = (_u8)Msg.Rsp.Option;
+ }
+
+ if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen)
+ {
+ *pConfigLen = (_u8)CmdExt.RxPayloadLen;
+ return SL_ESMALLBUF;
+ }
+ else
+ {
+ *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen;
+ }
+
+ return (_i16)Msg.Rsp.Status;
+ }
+ else
+ {
+ return -1;
+ }
+}
+#endif
+
+/******************************************************************************
+sl_DevSet
+******************************************************************************/
+typedef union
+{
+ _DeviceSetGet_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlDeviceMsgSet_u;
+
+const _SlCmdCtrl_t _SlDeviceSetCmdCtrl =
+{
+ SL_OPCODE_DEVICE_DEVICESET,
+ sizeof(_DeviceSetGet_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_DevSet)
+_i32 sl_DevSet(_u8 DeviceSetId ,_u8 Option,_u8 ConfigLen, _u8 *pValues)
+{
+ _SlDeviceMsgSet_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (ConfigLen+3) & (~3);
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pValues;
+ CmdExt.pRxPayload = NULL;
+
+
+ Msg.Cmd.DeviceSetId = DeviceSetId;
+ Msg.Cmd.ConfigLen = ConfigLen;
+ Msg.Cmd.Option = Option;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceSetCmdCtrl, &Msg, &CmdExt));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+
+/******************************************************************************
+_SlDrvDeviceEventHandler - handles internally device async events
+******************************************************************************/
+void _SlDrvDeviceEventHandler(void *pArgs)
+{
+ _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pArgs;
+
+ switch(pHdr->GenHeader.Opcode)
+ {
+ case SL_OPCODE_DEVICE_INITCOMPLETE:
+ _sl_HandleAsync_InitComplete(pHdr);
+ break;
+ case SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE:
+ _sl_HandleAsync_Stop(pHdr);
+ break;
+ case SL_OPCODE_DEVICE_DEVICEASYNCFATALERROR:
+#ifdef sl_GeneralEvtHdlr
+ {
+ _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pHdr);
+ SlDeviceEvent_t devHandler;
+ devHandler.Event = SL_DEVICE_FATAL_ERROR_EVENT;
+ devHandler.EventData.deviceEvent.status = pMsgArgs->status & 0xFF;
+ devHandler.EventData.deviceEvent.sender = (SlErrorSender_e)((pMsgArgs->status >> 8) & 0xFF);
+ sl_GeneralEvtHdlr(&devHandler);
+ }
+#endif
+ break;
+ default:
+ SL_ERROR_TRACE1(MSG_306, "ASSERT: _SlDrvDeviceEventHandler : invalid opcode = 0x%x", pHdr->GenHeader.Opcode);
+ VERIFY_PROTOCOL(0);
+ }
+}
+
+
+/******************************************************************************
+sl_UartSetMode
+******************************************************************************/
+#ifdef SL_IF_TYPE_UART
+typedef union
+{
+ _DevUartSetModeCommand_t Cmd;
+ _DevUartSetModeResponse_t Rsp;
+}_SlUartSetModeMsg_u;
+
+const _SlCmdCtrl_t _SlUartSetModeCmdCtrl =
+{
+ SL_OPCODE_DEVICE_SETUARTMODECOMMAND,
+ sizeof(_DevUartSetModeCommand_t),
+ sizeof(_DevUartSetModeResponse_t)
+};
+
+
+#if _SL_INCLUDE_FUNC(sl_UartSetMode)
+_i16 sl_UartSetMode(const SlUartIfParams_t* pUartParams)
+{
+ _SlUartSetModeMsg_u Msg;
+ _u32 magicCode = 0xFFFFFFFF;
+
+ Msg.Cmd.BaudRate = pUartParams->BaudRate;
+ Msg.Cmd.FlowControlEnable = pUartParams->FlowControlEnable;
+
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlUartSetModeCmdCtrl, &Msg, NULL));
+
+ /* cmd response OK, we can continue with the handshake */
+ if (SL_RET_CODE_OK == Msg.Rsp.status)
+ {
+ sl_IfMaskIntHdlr();
+
+ /* Close the comm port */
+ sl_IfClose(g_pCB->FD);
+
+ /* Re-open the comm port */
+ sl_IfOpen((void * )pUartParams, UART_IF_OPEN_FLAG_RE_OPEN);
+
+ sl_IfUnMaskIntHdlr();
+
+ /* send the magic code and wait for the response */
+ sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4);
+
+ magicCode = UART_SET_MODE_MAGIC_CODE;
+ sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4);
+
+ /* clear magic code */
+ magicCode = 0;
+
+ /* wait (blocking) till the magic code to be returned from device */
+ sl_IfRead(g_pCB->FD, (_u8* )&magicCode, 4);
+
+ /* check for the received magic code matching */
+ if (UART_SET_MODE_MAGIC_CODE != magicCode)
+ {
+ _SL_ASSERT(0);
+ }
+ }
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+#endif
+
+
diff --git a/cc3200/simplelink/source/driver.c b/cc3200/simplelink/source/driver.c
new file mode 100644
index 0000000000..fe6bf52520
--- /dev/null
+++ b/cc3200/simplelink/source/driver.c
@@ -0,0 +1,1520 @@
+/*
+* driver.c - CC31xx/CC32xx Host Driver Implementation
+*
+* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+#include "flowcont.h"
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+#define _SL_PENDING_RX_MSG(pDriverCB) ((pDriverCB)->RxIrqCnt != (pDriverCB)->RxDoneCnt)
+
+/* 2 LSB of the N2H_SYNC_PATTERN are for sequence number
+only in SPI interface
+support backward sync pattern */
+#define N2H_SYNC_PATTERN_SEQ_NUM_BITS ((_u32)0x00000003) /* Bits 0..1 - use the 2 LBS for seq num */
+#define N2H_SYNC_PATTERN_SEQ_NUM_EXISTS ((_u32)0x00000004) /* Bit 2 - sign that sequence number exists in the sync pattern */
+#define N2H_SYNC_PATTERN_MASK ((_u32)0xFFFFFFF8) /* Bits 3..31 - constant SYNC PATTERN */
+#define N2H_SYNC_SPI_BUGS_MASK ((_u32)0x7FFF7F7F) /* Bits 7,15,31 - ignore the SPI (8,16,32 bites bus) error bits */
+#define BUF_SYNC_SPIM(pBuf) ((*(_u32 *)(pBuf)) & N2H_SYNC_SPI_BUGS_MASK)
+#define N2H_SYNC_SPIM (N2H_SYNC_PATTERN & N2H_SYNC_SPI_BUGS_MASK)
+#define N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum) ((N2H_SYNC_SPIM & N2H_SYNC_PATTERN_MASK) | N2H_SYNC_PATTERN_SEQ_NUM_EXISTS | ((TxSeqNum) & (N2H_SYNC_PATTERN_SEQ_NUM_BITS)))
+#define MATCH_WOUT_SEQ_NUM(pBuf) ( BUF_SYNC_SPIM(pBuf) == N2H_SYNC_SPIM )
+#define MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ( BUF_SYNC_SPIM(pBuf) == (N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum)) )
+#define N2H_SYNC_PATTERN_MATCH(pBuf, TxSeqNum) \
+ ( \
+ ( (*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ) ) || \
+ ( !(*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WOUT_SEQ_NUM(pBuf ) ) ) \
+ )
+
+#define OPCODE(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Opcode)
+#define RSP_PAYLOAD_LEN(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Len - _SL_RESP_SPEC_HDR_SIZE)
+#define SD(_ptr) (((_SocketAddrResponse_u *)(_ptr))->IpV4.sd)
+/* Actual size of Recv/Recvfrom response data */
+#define ACT_DATA_SIZE(_ptr) (((_SocketAddrResponse_u *)(_ptr))->IpV4.statusOrLen)
+
+#if (SL_MEMORY_MGMT == SL_MEMORY_MGMT_STATIC)
+typedef struct
+{
+ _u32 Align;
+ _SlDriverCb_t DriverCB;
+ _u8 AsyncRespBuf[SL_ASYNC_MAX_MSG_LEN];
+}_SlStatMem_t;
+
+_SlStatMem_t g_StatMem;
+#endif
+
+/*****************************************************************************/
+/* Variables */
+/*****************************************************************************/
+const _SlSyncPattern_t g_H2NSyncPattern = H2N_SYNC_PATTERN;
+const _SlSyncPattern_t g_H2NCnysPattern = H2N_CNYS_PATTERN;
+const _SlActionLookup_t _SlActionLookupTable[7] =
+{
+ {ACCEPT_ID, SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE, (_SlSpawnEntryFunc_t)_sl_HandleAsync_Accept},
+ {CONNECT_ID, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_sl_HandleAsync_Connect},
+ {SELECT_ID, SL_OPCODE_SOCKET_SELECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_sl_HandleAsync_Select},
+ {GETHOSYBYNAME_ID, SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_sl_HandleAsync_DnsGetHostByName},
+ {GETHOSYBYSERVICE_ID, SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_sl_HandleAsync_DnsGetHostByService},
+ {PING_ID, SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE, (_SlSpawnEntryFunc_t)_sl_HandleAsync_PingResponse},
+ {START_STOP_ID, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE,(_SlSpawnEntryFunc_t)_sl_HandleAsync_Stop}
+
+};
+
+_SlDriverCb_t* g_pCB = NULL;
+P_SL_DEV_PING_CALLBACK pPingCallBackFunc = NULL;
+_u8 gFirstCmdMode = 0;
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+_SlReturnVal_t _SlDrvMsgRead(void);
+_SlReturnVal_t _SlDrvMsgWrite(void);
+_SlReturnVal_t _SlDrvMsgReadCmdCtx(void);
+_SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue);
+void _SlDrvClassifyRxMsg(_SlOpcode_t Opcode );
+_SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf, _u8 *pAlignSize);
+void _SlDrvShiftDWord(_u8 *pBuf);
+void _SlDrvDriverCBInit(void);
+void _SlAsyncEventGenericHandler(void);
+_i16 _SlDrvWaitForPoolObj(_u32 ActionID, _u8 SocketID);
+void _SlDrvReleasePoolObj(_u8 pObj);
+void _SlDrvObjInit(void);
+void _SlDrvObjDeInit(void);
+void _SlRemoveFromList(_u8* ListIndex, _u8 ItemIndex);
+_SlReturnVal_t _SlFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd);
+
+
+/*****************************************************************************/
+/* Internal functions */
+/*****************************************************************************/
+
+
+
+/*****************************************************************************
+_SlDrvDriverCBInit - init Driver Control Block
+*****************************************************************************/
+void _SlDrvDriverCBInit(void)
+{
+ _u8 Idx;
+
+#if (SL_MEMORY_MGMT == SL_MEMORY_MGMT_STATIC)
+ g_pCB = &(g_StatMem.DriverCB);
+#else
+ g_pCB = sl_Malloc(sizeof(_SlDriverCb_t));
+#endif
+ MALLOC_OK_CHECK(g_pCB);
+
+ sl_Memset((g_pCB), 0, sizeof(_SlDriverCb_t));
+
+ OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->CmdSyncObj, "CmdSyncObj") );
+ sl_SyncObjClear(&g_pCB->CmdSyncObj);
+
+ OSI_RET_OK_CHECK( sl_LockObjCreate(&g_pCB->GlobalLockObj, "GlobalLockObj") );
+
+ OSI_RET_OK_CHECK( sl_LockObjCreate(&g_pCB->ProtectionLockObj, "ProtectionLockObj") );
+
+ _SlDrvObjInit();
+
+ for (Idx = 0; Idx < MAX_CONCURRENT_ACTIONS; Idx++)
+ {
+ OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->ObjPool[Idx].SyncObj, "SyncObj") );
+ sl_SyncObjClear(&g_pCB->ObjPool[Idx].SyncObj);
+ }
+ _SlDrvFlowContInit();
+ gFirstCmdMode = 0;
+}
+
+/*****************************************************************************
+_SlDrvDriverCBDeinit - De init Driver Control Block
+*****************************************************************************/
+void _SlDrvDriverCBDeinit()
+{
+ _u8 Idx;
+
+ _SlDrvFlowContDeinit();
+
+ OSI_RET_OK_CHECK( sl_SyncObjDelete(&g_pCB->CmdSyncObj) );
+
+ OSI_RET_OK_CHECK( sl_LockObjDelete(&g_pCB->GlobalLockObj) );
+
+ OSI_RET_OK_CHECK( sl_LockObjDelete(&g_pCB->ProtectionLockObj) );
+ for (Idx = 0; Idx < MAX_CONCURRENT_ACTIONS; Idx++)
+ {
+ OSI_RET_OK_CHECK( sl_SyncObjDelete(&g_pCB->ObjPool[Idx].SyncObj) );
+ }
+
+ _SlDrvObjDeInit();
+
+#if (SL_MEMORY_MGMT == SL_MEMORY_MGMT_STATIC)
+ g_pCB = NULL;
+#else
+ sl_Free(g_pCB);
+#endif
+
+ g_pCB = NULL;
+}
+
+/*****************************************************************************
+_SlDrvRxIrqHandler - Interrupt handler
+*****************************************************************************/
+void _SlDrvRxIrqHandler(void *pValue)
+{
+ sl_IfMaskIntHdlr();
+
+ g_pCB->RxIrqCnt++;
+
+ if (TRUE == g_pCB->IsCmdRespWaited)
+ {
+ OSI_RET_OK_CHECK( sl_SyncObjSignalFromIRQ(&g_pCB->CmdSyncObj) );
+ }
+ else
+ {
+ sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, 0);
+ }
+}
+
+/*****************************************************************************
+_SlDrvCmdOp
+*****************************************************************************/
+_SlReturnVal_t _SlDrvCmdOp(
+ _SlCmdCtrl_t *pCmdCtrl ,
+ void *pTxRxDescBuff ,
+ _SlCmdExt_t *pCmdExt)
+{
+ _SlReturnVal_t RetVal;
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->GlobalLockObj, SL_OS_WAIT_FOREVER));
+ g_pCB->IsCmdRespWaited = TRUE;
+
+ SL_TRACE0(DBG_MSG, MSG_312, "_SlDrvCmdOp: call _SlDrvMsgWrite");
+ /* send the message */
+ g_pCB->FunctionParams.pCmdCtrl = pCmdCtrl;
+ g_pCB->FunctionParams.pTxRxDescBuff = pTxRxDescBuff;
+ g_pCB->FunctionParams.pCmdExt = pCmdExt;
+
+ RetVal = _SlDrvMsgWrite();
+
+ if(SL_OS_RET_CODE_OK == RetVal)
+ {
+
+#ifndef SL_IF_TYPE_UART
+ /* Waiting for SPI to stabilize after first command */
+ if( 0 == gFirstCmdMode )
+ {
+ volatile _u32 CountVal = 0;
+ gFirstCmdMode = 1;
+ CountVal = CPU_FREQ_IN_MHZ*USEC_DELAY;
+ while( CountVal-- );
+ }
+#endif
+ /* wait for respond */
+ RetVal = _SlDrvMsgReadCmdCtx(); /* will free global lock */
+ SL_TRACE0(DBG_MSG, MSG_314, "_SlDrvCmdOp: exited _SlDrvMsgReadCmdCtx");
+
+ }
+ else
+ {
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->GlobalLockObj));
+ }
+
+ return RetVal;
+}
+
+/*****************************************************************************
+_SlDrvCmdSend
+Send SL command without waiting for command response
+This function is unprotected and the caller should make
+sure global lock is active
+*****************************************************************************/
+_SlReturnVal_t _SlDrvCmdSend(
+ _SlCmdCtrl_t *pCmdCtrl ,
+ void *pTxRxDescBuff ,
+ _SlCmdExt_t *pCmdExt)
+{
+ _SlReturnVal_t RetVal;
+
+ g_pCB->IsCmdRespWaited = FALSE;
+
+ SL_TRACE0(DBG_MSG, MSG_312, "_SlDrvCmdSend: call _SlDrvMsgWrite");
+ /* send the message */
+ g_pCB->FunctionParams.pCmdCtrl = pCmdCtrl;
+ g_pCB->FunctionParams.pTxRxDescBuff = pTxRxDescBuff;
+ g_pCB->FunctionParams.pCmdExt = pCmdExt;
+
+ RetVal = _SlDrvMsgWrite();
+
+ return RetVal;
+}
+
+/*****************************************************************************
+_SlDrvDataReadOp
+*****************************************************************************/
+_SlReturnVal_t _SlDrvDataReadOp(
+ _SlSd_t Sd,
+ _SlCmdCtrl_t *pCmdCtrl ,
+ void *pTxRxDescBuff ,
+ _SlCmdExt_t *pCmdExt)
+{
+ _SlReturnVal_t RetVal;
+ _u8 ObjIdx = MAX_CONCURRENT_ACTIONS;
+ _SlArgsData_t pArgsData;
+
+ /* Validate input arguments */
+ VERIFY_PROTOCOL(NULL != pCmdExt->pRxPayload);
+
+ /* If zero bytes is requested, return error. */
+ /* This allows us not to fill remote socket's IP address in return arguments */
+ VERIFY_PROTOCOL(0 != pCmdExt->RxPayloadLen);
+
+ /* Validate socket */
+ if((Sd & BSD_SOCKET_ID_MASK) >= SL_MAX_SOCKETS)
+ {
+ return SL_EBADF;
+ }
+
+ /*Use Obj to issue the command, if not available try later*/
+ ObjIdx = (_u8)_SlDrvWaitForPoolObj(RECV_ID, Sd & BSD_SOCKET_ID_MASK);
+
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ pArgsData.pData = pCmdExt->pRxPayload;
+ pArgsData.pArgs = (_u8 *)pTxRxDescBuff;
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&pArgsData;
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+
+
+ /* Do Flow Control check/update for DataWrite operation */
+ OSI_RET_OK_CHECK( sl_LockObjLock(&g_pCB->FlowContCB.TxLockObj, SL_OS_WAIT_FOREVER) );
+
+ /* Clear SyncObj for the case it was signalled before TxPoolCnt */
+ /* dropped below '1' (last Data buffer was taken) */
+ /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */
+ sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj);
+
+ if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN)
+ {
+
+ /* If TxPoolCnt was increased by other thread at this moment,
+ TxSyncObj won't wait here */
+ OSI_RET_OK_CHECK( sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_WAIT_FOREVER) );
+ }
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->GlobalLockObj, SL_OS_WAIT_FOREVER));
+
+ VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN);
+ g_pCB->FlowContCB.TxPoolCnt--;
+
+ OSI_RET_OK_CHECK( sl_LockObjUnlock(&g_pCB->FlowContCB.TxLockObj) );
+
+ /* send the message */
+ g_pCB->TempProtocolHeader.Opcode = pCmdCtrl->Opcode;
+ g_pCB->TempProtocolHeader.Len = _SL_PROTOCOL_CALC_LEN(pCmdCtrl,pCmdExt);
+ g_pCB->FunctionParams.pCmdCtrl = pCmdCtrl;
+ g_pCB->FunctionParams.pTxRxDescBuff = (_u8 *)pTxRxDescBuff;
+ g_pCB->FunctionParams.pCmdExt = pCmdExt;
+ RetVal = _SlDrvMsgWrite();
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->GlobalLockObj));
+
+ if(SL_OS_RET_CODE_OK == RetVal)
+ {
+ /* Wait for response message. Will be signalled by _SlDrvMsgRead. */
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+ }
+
+ _SlDrvReleasePoolObj(ObjIdx);
+ return RetVal;
+}
+
+/* ******************************************************************************/
+/* _SlDrvDataWriteOp */
+/* ******************************************************************************/
+_SlReturnVal_t _SlDrvDataWriteOp(
+ _SlSd_t Sd,
+ _SlCmdCtrl_t *pCmdCtrl ,
+ void *pTxRxDescBuff ,
+ _SlCmdExt_t *pCmdExt)
+{
+ _SlReturnVal_t RetVal = SL_EAGAIN; /* initiated as SL_EAGAIN for the non blocking mode */
+ while( 1 )
+ {
+ /* Do Flow Control check/update for DataWrite operation */
+ OSI_RET_OK_CHECK( sl_LockObjLock(&g_pCB->FlowContCB.TxLockObj, SL_OS_WAIT_FOREVER) );
+
+ /* Clear SyncObj for the case it was signalled before TxPoolCnt */
+ /* dropped below '1' (last Data buffer was taken) */
+ /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */
+ sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj);
+
+ /* we have indication that the last send has failed - socket is no longer valid for operations */
+ if(g_pCB->SocketTXFailure & (1<<(Sd & BSD_SOCKET_ID_MASK)))
+ {
+ OSI_RET_OK_CHECK( sl_LockObjUnlock(&g_pCB->FlowContCB.TxLockObj) );
+ return SL_SOC_ERROR;
+ }
+ if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN + 1)
+ {
+ /* we have indication that this socket is set as blocking and we try to */
+ /* unblock it - return an error */
+ if( g_pCB->SocketNonBlocking >> (Sd & BSD_SOCKET_ID_MASK) )
+ {
+ OSI_RET_OK_CHECK( sl_LockObjUnlock(&g_pCB->FlowContCB.TxLockObj) );
+ return RetVal;
+ }
+ /* If TxPoolCnt was increased by other thread at this moment, */
+ /* TxSyncObj won't wait here */
+ OSI_RET_OK_CHECK( sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_WAIT_FOREVER) );
+ }
+ if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN + 1 )
+ {
+ break;
+ }
+ else
+ {
+ OSI_RET_OK_CHECK( sl_LockObjUnlock(&g_pCB->FlowContCB.TxLockObj) );
+ }
+ }
+ OSI_RET_OK_CHECK( sl_LockObjLock(&g_pCB->GlobalLockObj, SL_OS_WAIT_FOREVER) );
+
+ VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN + 1 );
+ g_pCB->FlowContCB.TxPoolCnt--;
+
+ OSI_RET_OK_CHECK( sl_LockObjUnlock(&g_pCB->FlowContCB.TxLockObj) );
+
+ /* send the message */
+ g_pCB->TempProtocolHeader.Opcode = pCmdCtrl->Opcode;
+ g_pCB->TempProtocolHeader.Len = _SL_PROTOCOL_CALC_LEN(pCmdCtrl,pCmdExt);
+
+ g_pCB->FunctionParams.pCmdCtrl = pCmdCtrl;
+ g_pCB->FunctionParams.pTxRxDescBuff = pTxRxDescBuff;
+ g_pCB->FunctionParams.pCmdExt = pCmdExt;
+ RetVal = _SlDrvMsgWrite();
+
+ OSI_RET_OK_CHECK( sl_LockObjUnlock(&g_pCB->GlobalLockObj) );
+
+ return RetVal;
+}
+
+/* ******************************************************************************/
+/* _SlDrvMsgWrite */
+/* ******************************************************************************/
+_SlReturnVal_t _SlDrvMsgWrite(void)
+{
+ VERIFY_PROTOCOL(NULL != g_pCB->FunctionParams.pCmdCtrl);
+
+ g_pCB->TempProtocolHeader.Opcode = g_pCB->FunctionParams.pCmdCtrl->Opcode;
+ g_pCB->TempProtocolHeader.Len = _SL_PROTOCOL_CALC_LEN(g_pCB->FunctionParams.pCmdCtrl,
+ g_pCB->FunctionParams.pCmdExt);
+ /* */
+ if (g_pCB->RelayFlagsViaRxPayload == TRUE)
+ {
+ g_pCB->TempProtocolHeader.Len = g_pCB->TempProtocolHeader.Len + g_pCB->FunctionParams.pCmdExt->RxPayloadLen;
+ }
+
+#ifdef SL_START_WRITE_STAT
+ sl_IfStartWriteSequence(g_pCB->FD);
+#endif
+
+#ifdef SL_IF_TYPE_UART
+ /* Write long sync pattern */
+ NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Long, 2*SYNC_PATTERN_LEN);
+#else
+ /* Write short sync pattern */
+ NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Short, SYNC_PATTERN_LEN);
+#endif
+
+ /* Header */
+ NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_pCB->TempProtocolHeader, _SL_CMD_HDR_SIZE);
+
+ /* Descriptors */
+ if (g_pCB->FunctionParams.pTxRxDescBuff && g_pCB->FunctionParams.pCmdCtrl->TxDescLen > 0)
+ {
+ NWP_IF_WRITE_CHECK(g_pCB->FD, g_pCB->FunctionParams.pTxRxDescBuff,
+ _SL_PROTOCOL_ALIGN_SIZE(g_pCB->FunctionParams.pCmdCtrl->TxDescLen));
+ }
+
+ /* A special mode where Rx payload and Rx length are used as Tx as well */
+ /* This mode requires no Rx payload on the response and currently used by fs_Close and sl_Send on */
+ /* transceiver mode */
+ if (g_pCB->RelayFlagsViaRxPayload == TRUE )
+ {
+ g_pCB->RelayFlagsViaRxPayload = FALSE;
+ NWP_IF_WRITE_CHECK(g_pCB->FD, g_pCB->FunctionParams.pCmdExt->pRxPayload,
+ _SL_PROTOCOL_ALIGN_SIZE(g_pCB->FunctionParams.pCmdExt->RxPayloadLen));
+ }
+
+ /* Payload */
+ if (g_pCB->FunctionParams.pCmdExt && g_pCB->FunctionParams.pCmdExt->TxPayloadLen > 0)
+ {
+ /* If the message has payload, it is mandatory that the message's arguments are protocol aligned. */
+ /* Otherwise the aligning of arguments will create a gap between arguments and payload. */
+ VERIFY_PROTOCOL(_SL_IS_PROTOCOL_ALIGNED_SIZE(g_pCB->FunctionParams.pCmdCtrl->TxDescLen));
+
+ NWP_IF_WRITE_CHECK(g_pCB->FD, g_pCB->FunctionParams.pCmdExt->pTxPayload,
+ _SL_PROTOCOL_ALIGN_SIZE(g_pCB->FunctionParams.pCmdExt->TxPayloadLen));
+ }
+
+
+ _SL_DBG_CNT_INC(MsgCnt.Write);
+
+#ifdef SL_START_WRITE_STAT
+ sl_IfEndWriteSequence(g_pCB->FD);
+#endif
+
+ return SL_OS_RET_CODE_OK;
+}
+
+/* ******************************************************************************/
+/* _SlDrvMsgRead */
+/* ******************************************************************************/
+_SlReturnVal_t _SlDrvMsgRead(void)
+{
+ /* alignment for small memory models */
+ union
+ {
+ _u8 TempBuf[_SL_RESP_HDR_SIZE];
+ _u32 DummyBuf[2];
+ } uBuf;
+ _u8 TailBuffer[4];
+ _u16 LengthToCopy;
+ _u16 AlignedLengthRecv;
+ _u8 AlignSize;
+
+ VERIFY_RET_OK(_SlDrvRxHdrRead((_u8*)(uBuf.TempBuf), &AlignSize));
+
+ /* 'Init Compelete' message bears no valid FlowControl info */
+ if(SL_OPCODE_DEVICE_INITCOMPLETE != OPCODE(uBuf.TempBuf))
+ {
+ g_pCB->FlowContCB.TxPoolCnt = ((_SlResponseHeader_t *)uBuf.TempBuf)->TxPoolCnt;
+ g_pCB->SocketNonBlocking = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketNonBlocking;
+ g_pCB->SocketTXFailure = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketTXFailure;
+
+ if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN)
+ {
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->FlowContCB.TxSyncObj));
+ }
+ }
+
+ _SlDrvClassifyRxMsg(OPCODE(uBuf.TempBuf));
+
+ switch(g_pCB->FunctionParams.AsyncExt.RxMsgClass)
+ {
+ case ASYNC_EVT_CLASS:
+
+ VERIFY_PROTOCOL(NULL == g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+
+#if (SL_MEMORY_MGMT == SL_MEMORY_MGMT_STATIC)
+ g_pCB->FunctionParams.AsyncExt.pAsyncBuf = g_StatMem.AsyncRespBuf;
+#else
+ g_pCB->FunctionParams.AsyncExt.pAsyncBuf = sl_Malloc(SL_ASYNC_MAX_MSG_LEN);
+#endif
+ MALLOC_OK_CHECK(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+
+ sl_Memcpy(g_pCB->FunctionParams.AsyncExt.pAsyncBuf, uBuf.TempBuf, _SL_RESP_HDR_SIZE);
+
+ /* This is an Async message. Read the rest of it. */
+ if (_SL_PROTOCOL_ALIGN_SIZE(RSP_PAYLOAD_LEN(uBuf.TempBuf)) <= SL_ASYNC_MAX_PAYLOAD_LEN)
+ {
+ AlignedLengthRecv = _SL_PROTOCOL_ALIGN_SIZE(RSP_PAYLOAD_LEN(uBuf.TempBuf));
+ }
+ else
+ {
+ AlignedLengthRecv = _SL_PROTOCOL_ALIGN_SIZE(SL_ASYNC_MAX_PAYLOAD_LEN);
+ }
+
+ if (RSP_PAYLOAD_LEN(uBuf.TempBuf) > 0)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,
+ g_pCB->FunctionParams.AsyncExt.pAsyncBuf + _SL_RESP_HDR_SIZE,
+ AlignedLengthRecv);
+ }
+ /* In case ASYNC RX buffer length is smaller then the received data length, dump the rest */
+ if ((_SL_PROTOCOL_ALIGN_SIZE(RSP_PAYLOAD_LEN(uBuf.TempBuf)) > SL_ASYNC_MAX_PAYLOAD_LEN))
+ {
+ AlignedLengthRecv = _SL_PROTOCOL_ALIGN_SIZE(RSP_PAYLOAD_LEN(uBuf.TempBuf)) - SL_ASYNC_MAX_PAYLOAD_LEN;
+ while (AlignedLengthRecv > 0)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4);
+ AlignedLengthRecv = AlignedLengthRecv - 4;
+ }
+ }
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ if ((SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE == OPCODE(uBuf.TempBuf)) || (SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 == OPCODE(uBuf.TempBuf)) || (SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE == OPCODE(uBuf.TempBuf)))
+ {
+ /* go over the active list if exist to find obj waiting for this Async event */
+ _SlFindAndSetActiveObj(OPCODE(uBuf.TempBuf),(((_SocketResponse_t *)(g_pCB->FunctionParams.AsyncExt.pAsyncBuf + _SL_RESP_HDR_SIZE))->sd) & BSD_SOCKET_ID_MASK);
+ }
+ else
+ {
+ _SlFindAndSetActiveObj(OPCODE(uBuf.TempBuf),SL_MAX_SOCKETS);
+ }
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+
+ break;
+
+ case RECV_RESP_CLASS:
+ {
+ _u8 ExpArgSize; /* Expected size of Recv/Recvfrom arguments */
+
+ switch(OPCODE(uBuf.TempBuf))
+ {
+ case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE:
+ ExpArgSize = RECVFROM_IPV4_ARGS_SIZE;
+ break;
+ case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6:
+ ExpArgSize = RECVFROM_IPV6_ARGS_SIZE;
+ break;
+ default:
+ /* SL_OPCODE_SOCKET_RECVASYNCRESPONSE: */
+ ExpArgSize = RECV_ARGS_SIZE;
+ }
+
+ /* Read first 4 bytes of Recv/Recvfrom response to get SocketId and actual */
+ /* response data length */
+ NWP_IF_READ_CHECK(g_pCB->FD, &uBuf.TempBuf[4], RECV_ARGS_SIZE);
+
+ /* Validate Socket ID and Received Length value. */
+ VERIFY_PROTOCOL((SD(&uBuf.TempBuf[4])& BSD_SOCKET_ID_MASK) < SL_MAX_SOCKETS);
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ /* go over the active list if exist to find obj waiting for this Async event */
+ VERIFY_RET_OK(_SlFindAndSetActiveObj(OPCODE(uBuf.TempBuf),SD(&uBuf.TempBuf[4]) & BSD_SOCKET_ID_MASK));
+
+ /* Verify data is waited on this socket. The pArgs should have been set by _SlDrvDataReadOp(). */
+ VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData))->pArgs);
+
+ sl_Memcpy( ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs, &uBuf.TempBuf[4], RECV_ARGS_SIZE);
+
+ if(ExpArgSize > RECV_ARGS_SIZE)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,
+ ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs + RECV_ARGS_SIZE,
+ ExpArgSize - RECV_ARGS_SIZE);
+ }
+
+ /* Here g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData contains requested(expected) Recv/Recvfrom DataSize. */
+ /* Overwrite requested DataSize with actual one. */
+ /* If error is received, this information will be read from arguments. */
+ if(ACT_DATA_SIZE(&uBuf.TempBuf[4]) > 0)
+ {
+ VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData);
+
+ /* Read 4 bytes aligned from interface */
+ /* therefore check the requested length and read only */
+ /* 4 bytes aligned data. The rest unaligned (if any) will be read */
+ /* and copied to a TailBuffer */
+ LengthToCopy = ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (3);
+ AlignedLengthRecv = ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (~3);
+ if( AlignedLengthRecv >= 4)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData,AlignedLengthRecv );
+ }
+ /* copy the unaligned part, if any */
+ if( LengthToCopy > 0)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4);
+ /* copy TailBuffer unaligned part (1/2/3 bytes) */
+ sl_Memcpy(((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData + AlignedLengthRecv,TailBuffer,LengthToCopy);
+ }
+ }
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj)));
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ }
+ break;
+
+ case CMD_RESP_CLASS:
+
+ /* Some commands pass a maximum arguments size. */
+ /* In this case Driver will send extra dummy patterns to NWP if */
+ /* the response message is smaller than maximum. */
+ /* When RxDescLen is not exact, using RxPayloadLen is forbidden! */
+ /* If such case cannot be avoided - parse message here to detect */
+ /* arguments/payload border. */
+ NWP_IF_READ_CHECK(g_pCB->FD,
+ g_pCB->FunctionParams.pTxRxDescBuff,
+ _SL_PROTOCOL_ALIGN_SIZE(g_pCB->FunctionParams.pCmdCtrl->RxDescLen));
+
+ if((NULL != g_pCB->FunctionParams.pCmdExt) && (0 != g_pCB->FunctionParams.pCmdExt->RxPayloadLen))
+ {
+ /* Actual size of command's response payload: - */
+ _i16 ActDataSize = RSP_PAYLOAD_LEN(uBuf.TempBuf) - g_pCB->FunctionParams.pCmdCtrl->RxDescLen;
+
+ g_pCB->FunctionParams.pCmdExt->ActualRxPayloadLen = ActDataSize;
+
+ /* Check that the space prepared by user for the response data is sufficient. */
+ if(ActDataSize <= 0)
+ {
+ g_pCB->FunctionParams.pCmdExt->RxPayloadLen = 0;
+ }
+ else
+ {
+ /* In case the user supplied Rx buffer length which is smaller then the received data length, copy according to user length */
+ if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen)
+ {
+ LengthToCopy = g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (3);
+ AlignedLengthRecv = g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (~3);
+ }
+ else
+ {
+ LengthToCopy = ActDataSize & (3);
+ AlignedLengthRecv = ActDataSize & (~3);
+ }
+ /* Read 4 bytes aligned from interface */
+ /* therefore check the requested length and read only */
+ /* 4 bytes aligned data. The rest unaligned (if any) will be read */
+ /* and copied to a TailBuffer */
+
+ if( AlignedLengthRecv >= 4)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,
+ g_pCB->FunctionParams.pCmdExt->pRxPayload,
+ AlignedLengthRecv );
+
+ }
+ /* copy the unaligned part, if any */
+ if( LengthToCopy > 0)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4);
+ /* copy TailBuffer unaligned part (1/2/3 bytes) */
+ sl_Memcpy(g_pCB->FunctionParams.pCmdExt->pRxPayload + AlignedLengthRecv,
+ TailBuffer,
+ LengthToCopy);
+ ActDataSize = ActDataSize-4;
+ }
+ /* In case the user supplied Rx buffer length which is smaller then the received data length, dump the rest */
+ if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen)
+ {
+ /* calculate the rest of the data size to dump */
+ AlignedLengthRecv = ActDataSize - (g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (~3));
+ while( AlignedLengthRecv > 0)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer, 4 );
+ AlignedLengthRecv = AlignedLengthRecv - 4;
+ }
+ }
+ }
+ }
+ break;
+
+ default:
+ /* DUMMY_MSG_CLASS: Flow control message has no payload. */
+ break;
+ }
+
+ if(AlignSize > 0)
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD, uBuf.TempBuf, AlignSize);
+ }
+
+ _SL_DBG_CNT_INC(MsgCnt.Read);
+
+ /* Unmask Interrupt call */
+ sl_IfUnMaskIntHdlr();
+
+ return SL_OS_RET_CODE_OK;
+}
+
+/* ******************************************************************************/
+/* _SlAsyncEventGenericHandler */
+/* ******************************************************************************/
+void _SlAsyncEventGenericHandler(void)
+{
+ _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)g_pCB->FunctionParams.AsyncExt.pAsyncBuf;
+ SlWlanEvent_t wlanEvent;
+ SlNetAppEvent_t netAppEvent;
+ SlSockEvent_t sockAppEvent;
+
+ if (NULL != g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler)
+ {
+ switch(pHdr->GenHeader.Opcode)
+ {
+ case SL_OPCODE_WLAN_P2P_DEV_FOUND:
+ {
+ slPeerInfoAsyncResponse_t* pResp = (slPeerInfoAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ wlanEvent.Event = SL_WLAN_P2P_DEV_FOUND_EVENT;
+ sl_Memcpy(wlanEvent.EventData.P2PModeDevFound.mac,pResp->mac, 6);
+ sl_Memcpy(wlanEvent.EventData.P2PModeDevFound.go_peer_device_name,pResp->go_peer_device_name,pResp->go_peer_device_name_len);
+ wlanEvent.EventData.P2PModeDevFound.go_peer_device_name_len = pResp->go_peer_device_name_len;
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ break;
+ }
+
+ case SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED:
+ {
+ slPeerInfoAsyncResponse_t* pResp = (slPeerInfoAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+
+ wlanEvent.Event = SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT;
+ sl_Memcpy(wlanEvent.EventData.P2PModeNegReqReceived.mac,pResp->mac, 6);
+ sl_Memcpy(wlanEvent.EventData.P2PModeNegReqReceived.go_peer_device_name,pResp->go_peer_device_name,pResp->go_peer_device_name_len);
+ wlanEvent.EventData.P2PModeNegReqReceived.go_peer_device_name_len = pResp->go_peer_device_name_len;
+ wlanEvent.EventData.P2PModeNegReqReceived.wps_dev_password_id = pResp->wps_dev_password_id;
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ break;
+ }
+ case SL_OPCODE_WLAN_CONNECTION_FAILED:
+ {
+ slWlanConnFailureAsyncResponse_t * pResp = (slWlanConnFailureAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+
+ wlanEvent.Event = SL_WLAN_CONNECTION_FAILED_EVENT;
+ wlanEvent.EventData.P2PModewlanConnectionFailure.status = pResp->status;
+
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ break;
+ }
+
+ case SL_OPCODE_WLAN_WLANASYNCCONNECTEDRESPONSE:
+ {
+ slWlanConnectAsyncResponse_t *pWlanResp = (slWlanConnectAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ sl_Memset(&wlanEvent.EventData.STAandP2PModeWlanConnected,0,sizeof(slWlanConnectAsyncResponse_t));
+ wlanEvent.Event = SL_WLAN_CONNECT_EVENT;
+ wlanEvent.EventData.STAandP2PModeWlanConnected.connection_type = pWlanResp->connection_type;
+ sl_Memcpy(wlanEvent.EventData.STAandP2PModeWlanConnected.bssid, pWlanResp->bssid, 6);
+ sl_Memcpy(wlanEvent.EventData.STAandP2PModeWlanConnected.go_peer_device_name,pWlanResp->go_peer_device_name,pWlanResp->go_peer_device_name_len);
+ sl_Memcpy(wlanEvent.EventData.STAandP2PModeWlanConnected.ssid_name, pWlanResp->ssid_name, pWlanResp->ssid_len);
+ wlanEvent.EventData.STAandP2PModeWlanConnected.ssid_len = pWlanResp->ssid_len;
+ wlanEvent.EventData.STAandP2PModeWlanConnected.go_peer_device_name_len = pWlanResp->go_peer_device_name_len;
+
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ break;
+ }
+ case SL_OPCODE_WLAN_WLANASYNCDISCONNECTEDRESPONSE:
+ {
+ slWlanConnectAsyncResponse_t *pWlanResp = (slWlanConnectAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ sl_Memset(&wlanEvent.EventData.STAandP2PModeDisconnected,0,sizeof(slWlanConnectAsyncResponse_t));
+ wlanEvent.Event = SL_WLAN_DISCONNECT_EVENT;
+ wlanEvent.EventData.STAandP2PModeDisconnected.connection_type = pWlanResp->connection_type;
+ sl_Memcpy(wlanEvent.EventData.STAandP2PModeDisconnected.bssid, pWlanResp->bssid, 6);
+ sl_Memcpy(wlanEvent.EventData.STAandP2PModeDisconnected.go_peer_device_name,pWlanResp->go_peer_device_name,pWlanResp->go_peer_device_name_len);
+ sl_Memcpy(wlanEvent.EventData.STAandP2PModeDisconnected.ssid_name, pWlanResp->ssid_name, pWlanResp->ssid_len);
+ wlanEvent.EventData.STAandP2PModeDisconnected.ssid_len = pWlanResp->ssid_len;
+ wlanEvent.EventData.STAandP2PModeDisconnected.reason_code = pWlanResp->reason_code;
+ wlanEvent.EventData.STAandP2PModeDisconnected.go_peer_device_name_len = pWlanResp->go_peer_device_name_len;
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ break;
+ }
+ case SL_OPCODE_NETAPP_IPACQUIRED:
+ {
+ SlIpV4AcquiredAsync_t *pIpV4 = (SlIpV4AcquiredAsync_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ netAppEvent.Event = SL_NETAPP_IPV4_IPACQUIRED_EVENT;
+ netAppEvent.EventData.ipAcquiredV4.ip = pIpV4->ip;
+ netAppEvent.EventData.ipAcquiredV4.gateway = pIpV4->gateway;
+ netAppEvent.EventData.ipAcquiredV4.dns = pIpV4->dns;
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&netAppEvent);
+ }
+ break;
+ case SL_OPCODE_NETAPP_IPACQUIRED_V6:
+ {
+ SlIpV6AcquiredAsync_t *pIpV6 = (SlIpV6AcquiredAsync_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ netAppEvent.Event = SL_NETAPP_IPV6_IPACQUIRED_EVENT;
+ sl_Memcpy((void *)&netAppEvent.EventData.ipAcquiredV6.ip[0],(void *)&pIpV6->ip[0],sizeof(pIpV6->ip[0])*4);
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&netAppEvent);
+ }
+ break;
+
+ case SL_OPCODE_NETAPP_IP_LEASED:
+ {
+ SlIpLeasedAsync_t *pIpV4 = (SlIpLeasedAsync_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ netAppEvent.Event = SL_NETAPP_IP_LEASED_EVENT;
+ netAppEvent.EventData.ipLeased.ip_address = pIpV4->ip_address;
+ netAppEvent.EventData.ipLeased.lease_time = pIpV4->lease_time;
+ sl_Memcpy(netAppEvent.EventData.ipLeased.mac, pIpV4->mac, 6);
+
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&netAppEvent);
+ }
+ break;
+
+ case SL_OPCODE_NETAPP_IP_RELEASED:
+ {
+ SlIpReleasedAsync_t *pIpV4 = (SlIpReleasedAsync_t *)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ netAppEvent.Event = SL_NETAPP_IP_RELEASED_EVENT;
+ netAppEvent.EventData.ipReleased.ip_address = pIpV4->ip_address;
+ netAppEvent.EventData.ipReleased.reason = pIpV4->reason;
+ sl_Memcpy(netAppEvent.EventData.ipReleased.mac, pIpV4->mac, 6);
+
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&netAppEvent);
+ }
+ break;
+
+ case SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE:
+ {
+ SlSockEventData_t *txfailparams = (SlSockEventData_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ sockAppEvent.Event = SL_SOCKET_TX_FAILED_EVENT;
+ sl_Memcpy((void *)&sockAppEvent.EventData,(void *)txfailparams,sizeof(SlSockEventData_t));
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&sockAppEvent);
+ }
+ break;
+
+ case SL_OPCODE_SOCKET_SOCKETASYNCEVENT:
+ {
+ SlSockEventData_t *socketAsyncEvent = (SlSockEventData_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ sockAppEvent.Event = SL_SOCKET_ASYNC_EVENT;
+ sockAppEvent.EventData.socketAsyncEvent.sd = socketAsyncEvent->socketAsyncEvent.sd;
+ sockAppEvent.EventData.socketAsyncEvent.type = socketAsyncEvent->socketAsyncEvent.type; /* one of the possible types of socket */
+ sockAppEvent.EventData.socketAsyncEvent.val = socketAsyncEvent->socketAsyncEvent.val;
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&sockAppEvent);
+ }
+ break;
+
+ case SL_OPCODE_WLAN_SMART_CONFIG_START_ASYNC_RESPONSE:
+ {
+ slSmartConfigStartAsyncResponse_t *pResp = (slSmartConfigStartAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+
+ wlanEvent.Event = SL_WLAN_SMART_CONFIG_COMPLETE_EVENT;
+ wlanEvent.EventData.smartConfigStartResponse.status = pResp->status;
+ wlanEvent.EventData.smartConfigStartResponse.ssid_len = pResp->ssid_len;
+ wlanEvent.EventData.smartConfigStartResponse.private_token_len = pResp->private_token_len;
+
+ sl_Memset(wlanEvent.EventData.smartConfigStartResponse.ssid, 0x00, sizeof(wlanEvent.EventData.smartConfigStartResponse.ssid));
+ sl_Memcpy(wlanEvent.EventData.smartConfigStartResponse.ssid, pResp->ssid, pResp->ssid_len);
+ /* if private data exist */
+ if (pResp->private_token_len)
+ {
+ sl_Memset(wlanEvent.EventData.smartConfigStartResponse.private_token, 0x00, sizeof(wlanEvent.EventData.smartConfigStartResponse.private_token));
+ sl_Memcpy(wlanEvent.EventData.smartConfigStartResponse.private_token, pResp->private_token, pResp->private_token_len);
+ }
+
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ }
+ break;
+
+ case SL_OPCODE_WLAN_SMART_CONFIG_STOP_ASYNC_RESPONSE:
+ {
+ slSmartConfigStopAsyncResponse_t *pResp = (slSmartConfigStopAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+
+ wlanEvent.Event = SL_WLAN_SMART_CONFIG_STOP_EVENT;
+ wlanEvent.EventData.smartConfigStopResponse.status = pResp->status;
+
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ }
+ break;
+
+ case SL_OPCODE_WLAN_STA_CONNECTED:
+ {
+ slPeerInfoAsyncResponse_t* pResp = (slPeerInfoAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ sl_Memset(&wlanEvent.EventData.APModeStaConnected,0,sizeof(slPeerInfoAsyncResponse_t));
+ wlanEvent.Event = SL_WLAN_STA_CONNECTED_EVENT;
+ sl_Memcpy(wlanEvent.EventData.APModeStaConnected.mac,pResp->mac, 6);
+ sl_Memcpy(wlanEvent.EventData.APModeStaConnected.go_peer_device_name,pResp->go_peer_device_name,pResp->go_peer_device_name_len);
+ wlanEvent.EventData.APModeStaConnected.go_peer_device_name_len = pResp->go_peer_device_name_len;
+
+ sl_Memcpy(wlanEvent.EventData.APModeStaConnected.own_ssid,pResp->own_ssid,pResp->own_ssid_len);
+ wlanEvent.EventData.APModeStaConnected.own_ssid_len = pResp->own_ssid_len;
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ }
+ break;
+
+ case SL_OPCODE_WLAN_STA_DISCONNECTED:
+ {
+ slPeerInfoAsyncResponse_t* pResp = (slPeerInfoAsyncResponse_t*)_SL_RESP_ARGS_START(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ sl_Memset(&wlanEvent.EventData.APModestaDisconnected,0,sizeof(slPeerInfoAsyncResponse_t));
+ wlanEvent.Event = SL_WLAN_STA_DISCONNECTED_EVENT;
+ sl_Memcpy(wlanEvent.EventData.APModestaDisconnected.mac,pResp->mac, 6);
+ sl_Memcpy(wlanEvent.EventData.APModestaDisconnected.go_peer_device_name,pResp->go_peer_device_name,pResp->go_peer_device_name_len);
+ wlanEvent.EventData.APModestaDisconnected.go_peer_device_name_len = pResp->go_peer_device_name_len;
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&wlanEvent);
+ }
+ break;
+
+ case SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE:
+ {
+ _sl_HandleAsync_PingResponse((void *)g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ }
+ break;
+
+
+ default:
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+ break;
+ }
+ }
+}
+
+
+/* ******************************************************************************/
+/* _SlDrvMsgReadCmdCtx */
+/* ******************************************************************************/
+_SlReturnVal_t _SlDrvMsgReadCmdCtx(void)
+{
+
+ /* after command response is received and isCmdRespWaited */
+ /* flag is set FALSE, it is necessary to read out all */
+ /* Async messages in Commands context, because ssiDma_IsrHandleSignalFromSlave */
+ /* could have dispatched some Async messages to g_NwpIf.CmdSyncObj */
+ /* after command response but before this response has been processed */
+ /* by spi_singleRead and isCmdRespWaited was set FALSE. */
+ while (TRUE == g_pCB->IsCmdRespWaited)
+ {
+ if(_SL_PENDING_RX_MSG(g_pCB))
+ {
+ g_pCB->FunctionParams.AsyncExt.pAsyncBuf = NULL;/* buffer must be allocated by _SlDrvMsgRead */
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler= NULL;
+ g_pCB->FunctionParams.AsyncExt.RxMsgClass = (_SlRxMsgClass_e)(-1);/* init to illegal value and verify it's overwritten with the valid one */
+
+ VERIFY_RET_OK(_SlDrvMsgRead());
+ g_pCB->RxDoneCnt++;
+
+ if (CMD_RESP_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass)
+ {
+ g_pCB->IsCmdRespWaited = FALSE;
+
+ /* In case CmdResp has been read without waiting on CmdSyncObj - that */
+ /* Sync object. That to prevent old signal to be processed. */
+ sl_SyncObjClear(&g_pCB->CmdSyncObj);
+ }
+ else if (ASYNC_EVT_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass)
+ {
+ /* If Async event has been read in CmdResp context, check whether */
+ /* there is a handler for this event. If there is, spawn specific */
+ /* handler. Otherwise free the event's buffer. */
+ /* This way there will be no "dry shots" from CmdResp context to */
+ /* temporary context, i.e less waste of CPU and faster buffer */
+ /* release. */
+ _SlAsyncEventGenericHandler();
+
+#if (SL_MEMORY_MGMT == SL_MEMORY_MGMT_STATIC)
+ g_pCB->FunctionParams.AsyncExt.pAsyncBuf = NULL;
+#else
+ sl_Free(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+#endif
+ }
+ }
+ else
+ {
+ /* CmdSyncObj will be signaled by IRQ */
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->CmdSyncObj, SL_OS_WAIT_FOREVER));
+ }
+ }
+
+ /* If there are more pending Rx Msgs after CmdResp is received, */
+ /* that means that these are Async, Dummy or Read Data Msgs. */
+ /* Spawn _SlDrvMsgReadSpawnCtx to trigger reading these messages from */
+ /* Temporary context. */
+ /* sl_Spawn is activated, using a different context */
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->GlobalLockObj));
+ if(_SL_PENDING_RX_MSG(g_pCB))
+ {
+ sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, 0);
+ }
+
+ return SL_OS_RET_CODE_OK;
+}
+
+/* ******************************************************************************/
+/* _SlDrvMsgReadSpawnCtx */
+/* ******************************************************************************/
+_SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue)
+{
+#ifdef SL_POLLING_MODE_USED
+ _i16 retCode = OSI_OK;
+ /* for polling based systems */
+ do
+ {
+ retCode = sl_LockObjLock(&g_pCB->GlobalLockObj, 0);
+ if ( OSI_OK != retCode )
+ {
+ if (TRUE == g_pCB->IsCmdRespWaited)
+ {
+ OSI_RET_OK_CHECK( sl_SyncObjSignal(&g_pCB->CmdSyncObj) );
+ return SL_RET_CODE_OK;
+ }
+ }
+
+ }
+ while (OSI_OK != retCode);
+
+#else
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->GlobalLockObj, SL_OS_WAIT_FOREVER) );
+#endif
+
+ g_pCB->FunctionParams.AsyncExt.pAsyncBuf = NULL;/* buffer must be allocated by _SlDrvMsgRead */
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler= NULL;
+ g_pCB->FunctionParams.AsyncExt.RxMsgClass = CMD_RESP_CLASS;/* init to illegal value and verify it's overwritten with the valid one */
+
+ /* Messages might have been read by CmdResp context. Therefore after */
+ /* getting LockObj, check again where the Pending Rx Msg is still present. */
+ if(FALSE == (_SL_PENDING_RX_MSG(g_pCB)))
+ {
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->GlobalLockObj));
+ return SL_RET_CODE_OK;
+ }
+
+ VERIFY_RET_OK(_SlDrvMsgRead());
+
+ g_pCB->RxDoneCnt++;
+
+ switch(g_pCB->FunctionParams.AsyncExt.RxMsgClass)
+ {
+ case ASYNC_EVT_CLASS:
+ /* If got here and protected by LockObj a message is waiting */
+ /* to be read */
+ VERIFY_PROTOCOL(NULL != g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+
+ _SlAsyncEventGenericHandler();
+
+#if (SL_MEMORY_MGMT == SL_MEMORY_MGMT_STATIC)
+ g_pCB->FunctionParams.AsyncExt.pAsyncBuf = NULL;
+#else
+ sl_Free(g_pCB->FunctionParams.AsyncExt.pAsyncBuf);
+#endif
+ break;
+ case DUMMY_MSG_CLASS:
+ case RECV_RESP_CLASS:
+ /* These types are legal in this context. Do nothing */
+ break;
+ case CMD_RESP_CLASS:
+ /* Command response is illegal in this context. */
+ /* No 'break' here: Assert! */
+ default:
+ VERIFY_PROTOCOL(0);
+ }
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->GlobalLockObj));
+
+ return(SL_RET_CODE_OK);
+}
+
+/* ******************************************************************************/
+/* _SlDrvClassifyRxMsg */
+/* ******************************************************************************/
+void _SlDrvClassifyRxMsg(
+ _SlOpcode_t Opcode)
+{
+
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = NULL;
+
+ /* Async event has received */
+ if (0 == (SL_OPCODE_SYNC & Opcode))
+ {
+ if (SL_OPCODE_DEVICE_DEVICEASYNCDUMMY == Opcode)
+ {
+ g_pCB->FunctionParams.AsyncExt.RxMsgClass = DUMMY_MSG_CLASS;
+ }
+ else if ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode) )
+ {
+ g_pCB->FunctionParams.AsyncExt.RxMsgClass = RECV_RESP_CLASS;
+ }
+ else
+ {
+ g_pCB->FunctionParams.AsyncExt.RxMsgClass = ASYNC_EVT_CLASS;
+
+ /* set silo handler */
+ if (SL_OPCODE_SILO_DEVICE == (Opcode & SL_OPCODE_SILO_MASK))
+ {
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = _SlDrvDeviceEventHandler;
+ }
+ else if (SL_OPCODE_SILO_WLAN == (Opcode & SL_OPCODE_SILO_MASK))
+ {
+#ifdef sl_WlanEvtHdlr
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = (_SlSpawnEntryFunc_t)sl_WlanEvtHdlr;
+#endif
+ }
+ else if (SL_OPCODE_SILO_SOCKET == (Opcode & SL_OPCODE_SILO_MASK))
+ {
+
+#ifdef sl_SockEvtHdlr
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = (_SlSpawnEntryFunc_t)sl_SockEvtHdlr;
+#endif
+ }
+ else if (SL_OPCODE_SILO_NETAPP == (Opcode & SL_OPCODE_SILO_MASK))
+ {
+
+ if ((SL_OPCODE_NETAPP_HTTPGETTOKENVALUE == Opcode) || (SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE == Opcode))
+ {
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = _SlDrvNetAppEventHandler;
+ }
+#ifdef sl_NetAppEvtHdlr
+ else
+ {
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = (_SlSpawnEntryFunc_t)sl_NetAppEvtHdlr;
+ }
+#endif
+ }
+ /* else if (SL_OPCODE_SILO_NVMEM == (Opcode & SL_OPCODE_SILO_MASK)) */
+ /* { */
+ /* } */
+ /* else if (SL_OPCODE_SILO_NETCFG == (Opcode & SL_OPCODE_SILO_MASK)) */
+ /* { */
+ /* } */
+ else
+ {
+ SL_ERROR_TRACE1(MSG_311, "ASSERT: _SlDrvClassifyRxMsg : invalid opcode = 0x%x", Opcode);
+ }
+ }
+ }
+ else
+ {
+ /* These may be Command responses only */
+ g_pCB->FunctionParams.AsyncExt.RxMsgClass = CMD_RESP_CLASS;
+ }
+
+}
+
+/* ******************************************************************************/
+/* _SlDrvShiftDWord */
+/* ******************************************************************************/
+void _SlDrvShiftDWord(_u8 *pBuf)
+{
+ _u8 ShiftIdx;
+ for(ShiftIdx = 0; ShiftIdx< 7; ShiftIdx++)
+ {
+ pBuf[ShiftIdx] = pBuf[ShiftIdx+1];
+ }
+ pBuf[7] = 0;
+}
+
+/* ******************************************************************************/
+/* _SlDrvRxHdrRead */
+/* ******************************************************************************/
+_SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf, _u8 *pAlignSize)
+{
+ _u32 SyncCnt = 0;
+
+#ifndef SL_IF_TYPE_UART
+ /* 1. Write CNYS pattern to NWP when working in SPI mode only */
+ NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NCnysPattern.Short, SYNC_PATTERN_LEN);
+#endif
+
+ /* 2. Read 4 bytes (protocol aligned) */
+ NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], 4);
+ _SL_DBG_SYNC_LOG(SyncCnt,pBuf);
+
+ /* Wait for SYNC_PATTERN_LEN from the device */
+ while ( ! N2H_SYNC_PATTERN_MATCH(pBuf, g_pCB->TxSeqNum) )
+ {
+ /* 3. Debug limit of scan */
+ VERIFY_PROTOCOL(SyncCnt < SL_SYNC_SCAN_THRESHOLD);
+
+ /* 4. Read next 4 bytes to Low 4 bytes of buffer */
+ if(0 == (SyncCnt % (_u32)SYNC_PATTERN_LEN))
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[4], 4);
+ _SL_DBG_SYNC_LOG(SyncCnt,pBuf);
+ }
+
+ /* 5. Shift Buffer Up for checking if the sync is shifted */
+ _SlDrvShiftDWord(pBuf);
+
+ SyncCnt++;
+ }
+
+ /* 5. Sync pattern found. If needed, complete number of read bytes to multiple of 4 (protocol align) */
+ SyncCnt %= SYNC_PATTERN_LEN;
+
+ if(SyncCnt > 0)
+ {
+ *(_u32 *)&pBuf[0] = *(_u32 *)&pBuf[4];
+ NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN - SyncCnt], (_u16)SyncCnt);
+ }
+ else
+ {
+ NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], 4);
+ }
+
+ /* 6. Scan for Double pattern. */
+ while ( N2H_SYNC_PATTERN_MATCH(pBuf, g_pCB->TxSeqNum) )
+ {
+ _SL_DBG_CNT_INC(Work.DoubleSyncPattern);
+ NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], SYNC_PATTERN_LEN);
+ }
+ g_pCB->TxSeqNum++;
+
+ /* 7. Here we've read Generic Header (4 bytes). Read the Resp Specific header (4 more bytes). */
+ NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN], _SL_RESP_SPEC_HDR_SIZE);
+
+ /* 8. Here we've read the entire Resp Header. */
+ /* Return number bytes needed to be sent after read for NWP Rx 4-byte alignment (protocol alignment) */
+ *pAlignSize = (_u8)((SyncCnt > 0) ? (SYNC_PATTERN_LEN - SyncCnt) : 0);
+
+ return SL_RET_CODE_OK;
+}
+
+/* ***************************************************************************** */
+/* _SlDrvBasicCmd */
+/* ***************************************************************************** */
+typedef union
+{
+ _BasicResponse_t Rsp;
+}_SlBasicCmdMsg_u;
+
+_i16 _SlDrvBasicCmd(_SlOpcode_t Opcode)
+{
+ _SlBasicCmdMsg_u Msg = {{0, 0}};
+ _SlCmdCtrl_t CmdCtrl;
+
+ CmdCtrl.Opcode = Opcode;
+ CmdCtrl.TxDescLen = 0;
+ CmdCtrl.RxDescLen = sizeof(_BasicResponse_t);
+
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+}
+
+/* ***************************************************************************** */
+/* _SlDrvWaitForPoolObj */
+/* ***************************************************************************** */
+_i16 _SlDrvWaitForPoolObj(_u32 ActionID, _u8 SocketID)
+{
+ _u8 CurrObjIndex = MAX_CONCURRENT_ACTIONS;
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ /* Get free object */
+ if (MAX_CONCURRENT_ACTIONS > g_pCB->FreePoolIdx)
+ {
+ /* save the current obj index */
+ CurrObjIndex = g_pCB->FreePoolIdx;
+ /* set the new free index */
+ if (MAX_CONCURRENT_ACTIONS > g_pCB->ObjPool[CurrObjIndex].NextIndex)
+ {
+ g_pCB->FreePoolIdx = g_pCB->ObjPool[CurrObjIndex].NextIndex;
+ }
+ else
+ {
+ /* No further free actions available */
+ g_pCB->FreePoolIdx = MAX_CONCURRENT_ACTIONS;
+ }
+ }
+ else
+ {
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ return CurrObjIndex;
+ }
+ g_pCB->ObjPool[CurrObjIndex].ActionID = (_u8)ActionID;
+ if (SL_MAX_SOCKETS > SocketID)
+ {
+ g_pCB->ObjPool[CurrObjIndex].AdditionalData = SocketID;
+ }
+ /*In case this action is socket related, SocketID bit will be on
+ In case SocketID is set to SL_MAX_SOCKETS, the socket is not relevant to the action. In that case ActionID bit will be on */
+ while ( ( (SL_MAX_SOCKETS > SocketID) && (g_pCB->ActiveActionsBitmap & (1<ActiveActionsBitmap & (1<ObjPool[CurrObjIndex].NextIndex = g_pCB->PendingPoolIdx;
+ g_pCB->PendingPoolIdx = CurrObjIndex;
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ //wait for action to be free
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[CurrObjIndex].SyncObj, SL_OS_WAIT_FOREVER));
+ //set params and move to active (remove from pending list at _SlDrvReleasePoolObj)
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+ }
+ /*mark as active. Set socket as active if action is on socket, otherwise mark action as active*/
+ if (SL_MAX_SOCKETS > SocketID)
+ {
+ g_pCB->ActiveActionsBitmap |= (1<ActiveActionsBitmap |= (1<ObjPool[CurrObjIndex].NextIndex = g_pCB->ActivePoolIdx;
+ g_pCB->ActivePoolIdx = CurrObjIndex;
+ /* unlock */
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ return CurrObjIndex;
+}
+
+/* ******************************************************************************/
+/* _SlDrvReleasePoolObj */
+/* ******************************************************************************/
+void _SlDrvReleasePoolObj(_u8 ObjIdx)
+{
+ _u8 PendingIndex;
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ /* go over the pending list and release other pending action if needed */
+ PendingIndex = g_pCB->PendingPoolIdx;
+ while(MAX_CONCURRENT_ACTIONS > PendingIndex)
+ {
+ /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */
+ if ( (g_pCB->ObjPool[PendingIndex].ActionID == g_pCB->ObjPool[ObjIdx].ActionID) &&
+ ( (SL_MAX_SOCKETS == (g_pCB->ObjPool[PendingIndex].AdditionalData & BSD_SOCKET_ID_MASK)) ||
+ ((SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & BSD_SOCKET_ID_MASK)) && ( (g_pCB->ObjPool[PendingIndex].AdditionalData & BSD_SOCKET_ID_MASK) == (g_pCB->ObjPool[ObjIdx].AdditionalData & BSD_SOCKET_ID_MASK) ))) )
+ {
+ /* remove from pending list */
+ _SlRemoveFromList(&g_pCB->PendingPoolIdx, PendingIndex);
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&(g_pCB->ObjPool[PendingIndex].SyncObj)));
+ break;
+ }
+ PendingIndex = g_pCB->ObjPool[PendingIndex].NextIndex;
+ }
+
+ if (SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & BSD_SOCKET_ID_MASK))
+ {
+ /* unset socketID */
+ g_pCB->ActiveActionsBitmap &= ~(1<<(g_pCB->ObjPool[ObjIdx].AdditionalData & BSD_SOCKET_ID_MASK));
+ }
+ else
+ {
+ /* unset actionID */
+ g_pCB->ActiveActionsBitmap &= ~(1<ObjPool[ObjIdx].ActionID);
+ }
+
+ /* delete old data */
+ g_pCB->ObjPool[ObjIdx].pRespArgs = NULL;
+ g_pCB->ObjPool[ObjIdx].ActionID = 0;
+ g_pCB->ObjPool[ObjIdx].AdditionalData = SL_MAX_SOCKETS;
+
+ /* remove from active list */
+ _SlRemoveFromList(&g_pCB->ActivePoolIdx, ObjIdx);
+ /* move to free list */
+ g_pCB->ObjPool[ObjIdx].NextIndex = g_pCB->FreePoolIdx;
+ g_pCB->FreePoolIdx = ObjIdx;
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+}
+
+
+
+/* ******************************************************************************/
+/* _SlDrvObjInit */
+/* ******************************************************************************/
+void _SlDrvObjInit(void)
+{
+ _u8 Idx;
+
+ sl_Memset(&g_pCB->ObjPool[0],0,MAX_CONCURRENT_ACTIONS*sizeof(_SlPoolObj_t));
+ /* place all Obj in the free list */
+ g_pCB->FreePoolIdx = 0;
+ for (Idx = 0 ; Idx < MAX_CONCURRENT_ACTIONS ; Idx++)
+ {
+ g_pCB->ObjPool[Idx].NextIndex = Idx + 1;
+ g_pCB->ObjPool[Idx].AdditionalData = SL_MAX_SOCKETS;
+ }
+
+ g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS;
+ g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS;
+
+}
+
+/* ******************************************************************************/
+/* _SlDrvObjDeInit */
+/* ******************************************************************************/
+void _SlDrvObjDeInit(void)
+{
+ g_pCB->FreePoolIdx = 0;
+ g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS;
+ g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS;
+
+}
+
+/* ******************************************************************************/
+/* _SlRemoveFromList */
+/* ******************************************************************************/
+void _SlRemoveFromList(_u8 *ListIndex, _u8 ItemIndex)
+{
+ _u8 Idx;
+ /* only one item in the list */
+ if (MAX_CONCURRENT_ACTIONS == g_pCB->ObjPool[*ListIndex].NextIndex)
+ {
+ *ListIndex = MAX_CONCURRENT_ACTIONS;
+ }
+ /* need to remove the first item in the list and therefore update the global which holds this index */
+ else if (*ListIndex == ItemIndex)
+ {
+ *ListIndex = g_pCB->ObjPool[ItemIndex].NextIndex;
+ }
+ else
+ {
+ Idx = *ListIndex;
+ while(MAX_CONCURRENT_ACTIONS > Idx)
+ {
+ /* remove from list */
+ if (g_pCB->ObjPool[Idx].NextIndex == ItemIndex)
+ {
+ g_pCB->ObjPool[Idx].NextIndex = g_pCB->ObjPool[ItemIndex].NextIndex;
+ break;
+ }
+ Idx = g_pCB->ObjPool[Idx].NextIndex;
+ }
+ }
+}
+
+
+/* ******************************************************************************/
+/* _SlFindAndSetActiveObj */
+/* ******************************************************************************/
+_SlReturnVal_t _SlFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd)
+{
+ _u8 ActiveIndex;
+
+ ActiveIndex = g_pCB->ActivePoolIdx;
+ /* go over the active list if exist to find obj waiting for this Async event */
+ while (MAX_CONCURRENT_ACTIONS > ActiveIndex)
+ {
+ /* unset the Ipv4\IPv6 bit in the opcode if family bit was set */
+ if (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_NETAPP_FAMILY_MASK)
+ {
+ Opcode &= ~SL_OPCODE_IPV6;
+ }
+
+ if ((g_pCB->ObjPool[ActiveIndex].ActionID == RECV_ID) && (Sd == g_pCB->ObjPool[ActiveIndex].AdditionalData) &&
+ ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode) ) )
+ {
+ g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex;
+ return SL_RET_CODE_OK;
+ }
+ /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */
+ if ( (_SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].ActionAsyncOpcode == Opcode) &&
+ ( ((Sd == (g_pCB->ObjPool[ActiveIndex].AdditionalData & BSD_SOCKET_ID_MASK) ) && (SL_MAX_SOCKETS > Sd)) || (SL_MAX_SOCKETS == (g_pCB->ObjPool[ActiveIndex].AdditionalData & BSD_SOCKET_ID_MASK)) ) )
+ {
+ /* set handler */
+ g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = _SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].AsyncEventHandler;
+ g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex;
+ return SL_RET_CODE_OK;
+ }
+ ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex;
+ }
+
+ return SL_RET_CODE_SELF_ERROR;
+}
diff --git a/cc3200/simplelink/source/driver.h b/cc3200/simplelink/source/driver.h
new file mode 100644
index 0000000000..9aa3b729a2
--- /dev/null
+++ b/cc3200/simplelink/source/driver.h
@@ -0,0 +1,220 @@
+/*
+ * driver.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __DRIVER_INT_H__
+#define __DRIVER_INT_H__
+
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+
+#ifndef CPU_FREQ_IN_MHZ
+ #define CPU_FREQ_IN_MHZ (200)
+#endif
+#define USEC_DELAY (50)
+
+/*****************************************************************************/
+/* Structure/Enum declarations */
+/*****************************************************************************/
+
+typedef struct
+{
+ _SlOpcode_t Opcode;
+ _SlArgSize_t TxDescLen;
+ _SlArgSize_t RxDescLen;
+}_SlCmdCtrl_t;
+
+typedef struct
+{
+ _u16 TxPayloadLen;
+ _u16 RxPayloadLen;
+ _u16 ActualRxPayloadLen;
+ _u8 *pTxPayload;
+ _u8 *pRxPayload;
+}_SlCmdExt_t;
+
+
+typedef struct _SlArgsData_t
+{
+ _u8 *pArgs;
+ _u8 *pData;
+} _SlArgsData_t;
+
+
+typedef struct _SlPoolObj_t
+{
+ _SlSyncObj_t SyncObj;
+ _u8 *pRespArgs;
+ _u8 ActionID;
+ _u8 AdditionalData; /* use for socketID and one bit which indicate supprt IPV6 or not (1=support, 0 otherwise) */
+ _u8 NextIndex;
+
+} _SlPoolObj_t;
+
+
+typedef enum
+{
+ SOCKET_0,
+ SOCKET_1,
+ SOCKET_2,
+ SOCKET_3,
+ SOCKET_4,
+ SOCKET_5,
+ SOCKET_6,
+ SOCKET_7,
+ MAX_SOCKET_ENUM_IDX,
+ ACCEPT_ID = MAX_SOCKET_ENUM_IDX,
+ CONNECT_ID,
+ SELECT_ID,
+ GETHOSYBYNAME_ID,
+ GETHOSYBYSERVICE_ID,
+ PING_ID,
+ START_STOP_ID,
+ RECV_ID
+}_SlActionID_e;
+
+typedef struct _SlActionLookup_t
+{
+ _u8 ActionID;
+ _u16 ActionAsyncOpcode;
+ _SlSpawnEntryFunc_t AsyncEventHandler;
+
+} _SlActionLookup_t;
+
+
+typedef struct
+{
+ _u8 TxPoolCnt;
+ _SlLockObj_t TxLockObj;
+ _SlSyncObj_t TxSyncObj;
+}_SlFlowContCB_t;
+
+typedef enum
+{
+ RECV_RESP_CLASS,
+ CMD_RESP_CLASS,
+ ASYNC_EVT_CLASS,
+ DUMMY_MSG_CLASS
+}_SlRxMsgClass_e;
+
+typedef struct
+{
+ _u8 *pAsyncBuf; /* place to write pointer to buffer with CmdResp's Header + Arguments */
+ _u8 ActionIndex;
+ _SlSpawnEntryFunc_t AsyncEvtHandler; /* place to write pointer to AsyncEvent handler (calc-ed by Opcode) */
+ _SlRxMsgClass_e RxMsgClass; /* type of Rx message */
+} AsyncExt_t;
+
+typedef _u8 _SlSd_t;
+
+typedef struct
+{
+ _SlCmdCtrl_t *pCmdCtrl;
+ _u8 *pTxRxDescBuff;
+ _SlCmdExt_t *pCmdExt;
+ AsyncExt_t AsyncExt;
+}_SlFunctionParams_t;
+
+
+typedef struct
+{
+ _SlFd_t FD;
+ _SlLockObj_t GlobalLockObj;
+ _SlCommandHeader_t TempProtocolHeader;
+ P_INIT_CALLBACK pInitCallback;
+
+ _SlPoolObj_t ObjPool[MAX_CONCURRENT_ACTIONS];
+ _u8 FreePoolIdx;
+ _u8 PendingPoolIdx;
+ _u8 ActivePoolIdx;
+ _u32 ActiveActionsBitmap;
+ _SlLockObj_t ProtectionLockObj;
+
+ _SlSyncObj_t CmdSyncObj;
+ _u8 IsCmdRespWaited;
+
+ _SlFlowContCB_t FlowContCB;
+
+ _u8 TxSeqNum;
+ _volatile _u8 RxIrqCnt;
+ _u8 RxDoneCnt;
+ _u8 SocketNonBlocking;
+ _u8 SocketTXFailure;
+ _u8 RelayFlagsViaRxPayload;
+ /* for stack reduction the parameters are globals */
+ _SlFunctionParams_t FunctionParams;
+
+}_SlDriverCb_t;
+
+
+
+extern _SlDriverCb_t* g_pCB;
+extern P_SL_DEV_PING_CALLBACK pPingCallBackFunc;
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+extern void _SlDrvDriverCBInit(void);
+extern void _SlDrvDriverCBDeinit(void);
+extern void _SlDrvRxIrqHandler(void *pValue);
+extern _SlReturnVal_t _SlDrvCmdOp(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt);
+extern _SlReturnVal_t _SlDrvCmdSend(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt);
+extern _SlReturnVal_t _SlDrvDataReadOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt);
+extern _SlReturnVal_t _SlDrvDataWriteOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt);
+extern _i16 _SlDrvBasicCmd(_SlOpcode_t Opcode);
+
+extern void _sl_HandleAsync_InitComplete(void *pVoidBuf);
+extern void _sl_HandleAsync_Connect(void *pVoidBuf);
+extern void _sl_HandleAsync_Accept(void *pVoidBuf);
+extern void _sl_HandleAsync_Select(void *pVoidBuf);
+extern void _sl_HandleAsync_DnsGetHostByName(void *pVoidBuf);
+extern void _sl_HandleAsync_DnsGetHostByService(void *pVoidBuf);
+extern void _sl_HandleAsync_DnsGetHostByAddr(void *pVoidBuf);
+extern void _sl_HandleAsync_PingResponse(void *pVoidBuf);
+extern void _SlDrvNetAppEventHandler(void *pArgs);
+extern void _SlDrvDeviceEventHandler(void *pArgs);
+extern void _sl_HandleAsync_Stop(void *pVoidBuf);
+extern _i16 _SlDrvWaitForPoolObj(_u32 ActionID, _u8 SocketID);
+extern void _SlDrvReleasePoolObj(_u8 pObj);
+extern void _SlDrvObjInit(void);
+
+#define _SL_PROTOCOL_ALIGN_SIZE(msgLen) (((msgLen)+3) & (~3))
+#define _SL_IS_PROTOCOL_ALIGNED_SIZE(msgLen) (!((msgLen) & 3))
+#define _SL_PROTOCOL_CALC_LEN(pCmdCtrl,pCmdExt) ((pCmdExt) ? \
+ (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen) + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayloadLen)) : \
+ (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen)))
+#endif /* __DRIVER_INT_H__ */
diff --git a/cc3200/simplelink/source/flowcont.c b/cc3200/simplelink/source/flowcont.c
new file mode 100644
index 0000000000..889241ea2b
--- /dev/null
+++ b/cc3200/simplelink/source/flowcont.c
@@ -0,0 +1,71 @@
+/*
+ * flowcont.c - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+#include "flowcont.h"
+
+
+/*****************************************************************************/
+/* _SlDrvFlowContInit */
+/*****************************************************************************/
+void _SlDrvFlowContInit(void)
+{
+ g_pCB->FlowContCB.TxPoolCnt = FLOW_CONT_MIN;
+
+ OSI_RET_OK_CHECK(sl_LockObjCreate(&g_pCB->FlowContCB.TxLockObj, "TxLockObj"));
+
+ OSI_RET_OK_CHECK(sl_SyncObjCreate(&g_pCB->FlowContCB.TxSyncObj, "TxSyncObj"));
+}
+
+/*****************************************************************************/
+/* _SlDrvFlowContDeinit */
+/*****************************************************************************/
+void _SlDrvFlowContDeinit(void)
+{
+ g_pCB->FlowContCB.TxPoolCnt = 0;
+
+ OSI_RET_OK_CHECK(sl_LockObjDelete(&g_pCB->FlowContCB.TxLockObj));
+
+ OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->FlowContCB.TxSyncObj));
+}
+
diff --git a/cc3200/simplelink/source/flowcont.h b/cc3200/simplelink/source/flowcont.h
new file mode 100644
index 0000000000..3dcc130d83
--- /dev/null
+++ b/cc3200/simplelink/source/flowcont.h
@@ -0,0 +1,61 @@
+/*
+ * flowcont.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __FLOWCONT_H__
+#define __FLOWCONT_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+#define FLOW_CONT_MIN 1
+
+/*****************************************************************************/
+/* Function prototypes */
+/*****************************************************************************/
+extern void _SlDrvFlowContInit(void);
+extern void _SlDrvFlowContDeinit(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __FLOWCONT_H__ */
+
diff --git a/cc3200/simplelink/source/fs.c b/cc3200/simplelink/source/fs.c
new file mode 100644
index 0000000000..cc44e262ea
--- /dev/null
+++ b/cc3200/simplelink/source/fs.c
@@ -0,0 +1,415 @@
+/*
+ * fs.c - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+#define sl_min(a,b) (((a) < (b)) ? (a) : (b))
+#define MAX_NVMEM_CHUNK_SIZE 1460
+
+/*****************************************************************************/
+/* Internal functions */
+/*****************************************************************************/
+
+
+/*****************************************************************************/
+/* _sl_Strlen */
+/*****************************************************************************/
+_u16 _sl_Strlen(const _u8 *buffer)
+{
+ _u16 len = 0;
+ if( buffer != NULL )
+ {
+ while(*buffer++) len++;
+ }
+ return len;
+}
+
+/*****************************************************************************/
+/* _sl_GetCreateFsMode */
+/*****************************************************************************/
+_u32 _sl_GetCreateFsMode(_u32 maxSizeInBytes,_u32 accessFlags)
+{
+ _u32 granIdx = 0;
+ _u32 granNum = 0;
+ _u32 granTable[_FS_MAX_MODE_SIZE_GRAN] = {256,1024,4096,16384,65536};
+ for(granIdx= _FS_MODE_SIZE_GRAN_256B ;granIdx< _FS_MAX_MODE_SIZE_GRAN;granIdx++)
+ {
+ if( granTable[granIdx]*255 >= maxSizeInBytes )
+ break;
+ }
+ granNum = maxSizeInBytes/granTable[granIdx];
+ if( maxSizeInBytes % granTable[granIdx] != 0 )
+ granNum++;
+
+ return _FS_MODE(_FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST, granIdx, granNum, accessFlags);
+}
+
+
+/*****************************************************************************/
+/* API functions */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* sl_FsOpen */
+/*****************************************************************************/
+typedef union
+{
+ _FsOpenCommand_t Cmd;
+ _FsOpenResponse_t Rsp;
+}_SlFsOpenMsg_u;
+
+const _SlCmdCtrl_t _SlFsOpenCmdCtrl =
+{
+ SL_OPCODE_NVMEM_FILEOPEN,
+ sizeof(_FsOpenCommand_t),
+ sizeof(_FsOpenResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_FsOpen)
+_i32 sl_FsOpen(_u8 *pFileName,_u32 AccessModeAndMaxSize, _u32 *pToken,_i32 *pFileHandle)
+{
+ _SlReturnVal_t RetVal;
+ _SlFsOpenMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (_sl_Strlen(pFileName)+4) & (~3); // add 4: 1 for NULL and the 3 for align
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = pFileName;
+ CmdExt.pRxPayload = NULL;
+
+ Msg.Cmd.Mode = AccessModeAndMaxSize;
+
+ if(pToken != NULL)
+ {
+ Msg.Cmd.Token = *pToken;
+ }
+ else
+ {
+ Msg.Cmd.Token = 0;
+ }
+
+ RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsOpenCmdCtrl, &Msg, &CmdExt);
+ *pFileHandle = Msg.Rsp.FileHandle;
+ if (pToken != NULL)
+ {
+ *pToken = Msg.Rsp.Token;
+ }
+
+ /* in case of an error, return the erros file handler as an error code */
+ if( *pFileHandle < 0 )
+ {
+ return *pFileHandle;
+ }
+ return (_i32)RetVal;
+}
+#endif
+
+/*****************************************************************************/
+/* sl_FsClose */
+/*****************************************************************************/
+typedef union
+{
+ _FsCloseCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlFsCloseMsg_u;
+
+const _SlCmdCtrl_t _SlFsCloseCmdCtrl =
+{
+ SL_OPCODE_NVMEM_FILECLOSE,
+ sizeof(_FsCloseCommand_t),
+ sizeof(_FsCloseResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_FsClose)
+_i16 sl_FsClose(_i32 FileHdl, _u8* pCeritificateFileName,_u8* pSignature ,_u32 SignatureLen)
+{
+ _SlFsCloseMsg_u Msg = {.Cmd = {0, 0, 0}, .Rsp = {0, 0}};
+ _SlCmdExt_t ExtCtrl;
+
+ Msg.Cmd.FileHandle = FileHdl;
+ if( pCeritificateFileName != NULL )
+ {
+ Msg.Cmd.CertificFileNameLength = (_sl_Strlen(pCeritificateFileName)+4) & (~3); /* add 4: 1 for NULL and the 3 for align */
+ }
+ Msg.Cmd.SignatureLen = SignatureLen;
+
+ ExtCtrl.TxPayloadLen = ((SignatureLen+3) & (~3)); /* align */
+ ExtCtrl.pTxPayload = pSignature;
+ ExtCtrl.RxPayloadLen = (_u16)Msg.Cmd.CertificFileNameLength;
+ ExtCtrl.pRxPayload = pCeritificateFileName; /* Add signature */
+
+ if(ExtCtrl.pRxPayload != NULL && ExtCtrl.RxPayloadLen != 0)
+ {
+ g_pCB->RelayFlagsViaRxPayload = TRUE;
+ }
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsCloseCmdCtrl, &Msg, &ExtCtrl));
+
+ return (_i16)((_i16)Msg.Rsp.status);
+}
+#endif
+
+
+/*****************************************************************************/
+/* sl_FsRead */
+/*****************************************************************************/
+typedef union
+{
+ _FsReadCommand_t Cmd;
+ _FsReadResponse_t Rsp;
+}_SlFsReadMsg_u;
+
+const _SlCmdCtrl_t _SlFsReadCmdCtrl =
+{
+ SL_OPCODE_NVMEM_FILEREADCOMMAND,
+ sizeof(_FsReadCommand_t),
+ sizeof(_FsReadResponse_t)
+};
+
+
+#if _SL_INCLUDE_FUNC(sl_FsRead)
+_i32 sl_FsRead(_i32 FileHdl, _u32 Offset, _u8* pData, _u32 Len)
+{
+ _SlFsReadMsg_u Msg;
+ _SlCmdExt_t ExtCtrl;
+ _u16 ChunkLen;
+ _SlReturnVal_t RetVal =0;
+ _i32 RetCount = 0;
+
+ ExtCtrl.TxPayloadLen = 0;
+ ExtCtrl.pTxPayload = NULL;
+
+ ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len);
+ ExtCtrl.RxPayloadLen = ChunkLen;
+ ExtCtrl.pRxPayload = (_u8 *)(pData);
+ Msg.Cmd.Offset = Offset;
+ Msg.Cmd.Len = ChunkLen;
+ Msg.Cmd.FileHandle = FileHdl;
+ do
+ {
+ RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsReadCmdCtrl, &Msg, &ExtCtrl);
+ if(SL_OS_RET_CODE_OK == RetVal)
+ {
+ if( Msg.Rsp.status < 0)
+ {
+ if( RetCount > 0)
+ {
+ return RetCount;
+ }
+ else
+ {
+ return Msg.Rsp.status;
+ }
+ }
+ RetCount += (_i32)Msg.Rsp.status;
+ Len -= ChunkLen;
+ Offset += ChunkLen;
+ Msg.Cmd.Offset = Offset;
+ ExtCtrl.pRxPayload += ChunkLen;
+ ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len);
+ ExtCtrl.RxPayloadLen = ChunkLen;
+ Msg.Cmd.Len = ChunkLen;
+ Msg.Cmd.FileHandle = FileHdl;
+ }
+ else
+ {
+ return RetVal;
+ }
+ }while(ChunkLen > 0);
+
+ return (_i32)RetCount;
+}
+#endif
+
+/*****************************************************************************/
+/* sl_FsWrite */
+/*****************************************************************************/
+typedef union
+{
+ _FsWriteCommand_t Cmd;
+ _FsWriteResponse_t Rsp;
+}_SlFsWriteMsg_u;
+
+const _SlCmdCtrl_t _SlFsWriteCmdCtrl =
+{
+ SL_OPCODE_NVMEM_FILEWRITECOMMAND,
+ sizeof(_FsWriteCommand_t),
+ sizeof(_FsWriteResponse_t)
+};
+
+
+#if _SL_INCLUDE_FUNC(sl_FsWrite)
+_i32 sl_FsWrite(_i32 FileHdl, _u32 Offset, _u8* pData, _u32 Len)
+{
+ _SlFsWriteMsg_u Msg;
+ _SlCmdExt_t ExtCtrl;
+ _u16 ChunkLen;
+ _SlReturnVal_t RetVal;
+ _i32 RetCount = 0;
+
+ ExtCtrl.RxPayloadLen = 0;
+ ExtCtrl.pRxPayload = NULL;
+
+ ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len);
+ ExtCtrl.TxPayloadLen = ChunkLen;
+ ExtCtrl.pTxPayload = (_u8 *)(pData);
+ Msg.Cmd.Offset = Offset;
+ Msg.Cmd.Len = ChunkLen;
+ Msg.Cmd.FileHandle = FileHdl;
+
+ do
+ {
+
+ RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsWriteCmdCtrl, &Msg, &ExtCtrl);
+ if(SL_OS_RET_CODE_OK == RetVal)
+ {
+ if( Msg.Rsp.status < 0)
+ {
+ if( RetCount > 0)
+ {
+ return RetCount;
+ }
+ else
+ {
+ return Msg.Rsp.status;
+ }
+ }
+
+ RetCount += (_i32)Msg.Rsp.status;
+ Len -= ChunkLen;
+ Offset += ChunkLen;
+ Msg.Cmd.Offset = Offset;
+ ExtCtrl.pTxPayload += ChunkLen;
+ ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len);
+ ExtCtrl.TxPayloadLen = ChunkLen;
+ Msg.Cmd.Len = ChunkLen;
+ Msg.Cmd.FileHandle = FileHdl;
+ }
+ else
+ {
+ return RetVal;
+ }
+ }while(ChunkLen > 0);
+
+ return (_i32)RetCount;
+}
+#endif
+
+/*****************************************************************************/
+/* sl_FsGetInfo */
+/*****************************************************************************/
+typedef union
+{
+ _FsGetInfoCommand_t Cmd;
+ _FsGetInfoResponse_t Rsp;
+}_SlFsGetInfoMsg_u;
+
+const _SlCmdCtrl_t _SlFsGetInfoCmdCtrl =
+{
+ SL_OPCODE_NVMEM_FILEGETINFOCOMMAND,
+ sizeof(_FsGetInfoCommand_t),
+ sizeof(_FsGetInfoResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_FsGetInfo)
+_i16 sl_FsGetInfo(_u8 *pFileName,_u32 Token,SlFsFileInfo_t* pFsFileInfo)
+{
+ _SlFsGetInfoMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (_sl_Strlen(pFileName)+4) & (~3); /* add 4: 1 for NULL and the 3 for align */
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = pFileName;
+ CmdExt.pRxPayload = NULL;
+ Msg.Cmd.Token = Token;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsGetInfoCmdCtrl, &Msg, &CmdExt));
+
+ pFsFileInfo->flags = Msg.Rsp.flags;
+ pFsFileInfo->FileLen = Msg.Rsp.FileLen;
+ pFsFileInfo->AllocatedLen = Msg.Rsp.AllocatedLen;
+ pFsFileInfo->Token[0] = Msg.Rsp.Token[0];
+ pFsFileInfo->Token[1] = Msg.Rsp.Token[1];
+ pFsFileInfo->Token[2] = Msg.Rsp.Token[2];
+ pFsFileInfo->Token[3] = Msg.Rsp.Token[3];
+ return (_i16)((_i16)Msg.Rsp.Status);
+}
+#endif
+
+/*****************************************************************************/
+/* sl_FsDel */
+/*****************************************************************************/
+typedef union
+{
+ _FsDeleteCommand_t Cmd;
+ _FsDeleteResponse_t Rsp;
+}_SlFsDeleteMsg_u;
+
+const _SlCmdCtrl_t _SlFsDeleteCmdCtrl =
+{
+ SL_OPCODE_NVMEM_FILEDELCOMMAND,
+ sizeof(_FsDeleteCommand_t),
+ sizeof(_FsDeleteResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_FsDel)
+_i16 sl_FsDel(_u8 *pFileName,_u32 Token)
+{
+ _SlFsDeleteMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (_sl_Strlen(pFileName)+4) & (~3); /* add 4: 1 for NULL and the 3 for align */
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = pFileName;
+ CmdExt.pRxPayload = NULL;
+ Msg.Cmd.Token = Token;
+
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsDeleteCmdCtrl, &Msg, &CmdExt));
+
+ return (_i16)((_i16)Msg.Rsp.status);
+}
+#endif
diff --git a/cc3200/simplelink/source/netapp.c b/cc3200/simplelink/source/netapp.c
new file mode 100644
index 0000000000..32315e093a
--- /dev/null
+++ b/cc3200/simplelink/source/netapp.c
@@ -0,0 +1,1285 @@
+/*
+ * netapp.c - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+#define NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT ((_u32)0x1 << 31)
+
+#ifdef SL_TINY
+#define NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH 63
+#else
+#define NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH 255
+#endif
+
+
+/*****************************************************************************/
+/* Functions prototypes */
+/*****************************************************************************/
+void _sl_HandleAsync_DnsGetHostByName(void *pVoidBuf);
+void _sl_HandleAsync_DnsGetHostByService(void *pVoidBuf);
+void _sl_HandleAsync_PingResponse(void *pVoidBuf);
+void CopyPingResultsToReport(_PingReportResponse_t *pResults,SlPingReport_t *pReport);
+_u16 sl_NetAppSendTokenValue(slHttpServerData_t * Token);
+_i16 sl_NetAppMDNSRegisterUnregisterService(const _i8* pServiceName,
+ _u8 ServiceNameLen,
+ const _i8* pText,
+ _u8 TextLen,
+ _u16 Port,
+ _u32 TTL,
+ _u32 Options);
+
+
+/*****************************************************************************/
+/* API functions */
+/*****************************************************************************/
+
+/*****************************************************************************
+ sl_NetAppStart
+*****************************************************************************/
+typedef union
+{
+ _NetAppStartStopCommand_t Cmd;
+ _NetAppStartStopResponse_t Rsp;
+}_SlNetAppStartStopMsg_u;
+
+const _SlCmdCtrl_t _SlNetAppStartCtrl =
+{
+ SL_OPCODE_NETAPP_START_COMMAND,
+ sizeof(_NetAppStartStopCommand_t),
+ sizeof(_NetAppStartStopResponse_t)
+};
+
+const _SlCmdCtrl_t _SlNetAppStopCtrl =
+{
+ SL_OPCODE_NETAPP_STOP_COMMAND,
+ sizeof(_NetAppStartStopCommand_t),
+ sizeof(_NetAppStartStopResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_NetAppStart)
+_i16 sl_NetAppStart(_u32 AppBitMap)
+{
+ _SlNetAppStartStopMsg_u Msg;
+ Msg.Cmd.appId = AppBitMap;
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStartCtrl, &Msg, NULL));
+
+ return Msg.Rsp.status;
+}
+#endif
+
+/*****************************************************************************
+ sl_NetAppStop
+*****************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_NetAppStop)
+_i16 sl_NetAppStop(_u32 AppBitMap)
+{
+ _SlNetAppStartStopMsg_u Msg;
+ Msg.Cmd.appId = AppBitMap;
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStopCtrl, &Msg, NULL));
+
+ return Msg.Rsp.status;
+}
+#endif
+
+
+/******************************************************************************/
+/* sl_NetAppGetServiceList */
+/******************************************************************************/
+typedef struct
+{
+ _u8 IndexOffest;
+ _u8 MaxServiceCount;
+ _u8 Flags;
+ _i8 Padding;
+}NetappGetServiceListCMD_t;
+
+typedef union
+{
+ NetappGetServiceListCMD_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlNetappGetServiceListMsg_u;
+
+const _SlCmdCtrl_t _SlGetServiceListeCtrl =
+{
+ SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE,
+ sizeof(NetappGetServiceListCMD_t),
+ sizeof(_BasicResponse_t)
+};
+
+
+#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList)
+_i16 sl_NetAppGetServiceList(_u8 IndexOffest,
+ _u8 MaxServiceCount,
+ _u8 Flags,
+ _i8 *pBuffer,
+ _u32 RxBufferLength
+ )
+{
+
+ _i32 retVal= 0;
+ _SlNetappGetServiceListMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+ _u16 ServiceSize = 0;
+ _u16 BufferSize = 0;
+
+ /*
+ Calculate RX pBuffer size
+ WARNING:
+ if this size is BufferSize than 1480 error should be returned because there
+ is no place in the RX packet.
+ */
+ switch(Flags)
+ {
+ case SL_NET_APP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE:
+ ServiceSize = sizeof(SlNetAppGetFullServiceWithTextIpv4List_t);
+ break;
+
+ case SL_NET_APP_FULL_SERVICE_IPV4_TYPE:
+ ServiceSize = sizeof(SlNetAppGetFullServiceIpv4List_t);
+ break;
+
+ case SL_NET_APP_SHORT_SERVICE_IPV4_TYPE:
+ ServiceSize = sizeof(SlNetAppGetShortServiceIpv4List_t);
+ break;
+
+ default:
+ ServiceSize = sizeof(_BasicResponse_t);
+ break;
+ }
+
+
+
+ BufferSize = MaxServiceCount * ServiceSize;
+
+ /*Check the size of the requested services is smaller than size of the user buffer.
+ If not an error is returned in order to avoid overwriting memory. */
+ if(RxBufferLength <= BufferSize)
+ {
+ return SL_ERROR_NETAPP_RX_BUFFER_LENGTH_ERROR;
+ }
+
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = BufferSize;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)pBuffer;
+
+ Msg.Cmd.IndexOffest = IndexOffest;
+ Msg.Cmd.MaxServiceCount = MaxServiceCount;
+ Msg.Cmd.Flags = Flags;
+ Msg.Cmd.Padding = 0;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetServiceListeCtrl, &Msg, &CmdExt));
+ retVal = Msg.Rsp.status;
+
+ return (_i16)retVal;
+}
+
+#endif
+
+/*****************************************************************************/
+/* sl_mDNSRegisterService */
+/*****************************************************************************/
+/*
+ * The below struct depicts the constant parameters of the command/API RegisterService.
+ *
+ 1. ServiceLen - The length of the service should be smaller than NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ 2. TextLen - The length of the text should be smaller than NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ 3. port - The port on this target host.
+ 4. TTL - The TTL of the service
+ 5. Options - bitwise parameters:
+ bit 0 - is unique (means if the service needs to be unique)
+ bit 31 - for internal use if the service should be added or deleted (set means ADD).
+ bit 1-30 for future.
+
+ NOTE:
+
+ 1. There are another variable parameter is this API which is the service name and the text.
+ 2. According to now there is no warning and Async event to user on if the service is a unique.
+*
+ */
+
+
+typedef struct
+{
+ _u8 ServiceNameLen;
+ _u8 TextLen;
+ _u16 Port;
+ _u32 TTL;
+ _u32 Options;
+}NetappMdnsSetService_t;
+
+typedef union
+{
+ NetappMdnsSetService_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlNetappMdnsRegisterServiceMsg_u;
+
+const _SlCmdCtrl_t _SlRegisterServiceCtrl =
+{
+ SL_OPCODE_NETAPP_MDNSREGISTERSERVICE,
+ sizeof(NetappMdnsSetService_t),
+ sizeof(_BasicResponse_t)
+};
+
+
+/******************************************************************************
+
+ sl_NetAppMDNSRegisterService
+
+ CALLER user from its host
+
+
+ DESCRIPTION:
+ Add/delete service
+ The function manipulates the command that register the service and call
+ to the NWP in order to add/delete the service to/from the mDNS package and to/from the DB.
+
+ This register service is a service offered by the application.
+ This unregister service is a service offered by the application before.
+
+ The service name should be full service name according to RFC
+ of the DNS-SD - means the value in name field in SRV answer.
+
+ Example for service name:
+ 1. PC1._ipp._tcp.local
+ 2. PC2_server._ftp._tcp.local
+
+ If the option is_unique is set, mDNS probes the service name to make sure
+ it is unique before starting to announce the service on the network.
+ Instance is the instance portion of the service name.
+
+
+
+
+ PARAMETERS:
+
+ The command is from constant parameters and variables parameters.
+
+ Constant parameters are:
+
+ ServiceLen - The length of the service.
+ TextLen - The length of the service should be smaller than 64.
+ port - The port on this target host.
+ TTL - The TTL of the service
+ Options - bitwise parameters:
+ bit 0 - is unique (means if the service needs to be unique)
+ bit 31 - for internal use if the service should be added or deleted (set means ADD).
+ bit 1-30 for future.
+
+ The variables parameters are:
+
+ Service name(full service name) - The service name.
+ Example for service name:
+ 1. PC1._ipp._tcp.local
+ 2. PC2_server._ftp._tcp.local
+
+ Text - The description of the service.
+ should be as mentioned in the RFC
+ (according to type of the service IPP,FTP...)
+
+ NOTE - pay attention
+
+ 1. Temporary - there is an allocation on stack of internal buffer.
+ Its size is NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ It means that the sum of the text length and service name length cannot be bigger than
+ NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ If it is - An error is returned.
+
+ 2. According to now from certain constraints the variables parameters are set in the
+ attribute part (contain constant parameters)
+
+
+
+ RETURNS: Status - the immediate response of the command status.
+ 0 means success.
+
+
+
+******************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterUnregisterService)
+
+_i16 sl_NetAppMDNSRegisterUnregisterService( const _i8* pServiceName,
+ _u8 ServiceNameLen,
+ const _i8* pText,
+ _u8 TextLen,
+ _u16 Port,
+ _u32 TTL,
+ _u32 Options)
+
+{
+ _SlNetappMdnsRegisterServiceMsg_u Msg;
+ _SlCmdExt_t CmdExt ;
+ _i8 ServiceNameAndTextBuffer[NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH];
+ _i8 *TextPtr;
+
+ /*
+
+ NOTE - pay attention
+
+ 1. Temporary - there is an allocation on stack of internal buffer.
+ Its size is NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ It means that the sum of the text length and service name length cannot be bigger than
+ NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ If it is - An error is returned.
+
+ 2. According to now from certain constraints the variables parameters are set in the
+ attribute part (contain constant parameters)
+
+
+ */
+
+ /*build the attribute part of the command.
+ It contains the constant parameters of the command*/
+
+ Msg.Cmd.ServiceNameLen = ServiceNameLen;
+ Msg.Cmd.Options = Options;
+ Msg.Cmd.Port = Port;
+ Msg.Cmd.TextLen = TextLen;
+ Msg.Cmd.TTL = TTL;
+
+ /*Build the payload part of the command
+ Copy the service name and text to one buffer.
+ NOTE - pay attention
+ The size of the service length + the text length should be smaller than 255,
+ Until the simplelink drive supports to variable length through SPI command. */
+ if(TextLen + ServiceNameLen > (NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH - 1 )) /*-1 is for giving a place to set null termination at the end of the text*/
+ {
+ return -1;
+ }
+
+ sl_Memset(ServiceNameAndTextBuffer,0,NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH);
+
+
+ /*Copy the service name*/
+ sl_Memcpy(ServiceNameAndTextBuffer,
+ pServiceName,
+ ServiceNameLen);
+
+ if(TextLen > 0 )
+ {
+
+ TextPtr = &ServiceNameAndTextBuffer[ServiceNameLen];
+ /*Copy the text just after the service name*/
+ sl_Memcpy(TextPtr,
+ pText,
+ TextLen);
+
+
+ }
+
+ CmdExt.TxPayloadLen = (TextLen + ServiceNameLen);
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)ServiceNameAndTextBuffer;
+ CmdExt.pRxPayload = NULL;
+
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlRegisterServiceCtrl, &Msg, &CmdExt));
+
+ return (_i16)Msg.Rsp.status;
+
+
+}
+#endif
+
+/**********************************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService)
+
+_i16 sl_NetAppMDNSRegisterService( const _i8* pServiceName,
+ _u8 ServiceNameLen,
+ const _i8* pText,
+ _u8 TextLen,
+ _u16 Port,
+ _u32 TTL,
+ _u32 Options)
+
+{
+
+ /*
+
+ NOTE - pay attention
+
+ 1. Temporary - there is an allocation on stack of internal buffer.
+ Its size is NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ It means that the sum of the text length and service name length cannot be bigger than
+ NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.
+ If it is - An error is returned.
+
+ 2. According to now from certain constraints the variables parameters are set in the
+ attribute part (contain constant parameters)
+
+ */
+
+ /*Set the add service bit in the options parameter.
+ In order not use different opcodes for the register service and unregister service
+ bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added
+ if it is cleared it means that the service should be deleted and there is only meaning to pServiceName
+ and ServiceNameLen values. */
+ Options |= NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT;
+
+ return sl_NetAppMDNSRegisterUnregisterService( pServiceName,
+ ServiceNameLen,
+ pText,
+ TextLen,
+ Port,
+ TTL,
+ Options);
+
+
+}
+#endif
+/**********************************************************************************************/
+
+
+
+/**********************************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService)
+
+_i16 sl_NetAppMDNSUnRegisterService( const _i8* pServiceName,
+ _u8 ServiceNameLen)
+
+
+{
+ _u32 Options = 0;
+
+ /*
+
+ NOTE - pay attention
+
+ The size of the service length should be smaller than 255,
+ Until the simplelink drive supports to variable length through SPI command.
+
+
+ */
+
+ /*Clear the add service bit in the options parameter.
+ In order not use different opcodes for the register service and unregister service
+ bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added
+ if it is cleared it means that the service should be deleted and there is only meaning to pServiceName
+ and ServiceNameLen values.*/
+
+ Options &= (~NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT);
+
+ return sl_NetAppMDNSRegisterUnregisterService( pServiceName,
+ ServiceNameLen,
+ NULL,
+ 0,
+ 0,
+ 0,
+ Options);
+
+
+}
+#endif
+/**********************************************************************************************/
+
+
+
+/*****************************************************************************/
+/* sl_DnsGetHostByService */
+/*****************************************************************************/
+/*
+ * The below struct depicts the constant parameters of the command/API sl_DnsGetHostByService.
+ *
+ 1. ServiceLen - The length of the service should be smaller than 255.
+ 2. AddrLen - TIPv4 or IPv6 (SL_AF_INET , SL_AF_INET6).
+*
+ */
+
+typedef struct
+{
+ _u8 ServiceLen;
+ _u8 AddrLen;
+ _u16 Padding;
+}_GetHostByServiceCommand_t;
+
+
+
+/*
+ * The below structure depict the constant parameters that are returned in the Async event answer
+ * according to command/API sl_DnsGetHostByService for IPv4 and IPv6.
+ *
+ 1Status - The status of the response.
+ 2.Address - Contains the IP address of the service.
+ 3.Port - Contains the port of the service.
+ 4.TextLen - Contains the max length of the text that the user wants to get.
+ it means that if the test of service is bigger that its value than
+ the text is cut to inout_TextLen value.
+ Output: Contain the length of the text that is returned. Can be full text or part
+ of the text (see above).
+
+*
+ */
+typedef struct
+{
+ _u16 Status;
+ _u16 TextLen;
+ _u32 Port;
+ _u32 Address;
+}_GetHostByServiceIPv4AsyncResponse_t;
+
+
+typedef struct
+{
+ _u16 Status;
+ _u16 TextLen;
+ _u32 Port;
+ _u32 Address[4];
+}_GetHostByServiceIPv6AsyncResponse_t;
+
+
+typedef union
+{
+ _GetHostByServiceIPv4AsyncResponse_t IpV4;
+ _GetHostByServiceIPv6AsyncResponse_t IpV6;
+}_GetHostByServiceAsyncResponseAttribute_u;
+
+/*
+ * The below struct contains pointers to the output parameters that the user gives
+ *
+ */
+typedef struct
+{
+ _i16 Status;
+ _u32 *out_pAddr;
+ _u32 *out_pPort;
+ _u16 *inout_TextLen; // in: max len , out: actual len
+ _i8 *out_pText;
+}_GetHostByServiceAsyncResponse_t;
+
+
+typedef union
+{
+ _GetHostByServiceCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlGetHostByServiceMsg_u;
+
+const _SlCmdCtrl_t _SlGetHostByServiceCtrl =
+{
+ SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE,
+ sizeof(_GetHostByServiceCommand_t),
+ sizeof(_BasicResponse_t)
+};
+
+
+
+/******************************************************************************/
+
+#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService)
+_i32 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */
+ _u8 ServiceLen,
+ _u8 Family, /* 4-IPv4 , 16-IPv6 */
+ _u32 pAddr[],
+ _u32 *pPort,
+ _u16 *pTextLen, /* in: max len , out: actual len */
+ _i8 *pText
+ )
+{
+ _SlGetHostByServiceMsg_u Msg;
+ _SlCmdExt_t CmdExt ;
+ _GetHostByServiceAsyncResponse_t AsyncRsp;
+ _u8 ObjIdx = MAX_CONCURRENT_ACTIONS;
+
+/*
+ Note:
+ 1. The return's attributes are belonged to first service that is found.
+ It can be other services with the same service name will response to
+ the query. The results of these responses are saved in the peer cache of the NWP, and
+ should be read by another API.
+
+ 2. Text length can be 120 bytes only - not more
+ It is because of constraints in the NWP on the buffer that is allocated for the Async event.
+
+ 3.The API waits to Async event by blocking. It means that the API is finished only after an Async event
+ is sent by the NWP.
+
+ 4.No rolling option!!! - only PTR type is sent.
+
+
+*/
+ /*build the attribute part of the command.
+ It contains the constant parameters of the command */
+
+ Msg.Cmd.ServiceLen = ServiceLen;
+ Msg.Cmd.AddrLen = Family;
+
+ /*Build the payload part of the command
+ Copy the service name and text to one buffer.*/
+ CmdExt.TxPayloadLen = ServiceLen;
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pServiceName;
+ CmdExt.pRxPayload = NULL;
+
+ /*set pointers to the output parameters (the returned parameters).
+ This pointers are belonged to local struct that is set to global Async response parameter.
+ It is done in order not to run more than one sl_DnsGetHostByService at the same time.
+ The API should be run only if global parameter is pointed to NULL. */
+ AsyncRsp.out_pText = pText;
+ AsyncRsp.inout_TextLen = (_u16* )pTextLen;
+ AsyncRsp.out_pPort = pPort;
+ AsyncRsp.out_pAddr = (_u32 *)pAddr;
+
+
+ /*Use Obj to issue the command, if not available try later */
+ ObjIdx = (_u8)_SlDrvWaitForPoolObj(GETHOSYBYSERVICE_ID,SL_MAX_SOCKETS);
+
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (void *)&AsyncRsp;
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ /* set bit to indicate IPv6 address is expected */
+ if (SL_AF_INET6 == Family)
+ {
+ g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK;
+ }
+ /* Send the command */
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByServiceCtrl, &Msg, &CmdExt));
+
+
+
+ /* If the immediate reponse is O.K. than wait for aSYNC event response. */
+ if(SL_RET_CODE_OK == Msg.Rsp.status)
+ {
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+
+ /* If we are - it means that Async event was sent.
+ The results are copied in the Async handle return functions */
+
+ Msg.Rsp.status = AsyncRsp.Status;
+ }
+
+ _SlDrvReleasePoolObj(ObjIdx);
+ return Msg.Rsp.status;
+}
+#endif
+/******************************************************************************/
+
+/******************************************************************************
+ _sl_HandleAsync_DnsGetHostByService
+
+ CALLER NWP - Async event on sl_DnsGetHostByService with IPv4 Family
+
+
+ DESCRIPTION:
+
+ Async event on sl_DnsGetHostByService command with IPv4 Family.
+ Return service attributes like IP address, port and text according to service name.
+ The user sets a service name Full/Part (see example below), and should get the:
+ 1. IP of the service
+ 2. The port of service.
+ 3. The text of service.
+
+ Hence it can make a connection to the specific service and use it.
+ It is similar to get host by name method.
+
+ It is done by a single shot query with PTR type on the service name.
+
+
+
+ Note:
+ 1. The return's attributes are belonged to first service that is found.
+ It can be other services with the same service name will response to
+ the query. The results of these responses are saved in the peer cache of the NWP, and
+ should be read by another API.
+
+
+ PARAMETERS:
+
+ pVoidBuf - is point to opcode of the event.
+ it contains the outputs that are given to the user
+
+ outputs description:
+
+ 1.out_pAddr[] - output: Contain the IP address of the service.
+ 2.out_pPort - output: Contain the port of the service.
+ 3.inout_TextLen - Input: Contain the max length of the text that the user wants to get.
+ it means that if the test of service is bigger that its value than
+ the text is cut to inout_TextLen value.
+ Output: Contain the length of the text that is returned. Can be full text or part
+ of the text (see above).
+
+ 4.out_pText - Contain the text of the service (full or part see above- inout_TextLen description).
+
+ *
+
+
+ RETURNS: success or fail.
+
+
+
+
+
+******************************************************************************/
+void _sl_HandleAsync_DnsGetHostByService(void *pVoidBuf)
+{
+
+ _GetHostByServiceAsyncResponse_t* Res;
+ _u16 TextLen;
+ _u16 UserTextLen;
+
+
+ /*pVoidBuf - is point to opcode of the event.*/
+
+ /*set pMsgArgs to point to the attribute of the event.*/
+ _GetHostByServiceIPv4AsyncResponse_t *pMsgArgs = (_GetHostByServiceIPv4AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf);
+
+ VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs);
+
+ /*IPv6*/
+ if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK)
+ {
+ return;
+ }
+ /*IPv4*/
+ else
+ {
+ /*************************************************************************************************
+
+ 1. Copy the attribute part of the evnt to the attribute part of the response
+ sl_Memcpy(g_pCB->GetHostByServiceCB.pAsyncRsp, pMsgArgs, sizeof(_GetHostByServiceIPv4AsyncResponse_t));
+
+ set to TextLen the text length of the service.*/
+ TextLen = pMsgArgs->TextLen;
+
+ /*Res pointed to mDNS global object struct */
+ Res = (_GetHostByServiceAsyncResponse_t*)g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs;
+
+
+
+ /*It is 4 bytes so we avoid from memcpy*/
+ Res->out_pAddr[0] = pMsgArgs->Address;
+ Res->out_pPort[0] = pMsgArgs->Port;
+ Res->Status = pMsgArgs->Status;
+
+ /*set to TextLen the text length of the user (input fromthe user).*/
+ UserTextLen = Res->inout_TextLen[0];
+
+ /*Cut the service text if the user requested for smaller text.*/
+ UserTextLen = (TextLen <= UserTextLen) ? TextLen : UserTextLen;
+ Res->inout_TextLen[0] = UserTextLen ;
+
+ /**************************************************************************************************
+
+ 2. Copy the payload part of the evnt (the text) to the payload part of the response
+ the lenght of the copy is according to the text length in the attribute part. */
+
+
+ sl_Memcpy(Res->out_pText ,
+ (_i8 *)(& pMsgArgs[1]) , /* & pMsgArgs[1] -> 1st byte after the fixed header = 1st byte of variable text.*/
+ UserTextLen );
+
+
+ /**************************************************************************************************/
+
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj));
+ return;
+ }
+}
+
+
+
+/*****************************************************************************/
+/* _sl_HandleAsync_DnsGetHostByAddr */
+/*****************************************************************************/
+void _sl_HandleAsync_DnsGetHostByAddr(void *pVoidBuf)
+{
+ SL_TRACE0(DBG_MSG, MSG_303, "STUB: _sl_HandleAsync_DnsGetHostByAddr not implemented yet!");
+ return;
+}
+
+/*****************************************************************************/
+/* sl_DnsGetHostByName */
+/*****************************************************************************/
+typedef union
+{
+ _GetHostByNameIPv4AsyncResponse_t IpV4;
+ _GetHostByNameIPv6AsyncResponse_t IpV6;
+}_GetHostByNameAsyncResponse_u;
+
+typedef union
+{
+ _GetHostByNameCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlGetHostByNameMsg_u;
+
+const _SlCmdCtrl_t _SlGetHostByNameCtrl =
+{
+ SL_OPCODE_NETAPP_DNSGETHOSTBYNAME,
+ sizeof(_GetHostByNameCommand_t),
+ sizeof(_BasicResponse_t)
+};
+#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName)
+_i16 sl_NetAppDnsGetHostByName(_i8 * hostname, _u16 usNameLen, _u32* out_ip_addr,_u8 family)
+{
+ _SlGetHostByNameMsg_u Msg;
+ _SlCmdExt_t ExtCtrl;
+ _GetHostByNameAsyncResponse_u AsyncRsp;
+ _u8 ObjIdx = MAX_CONCURRENT_ACTIONS;
+
+ ExtCtrl.TxPayloadLen = usNameLen;
+ ExtCtrl.RxPayloadLen = 0;
+ ExtCtrl.pTxPayload = (_u8 *)hostname;
+ ExtCtrl.pRxPayload = 0;
+
+ Msg.Cmd.Len = usNameLen;
+ Msg.Cmd.family = family;
+
+ /*Use Obj to issue the command, if not available try later */
+ ObjIdx = (_u8)_SlDrvWaitForPoolObj(GETHOSYBYNAME_ID,SL_MAX_SOCKETS);
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp;
+ /*set bit to indicate IPv6 address is expected */
+ if (SL_AF_INET6 == family)
+ {
+ g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK;
+ }
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByNameCtrl, &Msg, &ExtCtrl));
+
+ if(SL_RET_CODE_OK == Msg.Rsp.status)
+ {
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+ Msg.Rsp.status = AsyncRsp.IpV4.status;
+
+ if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status)
+ {
+ sl_Memcpy((_i8 *)out_ip_addr,
+ (_i8 *)&AsyncRsp.IpV4.ip0,
+ (SL_AF_INET == family) ? SL_IPV4_ADDRESS_SIZE : SL_IPV6_ADDRESS_SIZE);
+ }
+ }
+ _SlDrvReleasePoolObj(ObjIdx);
+ return Msg.Rsp.status;
+}
+#endif
+/******************************************************************************/
+/* _sl_HandleAsync_DnsGetHostByName */
+/******************************************************************************/
+void _sl_HandleAsync_DnsGetHostByName(void *pVoidBuf)
+{
+ _GetHostByNameIPv4AsyncResponse_t *pMsgArgs = (_GetHostByNameIPv4AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf);
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs);
+
+ /*IPv6 */
+ if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK)
+ {
+ sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_GetHostByNameIPv6AsyncResponse_t));
+ }
+ /*IPv4 */
+ else
+ {
+ sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_GetHostByNameIPv4AsyncResponse_t));
+ }
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj)));
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ return;
+}
+
+
+void CopyPingResultsToReport(_PingReportResponse_t *pResults,SlPingReport_t *pReport)
+{
+ pReport->PacketsSent = pResults->numSendsPings;
+ pReport->PacketsReceived = pResults->numSuccsessPings;
+ pReport->MinRoundTime = pResults->rttMin;
+ pReport->MaxRoundTime = pResults->rttMax;
+ pReport->AvgRoundTime = pResults->rttAvg;
+ pReport->TestTime = pResults->testTime;
+}
+
+
+/*****************************************************************************/
+/* _sl_HandleAsync_PingResponse */
+/*****************************************************************************/
+void _sl_HandleAsync_PingResponse(void *pVoidBuf)
+{
+ _PingReportResponse_t *pMsgArgs = (_PingReportResponse_t *)_SL_RESP_ARGS_START(pVoidBuf);
+ SlPingReport_t pingReport;
+
+ if(pPingCallBackFunc)
+ {
+ CopyPingResultsToReport(pMsgArgs,&pingReport);
+ pPingCallBackFunc(&pingReport);
+ }
+ else
+ {
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+ VERIFY_SOCKET_CB(NULL != g_pCB->PingCB.PingAsync.pAsyncRsp);
+
+ if (NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs)
+ {
+ sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_PingReportResponse_t));
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj));
+ }
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ }
+ return;
+}
+
+
+/*****************************************************************************/
+/* sl_PingStart */
+/*****************************************************************************/
+typedef union
+{
+ _PingStartCommand_t Cmd;
+ _PingReportResponse_t Rsp;
+}_SlPingStartMsg_u;
+
+
+typedef enum
+{
+ CMD_PING_TEST_RUNNING = 0,
+ CMD_PING_TEST_STOPPED
+}_SlPingStatus_e;
+
+
+#if _SL_INCLUDE_FUNC(sl_NetAppPingStart)
+_i16 sl_NetAppPingStart(SlPingStartCommand_t* pPingParams,_u8 family,SlPingReport_t *pReport,const P_SL_DEV_PING_CALLBACK pPingCallback)
+{
+ _SlCmdCtrl_t CmdCtrl = {0, sizeof(_PingStartCommand_t), sizeof(_BasicResponse_t)};
+ _SlPingStartMsg_u Msg;
+ _PingReportResponse_t PingRsp;
+ _u8 ObjIdx = MAX_CONCURRENT_ACTIONS;
+
+ if( 0 == pPingParams->Ip ) // stop any ongoing ping
+ {
+ return _SlDrvBasicCmd(SL_OPCODE_NETAPP_PINGSTOP);
+ }
+
+ if(SL_AF_INET == family)
+ {
+ CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART;
+ sl_Memcpy(&Msg.Cmd.ip0, &pPingParams->Ip, SL_IPV4_ADDRESS_SIZE);
+ }
+ else
+ {
+ CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART_V6;
+ sl_Memcpy(&Msg.Cmd.ip0, &pPingParams->Ip, SL_IPV6_ADDRESS_SIZE);
+ }
+
+ Msg.Cmd.pingIntervalTime = pPingParams->PingIntervalTime;
+ Msg.Cmd.PingSize = pPingParams->PingSize;
+ Msg.Cmd.pingRequestTimeout = pPingParams->PingRequestTimeout;
+ Msg.Cmd.totalNumberOfAttempts = pPingParams->TotalNumberOfAttempts;
+ Msg.Cmd.flags = pPingParams->Flags;
+
+ if( pPingCallback )
+ {
+ pPingCallBackFunc = pPingCallback;
+ }
+ else
+ {
+ /*Use Obj to issue the command, if not available try later */
+ ObjIdx = (_u8)_SlDrvWaitForPoolObj(PING_ID,SL_MAX_SOCKETS);
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+ /* async response handler for non callback mode */
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&PingRsp;
+ pPingCallBackFunc = NULL;
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ }
+
+
+ VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL));
+ /*send the command*/
+ if(CMD_PING_TEST_RUNNING == (_i16)Msg.Rsp.status || CMD_PING_TEST_STOPPED == (_i16)Msg.Rsp.status )
+ {
+ /* block waiting for results if no callback function is used */
+ if( NULL == pPingCallback )
+ {
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+ if( SL_OS_RET_CODE_OK == (_i16)PingRsp.status )
+ {
+ CopyPingResultsToReport(&PingRsp,pReport);
+ }
+ _SlDrvReleasePoolObj(ObjIdx);
+ }
+ }
+ else
+ { /* ping failure, no async response */
+ if( NULL == pPingCallback )
+ {
+ _SlDrvReleasePoolObj(ObjIdx);
+ }
+ }
+
+ return Msg.Rsp.status;
+}
+#endif
+
+/*****************************************************************************/
+/* sl_NetAppSet */
+/*****************************************************************************/
+typedef union
+{
+ _NetAppSetGet_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlNetAppMsgSet_u;
+
+const _SlCmdCtrl_t _SlNetAppSetCmdCtrl =
+{
+ SL_OPCODE_NETAPP_NETAPPSET,
+ sizeof(_NetAppSetGet_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_NetAppSet)
+_i32 sl_NetAppSet(_u8 AppId ,_u8 Option,_u8 OptionLen, _u8 *pOptionValue)
+{
+ _SlNetAppMsgSet_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (OptionLen+3) & (~3);
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pOptionValue;
+ CmdExt.pRxPayload = NULL;
+
+
+ Msg.Cmd.AppId = AppId;
+ Msg.Cmd.ConfigLen = OptionLen;
+ Msg.Cmd.ConfigOpt = Option;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppSetCmdCtrl, &Msg, &CmdExt));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+/*****************************************************************************/
+/* sl_NetAppSendTokenValue */
+/*****************************************************************************/
+typedef union
+{
+ sl_NetAppHttpServerSendToken_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlNetAppMsgSendTokenValue_u;
+
+const _SlCmdCtrl_t _SlNetAppSendTokenValueCmdCtrl =
+{
+ SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE,
+ sizeof(sl_NetAppHttpServerSendToken_t),
+ sizeof(_BasicResponse_t)
+};
+
+_u16 sl_NetAppSendTokenValue(slHttpServerData_t * Token_value)
+{
+ _SlNetAppMsgSendTokenValue_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (Token_value->value_len+3) & (~3);
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *) Token_value->token_value;
+ CmdExt.pRxPayload = NULL;
+
+ Msg.Cmd.token_value_len = Token_value->value_len;
+ Msg.Cmd.token_name_len = Token_value->name_len;
+ sl_Memcpy(&Msg.Cmd.token_name[0], Token_value->token_name, Token_value->name_len);
+
+
+ VERIFY_RET_OK(_SlDrvCmdSend((_SlCmdCtrl_t *)&_SlNetAppSendTokenValueCmdCtrl, &Msg, &CmdExt));
+
+ return Msg.Rsp.status;
+}
+
+/*****************************************************************************/
+/* sl_NetAppGet */
+/*****************************************************************************/
+typedef union
+{
+ _NetAppSetGet_t Cmd;
+ _NetAppSetGet_t Rsp;
+}_SlNetAppMsgGet_u;
+
+const _SlCmdCtrl_t _SlNetAppGetCmdCtrl =
+{
+ SL_OPCODE_NETAPP_NETAPPGET,
+ sizeof(_NetAppSetGet_t),
+ sizeof(_NetAppSetGet_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_NetAppGet)
+_i32 sl_NetAppGet(_u8 AppId, _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue)
+{
+ _SlNetAppMsgGet_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (*pOptionLen == 0)
+ {
+ return SL_EZEROLEN;
+ }
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = *pOptionLen;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)pOptionValue;
+ CmdExt.ActualRxPayloadLen = 0;
+
+ Msg.Cmd.AppId = AppId;
+ Msg.Cmd.ConfigOpt = Option;
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppGetCmdCtrl, &Msg, &CmdExt));
+
+
+ if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen)
+ {
+ *pOptionLen = (_u8)CmdExt.RxPayloadLen;
+ return SL_ESMALLBUF;
+ }
+ else
+ {
+ *pOptionLen = (_u8)CmdExt.ActualRxPayloadLen;
+ }
+
+ return (_i16)Msg.Rsp.Status;
+}
+#endif
+
+
+/*****************************************************************************/
+/* _SlDrvNetAppEventHandler */
+/*****************************************************************************/
+void _SlDrvNetAppEventHandler(void *pArgs)
+{
+ _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pArgs;
+#ifdef sl_HttpServerCallback
+ SlHttpServerEvent_t httpServerEvent;
+ SlHttpServerResponse_t httpServerResponse;
+#endif
+ switch(pHdr->GenHeader.Opcode)
+ {
+ case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE:
+ case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6:
+ _sl_HandleAsync_DnsGetHostByName(pArgs);
+ break;
+ case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE:
+ case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6:
+ _sl_HandleAsync_DnsGetHostByService(pArgs);
+ break;
+ case SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE:
+ _sl_HandleAsync_PingResponse(pArgs);
+ break;
+ case SL_OPCODE_NETAPP_HTTPGETTOKENVALUE:
+ {
+#ifdef sl_HttpServerCallback
+ _u8 *pTokenName;
+ slHttpServerData_t Token_value;
+ sl_NetAppHttpServerGetToken_t *httpGetToken = (sl_NetAppHttpServerGetToken_t *)_SL_RESP_ARGS_START(pHdr);
+ pTokenName = (_u8 *)((sl_NetAppHttpServerGetToken_t *)httpGetToken + 1);
+
+ httpServerResponse.Response = SL_NETAPP_HTTPSETTOKENVALUE;
+ httpServerResponse.ResponseData.token_value.len = MAX_TOKEN_VALUE_LEN;
+ httpServerResponse.ResponseData.token_value.data = (_u8 *)_SL_RESP_ARGS_START(pHdr) + MAX_TOKEN_NAME_LEN; //Reuse the async buffer for getting the token value response from the user
+
+ httpServerEvent.Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT;
+ httpServerEvent.EventData.httpTokenName.len = httpGetToken->token_name_len;
+ httpServerEvent.EventData.httpTokenName.data = pTokenName;
+
+ Token_value.token_name = pTokenName;
+
+ sl_HttpServerCallback (&httpServerEvent, &httpServerResponse);
+
+ Token_value.value_len = httpServerResponse.ResponseData.token_value.len;
+ Token_value.name_len = httpServerEvent.EventData.httpTokenName.len;
+
+ Token_value.token_value = httpServerResponse.ResponseData.token_value.data;
+
+
+ sl_NetAppSendTokenValue(&Token_value);
+#endif
+ }
+ break;
+
+ case SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE:
+ {
+#ifdef sl_HttpServerCallback
+ _u8 *pPostParams;
+
+ sl_NetAppHttpServerPostToken_t *httpPostTokenArgs = (sl_NetAppHttpServerPostToken_t *)_SL_RESP_ARGS_START(pHdr);
+ pPostParams = (_u8 *)((sl_NetAppHttpServerPostToken_t *)httpPostTokenArgs + 1);
+
+ httpServerEvent.Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT;
+
+ httpServerEvent.EventData.httpPostData.action.len = httpPostTokenArgs->post_action_len;
+ httpServerEvent.EventData.httpPostData.action.data = pPostParams;
+ pPostParams+=httpPostTokenArgs->post_action_len;
+
+ httpServerEvent.EventData.httpPostData.token_name.len = httpPostTokenArgs->token_name_len;
+ httpServerEvent.EventData.httpPostData.token_name.data = pPostParams;
+ pPostParams+=httpPostTokenArgs->token_name_len;
+
+ httpServerEvent.EventData.httpPostData.token_value.len = httpPostTokenArgs->token_value_len;
+ httpServerEvent.EventData.httpPostData.token_value.data = pPostParams;
+
+ httpServerResponse.Response = SL_NETAPP_RESPONSE_NONE;
+
+
+ sl_HttpServerCallback (&httpServerEvent, &httpServerResponse);
+#endif
+ }
+ break;
+ default:
+ SL_ERROR_TRACE1(MSG_305, "ASSERT: _SlDrvNetAppEventHandler : invalid opcode = 0x%x", pHdr->GenHeader.Opcode);
+ VERIFY_PROTOCOL(0);
+ }
+}
diff --git a/cc3200/simplelink/source/netcfg.c b/cc3200/simplelink/source/netcfg.c
new file mode 100644
index 0000000000..36d1e1fa97
--- /dev/null
+++ b/cc3200/simplelink/source/netcfg.c
@@ -0,0 +1,142 @@
+/*
+* netcfg.c - CC31xx/CC32xx Host Driver Implementation
+*
+* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+
+/*****************************************************************************/
+/* sl_NetCfgSet */
+/*****************************************************************************/
+typedef union
+{
+ _NetCfgSetGet_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlNetCfgMsgSet_u;
+
+const _SlCmdCtrl_t _SlNetCfgSetCmdCtrl =
+{
+ SL_OPCODE_DEVICE_NETCFG_SET_COMMAND,
+ sizeof(_NetCfgSetGet_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_NetCfgSet)
+_i32 sl_NetCfgSet(_u8 ConfigId ,_u8 ConfigOpt,_u8 ConfigLen, _u8 *pValues)
+{
+ _SlNetCfgMsgSet_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (ConfigLen+3) & (~3);
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pValues;
+ CmdExt.pRxPayload = NULL;
+
+
+ Msg.Cmd.ConfigId = ConfigId;
+ Msg.Cmd.ConfigLen = ConfigLen;
+ Msg.Cmd.ConfigOpt = ConfigOpt;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgSetCmdCtrl, &Msg, &CmdExt));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+
+/*****************************************************************************/
+/* sl_NetCfgGet */
+/*****************************************************************************/
+typedef union
+{
+ _NetCfgSetGet_t Cmd;
+ _NetCfgSetGet_t Rsp;
+}_SlNetCfgMsgGet_u;
+
+const _SlCmdCtrl_t _SlNetCfgGetCmdCtrl =
+{
+ SL_OPCODE_DEVICE_NETCFG_GET_COMMAND,
+ sizeof(_NetCfgSetGet_t),
+ sizeof(_NetCfgSetGet_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_NetCfgGet)
+_i32 sl_NetCfgGet(_u8 ConfigId, _u8 *pConfigOpt,_u8 *pConfigLen, _u8 *pValues)
+{
+ _SlNetCfgMsgGet_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (*pConfigLen == 0)
+ {
+ return SL_EZEROLEN;
+ }
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = *pConfigLen;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)pValues;
+ CmdExt.ActualRxPayloadLen = 0;
+ Msg.Cmd.ConfigLen = *pConfigLen;
+ Msg.Cmd.ConfigId = ConfigId;
+
+ if( pConfigOpt )
+ {
+ Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt;
+ }
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgGetCmdCtrl, &Msg, &CmdExt));
+
+ if( pConfigOpt )
+ {
+ *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt;
+ }
+ if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen)
+ {
+ *pConfigLen = (_u8)CmdExt.RxPayloadLen;
+ return SL_ESMALLBUF;
+ }
+ else
+ {
+ *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen;
+ }
+
+ return (_i16)Msg.Rsp.Status;
+}
+#endif
+
diff --git a/cc3200/simplelink/source/nonos.c b/cc3200/simplelink/source/nonos.c
new file mode 100644
index 0000000000..9e7d1772e2
--- /dev/null
+++ b/cc3200/simplelink/source/nonos.c
@@ -0,0 +1,153 @@
+/*
+* nonos.c - CC31xx/CC32xx Host Driver Implementation
+*
+* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+
+#ifndef SL_PLATFORM_MULTI_THREADED
+
+#include "nonos.h"
+
+#define NONOS_MAX_SPAWN_ENTRIES 5
+
+typedef struct
+{
+ _SlSpawnEntryFunc_t pEntry;
+ void* pValue;
+}_SlNonOsSpawnEntry_t;
+
+typedef struct
+{
+ _SlNonOsSpawnEntry_t SpawnEntries[NONOS_MAX_SPAWN_ENTRIES];
+}_SlNonOsCB_t;
+
+_SlNonOsCB_t g__SlNonOsCB;
+
+
+_SlNonOsRetVal_t _SlNonOsSemSet(_SlNonOsSemObj_t* pSemObj , _SlNonOsSemObj_t Value)
+{
+ *pSemObj = Value;
+ return NONOS_RET_OK;
+}
+
+_SlNonOsRetVal_t _SlNonOsSemGet(_SlNonOsSemObj_t* pSyncObj, _SlNonOsSemObj_t WaitValue, _SlNonOsSemObj_t SetValue, _SlNonOsTime_t Timeout)
+{
+ while (Timeout>0)
+ {
+ if (WaitValue == *pSyncObj)
+ {
+ *pSyncObj = SetValue;
+ break;
+ }
+ if (Timeout != NONOS_WAIT_FOREVER)
+ {
+ Timeout--;
+ }
+ _SlNonOsMainLoopTask();
+#ifdef _SlSyncWaitLoopCallback
+ if( __NON_OS_SYNC_OBJ_SIGNAL_VALUE == WaitValue )
+ {
+ if (WaitValue == *pSyncObj)
+ {
+ *pSyncObj = SetValue;
+ break;
+ }
+ _SlSyncWaitLoopCallback();
+ }
+#endif
+ }
+
+ if (0 == Timeout)
+ {
+ return NONOS_RET_ERR;
+ }
+ else
+ {
+ return NONOS_RET_OK;
+ }
+}
+
+
+_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags)
+{
+ _i16 i;
+
+ for (i=0 ; ipEntry)
+ {
+ pE->pValue = pValue;
+ pE->pEntry = pEntry;
+ break;
+ }
+ }
+
+ return NONOS_RET_OK;
+}
+
+
+_SlNonOsRetVal_t _SlNonOsMainLoopTask(void)
+{
+ _i16 i;
+
+ for (i=0 ; ipEntry;
+
+ if (NULL != pF)
+ {
+ if((g_pCB)->RxIrqCnt != (g_pCB)->RxDoneCnt)
+ {
+ pF(0);/*(pValue);*/
+ }
+ pE->pEntry = NULL;
+ pE->pValue = NULL;
+ }
+ }
+
+ return NONOS_RET_OK;
+}
+
+#endif /*(SL_PLATFORM != SL_PLATFORM_NON_OS)*/
diff --git a/cc3200/simplelink/source/nonos.h b/cc3200/simplelink/source/nonos.h
new file mode 100644
index 0000000000..a888a90cf9
--- /dev/null
+++ b/cc3200/simplelink/source/nonos.h
@@ -0,0 +1,325 @@
+/*
+ * nonos.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __NONOS_H__
+#define __NONOS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifndef SL_PLATFORM_MULTI_THREADED
+
+/* This function call the user defined function, if defined, from the sync wait loop */
+/* The use case of this function is to allow nonos system to call a user function to put the device into sleep */
+/* The wake up should be activated after getting an interrupt from the device to Host */
+/* The user function must return without blocking to prevent a delay on the event handling */
+/*
+#define _SlSyncWaitLoopCallback UserSleepFunction
+*/
+
+
+
+#define NONOS_WAIT_FOREVER 0xFF
+#define NONOS_NO_WAIT 0x01
+
+#define NONOS_RET_OK (0)
+#define NONOS_RET_ERR (0xFF)
+#define OSI_OK NONOS_RET_OK
+
+#define __NON_OS_SYNC_OBJ_CLEAR_VALUE 0x11
+#define __NON_OS_SYNC_OBJ_SIGNAL_VALUE 0x22
+#define __NON_OS_LOCK_OBJ_UNLOCK_VALUE 0x33
+#define __NON_OS_LOCK_OBJ_LOCK_VALUE 0x44
+
+/*!
+ \brief type definition for the return values of this adaptation layer
+*/
+typedef _i8 _SlNonOsRetVal_t;
+
+/*!
+ \brief type definition for a time value
+*/
+typedef _u8 _SlNonOsTime_t;
+
+/*!
+ \brief type definition for a sync object container
+
+ Sync object is object used to synchronize between two threads or thread and interrupt handler.
+ One thread is waiting on the object and the other thread send a signal, which then
+ release the waiting thread.
+ The signal must be able to be sent from interrupt context.
+ This object is generally implemented by binary semaphore or events.
+*/
+typedef _u8 _SlNonOsSemObj_t;
+
+
+#define _SlTime_t _SlNonOsTime_t
+
+#define _SlSyncObj_t _SlNonOsSemObj_t
+
+#define _SlLockObj_t _SlNonOsSemObj_t
+
+#define SL_OS_WAIT_FOREVER NONOS_WAIT_FOREVER
+
+#define SL_OS_RET_CODE_OK NONOS_RET_OK
+
+#define SL_OS_NO_WAIT NONOS_NO_WAIT
+
+
+
+
+
+/*!
+ \brief This function creates a sync object
+
+ The sync object is used for synchronization between different thread or ISR and
+ a thread.
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful creation the function return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsSyncObjCreate(pSyncObj) _SlNonOsSemSet(pSyncObj,__NON_OS_SYNC_OBJ_CLEAR_VALUE)
+
+/*!
+ \brief This function deletes a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsSyncObjDelete(pSyncObj) _SlNonOsSemSet(pSyncObj,0)
+
+/*!
+ \brief This function generates a sync signal for the object.
+
+ All suspended threads waiting on this sync object are resumed
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signaling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function could be called from ISR context
+ \warning
+*/
+#define _SlNonOsSyncObjSignal(pSyncObj) _SlNonOsSemSet(pSyncObj,__NON_OS_SYNC_OBJ_SIGNAL_VALUE)
+
+/*!
+ \brief This function waits for a sync signal of the specific sync object
+
+ \param pSyncObj - pointer to the sync object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the sync signal
+ Currently, the simple link driver uses only two values:
+ - NONOS_WAIT_FOREVER
+ - NONOS_NO_WAIT
+
+ \return upon successful reception of the signal within the timeout window return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsSyncObjWait(pSyncObj , Timeout) _SlNonOsSemGet(pSyncObj,__NON_OS_SYNC_OBJ_SIGNAL_VALUE,__NON_OS_SYNC_OBJ_CLEAR_VALUE,Timeout)
+
+/*!
+ \brief This function clears a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful clearing the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsSyncObjClear(pSyncObj) _SlNonOsSemSet(pSyncObj,__NON_OS_SYNC_OBJ_CLEAR_VALUE)
+
+/*!
+ \brief This function creates a locking object.
+
+ The locking object is used for protecting a shared resources between different
+ threads.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsLockObjCreate(pLockObj) _SlNonOsSemSet(pLockObj,__NON_OS_LOCK_OBJ_UNLOCK_VALUE)
+
+/*!
+ \brief This function deletes a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsLockObjDelete(pLockObj) _SlNonOsSemSet(pLockObj,0)
+
+/*!
+ \brief This function locks a locking object.
+
+ All other threads that call this function before this thread calls
+ the _SlNonOsLockObjUnlock would be suspended
+
+ \param pLockObj - pointer to the locking object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the locking object
+ Currently, the simple link driver uses only two values:
+ - NONOS_WAIT_FOREVER
+ - NONOS_NO_WAIT
+
+
+ \return upon successful reception of the locking object the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsLockObjLock(pLockObj , Timeout) _SlNonOsSemGet(pLockObj,__NON_OS_LOCK_OBJ_UNLOCK_VALUE,__NON_OS_LOCK_OBJ_LOCK_VALUE,Timeout)
+
+/*!
+ \brief This function unlock a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful unlocking the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+#define _SlNonOsLockObjUnlock(pLockObj) _SlNonOsSemSet(pLockObj,__NON_OS_LOCK_OBJ_UNLOCK_VALUE)
+
+
+/*!
+ \brief This function call the pEntry callback from a different context
+
+ \param pEntry - pointer to the entry callback function
+
+ \param pValue - pointer to any type of memory structure that would be
+ passed to pEntry callback from the execution thread.
+
+ \param flags - execution flags - reserved for future usage
+
+ \return upon successful registration of the spawn the function return 0
+ (the function is not blocked till the end of the execution of the function
+ and could be returned before the execution is actually completed)
+ Otherwise, a negative value indicating the error code shall be returned
+ \note
+ \warning
+*/
+_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags);
+
+
+/*!
+ \brief This function must be called from the main loop in non-os paltforms
+
+ \param None
+
+ \return 0 - No more activities
+ 1 - Activity still in progress
+ \note
+ \warning
+*/
+_SlNonOsRetVal_t _SlNonOsMainLoopTask(void);
+
+extern _SlNonOsRetVal_t _SlNonOsSemGet(_SlNonOsSemObj_t* pSyncObj, _SlNonOsSemObj_t WaitValue, _SlNonOsSemObj_t SetValue, _SlNonOsTime_t Timeout);
+extern _SlNonOsRetVal_t _SlNonOsSemSet(_SlNonOsSemObj_t* pSemObj , _SlNonOsSemObj_t Value);
+extern _SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags);
+
+#if (defined(_SlSyncWaitLoopCallback))
+extern void _SlSyncWaitLoopCallback(void);
+#endif
+
+
+/*****************************************************************************
+
+ Overwrite SimpleLink driver OS adaptation functions
+
+
+ *****************************************************************************/
+
+#undef sl_SyncObjCreate
+#define sl_SyncObjCreate(pSyncObj,pName) _SlNonOsSemSet(pSyncObj,__NON_OS_SYNC_OBJ_CLEAR_VALUE)
+
+#undef sl_SyncObjDelete
+#define sl_SyncObjDelete(pSyncObj) _SlNonOsSemSet(pSyncObj,0)
+
+#undef sl_SyncObjSignal
+#define sl_SyncObjSignal(pSyncObj) _SlNonOsSemSet(pSyncObj,__NON_OS_SYNC_OBJ_SIGNAL_VALUE)
+
+#undef sl_SyncObjSignalFromIRQ
+#define sl_SyncObjSignalFromIRQ(pSyncObj) _SlNonOsSemSet(pSyncObj,__NON_OS_SYNC_OBJ_SIGNAL_VALUE)
+
+#undef sl_SyncObjWait
+#define sl_SyncObjWait(pSyncObj,Timeout) _SlNonOsSemGet(pSyncObj,__NON_OS_SYNC_OBJ_SIGNAL_VALUE,__NON_OS_SYNC_OBJ_CLEAR_VALUE,Timeout)
+
+#undef sl_LockObjCreate
+#define sl_LockObjCreate(pLockObj,pName) _SlNonOsSemSet(pLockObj,__NON_OS_LOCK_OBJ_UNLOCK_VALUE)
+
+#undef sl_LockObjDelete
+#define sl_LockObjDelete(pLockObj) _SlNonOsSemSet(pLockObj,0)
+
+#undef sl_LockObjLock
+#define sl_LockObjLock(pLockObj,Timeout) _SlNonOsSemGet(pLockObj,__NON_OS_LOCK_OBJ_UNLOCK_VALUE,__NON_OS_LOCK_OBJ_LOCK_VALUE,Timeout)
+
+#undef sl_LockObjUnlock
+#define sl_LockObjUnlock(pLockObj) _SlNonOsSemSet(pLockObj,__NON_OS_LOCK_OBJ_UNLOCK_VALUE)
+
+#undef sl_Spawn
+#define sl_Spawn(pEntry,pValue,flags) _SlNonOsSpawn(pEntry,pValue,flags)
+
+#undef _SlTaskEntry
+#define _SlTaskEntry _SlNonOsMainLoopTask
+
+#endif /* !SL_PLATFORM_MULTI_THREADED */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/cc3200/simplelink/source/objInclusion.h b/cc3200/simplelink/source/objInclusion.h
new file mode 100644
index 0000000000..c636724057
--- /dev/null
+++ b/cc3200/simplelink/source/objInclusion.h
@@ -0,0 +1,325 @@
+/*
+ * objInclusion.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#include
+
+#ifndef OBJINCLUSION_H_
+#define OBJINCLUSION_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+
+ For future use
+
+*******************************************************************************/
+
+#define __inln /* if inline functions requiered: #define __inln inline */
+
+#define SL_DEVICE /* Device silo is currently always mandatory */
+
+
+
+/******************************************************************************
+
+ Qualifiers for package customizations
+
+*******************************************************************************/
+
+#if defined (SL_DEVICE)
+#define __dev 1
+#else
+#define __dev 0
+#endif
+
+#if defined (SL_DEVICE) && defined (SL_INC_EXT_API)
+#define __dev__ext 1
+#else
+#define __dev__ext 0
+#endif
+
+
+#if (!defined (SL_PLATFORM_MULTI_THREADED)) || (!defined (SL_PLATFORM_EXTERNAL_SPAWN))
+#define __int__spwn 1
+#else
+#define __int__spwn 0
+#endif
+
+#if defined (SL_INC_NET_APP_PKG)
+#define __nap 1
+#else
+#define __nap 0
+#endif
+
+#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API)
+#define __nap__clt 1
+#else
+#define __nap__clt 0
+#endif
+
+#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_EXT_API)
+#define __nap__ext 1
+#else
+#define __nap__ext 0
+#endif
+
+#if defined (SL_INC_NET_CFG_PKG)
+#define __ncg 1
+#else
+#define __ncg 0
+#endif
+
+#if defined (SL_INC_NET_CFG_PKG) && defined (SL_INC_EXT_API)
+#define __ncg__ext 1
+#else
+#define __ncg__ext 0
+#endif
+
+#if defined (SL_INC_NVMEM_PKG)
+#define __nvm 1
+#else
+#define __nvm 0
+#endif
+
+#if defined (SL_INC_SOCKET_PKG)
+#define __sck 1
+#else
+#define __sck 0
+#endif
+
+#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_EXT_API)
+#define __sck__ext 1
+#else
+#define __sck__ext 0
+#endif
+
+#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SERVER_SIDE_API)
+#define __sck__srv 1
+#else
+#define __sck__srv 0
+#endif
+
+#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API)
+#define __sck__clt 1
+#else
+#define __sck__clt 0
+#endif
+
+#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_RECV_API)
+#define __sck__rcv 1
+#else
+#define __sck__rcv 0
+#endif
+
+#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SEND_API)
+#define __sck__snd 1
+#else
+#define __sck__snd 0
+#endif
+
+#if defined (SL_INC_WLAN_PKG)
+#define __wln 1
+#else
+#define __wln 0
+#endif
+
+#if defined (SL_INC_WLAN_PKG) && defined (SL_INC_EXT_API)
+#define __wln__ext 1
+#else
+#define __wln__ext 0
+#endif
+
+/* The return 1 is the function need to be included in the output */
+#define _SL_INCLUDE_FUNC(Name) (_SL_INC_##Name)
+
+/* Driver */
+#define _SL_INC_sl_NetAppStart __nap
+
+#define _SL_INC_sl_NetAppStop __nap
+
+#define _SL_INC_sl_NetAppDnsGetHostByName __nap__clt
+
+
+#define _SL_INC_sl_NetAppDnsGetHostByService __nap__clt
+#define _SL_INC_sl_NetAppMDNSRegisterService __nap__clt
+#define _SL_INC_sl_NetAppMDNSUnRegisterService __nap__clt
+#define _SL_INC_sl_NetAppMDNSRegisterUnregisterService __nap__clt
+#define _SL_INC_sl_NetAppGetServiceList __nap__clt
+
+
+#define _SL_INC_sl_DnsGetHostByAddr __nap__ext
+
+#define _SL_INC_sl_NetAppPingStart __nap
+
+#define _SL_INC_sl_NetAppPingReport __nap
+
+/* FS */
+#define _SL_INC_sl_FsOpen __nvm
+
+#define _SL_INC_sl_FsClose __nvm
+
+#define _SL_INC_sl_FsRead __nvm
+
+#define _SL_INC_sl_FsWrite __nvm
+
+#define _SL_INC_sl_FsGetInfo __nvm
+
+#define _SL_INC_sl_FsDel __nvm
+
+/* netcfg */
+#define _SL_INC_sl_MacAdrrSet __ncg
+
+#define _SL_INC_sl_MacAdrrGet __ncg
+
+#define _SL_INC_sl_NetCfgGet __ncg
+
+#define _SL_INC_sl_NetCfgSet __ncg
+
+#define _SL_INC_sl_NetAppSet __nap
+
+#define _SL_INC_sl_NetAppGet __nap
+
+/* socket */
+#define _SL_INC_sl_Socket __sck
+
+#define _SL_INC_sl_Close __sck__ext
+
+#define _SL_INC_sl_Accept __sck__srv
+
+#define _SL_INC_sl_Bind __sck
+
+#define _SL_INC_sl_Listen __sck__srv
+
+#define _SL_INC_sl_Connect __sck__clt
+
+#define _SL_INC_sl_Select __sck
+
+#define _SL_INC_sl_SetSockOpt __sck
+
+#define _SL_INC_sl_GetSockOpt __sck__ext
+
+#define _SL_INC_sl_Recv __sck__rcv
+
+#define _SL_INC_sl_RecvFrom __sck__rcv
+
+#define _SL_INC_sl_Write __sck__snd
+
+#define _SL_INC_sl_Send __sck__snd
+
+#define _SL_INC_sl_SendTo __sck__snd
+
+#define _SL_INC_sl_Htonl __sck
+
+#define _SL_INC_sl_Htons __sck
+
+/* wlan */
+#define _SL_INC_sl_WlanConnect __wln__ext
+
+#define _SL_INC_sl_WlanDisconnect __wln__ext
+
+#define _SL_INC_sl_WlanProfileAdd __wln__ext
+
+#define _SL_INC_sl_WlanProfileGet __wln__ext
+
+#define _SL_INC_sl_WlanProfileDel __wln__ext
+
+#define _SL_INC_sl_WlanPolicySet __wln__ext
+
+#define _SL_INC_sl_WlanPolicyGet __wln__ext
+
+#define _SL_INC_sl_WlanGetNetworkList __wln__ext
+
+#define _SL_INC_sl_WlanRxFilterAdd __wln__ext
+
+#define _SL_INC_sl_WlanRxFilterSet __wln__ext
+
+#define _SL_INC_sl_WlanRxFilterGet __wln__ext
+
+#define _SL_INC_sl_SmartConfigStart __wln
+
+#define _SL_INC_sl_SmartConfigOptSet __wln__ext
+
+
+#define _SL_INC_sl_WlanSmartConfigStart __wln
+
+#define _SL_INC_sl_WlanSmartConfigStop __wln
+
+#define _SL_INC_sl_WlanSetMode __wln
+
+#define _SL_INC_sl_WlanSet __wln
+
+#define _SL_INC_sl_WlanGet __wln
+
+#define _SL_INC_sl_SmartConfigOptSet __wln__ext
+
+#define _SL_INC_sl_SmartConfigOptGet __wln__ext
+
+#define _SL_INC_sl_WlanRxStatStart __wln__ext
+
+#define _SL_INC_sl_WlanRxStatStop __wln__ext
+
+#define _SL_INC_sl_WlanRxStatGet __wln__ext
+
+
+/* device */
+#define _SL_INC_sl_Task __int__spwn
+
+#define _SL_INC_sl_Start __dev
+
+#define _SL_INC_sl_Stop __dev
+
+#define _SL_INC_sl_StatusGet __dev
+
+#ifdef SL_IF_TYPE_UART
+#define _SL_INC_sl_UartSetMode __dev
+#endif
+
+#define _SL_INC_sl_EventMaskGet __dev__ext
+
+#define _SL_INC_sl_EventMaskSet __dev__ext
+
+#define _SL_INC_sl_DevGet __dev__ext
+
+#define _SL_INC_sl_DevSet __dev__ext
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /*OBJINCLUSION_H_ */
diff --git a/cc3200/simplelink/source/protocol.h b/cc3200/simplelink/source/protocol.h
new file mode 100644
index 0000000000..f83ad4c3df
--- /dev/null
+++ b/cc3200/simplelink/source/protocol.h
@@ -0,0 +1,1176 @@
+/*
+ * protocol.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/*******************************************************************************\
+*
+* FILE NAME: protocol.h
+*
+* DESCRIPTION: Constant and data structure definitions and function
+* prototypes for the SL protocol module, which implements
+* processing of SimpleLink Commands.
+*
+* AUTHOR:
+*
+\*******************************************************************************/
+
+#ifndef _SL_PROTOCOL_TYPES_H_
+#define _SL_PROTOCOL_TYPES_H_
+
+/****************************************************************************
+**
+** User I/F pools definitions
+**
+****************************************************************************/
+
+/****************************************************************************
+**
+** Definitions for SimpleLink Commands
+**
+****************************************************************************/
+
+
+/* pattern for LE 8/16/32 or BE*/
+#define H2N_SYNC_PATTERN {0xBBDDEEFF,0x4321,0x34,0x12}
+#define H2N_CNYS_PATTERN {0xBBDDEEFF,0x8765,0x78,0x56}
+
+#define H2N_DUMMY_PATTERN (_u32)0xFFFFFFFF
+#define N2H_SYNC_PATTERN (_u32)0xABCDDCBA
+#define SYNC_PATTERN_LEN (_u32)sizeof(_u32)
+#define UART_SET_MODE_MAGIC_CODE (_u32)0xAA55AA55
+#define SPI_16BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFF7FFF)
+#define SPI_8BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFFFF7F)
+
+
+
+typedef struct
+{
+ _u16 Opcode;
+ _u16 Len;
+}_SlGenericHeader_t;
+
+
+typedef struct
+{
+ _u32 Long;
+ _u16 Short;
+ _u8 Byte1;
+ _u8 Byte2;
+}_SlSyncPattern_t;
+
+typedef _SlGenericHeader_t _SlCommandHeader_t;
+
+typedef struct
+{
+ _SlGenericHeader_t GenHeader;
+ _u8 TxPoolCnt;
+ _u8 DevStatus;
+ _u8 SocketTXFailure;
+ _u8 SocketNonBlocking;
+}_SlResponseHeader_t;
+
+#define _SL_RESP_SPEC_HDR_SIZE (sizeof(_SlResponseHeader_t) - sizeof(_SlGenericHeader_t))
+#define _SL_RESP_HDR_SIZE sizeof(_SlResponseHeader_t)
+#define _SL_CMD_HDR_SIZE sizeof(_SlCommandHeader_t)
+
+#define _SL_RESP_ARGS_START(_pMsg) (((_SlResponseHeader_t *)(_pMsg)) + 1)
+
+/* Used only in NWP! */
+typedef struct
+{
+ _SlCommandHeader_t sl_hdr;
+ _u8 func_args_start;
+} T_SCMD;
+
+
+#define WLAN_CONN_STATUS_BIT 0x01
+#define EVENTS_Q_STATUS_BIT 0x02
+#define PENDING_RCV_CMD_BIT 0x04
+#define FW_BUSY_PACKETS_BIT 0x08
+
+#define INIT_STA_OK 0x11111111
+#define INIT_STA_ERR 0x22222222
+#define INIT_AP_OK 0x33333333
+#define INIT_AP_ERR 0x44444444
+#define INIT_P2P_OK 0x55555555
+#define INIT_P2P_ERR 0x66666666
+
+/****************************************************************************
+** OPCODES
+****************************************************************************/
+#define SL_IPV4_IPV6_OFFSET ( 9 )
+#define SL_OPCODE_IPV4 ( 0x0 << SL_IPV4_IPV6_OFFSET )
+#define SL_OPCODE_IPV6 ( 0x1 << SL_IPV4_IPV6_OFFSET )
+
+#define SL_SYNC_ASYNC_OFFSET ( 10 )
+#define SL_OPCODE_SYNC (0x1 << SL_SYNC_ASYNC_OFFSET )
+#define SL_OPCODE_SILO_OFFSET ( 11 )
+#define SL_OPCODE_SILO_MASK ( 0xF << SL_OPCODE_SILO_OFFSET )
+#define SL_OPCODE_SILO_DEVICE ( 0x0 << SL_OPCODE_SILO_OFFSET )
+#define SL_OPCODE_SILO_WLAN ( 0x1 << SL_OPCODE_SILO_OFFSET )
+#define SL_OPCODE_SILO_SOCKET ( 0x2 << SL_OPCODE_SILO_OFFSET )
+#define SL_OPCODE_SILO_NETAPP ( 0x3 << SL_OPCODE_SILO_OFFSET )
+#define SL_OPCODE_SILO_NVMEM ( 0x4 << SL_OPCODE_SILO_OFFSET )
+#define SL_OPCODE_SILO_NETCFG ( 0x5 << SL_OPCODE_SILO_OFFSET )
+
+#define SL_FAMILY_SHIFT (0x4)
+#define SL_FLAGS_MASK (0xF)
+
+#define SL_OPCODE_DEVICE_INITCOMPLETE 0x0008
+#define SL_OPCODE_DEVICE_STOP_COMMAND 0x8473
+#define SL_OPCODE_DEVICE_STOP_RESPONSE 0x0473
+#define SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE 0x0073
+#define SL_OPCODE_DEVICE_DEVICEASYNCDUMMY 0x0063
+
+#define SL_OPCODE_DEVICE_VERSIONREADCOMMAND 0x8470
+#define SL_OPCODE_DEVICE_VERSIONREADRESPONSE 0x0470
+#define SL_OPCODE_DEVICE_DEVICEASYNCFATALERROR 0x0078
+#define SL_OPCODE_WLAN_WLANCONNECTCOMMAND 0x8C80
+#define SL_OPCODE_WLAN_WLANCONNECTRESPONSE 0x0C80
+#define SL_OPCODE_WLAN_WLANASYNCCONNECTEDRESPONSE 0x0880
+#define SL_OPCODE_WLAN_P2P_DEV_FOUND 0x0830
+#define SL_OPCODE_WLAN_CONNECTION_FAILED 0x0831
+#define SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED 0x0832
+
+#define SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND 0x8C81
+#define SL_OPCODE_WLAN_WLANDISCONNECTRESPONSE 0x0C81
+#define SL_OPCODE_WLAN_WLANASYNCDISCONNECTEDRESPONSE 0x0881
+#define SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND 0x8C82
+#define SL_OPCODE_WLAN_WLANCONNECTEAPCRESPONSE 0x0C82
+#define SL_OPCODE_WLAN_PROFILEADDCOMMAND 0x8C83
+#define SL_OPCODE_WLAN_PROFILEADDRESPONSE 0x0C83
+#define SL_OPCODE_WLAN_PROFILEGETCOMMAND 0x8C84
+#define SL_OPCODE_WLAN_PROFILEGETRESPONSE 0x0C84
+#define SL_OPCODE_WLAN_PROFILEDELCOMMAND 0x8C85
+#define SL_OPCODE_WLAN_PROFILEDELRESPONSE 0x0C85
+#define SL_OPCODE_WLAN_POLICYSETCOMMAND 0x8C86
+#define SL_OPCODE_WLAN_POLICYSETRESPONSE 0x0C86
+#define SL_OPCODE_WLAN_POLICYGETCOMMAND 0x8C87
+#define SL_OPCODE_WLAN_POLICYGETRESPONSE 0x0C87
+#define SL_OPCODE_WLAN_FILTERADD 0x8C88
+#define SL_OPCODE_WLAN_FILTERADDRESPONSE 0x0C88
+#define SL_OPCODE_WLAN_FILTERGET 0x8C89
+#define SL_OPCODE_WLAN_FILTERGETRESPONSE 0x0C89
+#define SL_OPCODE_WLAN_FILTERDELETE 0x8C8A
+#define SL_OPCODE_WLAN_FILTERDELETERESPOSNE 0x0C8A
+#define SL_OPCODE_WLAN_WLANGETSTATUSCOMMAND 0x8C8F
+#define SL_OPCODE_WLAN_WLANGETSTATUSRESPONSE 0x0C8F
+#define SL_OPCODE_WLAN_STARTTXCONTINUESCOMMAND 0x8CAA
+#define SL_OPCODE_WLAN_STARTTXCONTINUESRESPONSE 0x0CAA
+#define SL_OPCODE_WLAN_STOPTXCONTINUESCOMMAND 0x8CAB
+#define SL_OPCODE_WLAN_STOPTXCONTINUESRESPONSE 0x0CAB
+#define SL_OPCODE_WLAN_STARTRXSTATCOMMAND 0x8CAC
+#define SL_OPCODE_WLAN_STARTRXSTATRESPONSE 0x0CAC
+#define SL_OPCODE_WLAN_STOPRXSTATCOMMAND 0x8CAD
+#define SL_OPCODE_WLAN_STOPRXSTATRESPONSE 0x0CAD
+#define SL_OPCODE_WLAN_GETRXSTATCOMMAND 0x8CAF
+#define SL_OPCODE_WLAN_GETRXSTATRESPONSE 0x0CAF
+#define SL_OPCODE_WLAN_POLICYSETCOMMANDNEW 0x8CB0
+#define SL_OPCODE_WLAN_POLICYSETRESPONSENEW 0x0CB0
+#define SL_OPCODE_WLAN_POLICYGETCOMMANDNEW 0x8CB1
+#define SL_OPCODE_WLAN_POLICYGETRESPONSENEW 0x0CB1
+
+#define SL_OPCODE_WLAN_SMART_CONFIG_START_COMMAND 0x8CB2
+#define SL_OPCODE_WLAN_SMART_CONFIG_START_RESPONSE 0x0CB2
+#define SL_OPCODE_WLAN_SMART_CONFIG_START_ASYNC_RESPONSE 0x08B2
+#define SL_OPCODE_WLAN_SMART_CONFIG_STOP_COMMAND 0x8CB3
+#define SL_OPCODE_WLAN_SMART_CONFIG_STOP_RESPONSE 0x0CB3
+#define SL_OPCODE_WLAN_SMART_CONFIG_STOP_ASYNC_RESPONSE 0x08B3
+#define SL_OPCODE_WLAN_SET_MODE 0x8CB4
+#define SL_OPCODE_WLAN_SET_MODE_RESPONSE 0x0CB4
+#define SL_OPCODE_WLAN_CFG_SET 0x8CB5
+#define SL_OPCODE_WLAN_CFG_SET_RESPONSE 0x0CB5
+#define SL_OPCODE_WLAN_CFG_GET 0x8CB6
+#define SL_OPCODE_WLAN_CFG_GET_RESPONSE 0x0CB6
+#define SL_OPCODE_WLAN_STA_CONNECTED 0x082E
+#define SL_OPCODE_WLAN_STA_DISCONNECTED 0x082F
+#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND 0x8C67
+#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND_RESPONSE 0x0C67
+
+#define SL_OPCODE_SOCKET_SOCKET 0x9401
+#define SL_OPCODE_SOCKET_SOCKETRESPONSE 0x1401
+#define SL_OPCODE_SOCKET_CLOSE 0x9402
+#define SL_OPCODE_SOCKET_CLOSERESPONSE 0x1402
+#define SL_OPCODE_SOCKET_ACCEPT 0x9403
+#define SL_OPCODE_SOCKET_ACCEPTRESPONSE 0x1403
+#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE 0x1003
+#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 0x1203
+#define SL_OPCODE_SOCKET_BIND 0x9404
+#define SL_OPCODE_SOCKET_BIND_V6 0x9604
+#define SL_OPCODE_SOCKET_BINDRESPONSE 0x1404
+#define SL_OPCODE_SOCKET_LISTEN 0x9405
+#define SL_OPCODE_SOCKET_LISTENRESPONSE 0x1405
+#define SL_OPCODE_SOCKET_CONNECT 0x9406
+#define SL_OPCODE_SOCKET_CONNECT_V6 0x9606
+#define SL_OPCODE_SOCKET_CONNECTRESPONSE 0x1406
+#define SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE 0x1006
+#define SL_OPCODE_SOCKET_SELECT 0x9407
+#define SL_OPCODE_SOCKET_SELECTRESPONSE 0x1407
+#define SL_OPCODE_SOCKET_SELECTASYNCRESPONSE 0x1007
+#define SL_OPCODE_SOCKET_SETSOCKOPT 0x9408
+#define SL_OPCODE_SOCKET_SETSOCKOPTRESPONSE 0x1408
+#define SL_OPCODE_SOCKET_GETSOCKOPT 0x9409
+#define SL_OPCODE_SOCKET_GETSOCKOPTRESPONSE 0x1409
+#define SL_OPCODE_SOCKET_RECV 0x940A
+#define SL_OPCODE_SOCKET_RECVASYNCRESPONSE 0x100A
+#define SL_OPCODE_SOCKET_RECVFROM 0x940B
+#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE 0x100B
+#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 0x120B
+#define SL_OPCODE_SOCKET_SEND 0x940C
+#define SL_OPCODE_SOCKET_SENDTO 0x940D
+#define SL_OPCODE_SOCKET_SENDTO_V6 0x960D
+#define SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE 0x100E
+#define SL_OPCODE_SOCKET_SOCKETASYNCEVENT 0x100F
+#define SL_OPCODE_NETAPP_START_COMMAND 0x9C0A
+#define SL_OPCODE_NETAPP_START_RESPONSE 0x1C0A
+#define SL_OPCODE_NETAPP_NETAPPSTARTRESPONSE 0x1C0A
+#define SL_OPCODE_NETAPP_STOP_COMMAND 0x9C61
+#define SL_OPCODE_NETAPP_STOP_RESPONSE 0x1C61
+#define SL_OPCODE_NETAPP_NETAPPSET 0x9C0B
+#define SL_OPCODE_NETAPP_NETAPPSETRESPONSE 0x1C0B
+#define SL_OPCODE_NETAPP_NETAPPGET 0x9C27
+#define SL_OPCODE_NETAPP_NETAPPGETRESPONSE 0x1C27
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAME 0x9C20
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMERESPONSE 0x1C20
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE 0x1820
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6 0x1A20
+#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE 0x9C71
+#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE_RESPONSE 0x1C72
+#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICE 0x9C34
+#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICERESPONSE 0x1C34
+#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE 0x9C35
+#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICERESPONSE 0x1C35
+#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE 0x1835
+#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6 0x1A35
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR 0x9C26
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR_V6 0x9E26
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRRESPONSE 0x1C26
+#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRASYNCRESPONSE 0x1826
+#define SL_OPCODE_NETAPP_PINGSTART 0x9C21
+#define SL_OPCODE_NETAPP_PINGSTART_V6 0x9E21
+#define SL_OPCODE_NETAPP_PINGSTARTRESPONSE 0x1C21
+#define SL_OPCODE_NETAPP_PINGREPORTREQUEST 0x9C22
+#define SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE 0x1822
+#define SL_OPCODE_NETAPP_PINGSTOP 0x9C23
+#define SL_OPCODE_NETAPP_PINGSTOPRESPONSE 0x1C23
+#define SL_OPCODE_NETAPP_ARPFLUSH 0x9C24
+#define SL_OPCODE_NETAPP_ARPFLUSHRESPONSE 0x1C24
+#define SL_OPCODE_NETAPP_IPACQUIRED 0x1825
+#define SL_OPCODE_NETAPP_IPV4_LOST 0x1832
+#define SL_OPCODE_NETAPP_DHCP_IPV4_ACQUIRE_TIMEOUT 0x1833
+#define SL_OPCODE_NETAPP_IPACQUIRED_V6 0x1A25
+#define SL_OPCODE_NETAPP_IPERFSTARTCOMMAND 0x9C28
+#define SL_OPCODE_NETAPP_IPERFSTARTRESPONSE 0x1C28
+#define SL_OPCODE_NETAPP_IPERFSTOPCOMMAND 0x9C29
+#define SL_OPCODE_NETAPP_IPERFSTOPRESPONSE 0x1C29
+#define SL_OPCODE_NETAPP_CTESTSTARTCOMMAND 0x9C2A
+#define SL_OPCODE_NETAPP_CTESTSTARTRESPONSE 0x1C2A
+#define SL_OPCODE_NETAPP_CTESTASYNCRESPONSE 0x182A
+#define SL_OPCODE_NETAPP_CTESTSTOPCOMMAND 0x9C2B
+#define SL_OPCODE_NETAPP_CTESTSTOPRESPONSE 0x1C2B
+#define SL_OPCODE_NETAPP_IP_LEASED 0x182C
+#define SL_OPCODE_NETAPP_IP_RELEASED 0x182D
+#define SL_OPCODE_NETAPP_HTTPGETTOKENVALUE 0x182E
+#define SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE 0x9C2F
+#define SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE 0x1830
+#define SL_OPCODE_NVMEM_FILEOPEN 0xA43C
+#define SL_OPCODE_NVMEM_FILEOPENRESPONSE 0x243C
+#define SL_OPCODE_NVMEM_FILECLOSE 0xA43D
+#define SL_OPCODE_NVMEM_FILECLOSERESPONSE 0x243D
+#define SL_OPCODE_NVMEM_FILEREADCOMMAND 0xA440
+#define SL_OPCODE_NVMEM_FILEREADRESPONSE 0x2440
+#define SL_OPCODE_NVMEM_FILEWRITECOMMAND 0xA441
+#define SL_OPCODE_NVMEM_FILEWRITERESPONSE 0x2441
+#define SL_OPCODE_NVMEM_FILEGETINFOCOMMAND 0xA442
+#define SL_OPCODE_NVMEM_FILEGETINFORESPONSE 0x2442
+#define SL_OPCODE_NVMEM_FILEDELCOMMAND 0xA443
+#define SL_OPCODE_NVMEM_FILEDELRESPONSE 0x2443
+#define SL_OPCODE_NVMEM_NVMEMFORMATCOMMAND 0xA444
+#define SL_OPCODE_NVMEM_NVMEMFORMATRESPONSE 0x2444
+
+#define SL_OPCODE_DEVICE_SETDEBUGLEVELCOMMAND 0x846A
+#define SL_OPCODE_DEVICE_SETDEBUGLEVELRESPONSE 0x046A
+
+#define SL_OPCODE_DEVICE_NETCFG_SET_COMMAND 0x8432
+#define SL_OPCODE_DEVICE_NETCFG_SET_RESPONSE 0x0432
+#define SL_OPCODE_DEVICE_NETCFG_GET_COMMAND 0x8433
+#define SL_OPCODE_DEVICE_NETCFG_GET_RESPONSE 0x0433
+/* */
+#define SL_OPCODE_DEVICE_SETUARTMODECOMMAND 0x846B
+#define SL_OPCODE_DEVICE_SETUARTMODERESPONSE 0x046B
+#define SL_OPCODE_DEVICE_SSISIZESETCOMMAND 0x846B
+#define SL_OPCODE_DEVICE_SSISIZESETRESPONSE 0x046B
+
+/* */
+#define SL_OPCODE_DEVICE_EVENTMASKSET 0x8464
+#define SL_OPCODE_DEVICE_EVENTMASKSETRESPONSE 0x0464
+#define SL_OPCODE_DEVICE_EVENTMASKGET 0x8465
+#define SL_OPCODE_DEVICE_EVENTMASKGETRESPONSE 0x0465
+
+#define SL_OPCODE_DEVICE_DEVICEGET 0x8466
+#define SL_OPCODE_DEVICE_DEVICEGETRESPONSE 0x0466
+#define SL_OPCODE_DEVICE_DEVICESET 0x84B7
+#define SL_OPCODE_DEVICE_DEVICESETRESPONSE 0x04B7
+
+#define SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND 0x8C8C
+#define SL_OPCODE_WLAN_SCANRESULTSGETRESPONSE 0x0C8C
+#define SL_OPCODE_WLAN_SMARTCONFIGOPTSET 0x8C8D
+#define SL_OPCODE_WLAN_SMARTCONFIGOPTSETRESPONSE 0x0C8D
+#define SL_OPCODE_WLAN_SMARTCONFIGOPTGET 0x8C8E
+#define SL_OPCODE_WLAN_SMARTCONFIGOPTGETRESPONSE 0x0C8E
+
+#define SL_OPCODE_FREE_BSD_RECV_BUFFER 0xCCCB
+#define SL_OPCODE_FREE_NON_BSD_READ_BUFFER 0xCCCD
+
+
+/* Rx Filters opcodes */
+#define SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND 0x8C6C
+#define SL_OPCODE_WLAN_WLANRXFILTERADDRESPONSE 0x0C6C
+#define SL_OPCODE_WLAN_WLANRXFILTERSETCOMMAND 0x8C6D
+#define SL_OPCODE_WLAN_WLANRXFILTERSETRESPONSE 0x0C6D
+#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFOCOMMAND 0x8C6E
+#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFORESPONSE 0x0C6E
+#define SL_OPCODE_WLAN_WLANRXFILTERGETCOMMAND 0x8C6F
+#define SL_OPCODE_WLAN_WLANRXFILTERGETRESPONSE 0x0C6F
+#define SL_OPCODE_WLAN_WLANRXFILTERGETINFO 0x8C70
+#define SL_OPCODE_WLAN_WLANRXFILTERGETINFORESPONSE 0x0C70
+
+
+/******************************************************************************************/
+/* Device structs */
+/******************************************************************************************/
+typedef _u32 InitStatus_t;
+
+
+typedef struct
+{
+ _i32 Status;
+}InitComplete_t;
+
+typedef struct
+{
+ _i16 status;
+ _u16 padding;
+
+}_BasicResponse_t;
+
+typedef struct
+{
+ _u16 Timeout;
+ _u16 padding;
+}_DevStopCommand_t;
+
+typedef struct
+{
+ _u32 group;
+ _u32 mask;
+}_DevMaskEventSetCommand_t;
+
+typedef _BasicResponse_t _DevMaskEventSetResponse_t;
+
+
+typedef struct
+{
+ _u32 group;
+}_DevMaskEventGetCommand_t;
+
+
+typedef struct
+{
+ _u32 group;
+ _u32 mask;
+}_DevMaskEventGetResponse_t;
+
+
+typedef struct
+{
+ _u32 group;
+}_DevStatusGetCommand_t;
+
+
+typedef struct
+{
+ _u32 group;
+ _u32 status;
+}_DevStatusGetResponse_t;
+
+typedef struct
+{
+ _u32 ChipId;
+ _u32 FwVersion[4];
+ _u8 PhyVersion[4];
+}_Device_VersionReadResponsePart_t;
+
+typedef struct
+{
+ _Device_VersionReadResponsePart_t part;
+ _u32 NwpVersion[4];
+ _u16 RomVersion;
+ _u16 Padding;
+}_Device_VersionReadResponseFull_t;
+
+
+typedef struct
+{
+ _u32 BaudRate;
+ _u8 FlowControlEnable;
+}_DevUartSetModeCommand_t;
+
+typedef _BasicResponse_t _DevUartSetModeResponse_t;
+
+/******************************************************/
+
+typedef struct
+{
+ _u8 SsiSizeInBytes;
+ _u8 Padding[3];
+}_StellarisSsiSizeSet_t;
+
+/*****************************************************************************************/
+/* WLAN structs */
+/*****************************************************************************************/
+#define MAXIMAL_PASSWORD_LENGTH (64)
+
+typedef struct{
+ _u8 SecType;
+ _u8 SsidLen;
+ _u8 Bssid[6];
+ _u8 PasswordLen;
+}_WlanConnectCommon_t;
+
+#define SSID_STRING(pCmd) (_i8 *)((_WlanConnectCommon_t *)(pCmd) + 1)
+#define PASSWORD_STRING(pCmd) (SSID_STRING(pCmd) + ((_WlanConnectCommon_t *)(pCmd))->SsidLen)
+
+typedef struct{
+ _WlanConnectCommon_t Common;
+ _u8 UserLen;
+ _u8 AnonUserLen;
+ _u8 CertIndex;
+ _u32 EapBitmask;
+}_WlanConnectEapCommand_t;
+
+#define EAP_SSID_STRING(pCmd) (_i8 *)((_WlanConnectEapCommand_t *)(pCmd) + 1)
+#define EAP_PASSWORD_STRING(pCmd) (EAP_SSID_STRING(pCmd) + ((_WlanConnectEapCommand_t *)(pCmd))->Common.SsidLen)
+#define EAP_USER_STRING(pCmd) (EAP_PASSWORD_STRING(pCmd) + ((_WlanConnectEapCommand_t *)(pCmd))->Common.PasswordLen)
+#define EAP_ANON_USER_STRING(pCmd) (EAP_USER_STRING(pCmd) + ((_WlanConnectEapCommand_t *)(pCmd))->UserLen)
+
+
+typedef struct
+{
+ _u8 PolicyType;
+ _u8 Padding;
+ _u8 PolicyOption;
+ _u8 PolicyOptionLen;
+}_WlanPoliciySetGet_t;
+
+
+typedef struct{
+ _u32 minDwellTime;
+ _u32 maxDwellTime;
+ _u32 numProbeResponse;
+ _u32 G_Channels_mask;
+ _i32 rssiThershold;
+ _i32 snrThershold;
+ _i32 defaultTXPower;
+ _u16 intervalList[16];
+}_WlanScanParamSetCommand_t;
+
+
+typedef struct{
+ _i8 SecType;
+ _u8 SsidLen;
+ _u8 Priority;
+ _u8 Bssid[6];
+ _u8 PasswordLen;
+ _u8 WepKeyId;
+}_WlanAddGetProfile_t;
+
+
+typedef struct{
+ _WlanAddGetProfile_t Common;
+ _u8 UserLen;
+ _u8 AnonUserLen;
+ _u8 CertIndex;
+ _u16 padding;
+ _u32 EapBitmask;
+}_WlanAddGetEapProfile_t;
+
+
+
+
+#define PROFILE_SSID_STRING(pCmd) ((_i8 *)((_WlanAddGetProfile_t *)(pCmd) + 1))
+#define PROFILE_PASSWORD_STRING(pCmd) (PROFILE_SSID_STRING(pCmd) + ((_WlanAddGetProfile_t *)(pCmd))->SsidLen)
+
+#define EAP_PROFILE_SSID_STRING(pCmd) (_i8 *)((_WlanAddGetEapProfile_t *)(pCmd) + 1)
+#define EAP_PROFILE_PASSWORD_STRING(pCmd) (EAP_PROFILE_SSID_STRING(pCmd) + ((_WlanAddGetEapProfile_t *)(pCmd))->Common.SsidLen)
+#define EAP_PROFILE_USER_STRING(pCmd) (EAP_PROFILE_PASSWORD_STRING(pCmd) + ((_WlanAddGetEapProfile_t *)(pCmd))->Common.PasswordLen)
+#define EAP_PROFILE_ANON_USER_STRING(pCmd) (EAP_PROFILE_USER_STRING(pCmd) + ((_WlanAddGetEapProfile_t *)(pCmd))->UserLen)
+
+
+
+typedef struct
+{
+ _u8 index;
+ _u8 padding[3];
+}_WlanProfileDelGetCommand_t;
+
+typedef _BasicResponse_t _WlanGetNetworkListResponse_t;
+
+typedef struct
+{
+ _u8 index;
+ _u8 count;
+ _i8 padding[2];
+}_WlanGetNetworkListCommand_t;
+
+
+
+
+typedef struct
+{
+ _u32 groupIdBitmask;
+ _u8 cipher;
+ _u8 publicKeyLen;
+ _u8 group1KeyLen;
+ _u8 group2KeyLen;
+}_WlanSmartConfigStartCommand_t;
+
+#define SMART_CONFIG_START_PUBLIC_KEY_STRING(pCmd) ((_i8 *)((_WlanSmartConfigStartCommand_t *)(pCmd) + 1))
+#define SMART_CONFIG_START_GROUP1_KEY_STRING(pCmd) ((_i8 *) (SMART_CONFIG_START_PUBLIC_KEY_STRING(pCmd) + ((_WlanSmartConfigStartCommand_t *)(pCmd))->publicKeyLen))
+#define SMART_CONFIG_START_GROUP2_KEY_STRING(pCmd) ((_i8 *) (SMART_CONFIG_START_GROUP1_KEY_STRING(pCmd) + ((_WlanSmartConfigStartCommand_t *)(pCmd))->group1KeyLen))
+
+
+
+typedef struct
+{
+ _u8 mode;
+ _u8 padding[3];
+}_WlanSetMode_t;
+
+
+
+
+typedef struct
+{
+ _u16 Status;
+ _u16 ConfigId;
+ _u16 ConfigOpt;
+ _u16 ConfigLen;
+}_WlanCfgSetGet_t;
+
+
+/* ******************************************************************************/
+/* RX filters - Start */
+/* ******************************************************************************/
+/* -- 80 bytes */
+typedef struct _WlanRxFilterAddCommand_t
+{
+ /* -- 1 byte */
+ SlrxFilterRuleType_t RuleType;
+ /* -- 1 byte */
+ SlrxFilterFlags_t FilterFlags;
+ /* -- 1 byte */
+ SlrxFilterID_t FilterId;
+ /* -- 1 byte */
+ _u8 Padding;
+ /* -- 56 byte */
+ SlrxFilterRule_t Rule;
+ /* -- 12 byte ( 3 padding ) */
+ SlrxFilterTrigger_t Trigger;
+ /* -- 8 byte */
+ SlrxFilterAction_t Action;
+}_WlanRxFilterAddCommand_t;
+
+
+
+/* -- 4 bytes */
+typedef struct l_WlanRxFilterAddCommandReponse_t
+{
+ /* -- 1 byte */
+ SlrxFilterID_t FilterId;
+ /* -- 1 Byte */
+ _u8 Status;
+ /* -- 2 byte */
+ _u8 Padding[2];
+
+}_WlanRxFilterAddCommandReponse_t;
+
+
+
+/*
+ * \struct _WlanRxFilterSetCommand_t
+ */
+typedef struct _WlanRxFilterSetCommand_t
+{
+ _u16 InputBufferLength;
+ /* 1 byte */
+ SLrxFilterOperation_t RxFilterOperation;
+ _u8 Padding[1];
+}_WlanRxFilterSetCommand_t;
+
+/**
+ * \struct _WlanRxFilterSetCommandReponse_t
+ */
+typedef struct _WlanRxFilterSetCommandReponse_t
+{
+ /* 1 byte */
+ _u8 Status;
+ /* 3 bytes */
+ _u8 Padding[3];
+
+}_WlanRxFilterSetCommandReponse_t;
+
+/**
+ * \struct _WlanRxFilterGetCommand_t
+ */
+typedef struct _WlanRxFilterGetCommand_t
+{
+ _u16 OutputBufferLength;
+ /* 1 byte */
+ SLrxFilterOperation_t RxFilterOperation;
+ _u8 Padding[1];
+}_WlanRxFilterGetCommand_t;
+
+/**
+ * \struct _WlanRxFilterGetCommandReponse_t
+ */
+typedef struct _WlanRxFilterGetCommandReponse_t
+{
+ /* 1 byte */
+ _u8 Status;
+ /* 1 bytes */
+ _u8 Padding;
+ /* 2 byte */
+ _u16 OutputBufferLength;
+
+}_WlanRxFilterGetCommandReponse_t;
+
+
+
+/* ******************************************************************************/
+/* RX filters -- End */
+/* ******************************************************************************/
+
+typedef struct
+{
+ _u16 status;
+ _u8 WlanRole; /* 0 = station, 2 = AP */
+ _u8 Ipv6Enabled;
+ _u8 Ipv6DhcpEnabled;
+
+ _u32 ipV6Global[4];
+ _u32 ipV6Local[4];
+ _u32 ipV6DnsServer[4];
+ _u8 Ipv6DhcpState;
+
+}_NetappIpV6configRetArgs_t;
+
+
+typedef struct
+{
+ _u8 ipV4[4];
+ _u8 ipV4Mask[4];
+ _u8 ipV4Gateway[4];
+ _u8 ipV4DnsServer[4];
+ _u8 ipV4Start[4];
+ _u8 ipV4End[4];
+}_NetCfgIpV4AP_Args_t;
+
+
+
+typedef struct
+{
+ _u16 status;
+ _u8 MacAddr[6];
+} _MAC_Address_SetGet_t;
+
+
+typedef struct
+{
+ _u16 Status;
+ _u16 ConfigId;
+ _u16 ConfigOpt;
+ _u16 ConfigLen;
+}_NetCfgSetGet_t;
+
+typedef struct
+{
+ _u16 Status;
+ _u16 DeviceSetId;
+ _u16 Option;
+ _u16 ConfigLen;
+}_DeviceSetGet_t;
+
+
+
+
+/******************************************************************************************/
+/* Socket structs */
+/******************************************************************************************/
+
+typedef struct
+{
+ _u8 Domain;
+ _u8 Type;
+ _u8 Protocol;
+ _u8 Padding;
+}_SocketCommand_t;
+
+
+typedef struct
+{
+ _i16 statusOrLen;
+ _u8 sd;
+ _u8 padding;
+}_SocketResponse_t;
+
+typedef struct
+{
+ _u8 sd;
+ _u8 family;
+ _u8 padding1;
+ _u8 padding2;
+}_AcceptCommand_t;
+
+
+typedef struct
+{
+ _i16 statusOrLen;
+ _u8 sd;
+ _u8 family;
+ _u16 port;
+ _u16 paddingOrAddr;
+ _u32 address;
+}_SocketAddrAsyncIPv4Response_t;
+
+typedef struct
+{
+ _i16 statusOrLen;
+ _u8 sd;
+ _u8 family;
+ _u16 port;
+ _u8 address[6];
+}_SocketAddrAsyncIPv6EUI48Response_t;
+typedef struct
+{
+ _i16 statusOrLen;
+ _u8 sd;
+ _u8 family;
+ _u16 port;
+ _u16 paddingOrAddr;
+ _u32 address[4];
+}_SocketAddrAsyncIPv6Response_t;
+
+
+typedef struct
+{
+ _i16 lenOrPadding;
+ _u8 sd;
+ _u8 FamilyAndFlags;
+ _u16 port;
+ _u16 paddingOrAddr;
+ _u32 address;
+}_SocketAddrIPv4Command_t;
+
+typedef struct
+{
+ _i16 lenOrPadding;
+ _u8 sd;
+ _u8 FamilyAndFlags;
+ _u16 port;
+ _u8 address[6];
+}_SocketAddrIPv6EUI48Command_t;
+typedef struct
+{
+ _i16 lenOrPadding;
+ _u8 sd;
+ _u8 FamilyAndFlags;
+ _u16 port;
+ _u16 paddingOrAddr;
+ _u32 address[4];
+}_SocketAddrIPv6Command_t;
+
+typedef union {
+ _SocketAddrIPv4Command_t IpV4;
+ _SocketAddrIPv6EUI48Command_t IpV6EUI48;
+#ifdef SL_SUPPORT_IPV6
+ _SocketAddrIPv6Command_t IpV6;
+#endif
+} _SocketAddrCommand_u;
+
+typedef union {
+ _SocketAddrAsyncIPv4Response_t IpV4;
+ _SocketAddrAsyncIPv6EUI48Response_t IpV6EUI48;
+#ifdef SL_SUPPORT_IPV6
+ _SocketAddrAsyncIPv6Response_t IpV6;
+#endif
+} _SocketAddrResponse_u;
+
+typedef struct
+{
+ _u8 sd;
+ _u8 backlog;
+ _u8 padding1;
+ _u8 padding2;
+}_ListenCommand_t;
+
+typedef struct
+{
+ _u8 sd;
+ _u8 padding0;
+ _u8 padding1;
+ _u8 padding2;
+}_CloseCommand_t;
+
+
+typedef struct
+{
+ _u8 nfds;
+ _u8 readFdsCount;
+ _u8 writeFdsCount;
+ _u8 padding;
+ _u16 readFds;
+ _u16 writeFds;
+ _u16 tv_usec;
+ _u16 tv_sec;
+}_SelectCommand_t;
+
+
+typedef struct
+{
+ _u16 status;
+ _u8 readFdsCount;
+ _u8 writeFdsCount;
+ _u16 readFds;
+ _u16 writeFds;
+}_SelectAsyncResponse_t;
+
+typedef struct
+{
+ _u8 sd;
+ _u8 level;
+ _u8 optionName;
+ _u8 optionLen;
+}_setSockOptCommand_t;
+
+typedef struct
+{
+ _u8 sd;
+ _u8 level;
+ _u8 optionName;
+ _u8 optionLen;
+}_getSockOptCommand_t;
+
+typedef struct
+{
+ _i16 status;
+ _u8 sd;
+ _u8 optionLen;
+}_getSockOptResponse_t;
+
+
+typedef struct
+{
+ _u16 StatusOrLen;
+ _u8 sd;
+ _u8 FamilyAndFlags;
+}_sendRecvCommand_t;
+
+/*****************************************************************************************
+* NETAPP structs
+******************************************************************************************/
+
+
+typedef _BasicResponse_t _NetAppStartStopResponse_t;
+
+typedef struct
+{
+ _u32 appId;
+}_NetAppStartStopCommand_t;
+
+typedef struct
+{
+ _u16 Status;
+ _u16 AppId;
+ _u16 ConfigOpt;
+ _u16 ConfigLen;
+}_NetAppSetGet_t;
+typedef struct
+{
+ _u16 port_number;
+} _NetAppHttpServerGetSet_port_num_t;
+
+typedef struct
+{
+ _u8 auth_enable;
+}_NetAppHttpServerGetSet_auth_enable_t;
+
+typedef struct _sl_NetAppHttpServerGetToken_t
+{
+ _u8 token_name_len;
+ _u8 padd1;
+ _u16 padd2;
+}sl_NetAppHttpServerGetToken_t;
+
+typedef struct _sl_NetAppHttpServerSendToken_t
+{
+ _u8 token_value_len;
+ _u8 token_name_len;
+ _u8 token_name[MAX_TOKEN_NAME_LEN];
+ _u16 padd;
+}sl_NetAppHttpServerSendToken_t;
+
+typedef struct _sl_NetAppHttpServerPostToken_t
+{
+ _u8 post_action_len;
+ _u8 token_name_len;
+ _u8 token_value_len;
+ _u8 padding;
+}sl_NetAppHttpServerPostToken_t;
+
+
+typedef struct
+{
+ _u16 Len;
+ _u8 family;
+ _u8 padding;
+}_GetHostByNameCommand_t;
+
+typedef struct
+{
+ _u16 status;
+ _u16 padding;
+ _u32 ip0;
+ _u32 ip1;
+ _u32 ip2;
+ _u32 ip3;
+}_GetHostByNameIPv6AsyncResponse_t;
+
+typedef struct
+{
+ _u16 status;
+ _u8 padding1;
+ _u8 padding2;
+ _u32 ip0;
+}_GetHostByNameIPv4AsyncResponse_t;
+
+
+
+
+typedef enum
+{
+ CTST_BSD_UDP_TX,
+ CTST_BSD_UDP_RX,
+ CTST_BSD_TCP_TX,
+ CTST_BSD_TCP_RX,
+ CTST_BSD_TCP_SERVER_BI_DIR,
+ CTST_BSD_TCP_CLIENT_BI_DIR,
+ CTST_BSD_UDP_BI_DIR,
+ CTST_BSD_RAW_TX,
+ CTST_BSD_RAW_RX,
+ CTST_BSD_RAW_BI_DIR,
+ CTST_BSD_SECURED_TCP_TX,
+ CTST_BSD_SECURED_TCP_RX,
+ CTST_BSD_SECURED_TCP_SERVER_BI_DIR,
+ CTST_BSD_SECURED_TCP_CLIENT_BI_DIR
+ }CommTest_e;
+
+typedef struct _sl_protocol_CtestStartCommand_t
+{
+ _u32 Test;
+ _u16 DestPort;
+ _u16 SrcPort;
+ _u32 DestAddr[4];
+ _u32 PayloadSize;
+ _u32 timeout;
+ _u32 csEnabled;
+ _u32 secure;
+ _u32 rawProtocol;
+ _u8 reserved1[4];
+}_CtestStartCommand_t;
+
+typedef struct
+{
+ _u8 test;
+ _u8 socket;
+ _i16 status;
+ _u32 startTime;
+ _u32 endTime;
+ _u16 txKbitsSec;
+ _u16 rxKbitsSec;
+ _u32 outOfOrderPackets;
+ _u32 missedPackets;
+}_CtestAsyncResponse_t;
+
+typedef struct
+{
+ _u32 pingIntervalTime;
+ _u16 PingSize;
+ _u16 pingRequestTimeout;
+ _u32 totalNumberOfAttempts;
+ _u32 flags;
+ _u32 ip0;
+ _u32 ip1OrPaadding;
+ _u32 ip2OrPaadding;
+ _u32 ip3OrPaadding;
+}_PingStartCommand_t;
+
+typedef struct
+{
+ _u16 status;
+ _u16 rttMin;
+ _u16 rttMax;
+ _u16 rttAvg;
+ _u32 numSuccsessPings;
+ _u32 numSendsPings;
+ _u32 testTime;
+}_PingReportResponse_t;
+
+
+typedef struct
+{
+ _u32 ip;
+ _u32 gateway;
+ _u32 dns;
+}_IpV4AcquiredAsync_t;
+
+
+typedef enum
+{
+ ACQUIRED_IPV6_LOCAL = 1,
+ ACQUIRED_IPV6_GLOBAL
+}IpV6AcquiredType_e;
+
+
+typedef struct
+{
+ _u32 type;
+ _u32 ip[4];
+ _u32 gateway[4];
+ _u32 dns[4];
+}_IpV6AcquiredAsync_t;
+
+
+typedef union
+{
+ _SocketCommand_t EventMask;
+ _sendRecvCommand_t DeviceInit;
+}_device_commands_t;
+
+/*****************************************************************************************
+* FS structs
+******************************************************************************************/
+
+typedef struct
+{
+ _u32 FileHandle;
+ _u32 Offset;
+ _u16 Len;
+ _u16 Padding;
+}_FsReadCommand_t;
+
+typedef struct
+{
+ _u32 Mode;
+ _u32 Token;
+}_FsOpenCommand_t;
+
+typedef struct
+{
+ _u32 FileHandle;
+ _u32 Token;
+}_FsOpenResponse_t;
+
+
+typedef struct
+{
+ _u32 FileHandle;
+ _u32 CertificFileNameLength;
+ _u32 SignatureLen;
+}_FsCloseCommand_t;
+
+
+typedef _BasicResponse_t _FsReadResponse_t;
+typedef _BasicResponse_t _FsDeleteResponse_t;
+typedef _BasicResponse_t _FsCloseResponse_t;
+
+typedef struct
+{
+ _u16 Status;
+ _u16 flags;
+ _u32 FileLen;
+ _u32 AllocatedLen;
+ _u32 Token[4];
+}_FsGetInfoResponse_t;
+
+typedef struct
+{
+ _u8 DeviceID;
+ _u8 Padding[3];
+}_FsFormatCommand_t;
+
+typedef _BasicResponse_t _FsFormatResponse_t;
+
+typedef struct
+{
+ _u32 Token;
+}_FsDeleteCommand_t;
+
+typedef _FsDeleteCommand_t _FsGetInfoCommand_t;
+
+typedef struct
+{
+ _u32 FileHandle;
+ _u32 Offset;
+ _u16 Len;
+ _u16 Padding;
+}_FsWriteCommand_t;
+
+typedef _BasicResponse_t _FsWriteResponse_t;
+
+
+
+/* Set Max Async Payload length depending on flavor (Tiny, Small, etc.) */
+#define SL_ASYNC_MAX_PAYLOAD_LEN 160 /* size must be aligned to 4 */
+#define SL_ASYNC_MAX_MSG_LEN (_SL_RESP_HDR_SIZE + SL_ASYNC_MAX_PAYLOAD_LEN)
+
+#define RECV_ARGS_SIZE (sizeof(_SocketResponse_t))
+#define RECVFROM_IPV4_ARGS_SIZE (sizeof(_SocketAddrAsyncIPv4Response_t))
+#define RECVFROM_IPV6_ARGS_SIZE (sizeof(_SocketAddrAsyncIPv6Response_t))
+
+#define SL_IPV4_ADDRESS_SIZE (sizeof(_u32))
+#define SL_IPV6_ADDRESS_SIZE (4 * sizeof(_u32))
+
+#endif /* _SL_PROTOCOL_TYPES_H_ */
diff --git a/cc3200/simplelink/source/socket.c b/cc3200/simplelink/source/socket.c
new file mode 100644
index 0000000000..34dd4a8b43
--- /dev/null
+++ b/cc3200/simplelink/source/socket.c
@@ -0,0 +1,1123 @@
+/*
+ * socket.c - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+
+
+/*******************************************************************************/
+/* Functions prototypes */
+/*******************************************************************************/
+void _sl_BuildAddress(const SlSockAddr_t *addr, _i16 addrlen, _SocketAddrCommand_u *pCmd);
+void _sl_ParseAddress(_SocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen);
+void _sl_HandleAsync_Connect(void *pVoidBuf);
+void _sl_HandleAsync_Accept(void *pVoidBuf);
+void _sl_HandleAsync_Select(void *pVoidBuf);
+_u16 _sl_TruncatePayloadByProtocol(const _i16 pSd,const _u16 length);
+
+/*******************************************************************************/
+/* Functions */
+/*******************************************************************************/
+
+/* ******************************************************************************/
+/* _sl_BuildAddress */
+/* ******************************************************************************/
+void _sl_BuildAddress(const SlSockAddr_t *addr, _i16 addrlen, _SocketAddrCommand_u *pCmd)
+{
+
+ /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 */
+ /* is possible as _i32 as these parameters are in the same offset and size for these */
+ /* three families. */
+ pCmd->IpV4.FamilyAndFlags = (addr->sa_family << 4) & 0xF0;
+ pCmd->IpV4.port = ((SlSockAddrIn_t *)addr)->sin_port;
+
+ if(SL_AF_INET == addr->sa_family)
+ {
+ pCmd->IpV4.address = ((SlSockAddrIn_t *)addr)->sin_addr.s_addr;
+ }
+ else if (SL_AF_INET6_EUI_48 == addr->sa_family )
+ {
+ sl_Memcpy( pCmd->IpV6EUI48.address,((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u8, 6);
+ }
+#ifdef SL_SUPPORT_IPV6
+ else
+ {
+ sl_Memcpy(pCmd->IpV6.address, ((sockaddr_in6 *)addr)->sin6_addr._S6_un._S6_u32, 16 );
+ }
+#endif
+}
+
+/* ******************************************************************************/
+/* _sl_TruncatePayloadByProtocol */
+/* ******************************************************************************/
+_u16 _sl_TruncatePayloadByProtocol(const _i16 sd,const _u16 length)
+{
+ _u16 maxLength;
+
+ switch(sd & SL_SOCKET_PAYLOAD_TYPE_MASK)
+ {
+ case SL_SOCKET_PAYLOAD_TYPE_UDP_IPV4:
+ maxLength = 1472;
+ break;
+
+ case SL_SOCKET_PAYLOAD_TYPE_TCP_IPV4:
+ maxLength = 1460;
+ break;
+
+ case SL_SOCKET_PAYLOAD_TYPE_UDP_IPV6:
+ maxLength = 1452;
+ break;
+
+ case SL_SOCKET_PAYLOAD_TYPE_TCP_IPV6:
+ maxLength = 1440;
+ break;
+ case SL_SOCKET_PAYLOAD_TYPE_TCP_IPV4_SECURE:
+ case SL_SOCKET_PAYLOAD_TYPE_UDP_IPV4_SECURE:
+ maxLength = 1402;
+ break;
+ case SL_SOCKET_PAYLOAD_TYPE_UDP_IPV6_SECURE:
+ case SL_SOCKET_PAYLOAD_TYPE_TCP_IPV6_SECURE:
+ maxLength = 1396;
+ break;
+ case SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER:
+ maxLength = 1476;
+ break;
+ case SL_SOCKET_PAYLOAD_TYPE_RAW_PACKET:
+ maxLength = 1514;
+ break;
+ case SL_SOCKET_PAYLOAD_TYPE_RAW_IP4:
+ maxLength = 1480;
+ break;
+ default:
+ maxLength = 1440;
+ break;
+ }
+
+ if( length > maxLength )
+ {
+ return maxLength;
+ }
+ else
+ {
+ return length;
+ }
+}
+
+/*******************************************************************************/
+/* _sl_ParseAddress */
+/*******************************************************************************/
+void _sl_ParseAddress(_SocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen)
+{
+ /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 */
+ /* is possible as long as these parameters are in the same offset and size for these */
+ /* three families. */
+ addr->sa_family = pRsp->IpV4.family;
+ ((SlSockAddrIn_t *)addr)->sin_port = pRsp->IpV4.port;
+
+ *addrlen = (SL_AF_INET == addr->sa_family) ? sizeof(SlSockAddrIn_t) : sizeof(SlSockAddrIn6_t);
+
+ if(SL_AF_INET == addr->sa_family)
+ {
+ ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = pRsp->IpV4.address;
+ }
+ else if (SL_AF_INET6_EUI_48 == addr->sa_family )
+ {
+ sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u8, pRsp->IpV6EUI48.address, 6);
+ }
+#ifdef SL_SUPPORT_IPV6
+ else
+ {
+ sl_Memcpy(((sockaddr_in6 *)addr)->sin6_addr._S6_un._S6_u32, pRsp->IpV6.address, 16);
+ }
+#endif
+}
+
+/*******************************************************************************/
+/* sl_Socket */
+/*******************************************************************************/
+typedef union
+{
+ _u32 Dummy;
+ _SocketCommand_t Cmd;
+ _SocketResponse_t Rsp;
+}_SlSockSocketMsg_u;
+
+const _SlCmdCtrl_t _SlSockSocketCmdCtrl =
+{
+ SL_OPCODE_SOCKET_SOCKET,
+ sizeof(_SocketCommand_t),
+ sizeof(_SocketResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_Socket)
+_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol)
+{
+ _SlSockSocketMsg_u Msg;
+
+ Msg.Cmd.Domain = (_u8)Domain;
+ Msg.Cmd.Type = (_u8)Type;
+ Msg.Cmd.Protocol = (_u8)Protocol;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSockSocketCmdCtrl, &Msg, NULL));
+
+ if( Msg.Rsp.statusOrLen < 0 )
+ {
+ return( Msg.Rsp.statusOrLen );
+ }
+ else
+ {
+ return (_i16)((_u8)Msg.Rsp.sd);
+}
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Close */
+/*******************************************************************************/
+typedef union
+{
+ _CloseCommand_t Cmd;
+ _SocketResponse_t Rsp;
+}_SlSockCloseMsg_u;
+
+const _SlCmdCtrl_t _SlSockCloseCmdCtrl =
+{
+ SL_OPCODE_SOCKET_CLOSE,
+ sizeof(_CloseCommand_t),
+ sizeof(_SocketResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_Close)
+_i16 sl_Close(_i16 sd)
+{
+ _SlSockCloseMsg_u Msg;
+
+ Msg.Cmd.sd = (_u8)sd;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSockCloseCmdCtrl, &Msg, NULL));
+
+ return Msg.Rsp.statusOrLen;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Bind */
+/*******************************************************************************/
+typedef union
+{
+ _SocketAddrCommand_u Cmd;
+ _SocketResponse_t Rsp;
+}_SlSockBindMsg_u;
+
+#if _SL_INCLUDE_FUNC(sl_Bind)
+_i16 sl_Bind(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen)
+{
+ _SlSockBindMsg_u Msg;
+ _SlCmdCtrl_t CmdCtrl = {0, 0, sizeof(_SocketResponse_t)};
+
+ switch(addr->sa_family)
+ {
+ case SL_AF_INET :
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv4Command_t);
+ break;
+ case SL_AF_INET6_EUI_48:
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND_V6;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv6EUI48Command_t);
+ break;
+#ifdef SL_SUPPORT_IPV6
+ case AF_INET6:
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND_V6;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv6Command_t);
+ break;
+#endif
+ case SL_AF_RF :
+ default:
+ return SL_RET_CODE_INVALID_INPUT;
+ }
+
+ Msg.Cmd.IpV4.lenOrPadding = 0;
+ Msg.Cmd.IpV4.sd = (_u8)sd;
+
+ _sl_BuildAddress(addr, addrlen, &Msg.Cmd);
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL));
+
+ return Msg.Rsp.statusOrLen;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Sendto */
+/*******************************************************************************/
+typedef union
+{
+ _SocketAddrCommand_u Cmd;
+ /* no response for 'sendto' commands*/
+}_SlSendtoMsg_u;
+
+#if _SL_INCLUDE_FUNC(sl_SendTo)
+_i16 sl_SendTo(_i16 sd, const void *pBuf, _i16 Len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen)
+{
+ _SlSendtoMsg_u Msg;
+ _SlCmdCtrl_t CmdCtrl = {0, 0, 0};
+ _SlCmdExt_t CmdExt;
+ _u16 ChunkLen;
+ _i16 RetVal;
+
+ CmdExt.TxPayloadLen = (_u16)Len;
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pBuf;
+ CmdExt.pRxPayload = NULL;
+
+
+ switch(to->sa_family)
+ {
+ case SL_AF_INET:
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv4Command_t);
+ break;
+ case SL_AF_INET6_EUI_48:
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND_V6;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv6EUI48Command_t);
+ break;
+#ifdef SL_SUPPORT_IPV6
+ case AF_INET6:
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO_V6;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv6Command_t);
+ break;
+#endif
+ case SL_AF_RF:
+ default:
+ return SL_RET_CODE_INVALID_INPUT;
+ }
+
+ ChunkLen = _sl_TruncatePayloadByProtocol(sd,Len);
+ Msg.Cmd.IpV4.lenOrPadding = ChunkLen;
+ CmdExt.TxPayloadLen = ChunkLen;
+
+ Msg.Cmd.IpV4.sd = (_u8)sd;
+
+ _sl_BuildAddress(to, tolen, &Msg.Cmd);
+
+ Msg.Cmd.IpV4.FamilyAndFlags |= flags & 0x0F;
+
+ do
+ {
+ RetVal = _SlDrvDataWriteOp((_SlSd_t)sd, &CmdCtrl, &Msg, &CmdExt);
+
+ if(SL_OS_RET_CODE_OK == RetVal)
+ {
+ CmdExt.pTxPayload += ChunkLen;
+ ChunkLen = (_u16)((_u8 *)pBuf + Len - CmdExt.pTxPayload);
+ ChunkLen = _sl_TruncatePayloadByProtocol(sd,ChunkLen);
+ CmdExt.TxPayloadLen = ChunkLen;
+ Msg.Cmd.IpV4.lenOrPadding = ChunkLen;
+ }
+ else
+ {
+ return RetVal;
+ }
+ }while(ChunkLen > 0);
+
+ return (_i16)Len;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Recvfrom */
+/*******************************************************************************/
+typedef union
+{
+ _sendRecvCommand_t Cmd;
+ _SocketAddrResponse_u Rsp;
+}_SlRecvfromMsg_u;
+
+const _SlCmdCtrl_t _SlRecvfomCmdCtrl =
+{
+ SL_OPCODE_SOCKET_RECVFROM,
+ sizeof(_sendRecvCommand_t),
+ sizeof(_SocketAddrResponse_u)
+};
+
+#if _SL_INCLUDE_FUNC(sl_RecvFrom)
+_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 Len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen)
+{
+ _SlRecvfromMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+ _i16 RetVal;
+
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = Len;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)buf;
+
+
+ Msg.Cmd.sd = (_u8)sd;
+ Msg.Cmd.StatusOrLen = Len;
+ /* no size truncation in recv path */
+ CmdExt.RxPayloadLen = Msg.Cmd.StatusOrLen;
+
+ if(sizeof(SlSockAddrIn_t) == *fromlen)
+ {
+ Msg.Cmd.FamilyAndFlags = SL_AF_INET;
+ }
+ else if (sizeof(SlSockAddrIn6_t) == *fromlen)
+ {
+ Msg.Cmd.FamilyAndFlags = SL_AF_INET6;
+ }
+ else
+ {
+ return SL_RET_CODE_INVALID_INPUT;
+ }
+
+ Msg.Cmd.FamilyAndFlags = (Msg.Cmd.FamilyAndFlags << 4) & 0xF0;
+ Msg.Cmd.FamilyAndFlags |= flags & 0x0F;
+
+ RetVal = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvfomCmdCtrl, &Msg, &CmdExt);
+ if( RetVal != SL_OS_RET_CODE_OK )
+ {
+ return RetVal;
+ }
+
+ RetVal = Msg.Rsp.IpV4.statusOrLen;
+
+ if(RetVal >= 0)
+ {
+ VERIFY_PROTOCOL(sd == Msg.Rsp.IpV4.sd);
+#if 0
+ _sl_ParseAddress(&Msg.Rsp, from, fromlen);
+#else
+ from->sa_family = Msg.Rsp.IpV4.family;
+ if(SL_AF_INET == from->sa_family)
+ {
+ ((SlSockAddrIn_t *)from)->sin_port = Msg.Rsp.IpV4.port;
+ ((SlSockAddrIn_t *)from)->sin_addr.s_addr = Msg.Rsp.IpV4.address;
+ *fromlen = sizeof(SlSockAddrIn_t);
+ }
+ else if (SL_AF_INET6_EUI_48 == from->sa_family )
+ {
+ ((SlSockAddrIn6_t *)from)->sin6_port = Msg.Rsp.IpV6EUI48.port;
+ sl_Memcpy(((SlSockAddrIn6_t *)from)->sin6_addr._S6_un._S6_u8, Msg.Rsp.IpV6EUI48.address, 6);
+ }
+#ifdef SL_SUPPORT_IPV6
+ else if(AF_INET6 == from->sa_family)
+ {
+ VERIFY_PROTOCOL(*fromlen >= sizeof(sockaddr_in6));
+
+ ((sockaddr_in6 *)from)->sin6_port = Msg.Rsp.IpV6.port;
+ sl_Memcpy(((sockaddr_in6 *)from)->sin6_addr._S6_un._S6_u32, Msg.Rsp.IpV6.address, 16);
+ *fromlen = sizeof(sockaddr_in6);
+ }
+#endif
+#endif
+ }
+
+ return (_i16)RetVal;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Connect */
+/*******************************************************************************/
+typedef union
+{
+ _SocketAddrCommand_u Cmd;
+ _SocketResponse_t Rsp;
+}_SlSockConnectMsg_u;
+
+#if _SL_INCLUDE_FUNC(sl_Connect)
+_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen)
+{
+ _SlSockConnectMsg_u Msg;
+ _SlReturnVal_t RetVal;
+ _SlCmdCtrl_t CmdCtrl = {0, 0, sizeof(_SocketResponse_t)};
+ _SocketResponse_t AsyncRsp;
+ _u8 ObjIdx = MAX_CONCURRENT_ACTIONS;
+
+
+ switch(addr->sa_family)
+ {
+ case SL_AF_INET :
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv4Command_t);
+ break;
+ case SL_AF_INET6_EUI_48:
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT_V6;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv6EUI48Command_t);
+ break;
+#ifdef SL_SUPPORT_IPV6
+ case AF_INET6:
+ CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT_V6;
+ CmdCtrl.TxDescLen = sizeof(_SocketAddrIPv6Command_t);
+ break;
+#endif
+ case SL_AF_RF :
+ default:
+ return SL_RET_CODE_INVALID_INPUT;
+ }
+
+ Msg.Cmd.IpV4.lenOrPadding = 0;
+ Msg.Cmd.IpV4.sd = (_u8)sd;
+
+ _sl_BuildAddress(addr, addrlen, &Msg.Cmd);
+
+ /* Use Obj to issue the command, if not available try later */
+ ObjIdx = (_u8)_SlDrvWaitForPoolObj(CONNECT_ID, (_u8)(sd & BSD_SOCKET_ID_MASK));
+
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp;
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+
+ /* send the command */
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL));
+ VERIFY_PROTOCOL(Msg.Rsp.sd == sd)
+
+ RetVal = Msg.Rsp.statusOrLen;
+
+ if(SL_RET_CODE_OK == RetVal)
+ {
+ /* wait for async and get Data Read parameters */
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+
+ VERIFY_PROTOCOL(AsyncRsp.sd == sd);
+
+ RetVal = AsyncRsp.statusOrLen;
+ }
+ _SlDrvReleasePoolObj(ObjIdx);
+ return RetVal;
+}
+#endif
+
+/*******************************************************************************/
+/* _sl_HandleAsync_Connect */
+/*******************************************************************************/
+void _sl_HandleAsync_Connect(void *pVoidBuf)
+{
+ _SocketResponse_t *pMsgArgs = (_SocketResponse_t *)_SL_RESP_ARGS_START(pVoidBuf);
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ VERIFY_PROTOCOL((pMsgArgs->sd & BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS);
+ VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs);
+
+ ((_SocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->sd = pMsgArgs->sd;
+ ((_SocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->statusOrLen = pMsgArgs->statusOrLen;
+
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj));
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ return;
+}
+
+/*******************************************************************************/
+/* sl_Send */
+/*******************************************************************************/
+typedef union
+{
+ _sendRecvCommand_t Cmd;
+ /* no response for 'sendto' commands*/
+}_SlSendMsg_u;
+
+const _SlCmdCtrl_t _SlSendCmdCtrl =
+{
+ SL_OPCODE_SOCKET_SEND,
+ sizeof(_sendRecvCommand_t),
+ 0
+};
+
+#if _SL_INCLUDE_FUNC(sl_Send)
+_i16 sl_Send(_i16 sd, const void *pBuf, _i16 Len, _i16 flags)
+{
+ _SlSendMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+ _u16 ChunkLen;
+ _i16 RetVal;
+ _u32 tempVal;
+ _u8 runSingleChunk = FALSE;
+
+ CmdExt.TxPayloadLen = Len;
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pBuf;
+
+ /* Only for RAW transceiver type socket, relay the flags parameter in the 2 bytes (4 byte aligned) before the actual payload */
+ if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER)
+ {
+ tempVal = flags;
+ CmdExt.pRxPayload = (_u8 *)&tempVal;
+ CmdExt.RxPayloadLen = 4;
+ g_pCB->RelayFlagsViaRxPayload = TRUE;
+ runSingleChunk = TRUE;
+ }
+ else
+ {
+ CmdExt.pRxPayload = NULL;
+ }
+
+ ChunkLen = _sl_TruncatePayloadByProtocol(sd,Len);
+ CmdExt.TxPayloadLen = ChunkLen;
+
+ Msg.Cmd.StatusOrLen = ChunkLen;
+ Msg.Cmd.sd = (_u8)sd;
+ Msg.Cmd.FamilyAndFlags |= flags & 0x0F;
+
+ do
+ {
+ RetVal = _SlDrvDataWriteOp((_u8)sd, (_SlCmdCtrl_t *)&_SlSendCmdCtrl, &Msg, &CmdExt);
+ if(SL_OS_RET_CODE_OK == RetVal)
+ {
+ CmdExt.pTxPayload += ChunkLen;
+ ChunkLen = (_u8 *)pBuf + Len - CmdExt.pTxPayload;
+ ChunkLen = _sl_TruncatePayloadByProtocol(sd,ChunkLen);
+ CmdExt.TxPayloadLen = ChunkLen;
+ Msg.Cmd.StatusOrLen = ChunkLen;
+ }
+ else
+ {
+ return RetVal;
+ }
+ }while((ChunkLen > 0) && (runSingleChunk==FALSE));
+
+ return (_i16)Len;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Listen */
+/*******************************************************************************/
+typedef union
+{
+ _ListenCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlListenMsg_u;
+
+const _SlCmdCtrl_t _SlListenCmdCtrl =
+{
+ SL_OPCODE_SOCKET_LISTEN,
+ sizeof(_ListenCommand_t),
+ sizeof(_BasicResponse_t),
+};
+
+#if _SL_INCLUDE_FUNC(sl_Listen)
+_i16 sl_Listen(_i16 sd, _i16 backlog)
+{
+ _SlListenMsg_u Msg;
+
+ Msg.Cmd.sd = (_u8)sd;
+ Msg.Cmd.backlog = (_u8)backlog;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlListenCmdCtrl, &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Accept */
+/*******************************************************************************/
+typedef union
+{
+ _AcceptCommand_t Cmd;
+ _SocketResponse_t Rsp;
+}_SlSockAcceptMsg_u;
+
+const _SlCmdCtrl_t _SlAcceptCmdCtrl =
+{
+ SL_OPCODE_SOCKET_ACCEPT,
+ sizeof(_AcceptCommand_t),
+ sizeof(_BasicResponse_t),
+};
+
+#if _SL_INCLUDE_FUNC(sl_Accept)
+_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen)
+{
+ _SlSockAcceptMsg_u Msg;
+ _SlReturnVal_t RetVal;
+ _SocketAddrResponse_u AsyncRsp;
+
+ _u8 ObjIdx = MAX_CONCURRENT_ACTIONS;
+
+
+ Msg.Cmd.sd = (_u8)sd;
+ Msg.Cmd.family = (sizeof(SlSockAddrIn_t) == *addrlen) ? SL_AF_INET : SL_AF_INET6;
+
+ /* Use Obj to issue the command, if not available try later */
+ ObjIdx = (_u8)_SlDrvWaitForPoolObj(ACCEPT_ID, (_u8)(sd & BSD_SOCKET_ID_MASK));
+
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp;
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ /* send the command */
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlAcceptCmdCtrl, &Msg, NULL));
+ VERIFY_PROTOCOL(Msg.Rsp.sd == sd);
+
+ RetVal = Msg.Rsp.statusOrLen;
+
+ if(SL_OS_RET_CODE_OK == RetVal)
+ {
+ /* wait for async and get Data Read parameters */
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+
+ VERIFY_PROTOCOL(AsyncRsp.IpV4.sd == sd);
+
+ RetVal = AsyncRsp.IpV4.statusOrLen;
+ if( (NULL != addr) && (NULL != addrlen) )
+ {
+#if 0 /* Kept for backup */
+ _sl_ParseAddress(&AsyncRsp, addr, addrlen);
+#else
+ addr->sa_family = AsyncRsp.IpV4.family;
+
+ if(SL_AF_INET == addr->sa_family)
+ {
+ if( *addrlen == sizeof( SlSockAddrIn_t ) )
+ {
+ ((SlSockAddrIn_t *)addr)->sin_port = AsyncRsp.IpV4.port;
+ ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = AsyncRsp.IpV4.address;
+ }
+ else
+ {
+ *addrlen = 0;
+ }
+ }
+ else if (SL_AF_INET6_EUI_48 == addr->sa_family )
+ {
+ if( *addrlen == sizeof( SlSockAddrIn6_t ) )
+ {
+ ((SlSockAddrIn6_t *)addr)->sin6_port = AsyncRsp.IpV6EUI48.port ;
+ /* will be called from here and from _sl_BuildAddress*/
+ sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u8, AsyncRsp.IpV6EUI48.address, 6);
+ }
+ else
+ {
+ *addrlen = 0;
+ }
+ }
+#ifdef SL_SUPPORT_IPV6
+ else
+ {
+ if( *addrlen == sizeof( sockaddr_in6 ) )
+ {
+ ((sockaddr_in6 *)addr)->sin6_port = AsyncRsp.IpV6.port ;
+ sl_Memcpy(((sockaddr_in6 *)addr)->sin6_addr._S6_un._S6_u32, AsyncRsp.IpV6.address, 16);
+ }
+ else
+ {
+ *addrlen = 0;
+ }
+ }
+#endif
+#endif
+ }
+ }
+
+ _SlDrvReleasePoolObj(ObjIdx);
+ return (_i16)RetVal;
+}
+#endif
+
+
+/*******************************************************************************/
+/* sl_Htonl */
+/*******************************************************************************/
+_u32 sl_Htonl( _u32 val )
+{
+ _u32 i = 1;
+ _i8 *p = (_i8 *)&i;
+ if (p[0] == 1) /* little endian */
+ {
+ p[0] = ((_i8* )&val)[3];
+ p[1] = ((_i8* )&val)[2];
+ p[2] = ((_i8* )&val)[1];
+ p[3] = ((_i8* )&val)[0];
+ return i;
+ }
+ else /* big endian */
+ {
+ return val;
+ }
+}
+
+/*******************************************************************************/
+/* sl_Htonl */
+/*******************************************************************************/
+_u16 sl_Htons( _u16 val )
+{
+ _i16 i = 1;
+ _i8 *p = (_i8 *)&i;
+ if (p[0] == 1) /* little endian */
+ {
+ p[0] = ((_i8* )&val)[1];
+ p[1] = ((_i8* )&val)[0];
+ return i;
+ }
+ else /* big endian */
+ {
+ return val;
+ }
+}
+
+/*******************************************************************************/
+/* _sl_HandleAsync_Accept */
+/*******************************************************************************/
+void _sl_HandleAsync_Accept(void *pVoidBuf)
+{
+ _SocketAddrResponse_u *pMsgArgs = (_SocketAddrResponse_u *)_SL_RESP_ARGS_START(pVoidBuf);
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ VERIFY_PROTOCOL(( pMsgArgs->IpV4.sd & BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS);
+ VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs);
+
+ sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs,sizeof(_SocketAddrResponse_u));
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj));
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ return;
+}
+
+/*******************************************************************************/
+/* sl_Recv */
+/*******************************************************************************/
+typedef union
+{
+ _sendRecvCommand_t Cmd;
+ _SocketResponse_t Rsp;
+}_SlRecvMsg_u;
+
+const _SlCmdCtrl_t _SlRecvCmdCtrl =
+{
+ SL_OPCODE_SOCKET_RECV,
+ sizeof(_sendRecvCommand_t),
+ sizeof(_SocketResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_Recv)
+_i16 sl_Recv(_i16 sd, void *pBuf, _i16 Len, _i16 flags)
+{
+ _SlRecvMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+ _SlReturnVal_t status;
+
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = Len;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)pBuf;
+
+ Msg.Cmd.sd = (_u8)sd;
+ Msg.Cmd.StatusOrLen = Len;
+
+ /* no size truncation in recv path */
+ CmdExt.RxPayloadLen = Msg.Cmd.StatusOrLen;
+
+ Msg.Cmd.FamilyAndFlags = flags & 0x0F;
+
+ status = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvCmdCtrl, &Msg, &CmdExt);
+ if( status != SL_OS_RET_CODE_OK )
+ {
+ return status;
+ }
+
+ /* if the Device side sends less than expected it is not the Driver's role */
+ /* the returned value could be smaller than the requested size */
+ return (_i16)Msg.Rsp.statusOrLen;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_SetSockOpt */
+/*******************************************************************************/
+typedef union
+{
+ _setSockOptCommand_t Cmd;
+ _SocketResponse_t Rsp;
+}_SlSetSockOptMsg_u;
+
+const _SlCmdCtrl_t _SlSetSockOptCmdCtrl =
+{
+ SL_OPCODE_SOCKET_SETSOCKOPT,
+ sizeof(_setSockOptCommand_t),
+ sizeof(_SocketResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_SetSockOpt)
+_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen)
+{
+ _SlSetSockOptMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = optlen;
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)optval;
+ CmdExt.pRxPayload = NULL;
+
+ Msg.Cmd.sd = (_u8)sd;
+ Msg.Cmd.level = (_u8)level;
+ Msg.Cmd.optionLen = (_u8)optlen;
+ Msg.Cmd.optionName = (_u8)optname;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSetSockOptCmdCtrl, &Msg, &CmdExt));
+
+ return (_i16)Msg.Rsp.statusOrLen;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_GetSockOpt */
+/*******************************************************************************/
+typedef union
+{
+ _getSockOptCommand_t Cmd;
+ _getSockOptResponse_t Rsp;
+}_SlGetSockOptMsg_u;
+
+const _SlCmdCtrl_t _SlGetSockOptCmdCtrl =
+{
+ SL_OPCODE_SOCKET_GETSOCKOPT,
+ sizeof(_getSockOptCommand_t),
+ sizeof(_getSockOptResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_GetSockOpt)
+_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen)
+{
+ _SlGetSockOptMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (*optlen == 0)
+ {
+ return SL_EZEROLEN;
+ }
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = *optlen;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = optval;
+ CmdExt.ActualRxPayloadLen = 0;
+
+ Msg.Cmd.sd = (_u8)sd;
+ Msg.Cmd.level = (_u8)level;
+ Msg.Cmd.optionLen = (_u8)(*optlen);
+ Msg.Cmd.optionName = (_u8)optname;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetSockOptCmdCtrl, &Msg, &CmdExt));
+
+ if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen)
+ {
+ *optlen = Msg.Rsp.optionLen;
+ return SL_ESMALLBUF;
+ }
+ else
+ {
+ *optlen = (_u8)CmdExt.ActualRxPayloadLen;
+ }
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Select */
+/* ******************************************************************************/
+typedef union
+{
+ _SelectCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlSelectMsg_u;
+
+const _SlCmdCtrl_t _SlSelectCmdCtrl =
+{
+ SL_OPCODE_SOCKET_SELECT,
+ sizeof(_SelectCommand_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_Select)
+_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout)
+{
+ _SlSelectMsg_u Msg;
+ _SelectAsyncResponse_t AsyncRsp;
+ _u8 ObjIdx = MAX_CONCURRENT_ACTIONS;
+
+ Msg.Cmd.nfds = (_u8)nfds;
+ Msg.Cmd.readFdsCount = 0;
+ Msg.Cmd.writeFdsCount = 0;
+
+ Msg.Cmd.readFds = 0;
+ Msg.Cmd.writeFds = 0;
+
+ if( readsds )
+ {
+ Msg.Cmd.readFds = (_u16)readsds->fd_array[0];
+ }
+ if( writesds )
+ {
+ Msg.Cmd.writeFds = (_u16)writesds->fd_array[0];
+ }
+ if( NULL == timeout )
+ {
+ Msg.Cmd.tv_sec = 0xffff;
+ Msg.Cmd.tv_usec = 0xffff;
+ }
+ else
+ {
+ if( 0xffff <= timeout->tv_sec )
+ {
+ Msg.Cmd.tv_sec = 0xffff;
+ }
+ else
+ {
+ Msg.Cmd.tv_sec = (_u16)timeout->tv_sec;
+ }
+ timeout->tv_usec = timeout->tv_usec >> 10; /* convert to milliseconds */
+ if( 0xffff <= timeout->tv_usec )
+ {
+ Msg.Cmd.tv_usec = 0xffff;
+ }
+ else
+ {
+ Msg.Cmd.tv_usec = (_u16)timeout->tv_usec;
+ }
+ }
+
+ /* Use Obj to issue the command, if not available try later */
+ ObjIdx = (_u8)_SlDrvWaitForPoolObj(SELECT_ID, SL_MAX_SOCKETS);
+
+ if (MAX_CONCURRENT_ACTIONS == ObjIdx)
+ {
+ return SL_POOL_IS_EMPTY;
+ }
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp;
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ /* send the command */
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL));
+
+ if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status)
+ {
+ OSI_RET_OK_CHECK(sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_WAIT_FOREVER));
+ Msg.Rsp.status = AsyncRsp.status;
+
+ if( ((_i16)Msg.Rsp.status) >= 0 )
+ {
+ if( readsds )
+ {
+ readsds->fd_array[0] = AsyncRsp.readFds;
+ }
+ if( writesds )
+ {
+ writesds->fd_array[0] = AsyncRsp.writeFds;
+ }
+ }
+ }
+
+ _SlDrvReleasePoolObj(ObjIdx);
+ return (_i16)Msg.Rsp.status;
+}
+
+/* Select helper functions */
+/*******************************************************************************/
+/* SL_FD_SET */
+/* ******************************************************************************/
+void SL_FD_SET(_i16 fd, SlFdSet_t *fdset)
+{
+ fdset->fd_array[0] |= (1<< (fd & BSD_SOCKET_ID_MASK));
+}
+/*******************************************************************************/
+/* SL_FD_CLR */
+/*******************************************************************************/
+void SL_FD_CLR(_i16 fd, SlFdSet_t *fdset)
+{
+ fdset->fd_array[0] &= ~(1<< (fd & BSD_SOCKET_ID_MASK));
+}
+/*******************************************************************************/
+/* SL_FD_ISSET */
+/*******************************************************************************/
+_i16 SL_FD_ISSET(_i16 fd, SlFdSet_t *fdset)
+{
+ if( fdset->fd_array[0] & (1<< (fd & BSD_SOCKET_ID_MASK)) )
+ {
+ return 1;
+ }
+ return 0;
+}
+/*******************************************************************************/
+/* SL_FD_ZERO */
+/*******************************************************************************/
+void SL_FD_ZERO(SlFdSet_t *fdset)
+{
+ fdset->fd_array[0] = 0;
+}
+
+#endif
+
+/*******************************************************************************/
+/* _sl_HandleAsync_Select */
+/*******************************************************************************/
+void _sl_HandleAsync_Select(void *pVoidBuf)
+{
+ _SelectAsyncResponse_t *pMsgArgs = (_SelectAsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf);
+
+ OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER));
+
+ VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs);
+
+ sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_SelectAsyncResponse_t));
+ OSI_RET_OK_CHECK(sl_SyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj));
+
+ OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj));
+ return;
+}
+
diff --git a/cc3200/simplelink/source/spawn.c b/cc3200/simplelink/source/spawn.c
new file mode 100644
index 0000000000..fdf1930ca4
--- /dev/null
+++ b/cc3200/simplelink/source/spawn.c
@@ -0,0 +1,197 @@
+/*
+ * spawn.c - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include "simplelink.h"
+
+
+#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN))
+
+#define _SL_MAX_INTERNAL_SPAWN_ENTRIES 10
+
+typedef struct _SlInternalSpawnEntry_t
+{
+ _SlSpawnEntryFunc_t pEntry;
+ void* pValue;
+ struct _SlInternalSpawnEntry_t* pNext;
+}_SlInternalSpawnEntry_t;
+
+typedef struct
+{
+ _SlInternalSpawnEntry_t SpawnEntries[_SL_MAX_INTERNAL_SPAWN_ENTRIES];
+ _SlInternalSpawnEntry_t* pFree;
+ _SlInternalSpawnEntry_t* pWaitForExe;
+ _SlInternalSpawnEntry_t* pLastInWaitList;
+ _SlSyncObj_t SyncObj;
+ _SlLockObj_t LockObj;
+}_SlInternalSpawnCB_t;
+
+_SlInternalSpawnCB_t g_SlInternalSpawnCB;
+
+
+void _SlInternalSpawnTaskEntry()
+{
+ _i16 i;
+ _SlInternalSpawnEntry_t* pEntry;
+ _u8 LastEntry;
+
+ /* create and lock the locking object. lock in order to avoid race condition
+ on the first creation */
+ sl_LockObjCreate(&g_SlInternalSpawnCB.LockObj,"SlSpawnProtect");
+ sl_LockObjLock(&g_SlInternalSpawnCB.LockObj,SL_OS_NO_WAIT);
+
+ /* create and clear the sync object */
+ sl_SyncObjCreate(&g_SlInternalSpawnCB.SyncObj,"SlSpawnSync");
+ sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj,SL_OS_NO_WAIT);
+
+ g_SlInternalSpawnCB.pFree = &g_SlInternalSpawnCB.SpawnEntries[0];
+ g_SlInternalSpawnCB.pWaitForExe = NULL;
+ g_SlInternalSpawnCB.pLastInWaitList = NULL;
+
+ /* create the link list between the entries */
+ for (i=0 ; i<_SL_MAX_INTERNAL_SPAWN_ENTRIES - 1 ; i++)
+ {
+ g_SlInternalSpawnCB.SpawnEntries[i].pNext = &g_SlInternalSpawnCB.SpawnEntries[i+1];
+ g_SlInternalSpawnCB.SpawnEntries[i].pEntry = NULL;
+ }
+ g_SlInternalSpawnCB.SpawnEntries[i].pNext = NULL;
+
+ sl_LockObjUnlock(&g_SlInternalSpawnCB.LockObj);
+
+
+ /* here we ready to execute entries */
+
+ while (TRUE)
+ {
+ sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj,SL_OS_WAIT_FOREVER);
+ /* go over all entries that already waiting for execution */
+ LastEntry = FALSE;
+ do
+ {
+ /* get entry to execute */
+ sl_LockObjLock(&g_SlInternalSpawnCB.LockObj,SL_OS_WAIT_FOREVER);
+
+ pEntry = g_SlInternalSpawnCB.pWaitForExe;
+ if ( NULL == pEntry )
+ {
+ sl_LockObjUnlock(&g_SlInternalSpawnCB.LockObj);
+ break;
+ }
+ g_SlInternalSpawnCB.pWaitForExe = pEntry->pNext;
+ if (pEntry == g_SlInternalSpawnCB.pLastInWaitList)
+ {
+ g_SlInternalSpawnCB.pLastInWaitList = NULL;
+ LastEntry = TRUE;
+ }
+
+ sl_LockObjUnlock(&g_SlInternalSpawnCB.LockObj);
+
+
+ /* pEntry could be null in case that the sync was already set by some
+ of the entries during execution of earlier entry */
+ if (NULL != pEntry)
+ {
+ pEntry->pEntry(pEntry->pValue);
+ /* free the entry */
+ sl_LockObjLock(&g_SlInternalSpawnCB.LockObj,SL_OS_WAIT_FOREVER);
+
+ pEntry->pNext = g_SlInternalSpawnCB.pFree;
+ g_SlInternalSpawnCB.pFree = pEntry;
+
+
+ if (NULL != g_SlInternalSpawnCB.pWaitForExe)
+ {
+ /* new entry received meanwhile */
+ LastEntry = FALSE;
+ }
+
+ sl_LockObjUnlock(&g_SlInternalSpawnCB.LockObj);
+
+ }
+
+ }while (!LastEntry);
+ }
+}
+
+
+_i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags)
+{
+ _i16 Res = 0;
+ _SlInternalSpawnEntry_t* pSpawnEntry;
+
+ if (NULL == pEntry)
+ {
+ Res = -1;
+ }
+ else
+ {
+ sl_LockObjLock(&g_SlInternalSpawnCB.LockObj,SL_OS_WAIT_FOREVER);
+
+ pSpawnEntry = g_SlInternalSpawnCB.pFree;
+ g_SlInternalSpawnCB.pFree = pSpawnEntry->pNext;
+
+ pSpawnEntry->pEntry = pEntry;
+ pSpawnEntry->pValue = pValue;
+ pSpawnEntry->pNext = NULL;
+
+ if (NULL == g_SlInternalSpawnCB.pWaitForExe)
+ {
+ g_SlInternalSpawnCB.pWaitForExe = pSpawnEntry;
+ g_SlInternalSpawnCB.pLastInWaitList = pSpawnEntry;
+ }
+ else
+ {
+ g_SlInternalSpawnCB.pLastInWaitList->pNext = pSpawnEntry;
+ g_SlInternalSpawnCB.pLastInWaitList = pSpawnEntry;
+ }
+
+ sl_LockObjUnlock(&g_SlInternalSpawnCB.LockObj);
+ /* this sync is called after releasing the lock object to avoid unnecessary context switches */
+ sl_SyncObjSignal(&g_SlInternalSpawnCB.SyncObj);
+ }
+
+ return Res;
+}
+
+
+
+
+
+#endif
diff --git a/cc3200/simplelink/source/spawn.h b/cc3200/simplelink/source/spawn.h
new file mode 100644
index 0000000000..82c112d2e1
--- /dev/null
+++ b/cc3200/simplelink/source/spawn.h
@@ -0,0 +1,63 @@
+/*
+ * spawn.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+#ifndef __NONOS_H__
+#define __NONOS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN))
+
+extern void _SlInternalSpawnTaskEntry();
+extern _i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags);
+
+#undef sl_Spawn
+#define sl_Spawn(pEntry,pValue,flags) _SlInternalSpawn(pEntry,pValue,flags)
+
+#undef _SlTaskEntry
+#define _SlTaskEntry _SlInternalSpawnTaskEntry
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/cc3200/simplelink/source/wlan.c b/cc3200/simplelink/source/wlan.c
new file mode 100644
index 0000000000..648a624e1f
--- /dev/null
+++ b/cc3200/simplelink/source/wlan.c
@@ -0,0 +1,993 @@
+/*
+* wlan.c - CC31xx/CC32xx Host Driver Implementation
+*
+* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+*
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+/*****************************************************************************/
+/* Include files */
+/*****************************************************************************/
+#include
+#include "simplelink.h"
+#include "protocol.h"
+#include "driver.h"
+
+/*****************************************************************************/
+/* Macro declarations */
+/*****************************************************************************/
+#define MAX_SSID_LEN (32)
+#define MAX_KEY_LEN (63)
+#define MAX_USER_LEN (32)
+#define MAX_ANON_USER_LEN (32)
+#define MAX_SMART_CONFIG_KEY (16)
+
+
+/*****************************************************************************
+sl_WlanConnect
+*****************************************************************************/
+typedef struct
+{
+ _WlanConnectEapCommand_t Args;
+ _i8 Strings[MAX_SSID_LEN + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN];
+}_WlanConnectCmd_t;
+
+typedef union
+{
+ _WlanConnectCmd_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlWlanConnectMsg_u;
+
+
+#if _SL_INCLUDE_FUNC(sl_WlanConnect)
+_i16 sl_WlanConnect(_i8* pName, _i16 NameLen, _u8 *pMacAddr, SlSecParams_t* pSecParams , SlSecParamsExt_t* pSecExtParams)
+{
+ _SlWlanConnectMsg_u Msg;
+ _SlCmdCtrl_t CmdCtrl;
+
+ // Clear the above structures
+ memset (&Msg, 0, sizeof(Msg));
+ memset (&CmdCtrl, 0, sizeof(CmdCtrl));
+
+ CmdCtrl.TxDescLen = 0;/* init */
+ CmdCtrl.RxDescLen = sizeof(_BasicResponse_t);
+
+ /* verify SSID length */
+ VERIFY_PROTOCOL(NameLen <= MAX_SSID_LEN);
+ /* update SSID length */
+ Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen;
+
+ /* Profile with no security */
+ /* Enterprise security profile */
+ if (NULL != pSecExtParams)
+ {
+ /* Update command opcode */
+ CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND;
+ CmdCtrl.TxDescLen += sizeof(_WlanConnectEapCommand_t);
+ /* copy SSID */
+ sl_Memcpy(EAP_SSID_STRING(&Msg), pName, NameLen);
+ CmdCtrl.TxDescLen += NameLen;
+ /* Copy password if supplied */
+ if ((NULL != pSecParams) && (pSecParams->KeyLen > 0))
+ {
+ /* update security type */
+ Msg.Cmd.Args.Common.SecType = pSecParams->Type;
+ /* verify key length */
+ if (pSecParams->KeyLen > MAX_KEY_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ /* update key length */
+ Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen;
+ ARG_CHECK_PTR(pSecParams->Key);
+ /* copy key */
+ sl_Memcpy(EAP_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen);
+ CmdCtrl.TxDescLen += pSecParams->KeyLen;
+ }
+ else
+ {
+ Msg.Cmd.Args.Common.PasswordLen = 0;
+ }
+
+ ARG_CHECK_PTR(pSecExtParams);
+ /* Update Eap bitmask */
+ Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod;
+ /* Update Certificate file ID index - currently not supported */
+ Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex;
+ /* verify user length */
+ if (pSecExtParams->UserLen > MAX_USER_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ Msg.Cmd.Args.UserLen = pSecExtParams->UserLen;
+ /* copy user name (identity) */
+ if(pSecExtParams->UserLen > 0)
+ {
+ sl_Memcpy(EAP_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen);
+ CmdCtrl.TxDescLen += pSecExtParams->UserLen;
+ }
+ /* verify Anonymous user length */
+ if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen;
+ /* copy Anonymous user */
+ if(pSecExtParams->AnonUserLen > 0)
+ {
+ sl_Memcpy(EAP_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen);
+ CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen;
+ }
+
+ }
+
+ /* Regular or open security profile */
+ else
+ {
+ /* Update command opcode */
+ CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTCOMMAND;
+ CmdCtrl.TxDescLen += sizeof(_WlanConnectCommon_t);
+ /* copy SSID */
+ sl_Memcpy(SSID_STRING(&Msg), pName, NameLen);
+ CmdCtrl.TxDescLen += NameLen;
+ /* Copy password if supplied */
+ if( NULL != pSecParams )
+ {
+ /* update security type */
+ Msg.Cmd.Args.Common.SecType = pSecParams->Type;
+ /* verify key length is valid */
+ if (pSecParams->KeyLen > MAX_KEY_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ /* update key length */
+ Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen;
+ CmdCtrl.TxDescLen += pSecParams->KeyLen;
+ /* copy key (could be no key in case of WPS pin) */
+ if( NULL != pSecParams->Key )
+ {
+ sl_Memcpy(PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen);
+ }
+ }
+ /* Profile with no security */
+ else
+ {
+ Msg.Cmd.Args.Common.PasswordLen = 0;
+ Msg.Cmd.Args.Common.SecType = SL_SEC_TYPE_OPEN;
+ }
+ }
+ /* If BSSID is not null, copy to buffer, otherwise set to 0 */
+ if(NULL != pMacAddr)
+ {
+ sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid));
+ }
+ else
+ {
+ sl_Memset(Msg.Cmd.Args.Common.Bssid, 0, sizeof(Msg.Cmd.Args.Common.Bssid));
+ }
+
+
+ VERIFY_RET_OK ( _SlDrvCmdOp(&CmdCtrl, &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_Disconnect */
+/* ******************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_WlanDisconnect)
+_i16 sl_WlanDisconnect(void)
+{
+ return _SlDrvBasicCmd(SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND);
+}
+#endif
+
+/******************************************************************************/
+/* sl_PolicySet */
+/******************************************************************************/
+typedef union
+{
+ _WlanPoliciySetGet_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlPolicyMsg_u;
+
+const _SlCmdCtrl_t _SlPolicySetCmdCtrl =
+{
+ SL_OPCODE_WLAN_POLICYSETCOMMAND,
+ sizeof(_WlanPoliciySetGet_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_WlanPolicySet)
+_i16 sl_WlanPolicySet(_u8 Type , const _u8 Policy, _u8 *pVal,_u8 ValLen)
+{
+ _SlPolicyMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = ValLen;
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pVal;
+ CmdExt.pRxPayload = NULL;
+
+
+ Msg.Cmd.PolicyType = Type;
+ Msg.Cmd.PolicyOption = Policy;
+ Msg.Cmd.PolicyOptionLen = ValLen;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicySetCmdCtrl, &Msg, &CmdExt));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+
+/******************************************************************************/
+/* sl_PolicyGet */
+/******************************************************************************/
+typedef union
+{
+ _WlanPoliciySetGet_t Cmd;
+ _WlanPoliciySetGet_t Rsp;
+}_SlPolicyGetMsg_u;
+
+const _SlCmdCtrl_t _SlPolicyGetCmdCtrl =
+{
+ SL_OPCODE_WLAN_POLICYGETCOMMAND,
+ sizeof(_WlanPoliciySetGet_t),
+ sizeof(_WlanPoliciySetGet_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet)
+_i16 sl_WlanPolicyGet(_u8 Type , _u8 Policy,_u8 *pVal,_u8 *pValLen)
+{
+ _SlPolicyGetMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (*pValLen == 0)
+ {
+ return SL_EZEROLEN;
+ }
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = *pValLen;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = pVal;
+ CmdExt.ActualRxPayloadLen = 0;
+
+
+ Msg.Cmd.PolicyType = Type;
+ Msg.Cmd.PolicyOption = Policy;
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicyGetCmdCtrl, &Msg, &CmdExt));
+
+
+ if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen)
+ {
+ *pValLen = Msg.Rsp.PolicyOptionLen;
+ return SL_ESMALLBUF;
+ }
+ else
+ {
+ /* no pointer valus, fill the results into _i8 */
+ *pValLen = (_u8)CmdExt.ActualRxPayloadLen;
+ if( 0 == CmdExt.ActualRxPayloadLen )
+ {
+ *pValLen = 1;
+ pVal[0] = Msg.Rsp.PolicyOption;
+ }
+ }
+ return (_i16)SL_OS_RET_CODE_OK;
+}
+#endif
+
+
+/*******************************************************************************/
+/* sl_ProfileAdd */
+/*******************************************************************************/
+typedef struct
+{
+ _WlanAddGetEapProfile_t Args;
+ _i8 Strings[MAX_SSID_LEN + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN];
+}_SlProfileParams_t;
+
+typedef union
+{
+ _SlProfileParams_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlProfileAddMsg_u;
+
+
+
+#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd)
+_i16 sl_WlanProfileAdd(_i8* pName, _i16 NameLen, _u8 *pMacAddr, SlSecParams_t* pSecParams , SlSecParamsExt_t* pSecExtParams, _u32 Priority, _u32 Options)
+{
+ _SlProfileAddMsg_u Msg;
+ _SlCmdCtrl_t CmdCtrl = {0};
+ CmdCtrl.TxDescLen = 0;/* init */
+ CmdCtrl.RxDescLen = sizeof(_BasicResponse_t);
+
+ /* update priority */
+ Msg.Cmd.Args.Common.Priority = (_u8)Priority;
+ /* verify SSID length */
+ VERIFY_PROTOCOL(NameLen <= MAX_SSID_LEN);
+ /* update SSID length */
+ Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen;
+
+
+ /* Enterprise security profile */
+ if (NULL != pSecExtParams)
+ {
+ /* Update command opcode */
+ CmdCtrl.Opcode = SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND;
+ CmdCtrl.TxDescLen += sizeof(_WlanAddGetEapProfile_t);
+
+ /* copy SSID */
+ sl_Memcpy(EAP_PROFILE_SSID_STRING(&Msg), pName, NameLen);
+ CmdCtrl.TxDescLen += NameLen;
+
+ /* Copy password if supplied */
+ if ((NULL != pSecParams) && (pSecParams->KeyLen > 0))
+ {
+ /* update security type */
+ Msg.Cmd.Args.Common.SecType = pSecParams->Type;
+
+ if( SL_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType )
+ {
+ Msg.Cmd.Args.Common.WepKeyId = 0;
+ }
+
+ /* verify key length */
+ if (pSecParams->KeyLen > MAX_KEY_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ VERIFY_PROTOCOL(pSecParams->KeyLen <= MAX_KEY_LEN);
+ /* update key length */
+ Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen;
+ CmdCtrl.TxDescLen += pSecParams->KeyLen;
+ ARG_CHECK_PTR(pSecParams->Key);
+ /* copy key */
+ sl_Memcpy(EAP_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen);
+ }
+ else
+ {
+ Msg.Cmd.Args.Common.PasswordLen = 0;
+ }
+
+ ARG_CHECK_PTR(pSecExtParams);
+ /* Update Eap bitmask */
+ Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod;
+ /* Update Certificate file ID index - currently not supported */
+ Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex;
+ /* verify user length */
+ if (pSecExtParams->UserLen > MAX_USER_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ Msg.Cmd.Args.UserLen = pSecExtParams->UserLen;
+ /* copy user name (identity) */
+ if(pSecExtParams->UserLen > 0)
+ {
+ sl_Memcpy(EAP_PROFILE_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen);
+ CmdCtrl.TxDescLen += pSecExtParams->UserLen;
+ }
+
+ /* verify Anonymous user length (for tunneled) */
+ if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen;
+
+ /* copy Anonymous user */
+ if(pSecExtParams->AnonUserLen > 0)
+ {
+ sl_Memcpy(EAP_PROFILE_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen);
+ CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen;
+ }
+
+ }
+ /* Regular or open security profile */
+ else
+ {
+ /* Update command opcode */
+ CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEADDCOMMAND;
+ /* update commnad length */
+ CmdCtrl.TxDescLen += sizeof(_WlanAddGetProfile_t);
+
+ if (NULL != pName)
+ {
+ /* copy SSID */
+ sl_Memcpy(PROFILE_SSID_STRING(&Msg), pName, NameLen);
+ CmdCtrl.TxDescLen += NameLen;
+ }
+
+ /* Copy password if supplied */
+ if( NULL != pSecParams )
+ {
+ /* update security type */
+ Msg.Cmd.Args.Common.SecType = pSecParams->Type;
+
+ if( SL_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType )
+ {
+ Msg.Cmd.Args.Common.WepKeyId = 0;
+ }
+
+ /* verify key length */
+ if (pSecParams->KeyLen > MAX_KEY_LEN)
+ {
+ return SL_INVALPARAM;
+ }
+ /* update key length */
+ Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen;
+ CmdCtrl.TxDescLen += pSecParams->KeyLen;
+ /* copy key (could be no key in case of WPS pin) */
+ if( NULL != pSecParams->Key )
+ {
+ sl_Memcpy(PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen);
+ }
+ }
+ else
+ {
+ Msg.Cmd.Args.Common.SecType = SL_SEC_TYPE_OPEN;
+ Msg.Cmd.Args.Common.PasswordLen = 0;
+ }
+
+ }
+
+
+ /* If BSSID is not null, copy to buffer, otherwise set to 0 */
+ if(NULL != pMacAddr)
+ {
+ sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid));
+ }
+ else
+ {
+ sl_Memset(Msg.Cmd.Args.Common.Bssid, 0, sizeof(Msg.Cmd.Args.Common.Bssid));
+ }
+
+ VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+/*******************************************************************************/
+/* sl_ProfileGet */
+/*******************************************************************************/
+typedef union
+{
+ _WlanProfileDelGetCommand_t Cmd;
+ _SlProfileParams_t Rsp;
+}_SlProfileGetMsg_u;
+
+const _SlCmdCtrl_t _SlProfileGetCmdCtrl =
+{
+ SL_OPCODE_WLAN_PROFILEGETCOMMAND,
+ sizeof(_WlanProfileDelGetCommand_t),
+ sizeof(_SlProfileParams_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_WlanProfileGet)
+_i16 sl_WlanProfileGet(_i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlSecParams_t* pSecParams, SlGetSecParamsExt_t* pEntParams, _u32 *pPriority)
+{
+ _SlProfileGetMsg_u Msg;
+ Msg.Cmd.index = (_u8)Index;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileGetCmdCtrl, &Msg, NULL));
+
+ pSecParams->Type = Msg.Rsp.Args.Common.SecType;
+ /* since password is not transferred in getprofile, password length should always be zero */
+ pSecParams->KeyLen = Msg.Rsp.Args.Common.PasswordLen;
+ if (NULL != pEntParams)
+ {
+ pEntParams->UserLen = Msg.Rsp.Args.UserLen;
+ /* copy user name */
+ if (pEntParams->UserLen > 0)
+ {
+ sl_Memcpy(pEntParams->User, EAP_PROFILE_USER_STRING(&Msg), pEntParams->UserLen);
+ }
+ pEntParams->AnonUserLen = Msg.Rsp.Args.AnonUserLen;
+ /* copy anonymous user name */
+ if (pEntParams->AnonUserLen > 0)
+ {
+ sl_Memcpy(pEntParams->AnonUser, EAP_PROFILE_ANON_USER_STRING(&Msg), pEntParams->AnonUserLen);
+ }
+ }
+
+ *pNameLen = Msg.Rsp.Args.Common.SsidLen;
+ *pPriority = Msg.Rsp.Args.Common.Priority;
+
+ if (NULL != Msg.Rsp.Args.Common.Bssid)
+ {
+ sl_Memcpy(pMacAddr, Msg.Rsp.Args.Common.Bssid, sizeof(Msg.Rsp.Args.Common.Bssid));
+ }
+
+ sl_Memcpy(pName, EAP_PROFILE_SSID_STRING(&Msg), *pNameLen);
+
+ return (_i16)Msg.Rsp.Args.Common.SecType;
+
+}
+#endif
+/*******************************************************************************/
+/* sl_ProfileDel */
+/*******************************************************************************/
+typedef union
+{
+ _WlanProfileDelGetCommand_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlProfileDelMsg_u;
+
+const _SlCmdCtrl_t _SlProfileDelCmdCtrl =
+{
+ SL_OPCODE_WLAN_PROFILEDELCOMMAND,
+ sizeof(_WlanProfileDelGetCommand_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_WlanProfileDel)
+_i16 sl_WlanProfileDel(_i16 Index)
+{
+ _SlProfileDelMsg_u Msg;
+
+ Msg.Cmd.index = (_u8)Index;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileDelCmdCtrl, &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+
+/******************************************************************************/
+/* sl_WlanGetNetworkList */
+/******************************************************************************/
+typedef union
+{
+ _WlanGetNetworkListCommand_t Cmd;
+ _WlanGetNetworkListResponse_t Rsp;
+}_SlWlanGetNetworkListMsg_u;
+
+const _SlCmdCtrl_t _SlWlanGetNetworkListCtrl =
+{
+ SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND,
+ sizeof(_WlanGetNetworkListCommand_t),
+ sizeof(_WlanGetNetworkListResponse_t)
+};
+
+
+#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList)
+_i16 sl_WlanGetNetworkList(_u8 Index, _u8 Count, Sl_WlanNetworkEntry_t *pEntries)
+{
+ _i16 retVal = 0;
+ _SlWlanGetNetworkListMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (Count == 0)
+ {
+ return SL_EZEROLEN;
+ }
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = sizeof(Sl_WlanNetworkEntry_t)*(Count);
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)pEntries;
+
+ Msg.Cmd.index = Index;
+ Msg.Cmd.count = Count;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanGetNetworkListCtrl, &Msg, &CmdExt));
+ retVal = Msg.Rsp.status;
+
+ return (_i16)retVal;
+}
+#endif
+
+
+
+
+
+/******************************************************************************/
+/* RX filters message command response structures */
+/******************************************************************************/
+
+/* Set command */
+typedef union
+{
+ _WlanRxFilterAddCommand_t Cmd;
+ _WlanRxFilterAddCommandReponse_t Rsp;
+}_SlrxFilterAddMsg_u;
+
+const _SlCmdCtrl_t _SlRxFilterAddtCmdCtrl =
+{
+ SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND,
+ sizeof(_WlanRxFilterAddCommand_t),
+ sizeof(_WlanRxFilterAddCommandReponse_t)
+};
+
+
+/* Set command */
+typedef union _SlRxFilterSetMsg_u
+{
+ _WlanRxFilterSetCommand_t Cmd;
+ _WlanRxFilterSetCommandReponse_t Rsp;
+}_SlRxFilterSetMsg_u;
+
+
+const _SlCmdCtrl_t _SlRxFilterSetCmdCtrl =
+{
+ SL_OPCODE_WLAN_WLANRXFILTERSETCOMMAND,
+ sizeof(_WlanRxFilterSetCommand_t),
+ sizeof(_WlanRxFilterSetCommandReponse_t)
+};
+
+/* Get command */
+typedef union _SlRxFilterGetMsg_u
+{
+ _WlanRxFilterGetCommand_t Cmd;
+ _WlanRxFilterGetCommandReponse_t Rsp;
+}_SlRxFilterGetMsg_u;
+
+
+const _SlCmdCtrl_t _SlRxFilterGetCmdCtrl =
+{
+ SL_OPCODE_WLAN_WLANRXFILTERGETCOMMAND,
+ sizeof(_WlanRxFilterGetCommand_t),
+ sizeof(_WlanRxFilterGetCommandReponse_t)
+};
+
+
+/*******************************************************************************/
+/* RX filters */
+/*******************************************************************************/
+
+#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd)
+SlrxFilterID_t sl_WlanRxFilterAdd( SlrxFilterRuleType_t RuleType,
+ SlrxFilterFlags_t FilterFlags,
+ const SlrxFilterRule_t* const Rule,
+ const SlrxFilterTrigger_t* const Trigger,
+ const SlrxFilterAction_t* const Action,
+ SlrxFilterID_t* pFilterId)
+{
+
+
+ _SlrxFilterAddMsg_u Msg;
+ Msg.Cmd.RuleType = RuleType;
+ /* filterId is zero */
+ Msg.Cmd.FilterId = 0;
+ Msg.Cmd.FilterFlags = FilterFlags;
+ sl_Memcpy( &(Msg.Cmd.Rule), Rule, sizeof(SlrxFilterRule_t) );
+ sl_Memcpy( &(Msg.Cmd.Trigger), Trigger, sizeof(SlrxFilterTrigger_t) );
+ sl_Memcpy( &(Msg.Cmd.Action), Action, sizeof(SlrxFilterAction_t) );
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlRxFilterAddtCmdCtrl, &Msg, NULL) );
+ *pFilterId = Msg.Rsp.FilterId;
+ return (_i16)Msg.Rsp.Status;
+
+}
+#endif
+
+
+
+/*******************************************************************************/
+/* RX filters */
+/*******************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_WlanRxFilterSet)
+_i16 sl_WlanRxFilterSet(const SLrxFilterOperation_t RxFilterOperation,
+ const _u8* const pInputBuffer,
+ _u16 InputbufferLength)
+{
+ _SlRxFilterSetMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = InputbufferLength;
+ CmdExt.pTxPayload = (_u8 *)pInputBuffer;
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pRxPayload = (_u8 *)NULL;
+
+ Msg.Cmd.RxFilterOperation = RxFilterOperation;
+ Msg.Cmd.InputBufferLength = InputbufferLength;
+
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlRxFilterSetCmdCtrl, &Msg, &CmdExt) );
+
+
+ return (_i16)Msg.Rsp.Status;
+}
+#endif
+
+/******************************************************************************/
+/* RX filters */
+/******************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_WlanRxFilterGet)
+_i16 sl_WlanRxFilterGet(const SLrxFilterOperation_t RxFilterOperation,
+ _u8* pOutputBuffer,
+ _u16 OutputbufferLength)
+{
+ _SlRxFilterGetMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (OutputbufferLength == 0)
+ {
+ return SL_EZEROLEN;
+ }
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.RxPayloadLen = OutputbufferLength;
+ CmdExt.pRxPayload = (_u8 *)pOutputBuffer;
+ CmdExt.ActualRxPayloadLen = 0;
+
+ Msg.Cmd.RxFilterOperation = RxFilterOperation;
+ Msg.Cmd.OutputBufferLength = OutputbufferLength;
+
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlRxFilterGetCmdCtrl, &Msg, &CmdExt) );
+
+ if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen)
+ {
+ return SL_ESMALLBUF;
+ }
+
+ return (_i16)Msg.Rsp.Status;
+}
+#endif
+
+/*******************************************************************************/
+/* sl_WlanRxStatStart */
+/*******************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart)
+_i16 sl_WlanRxStatStart(void)
+{
+ return _SlDrvBasicCmd(SL_OPCODE_WLAN_STARTRXSTATCOMMAND);
+}
+#endif
+
+#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop)
+_i16 sl_WlanRxStatStop(void)
+{
+ return _SlDrvBasicCmd(SL_OPCODE_WLAN_STOPRXSTATCOMMAND);
+}
+#endif
+
+#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet)
+_i16 sl_WlanRxStatGet(SlGetRxStatResponse_t *pRxStat,_u32 Flags)
+{
+ _SlCmdCtrl_t CmdCtrl = {SL_OPCODE_WLAN_GETRXSTATCOMMAND, 0, sizeof(SlGetRxStatResponse_t)};
+ sl_Memset(pRxStat,0,sizeof(SlGetRxStatResponse_t));
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, pRxStat, NULL));
+
+ return 0;
+}
+#endif
+
+
+
+/******************************************************************************/
+/* sl_WlanSmartConfigStop */
+/******************************************************************************/
+#if _SL_INCLUDE_FUNC(sl_WlanSmartConfigStop)
+_i16 sl_WlanSmartConfigStop(void)
+{
+ return _SlDrvBasicCmd(SL_OPCODE_WLAN_SMART_CONFIG_STOP_COMMAND);
+}
+#endif
+
+
+/******************************************************************************/
+/* sl_WlanSmartConfigStart */
+/******************************************************************************/
+
+
+typedef struct
+{
+ _WlanSmartConfigStartCommand_t Args;
+ _i8 Strings[3 * MAX_SMART_CONFIG_KEY]; /* public key + groupId1 key + groupId2 key */
+}_SlSmartConfigStart_t;
+
+typedef union
+{
+ _SlSmartConfigStart_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlSmartConfigStartMsg_u;
+
+const _SlCmdCtrl_t _SlSmartConfigStartCmdCtrl =
+{
+ SL_OPCODE_WLAN_SMART_CONFIG_START_COMMAND,
+ sizeof(_SlSmartConfigStart_t),
+ sizeof(_BasicResponse_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_WlanSmartConfigStart)
+_i16 sl_WlanSmartConfigStart( const _u32 groupIdBitmask,
+ const _u8 cipher,
+ const _u8 publicKeyLen,
+ const _u8 group1KeyLen,
+ const _u8 group2KeyLen,
+ const _u8* pPublicKey,
+ const _u8* pGroup1Key,
+ const _u8* pGroup2Key)
+{
+ _SlSmartConfigStartMsg_u Msg;
+
+ Msg.Cmd.Args.groupIdBitmask = (_u8)groupIdBitmask;
+ Msg.Cmd.Args.cipher = (_u8)cipher;
+ Msg.Cmd.Args.publicKeyLen = (_u8)publicKeyLen;
+ Msg.Cmd.Args.group1KeyLen = (_u8)group1KeyLen;
+ Msg.Cmd.Args.group2KeyLen = (_u8)group2KeyLen;
+
+ /* copy keys (if exist) after command (one after another) */
+ sl_Memcpy(SMART_CONFIG_START_PUBLIC_KEY_STRING(&Msg), pPublicKey, publicKeyLen);
+ sl_Memcpy(SMART_CONFIG_START_GROUP1_KEY_STRING(&Msg), pGroup1Key, group1KeyLen);
+ sl_Memcpy(SMART_CONFIG_START_GROUP2_KEY_STRING(&Msg), pGroup2Key, group2KeyLen);
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSmartConfigStartCmdCtrl , &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+
+
+}
+#endif
+
+
+/*******************************************************************************/
+/* sl_WlanSetMode */
+/*******************************************************************************/
+typedef union
+{
+ _WlanSetMode_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlwlanSetModeMsg_u;
+
+const _SlCmdCtrl_t _SlWlanSetModeCmdCtrl =
+{
+ SL_OPCODE_WLAN_SET_MODE,
+ sizeof(_WlanSetMode_t),
+ sizeof(_BasicResponse_t)
+};
+
+/* possible values are:
+WLAN_SET_STA_MODE = 1
+WLAN_SET_AP_MODE = 2
+WLAN_SET_P2P_MODE = 3 */
+
+#if _SL_INCLUDE_FUNC(sl_WlanSetMode)
+_i16 sl_WlanSetMode(const _u8 mode)
+{
+ _SlwlanSetModeMsg_u Msg;
+
+ Msg.Cmd.mode = mode;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanSetModeCmdCtrl , &Msg, NULL));
+
+ return (_i16)Msg.Rsp.status;
+
+}
+#endif
+
+
+
+
+/*******************************************************************************/
+/* sl_WlanSet */
+/* ******************************************************************************/
+typedef union
+{
+ _WlanCfgSetGet_t Cmd;
+ _BasicResponse_t Rsp;
+}_SlWlanCfgSetMsg_u;
+
+const _SlCmdCtrl_t _SlWlanCfgSetCmdCtrl =
+{
+ SL_OPCODE_WLAN_CFG_SET,
+ sizeof(_WlanCfgSetGet_t),
+ sizeof(_BasicResponse_t)
+};
+
+
+#if _SL_INCLUDE_FUNC(sl_WlanSet)
+_i16 sl_WlanSet(_u16 ConfigId ,_u16 ConfigOpt,_u16 ConfigLen, _u8 *pValues)
+{
+ _SlWlanCfgSetMsg_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ CmdExt.TxPayloadLen = (ConfigLen+3) & (~3);
+ CmdExt.RxPayloadLen = 0;
+ CmdExt.pTxPayload = (_u8 *)pValues;
+ CmdExt.pRxPayload = NULL;
+
+
+ Msg.Cmd.ConfigId = ConfigId;
+ Msg.Cmd.ConfigLen = ConfigLen;
+ Msg.Cmd.ConfigOpt = ConfigOpt;
+
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgSetCmdCtrl, &Msg, &CmdExt));
+
+ return (_i16)Msg.Rsp.status;
+}
+#endif
+
+
+/******************************************************************************/
+/* sl_WlanGet */
+/******************************************************************************/
+typedef union
+{
+ _WlanCfgSetGet_t Cmd;
+ _WlanCfgSetGet_t Rsp;
+}_SlWlanCfgMsgGet_u;
+
+const _SlCmdCtrl_t _SlWlanCfgGetCmdCtrl =
+{
+ SL_OPCODE_WLAN_CFG_GET,
+ sizeof(_WlanCfgSetGet_t),
+ sizeof(_WlanCfgSetGet_t)
+};
+
+#if _SL_INCLUDE_FUNC(sl_WlanGet)
+_i16 sl_WlanGet(_u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues)
+{
+ _SlWlanCfgMsgGet_u Msg;
+ _SlCmdExt_t CmdExt;
+
+ if (*pConfigLen == 0)
+ {
+ return SL_EZEROLEN;
+ }
+ CmdExt.TxPayloadLen = 0;
+ CmdExt.RxPayloadLen = *pConfigLen;
+ CmdExt.pTxPayload = NULL;
+ CmdExt.pRxPayload = (_u8 *)pValues;
+ CmdExt.ActualRxPayloadLen = 0;
+
+ Msg.Cmd.ConfigId = ConfigId;
+ if( pConfigOpt )
+ {
+ Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt;
+ }
+ VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgGetCmdCtrl, &Msg, &CmdExt));
+
+ if( pConfigOpt )
+ {
+ *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt;
+ }
+ if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen)
+ {
+ *pConfigLen = (_u8)CmdExt.RxPayloadLen;
+ return SL_ESMALLBUF;
+ }
+ else
+ {
+ *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen;
+ }
+
+
+ return (_i16)Msg.Rsp.Status;
+}
+#endif
diff --git a/cc3200/simplelink/user.h b/cc3200/simplelink/user.h
new file mode 100644
index 0000000000..82cc420ce4
--- /dev/null
+++ b/cc3200/simplelink/user.h
@@ -0,0 +1,1058 @@
+/*
+ * user.h - CC31xx/CC32xx Host Driver Implementation
+ *
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+
+#ifndef __USER_H__
+#define __USER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup porting_user_include Porting - User Include Files
+
+ This section IS NOT REQUIRED in case user provided primitives are handled
+ in makefiles or project configurations (IDE)
+
+ PORTING ACTION:
+ - Include all required header files for the definition of:
+ -# Transport layer library API (e.g. SPI, UART)
+ -# OS primitives definitions (e.g. Task spawn, Semaphores)
+ -# Memory management primitives (e.g. alloc, free)
+
+ ******************************************************************************
+ */
+
+#include
+#include "cc_pal.h"
+
+/*!
+ \def MAX_CONCURRENT_ACTIONS
+
+ \brief Defines the maximum number of concurrent action in the system
+ Min:1 , Max: 32
+
+ Actions which has async events as return, can be
+
+ \sa
+
+ \note In case there are not enough resources for the actions needed in the system,
+ error is received: POOL_IS_EMPTY
+ one option is to increase MAX_CONCURRENT_ACTIONS
+ (improves performance but results in memory consumption)
+ Other option is to call the API later (decrease performance)
+
+ \warning In case of setting to one, recommend to use non-blocking recv\recvfrom to allow
+ multiple socket recv
+*/
+#define MAX_CONCURRENT_ACTIONS 10
+/*!
+ \def CPU_FREQ_IN_MHZ
+ \brief Defines CPU frequency for Host side, for better accuracy of busy loops, if any
+ \sa
+ \note
+
+ \warning If not set the default CPU frequency is set to 200MHz
+ This option will be deprecated in future release
+*/
+
+#define CPU_FREQ_IN_MHZ 80
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup porting_capabilities Porting - Capabilities Set
+
+ This section IS NOT REQUIRED in case one of the following pre defined
+ capabilities set is in use:
+ - SL_TINY
+ - SL_SMALL
+ - SL_FULL
+
+ PORTING ACTION:
+ - Define one of the pre-defined capabilities set or uncomment the
+ relevant definitions below to select the required capabilities
+
+ @{
+
+ *******************************************************************************
+*/
+
+/*!
+ \def SL_INC_ARG_CHECK
+
+ \brief Defines whether the SimpleLink driver perform argument check
+ or not
+
+ When defined, the SimpleLink driver perform argument check on
+ function call. Removing this define could reduce some code
+ size and improve slightly the performances but may impact in
+ unpredictable behavior in case of invalid arguments
+
+ \sa
+
+ \note belongs to \ref proting_sec
+
+ \warning Removing argument check may cause unpredictable behavior in
+ case of invalid arguments.
+ In this case the user is responsible to argument validity
+ (for example all handlers must not be NULL)
+*/
+#define SL_INC_ARG_CHECK
+
+
+/*!
+ \def SL_INC_STD_BSD_API_NAMING
+
+ \brief Defines whether SimpleLink driver should expose standard BSD
+ APIs or not
+
+ When defined, the SimpleLink driver in addtion to its alternative
+ BSD APIs expose also standard BSD APIs.
+ Stadrad BSD API includs the following functions:
+ socket , close , accept , bind , listen , connect , select ,
+ setsockopt , getsockopt , recv , recvfrom , write , send , sendto ,
+ gethostbyname
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_STD_BSD_API_NAMING
+
+
+/*!
+ \brief Defines whether to include extended API in SimpleLink driver
+ or not
+
+ When defined, the SimpleLink driver will include also all
+ exteded API of the included packages
+
+ \sa ext_api
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_EXT_API
+
+/*!
+ \brief Defines whether to include WLAN package in SimpleLink driver
+ or not
+
+ When defined, the SimpleLink driver will include also
+ the WLAN package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_WLAN_PKG
+
+/*!
+ \brief Defines whether to include SOCKET package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also
+ the SOCKET package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCKET_PKG
+
+/*!
+ \brief Defines whether to include NET_APP package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also the
+ NET_APP package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_NET_APP_PKG
+
+/*!
+ \brief Defines whether to include NET_CFG package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also
+ the NET_CFG package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_NET_CFG_PKG
+
+/*!
+ \brief Defines whether to include NVMEM package in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also the
+ NVMEM package
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_NVMEM_PKG
+
+/*!
+ \brief Defines whether to include socket server side APIs
+ in SimpleLink driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ server side APIs
+
+ \sa server_side
+
+ \note
+
+ \warning
+*/
+#define SL_INC_SOCK_SERVER_SIDE_API
+
+/*!
+ \brief Defines whether to include socket client side APIs in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ client side APIs
+
+ \sa client_side
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCK_CLIENT_SIDE_API
+
+/*!
+ \brief Defines whether to include socket receive APIs in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ receive side APIs
+
+ \sa recv_api
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCK_RECV_API
+
+/*!
+ \brief Defines whether to include socket send APIs in SimpleLink
+ driver or not
+
+ When defined, the SimpleLink driver will include also socket
+ send side APIs
+
+ \sa send_api
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+#define SL_INC_SOCK_SEND_API
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup ported_enable_device Ported on CC32XX - Device Enable/Disable
+
+ The enable/disable API provide mechanism to enable/disable the network processor
+
+
+ PORTING ACTION:
+ - None
+ @{
+
+ ******************************************************************************
+ */
+
+/*!
+ \brief Preamble to the enabling the Network Processor.
+ Placeholder to implement any pre-process operations
+ before enabling networking operations.
+
+ \sa sl_DeviceEnable
+
+ \note belongs to \ref ported_sec
+
+*/
+#define sl_DeviceEnablePreamble() NwpPowerOnPreamble()
+
+/*!
+ \brief Enable the Network Processor
+
+ \sa sl_DeviceDisable
+
+ \note belongs to \ref ported_sec
+
+*/
+#define sl_DeviceEnable() NwpPowerOn()
+
+/*!
+ \brief Disable the Network Processor
+
+ \sa sl_DeviceEnable
+
+ \note belongs to \ref ported_sec
+*/
+#define sl_DeviceDisable() NwpPowerOff()
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+/*!
+ ******************************************************************************
+
+ \defgroup ported_interface Ported on CC32XX - Communication Interface
+
+ The simple link device can work with different communication
+ channels (e.g. spi/uart). Texas Instruments provides single driver
+ that can work with all these types. This section bind between the
+ physical communication interface channel and the SimpleLink driver
+
+
+ \note Correct and efficient implementation of this driver is critical
+ for the performances of the SimpleLink device on this platform.
+
+
+ PORTING ACTION:
+ - None
+
+ @{
+
+ ******************************************************************************
+*/
+
+#define _SlFd_t Fd_t
+
+/*!
+ \brief Opens an interface communication port to be used for communicating
+ with a SimpleLink device
+
+ Given an interface name and option flags, this function opens
+ the communication port and creates a file descriptor.
+ This file descriptor is used afterwards to read and write
+ data from and to this specific communication channel.
+ The speed, clock polarity, clock phase, chip select and all other
+ specific attributes of the channel are all should be set to hardcoded
+ in this function.
+
+ \param ifName - points to the interface name/path. The interface name is an
+ optional attributes that the simple link driver receives
+ on opening the driver (sl_Start).
+ In systems that the spi channel is not implemented as
+ part of the os device drivers, this parameter could be NULL.
+
+ \param flags - optional flags parameters for future use
+
+ \return upon successful completion, the function shall open the channel
+ and return a non-negative integer representing the file descriptor.
+ Otherwise, -1 shall be returned
+
+ \sa sl_IfClose , sl_IfRead , sl_IfWrite
+
+ \note The prototype of the function is as follow:
+ Fd_t xxx_IfOpen(char* pIfName , unsigned long flags);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfOpen spi_Open
+
+/*!
+ \brief Closes an opened interface communication port
+
+ \param fd - file descriptor of opened communication channel
+
+ \return upon successful completion, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa sl_IfOpen , sl_IfRead , sl_IfWrite
+
+ \note The prototype of the function is as follow:
+ int xxx_IfClose(Fd_t Fd);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfClose spi_Close
+
+/*!
+ \brief Attempts to read up to len bytes from an opened communication channel
+ into a buffer starting at pBuff.
+
+ \param fd - file descriptor of an opened communication channel
+
+ \param pBuff - pointer to the first location of a buffer that contains enough
+ space for all expected data
+
+ \param len - number of bytes to read from the communication channel
+
+ \return upon successful completion, the function shall return the number of read bytes.
+ Otherwise, 0 shall be returned
+
+ \sa sl_IfClose , sl_IfOpen , sl_IfWrite
+
+
+ \note The prototype of the function is as follow:
+ int xxx_IfRead(Fd_t Fd , char* pBuff , int Len);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfRead spi_Read
+
+/*!
+ \brief attempts to write up to len bytes to the SPI channel
+
+ \param fd - file descriptor of an opened communication channel
+
+ \param pBuff - pointer to the first location of a buffer that contains
+ the data to send over the communication channel
+
+ \param len - number of bytes to write to the communication channel
+
+ \return upon successful completion, the function shall return the number of sent bytes.
+ therwise, 0 shall be returned
+
+ \sa sl_IfClose , sl_IfOpen , sl_IfRead
+
+ \note This function could be implemented as zero copy and return only upon successful completion
+ of writing the whole buffer, but in cases that memory allocation is not too tight, the
+ function could copy the data to internal buffer, return back and complete the write in
+ parallel to other activities as long as the other SPI activities would be blocked until
+ the entire buffer write would be completed
+
+ The prototype of the function is as follow:
+ int xxx_IfWrite(Fd_t Fd , char* pBuff , int Len);
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfWrite spi_Write
+
+/*!
+ \brief register an interrupt handler routine for the host IRQ
+
+ \param InterruptHdl - pointer to interrupt handler routine
+
+ \param pValue - pointer to a memory structure that is passed
+ to the interrupt handler.
+
+ \return upon successful registration, the function shall return 0.
+ Otherwise, -1 shall be returned
+
+ \sa
+
+ \note If there is already registered interrupt handler, the function
+ should overwrite the old handler with the new one
+
+ \note If the handler is a null pointer, the function should un-register the
+ interrupt handler, and the interrupts can be disabled.
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+#define sl_IfRegIntHdlr(InterruptHdl , pValue) NwpRegisterInterruptHandler(InterruptHdl , pValue)
+
+/*!
+ \brief Masks the Host IRQ
+
+ \sa sl_IfUnMaskIntHdlr
+
+
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+
+
+#define sl_IfMaskIntHdlr() NwpMaskInterrupt()
+
+/*!
+ \brief Unmasks the Host IRQ
+
+ \sa sl_IfMaskIntHdlr
+
+
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+
+#define sl_IfUnMaskIntHdlr() NwpUnMaskInterrupt()
+
+/*!
+ \brief Write Handers for statistics debug on write
+
+ \param interface handler - pointer to interrupt handler routine
+
+
+ \return no return value
+
+ \sa
+
+ \note An optional hooks for monitoring before and after write info
+
+ \note belongs to \ref ported_sec
+
+ \warning
+*/
+/* #define SL_START_WRITE_STAT */
+
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+*/
+
+/*!
+ ******************************************************************************
+
+ \defgroup ported_os Ported on CC32XX - Operating System
+
+ The simple link driver can run on multi-threaded environment as well
+ as non-os environment (mail loop)
+
+ This section IS NOT REQUIRED in case you are working on non-os environment.
+
+ If you choose to work in multi-threaded environment under any operating system
+ you will have to provide some basic adaptation routines to allow the driver
+ to protect access to resources from different threads (locking object) and
+ to allow synchronization between threads (sync objects).
+
+ PORTING ACTION:
+ -# Uncomment SL_PLATFORM_MULTI_THREADED define
+ -# Bind locking object routines
+ -# Bind synchronization object routines
+ -# Optional - Bind spawn thread routine
+
+ @{
+
+ ******************************************************************************
+*/
+
+#define SL_PLATFORM_MULTI_THREADED
+
+
+#ifdef SL_PLATFORM_MULTI_THREADED
+#include "osi.h"
+
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define SL_OS_RET_CODE_OK ((int)OSI_OK)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define SL_OS_WAIT_FOREVER ((OsiTime_t)OSI_WAIT_FOREVER)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define SL_OS_NO_WAIT ((OsiTime_t)OSI_NO_WAIT)
+
+/*!
+ \brief type definition for a time value
+
+ \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc.
+
+ \note belongs to \ref ported_sec
+*/
+#define _SlTime_t OsiTime_t
+
+/*!
+ \brief type definition for a sync object container
+
+ Sync object is object used to synchronize between two threads or thread and interrupt handler.
+ One thread is waiting on the object and the other thread send a signal, which then
+ release the waiting thread.
+ The signal must be able to be sent from interrupt context.
+ This object is generally implemented by binary semaphore or events.
+
+ \note On each porting or platform the type could be whatever is needed - integer, structure etc.
+
+ \note belongs to \ref ported_sec
+*/
+typedef OsiSyncObj_t _SlSyncObj_t;
+
+
+/*!
+ \brief This function creates a sync object
+
+ The sync object is used for synchronization between diffrent thread or ISR and
+ a thread.
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_SyncObjCreate(pSyncObj,pName) osi_SyncObjCreate(pSyncObj)
+
+
+/*!
+ \brief This function deletes a sync object
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_SyncObjDelete(pSyncObj) osi_SyncObjDelete(pSyncObj)
+
+
+/*!
+ \brief This function generates a sync signal for the object.
+
+ All suspended threads waiting on this sync object are resumed
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signaling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function could be called from ISR context
+ \warning
+*/
+#define sl_SyncObjSignal(pSyncObj) osi_SyncObjSignal(pSyncObj)
+
+/*!
+ \brief This function generates a sync signal for the object from Interrupt
+
+ This is for RTOS that should signal from IRQ using a dedicated API
+
+ \param pSyncObj - pointer to the sync object control block
+
+ \return upon successful signaling the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note the function could be called from ISR context
+ \warning
+*/
+#define sl_SyncObjSignalFromIRQ(pSyncObj) osi_SyncObjSignalFromISR(pSyncObj)
+
+/*!
+ \brief This function waits for a sync signal of the specific sync object
+
+ \param pSyncObj - pointer to the sync object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the sync signal
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+ \return upon successful reception of the signal within the timeout window return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_SyncObjWait(pSyncObj,Timeout) osi_SyncObjWait(pSyncObj,Timeout)
+
+/*!
+ \brief type definition for a locking object container
+
+ Locking object are used to protect a resource from mutual accesses of two or more threads.
+ The locking object should suppurt reentrant locks by a signal thread.
+ This object is generally implemented by mutex semaphore
+
+ \note On each porting or platform the type could be whatever is needed - integer, structure etc.
+ \note belongs to \ref ported_sec
+*/
+typedef OsiLockObj_t _SlLockObj_t;
+
+/*!
+ \brief This function creates a locking object.
+
+ The locking object is used for protecting a shared resources between different
+ threads.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful creation the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjCreate(pLockObj,pName) osi_LockObjCreate(pLockObj)
+
+/*!
+ \brief This function deletes a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful deletion the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjDelete(pLockObj) osi_LockObjDelete(pLockObj)
+
+/*!
+ \brief This function locks a locking object.
+
+ All other threads that call this function before this thread calls
+ the osi_LockObjUnlock would be suspended
+
+ \param pLockObj - pointer to the locking object control block
+ \param Timeout - numeric value specifies the maximum number of mSec to
+ stay suspended while waiting for the locking object
+ Currently, the simple link driver uses only two values:
+ - OSI_WAIT_FOREVER
+ - OSI_NO_WAIT
+
+
+ \return upon successful reception of the locking object the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjLock(pLockObj,Timeout) osi_LockObjLock(pLockObj,Timeout)
+
+/*!
+ \brief This function unlock a locking object.
+
+ \param pLockObj - pointer to the locking object control block
+
+ \return upon successful unlocking the function should return 0
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_LockObjUnlock(pLockObj) osi_LockObjUnlock(pLockObj)
+
+#endif
+/*!
+ \brief This function call the pEntry callback from a different context
+
+ \param pEntry - pointer to the entry callback function
+
+ \param pValue - pointer to any type of memory structure that would be
+ passed to pEntry callback from the execution thread.
+
+ \param flags - execution flags - reserved for future usage
+
+ \return upon successful registration of the spawn the function should return 0
+ (the function is not blocked till the end of the execution of the function
+ and could be returned before the execution is actually completed)
+ Otherwise, a negative value indicating the error code shall be returned
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define SL_PLATFORM_EXTERNAL_SPAWN
+
+#ifdef SL_PLATFORM_EXTERNAL_SPAWN
+#define sl_Spawn(pEntry,pValue,flags) osi_Spawn(pEntry,pValue,flags)
+#endif
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+/*!
+ ******************************************************************************
+
+ \defgroup porting_mem_mgm Porting - Memory Management
+
+ This section declare in which memory management model the SimpleLink driver
+ will run:
+ -# Static
+ -# Dynamic
+
+ This section IS NOT REQUIRED in case Static model is selected.
+
+ The default memory model is Static
+
+ PORTING ACTION:
+ - If dynamic model is selected, define the alloc and free functions.
+
+ @{
+
+ *****************************************************************************
+*/
+
+/*!
+ \brief Defines whether the SimpleLink driver is working in dynamic
+ memory model or not
+
+ When defined, the SimpleLink driver use dynamic allocations
+ if dynamic allocation is selected malloc and free functions
+ must be retrieved
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define SL_MEMORY_MGMT_DYNAMIC 1
+#define SL_MEMORY_MGMT_STATIC 0
+
+#define SL_MEMORY_MGMT SL_MEMORY_MGMT_DYNAMIC
+
+#ifdef SL_MEMORY_MGMT_DYNAMIC
+#ifdef SL_PLATFORM_MULTI_THREADED
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Malloc(Size) mem_Malloc(Size)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Free(pMem) mem_Free(pMem)
+#else
+#include
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Malloc(Size) malloc(Size)
+
+/*!
+ \brief
+ \sa
+ \note belongs to \ref ported_sec
+ \warning
+*/
+#define sl_Free(pMem) free(pMem)
+#endif
+#endif
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+/*!
+ ******************************************************************************
+
+ \defgroup porting_events Porting - Event Handlers
+
+ This section includes the asynchronous event handlers routines
+
+ PORTING ACTION:
+ -Uncomment the required handler and define your routine as the value
+ of this handler
+
+ @{
+
+ ******************************************************************************
+ */
+
+/*!
+ \brief
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_GeneralEvtHdlr SimpleLinkGeneralEventHandler
+
+
+/*!
+ \brief An event handler for WLAN connection or disconnection indication
+ This event handles async WLAN events.
+ Possible events are:
+ SL_WLAN_CONNECT_EVENT - indicates WLAN is connected
+ SL_WLAN_DISCONNECT_EVENT - indicates WLAN is disconnected
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_WlanEvtHdlr SimpleLinkWlanEventHandler
+
+
+/*!
+ \brief An event handler for IP address asynchronous event. Usually accepted after new WLAN connection.
+ This event handles networking events.
+ Possible events are:
+ SL_NETAPP_IPV4_ACQUIRED - IP address was acquired (DHCP or Static)
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_NetAppEvtHdlr SimpleLinkNetAppEventHandler
+
+/*!
+ \brief A callback for HTTP server events.
+ Possible events are:
+ SL_NETAPP_HTTPGETTOKENVALUE - NWP requests to get the value of a specific token
+ SL_NETAPP_HTTPPOSTTOKENVALUE - NWP post to the host a new value for a specific token
+
+ \param pServerEvent - Contains the relevant event information (SL_NETAPP_HTTPGETTOKENVALUE or SL_NETAPP_HTTPPOSTTOKENVALUE)
+
+ \param pServerResponse - Should be filled by the user with the relevant response information (i.e SL_NETAPP_HTTPSETTOKENVALUE as a response to SL_NETAPP_HTTPGETTOKENVALUE event)
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_HttpServerCallback SimpleLinkHttpServerCallback
+/*!
+ \brief
+
+ \sa
+
+ \note belongs to \ref porting_sec
+
+ \warning
+*/
+
+#define sl_SockEvtHdlr SimpleLinkSockEventHandler
+
+
+
+#define _SL_USER_TYPES
+#define _u8 unsigned char
+#define _i8 signed char
+
+#define _u16 unsigned short
+#define _i16 signed short
+
+#define _u32 unsigned int
+#define _i32 signed int
+#define _volatile volatile
+#define _const const
+
+
+
+/*!
+
+ Close the Doxygen group.
+ @}
+
+ */
+
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // __USER_H__
diff --git a/cc3200/telnet/telnet.c b/cc3200/telnet/telnet.c
new file mode 100644
index 0000000000..64c4805803
--- /dev/null
+++ b/cc3200/telnet/telnet.c
@@ -0,0 +1,482 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "mpconfig.h"
+#include MICROPY_HAL_H
+#include "misc.h"
+#include "nlr.h"
+#include "qstr.h"
+#include "obj.h"
+#include "telnet.h"
+#include "simplelink.h"
+#include "modwlan.h"
+#include "debug.h"
+#include "mpexception.h"
+#include "serverstask.h"
+#include "pybstdio.h"
+#include "genhdr/py-version.h"
+
+
+/******************************************************************************
+ DEFINE PRIVATE CONSTANTS
+ ******************************************************************************/
+#define TELNET_PORT 23
+#define TELNET_RX_BUFFER_SIZE 256
+#define TELNET_MAX_CLIENTS 1
+#define TELNET_TX_RETRIES_MAX 25
+#define TELNET_WAIT_TIME_MS 7
+#define TELNET_LOGIN_RETRIES_MAX 3
+#define TELNET_TIMEOUT_MS 300000 // 5 minutes
+#define TELNET_CYCLE_TIME_MS (SERVERS_CYCLE_TIME_MS * 2)
+
+/******************************************************************************
+ DEFINE PRIVATE TYPES
+ ******************************************************************************/
+typedef enum {
+ E_TELNET_RESULT_OK = 0,
+ E_TELNET_RESULT_AGAIN,
+ E_TELNET_RESULT_FAILED
+} telnet_result_t;
+
+typedef enum {
+ E_TELNET_STE_DISABLED = 0,
+ E_TELNET_STE_START,
+ E_TELNET_STE_LISTEN,
+ E_TELNET_STE_CONNECTED,
+ E_TELNET_STE_LOGGED_IN
+} telnet_state_t;
+
+typedef enum {
+ E_TELNET_STE_SUB_WELCOME,
+ E_TELNET_STE_SUB_SND_USER_OPTIONS,
+ E_TELNET_STE_SUB_REQ_USER,
+ E_TELNET_STE_SUB_GET_USER,
+ E_TELNET_STE_SUB_REQ_PASSWORD,
+ E_TELNET_STE_SUB_SND_PASSWORD_OPTIONS,
+ E_TELNET_STE_SUB_GET_PASSWORD,
+ E_TELNET_STE_SUB_INVALID_LOGGIN,
+ E_TELNET_STE_SUB_SND_REPL_OPTIONS,
+ E_TELNET_STE_SUB_LOGGIN_SUCCESS
+} telnet_connected_substate_t;
+
+typedef union {
+ telnet_connected_substate_t connected;
+} telnet_substate_t;
+
+typedef struct {
+ uint8_t *rxBuffer;
+ int16_t sd;
+ int16_t n_sd;
+ int16_t rxWindex;
+ int16_t rxRindex;
+ uint16_t timeout;
+ telnet_state_t state;
+ telnet_substate_t substate;
+ uint8_t txRetries;
+ uint8_t logginRetries;
+ bool enabled;
+ bool credentialsValid;
+} telnet_data_t;
+
+/******************************************************************************
+ DECLARE PRIVATE DATA
+ ******************************************************************************/
+static telnet_data_t telnet_data;
+static const char* telnet_welcome_msg = "Micro Python " MICROPY_GIT_TAG " on " MICROPY_BUILD_DATE "; " MICROPY_HW_BOARD_NAME " with " MICROPY_HW_MCU_NAME "\r\n";
+static const char* telnet_request_user = "Login as:";
+static const char* telnet_request_password = "Password:";
+static const char* telnet_invalid_loggin = "\r\nInvalid credentials, try again\r\n";
+static char telnet_loggin_success[] = "\r\nLogin succeeded!\r\nType \"help()\" for more information.\r\n";
+static const uint8_t telnet_options_user[] = // IAC WONT ECHO IAC WONT SUPPRESS_GO_AHEAD IAC WILL LINEMODE
+ { 255, 252, 1, 255, 252, 3, 255, 251, 34 };
+static const uint8_t telnet_options_pass[] = // IAC WILL ECHO IAC WONT SUPPRESS_GO_AHEAD IAC WILL LINEMODE
+ { 255, 251, 1, 255, 252, 3, 255, 251, 34 };
+static const uint8_t telnet_options_repl[] = // IAC WILL ECHO IAC WILL SUPPRESS_GO_AHEAD IAC WONT LINEMODE
+ { 255, 251, 1, 255, 251, 3, 255, 252, 34 };
+
+/******************************************************************************
+ DECLARE PRIVATE FUNCTIONS
+ ******************************************************************************/
+static void telnet_wait_for_enabled (void);
+static bool telnet_create_socket (void);
+static void telnet_wait_for_connection (void);
+static void telnet_send_and_proceed (void *data, _i16 Len, telnet_connected_substate_t next_state);
+static telnet_result_t telnet_send_non_blocking (void *data, _i16 Len);
+static telnet_result_t telnet_recv_text_non_blocking (void *buff, _i16 Maxlen, _i16 *rxLen);
+static void telnet_process (void);
+static void telnet_parse_input (uint8_t *str, int16_t *len);
+static bool telnet_send_with_retries (int16_t sd, const void *pBuf, int16_t len);
+static void telnet_reset (void);
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+void telnet_init (void) {
+ // Allocate memory for the receive buffer (from the RTOS heap)
+ ASSERT ((telnet_data.rxBuffer = mem_Malloc(TELNET_RX_BUFFER_SIZE)) != NULL);
+ telnet_data.state = E_TELNET_STE_DISABLED;
+}
+
+void telnet_run (void) {
+ _i16 rxLen;
+ switch (telnet_data.state) {
+ case E_TELNET_STE_DISABLED:
+ telnet_wait_for_enabled();
+ break;
+ case E_TELNET_STE_START:
+ if (telnet_create_socket()) {
+ telnet_data.state = E_TELNET_STE_LISTEN;
+ }
+ break;
+ case E_TELNET_STE_LISTEN:
+ telnet_wait_for_connection();
+ break;
+ case E_TELNET_STE_CONNECTED:
+ switch (telnet_data.substate.connected) {
+ case E_TELNET_STE_SUB_WELCOME:
+ telnet_send_and_proceed((void *)telnet_welcome_msg, strlen(telnet_welcome_msg), E_TELNET_STE_SUB_SND_USER_OPTIONS);
+ break;
+ case E_TELNET_STE_SUB_SND_USER_OPTIONS:
+ telnet_send_and_proceed((void *)telnet_options_user, sizeof(telnet_options_user), E_TELNET_STE_SUB_REQ_USER);
+ break;
+ case E_TELNET_STE_SUB_REQ_USER:
+ telnet_send_and_proceed((void *)telnet_request_user, strlen(telnet_request_user), E_TELNET_STE_SUB_GET_USER);
+ break;
+ case E_TELNET_STE_SUB_GET_USER:
+ if (E_TELNET_RESULT_OK == telnet_recv_text_non_blocking(telnet_data.rxBuffer, TELNET_RX_BUFFER_SIZE, &rxLen)) {
+ // Skip /r/n
+ if (rxLen < 2 || memcmp(servers_user, (const char *)telnet_data.rxBuffer, MAX((rxLen - 2), strlen(servers_user)))) {
+ telnet_data.credentialsValid = false;
+ }
+ telnet_data.substate.connected = E_TELNET_STE_SUB_SND_PASSWORD_OPTIONS;
+ }
+ break;
+ case E_TELNET_STE_SUB_SND_PASSWORD_OPTIONS:
+ telnet_send_and_proceed((void *)telnet_options_pass, sizeof(telnet_options_pass), E_TELNET_STE_SUB_REQ_PASSWORD);
+ break;
+ case E_TELNET_STE_SUB_REQ_PASSWORD:
+ telnet_send_and_proceed((void *)telnet_request_password, strlen(telnet_request_password), E_TELNET_STE_SUB_GET_PASSWORD);
+ // to catch a possible "/r/n" that was left
+ telnet_recv_text_non_blocking(telnet_data.rxBuffer, TELNET_RX_BUFFER_SIZE, &rxLen);
+ break;
+ case E_TELNET_STE_SUB_GET_PASSWORD:
+ if (E_TELNET_RESULT_OK == telnet_recv_text_non_blocking(telnet_data.rxBuffer, TELNET_RX_BUFFER_SIZE, &rxLen)) {
+ // Skip /r/n
+ if (rxLen < 2 || memcmp(servers_pass, (const char *)telnet_data.rxBuffer, MAX((rxLen - 2), strlen(servers_pass)))) {
+ telnet_data.credentialsValid = false;
+ }
+ if (telnet_data.credentialsValid) {
+ telnet_data.substate.connected = E_TELNET_STE_SUB_SND_REPL_OPTIONS;
+ }
+ else {
+ telnet_data.substate.connected = E_TELNET_STE_SUB_INVALID_LOGGIN;
+ }
+ }
+ break;
+ case E_TELNET_STE_SUB_INVALID_LOGGIN:
+ if (E_TELNET_RESULT_OK == telnet_send_non_blocking((void *)telnet_invalid_loggin, strlen(telnet_invalid_loggin))) {
+ telnet_data.credentialsValid = true;
+ if (++telnet_data.logginRetries >= TELNET_LOGIN_RETRIES_MAX) {
+ telnet_reset();
+ }
+ else {
+ telnet_data.substate.connected = E_TELNET_STE_SUB_SND_USER_OPTIONS;
+ }
+ }
+ break;
+ case E_TELNET_STE_SUB_SND_REPL_OPTIONS:
+ telnet_send_and_proceed((void *)telnet_options_repl, sizeof(telnet_options_repl), E_TELNET_STE_SUB_LOGGIN_SUCCESS);
+ break;
+ case E_TELNET_STE_SUB_LOGGIN_SUCCESS:
+ if (E_TELNET_RESULT_OK == telnet_send_non_blocking((void *)telnet_loggin_success, strlen(telnet_loggin_success))) {
+ // fake "enter" key pressed to display the prompt
+ telnet_data.rxBuffer[telnet_data.rxWindex++] = '\r';
+ telnet_data.state= E_TELNET_STE_LOGGED_IN;
+ }
+ default:
+ break;
+ }
+ break;
+ case E_TELNET_STE_LOGGED_IN:
+ telnet_process();
+ break;
+ default:
+ break;
+ }
+
+ if (telnet_data.state >= E_TELNET_STE_CONNECTED) {
+ if (telnet_data.timeout++ > (TELNET_TIMEOUT_MS / TELNET_CYCLE_TIME_MS)) {
+ telnet_reset();
+ }
+ }
+}
+
+void telnet_tx_strn (const char *str, int len) {
+ if (len > 0 && telnet_data.n_sd > 0) {
+ telnet_send_with_retries(telnet_data.n_sd, str, len);
+ }
+}
+
+void telnet_tx_strn_cooked (const char *str, uint len) {
+ int32_t nslen = 0;
+ const char *_str = str;
+
+ for (int i = 0; i < len; i++) {
+ if (str[i] == '\n') {
+ telnet_send_with_retries(telnet_data.n_sd, _str, nslen);
+ telnet_send_with_retries(telnet_data.n_sd, "\r\n", 2);
+ _str += nslen + 1;
+ nslen = 0;
+ }
+ else {
+ nslen++;
+ }
+ }
+ if (_str < str + len) {
+ telnet_send_with_retries(telnet_data.n_sd, _str, nslen);
+ }
+}
+
+bool telnet_rx_any (void) {
+ return (telnet_data.n_sd > 0) ? ((telnet_data.rxRindex < telnet_data.rxWindex) &&
+ (telnet_data.state == E_TELNET_STE_LOGGED_IN)) : false;
+}
+
+int telnet_rx_char (void) {
+ int rx_char = -1;
+ if (telnet_data.rxRindex < telnet_data.rxWindex) {
+ rx_char = (int)telnet_data.rxBuffer[telnet_data.rxRindex++];
+ }
+ return rx_char;
+}
+
+void telnet_enable (void) {
+ telnet_data.enabled = true;
+}
+
+void telnet_disable (void) {
+ telnet_reset();
+ telnet_data.enabled = false;
+ telnet_data.state = E_TELNET_STE_DISABLED;
+}
+
+bool telnet_is_enabled (void) {
+ return telnet_data.enabled;
+}
+
+bool telnet_is_active (void) {
+ return (telnet_data.state == E_TELNET_STE_LOGGED_IN);
+}
+
+/******************************************************************************
+ DEFINE PRIVATE FUNCTIONS
+ ******************************************************************************/
+static void telnet_wait_for_enabled (void) {
+ // Init telnet's data
+ telnet_data.n_sd = -1;
+ telnet_data.sd = -1;
+
+ // Check if the telnet service has been enabled
+ if (telnet_data.enabled) {
+ telnet_data.state = E_TELNET_STE_START;
+ }
+}
+
+static bool telnet_create_socket (void) {
+ SlSockNonblocking_t nonBlockingOption;
+ sockaddr_in sServerAddress;
+ _i16 result;
+
+ // Open a socket for telnet
+ ASSERT ((telnet_data.sd = sl_Socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) > 0);
+ if (telnet_data.sd > 0) {
+ // Enable non-blocking mode
+ nonBlockingOption.NonblockingEnabled = 1;
+ ASSERT (sl_SetSockOpt(telnet_data.sd, SOL_SOCKET, SL_SO_NONBLOCKING, &nonBlockingOption, sizeof(nonBlockingOption)) == SL_SOC_OK);
+
+ // Bind the socket to a port number
+ sServerAddress.sin_family = AF_INET;
+ sServerAddress.sin_addr.s_addr = htonl(INADDR_ANY);
+ sServerAddress.sin_port = htons(TELNET_PORT);
+
+ ASSERT (sl_Bind(telnet_data.sd, (const SlSockAddr_t *)&sServerAddress, sizeof(sServerAddress)) == SL_SOC_OK);
+
+ // Start listening
+ ASSERT ((result = sl_Listen (telnet_data.sd, TELNET_MAX_CLIENTS)) == SL_SOC_OK);
+
+ return (result == SL_SOC_OK) ? true : false;
+ }
+
+ return false;
+}
+
+static void telnet_wait_for_connection (void) {
+ SlSocklen_t in_addrSize;
+ sockaddr_in sClientAddress;
+
+ // accepts a connection from a TCP client, if there is any, otherwise returns SL_EAGAIN
+ telnet_data.n_sd = sl_Accept(telnet_data.sd, (SlSockAddr_t *)&sClientAddress, (SlSocklen_t *)&in_addrSize);
+ if (telnet_data.n_sd == SL_EAGAIN) {
+ return;
+ }
+ else {
+ // close the listening socket, we don't need it anymore
+ sl_Close(telnet_data.sd);
+
+ if (telnet_data.n_sd <= 0) {
+ // error
+ telnet_reset();
+ return;
+ }
+
+ // client connected, so go on
+ telnet_data.rxWindex = 0;
+ telnet_data.rxRindex = 0;
+ telnet_data.txRetries = 0;
+
+ telnet_data.state = E_TELNET_STE_CONNECTED;
+ telnet_data.substate.connected = E_TELNET_STE_SUB_WELCOME;
+ telnet_data.credentialsValid = true;
+ telnet_data.logginRetries = 0;
+ telnet_data.timeout = 0;
+ }
+}
+
+static void telnet_send_and_proceed (void *data, _i16 Len, telnet_connected_substate_t next_state) {
+ if (E_TELNET_RESULT_OK == telnet_send_non_blocking(data, Len)) {
+ telnet_data.substate.connected = next_state;
+ }
+}
+
+static telnet_result_t telnet_send_non_blocking (void *data, _i16 Len) {
+ int16_t result = sl_Send(telnet_data.n_sd, data, Len, 0);
+
+ if (result > 0) {
+ telnet_data.txRetries = 0;
+ return E_TELNET_RESULT_OK;
+ }
+ else if ((TELNET_TX_RETRIES_MAX >= ++telnet_data.txRetries) && (result == SL_EAGAIN)) {
+ return E_TELNET_RESULT_AGAIN;
+ }
+ else {
+ // error
+ telnet_reset();
+ return E_TELNET_RESULT_FAILED;
+ }
+}
+
+static telnet_result_t telnet_recv_text_non_blocking (void *buff, _i16 Maxlen, _i16 *rxLen) {
+ *rxLen = sl_Recv(telnet_data.n_sd, buff, Maxlen, 0);
+
+ // if there's data received, parse it
+ if (*rxLen > 0) {
+ telnet_data.timeout = 0;
+ telnet_parse_input (buff, rxLen);
+ if (*rxLen > 0) {
+ return E_TELNET_RESULT_OK;
+ }
+ }
+ else if (*rxLen != SL_EAGAIN) {
+ // error
+ telnet_reset();
+ return E_TELNET_RESULT_FAILED;
+ }
+ return E_TELNET_RESULT_AGAIN;
+}
+
+static void telnet_process (void) {
+ if (!telnet_rx_any()) {
+ telnet_data.rxWindex = 0;
+ telnet_data.rxRindex = 0;
+ }
+
+ if (telnet_data.rxWindex < TELNET_RX_BUFFER_SIZE) {
+ _i16 rxLen;
+ if (E_TELNET_RESULT_OK == telnet_recv_text_non_blocking(&telnet_data.rxBuffer[telnet_data.rxWindex],
+ TELNET_RX_BUFFER_SIZE - telnet_data.rxWindex, &rxLen)) {
+ telnet_data.rxWindex += rxLen;
+ }
+ }
+}
+
+static void telnet_parse_input (uint8_t *str, int16_t *len) {
+ int16_t b_len = *len;
+ uint8_t *b_str = str;
+
+ for (uint8_t *_str = b_str; _str < b_str + b_len; ) {
+ if (*_str <= 127) {
+ if (telnet_data.state == E_TELNET_STE_LOGGED_IN && *_str == user_interrupt_char) {
+ // raise keyboard exception
+ mpexception_keyboard_nlr_jump();
+ (*len)--;
+ _str++;
+ }
+ else {
+ *str++ = *_str++;
+ }
+ }
+ else {
+ _str += 3;
+ *len -= 3;
+ }
+ }
+}
+
+static bool telnet_send_with_retries (int16_t sd, const void *pBuf, int16_t len) {
+ int32_t retries = 0;
+
+#ifdef USE_FREERTOS
+ // abort sending if we happen to be within interrupt context
+ if ((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0) {
+#endif
+ do {
+ _i16 result = sl_Send(sd, pBuf, len, 0);
+ if (result > 0) {
+ return true;
+ }
+ else if (SL_EAGAIN != result) {
+ return false;
+ }
+ HAL_Delay (TELNET_WAIT_TIME_MS);
+ } while (++retries <= TELNET_TX_RETRIES_MAX);
+#ifdef USE_FREERTOS
+ } else {
+ // TODO: blink the BLD
+ }
+#endif
+
+ return false;
+}
+
+static void telnet_reset (void) {
+ // close the connection and start all over again
+ servers_close_socket(&telnet_data.n_sd);
+ servers_close_socket(&telnet_data.sd);
+ telnet_data.state = E_TELNET_STE_START;
+}
diff --git a/cc3200/telnet/telnet.h b/cc3200/telnet/telnet.h
new file mode 100644
index 0000000000..913cd73e15
--- /dev/null
+++ b/cc3200/telnet/telnet.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TELNET_H_
+#define TELNET_H_
+
+/******************************************************************************
+ DECLARE EXPORTED FUNCTIONS
+ ******************************************************************************/
+extern void telnet_init (void);
+extern void telnet_run (void);
+extern void telnet_tx_strn (const char *str, int len);
+extern void telnet_tx_strn_cooked (const char *str, uint len);
+extern bool telnet_rx_any (void);
+extern int telnet_rx_char (void);
+extern void telnet_enable (void);
+extern void telnet_disable (void);
+extern bool telnet_is_enabled (void);
+extern bool telnet_is_active (void);
+
+#endif /* TELNET_H_ */
diff --git a/cc3200/util/fifo.c b/cc3200/util/fifo.c
new file mode 100644
index 0000000000..73b2b7161c
--- /dev/null
+++ b/cc3200/util/fifo.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "std.h"
+#include "fifo.h"
+
+
+/******************************************************************************
+ DEFINE PUBLIC FUNCTIONS
+ ******************************************************************************/
+void FIFO_Init (FIFO_t *fifo, unsigned int uiElementsMax,
+ void (*pfElmentPush)(void * const pvFifo, const void * const pvElement),
+ void (*pfElementPop)(void * const pvFifo, void * const pvElement)) {
+ if (fifo) {
+ fifo->uiFirst = 0;
+ fifo->uiLast = uiElementsMax - 1;
+ fifo->uiElementCount = 0;
+ fifo->uiElementsMax = uiElementsMax;
+ fifo->pfElementPush = pfElmentPush;
+ fifo->pfElementPop = pfElementPop;
+ }
+}
+
+bool FIFO_bPushElement (FIFO_t *fifo, const void * const pvElement) {
+ if (!fifo) {
+ return false;
+ }
+ // Check if the queue is full
+ if (true == FIFO_IsFull (fifo)) {
+ return false;
+ }
+
+ // Increment the element count
+ if (fifo->uiElementsMax > fifo->uiElementCount) {
+ fifo->uiElementCount++;
+ }
+ fifo->uiLast++;
+ if (fifo->uiLast == fifo->uiElementsMax) {
+ fifo->uiLast = 0;
+ }
+ // Insert the element into the queue
+ fifo->pfElementPush(fifo, pvElement);
+ return true;
+}
+
+bool FIFO_bPopElement (FIFO_t *fifo, void * const pvElement) {
+ if (!fifo) {
+ return false;
+ }
+ // Check if the queue is empty
+ if (true == FIFO_IsEmpty (fifo)) {
+ return false;
+ }
+
+ // Get the element from the queue
+ fifo->pfElementPop(fifo, pvElement);
+ // Decrement the element count
+ if (fifo->uiElementCount > 0) {
+ fifo->uiElementCount--;
+ }
+ fifo->uiFirst++;
+ if (fifo->uiFirst == fifo->uiElementsMax) {
+ fifo->uiFirst = 0;
+ }
+ return true;
+}
+
+bool FIFO_bPeekElement (FIFO_t *fifo, void * const pvElement) {
+ if (!fifo) {
+ return false;
+ }
+ // Check if the queue is empty
+ if (true == FIFO_IsEmpty (fifo)) {
+ return false;
+ }
+ // Get the element from the queue
+ fifo->pfElementPop(fifo, pvElement);
+ return true;
+}
+
+bool FIFO_IsEmpty (FIFO_t *fifo) {
+ if (fifo) {
+ return ((fifo->uiElementCount == 0) ? true : false);
+ }
+ return false;
+}
+
+bool FIFO_IsFull (FIFO_t *fifo) {
+ if (fifo) {
+ return ((fifo->uiElementCount < fifo->uiElementsMax) ? false : true);
+ }
+ return false;
+}
+
+void FIFO_Flush (FIFO_t *fifo) {
+ if (fifo) {
+ fifo->uiElementCount = 0;
+ fifo->uiFirst = 0;
+ fifo->uiLast = fifo->uiElementsMax - 1;
+ }
+}
diff --git a/cc3200/util/fifo.h b/cc3200/util/fifo.h
new file mode 100644
index 0000000000..c8590f5c2c
--- /dev/null
+++ b/cc3200/util/fifo.h
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef FIFO_H_
+#define FIFO_H_
+
+typedef struct {
+ void *pvElements;
+ unsigned int uiElementCount;
+ unsigned int uiElementsMax;
+ unsigned int uiFirst;
+ unsigned int uiLast;
+ void (*pfElementPush)(void * const pvFifo, const void * const pvElement);
+ void (*pfElementPop)(void * const pvFifo, void * const pvElement);
+}FIFO_t;
+
+extern void FIFO_Init (FIFO_t *fifo, unsigned int uiElementsMax,
+void (*pfElmentPush)(void * const pvFifo, const void * const pvElement),
+void (*pfElementPop)(void * const pvFifo, void * const pvElement));
+extern bool FIFO_bPushElement (FIFO_t *fifo, const void * const pvElement);
+extern bool FIFO_bPopElement (FIFO_t *fifo, void * const pvElement);
+extern bool FIFO_bPeekElement (FIFO_t *fifo, void * const pvElement);
+extern bool FIFO_IsEmpty (FIFO_t *fifo);
+extern bool FIFO_IsFull (FIFO_t *fifo);
+extern void FIFO_Flush (FIFO_t *fifo);
+
+#endif /* FIFO_H_ */
diff --git a/cc3200/util/gccollect.c b/cc3200/util/gccollect.c
new file mode 100644
index 0000000000..9ab19d63dd
--- /dev/null
+++ b/cc3200/util/gccollect.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "mpconfig.h"
+#include "misc.h"
+#include "qstr.h"
+#include "obj.h"
+#include "gc.h"
+#include "gccollect.h"
+#include "gchelper.h"
+#include MICROPY_HAL_H
+
+/******************************************************************************
+DECLARE PRIVATE DATA
+ ******************************************************************************/
+static uint32_t stackend;
+
+
+/******************************************************************************
+DECLARE PUBLIC FUNCTIONS
+ ******************************************************************************/
+void gc_collect_init (uint32_t sp) {
+ stackend = sp;
+}
+
+void gc_collect(void) {
+ // start the GC
+ gc_collect_start();
+
+ // get the registers and the sp
+ mp_uint_t regs[10];
+ mp_uint_t sp = gc_helper_get_regs_and_sp(regs);
+
+ // trace the stack, including the registers (since they live on the stack in this function)
+ gc_collect_root((void**)sp, (stackend - sp) / sizeof(uint32_t));
+
+ // end the GC
+ gc_collect_end();
+}
diff --git a/cc3200/util/gccollect.h b/cc3200/util/gccollect.h
new file mode 100644
index 0000000000..8e4c8896bf
--- /dev/null
+++ b/cc3200/util/gccollect.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+// variables defining memory layout
+extern uint32_t _etext;
+extern uint32_t _sidata;
+extern uint32_t _data;
+extern uint32_t _edata;
+extern uint32_t _bss;
+extern uint32_t _ebss;
+extern uint32_t _heap;
+extern uint32_t _eheap;
+extern uint32_t _stack;
+extern uint32_t _estack;
+
+void gc_collect_init (uint32_t sp);
+void gc_collect(void);
diff --git a/cc3200/util/gchelper.h b/cc3200/util/gchelper.h
new file mode 100644
index 0000000000..1f7d2fece4
--- /dev/null
+++ b/cc3200/util/gchelper.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef GC_HELPER_H_
+#define GC_HELPER_H_
+
+extern mp_uint_t gc_helper_get_sp(void);
+extern mp_uint_t gc_helper_get_regs_and_sp(mp_uint_t *regs);
+
+#endif /* GC_HELPER_H_ */
diff --git a/cc3200/util/gchelper.s b/cc3200/util/gchelper.s
new file mode 100644
index 0000000000..aa8fb499e9
--- /dev/null
+++ b/cc3200/util/gchelper.s
@@ -0,0 +1,41 @@
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+ .text
+ .align 2
+
+
+
+@ uint gc_helper_get_sp(void)
+ .global gc_helper_get_sp
+ .thumb
+ .thumb_func
+ .type gc_helper_get_sp, %function
+gc_helper_get_sp:
+ @ return the sp
+ mov r0, sp
+ bx lr
+
+
+
+@ uint gc_helper_get_regs_and_sp(r0=uint regs[10])
+ .global gc_helper_get_regs_and_sp
+ .thumb
+ .thumb_func
+ .type gc_helper_get_regs_and_sp, %function
+gc_helper_get_regs_and_sp:
+ @ store registers into given array
+ str r4, [r0], #4
+ str r5, [r0], #4
+ str r6, [r0], #4
+ str r7, [r0], #4
+ str r8, [r0], #4
+ str r9, [r0], #4
+ str r10, [r0], #4
+ str r11, [r0], #4
+ str r12, [r0], #4
+ str r13, [r0], #4
+
+ @ return the sp
+ mov r0, sp
+ bx lr
diff --git a/cc3200/util/hash.c b/cc3200/util/hash.c
new file mode 100644
index 0000000000..a7afdf9f2f
--- /dev/null
+++ b/cc3200/util/hash.c
@@ -0,0 +1,72 @@
+#include "std.h"
+#include
+#include
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_nvic.h"
+#include "inc/hw_shamd5.h"
+#include "inc/hw_dthe.h"
+#include "hw_memmap.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "shamd5.h"
+#include "hash.h"
+
+#ifdef USE_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+#endif
+
+
+#ifdef USE_FREERTOS
+static SemaphoreHandle_t xShamd5Semaphore = NULL;
+#endif
+
+void HASH_Init (void) {
+ // Enable the Data Hashing and Transform Engine
+ MAP_PRCMPeripheralClkEnable(PRCM_DTHE, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
+#ifdef USE_FREERTOS
+ vSemaphoreCreateBinary(xShamd5Semaphore);
+#endif
+}
+
+
+
+void HASH_SHAMD5Start (uint32_t algo, uint32_t blocklen) {
+
+#ifdef USE_FREERTOS
+ xSemaphoreTake (xShamd5Semaphore, portMAX_DELAY);
+#endif
+
+ MAP_PRCMPeripheralReset(PRCM_DTHE);
+
+ // wait until the context is ready
+ while ((HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_CONTEXT_READY) == 0);
+
+ // Configure the SHA/MD5 module algorithm
+ MAP_SHAMD5ConfigSet(SHAMD5_BASE, algo);
+
+ // if not a multiple of 64 bytes, close the hash
+ if (blocklen % 64) {
+ HWREG(SHAMD5_BASE + SHAMD5_O_MODE) |= SHAMD5_MODE_CLOSE_HASH;
+ }
+
+ // set the lenght
+ HWREG(SHAMD5_BASE + SHAMD5_O_LENGTH) = blocklen;
+}
+
+void HASH_SHAMD5Update (uint8_t *data, uint32_t datalen) {
+ // write the data
+ SHAMD5DataWriteMultiple(data, datalen);
+}
+
+void HASH_SHAMD5Read (uint8_t *hash) {
+ // wait for the output to be ready.
+ while((HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == 0);
+ // read the result.
+ MAP_SHAMD5ResultRead(SHAMD5_BASE, hash);
+#ifdef USE_FREERTOS
+ xSemaphoreGive (xShamd5Semaphore);
+#endif
+}
diff --git a/cc3200/util/hash.h b/cc3200/util/hash.h
new file mode 100644
index 0000000000..d131584611
--- /dev/null
+++ b/cc3200/util/hash.h
@@ -0,0 +1,10 @@
+#ifndef HASH_H_
+#define HASH_H_
+
+extern void HASH_Init (void);
+extern void HASH_SHAMD5Start (uint32_t algo, uint32_t blocklen);
+extern void HASH_SHAMD5Update (uint8_t *data, uint32_t datalen);
+extern void HASH_SHAMD5Read (uint8_t *hash);
+
+
+#endif /* HASH_H_ */
diff --git a/cc3200/util/random.c b/cc3200/util/random.c
new file mode 100644
index 0000000000..be6400def5
--- /dev/null
+++ b/cc3200/util/random.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "rom_map.h"
+#include "prcm.h"
+#include "simplelink.h"
+#include "modwlan.h"
+#include "py/obj.h"
+#include "random.h"
+
+
+/******************************************************************************
+* LOCAL TYPES
+******************************************************************************/
+typedef union Id_t {
+ uint32_t id32;
+ uint16_t id16[3];
+ uint8_t id8[6];
+} Id_t;
+
+/******************************************************************************
+* LOCAL VARIABLES
+******************************************************************************/
+static uint32_t s_seed;
+
+/******************************************************************************
+* LOCAL FUNCTION DECLARATIONS
+******************************************************************************/
+static uint32_t lfsr (uint32_t input);
+
+/******************************************************************************
+* PRIVATE FUNCTIONS
+******************************************************************************/
+static uint32_t lfsr (uint32_t input) {
+ assert( input != 0 );
+
+ /*lint -save -e501*/
+ return (input >> 1) ^ (-(input & 0x01) & 0x00E10000);
+ /*lint -restore*/
+}
+
+#if MICROPY_HW_ENABLE_RNG
+/// \moduleref rng
+
+/// \function rng()
+/// Return a 24-bit hardware generated random number.
+STATIC mp_obj_t pyb_rng_get(void) {
+ return mp_obj_new_int(rng_get());
+}
+
+MP_DEFINE_CONST_FUN_OBJ_0(pyb_rng_get_obj, pyb_rng_get);
+#endif
+
+/******************************************************************************
+* PUBLIC FUNCTIONS
+******************************************************************************/
+void rng_init0 (void) {
+ Id_t juggler;
+ uint32_t seconds;
+ uint16_t mseconds;
+
+ // get the seconds and the milliseconds from the RTC
+ MAP_PRCMRTCGet(&seconds, &mseconds);
+
+ wlan_get_mac (juggler.id8);
+
+ // Flatten the 48-bit board identification to 24 bits
+ juggler.id16[0] ^= juggler.id16[2];
+
+ juggler.id8[0] ^= juggler.id8[3];
+ juggler.id8[1] ^= juggler.id8[4];
+ juggler.id8[2] ^= juggler.id8[5];
+
+ s_seed = juggler.id32 & 0x00FFFFFF;
+ s_seed += (seconds & 0x000FFFFF) + mseconds;
+ // The seed must not be zero
+ if (s_seed == 0) {
+ s_seed = 1;
+ }
+}
+
+uint32_t rng_get (void) {
+ s_seed = lfsr( s_seed );
+ return s_seed;
+}
diff --git a/cc3200/util/random.h b/cc3200/util/random.h
new file mode 100644
index 0000000000..78ca578936
--- /dev/null
+++ b/cc3200/util/random.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef __RANDOM_H
+#define __RANDOM_H
+
+void rng_init0 (void);
+uint32_t rng_get (void);
+
+#if MICROPY_HW_ENABLE_RNG
+ MP_DECLARE_CONST_FUN_OBJ(pyb_rng_get_obj);
+#endif
+
+#endif // __RANDOM_H
diff --git a/cc3200/util/socketfifo.c b/cc3200/util/socketfifo.c
new file mode 100644
index 0000000000..cfe92a82b6
--- /dev/null
+++ b/cc3200/util/socketfifo.c
@@ -0,0 +1,107 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+
+#include
+#include "osi.h"
+#include "fifo.h"
+#include "socketfifo.h"
+
+
+/*----------------------------------------------------------------------------
+ ** Declare private functions
+ */
+static void socketfifo_Push (void * const pvFifo, const void * const pvElement);
+static void socketfifo_Pop (void * const pvFifo, void * const pvElement);
+
+/*----------------------------------------------------------------------------
+ ** Declare private data
+ */
+static FIFO_t *socketfifo;
+
+/*----------------------------------------------------------------------------
+ ** Define public functions
+ */
+void SOCKETFIFO_Init (FIFO_t *fifo, void *elements, uint32_t maxcount) {
+ // Initialize global data
+ socketfifo = fifo;
+ socketfifo->pvElements = elements;
+ FIFO_Init (socketfifo, maxcount, socketfifo_Push, socketfifo_Pop);
+}
+
+bool SOCKETFIFO_Push (const void * const element) {
+ return FIFO_bPushElement (socketfifo, element);
+}
+
+bool SOCKETFIFO_Pop (void * const element) {
+ return FIFO_bPopElement (socketfifo, element);
+}
+
+bool SOCKETFIFO_Peek (void * const element) {
+ return FIFO_bPeekElement (socketfifo, element);
+}
+
+bool SOCKETFIFO_IsEmpty (void) {
+ return FIFO_IsEmpty (socketfifo);
+}
+
+bool SOCKETFIFO_IsFull (void) {
+ return FIFO_IsFull (socketfifo);
+}
+
+void SOCKETFIFO_Flush (void) {
+ SocketFifoElement_t element;
+ while (SOCKETFIFO_Pop(&element)) {
+ if (element.freedata) {
+ mem_Free(element.data);
+ }
+ }
+}
+
+unsigned int SOCKETFIFO_Count (void) {
+ return socketfifo->uiElementCount;
+}
+
+/*----------------------------------------------------------------------------
+ ** Define private functions
+ */
+static void socketfifo_Push (void * const pvFifo, const void * const pvElement) {
+ if ((pvFifo != NULL) && (NULL != pvElement)) {
+ unsigned int uiLast = ((FIFO_t *)pvFifo)->uiLast;
+ memcpy (&((SocketFifoElement_t *)((FIFO_t *)pvFifo)->pvElements)[uiLast], pvElement, sizeof(SocketFifoElement_t));
+ }
+}
+
+static void socketfifo_Pop (void * const pvFifo, void * const pvElement) {
+ if ((pvFifo != NULL) && (NULL != pvElement)) {
+ unsigned int uiFirst = ((FIFO_t *)pvFifo)->uiFirst;
+ memcpy (pvElement, &((SocketFifoElement_t *)((FIFO_t *)pvFifo)->pvElements)[uiFirst], sizeof(SocketFifoElement_t));
+ }
+}
+
diff --git a/cc3200/util/socketfifo.h b/cc3200/util/socketfifo.h
new file mode 100644
index 0000000000..69b17658ff
--- /dev/null
+++ b/cc3200/util/socketfifo.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2015 Daniel Campora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef SOCKETFIFO_H_
+#define SOCKETFIFO_H_
+
+/*----------------------------------------------------------------------------
+ ** Imports
+ */
+
+/*----------------------------------------------------------------------------
+ ** Define constants
+ */
+
+/*----------------------------------------------------------------------------
+ ** Define types
+ */
+
+typedef struct {
+ void *data;
+ signed short *sd;
+ unsigned short datasize;
+ unsigned char closesockets;
+ bool freedata;
+
+}SocketFifoElement_t;
+
+/*----------------------------------------------------------------------------
+ ** Declare public functions
+ */
+extern void SOCKETFIFO_Init (FIFO_t *fifo, void *elements, uint32_t maxcount);
+extern bool SOCKETFIFO_Push (const void * const element);
+extern bool SOCKETFIFO_Pop (void * const element);
+extern bool SOCKETFIFO_Peek (void * const element);
+extern bool SOCKETFIFO_IsEmpty (void);
+extern bool SOCKETFIFO_IsFull (void);
+extern void SOCKETFIFO_Flush (void);
+extern unsigned int SOCKETFIFO_Count (void);
+
+#endif /* SOCKETFIFO_H_ */
diff --git a/cc3200/util/std.h b/cc3200/util/std.h
new file mode 100644
index 0000000000..8368432b9f
--- /dev/null
+++ b/cc3200/util/std.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the Micro Python project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2013, 2014 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+typedef unsigned int size_t;
+
+void *memcpy(void *dest, const void *src, size_t n);
+void *memmove(void *dest, const void *src, size_t n);
+void *memset(void *s, int c, size_t n);
+
+size_t strlen(const char *str);
+int strcmp(const char *s1, const char *s2);
+int strncmp(const char *s1, const char *s2, size_t n);
+char *strcpy(char *dest, const char *src);
+char *strcat(char *dest, const char *src);
+char *strchr(const char *s, int c);
+char *strstr(const char *haystack, const char *needle);
+
+int printf(const char *fmt, ...);
+int snprintf(char *str, size_t size, const char *fmt, ...);
+
+void stoupper (char *str);