kopia lustrzana https://github.com/micropython/micropython
mimxrt/mimxrt_sdram: Allow boards to override the default SDRAM config.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>pull/12376/head
iabdalkader
Damien George
rodzic
4b9c459133
commit
805c750164
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@ -42,10 +42,51 @@ extern uint8_t __sdram_start;
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#define SDRAM_PIN_CONFIG (0xE1UL)
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#endif
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void mimxrt_sdram_init(void) {
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#ifndef MICROPY_HW_SDRAM_TIMING_TRC
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#if defined(MIMXRT117x_SERIES)
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#define MICROPY_HW_SDRAM_TIMING_TRC (60)
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#define MICROPY_HW_SDRAM_TIMING_TRP (15)
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#define MICROPY_HW_SDRAM_TIMING_TRCD (15)
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#define MICROPY_HW_SDRAM_TIMING_TWR (2)
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#define MICROPY_HW_SDRAM_TIMING_TRRD (2)
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#define MICROPY_HW_SDRAM_TIMING_TXSR (70)
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#define MICROPY_HW_SDRAM_TIMING_TRAS (42)
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#define MICROPY_HW_SDRAM_TIMING_TREF (64 * 1000000 / 8192) // 64ms/8192
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#if !defined(MIMXRT117x_SERIES)
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#define MICROPY_HW_SDRAM_CAS_LATENCY (kSEMC_LatencyThree)
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#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH (kSEMC_PortSize32Bit)
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#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM (kSEMC_SdramColunm_9bit)
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#define MICROPY_HW_SDRAM_BURST_LENGTH (kSEMC_Sdram_BurstLen8)
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#define MICROPY_HW_SDRAM_RBURST_LENGTH (1)
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#define MICROPY_HW_SDRAM_DELAY_CHAIN (2)
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#else
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#define MICROPY_HW_SDRAM_TIMING_TRC (60)
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#define MICROPY_HW_SDRAM_TIMING_TRP (18)
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#define MICROPY_HW_SDRAM_TIMING_TRCD (18)
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#define MICROPY_HW_SDRAM_TIMING_TWR (12)
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#define MICROPY_HW_SDRAM_TIMING_TRRD (60)
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#define MICROPY_HW_SDRAM_TIMING_TXSR (67)
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#define MICROPY_HW_SDRAM_TIMING_TRAS (42)
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#define MICROPY_HW_SDRAM_TIMING_TREF (64 * 1000000 / 8192) // 64ms/8192
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#define MICROPY_HW_SDRAM_CAS_LATENCY (kSEMC_LatencyThree)
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#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH (kSEMC_PortSize16Bit)
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#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM (kSEMC_SdramColunm_9bit)
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#define MICROPY_HW_SDRAM_BURST_LENGTH (kSEMC_Sdram_BurstLen1)
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#define MICROPY_HW_SDRAM_RBURST_LENGTH (1)
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#endif
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#endif
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void mimxrt_sdram_init(void) {
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// Set Clocks
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#if defined(MIMXRT117x_SERIES)
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CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 29);
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clock_root_config_t rootCfg = { 0 };
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rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
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rootCfg.div = 2;
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CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
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#else
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 29); // '29' PLL2 PFD2 frequency = 528MHz * 18 / 29 = 327.72MHz (with 528MHz = PLL2 frequency)
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CLOCK_SetMux(kCLOCK_SemcAltMux, 0); // '0' PLL2 PFD2 will be selected as alternative clock for SEMC root clock
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CLOCK_SetMux(kCLOCK_SemcMux, 1); // '1' SEMC alternative clock will be used as SEMC clock root
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@ -137,7 +178,7 @@ void mimxrt_sdram_init(void) {
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DQS, 1UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DQS, SDRAM_PIN_CONFIG);
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#if defined(MIMXRT117x_SERIES)
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#if defined(MIMXRT_IOMUXC_SEMC_DATA16)
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// Data Pins 16..31
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IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA16, 0UL);
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IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA16, SDRAM_PIN_CONFIG);
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@ -209,62 +250,38 @@ void mimxrt_sdram_init(void) {
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SEMC_Init(SEMC, &semc_cfg);
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#if defined(MIMXRT117x_SERIES)
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uint32_t clock_freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Semc);
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semc_sdram_config_t sdram_cfg = {
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.csxPinMux = kSEMC_MUXCSX0,
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.address = 0x80000000,
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.memsize_kbytes = (MICROPY_HW_SDRAM_SIZE >> 10),
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.portSize = kSEMC_PortSize32Bit, // two 16-bit SDRAMs make up 32-bit portsize
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.burstLen = kSEMC_Sdram_BurstLen8,
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.columnAddrBitNum = kSEMC_SdramColunm_9bit,
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.casLatency = kSEMC_LatencyThree,
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.tPrecharge2Act_Ns = 15, // tRP 15ns
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.tAct2ReadWrite_Ns = 15, // tRCD 15ns
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.tRefreshRecovery_Ns = 70, // Use the maximum of the (Trfc , Txsr).
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.tWriteRecovery_Ns = 2, // tWR 2ns
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.tCkeOff_Ns = 42, // The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.
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.tAct2Prechage_Ns = 40, // tRAS 40ns
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.tSelfRefRecovery_Ns = 70,
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.tRefresh2Refresh_Ns = 60,
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.tAct2Act_Ns = 2, // tRC/tRDD 2ns
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.tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq),
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.refreshPeriod_nsPerRow = 64 * 1000000 / 8192, // 64ms/8192
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.refreshUrgThreshold = sdram_cfg.refreshPeriod_nsPerRow,
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.refreshBurstLen = 1,
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.delayChain = 2,
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};
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#else
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uint32_t clock_freq = CLOCK_GetFreq(kCLOCK_SemcClk);
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#endif
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semc_sdram_config_t sdram_cfg = {
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.csxPinMux = kSEMC_MUXCSX0,
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.address = ((uint32_t)&__sdram_start),
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.memsize_kbytes = (MICROPY_HW_SDRAM_SIZE >> 10), // Right shift by 10 == division by 1024
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.portSize = kSEMC_PortSize16Bit,
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.burstLen = kSEMC_Sdram_BurstLen1,
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.columnAddrBitNum = kSEMC_SdramColunm_9bit,
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.casLatency = kSEMC_LatencyThree,
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.tPrecharge2Act_Ns = 18, // Trp 18ns
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.tAct2ReadWrite_Ns = 18, // Trcd 18ns
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.tRefreshRecovery_Ns = (60 + 67),
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.tWriteRecovery_Ns = 12, // 12ns
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.tCkeOff_Ns = 42, // The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.
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.tAct2Prechage_Ns = 42, // Tras 42ns
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.tSelfRefRecovery_Ns = 67,
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.tRefresh2Refresh_Ns = 60,
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.tAct2Act_Ns = 60,
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.tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq),
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.portSize = MICROPY_HW_SDRAM_MEM_BUS_WIDTH,
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.burstLen = MICROPY_HW_SDRAM_BURST_LENGTH,
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.columnAddrBitNum = MICROPY_HW_SDRAM_COLUMN_BITS_NUM,
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.casLatency = MICROPY_HW_SDRAM_CAS_LATENCY,
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.tPrecharge2Act_Ns = MICROPY_HW_SDRAM_TIMING_TRP,
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.tAct2ReadWrite_Ns = MICROPY_HW_SDRAM_TIMING_TRCD,
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.tRefreshRecovery_Ns = MICROPY_HW_SDRAM_TIMING_TXSR,
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.tSelfRefRecovery_Ns = MICROPY_HW_SDRAM_TIMING_TXSR,
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.tWriteRecovery_Ns = MICROPY_HW_SDRAM_TIMING_TWR,
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.tCkeOff_Ns = MICROPY_HW_SDRAM_TIMING_TRAS,
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.tAct2Prechage_Ns = MICROPY_HW_SDRAM_TIMING_TRAS,
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.tRefresh2Refresh_Ns = MICROPY_HW_SDRAM_TIMING_TRC,
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.tAct2Act_Ns = MICROPY_HW_SDRAM_TIMING_TRRD,
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.tIdleTimeout_Ns = 0UL,
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.refreshPeriod_nsPerRow = 64 * 1000000 / 8192, // 64ms/8192
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.refreshUrgThreshold = 64 * 1000000 / 8192, // 64ms/8192
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.refreshBurstLen = 1
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.refreshPeriod_nsPerRow = MICROPY_HW_SDRAM_TIMING_TREF,
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.refreshUrgThreshold = MICROPY_HW_SDRAM_TIMING_TREF,
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.refreshBurstLen = MICROPY_HW_SDRAM_RBURST_LENGTH,
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#ifdef MICROPY_HW_SDRAM_DELAY_CHAIN
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.delayChain = MICROPY_HW_SDRAM_DELAY_CHAIN,
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#endif
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.tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq),
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};
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#endif
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(status_t)SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdram_cfg, clock_freq);
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}
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