renesas-ra/boards/ARDUINO_PORTENTA_C33: Add support for Portenta C33.

Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
2023-07-06 16:45:07 +02:00 · 2023-07-06 16:45:07 +02:00 · 7802eed14b
commit 7802eed14b
--- a/ports/renesas-ra/README.md
+++ b/ports/renesas-ra/README.md
@ -40,6 +40,11 @@ Linux, Mac and Windows hosts via https://developer.arm.com/downloads/-/arm-gnu-t
 The compiler can be changed using the `CROSS_COMPILE` variable
 when invoking `make`.

+* Protocol buffer compiler
+Building for the `ARDUINO_PORTENTA_C33` board will build the `esp_hosted` driver, that depends
+on the Protocol Buffer Compiler being installed. On Debian/Ubuntu, this can be installed with
+`sudo apt-get install protobuf-compiler`.
+
 * Obtain submodules
 First the submodules must be obtained using:

--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/board.json
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/board.json
@ -0,0 +1,23 @@
+{
+    "deploy": [
+        "./deploy.md"
+    ],
+    "docs": "",
+    "features": [
+        "512KB SRAM",
+        "2MB Flash",
+        "16MB QSPI Flash",
+        "USB High Speed Phy",
+        "10/100 Ethernet Phy",
+        "ESP32 WiFi/BT Module",
+        "NXP SE050 crypto device"
+    ],
+    "images": [
+        "ABX00074_01.iso_1000x750.jpg"
+    ],
+    "mcu": "RA6M5",
+    "product": "Arduino Portenta C33",
+    "thumbnail": "",
+    "url": "https://store.arduino.cc/pages/portenta-c33",
+    "vendor": "Arduino"
+}
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/board_init.c
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/board_init.c
@ -0,0 +1,53 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Arduino SA
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "py/mphal.h"
+#include "r_sce.h"
+
+// Key code for writing PRCR register.
+#define BSP_PRV_PRCR_KEY            (0xA500U)
+#define BSP_PRV_PRCR_PRC1_UNLOCK    ((BSP_PRV_PRCR_KEY) | 0x2U)
+#define BSP_PRV_PRCR_LOCK               ((BSP_PRV_PRCR_KEY) | 0x0U)
+#define BOOT_DOUBLE_TAP_DATA        (0x07738135)
+#define BOOT_DOUBLE_TAP_ADDR        (*((volatile uint32_t *)&R_SYSTEM->VBTBKR[0]))
+
+void PORTENTA_C33_board_startup() {
+    // Enable USB_BASE
+    R_SYSTEM->PRCR = (uint16_t)BSP_PRV_PRCR_PRC1_UNLOCK;
+    R_MSTP->MSTPCRB &= ~(1U << 11U);
+    R_MSTP->MSTPCRB &= ~(1U << 12U);
+    R_SYSTEM->PRCR = (uint16_t)BSP_PRV_PRCR_LOCK;
+
+    // Re-enable IRQs after jump from the bootloader.
+    __enable_irq();
+}
+
+void PORTENTA_C33_board_enter_bootloader(void) {
+    R_SYSTEM->PRCR = (uint16_t)BSP_PRV_PRCR_PRC1_UNLOCK;
+    BOOT_DOUBLE_TAP_ADDR = BOOT_DOUBLE_TAP_DATA;
+    R_SYSTEM->PRCR = (uint16_t)BSP_PRV_PRCR_LOCK;
+    NVIC_SystemReset();
+}
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/deploy.md
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/deploy.md
@ -0,0 +1,8 @@
+### dfu-util
+
+This board can programmed via DFU bootloader, using e.g. [dfu-util](http://dfu-util.sourceforge.net/).
+To enter the DFU bootloader, double tap the reset (blue) button, or you can use `machine.bootloader()` from the MicroPython REPL.
+
+```bash
+dfu-util -a 0 -d 2341:0368 -D build-ARDUINO_PORTENTA_C33/firmware.bin -Q # -s :leave
+```
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/manifest.py
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/manifest.py
@ -0,0 +1,12 @@
+include("$(PORT_DIR)/boards/manifest.py")
+
+# Networking
+require("bundle-networking")
+
+# Utils
+require("time")
+require("senml")
+require("logging")
+
+# Bluetooth
+require("aioble")
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/mbedtls_config_board.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/mbedtls_config_board.h
@ -0,0 +1,8 @@
+#ifndef MICROPY_INCLUDED_MBEDTLS_CONFIG_BOARD_H
+#define MICROPY_INCLUDED_MBEDTLS_CONFIG_BOARD_H
+
+#define MBEDTLS_ECP_NIST_OPTIM
+
+#include "ports/renesas-ra/mbedtls/mbedtls_config.h"
+
+#endif /* MICROPY_INCLUDED_MBEDTLS_CONFIG_BOARD_H */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/mpconfigboard.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/mpconfigboard.h
@ -0,0 +1,107 @@
+/*
+ * This file is part of the MicroPython project, http://micropython.org/
+ * The MIT License (MIT)
+ * Copyright (c) 2023 Arduino SA
+ */
+
+// MCU config
+#define MICROPY_HW_BOARD_NAME       "PORTENTA C33"
+#define MICROPY_HW_MCU_NAME         "RA6M5"
+#define MICROPY_HW_MCU_SYSCLK       200000000
+#define MICROPY_HW_MCU_PCLK         100000000
+
+// module config
+#define MICROPY_EMIT_THUMB          (1)
+#define MICROPY_EMIT_INLINE_THUMB   (1)
+#define MICROPY_PY_BUILTINS_COMPLEX (1)
+#define MICROPY_PY_GENERATOR_PEND_THROW (1)
+#define MICROPY_PY_MATH             (1)
+#define MICROPY_PY_UHEAPQ           (1)
+#define MICROPY_PY_UTIMEQ           (1)
+#define MICROPY_PY_THREAD           (0) // disable ARM_THUMB_FP using vldr due to RA has single float only
+#define MICROPY_PY_NETWORK          (1)
+
+// peripheral config
+#define MICROPY_HW_ENABLE_RNG       (1)
+#define MICROPY_HW_ENABLE_RTC       (1)
+#define MICROPY_HW_RTC_SOURCE       (1)
+#define MICROPY_HW_ENABLE_ADC       (1)
+#define MICROPY_HW_HAS_FLASH        (1)
+#define MICROPY_HW_ENABLE_USBDEV    (1)
+#define MICROPY_HW_ENABLE_UART_REPL (0)
+#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1)
+
+#define MICROPY_BOARD_STARTUP       PORTENTA_C33_board_startup
+void PORTENTA_C33_board_startup(void);
+
+#define MICROPY_BOARD_ENTER_BOOTLOADER(nargs, args) PORTENTA_C33_board_enter_bootloader()
+void PORTENTA_C33_board_enter_bootloader(void);
+
+// board config
+// USB
+#define MICROPY_HW_USB_VID          (0x2341)
+#define MICROPY_HW_USB_PID          (0x0468)
+
+// UART
+#define MICROPY_HW_UART9_TX         (pin_P602)
+#define MICROPY_HW_UART9_RX         (pin_P110)
+#define MICROPY_HW_UART9_CTS        (pin_P604)
+#define MICROPY_HW_UART9_RTS        (pin_P603)
+
+#define MICROPY_HW_UART8_TX         (pin_PA00)
+#define MICROPY_HW_UART8_RX         (pin_P607)
+#define MICROPY_HW_UART8_CTS        (pin_P801)
+#define MICROPY_HW_UART8_RTS        (pin_P606)
+
+#if MICROPY_HW_ENABLE_UART_REPL
+#define MICROPY_HW_UART_REPL        (HW_UART_9)
+#define MICROPY_HW_UART_REPL_BAUD   (115200)
+#endif
+
+// I2C
+#define MICROPY_HW_I2C2_SCL         (pin_P407)
+#define MICROPY_HW_I2C2_SDA         (pin_P408)
+
+// SPI
+#define MICROPY_HW_SPI1_SSL         (pin_P104)
+#define MICROPY_HW_SPI1_RSPCK       (pin_P102)
+#define MICROPY_HW_SPI1_MISO        (pin_P100)
+#define MICROPY_HW_SPI1_MOSI        (pin_P101)
+
+// DAC
+#define MICROPY_HW_DAC0             (pin_P014)
+#define MICROPY_HW_DAC1             (pin_P015)
+
+// PWM
+#define MICROPY_HW_PWM_1A           (pin_P105)
+#define MICROPY_HW_PWM_8B           (pin_P106)
+#define MICROPY_HW_PWM_3A           (pin_P111)
+#define MICROPY_HW_PWM_7B           (pin_P303)
+#define MICROPY_HW_PWM_6B           (pin_P401)
+// #define MICROPY_HW_PWM            (pin_P210) // AGT
+#define MICROPY_HW_PWM_6A           (pin_P601)
+
+// LEDs
+#define MICROPY_HW_LED1             (pin_P107)
+#define MICROPY_HW_LED2             (pin_P400)
+#define MICROPY_HW_LED3             (pin_P800)
+#define MICROPY_HW_LED_ON(pin)      mp_hal_pin_low(pin)
+#define MICROPY_HW_LED_OFF(pin)     mp_hal_pin_high(pin)
+#define MICROPY_HW_LED_TOGGLE(pin)  mp_hal_pin_toggle(pin)
+
+// Bluetooth config.
+#define MICROPY_HW_BLE_UART_ID          (8)
+#define MICROPY_HW_BLE_UART_RTS         (MICROPY_HW_UART8_RTS)
+#define MICROPY_HW_BLE_UART_BAUDRATE    (115200)
+#define MICROPY_HW_BLE_UART_BAUDRATE_SECONDARY (921600)
+
+// WiFi config.
+#define MICROPY_HW_WIFI_SPI_ID          (1)
+#define MICROPY_HW_WIFI_SPI_CS          (pin_P104)
+#define MICROPY_HW_WIFI_SPI_BAUDRATE    (30 * 1000 * 1000)
+#define MICROPY_HW_WIFI_DATAREADY       (pin_P803)
+#define MICROPY_HW_WIFI_HANDSHAKE       (pin_P806)
+
+// ESP hosted control pins
+#define MICROPY_HW_ESP_HOSTED_RESET     (pin_P804)
+#define MICROPY_HW_ESP_HOSTED_GPIO0     (pin_P803)
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/mpconfigboard.mk
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/mpconfigboard.mk
@ -0,0 +1,22 @@
+CMSIS_MCU = RA6M5
+MCU_SERIES = m33
+LD_FILES = boards/ARDUINO_PORTENTA_C33/ra6m5.ld
+CFLAGS += -DCFG_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED \
+          -DCFG_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED \
+          -DCFG_TUSB_RHPORT0_MODE=0\
+          -DCFG_TUSB_RHPORT1_MODE=OPT_MODE_DEVICE
+
+# MicroPython settings
+MICROPY_VFS_FAT = 1
+MICROPY_HW_ENABLE_RNG = 1
+MICROPY_PY_BLUETOOTH = 1
+MICROPY_BLUETOOTH_NIMBLE = 1
+MICROPY_BLUETOOTH_BTSTACK = 0
+MICROPY_PY_LWIP = 1
+MICROPY_PY_SSL = 1
+MICROPY_SSL_MBEDTLS = 1
+MICROPY_PY_NETWORK = 1
+MICROPY_PY_NETWORK_ESP_HOSTED = 1
+
+FROZEN_MANIFEST = $(BOARD_DIR)/manifest.py
+MBEDTLS_CONFIG_FILE = '"$(BOARD_DIR)/mbedtls_config_board.h"'
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/pins.csv
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/pins.csv
@ -0,0 +1,152 @@
+P000,P000
+P001,P001
+P002,P002
+P003,P003
+P004,P004
+P005,P005
+P006,P006
+P007,P007
+P008,P008
+P009,P009
+P010,P010
+P014,P014
+P015,P015
+P100,P100
+P101,P101
+P102,P102
+P103,P103
+P104,P104
+P105,P105
+P106,P106
+P107,P107
+P108,P108
+P109,P109
+P110,P110
+P111,P111
+P112,P112
+P113,P113
+P114,P114
+P115,P115
+P200,P200
+P201,P201
+P202,P202
+P203,P203
+P204,P204
+P205,P205
+P206,P206
+P207,P207
+P208,P208
+P209,P209
+P210,P210
+P211,P211
+P212,P212
+P213,P213
+P214,P214
+P300,P300
+P301,P301
+P302,P302
+P303,P303
+P304,P304
+P305,P305
+P306,P306
+P307,P307
+P308,P308
+P309,P309
+P310,P310
+P311,P311
+P312,P312
+P313,P313
+P314,P314
+P315,P315
+P400,P400
+P401,P401
+P402,P402
+P403,P403
+P404,P404
+P405,P405
+P406,P406
+P407,P407
+P408,P408
+P409,P409
+P410,P410
+P411,P411
+P412,P412
+P413,P413
+P414,P414
+P415,P415
+P500,P500
+P501,P501
+P502,P502
+P503,P503
+P504,P504
+P505,P505
+P506,P506
+P507,P507
+P508,P508
+P511,P511
+P512,P512
+P513,P513
+P600,P600
+P601,P601
+P602,P602
+P603,P603
+P604,P604
+P605,P605
+P606,P606
+P607,P607
+P608,P608
+P609,P609
+P610,P610
+P611,P611
+P612,P612
+P613,P613
+P614,P614
+P615,P615
+P700,P700
+P701,P701
+P702,P702
+P703,P703
+P704,P704
+P705,P705
+P706,P706
+P707,P707
+P708,P708
+P800,P800
+P801,P801
+P802,P802
+P803,P803
+P804,P804
+P805,P805
+P806,P806
+P900,P900
+P901,P901
+P905,P905
+P906,P906
+P907,P907
+P908,P908
+PA00,PA00
+PA01,PA01
+PA08,PA08
+PA09,PA09
+PA10,PA10
+PB00,PB00
+PB01,PB01
+A0,P006
+A1,P005
+A2,P004
+A3,P002
+A4,P001
+A5,P015
+A6,P014
+D0,P105
+D1,P106
+D2,P111
+D3,P303
+D4,P401
+D5,P210
+LED1,P107
+LED2,P400
+LED3,P800
+LED_R,P107
+LED_G,P400
+LED_B,P800
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra6m5.ld
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra6m5.ld
@ -0,0 +1,306 @@
+/*
+                  Linker File for RA6M5 MCU
+*/
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  FLASH_BOOT (r)     : ORIGIN = 0x00000000, LENGTH = 0x00010000  /* 64K */
+  FLASH (rx)         : ORIGIN = 0x00010000, LENGTH = 0x000f0000  /* 960KB */
+  FLASH_FS (r)       : ORIGIN = 0x00100000, LENGTH = 0x00100000  /* 1MB */
+  RAM (rwx)          : ORIGIN = 0x20000000, LENGTH = 0x00080000  /* 512KB */
+  OSPI_RAM (rwx)     : ORIGIN = 0x68000000, LENGTH = 0x00800000  /* 8MB/8MB */
+  DATA_FLASH (rx)    : ORIGIN = 0x08000000, LENGTH = 0x00002000  /* 8KB */
+  QSPI_FLASH (rx)    : ORIGIN = 0x60000000, LENGTH = 0x01000000  /* 16MB/64MB */
+  OSPI_FLASH (rx)    : ORIGIN = 0x70000000, LENGTH = 0x01000000  /* 16MB/256MB */
+  ID_CODE (rx)       : ORIGIN = 0x00000000, LENGTH = 0x00000000  /* N/A */
+}
+
+/* Library configurations */
+/*GROUP(libgcc.a libc.a libm.a libnosys.a) */
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        _stext = .;
+        __ROM_Start = .;
+
+        /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+         * space because ROM registers are at address 0x400 and there is very little space
+         * in between. */
+        KEEP(*(.fixed_vectors*))
+        KEEP(*(.application_vectors*))
+        __Vectors_End = .;
+        __end__ = .;
+
+        /* ROM Registers start at address 0x00000400 */
+        . = __ROM_Start + 0x400;
+        KEEP(*(.rom_registers*))
+
+        /* Reserving 0x100 bytes of space for ROM registers. */
+        . = __ROM_Start + 0x500;
+
+        *(.text*)
+
+        KEEP(*(.version))
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+        __usb_dev_descriptor_start_fs = .;
+        KEEP(*(.usb_device_desc_fs*))
+        __usb_cfg_descriptor_start_fs = .;
+        KEEP(*(.usb_config_desc_fs*))
+        __usb_interface_descriptor_start_fs = .;
+        KEEP(*(.usb_interface_desc_fs*))
+        __usb_descriptor_end_fs = .;
+        __usb_dev_descriptor_start_hs = .;
+        KEEP(*(.usb_device_desc_hs*))
+        __usb_cfg_descriptor_start_hs = .;
+        KEEP(*(.usb_config_desc_hs*))
+        __usb_interface_descriptor_start_hs = .;
+        KEEP(*(.usb_interface_desc_hs*))
+        __usb_descriptor_end_hs = .;
+
+        KEEP(*(.eh_frame*))
+
+        __ROM_End = .;
+        _etext = .;
+    } > FLASH = 0xFF
+
+    __Vectors_Size = __Vectors_End - __Vectors;
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+        LONG (__etext)
+        LONG (__data_start__)
+        LONG (__data_end__ - __data_start__)
+        LONG (__etext2)
+        LONG (__data2_start__)
+        LONG (__data2_end__ - __data2_start__)
+        __copy_table_end__ = .;
+    } > FLASH
+    */
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+    /*
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        LONG (__bss2_start__)
+        LONG (__bss2_end__ - __bss2_start__)
+        __zero_table_end__ = .;
+    } > FLASH
+    */
+
+    __etext = .;
+
+    /* If DTC is used, put the DTC vector table at the start of SRAM.
+       This avoids memory holes due to 1K alignment required by it. */
+    .fsp_dtc_vector_table (NOLOAD) :
+    {
+        . = ORIGIN(RAM);
+        *(.fsp_dtc_vector_table)
+    } > RAM
+
+    /* Initialized data section. */
+    .data :
+    {
+        _sidata = .;
+        _sdata = .;
+        __data_start__ = .;
+        *(vtable)
+        *(.data.*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        __Code_In_RAM_Start = .;
+
+        KEEP(*(.code_in_ram*))
+        __Code_In_RAM_End = .;
+
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM AT > FLASH
+
+
+
+    .noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        __noinit_start = .;
+        KEEP(*(.noinit*))
+        __noinit_end = .;
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(8);
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        __HeapLimit = .;
+    } > RAM
+
+    /* Stacks are stored in this section. */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        __StackLimit = .;
+        /* Main stack */
+        KEEP(*(.stack))
+        __StackTop = .;
+        /* Thread stacks */
+        KEEP(*(.stack*))
+        __StackTopAll = .;
+        _estack = .;
+    } > RAM
+
+    PROVIDE(__stack = __StackTopAll);
+
+    /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+       at run time for things such as ThreadX memory pool allocations. */
+    __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+    /* Data flash. */
+    .data_flash :
+    {
+        __Data_Flash_Start = .;
+        KEEP(*(.data_flash*))
+        __Data_Flash_End = .;
+    } > DATA_FLASH
+
+    .id_code :
+    {
+        __ID_Code_Start = .;
+        KEEP(*(.id_code*))
+        __ID_Code_End = .;
+    } > ID_CODE
+}
+/* produce a link error if there is not this amount of RAM for these sections */
+/* _minimum_stack_size = 2K; */
+/* _minimum_heap_size = 16K; */
+
+/* Define tho top end of the stack.  The stack is full descending so begins just
+   above last byte of RAM.  Note that EABI requires the stack to be 8-byte
+   aligned for a call. */
+_estack = ORIGIN(RAM) + LENGTH(RAM);
+
+/* RAM extents for the garbage collector */
+_ram_start = ORIGIN(RAM);
+_ram_end = ORIGIN(RAM) + LENGTH(RAM);
+_heap_start = __HeapBase;	/* heap starts just after statically allocated memory */
+_heap_end = __HeapLimit;	/* tunable */
+
+_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS);
+_micropy_hw_internal_flash_storage_end   = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS);
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/board_cfg.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/board_cfg.h
@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void bsp_init(void *p_args);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BOARD_CFG_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_clock_cfg.h"
+#include "bsp_mcu_family_cfg.h"
+#include "board_cfg.h"
+#define RA_NOT_DEFINED 0
+#ifndef BSP_CFG_RTOS
+#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+#define BSP_CFG_RTOS (2)
+#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+#define BSP_CFG_RTOS (1)
+#else
+#define BSP_CFG_RTOS (0)
+#endif
+#endif
+#ifndef BSP_CFG_RTC_USED
+#define BSP_CFG_RTC_USED (1)
+#endif
+#undef RA_NOT_DEFINED
+#if defined(_RA_BOOT_IMAGE)
+#define BSP_CFG_BOOT_IMAGE (1)
+#endif
+#define BSP_CFG_MCU_VCC_MV (3300)
+#define BSP_CFG_STACK_MAIN_BYTES (0x4000)
+#define BSP_CFG_HEAP_BYTES (0x4d000)
+#define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+#define BSP_CFG_ASSERT (0)
+#define BSP_CFG_ERROR_LOG (0)
+
+#define BSP_CFG_PFS_PROTECT ((1))
+
+#define BSP_CFG_C_RUNTIME_INIT ((1))
+#define BSP_CFG_EARLY_INIT     ((0))
+
+#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+#endif
+
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+#endif
+#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_CFG_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (6)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH2CBG
+#define BSP_MCU_FEATURE_SET ('B')
+#define BSP_ROM_SIZE_BYTES (2097152)
+#define BSP_RAM_SIZE_BYTES (524288)
+#define BSP_DATA_FLASH_SIZE_BYTES (8192)
+#define BSP_PACKAGE_BGA
+#define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@ -0,0 +1,386 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bsp_mcu_device_pn_cfg.h"
+#include "bsp_mcu_device_cfg.h"
+#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+#include "bsp_clock_cfg.h"
+#define BSP_MCU_GROUP_RA6M5 (1)
+#define BSP_LOCO_HZ                 (32768)
+#define BSP_MOCO_HZ                 (8000000)
+#define BSP_SUB_CLOCK_HZ            (32768)
+#if   BSP_CFG_HOCO_FREQUENCY == 0
+#define BSP_HOCO_HZ                 (16000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 1
+#define BSP_HOCO_HZ                 (18000000)
+#elif BSP_CFG_HOCO_FREQUENCY == 2
+#define BSP_HOCO_HZ                 (20000000)
+#else
+#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+#endif
+
+#define BSP_CFG_FLL_ENABLE                 (0)
+
+#define BSP_CORTEX_VECTOR_TABLE_ENTRIES    (16U)
+#define BSP_VECTOR_TABLE_MAX_ENTRIES       (112U)
+
+#if defined(_RA_TZ_SECURE)
+#define BSP_TZ_SECURE_BUILD           (1)
+#define BSP_TZ_NONSECURE_BUILD        (0)
+#elif defined(_RA_TZ_NONSECURE)
+#define BSP_TZ_SECURE_BUILD           (0)
+#define BSP_TZ_NONSECURE_BUILD        (1)
+#else
+#define BSP_TZ_SECURE_BUILD           (0)
+#define BSP_TZ_NONSECURE_BUILD        (0)
+#endif
+
+/* TrustZone Settings */
+#define BSP_TZ_CFG_INIT_SECURE_ONLY       (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+#define BSP_TZ_CFG_SKIP_INIT              (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+#define BSP_TZ_CFG_EXCEPTION_RESPONSE     (0)
+
+/* CMSIS TrustZone Settings */
+#define SCB_CSR_AIRCR_INIT                (1)
+#define SCB_AIRCR_BFHFNMINS_VAL           (0)
+#define SCB_AIRCR_SYSRESETREQS_VAL        (1)
+#define SCB_AIRCR_PRIS_VAL                (0)
+#define TZ_FPU_NS_USAGE                   (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+#define SCB_NSACR_CP10_11_VAL             (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+#define FPU_FPCCR_TS_VAL                  (1U)
+#endif
+#define FPU_FPCCR_CLRONRETS_VAL           (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+#define FPU_FPCCR_CLRONRET_VAL            (1)
+#endif
+
+/* The C-Cache line size that is configured during startup. */
+#ifndef BSP_CFG_C_CACHE_LINE_SIZE
+#define BSP_CFG_C_CACHE_LINE_SIZE   (1U)
+#endif
+
+/* Type 1 Peripheral Security Attribution */
+
+/* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB ( \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+    (((1 > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+    (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+    (((1 > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+    (((1 > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+    (((1 > 0) ? 0U : 1U) << 23) /* SCI8 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+    (((1 > 0) ? 0U : 1U) << 31) /* SCI0 */ | \
+    0x33f4f9)         /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC ( \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \
+    0x7fffcef4)         /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD ( \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \
+    (((1 > 0) ? 0U : 1U) << 2) /* AGT1 */ | \
+    (((1 > 0) ? 0U : 1U) << 3) /* AGT0 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
+    (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+    (((2 > 0) ? 0U : 1U) << 20) /* DAC */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+    0xffae07f0)         /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE ( \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \
+    (((1 > 0) ? 0U : 1U) << 2) /* RTC */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+    0x3f3ff8)         /* Unused */
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR ( \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \
+    0xfffffffc)         /* Unused */
+#endif
+
+/* Type 2 Peripheral Security Attribution */
+
+/* Security attribution for Cache registers. */
+#ifndef BSP_TZ_CFG_CSAR
+#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
+#endif
+
+/* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+#define BSP_TZ_CFG_LVDSAR ( \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) |         /* LVD Channel 1 */ \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) |         /* LVD Channel 2 */ \
+    0xFFFFFFFCU)
+#endif
+
+/* Security attribution for LPM registers. */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((1 > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
+#endif
+/* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((1 > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU)
+#endif
+#endif
+
+/* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
+#endif
+
+/* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA ( \
+    (((1 > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \
+    0xFFFF0000U)
+#endif
+
+/* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+/* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_ICUSARC
+#define BSP_TZ_CFG_ICUSARC ( \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+    (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \
+    0xFFFFFF00U)
+#endif
+
+/* Security attribution registers for SELSR0. */
+#ifndef BSP_TZ_CFG_ICUSARD
+#define BSP_TZ_CFG_ICUSARD ((1 > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((1 > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
+#endif
+
+/* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((1 > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
+#endif
+
+/* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+#define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+/* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect FLWT and FCKMHZ registers from nonsecure write access. */
+#define BSP_TZ_CFG_FSAR (0xFEFEU)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_FSAR (0xFFFFU)
+#endif
+#endif
+
+/* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+#define BSP_TZ_CFG_SRAMSAR ( \
+    1 | \
+    ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
+    4 | \
+    0xFFFFFFF8U)
+#endif
+
+/* Security attribution for Standby RAM registers. */
+#ifndef BSP_TZ_CFG_STBRAMSAR
+#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+#endif
+
+/* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+#endif
+
+/* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+#endif
+/* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+#endif
+
+/* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26)
+#define OFS_SEQ5 (1 << 28) | (1 << 30)
+#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+/* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+            #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+#else
+#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+#endif
+#endif
+
+#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+
+/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+#define BSP_PRV_IELS_ENUM(vector)    (ELC_##vector)
+
+/* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+/* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+#define BSP_CFG_ROM_REG_BPS0 (~(0U))
+#endif
+/* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+#define BSP_CFG_ROM_REG_BPS1 (~(0U))
+#endif
+/* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+#define BSP_CFG_ROM_REG_BPS2 (~(0U))
+#endif
+/* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+#endif
+/* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+#define BSP_CFG_ROM_REG_PBPS0 (~(0U))
+#endif
+/* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+#define BSP_CFG_ROM_REG_PBPS1 (~(0U))
+#endif
+/* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+#define BSP_CFG_ROM_REG_PBPS2 (~(0U))
+#endif
+/* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+#endif
+/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@ -0,0 +1,16 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH2CBG.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+
+#endif /* BSP_PIN_CFG_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/bsp_clock_cfg.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/bsp_clock_cfg.h
@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U, 0U) /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U, 0U) /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_1) /* U60CK Div /1 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_6) /* CANFDCLK Div /6 */
+#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/common_data.c
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/common_data.c
@ -0,0 +1,37 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+sce_instance_ctrl_t sce_ctrl;
+const sce_cfg_t sce_cfg =
+{ .lifecycle = SCE_SSD };
+#if SCE_USER_SHA_384_ENABLED
+uint32_t SCE_USER_SHA_384_FUNCTION(uint8_t *message, uint8_t *digest, uint32_t message_length);
+#endif
+icu_instance_ctrl_t g_external_irq0_ctrl;
+const external_irq_cfg_t g_external_irq0_cfg =
+{ .channel = 0,
+  .trigger = EXTERNAL_IRQ_TRIG_RISING,
+  .filter_enable = false,
+  .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64,
+  .p_callback = NULL,
+  /** If NULL then do not add & */
+  #if defined(NULL)
+  .p_context = NULL,
+  #else
+  .p_context = &NULL,
+  #endif
+  .p_extend = NULL,
+  .ipl = (12),
+  #if defined(VECTOR_NUMBER_ICU_IRQ0)
+  .irq = VECTOR_NUMBER_ICU_IRQ0,
+  #else
+  .irq = FSP_INVALID_VECTOR,
+  #endif
+};
+/* Instance structure to use this module. */
+const external_irq_instance_t g_external_irq0 =
+{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu };
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, };
+void g_common_init(void) {
+}
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/common_data.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/common_data.h
@ -0,0 +1,31 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "r_sce.h"
+#include "r_icu.h"
+#include "r_external_irq_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+extern sce_instance_ctrl_t sce_ctrl;
+extern const sce_cfg_t sce_cfg;
+/** External IRQ on ICU Instance. */
+extern const external_irq_instance_t g_external_irq0;
+
+/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */
+extern icu_instance_ctrl_t g_external_irq0_ctrl;
+extern const external_irq_cfg_t g_external_irq0_cfg;
+
+#ifndef NULL
+void NULL(external_irq_callback_args_t *p_args);
+#endif
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/hal_data.c
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/hal_data.c
@ -0,0 +1,611 @@
+/* generated HAL source file - do not edit */
+#include "hal_data.h"
+/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */
+#define ADC_TRIGGER_ADC0        ADC_TRIGGER_SYNC_ELC
+#define ADC_TRIGGER_ADC0_B      ADC_TRIGGER_SYNC_ELC
+#define ADC_TRIGGER_ADC1        ADC_TRIGGER_SYNC_ELC
+#define ADC_TRIGGER_ADC1_B      ADC_TRIGGER_SYNC_ELC
+#define RA_NOT_DEFINED (UINT32_MAX)
+#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+
+/* If the transfer module is DMAC, define a DMAC transfer callback. */
+#include "r_dmac.h"
+extern void spi_tx_dmac_callback(spi_instance_ctrl_t const *const p_ctrl);
+
+void g_spi1_tx_transfer_callback(dmac_callback_args_t *p_args) {
+    FSP_PARAMETER_NOT_USED(p_args);
+    spi_tx_dmac_callback(&g_spi1_ctrl);
+}
+#endif
+
+#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+
+/* If the transfer module is DMAC, define a DMAC transfer callback. */
+#include "r_dmac.h"
+extern void spi_rx_dmac_callback(spi_instance_ctrl_t const *const p_ctrl);
+
+void g_spi1_rx_transfer_callback(dmac_callback_args_t *p_args) {
+    FSP_PARAMETER_NOT_USED(p_args);
+    spi_rx_dmac_callback(&g_spi1_ctrl);
+}
+#endif
+#undef RA_NOT_DEFINED
+
+spi_instance_ctrl_t g_spi1_ctrl;
+
+/** SPI extended configuration for SPI HAL driver */
+const spi_extended_cfg_t g_spi1_ext_cfg =
+{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN,
+  .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX,
+  .ssl_polarity = SPI_SSLP_HIGH,
+  .ssl_select = SPI_SSL_SELECT_SSL1,
+  .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE,
+  .parity = SPI_PARITY_MODE_DISABLE,
+  .byte_swap = SPI_BYTE_SWAP_DISABLE,
+  .spck_div =
+  {
+      /* Actual calculated bitrate: 10000000. */ .spbr = 4,
+      .brdv = 0
+  },
+  .spck_delay = SPI_DELAY_COUNT_1,
+  .ssl_negation_delay = SPI_DELAY_COUNT_1,
+  .next_access_delay = SPI_DELAY_COUNT_1 };
+
+/** SPI configuration for SPI HAL driver */
+const spi_cfg_t g_spi1_cfg =
+{ .channel = 1,
+
+  #if defined(VECTOR_NUMBER_SPI1_RXI)
+  .rxi_irq = VECTOR_NUMBER_SPI1_RXI,
+  #else
+  .rxi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SPI1_TXI)
+  .txi_irq = VECTOR_NUMBER_SPI1_TXI,
+  #else
+  .txi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SPI1_TEI)
+  .tei_irq = VECTOR_NUMBER_SPI1_TEI,
+  #else
+  .tei_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SPI1_ERI)
+  .eri_irq = VECTOR_NUMBER_SPI1_ERI,
+  #else
+  .eri_irq = FSP_INVALID_VECTOR,
+  #endif
+
+  .rxi_ipl = (12),
+  .txi_ipl = (12),
+  .tei_ipl = (12),
+  .eri_ipl = (12),
+
+  .operating_mode = SPI_MODE_MASTER,
+
+  .clk_phase = SPI_CLK_PHASE_EDGE_ODD,
+  .clk_polarity = SPI_CLK_POLARITY_HIGH,
+
+  .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE,
+  .bit_order = SPI_BIT_ORDER_MSB_FIRST,
+  .p_transfer_tx = g_spi1_P_TRANSFER_TX,
+  .p_transfer_rx = g_spi1_P_TRANSFER_RX,
+  .p_callback = spi_callback,
+
+  .p_context = NULL,
+  .p_extend = (void *)&g_spi1_ext_cfg, };
+
+/* Instance structure to use this module. */
+const spi_instance_t g_spi1 =
+{ .p_ctrl = &g_spi1_ctrl, .p_cfg = &g_spi1_cfg, .p_api = &g_spi_on_spi };
+sci_uart_instance_ctrl_t g_uart8_ctrl;
+
+baud_setting_t g_uart8_baud_setting =
+{
+    /* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 1,
+    .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 0, .cks = 0, .brr = 17, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme =
+        false
+};
+
+/** UART extended configuration for UARTonSCI HAL driver */
+const sci_uart_extended_cfg_t g_uart8_cfg_extend =
+{ .clock = SCI_UART_CLOCK_INT, .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel =
+      SCI_UART_NOISE_CANCELLATION_DISABLE,
+  .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart8_baud_setting, .flow_control =
+      SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS,
+  #if 0xFF != 0xFF
+  .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
+  #else
+  .flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
+  #endif
+  .rs485_setting =
+  { .enable = SCI_UART_RS485_DISABLE, .polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
+    #if 0xFF != 0xFF
+    .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
+    #else
+    .de_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
+    #endif
+  }, };
+
+/** UART interface configuration */
+const uart_cfg_t g_uart8_cfg =
+{ .channel = 8, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
+      user_uart_callback,
+  .p_context = NULL, .p_extend = &g_uart8_cfg_extend,
+#define RA_NOT_DEFINED (1)
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  .p_transfer_tx = NULL,
+  #else
+  .p_transfer_tx = &RA_NOT_DEFINED,
+  #endif
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  .p_transfer_rx = NULL,
+  #else
+  .p_transfer_rx = &RA_NOT_DEFINED,
+  #endif
+#undef RA_NOT_DEFINED
+  .rxi_ipl = (12),
+  .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
+  #if defined(VECTOR_NUMBER_SCI8_RXI)
+  .rxi_irq = VECTOR_NUMBER_SCI8_RXI,
+  #else
+  .rxi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SCI8_TXI)
+  .txi_irq = VECTOR_NUMBER_SCI8_TXI,
+  #else
+  .txi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SCI8_TEI)
+  .tei_irq = VECTOR_NUMBER_SCI8_TEI,
+  #else
+  .tei_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SCI8_ERI)
+  .eri_irq = VECTOR_NUMBER_SCI8_ERI,
+  #else
+  .eri_irq = FSP_INVALID_VECTOR,
+  #endif
+};
+
+/* Instance structure to use this module. */
+const uart_instance_t g_uart8 =
+{ .p_ctrl = &g_uart8_ctrl, .p_cfg = &g_uart8_cfg, .p_api = &g_uart_on_sci };
+agt_instance_ctrl_t g_timer1_ctrl;
+const agt_extended_cfg_t g_timer1_extend =
+{ .count_source = AGT_CLOCK_PCLKB,
+  .agto = AGT_PIN_CFG_DISABLED,
+  .agtoab_settings_b.agtoa = AGT_PIN_CFG_DISABLED,
+  .agtoab_settings_b.agtob = AGT_PIN_CFG_DISABLED,
+  .measurement_mode = AGT_MEASURE_DISABLED,
+  .agtio_filter = AGT_AGTIO_FILTER_NONE,
+  .enable_pin = AGT_ENABLE_PIN_NOT_USED,
+  .trigger_edge = AGT_TRIGGER_EDGE_RISING, };
+const timer_cfg_t g_timer1_cfg =
+{ .mode = TIMER_MODE_PERIODIC,
+/* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts = (uint32_t)0x10000,
+  .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 1, .p_callback = NULL,
+  /** If NULL then do not add & */
+  #if defined(NULL)
+  .p_context = NULL,
+  #else
+  .p_context = &NULL,
+  #endif
+  .p_extend = &g_timer1_extend,
+  .cycle_end_ipl = (5),
+  #if defined(VECTOR_NUMBER_AGT1_INT)
+  .cycle_end_irq = VECTOR_NUMBER_AGT1_INT,
+  #else
+  .cycle_end_irq = FSP_INVALID_VECTOR,
+  #endif
+};
+/* Instance structure to use this module. */
+const timer_instance_t g_timer1 =
+{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt };
+agt_instance_ctrl_t g_timer0_ctrl;
+const agt_extended_cfg_t g_timer0_extend =
+{ .count_source = AGT_CLOCK_PCLKB,
+  .agto = AGT_PIN_CFG_DISABLED,
+  .agtoab_settings_b.agtoa = AGT_PIN_CFG_DISABLED,
+  .agtoab_settings_b.agtob = AGT_PIN_CFG_DISABLED,
+  .measurement_mode = AGT_MEASURE_DISABLED,
+  .agtio_filter = AGT_AGTIO_FILTER_NONE,
+  .enable_pin = AGT_ENABLE_PIN_NOT_USED,
+  .trigger_edge = AGT_TRIGGER_EDGE_RISING, };
+const timer_cfg_t g_timer0_cfg =
+{ .mode = TIMER_MODE_PERIODIC,
+/* Actual period: 0.00131072 seconds. Actual duty: 50%. */ .period_counts = (uint32_t)0x10000,
+  .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = NULL,
+  /** If NULL then do not add & */
+  #if defined(NULL)
+  .p_context = NULL,
+  #else
+  .p_context = &NULL,
+  #endif
+  .p_extend = &g_timer0_extend,
+  .cycle_end_ipl = (5),
+  #if defined(VECTOR_NUMBER_AGT0_INT)
+  .cycle_end_irq = VECTOR_NUMBER_AGT0_INT,
+  #else
+  .cycle_end_irq = FSP_INVALID_VECTOR,
+  #endif
+};
+/* Instance structure to use this module. */
+const timer_instance_t g_timer0 =
+{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt };
+dac_instance_ctrl_t g_dac1_ctrl;
+const dac_extended_cfg_t g_dac1_ext_cfg =
+{ .enable_charge_pump = 0,
+  .data_format = DAC_DATA_FORMAT_FLUSH_RIGHT,
+  .output_amplifier_enabled = 0,
+  .internal_output_enabled = false, };
+const dac_cfg_t g_dac1_cfg =
+{ .channel = 1, .ad_da_synchronized = false, .p_extend = &g_dac1_ext_cfg };
+/* Instance structure to use this module. */
+const dac_instance_t g_dac1 =
+{ .p_ctrl = &g_dac1_ctrl, .p_cfg = &g_dac1_cfg, .p_api = &g_dac_on_dac };
+dac_instance_ctrl_t g_dac0_ctrl;
+const dac_extended_cfg_t g_dac0_ext_cfg =
+{ .enable_charge_pump = 0,
+  .data_format = DAC_DATA_FORMAT_FLUSH_RIGHT,
+  .output_amplifier_enabled = 0,
+  .internal_output_enabled = false, };
+const dac_cfg_t g_dac0_cfg =
+{ .channel = 0, .ad_da_synchronized = false, .p_extend = &g_dac0_ext_cfg };
+/* Instance structure to use this module. */
+const dac_instance_t g_dac0 =
+{ .p_ctrl = &g_dac0_ctrl, .p_cfg = &g_dac0_cfg, .p_api = &g_dac_on_dac };
+adc_instance_ctrl_t g_adc0_ctrl;
+const adc_extended_cfg_t g_adc0_cfg_extend =
+{ .add_average_count = ADC_ADD_OFF,
+  .clearing = ADC_CLEAR_AFTER_READ_ON,
+  .trigger_group_b = ADC_TRIGGER_SYNC_ELC,
+  .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED,
+  .adc_vref_control = ADC_VREF_CONTROL_VREFH,
+  .enable_adbuf = 0,
+  #if defined(VECTOR_NUMBER_ADC0_WINDOW_A)
+  .window_a_irq = VECTOR_NUMBER_ADC0_WINDOW_A,
+  #else
+  .window_a_irq = FSP_INVALID_VECTOR,
+  #endif
+  .window_a_ipl = (BSP_IRQ_DISABLED),
+  #if defined(VECTOR_NUMBER_ADC0_WINDOW_B)
+  .window_b_irq = VECTOR_NUMBER_ADC0_WINDOW_B,
+  #else
+  .window_b_irq = FSP_INVALID_VECTOR,
+  #endif
+  .window_b_ipl = (BSP_IRQ_DISABLED), };
+const adc_cfg_t g_adc0_cfg =
+{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment =
+      (adc_alignment_t)ADC_ALIGNMENT_RIGHT,
+  .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL,
+  /** If NULL then do not add & */
+  #if defined(NULL)
+  .p_context = NULL,
+  #else
+  .p_context = &NULL,
+  #endif
+  .p_extend = &g_adc0_cfg_extend,
+  #if defined(VECTOR_NUMBER_ADC0_SCAN_END)
+  .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END,
+  #else
+  .scan_end_irq = FSP_INVALID_VECTOR,
+  #endif
+  .scan_end_ipl = (BSP_IRQ_DISABLED),
+  #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B)
+  .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B,
+  #else
+  .scan_end_b_irq = FSP_INVALID_VECTOR,
+  #endif
+  .scan_end_b_ipl = (BSP_IRQ_DISABLED), };
+#if ((0) | (0))
+const adc_window_cfg_t g_adc0_window_cfg =
+{
+    .compare_mask = 0,
+    .compare_mode_mask = 0,
+    .compare_cfg = (0) | (0) | (0) | (ADC_COMPARE_CFG_EVENT_OUTPUT_OR),
+    .compare_ref_low = 0,
+    .compare_ref_high = 0,
+    .compare_b_channel = (ADC_WINDOW_B_CHANNEL_0),
+    .compare_b_mode = (ADC_WINDOW_B_MODE_LESS_THAN_OR_OUTSIDE),
+    .compare_b_ref_low = 0,
+    .compare_b_ref_high = 0,
+};
+#endif
+const adc_channel_cfg_t g_adc0_channel_cfg =
+{ .scan_mask = 0,
+  .scan_mask_group_b = 0,
+  .priority_group_a = ADC_GROUP_A_PRIORITY_OFF,
+  .add_mask = 0,
+  .sample_hold_mask = 0,
+  .sample_hold_states = 24,
+  #if ((0) | (0))
+  .p_window_cfg = (adc_window_cfg_t *)&g_adc0_window_cfg,
+  #else
+  .p_window_cfg = NULL,
+  #endif
+};
+/* Instance structure to use this module. */
+const adc_instance_t g_adc0 =
+{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc };
+iic_master_instance_ctrl_t g_i2c_master0_ctrl;
+const iic_master_extended_cfg_t g_i2c_master0_extend =
+{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, .timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED,
+/* Actual calculated bitrate: 98425. Actual calculated duty cycle: 50%. */ .clock_settings.brl_value = 28,
+  .clock_settings.brh_value = 28, .clock_settings.cks_value = 3, };
+const i2c_master_cfg_t g_i2c_master0_cfg =
+{ .channel = 0, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT,
+#define RA_NOT_DEFINED (1)
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  .p_transfer_tx = NULL,
+  #else
+  .p_transfer_tx = &RA_NOT_DEFINED,
+  #endif
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  .p_transfer_rx = NULL,
+  #else
+  .p_transfer_rx = &RA_NOT_DEFINED,
+  #endif
+#undef RA_NOT_DEFINED
+  .p_callback = NULL,
+  .p_context = NULL,
+  #if defined(VECTOR_NUMBER_IIC0_RXI)
+  .rxi_irq = VECTOR_NUMBER_IIC0_RXI,
+  #else
+  .rxi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_IIC0_TXI)
+  .txi_irq = VECTOR_NUMBER_IIC0_TXI,
+  #else
+  .txi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_IIC0_TEI)
+  .tei_irq = VECTOR_NUMBER_IIC0_TEI,
+  #else
+  .tei_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_IIC0_ERI)
+  .eri_irq = VECTOR_NUMBER_IIC0_ERI,
+  #else
+  .eri_irq = FSP_INVALID_VECTOR,
+  #endif
+  .ipl = (12),
+  .p_extend = &g_i2c_master0_extend, };
+/* Instance structure to use this module. */
+const i2c_master_instance_t g_i2c_master0 =
+{ .p_ctrl = &g_i2c_master0_ctrl, .p_cfg = &g_i2c_master0_cfg, .p_api = &g_i2c_master_on_iic };
+usb_instance_ctrl_t g_basic0_ctrl;
+
+#if !defined(g_usb_descriptor)
+extern usb_descriptor_t g_usb_descriptor;
+#endif
+#define RA_NOT_DEFINED (1)
+const usb_cfg_t g_basic0_cfg =
+{ .usb_mode = USB_MODE_PERI, .usb_speed = USB_SPEED_FS, .module_number = 0, .type = USB_CLASS_PCDC,
+  #if defined(g_usb_descriptor)
+  .p_usb_reg = g_usb_descriptor,
+  #else
+  .p_usb_reg = &g_usb_descriptor,
+  #endif
+  .usb_complience_cb = NULL,
+  #if defined(VECTOR_NUMBER_USBFS_INT)
+  .irq = VECTOR_NUMBER_USBFS_INT,
+  #else
+  .irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_USBFS_RESUME)
+  .irq_r = VECTOR_NUMBER_USBFS_RESUME,
+  #else
+  .irq_r = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_USBFS_FIFO_0)
+  .irq_d0 = VECTOR_NUMBER_USBFS_FIFO_0,
+  #else
+  .irq_d0 = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_USBFS_FIFO_1)
+  .irq_d1 = VECTOR_NUMBER_USBFS_FIFO_1,
+  #else
+  .irq_d1 = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_USBHS_USB_INT_RESUME)
+  .hsirq = VECTOR_NUMBER_USBHS_USB_INT_RESUME,
+  #else
+  .hsirq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_USBHS_FIFO_0)
+  .hsirq_d0 = VECTOR_NUMBER_USBHS_FIFO_0,
+  #else
+  .hsirq_d0 = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_USBHS_FIFO_1)
+  .hsirq_d1 = VECTOR_NUMBER_USBHS_FIFO_1,
+  #else
+  .hsirq_d1 = FSP_INVALID_VECTOR,
+  #endif
+  .ipl = (12),
+  .ipl_r = (12), .ipl_d0 = (12), .ipl_d1 = (12), .hsipl = (12), .hsipl_d0 = (12), .hsipl_d1 = (12),
+  #if (BSP_CFG_RTOS != 0)
+  .p_usb_apl_callback = NULL,
+  #else
+  .p_usb_apl_callback = NULL,
+  #endif
+  #if defined(NULL)
+  .p_context = NULL,
+  #else
+  .p_context = &NULL,
+  #endif
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  #else
+  .p_transfer_tx = &RA_NOT_DEFINED,
+  #endif
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  #else
+  .p_transfer_rx = &RA_NOT_DEFINED,
+  #endif
+};
+#undef RA_NOT_DEFINED
+
+/* Instance structure to use this module. */
+const usb_instance_t g_basic0 =
+{ .p_ctrl = &g_basic0_ctrl, .p_cfg = &g_basic0_cfg, .p_api = &g_usb_on_usb, };
+
+rtc_instance_ctrl_t g_rtc0_ctrl;
+const rtc_error_adjustment_cfg_t g_rtc0_err_cfg =
+{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC,
+  .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND,
+  .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE,
+  .adjustment_value = 0, };
+const rtc_cfg_t g_rtc0_cfg =
+{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback =
+      NULL,
+  .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14),
+  #if defined(VECTOR_NUMBER_RTC_ALARM)
+  .alarm_irq = VECTOR_NUMBER_RTC_ALARM,
+  #else
+  .alarm_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_RTC_PERIOD)
+  .periodic_irq = VECTOR_NUMBER_RTC_PERIOD,
+  #else
+  .periodic_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_RTC_CARRY)
+  .carry_irq = VECTOR_NUMBER_RTC_CARRY,
+  #else
+  .carry_irq = FSP_INVALID_VECTOR,
+  #endif
+};
+/* Instance structure to use this module. */
+const rtc_instance_t g_rtc0 =
+{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc };
+sci_uart_instance_ctrl_t g_uart9_ctrl;
+
+baud_setting_t g_uart9_baud_setting =
+{
+    /* Baud rate calculated with 0.469% error. */ .semr_baudrate_bits_b.abcse = 0,
+    .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 1, .cks = 0, .brr = 53, .mddr = (uint8_t)256, .semr_baudrate_bits_b.brme =
+        false
+};
+
+/** UART extended configuration for UARTonSCI HAL driver */
+const sci_uart_extended_cfg_t g_uart9_cfg_extend =
+{ .clock = SCI_UART_CLOCK_INT, .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel =
+      SCI_UART_NOISE_CANCELLATION_DISABLE,
+  .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart9_baud_setting, .flow_control =
+      SCI_UART_FLOW_CONTROL_RTS,
+  #if 0xFF != 0xFF
+  .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
+  #else
+  .flow_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
+  #endif
+  .rs485_setting =
+  { .enable = SCI_UART_RS485_DISABLE, .polarity = SCI_UART_RS485_DE_POLARITY_HIGH,
+    #if 0xFF != 0xFF
+    .de_control_pin = BSP_IO_PORT_FF_PIN_0xFF,
+    #else
+    .de_control_pin = (bsp_io_port_pin_t)UINT16_MAX,
+    #endif
+  }, };
+
+/** UART interface configuration */
+const uart_cfg_t g_uart9_cfg =
+{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback =
+      user_uart_callback,
+  .p_context = NULL, .p_extend = &g_uart9_cfg_extend,
+#define RA_NOT_DEFINED (1)
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  .p_transfer_tx = NULL,
+  #else
+  .p_transfer_tx = &RA_NOT_DEFINED,
+  #endif
+  #if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+  .p_transfer_rx = NULL,
+  #else
+  .p_transfer_rx = &RA_NOT_DEFINED,
+  #endif
+#undef RA_NOT_DEFINED
+  .rxi_ipl = (12),
+  .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12),
+  #if defined(VECTOR_NUMBER_SCI9_RXI)
+  .rxi_irq = VECTOR_NUMBER_SCI9_RXI,
+  #else
+  .rxi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SCI9_TXI)
+  .txi_irq = VECTOR_NUMBER_SCI9_TXI,
+  #else
+  .txi_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SCI9_TEI)
+  .tei_irq = VECTOR_NUMBER_SCI9_TEI,
+  #else
+  .tei_irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_SCI9_ERI)
+  .eri_irq = VECTOR_NUMBER_SCI9_ERI,
+  #else
+  .eri_irq = FSP_INVALID_VECTOR,
+  #endif
+};
+
+/* Instance structure to use this module. */
+const uart_instance_t g_uart9 =
+{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci };
+flash_hp_instance_ctrl_t g_flash0_ctrl;
+const flash_cfg_t g_flash0_cfg =
+{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL,
+  #if defined(VECTOR_NUMBER_FCU_FRDYI)
+  .irq = VECTOR_NUMBER_FCU_FRDYI,
+  #else
+  .irq = FSP_INVALID_VECTOR,
+  #endif
+  #if defined(VECTOR_NUMBER_FCU_FIFERR)
+  .err_irq = VECTOR_NUMBER_FCU_FIFERR,
+  #else
+  .err_irq = FSP_INVALID_VECTOR,
+  #endif
+  .err_ipl = (BSP_IRQ_DISABLED),
+  .ipl = (BSP_IRQ_DISABLED), };
+/* Instance structure to use this module. */
+const flash_instance_t g_flash0 =
+{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp };
+lpm_instance_ctrl_t g_lpm0_ctrl;
+
+const lpm_cfg_t g_lpm0_cfg =
+{ .low_power_mode = LPM_MODE_SLEEP, .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM
+      | (lpm_standby_wake_source_t)0,
+  #if BSP_FEATURE_LPM_HAS_SNOOZE
+  .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE,
+  .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING,
+  .snooze_end_sources = (lpm_snooze_end_t)0,
+  .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE,
+  #endif
+  #if BSP_FEATURE_LPM_HAS_SBYCR_OPE
+  .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+  #endif
+  #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY
+  .io_port_state = LPM_IO_PORT_NO_CHANGE,
+  .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0,
+  .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+  .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+  #endif
+  #if BSP_FEATURE_LPM_HAS_PDRAMSCR
+  .ram_retention_cfg.ram_retention = (uint8_t)(0),
+  .ram_retention_cfg.tcm_retention = false,
+  #endif
+  #if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP
+  .ram_retention_cfg.standby_ram_retention = false,
+  #endif
+  #if BSP_FEATURE_LPM_HAS_LDO_CONTROL
+  .ldo_standby_cfg.pll1_ldo = false,
+  .ldo_standby_cfg.pll2_ldo = false,
+  .ldo_standby_cfg.hoco_ldo = false,
+  #endif
+  .p_extend = NULL, };
+
+const lpm_instance_t g_lpm0 =
+{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg };
+void g_hal_init(void) {
+    g_common_init();
+}
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/hal_data.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/hal_data.h
@ -0,0 +1,177 @@
+/* generated HAL header file - do not edit */
+#ifndef HAL_DATA_H_
+#define HAL_DATA_H_
+#include <stdint.h>
+#include "bsp_api.h"
+#include "common_data.h"
+#include "r_spi.h"
+#include "r_sci_uart.h"
+#include "r_uart_api.h"
+#include "r_agt.h"
+#include "r_timer_api.h"
+#include "r_dac.h"
+#include "r_dac_api.h"
+#include "r_adc.h"
+#include "r_adc_api.h"
+#include "r_iic_master.h"
+#include "r_i2c_master_api.h"
+#include "r_usb_basic.h"
+#include "r_usb_basic_api.h"
+#include "r_usb_pcdc_api.h"
+#include "r_rtc.h"
+#include "r_rtc_api.h"
+#include "r_flash_hp.h"
+#include "r_flash_api.h"
+#include "r_lpm.h"
+#include "r_lpm_api.h"
+FSP_HEADER
+/** SPI on SPI Instance. */
+extern const spi_instance_t g_spi1;
+
+/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */
+extern spi_instance_ctrl_t g_spi1_ctrl;
+extern const spi_cfg_t g_spi1_cfg;
+
+/** Callback used by SPI Instance. */
+#ifndef spi_callback
+void spi_callback(spi_callback_args_t *p_args);
+#endif
+
+#define RA_NOT_DEFINED (1)
+#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+#define g_spi1_P_TRANSFER_TX (NULL)
+#else
+    #define g_spi1_P_TRANSFER_TX (&RA_NOT_DEFINED)
+#endif
+#if (RA_NOT_DEFINED == RA_NOT_DEFINED)
+#define g_spi1_P_TRANSFER_RX (NULL)
+#else
+    #define g_spi1_P_TRANSFER_RX (&RA_NOT_DEFINED)
+#endif
+#undef RA_NOT_DEFINED
+/** UART on SCI Instance. */
+extern const uart_instance_t g_uart8;
+
+/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
+extern sci_uart_instance_ctrl_t g_uart8_ctrl;
+extern const uart_cfg_t g_uart8_cfg;
+extern const sci_uart_extended_cfg_t g_uart8_cfg_extend;
+
+#ifndef user_uart_callback
+void user_uart_callback(uart_callback_args_t *p_args);
+#endif
+/** AGT Timer Instance */
+extern const timer_instance_t g_timer1;
+
+/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
+extern agt_instance_ctrl_t g_timer1_ctrl;
+extern const timer_cfg_t g_timer1_cfg;
+
+#ifndef NULL
+void NULL(timer_callback_args_t *p_args);
+#endif
+/** AGT Timer Instance */
+extern const timer_instance_t g_timer0;
+
+/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */
+extern agt_instance_ctrl_t g_timer0_ctrl;
+extern const timer_cfg_t g_timer0_cfg;
+
+#ifndef NULL
+void NULL(timer_callback_args_t *p_args);
+#endif
+/** DAC on DAC Instance. */
+extern const dac_instance_t g_dac1;
+
+/** Access the DAC instance using these structures when calling API functions directly (::p_api is not used). */
+extern dac_instance_ctrl_t g_dac1_ctrl;
+extern const dac_cfg_t g_dac1_cfg;
+/** DAC on DAC Instance. */
+extern const dac_instance_t g_dac0;
+
+/** Access the DAC instance using these structures when calling API functions directly (::p_api is not used). */
+extern dac_instance_ctrl_t g_dac0_ctrl;
+extern const dac_cfg_t g_dac0_cfg;
+/** ADC on ADC Instance. */
+extern const adc_instance_t g_adc0;
+
+/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */
+extern adc_instance_ctrl_t g_adc0_ctrl;
+extern const adc_cfg_t g_adc0_cfg;
+extern const adc_channel_cfg_t g_adc0_channel_cfg;
+
+#ifndef NULL
+void NULL(adc_callback_args_t *p_args);
+#endif
+
+#ifndef NULL
+#define ADC_DMAC_CHANNELS_PER_BLOCK_NULL  0
+#endif
+/* I2C Master on IIC Instance. */
+extern const i2c_master_instance_t g_i2c_master0;
+
+/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */
+extern iic_master_instance_ctrl_t g_i2c_master0_ctrl;
+extern const i2c_master_cfg_t g_i2c_master0_cfg;
+
+#ifndef NULL
+void NULL(i2c_master_callback_args_t *p_args);
+#endif
+/* Basic on USB Instance. */
+extern const usb_instance_t g_basic0;
+
+/** Access the USB instance using these structures when calling API functions directly (::p_api is not used). */
+extern usb_instance_ctrl_t g_basic0_ctrl;
+extern const usb_cfg_t g_basic0_cfg;
+
+#ifndef NULL
+void NULL(void *);
+#endif
+
+#if 2 == BSP_CFG_RTOS
+#ifndef NULL
+void NULL(usb_event_info_t *, usb_hdl_t, usb_onoff_t);
+#endif
+#endif
+/** CDC Driver on USB Instance. */
+/* RTC Instance. */
+extern const rtc_instance_t g_rtc0;
+
+/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */
+extern rtc_instance_ctrl_t g_rtc0_ctrl;
+extern const rtc_cfg_t g_rtc0_cfg;
+
+#ifndef NULL
+void NULL(rtc_callback_args_t *p_args);
+#endif
+/** UART on SCI Instance. */
+extern const uart_instance_t g_uart9;
+
+/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */
+extern sci_uart_instance_ctrl_t g_uart9_ctrl;
+extern const uart_cfg_t g_uart9_cfg;
+extern const sci_uart_extended_cfg_t g_uart9_cfg_extend;
+
+#ifndef user_uart_callback
+void user_uart_callback(uart_callback_args_t *p_args);
+#endif
+/* Flash on Flash HP Instance */
+extern const flash_instance_t g_flash0;
+
+/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */
+extern flash_hp_instance_ctrl_t g_flash0_ctrl;
+extern const flash_cfg_t g_flash0_cfg;
+
+#ifndef NULL
+void NULL(flash_callback_args_t *p_args);
+#endif
+/** lpm Instance */
+extern const lpm_instance_t g_lpm0;
+
+/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */
+extern lpm_instance_ctrl_t g_lpm0_ctrl;
+extern const lpm_cfg_t g_lpm0_cfg;
+void hal_entry(void);
+void g_hal_init(void);
+FSP_FOOTER
+#endif /* HAL_DATA_H_ */
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/pin_data.c
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/pin_data.c
@ -0,0 +1,76 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport_api.h"
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] =
+{
+    { .pin = BSP_IO_PORT_00_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_00_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_00_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_00_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_00_PIN_05, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_00_PIN_06, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_00_PIN_14, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_00_PIN_15, .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE) },
+    { .pin = BSP_IO_PORT_01_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SPI) },
+    { .pin = BSP_IO_PORT_01_PIN_01, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SPI) },
+    { .pin = BSP_IO_PORT_01_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SPI) },
+    { .pin = BSP_IO_PORT_01_PIN_04, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SPI) },
+    { .pin = BSP_IO_PORT_01_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
+    { .pin = BSP_IO_PORT_01_PIN_10, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
+    { .pin = BSP_IO_PORT_03_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_DEBUG) },
+    { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID
+        | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) },
+    { .pin = BSP_IO_PORT_04_PIN_08, .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID
+        | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC) },
+    { .pin = BSP_IO_PORT_06_PIN_02, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9) },
+    { .pin = BSP_IO_PORT_06_PIN_07, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
+    { .pin = BSP_IO_PORT_10_PIN_00, .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN
+        | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8) },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg =
+{ .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], };
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void) {
+    #if (2U == BSP_FEATURE_IOPORT_VERSION)
+    uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+    #else
+    uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+    #endif
+    memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+    for (uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+    {
+        uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+        uint32_t port = port_pin >> 8U;
+        uint32_t pin = port_pin & 0xFFU;
+        pmsar[port] &= (uint16_t) ~(1U << pin);
+    }
+
+    for (uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+    {
+        #if (2U == BSP_FEATURE_IOPORT_VERSION)
+        R_PMISC->PMSAR[i].PMSAR = (uint16_t)pmsar[i];
+        #else
+        R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+        #endif
+    }
+
+}
+#endif
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/vector_data.c
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/vector_data.c
@ -0,0 +1,69 @@
+/* generated vector source file - do not edit */
+#include "bsp_api.h"
+/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */
+#if VECTOR_DATA_IRQ_COUNT > 0
+BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) =
+{
+    [0] = sci_uart_rxi_isr,                     /* SCI9 RXI (Received data full) */
+    [1] = sci_uart_txi_isr,         /* SCI9 TXI (Transmit data empty) */
+    [2] = sci_uart_tei_isr,         /* SCI9 TEI (Transmit end) */
+    [3] = sci_uart_eri_isr,         /* SCI9 ERI (Receive error) */
+    [4] = rtc_alarm_periodic_isr,         /* RTC ALARM (Alarm interrupt) */
+    [5] = rtc_alarm_periodic_isr,         /* RTC PERIOD (Periodic interrupt) */
+    [6] = rtc_carry_isr,         /* RTC CARRY (Carry interrupt) */
+    [7] = r_icu_isr,         /* ICU IRQ0 (External pin interrupt 0) */
+    [8] = usbfs_interrupt_handler,         /* USBFS INT (USBFS interrupt) */
+    [9] = usbfs_resume_handler,         /* USBFS RESUME (USBFS resume interrupt) */
+    [10] = usbfs_d0fifo_handler,         /* USBFS FIFO 0 (DMA transfer request 0) */
+    [11] = usbfs_d1fifo_handler,         /* USBFS FIFO 1 (DMA transfer request 1) */
+    [12] = usbhs_interrupt_handler,         /* USBHS USB INT RESUME (USBHS interrupt) */
+    [13] = usbhs_d0fifo_handler,         /* USBHS FIFO 0 (DMA transfer request 0) */
+    [14] = usbhs_d1fifo_handler,         /* USBHS FIFO 1 (DMA transfer request 1) */
+    [15] = iic_master_rxi_isr,         /* IIC0 RXI (Receive data full) */
+    [16] = iic_master_txi_isr,         /* IIC0 TXI (Transmit data empty) */
+    [17] = iic_master_tei_isr,         /* IIC0 TEI (Transmit end) */
+    [18] = iic_master_eri_isr,         /* IIC0 ERI (Transfer error) */
+    [19] = agt_int_isr,         /* AGT0 INT (AGT interrupt) */
+    [20] = agt_int_isr,         /* AGT1 INT (AGT interrupt) */
+    [21] = sci_uart_rxi_isr,         /* SCI8 RXI (Received data full) */
+    [22] = sci_uart_txi_isr,         /* SCI8 TXI (Transmit data empty) */
+    [23] = sci_uart_tei_isr,         /* SCI8 TEI (Transmit end) */
+    [24] = sci_uart_eri_isr,         /* SCI8 ERI (Receive error) */
+    [25] = spi_rxi_isr,         /* SPI1 RXI (Receive buffer full) */
+    [26] = spi_txi_isr,         /* SPI1 TXI (Transmit buffer empty) */
+    [27] = spi_tei_isr,         /* SPI1 TEI (Transmission complete event) */
+    [28] = spi_eri_isr,         /* SPI1 ERI (Error) */
+};
+const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] =
+{
+    [0] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI),         /* SCI9 RXI (Received data full) */
+    [1] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI),         /* SCI9 TXI (Transmit data empty) */
+    [2] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI),         /* SCI9 TEI (Transmit end) */
+    [3] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI),         /* SCI9 ERI (Receive error) */
+    [4] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM),         /* RTC ALARM (Alarm interrupt) */
+    [5] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD),         /* RTC PERIOD (Periodic interrupt) */
+    [6] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY),         /* RTC CARRY (Carry interrupt) */
+    [7] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0),         /* ICU IRQ0 (External pin interrupt 0) */
+    [8] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT),         /* USBFS INT (USBFS interrupt) */
+    [9] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME),         /* USBFS RESUME (USBFS resume interrupt) */
+    [10] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_0),         /* USBFS FIFO 0 (DMA transfer request 0) */
+    [11] = BSP_PRV_IELS_ENUM(EVENT_USBFS_FIFO_1),         /* USBFS FIFO 1 (DMA transfer request 1) */
+    [12] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME),         /* USBHS USB INT RESUME (USBHS interrupt) */
+    [13] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_0),         /* USBHS FIFO 0 (DMA transfer request 0) */
+    [14] = BSP_PRV_IELS_ENUM(EVENT_USBHS_FIFO_1),         /* USBHS FIFO 1 (DMA transfer request 1) */
+    [15] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI),         /* IIC0 RXI (Receive data full) */
+    [16] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI),         /* IIC0 TXI (Transmit data empty) */
+    [17] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI),         /* IIC0 TEI (Transmit end) */
+    [18] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI),         /* IIC0 ERI (Transfer error) */
+    [19] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT),         /* AGT0 INT (AGT interrupt) */
+    [20] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT),         /* AGT1 INT (AGT interrupt) */
+    [21] = BSP_PRV_IELS_ENUM(EVENT_SCI8_RXI),         /* SCI8 RXI (Received data full) */
+    [22] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TXI),         /* SCI8 TXI (Transmit data empty) */
+    [23] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TEI),         /* SCI8 TEI (Transmit end) */
+    [24] = BSP_PRV_IELS_ENUM(EVENT_SCI8_ERI),         /* SCI8 ERI (Receive error) */
+    [25] = BSP_PRV_IELS_ENUM(EVENT_SPI1_RXI),         /* SPI1 RXI (Receive buffer full) */
+    [26] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TXI),         /* SPI1 TXI (Transmit buffer empty) */
+    [27] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TEI),         /* SPI1 TEI (Transmission complete event) */
+    [28] = BSP_PRV_IELS_ENUM(EVENT_SPI1_ERI),         /* SPI1 ERI (Error) */
+};
+#endif
--- a/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/vector_data.h
+++ b/ports/renesas-ra/boards/ARDUINO_PORTENTA_C33/ra_gen/vector_data.h
@ -0,0 +1,98 @@
+/* generated vector header file - do not edit */
+#ifndef VECTOR_DATA_H
+#define VECTOR_DATA_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* Number of interrupts allocated */
+#ifndef VECTOR_DATA_IRQ_COUNT
+#define VECTOR_DATA_IRQ_COUNT    (29)
+#endif
+/* ISR prototypes */
+void sci_uart_rxi_isr(void);
+void sci_uart_txi_isr(void);
+void sci_uart_tei_isr(void);
+void sci_uart_eri_isr(void);
+void rtc_alarm_periodic_isr(void);
+void rtc_carry_isr(void);
+void r_icu_isr(void);
+void usbfs_interrupt_handler(void);
+void usbfs_resume_handler(void);
+void usbfs_d0fifo_handler(void);
+void usbfs_d1fifo_handler(void);
+void usbhs_interrupt_handler(void);
+void usbhs_d0fifo_handler(void);
+void usbhs_d1fifo_handler(void);
+void iic_master_rxi_isr(void);
+void iic_master_txi_isr(void);
+void iic_master_tei_isr(void);
+void iic_master_eri_isr(void);
+void agt_int_isr(void);
+void spi_rxi_isr(void);
+void spi_txi_isr(void);
+void spi_tei_isr(void);
+void spi_eri_isr(void);
+
+/* Vector table allocations */
+#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)0)  /* SCI9 RXI (Received data full) */
+#define SCI9_RXI_IRQn          ((IRQn_Type)0)  /* SCI9 RXI (Received data full) */
+#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)1)  /* SCI9 TXI (Transmit data empty) */
+#define SCI9_TXI_IRQn          ((IRQn_Type)1)  /* SCI9 TXI (Transmit data empty) */
+#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)2)  /* SCI9 TEI (Transmit end) */
+#define SCI9_TEI_IRQn          ((IRQn_Type)2)  /* SCI9 TEI (Transmit end) */
+#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)3)  /* SCI9 ERI (Receive error) */
+#define SCI9_ERI_IRQn          ((IRQn_Type)3)  /* SCI9 ERI (Receive error) */
+#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)4)  /* RTC ALARM (Alarm interrupt) */
+#define RTC_ALARM_IRQn          ((IRQn_Type)4)  /* RTC ALARM (Alarm interrupt) */
+#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)5)  /* RTC PERIOD (Periodic interrupt) */
+#define RTC_PERIOD_IRQn          ((IRQn_Type)5)  /* RTC PERIOD (Periodic interrupt) */
+#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)6)  /* RTC CARRY (Carry interrupt) */
+#define RTC_CARRY_IRQn          ((IRQn_Type)6)  /* RTC CARRY (Carry interrupt) */
+#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)7)  /* ICU IRQ0 (External pin interrupt 0) */
+#define ICU_IRQ0_IRQn          ((IRQn_Type)7)  /* ICU IRQ0 (External pin interrupt 0) */
+#define VECTOR_NUMBER_USBFS_INT ((IRQn_Type)8)  /* USBFS INT (USBFS interrupt) */
+#define USBFS_INT_IRQn          ((IRQn_Type)8)  /* USBFS INT (USBFS interrupt) */
+#define VECTOR_NUMBER_USBFS_RESUME ((IRQn_Type)9)  /* USBFS RESUME (USBFS resume interrupt) */
+#define USBFS_RESUME_IRQn          ((IRQn_Type)9)  /* USBFS RESUME (USBFS resume interrupt) */
+#define VECTOR_NUMBER_USBFS_FIFO_0 ((IRQn_Type)10)  /* USBFS FIFO 0 (DMA transfer request 0) */
+#define USBFS_FIFO_0_IRQn          ((IRQn_Type)10)  /* USBFS FIFO 0 (DMA transfer request 0) */
+#define VECTOR_NUMBER_USBFS_FIFO_1 ((IRQn_Type)11)  /* USBFS FIFO 1 (DMA transfer request 1) */
+#define USBFS_FIFO_1_IRQn          ((IRQn_Type)11)  /* USBFS FIFO 1 (DMA transfer request 1) */
+#define VECTOR_NUMBER_USBHS_USB_INT_RESUME ((IRQn_Type)12)  /* USBHS USB INT RESUME (USBHS interrupt) */
+#define USBHS_USB_INT_RESUME_IRQn          ((IRQn_Type)12)  /* USBHS USB INT RESUME (USBHS interrupt) */
+#define VECTOR_NUMBER_USBHS_FIFO_0 ((IRQn_Type)13)  /* USBHS FIFO 0 (DMA transfer request 0) */
+#define USBHS_FIFO_0_IRQn          ((IRQn_Type)13)  /* USBHS FIFO 0 (DMA transfer request 0) */
+#define VECTOR_NUMBER_USBHS_FIFO_1 ((IRQn_Type)14)  /* USBHS FIFO 1 (DMA transfer request 1) */
+#define USBHS_FIFO_1_IRQn          ((IRQn_Type)14)  /* USBHS FIFO 1 (DMA transfer request 1) */
+#define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type)15)  /* IIC0 RXI (Receive data full) */
+#define IIC0_RXI_IRQn          ((IRQn_Type)15)  /* IIC0 RXI (Receive data full) */
+#define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type)16)  /* IIC0 TXI (Transmit data empty) */
+#define IIC0_TXI_IRQn          ((IRQn_Type)16)  /* IIC0 TXI (Transmit data empty) */
+#define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type)17)  /* IIC0 TEI (Transmit end) */
+#define IIC0_TEI_IRQn          ((IRQn_Type)17)  /* IIC0 TEI (Transmit end) */
+#define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type)18)  /* IIC0 ERI (Transfer error) */
+#define IIC0_ERI_IRQn          ((IRQn_Type)18)  /* IIC0 ERI (Transfer error) */
+#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)19)  /* AGT0 INT (AGT interrupt) */
+#define AGT0_INT_IRQn          ((IRQn_Type)19)  /* AGT0 INT (AGT interrupt) */
+#define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)20)  /* AGT1 INT (AGT interrupt) */
+#define AGT1_INT_IRQn          ((IRQn_Type)20)  /* AGT1 INT (AGT interrupt) */
+#define VECTOR_NUMBER_SCI8_RXI ((IRQn_Type)21)  /* SCI8 RXI (Received data full) */
+#define SCI8_RXI_IRQn          ((IRQn_Type)21)  /* SCI8 RXI (Received data full) */
+#define VECTOR_NUMBER_SCI8_TXI ((IRQn_Type)22)  /* SCI8 TXI (Transmit data empty) */
+#define SCI8_TXI_IRQn          ((IRQn_Type)22)  /* SCI8 TXI (Transmit data empty) */
+#define VECTOR_NUMBER_SCI8_TEI ((IRQn_Type)23)  /* SCI8 TEI (Transmit end) */
+#define SCI8_TEI_IRQn          ((IRQn_Type)23)  /* SCI8 TEI (Transmit end) */
+#define VECTOR_NUMBER_SCI8_ERI ((IRQn_Type)24)  /* SCI8 ERI (Receive error) */
+#define SCI8_ERI_IRQn          ((IRQn_Type)24)  /* SCI8 ERI (Receive error) */
+#define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type)25)  /* SPI1 RXI (Receive buffer full) */
+#define SPI1_RXI_IRQn          ((IRQn_Type)25)  /* SPI1 RXI (Receive buffer full) */
+#define VECTOR_NUMBER_SPI1_TXI ((IRQn_Type)26)  /* SPI1 TXI (Transmit buffer empty) */
+#define SPI1_TXI_IRQn          ((IRQn_Type)26)  /* SPI1 TXI (Transmit buffer empty) */
+#define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type)27)  /* SPI1 TEI (Transmission complete event) */
+#define SPI1_TEI_IRQn          ((IRQn_Type)27)  /* SPI1 TEI (Transmission complete event) */
+#define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type)28)  /* SPI1 ERI (Error) */
+#define SPI1_ERI_IRQn          ((IRQn_Type)28)  /* SPI1 ERI (Error) */
+#ifdef __cplusplus
+}
+#endif
+#endif /* VECTOR_DATA_H */