From 64ad6764240e5cf59a8c38272226569fdbf8071d Mon Sep 17 00:00:00 2001 From: "Kwabena W. Agyeman" Date: Mon, 21 Aug 2023 20:03:52 -0700 Subject: [PATCH] mimxrt/boards: Define missing SNVS pins for all processors. Signed-off-by: "Kwabena W. Agyeman" --- ports/mimxrt/boards/MIMXRT1011_af.csv | 1 + ports/mimxrt/boards/MIMXRT1015_af.csv | 1 + ports/mimxrt/boards/MIMXRT1021_af.csv | 1 + ports/mimxrt/boards/MIMXRT1052_af.csv | 3 +++ ports/mimxrt/boards/MIMXRT1062_af.csv | 6 +++--- ports/mimxrt/boards/MIMXRT1064_af.csv | 3 +++ ports/mimxrt/boards/MIMXRT1176_af.csv | 2 ++ ports/mimxrt/boards/make-pins.py | 6 ++++-- 8 files changed, 18 insertions(+), 5 deletions(-) diff --git a/ports/mimxrt/boards/MIMXRT1011_af.csv b/ports/mimxrt/boards/MIMXRT1011_af.csv index 11dd085463..be8a9c634d 100644 --- a/ports/mimxrt/boards/MIMXRT1011_af.csv +++ b/ports/mimxrt/boards/MIMXRT1011_af.csv @@ -42,3 +42,4 @@ GPIO_SD_10,FLEXSPI_A_SCLK,LPSPI2_SDO,LPUART2_TXD,,FLEXIO1_IO16,GPIO2_IO10,,,,,,, GPIO_SD_11,FLEXSPI_A_DATA3,LPSPI2_SCK,LPUART1_RXD,,FLEXIO1_IO17,GPIO2_IO11,WDOG1_RST_B_DEB,,,,,,ALT5 GPIO_SD_12,FLEXSPI_A_DQS,LPSPI2_PCS0,LPUART1_TXD,,FLEXIO1_IO18,GPIO2_IO12,WDOG2_RST_B_DEB,,,,,,ALT5 GPIO_SD_13,FLEXSPI_B_SCLK,SAI3_RX_BCLK,ARM_CM7_TXEV,CCM_PMIC_RDY,FLEXIO1_IO19,GPIO2_IO13,SRC_BT_CFG3,,,,,,ALT5 +PMIC_ON_REQ,SNVS_LP_PMIC_ON_REQ,,,,,GPIO5_IO00,,,,,,,ALT0 diff --git a/ports/mimxrt/boards/MIMXRT1015_af.csv b/ports/mimxrt/boards/MIMXRT1015_af.csv index d988662583..0d2504733c 100644 --- a/ports/mimxrt/boards/MIMXRT1015_af.csv +++ b/ports/mimxrt/boards/MIMXRT1015_af.csv @@ -55,3 +55,4 @@ GPIO_SD_B1_08,,FLEXSPI_A_DATA0,,SAI3_TX_DATA,LPSPI2_SDO,GPIO3_IO28,,,,,,,ALT5 GPIO_SD_B1_09,,FLEXSPI_A_DATA2,,SAI3_RX_BCLK,LPSPI2_SDI,GPIO3_IO29,CCM_REF_EN_B,,,,,,ALT5 GPIO_SD_B1_10,,FLEXSPI_A_DATA1,,SAI3_RX_SYNC,LPSPI2_PCS2,GPIO3_IO30,SRC_SYSTEM_RESET,,,,,,ALT5 GPIO_SD_B1_11,,FLEXSPI_A_SS0_B,,SAI3_RX_DATA,LPSPI2_PCS3,GPIO3_IO31,SRC_EARLY_RESET,,,,,,ALT5 +PMIC_ON_REQ,SNVS_LP_PMIC_ON_REQ,,,,,GPIO5_IO01,,,,,,,ALT0 diff --git a/ports/mimxrt/boards/MIMXRT1021_af.csv b/ports/mimxrt/boards/MIMXRT1021_af.csv index 3ce38eb0b9..79ef29927c 100644 --- a/ports/mimxrt/boards/MIMXRT1021_af.csv +++ b/ports/mimxrt/boards/MIMXRT1021_af.csv @@ -92,3 +92,4 @@ GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,ENET_RX_ER,SAI3_TX_DATA,LPSPI2_SDO,GP GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA2,ENET_TX_EN,SAI3_RX_BCLK,LPSPI2_SDI,GPIO3_IO29,CCM_REF_EN_B,,,,,,ALT5 GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA1,ENET_TX_DATA0,SAI3_RX_SYNC,LPSPI2_PCS2,GPIO3_IO30,SRC_SYSTEM_RESET,,,,,,ALT5 GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_SS0_B,ENET_TX_DATA1,SAI3_RX_DATA,LPSPI2_PCS3,GPIO3_IO31,SRC_EARLY_RESET,,,,,,ALT5 +PMIC_ON_REQ,SNVS_LP_PMIC_ON_REQ,,,,,GPIO5_IO01,,,,,,,ALT0 diff --git a/ports/mimxrt/boards/MIMXRT1052_af.csv b/ports/mimxrt/boards/MIMXRT1052_af.csv index 754bf4ab7b..ee11a12cfd 100644 --- a/ports/mimxrt/boards/MIMXRT1052_af.csv +++ b/ports/mimxrt/boards/MIMXRT1052_af.csv @@ -123,3 +123,6 @@ GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,LPUART7_TXD,SAI1_TX_BCLK,LPSPI2_SOUT, GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA1,LPUART7_RXD,SAI1_TX_SYNC,LPSPI2_SIN,GPIO3_IO09,,,,,,,ALT5 GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA2,LPUART2_RXD,LPI2C2_SDA,LPSPI2_PCS2,GPIO3_IO10,,,,,,,ALT5 GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_DATA3,LPUART2_TXD,LPI2C2_SCL,LPSPI2_PCS3,GPIO3_IO11,,,,,,,ALT5 +WAKEUP,,,,,,GPIO5_IO00,,NMI_GLUE_NMI,,,,,ALT5 +PMIC_ON_REQ,SNVS_LP_PMIC_ON_REQ,,,,,GPIO5_IO01,,,,,,,ALT0 +PMIC_STBY_REQ,CCM_PMIC_VSTBY_REQ,,,,,GPIO5_IO02,,,,,,,ALT0 diff --git a/ports/mimxrt/boards/MIMXRT1062_af.csv b/ports/mimxrt/boards/MIMXRT1062_af.csv index d2f0b22023..9af33137ab 100644 --- a/ports/mimxrt/boards/MIMXRT1062_af.csv +++ b/ports/mimxrt/boards/MIMXRT1062_af.csv @@ -123,6 +123,6 @@ GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,LPUART7_TXD,SAI1_TX_BCLK,LPSPI2_SOUT, GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA1,LPUART7_RXD,SAI1_TX_SYNC,LPSPI2_SIN,GPIO3_IO09,,,,,,,ALT5 GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA2,LPUART2_RXD,LPI2C2_SDA,LPSPI2_PCS2,GPIO3_IO10,,,,,,,ALT5 GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_DATA3,LPUART2_TXD,LPI2C2_SCL,LPSPI2_PCS3,GPIO3_IO11,,,,,,,ALT5 -WAKEUP,,,,,,GPIO5_IO00,,NMI,,,,,ALT5 -PMIC_ON_REQ,SNVS_PMIC_ON_REQ,,,,,GPIO5_IO01,,,,,,,ALT0 -PMIC_STBY_REQ,CCM_PMIC_STBY_REQ,,,,,GPIO5_IO02,,,,,,,ALT0 +WAKEUP,,,,,,GPIO5_IO00,,NMI_GLUE_NMI,,,,,ALT5 +PMIC_ON_REQ,SNVS_LP_PMIC_ON_REQ,,,,,GPIO5_IO01,,,,,,,ALT0 +PMIC_STBY_REQ,CCM_PMIC_VSTBY_REQ,,,,,GPIO5_IO02,,,,,,,ALT0 diff --git a/ports/mimxrt/boards/MIMXRT1064_af.csv b/ports/mimxrt/boards/MIMXRT1064_af.csv index 074a3f69ab..bcd063ff3d 100644 --- a/ports/mimxrt/boards/MIMXRT1064_af.csv +++ b/ports/mimxrt/boards/MIMXRT1064_af.csv @@ -123,3 +123,6 @@ GPIO_SD_B1_08,USDHC2_DATA4,FLEXSPI_A_DATA0,LPUART7_TXD,SAI1_TX_BCLK,LPSPI2_SOUT, GPIO_SD_B1_09,USDHC2_DATA5,FLEXSPI_A_DATA1,LPUART7_RXD,SAI1_TX_SYNC,LPSPI2_SIN,GPIO3_IO09,,,,,,,ALT5 GPIO_SD_B1_10,USDHC2_DATA6,FLEXSPI_A_DATA2,LPUART2_RXD,LPI2C2_SDA,LPSPI2_PCS2,GPIO3_IO10,,,,,,,ALT5 GPIO_SD_B1_11,USDHC2_DATA7,FLEXSPI_A_DATA3,LPUART2_TXD,LPI2C2_SCL,LPSPI2_PCS3,GPIO3_IO11,,,,,,,ALT5 +WAKEUP,,,,,,GPIO5_IO00,,NMI_GLUE_NMI,,,,,ALT5 +PMIC_ON_REQ,SNVS_LP_PMIC_ON_REQ,,,,,GPIO5_IO01,,,,,,,ALT0 +PMIC_STBY_REQ,CCM_PMIC_VSTBY_REQ,,,,,GPIO5_IO02,,,,,,,ALT0 diff --git a/ports/mimxrt/boards/MIMXRT1176_af.csv b/ports/mimxrt/boards/MIMXRT1176_af.csv index 21fd2a2417..5e99a49003 100644 --- a/ports/mimxrt/boards/MIMXRT1176_af.csv +++ b/ports/mimxrt/boards/MIMXRT1176_af.csv @@ -107,6 +107,8 @@ GPIO_LPSR_13,JTAG_MUX_MOD,MIC_BITSTREAM1,PIT2_TRIGGER1,,,GPIO6_IO13,,SAI4_RX_DAT GPIO_LPSR_14,JTAG_MUX_TCK,MIC_BITSTREAM2,PIT2_TRIGGER2,,,GPIO6_IO14,,SAI4_RX_BCLK,LPSPI5_SOUT,,GPIO12_IO14,,, GPIO_LPSR_15,JTAG_MUX_TMS,MIC_BITSTREAM3,PIT2_TRIGGER3,,,GPIO6_IO15,,SAI4_RX_SYNC,LPSPI5_SIN,,GPIO12_IO15,,, WAKEUP_DIG,,,,,,GPIO13_IO00,,NMI_GLUE_NMI,,,,,, +PMIC_ON_REQ_DIG,SNVS_LP_PMIC_ON_REQ,,,,,GPIO13_IO01,,,,,,,, +PMIC_STBY_REQ_DIG,CCM_PMIC_VSTBY_REQ,,,,,GPIO13_IO02,,,,,,,, GPIO_DISP_B1_00,VIDEO_MUX_LCDIF_CLK,ENET_1G_RX_EN,,TMR1_TIMER0,XBAR1_INOUT26,GPIO4_IO21,,,ENET_QOS_RX_EN,,GPIO10_IO21,,, GPIO_DISP_B1_01,VIDEO_MUX_LCDIF_ENABLE,ENET_1G_RX_CLK,ENET_1G_RX_ER,TMR1_TIMER1,XBAR1_INOUT27,GPIO4_IO22,,,ENET_QOS_RX_CLK,ENET_QOS_RX_ER,GPIO10_IO22,,, GPIO_DISP_B1_02,VIDEO_MUX_LCDIF_HSYNC,ENET_1G_RX_DATA00,LPI2C3_SCL,TMR1_TIMER2,XBAR1_INOUT28,GPIO4_IO23,,,ENET_QOS_RX_DATA00,LPUART1_TXD,GPIO10_IO23,,, diff --git a/ports/mimxrt/boards/make-pins.py b/ports/mimxrt/boards/make-pins.py index 51ae9eb717..5795e2f042 100644 --- a/ports/mimxrt/boards/make-pins.py +++ b/ports/mimxrt/boards/make-pins.py @@ -25,8 +25,8 @@ regexes = [ r"IOMUXC_(?PGPIO_DISP_B\d_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", r"IOMUXC_(?PGPIO_LPSR_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", r"IOMUXC_[SNVS_]*(?PWAKEUP[_DIG]*)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", - r"IOMUXC_SNVS_(?PPMIC_ON_REQ)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", - r"IOMUXC_SNVS_(?PPMIC_STBY_REQ)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_[SNVS_]*(?PPMIC_ON_REQ[_DIG]*)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_[SNVS_]*(?PPMIC_STBY_REQ[_DIG]*)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", r"IOMUXC_(?PGPIO_SNVS_\d\d_DIG)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", ] @@ -152,7 +152,9 @@ class Pin(object): "WAKEUP": "PIN_SNVS", "WAKEUP_DIG": "PIN_SNVS", "PMIC_ON_REQ": "PIN_SNVS", + "PMIC_ON_REQ_DIG": "PIN_SNVS", "PMIC_STBY_REQ": "PIN_SNVS", + "PMIC_STBY_REQ_DIG": "PIN_SNVS", } print(