mimxrt/boards: Add board files for MIMXRT1015 and MIMXRT1015_EVK.

OCOTP_Init() has been removed from mphalport.c.  The library files are
missing for the MIMXRT1015, and for just reading the OCOTP the Init is not
required.

ports/mimxrt/Makefile

@@ -186,7 +186,6 @@ SRC_HAL_IMX_C += \
 	$(MCU_DIR)/drivers/fsl_lpspi.c \
 	$(MCU_DIR)/drivers/fsl_lpspi_edma.c \
 	$(MCU_DIR)/drivers/fsl_lpuart.c \
-	$(MCU_DIR)/drivers/fsl_ocotp.c \
 	$(MCU_DIR)/drivers/fsl_pit.c \
 	$(MCU_DIR)/drivers/fsl_pwm.c \
 	$(MCU_DIR)/drivers/fsl_snvs_lp.c \

ports/mimxrt/boards/MIMXRT1015.ld

@@ -0,0 +1,38 @@
+/* Memory configuration */
+#if defined MICROPY_HW_FLASH_RESERVED
+reserved_size = MICROPY_HW_FLASH_RESERVED;
+#endif
+
+#if MICROPY_HW_FLASH_TYPE == qspi_nor
+flash_start         = 0x60000000;
+#else
+#error Unknown MICROPY_HW_FLASH_TYPE
+#endif
+flash_size          = MICROPY_HW_FLASH_SIZE;
+flash_end           = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size));
+flash_config_start  = flash_start;
+flash_config_size   = 0x00001000;
+ivt_start           = flash_start + 0x00001000;
+ivt_size            = 0x00001000;
+interrupts_start    = flash_start + 0x00002000;
+interrupts_size     = 0x00000400;
+text_start          = flash_start + 0x00002400;
+vfs_start           = flash_start + 0x00100000;
+text_size           = ((vfs_start) - (text_start));
+vfs_size            = ((flash_end) - (vfs_start));
+itcm_start          = 0x00000000;
+itcm_size           = 0x00008000;
+dtcm_start          = 0x20000000;
+dtcm_size           = 0x00008000;
+ocrm_start          = 0x20200000;
+ocrm_size           = 0x00010000;
+
+/* 24kiB stack. */
+__stack_size__ = 0x5000;
+_estack = __StackTop;
+_sstack = __StackLimit;
+
+/* Use second OCRAM bank for GC heap. */
+/* Use all OCRAM for the GC heap. */
+_gc_heap_start = ORIGIN(m_ocrm);
+_gc_heap_end = ORIGIN(m_ocrm) + LENGTH(m_ocrm);

ports/mimxrt/boards/MIMXRT1015_EVK/board.json

@@ -0,0 +1,23 @@
+{
+    "deploy": [
+        "../deploy_mimxrt.md"
+    ],
+    "docs": "",
+    "features": [
+        "MicroSD",
+        "MicroUSB",
+        "Microphone",
+        "AudioCodec",
+        "CAN",
+        "OpenSDA",
+        "JLink"
+    ],
+    "images": [
+        "MIMXRT1015-EVK-TOP.jpg"
+    ],
+    "mcu": "mimxrt",
+    "product": "MIMXRT1015_EVK",
+    "thumbnail": "",
+    "url": "https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1015-evaluation-kit:MIMXRT1015-EVK",
+    "vendor": "NXP"
+}

ports/mimxrt/boards/MIMXRT1015_EVK/clock_config.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ                         24000000U  /*!< Board xtal0 frequency in Hz */
+
+#define BOARD_XTAL32K_CLK_HZ                          32768U  /*!< Board xtal32k frequency in Hz */
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK             500000000U  /*!< Core clock frequency: 500000000Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT               500000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT         32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK                  0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M                     1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M                    24000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK          500000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT           30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT           125000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ      62500000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT               125000000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT             60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT             105600000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK                   63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT            62500000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT              63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1                 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2                 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3                 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT            30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT          0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT             117333333UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT              80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK                0UL
+
+/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
+/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
+ */
+extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */

ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h

@@ -0,0 +1,84 @@
+#define MICROPY_HW_BOARD_NAME "i.MX RT1015 EVK"
+#define MICROPY_HW_MCU_NAME   "MIMXRT1015DAF5A"
+
+// i.MX RT1015 EVK has 3 board LED
+// Todo: think about replacing the define with searching in the generated pins?
+#define MICROPY_HW_LED1_PIN (pin_GPIO_SD_B1_00)
+#define MICROPY_HW_LED2_PIN (pin_GPIO_SD_B1_01)
+#define MICROPY_HW_LED3_PIN (pin_GPIO_SD_B1_02)
+#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
+#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
+
+#define MICROPY_HW_NUM_PIN_IRQS (3 * 32)
+
+// Define mapping logical UART # to hardware UART #
+// RX/TX      HW-UART    Logical UART
+// DEBUG USB  LPUART1 -> 0
+// D3/D5      LPUART1
+// D0/D1      LPUART2 -> 1
+// D6/D9      LPUART3 -> 2
+// A0/A1      LPUART4 -> 5
+
+#define MICROPY_HW_UART_NUM     (sizeof(uart_index_table) / sizeof(uart_index_table)[0])
+#define MICROPY_HW_UART_INDEX   { 1, 4, 3 }
+
+#define IOMUX_TABLE_UART \
+    { IOMUXC_GPIO_AD_B0_06_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_07_LPUART1_RX }, \
+    { 0 }, { 0 }, \
+    { IOMUXC_GPIO_AD_B0_14_LPUART3_TX }, { IOMUXC_GPIO_AD_B0_15_LPUART3_RX }, \
+    { IOMUXC_GPIO_EMC_32_LPUART4_TX },   { IOMUXC_GPIO_EMC_33_LPUART4_RX }, \
+
+#define MICROPY_HW_SPI_INDEX { 1 }
+
+#define IOMUX_TABLE_SPI \
+    { IOMUXC_GPIO_AD_B0_10_LPSPI1_SCK }, { IOMUXC_GPIO_AD_B0_11_LPSPI1_PCS0 }, \
+    { IOMUXC_GPIO_AD_B0_12_LPSPI1_SDO }, { IOMUXC_GPIO_AD_B0_13_LPSPI1_SDI }, \
+    { 0 }
+
+#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx }
+
+#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx }
+
+// Define mapping hardware I2C # to logical I2C #
+// SDA/SCL  HW-I2C    Logical I2C
+// D14/D15  LPI2C4 ->    0
+// A4/A5    LPI2C1 ->    1
+// D0/D1    LPI2C2 ->    2
+
+#define MICROPY_HW_I2C_INDEX   { 1, 2 }
+
+#define IOMUX_TABLE_I2C \
+    { IOMUXC_GPIO_AD_B1_14_LPI2C1_SCL }, { IOMUXC_GPIO_AD_B1_15_LPI2C1_SDA }, \
+    { IOMUXC_GPIO_EMC_19_LPI2C2_SCL },   { IOMUXC_GPIO_EMC_18_LPI2C2_SDA },
+
+#define MICROPY_PY_MACHINE_I2S (1)
+#define MICROPY_HW_I2S_NUM (1)
+#define I2S_CLOCK_MUX { 0, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux }
+#define I2S_CLOCK_PRE_DIV { 0, kCLOCK_Sai1PreDiv, kCLOCK_Sai2PreDiv }
+#define I2S_CLOCK_DIV { 0, kCLOCK_Sai1Div, kCLOCK_Sai2Div }
+#define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir }
+#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx }
+#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx }
+
+#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \
+    { \
+        .hw_id = _hwid, \
+        .fn = _fn, \
+        .mode = _mode, \
+        .name = MP_QSTR_##_pin, \
+        .iomux = {_iomux}, \
+    }
+
+#define I2S_GPIO_MAP \
+    { \
+        I2S_GPIO(1, MCK, TX, GPIO_EMC_20, IOMUXC_GPIO_EMC_20_SAI1_MCLK), \
+        I2S_GPIO(1, SCK, RX, GPIO_EMC_19, IOMUXC_GPIO_EMC_19_SAI1_RX_BCLK), \
+        I2S_GPIO(1, WS, RX, GPIO_EMC_18, IOMUXC_GPIO_EMC_18_SAI1_RX_SYNC), \
+        I2S_GPIO(1, SD, RX, GPIO_EMC_21, IOMUXC_GPIO_EMC_21_SAI1_RX_DATA00),  \
+        I2S_GPIO(1, SCK, TX, GPIO_EMC_26, IOMUXC_GPIO_EMC_26_SAI1_TX_BCLK), \
+        I2S_GPIO(1, WS, TX, GPIO_EMC_27, IOMUXC_GPIO_EMC_27_SAI1_TX_SYNC),  \
+        I2S_GPIO(1, SD, TX, GPIO_EMC_25, IOMUXC_GPIO_EMC_25_SAI1_TX_DATA00), \
+    }
+
+#define MICROPY_BOARD_ROOT_POINTERS \
+    struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM];

ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.mk

@@ -0,0 +1,9 @@
+MCU_SERIES = MIMXRT1015
+MCU_VARIANT = MIMXRT1015DAF5A
+
+MICROPY_FLOAT_IMPL = single
+MICROPY_PY_MACHINE_SDCARD = 0
+MICROPY_HW_FLASH_TYPE ?= qspi_nor
+MICROPY_HW_FLASH_SIZE ?= 0x1000000  # 16MB
+
+MICROPY_BOOT_BUFFER_SIZE = (32 * 1024)

ports/mimxrt/boards/MIMXRT1015_EVK/pins.csv

@@ -0,0 +1,41 @@
+D0,GPIO_EMC_33
+D1,GPIO_EMC_32
+D2,GPIO_EMC_20
+D3,GPIO_EMC_26
+D4,GPIO_EMC_34
+D5,GPIO_EMC_27
+D6,GPIO_AD_B1_11
+D7,GPIO_AD_B0_15
+D8,GPIO_EMC_21
+D9,GPIO_EMC_22
+D10,GPIO_AD_B0_11
+D11,GPIO_AD_B0_12
+D12,GPIO_AD_B0_13
+D13,GPIO_AD_B0_10
+D14,GPIO_AD_B1_15
+D15,GPIO_AD_B1_14
+A0,GPIO_AD_B1_13
+A1,GPIO_AD_B0_14
+A2,GPIO_AD_B1_12
+A3,GPIO_AD_B1_10
+A4,GPIO_AD_B1_15
+A5,GPIO_AD_B1_14
+RX,GPIO_EMC_33
+TX,GPIO_EMC_32
+SDA,GPIO_AD_B1_15
+SCL,GPIO_AD_B1_14
+SCK,GPIO_AD_B0_10
+SDI,GPIO_AD_B0_13
+SDO,GPIO_AD_B0_12
+CS,GPIO_AD_B0_11
+LED1,GPIO_SD_B1_00
+LED2,GPIO_SD_B1_01
+LED3,GPIO_SD_B1_02
+BUTTON,GPIO_EMC_09
+MCK,GPIO_EMC_20
+SCK_RX,GPIO_EMC_19
+WS_RX,GPIO_EMC_18
+SD_RX,GPIO_EMC_21
+SCK_TX,GPIO_EMC_26
+WS_TX,GPIO_EMC_27
+SD_TX,GPIO_EMC_25

ports/mimxrt/boards/MIMXRT1015_af.csv

@@ -0,0 +1,57 @@
+Pad,ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ADC,ACMP,Default
+GPIO_AD_B0_00,JTAG_TMS,,,,,GPIO1_IO00,,GPT1_COMPARE1,,,,,ALT0
+GPIO_AD_B0_01,JTAG_TCK,,,,,GPIO1_IO01,,GPT1_CAPTURE2,,,,,ALT0
+GPIO_AD_B0_02,JTAG_MOD,,,,,GPIO1_IO02,,GPT1_CAPTURE1,,,,,ALT0
+GPIO_AD_B0_03,JTAG_TDI,,WDOG1_B,SAI1_MCLK,,GPIO1_IO03,USB_OTG1_OC,CCM_PMIC_RDY,,,,,ALT0
+GPIO_AD_B0_04,JTAG_TDO,,,,,GPIO1_IO04,USB_OTG1_PWR,EWM_OUT_B,,,,,ALT0
+GPIO_AD_B0_05,JTAG_TRSTB,,,,,GPIO1_IO05,USB_OTG1_ID,ARM_NMI,,,,,ALT0
+GPIO_AD_B0_06,PIT_TRIGGER0,MQS_RIGHT,LPUART1_TXD,,,GPIO1_IO06,REF_32K_OUT,,,,,,ALT5
+GPIO_AD_B0_07,PIT_TRIGGER1,MQS_LEFT,LPUART1_RXD,,,GPIO1_IO07,REF_24M_OUT,,,,,,ALT5
+GPIO_AD_B0_08,,,LPUART1_CTS_B,KPP_COL0,,GPIO1_IO08,ARM_CM7_TXEV,,,,,,ALT5
+GPIO_AD_B0_09,,,LPUART1_RTS_B,KPP_ROW0,CSU_CSU_INT_DEB,GPIO1_IO09,ARM_CM7_RXEV,,,,,,ALT5
+GPIO_AD_B0_10,,LPSPI1_SCK,,KPP_COL1,,GPIO1_IO10,ARM_TRACE_CLK,,,,,,ALT5
+GPIO_AD_B0_11,,LPSPI1_PCS0,,KPP_ROW1,,GPIO1_IO11,ARM_TRACE_SWO,,,,,,ALT5
+GPIO_AD_B0_12,,LPSPI1_SDO,LPUART3_CTS_B,KPP_COL2,,GPIO1_IO12,ARM_TRACE0,SNVS_VIO_5_CTL,,,ADC1_IN0,,ALT5
+GPIO_AD_B0_13,,LPSPI1_SDI,LPUART3_RTS_B,KPP_ROW2,,GPIO1_IO13,ARM_CM7_TRACE01,SNVS_VIO_5_B,,,,,ALT5
+GPIO_AD_B0_14,,,LPUART3_TXD,KPP_COL3,,GPIO1_IO14,ARM_CM7_TRACE02,WDOG1_ANY,,,ADC1_IN1,,ALT5
+GPIO_AD_B0_15,,,LPUART3_RXD,KPP_ROW3,,GPIO1_IO15,ARM_CM7_TRACE03,,,,ADC1_IN2,,ALT5
+GPIO_AD_B1_10,USB_OTG1_PWR,FLEXPWM1_PWM2_A,LPUART4_TXD,,FLEXIO1_D05,GPIO1_IO26,GPT2_CAPTURE1,,,,ADC1_IN10,,ALT5
+GPIO_AD_B1_11,USB_OTG1_ID,FLEXPWM1_PWM2_B,LPUART4_RXD,,FLEXIO1_D04,GPIO1_IO27,GPT2_COMPARE1,,,,ADC1_IN11,,ALT5
+GPIO_AD_B1_12,USB_OTG1_OC,ACMP1_OUT,,,FLEXIO1_D03,GPIO1_IO28,FLEXPWM1_PWM3_A,,,,ADC1_IN12,ACMP1_OUT,ALT5
+GPIO_AD_B1_13,LPI2C1_HREQ,ACMP2_OUT,,,FLEXIO1_D02,GPIO1_IO29,FLEXPWM1_PWM3_B,,,,ADC1_IN13,ACMP2_OUT,ALT5
+GPIO_AD_B1_14,LPI2C1_SCL,ACMP3_OUT,,,FLEXIO1_D01,GPIO1_IO30,,,,,ADC1_IN14,ACMP3_OUT,ALT5
+GPIO_AD_B1_15,LPI2C1_SDA,ACMP4_OUT,,,FLEXIO1_D00,GPIO1_IO31,,,,,ADC1_IN15,ACMP4_OUT,ALT5
+GPIO_EMC_04,,XBAR_INOUT04,SPDIF_OUT,SAI2_TX_BCLK,FLEXIO1_D16,GPIO2_IO04,,SJC_JTAG_ACT,,,,,ALT5
+GPIO_EMC_05,,XBAR_INOUT05,SPDIF_IN,SAI2_TX_SYNC,FLEXIO1_D17,GPIO2_IO05,,SJC_DE_B,,,,,ALT5
+GPIO_EMC_06,,XBAR_INOUT06,LPUART3_TXD,SAI2_TX_DATA,FLEXIO1_D18,GPIO2_IO06,,,,,,,ALT5
+GPIO_EMC_07,,XBAR_INOUT07,LPUART3_RXD,SAI2_RX_SYNC,FLEXIO1_D19,GPIO2_IO07,,,,,,,ALT5
+GPIO_EMC_08,,XBAR_INOUT08,,SAI2_RX_DATA,FLEXIO1_D20,GPIO2_IO08,,,,,,,ALT5
+GPIO_EMC_09,,XBAR_INOUT09,,SAI2_RX_BCLK,FLEXIO1_D21,GPIO2_IO09,,,,,,,ALT5
+GPIO_EMC_16,,,MQS_RIGHT,SAI2_MCLK,,GPIO2_IO16,SRC_BOOT_MODE0,,,,,,ALT5
+GPIO_EMC_17,,,MQS_LEFT,SAI3_MCLK,,GPIO2_IO17,SRC_BOOT_MODE1,,,,,,ALT5
+GPIO_EMC_18,,XBAR_INOUT16,LPI2C2_SDA,SAI1_RX_SYNC,FLEXIO1_D22,GPIO2_IO18,SRC_BT_CFG0,,,,,,ALT5
+GPIO_EMC_19,,XBAR_INOUT17,LPI2C2_SCL,SAI1_RX_BCLK,FLEXIO1_D23,GPIO2_IO19,SRC_BT_CFG1,,,,,,ALT5
+GPIO_EMC_20,,FLEXPWM1_PWM3_A,LPUART2_CTS_B,SAI1_MCLK,FLEXIO1_D24,GPIO2_IO20,SRC_BT_CFG2,,,,,,ALT5
+GPIO_EMC_21,,FLEXPWM1_PWM3_B,LPUART2_RTS_B,SAI1_RX_DATA0,FLEXIO1_D25,GPIO2_IO21,SRC_BT_CFG3,,,,,,ALT5
+GPIO_EMC_22,,FLEXPWM1_PWM2_A,LPUART2_TXD,SAI1_TX_DATA3,FLEXIO1_D26,GPIO2_IO22,SRC_BT_CFG4,,,,,,ALT5
+GPIO_EMC_23,,FLEXPWM1_PWM2_B,LPUART2_RXD,SAI1_TX_DATA2,FLEXIO1_D27,GPIO2_IO23,SRC_BT_CFG5,,,,,,ALT5
+GPIO_EMC_24,,FLEXPWM1_PWM1_A,,SAI1_TX_DATA1,FLEXIO1_D28,GPIO2_IO24,SRC_BT_CFG6,,,,,,ALT5
+GPIO_EMC_25,,FLEXPWM1_PWM1_B,,SAI1_TX_DATA0,FLEXIO1_D29,GPIO2_IO25,SRC_BT_CFG7,,,,,,ALT5
+GPIO_EMC_26,,FLEXPWM1_PWM0_A,,SAI1_TX_BCLK,FLEXIO1_D30,GPIO2_IO26,SRC_BT_CFG8,,,,,,ALT5
+GPIO_EMC_27,,FLEXPWM1_PWM0_B,,SAI1_TX_SYNC,FLEXIO1_D31,GPIO2_IO27,SRC_BT_CFG9,,,,,,ALT5
+GPIO_EMC_32,,TMR1_TIMER0,LPUART4_TXD,SAI3_TX_DATA,,GPIO3_IO00,,REF_24M_OUT,,,,,ALT5
+GPIO_EMC_33,,TMR1_TIMER1,LPUART4_RXD,SAI3_TX_BCLK,,GPIO3_IO01,,,,,,,ALT5
+GPIO_EMC_34,,TMR1_TIMER2,,SAI3_TX_SYNC,,GPIO3_IO02,,,,,,,ALT5
+GPIO_EMC_35,,TMR1_TIMER3,,,,GPIO3_IO03,,,,,,,ALT5
+GPIO_SD_B1_00,,FLEXSPI_B_DATA3,,XBAR_INOUT10,,GPIO3_IO20,,,,,,,ALT5
+GPIO_SD_B1_01,,FLEXSPI_B_SCLK,,FLEXSPI_A_SS1_B,,GPIO3_IO21,,,,,,,ALT5
+GPIO_SD_B1_02,,FLEXSPI_B_DATA0,,,,GPIO3_IO22,CCM_CLKO1,,,,,,ALT5
+GPIO_SD_B1_03,,FLEXSPI_B_DATA2,,,,GPIO3_IO23,CCM_CLKO2,,,,,,ALT5
+GPIO_SD_B1_04,,FLEXSPI_B_DATA1,,,EWM_OUT_B,GPIO3_IO24,CCM_WAIT,,,,,,ALT5
+GPIO_SD_B1_05,,FLEXSPI_A_DQS,,SAI3_MCLK,FLEXSPI_B_SS0_B,GPIO3_IO25,CCM_PMIC_RDY,,,,,,ALT5
+GPIO_SD_B1_06,,FLEXSPI_A_DATA3,,SAI3_TX_BCLK,LPSPI2_PCS0,GPIO3_IO26,CCM_STOP,,,,,,ALT5
+GPIO_SD_B1_07,,FLEXSPI_A_SCLK,,SAI3_TX_SYNC,LPSPI2_SCK,GPIO3_IO27,,,,,,,ALT5
+GPIO_SD_B1_08,,FLEXSPI_A_DATA0,,SAI3_TX_DATA,LPSPI2_SDO,GPIO3_IO28,,,,,,,ALT5
+GPIO_SD_B1_09,,FLEXSPI_A_DATA2,,SAI3_RX_BCLK,LPSPI2_SDI,GPIO3_IO29,CCM_REF_EN_B,,,,,,ALT5
+GPIO_SD_B1_10,,FLEXSPI_A_DATA1,,SAI3_RX_SYNC,LPSPI2_PCS2,GPIO3_IO30,SRC_SYSTEM_RESET,,,,,,ALT5
+GPIO_SD_B1_11,,FLEXSPI_A_SS0_B,,SAI3_RX_DATA,LPSPI2_PCS3,GPIO3_IO31,SRC_EARLY_RESET,,,,,,ALT5

ports/mimxrt/boards/make-flexram-config.py

@@ -172,6 +172,7 @@ def mimxrt_106x_gen_code(extract_dict):
 def main(defines_file, features_file, ld_script, controller):
     dispatcher = {
         "MIMXRT1011": (mimxrt_default_parser, mimxrt_default_gen_code),
+        "MIMXRT1015": (mimxrt_default_parser, mimxrt_default_gen_code),
         "MIMXRT1021": (mimxrt_default_parser, mimxrt_default_gen_code),
         "MIMXRT1052": (mimxrt_default_parser, mimxrt_default_gen_code),
         "MIMXRT1062": (mimxrt_default_parser, mimxrt_106x_gen_code),

ports/mimxrt/mphalport.c

@@ -33,7 +33,12 @@
 #include "ticks.h"
 #include "tusb.h"
 #include "fsl_snvs_lp.h"
+
+#if FSL_COMMON_DRIVER_VERSION != 0x020001
 #include "fsl_ocotp.h"
+#else
+void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz);
+#endif
 
 #include CPU_HEADER_H
 
@@ -124,7 +129,6 @@ uint64_t mp_hal_time_ns(void) {
 // MAC address
 
 void mp_hal_get_unique_id(uint8_t id[]) {
-    OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk));
     *(uint32_t *)&id[0] = OCOTP->CFG0;
     *(uint32_t *)&id[4] = OCOTP->CFG1;
 }