diff --git a/ports/mimxrt/Makefile b/ports/mimxrt/Makefile index c65e2a433c..d9c150525d 100644 --- a/ports/mimxrt/Makefile +++ b/ports/mimxrt/Makefile @@ -101,13 +101,12 @@ SRC_ETH_C += \ hal/phy/device/phydp83848/fsl_phydp83848.c \ hal/phy/device/phyksz8081/fsl_phyksz8081.c \ hal/phy/device/phylan8720/fsl_phylan8720.c \ + hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c \ hal/phy/mdio/enet/fsl_enet_mdio.c endif # NXP SDK sources SRC_HAL_IMX_C += \ - $(MCU_DIR)/drivers/fsl_adc.c \ - $(MCU_DIR)/drivers/fsl_cache.c \ $(MCU_DIR)/drivers/fsl_clock.c \ $(MCU_DIR)/drivers/fsl_common.c \ $(MCU_DIR)/drivers/fsl_dmamux.c \ @@ -124,10 +123,9 @@ SRC_HAL_IMX_C += \ $(MCU_DIR)/drivers/fsl_pwm.c \ $(MCU_DIR)/drivers/fsl_sai.c \ $(MCU_DIR)/drivers/fsl_snvs_lp.c \ - $(MCU_DIR)/drivers/fsl_trng.c \ $(MCU_DIR)/drivers/fsl_wdog.c \ - $(MCU_DIR)/system_$(MCU_SERIES).c \ - hal/fsl_flexspi_nor_boot.c \ + $(MCU_DIR)/system_$(MCU_SERIES)$(MCU_CORE).c \ + $(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \ ifeq ($(MICROPY_HW_SDRAM_AVAIL),1) SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_semc.c @@ -137,11 +135,29 @@ ifeq ($(MICROPY_PY_MACHINE_SDCARD),1) SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_usdhc.c endif -ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064)) +ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176)) SRC_HAL_IMX_C += \ $(MCU_DIR)/drivers/fsl_qtmr.c endif +ifeq ($(MCU_SERIES), MIMXRT1176) +INC += -I$(TOP)/$(MCU_DIR)/drivers/cm7 + +SRC_HAL_IMX_C += \ + $(MCU_DIR)/drivers/cm7/fsl_cache.c \ + $(MCU_DIR)/drivers/fsl_dcdc.c \ + $(MCU_DIR)/drivers/fsl_pmu.c \ + $(MCU_DIR)/drivers/fsl_common_arm.c \ + $(MCU_DIR)/drivers/fsl_anatop_ai.c \ + $(MCU_DIR)/drivers/fsl_caam.c \ + $(MCU_DIR)/drivers/fsl_lpadc.c +else +SRC_HAL_IMX_C += \ + $(MCU_DIR)/drivers/fsl_adc.c \ + $(MCU_DIR)/drivers/fsl_cache.c \ + $(MCU_DIR)/drivers/fsl_trng.c +endif + # C source files SRC_C += \ board_init.c \ @@ -243,7 +259,7 @@ SUPPORTS_HARDWARE_FP_DOUBLE = 0 # Assembly source files SRC_SS = \ - $(MCU_DIR)/gcc/startup_$(MCU_SERIES).S \ + $(MCU_DIR)/gcc/startup_$(MCU_SERIES)$(MCU_CORE).S \ hal/resethandler_MIMXRT10xx.S SRC_S += shared/runtime/gchelper_m3.s \ @@ -279,11 +295,11 @@ CFLAGS += \ -D__STARTUP_INITIALIZE_RAMFUNCTION \ -DBOARD_$(BOARD) \ -DBOARD_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \ - -DCFG_TUSB_MCU=OPT_MCU_MIMXRT10XX \ + -DCFG_TUSB_MCU=OPT_MCU_MIMXRT \ -DCLOCK_CONFIG_H='' \ - -DCPU_$(MCU_SERIES) \ + -DCPU_$(MCU_SERIES)$(MCU_CORE) \ -DCPU_$(MCU_VARIANT) \ - -DCPU_HEADER_H='<$(MCU_SERIES).h>' \ + -DCPU_HEADER_H='<$(MCU_SERIES)$(MCU_CORE).h>' \ -DFSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1 \ -DI2C_RETRY_TIMES=1000000 \ -DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \ @@ -438,9 +454,8 @@ $(HEADER_BUILD)/qstrdefs.generated.h: $(BOARD_DIR)/mpconfigboard.h $(GEN_FLEXRAM_CONFIG_SRC): $(ECHO) "Create $@" - $(Q)$(PYTHON) $(MAKE_FLEXRAM_LD) -d $(TOP)/$(MCU_DIR)/$(MCU_SERIES).h \ - -f $(TOP)/$(MCU_DIR)/$(MCU_SERIES)_features.h -l boards/$(MCU_SERIES).ld -c $(MCU_SERIES) > $(GEN_FLEXRAM_CONFIG_SRC) - + $(Q)$(PYTHON) $(MAKE_FLEXRAM_LD) -d $(TOP)/$(MCU_DIR)/$(MCU_SERIES)$(MCU_CORE).h \ + -f $(TOP)/$(MCU_DIR)/$(MCU_SERIES)$(MCU_CORE)_features.h -l boards/$(MCU_SERIES).ld -c $(MCU_SERIES) > $(GEN_FLEXRAM_CONFIG_SRC) # Use a pattern rule here so that make will only call make-pins.py once to make # both pins_gen.c and pins.h diff --git a/ports/mimxrt/board_init.c b/ports/mimxrt/board_init.c index d0625aac37..78001862f0 100644 --- a/ports/mimxrt/board_init.c +++ b/ports/mimxrt/board_init.c @@ -40,10 +40,15 @@ #include CLOCK_CONFIG_H #include "modmachine.h" - const uint8_t dcd_data[] = { 0x00 }; +void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn); + void board_init(void) { + // Clean and enable cache + SCB_CleanDCache(); + SCB_EnableDCache(); + SCB_EnableICache(); // Init clock BOARD_BootClockRUN(); SystemCoreClockUpdate(); @@ -51,7 +56,7 @@ void board_init(void) { // Enable IOCON clock CLOCK_EnableClock(kCLOCK_Iomuxc); - // ------------- SDRAM ------------ // + // SDRAM #if MICROPY_HW_SDRAM_AVAIL mimxrt_sdram_init(); #endif @@ -59,32 +64,8 @@ void board_init(void) { // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); - // ------------- USB0 ------------- // - // Clock - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); - - #ifdef USBPHY1 - USBPHY_Type *usb_phy = USBPHY1; - #else - USBPHY_Type *usb_phy = USBPHY; - #endif - - // Enable PHY support for Low speed device + LS via FS Hub - usb_phy->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK | USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; - - // Enable all power for normal operation - usb_phy->PWD = 0; - - // TX Timing - uint32_t phytx = usb_phy->TX; - phytx &= ~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK); - phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06); - usb_phy->TX = phytx; - - // USB1 - // CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U); - // CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U); + // USB0 + usb_phy0_init(0b0111, 0b0110, 0b0110); // Configure nominal values for D_CAL and TXCAL45DP/DN // ADC machine_adc_init(); @@ -99,6 +80,49 @@ void board_init(void) { #endif // RTC machine_rtc_start(); + + // OCRAM wait states (discarded, but code kept) + #if 0 + MECC1->PIPE_ECC_EN = + MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) | + MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) | + MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) | + MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1); + + MECC2->PIPE_ECC_EN = + MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(1) | + MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(1) | + MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(1) | + MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(1); + + FLEXRAM->FLEXRAM_CTRL = + FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(1) | + FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(1) | + FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(1) | + FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(1); + #endif +} + +void usb_phy0_init(uint8_t d_cal, uint8_t txcal45dp, uint8_t txcal45dn) { + #ifdef USBPHY1 + USBPHY_Type *usb_phy = USBPHY1; + #else + USBPHY_Type *usb_phy = USBPHY; + #endif + + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); + + #if defined(MIMXRT117x_SERIES) + usb_phy->TRIM_OVERRIDE_EN = USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(1) | + USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(1) | + USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(1) | + USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(1) | + USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(1); // Enable override for D_CAL and TXCAL45DP/DN + #endif + usb_phy->PWD = 0U; // Set all bits in PWD register to normal operation + usb_phy->TX = ((usb_phy->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(d_cal) | USBPHY_TX_TXCAL45DP(txcal45dp) | USBPHY_TX_TXCAL45DM(txcal45dn))); // Configure values for D_CAL and TXCAL45DP/DN } void USB_OTG1_IRQHandler(void) { diff --git a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h index 6c9aaff96a..73055526a0 100644 --- a/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1010_EVK/mpconfigboard.h @@ -54,6 +54,7 @@ #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx } #define I2S_WM8960_RX_MODE (1) +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ diff --git a/ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h index adb97fd24e..f37ba824f4 100644 --- a/ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1015_EVK/mpconfigboard.h @@ -59,6 +59,7 @@ #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir } #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ diff --git a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h index 762499f6c2..9a9befa126 100644 --- a/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1020_EVK/mpconfigboard.h @@ -73,6 +73,7 @@ #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir } #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ @@ -158,8 +159,8 @@ #define ENET_PHY_OPS phyksz8081_ops // Etherner PIN definitions -#define ENET_RESET_PIN pin_GPIO_AD_B0_04 -#define ENET_INT_PIN pin_GPIO_AD_B1_06 +#define ENET_RESET_PIN &pin_GPIO_AD_B0_04 +#define ENET_INT_PIN &pin_GPIO_AD_B1_06 #define IOMUX_TABLE_ENET \ { IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1, 0xB0E9u }, \ diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h index f2a7b0b78b..9cc740b1a6 100644 --- a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h @@ -62,6 +62,7 @@ #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } #define I2S_WM8960_RX_MODE (1) +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ @@ -148,8 +149,8 @@ #define ENET_PHY_OPS phyksz8081_ops // Etherner PIN definitions -#define ENET_RESET_PIN pin_GPIO_AD_B0_09 -#define ENET_INT_PIN pin_GPIO_AD_B0_10 +#define ENET_RESET_PIN &pin_GPIO_AD_B0_09 +#define ENET_INT_PIN &pin_GPIO_AD_B0_10 #define IOMUX_TABLE_ENET \ { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \ diff --git a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h index 5670902d11..7eecb1f6b4 100644 --- a/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1060_EVK/mpconfigboard.h @@ -62,6 +62,7 @@ #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } #define I2S_WM8960_RX_MODE (1) +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ @@ -146,8 +147,8 @@ #define ENET_PHY_OPS phyksz8081_ops // Etherner PIN definitions -#define ENET_RESET_PIN pin_GPIO_AD_B0_09 -#define ENET_INT_PIN pin_GPIO_AD_B0_10 +#define ENET_RESET_PIN &pin_GPIO_AD_B0_09 +#define ENET_INT_PIN &pin_GPIO_AD_B0_10 #define IOMUX_TABLE_ENET \ { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \ diff --git a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h index 0f4eaf246d..367b4a780b 100644 --- a/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h +++ b/ports/mimxrt/boards/MIMXRT1064_EVK/mpconfigboard.h @@ -62,6 +62,7 @@ #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } #define I2S_WM8960_RX_MODE (1) +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ @@ -146,8 +147,8 @@ #define ENET_PHY_OPS phyksz8081_ops // Etherner PIN definitions -#define ENET_RESET_PIN pin_GPIO_AD_B0_09 -#define ENET_INT_PIN pin_GPIO_AD_B0_10 +#define ENET_RESET_PIN &pin_GPIO_AD_B0_09 +#define ENET_INT_PIN &pin_GPIO_AD_B0_10 #define IOMUX_TABLE_ENET \ { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \ diff --git a/ports/mimxrt/boards/MIMXRT1170_EVK/board.json b/ports/mimxrt/boards/MIMXRT1170_EVK/board.json new file mode 100644 index 0000000000..01e554751b --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1170_EVK/board.json @@ -0,0 +1,28 @@ +{ + "deploy": [ + "../deploy_mimxrt.md" + ], + "docs": "", + "features": [ + "Ethernet", + "SDRAM", + "MicroSD", + "MicroUSB", + "Microphone", + "AudioCodec", + "SPDIF", + "CAN", + "Camera", + "SIM Socket", + "OpenSDA", + "JLink" + ], + "images": [ + "IMX-RT1170-EVK-TOP.jpg" + ], + "mcu": "mimxrt", + "product": "MIMXRT1170_EVK", + "thumbnail": "", + "url": "https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK", + "vendor": "NXP" +} diff --git a/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.h new file mode 100644 index 0000000000..0ec7ed7778 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.h @@ -0,0 +1,254 @@ +#define MICROPY_HW_BOARD_NAME "i.MX RT1170 EVK" +#define MICROPY_HW_MCU_NAME "MIMXRT1176DVMAA" +#define MICROPY_EVENT_POLL_HOOK \ + do { \ + extern void mp_handle_pending(bool); \ + mp_handle_pending(true); \ + } while (0); + +// MIMXRT1170_EVK has 2 user LEDs +#define MICROPY_HW_LED1_PIN (pin_GPIO_AD_04) +#define MICROPY_HW_LED2_PIN (pin_GPIO_AD_26) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin)) +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin)) + +#define MICROPY_HW_NUM_PIN_IRQS (6 * 32) + +// Define mapping hardware UART # to logical UART # +// LPUART2 on D0/D1 -> 1 +// LPUART3 on D12/D11 -> 2 +// LPUART5 on D10/D13 -> 3 +// LPUART11 on D15/D14 -> 4 +// LPUART12 on D25/D26 -> 5 +// LPUART8 on D33/D34 -> 6 +// LPUART7 on D35/D36 -> 7 + +#define MICROPY_HW_UART_NUM (sizeof(uart_index_table) / sizeof(uart_index_table)[0]) +#define MICROPY_HW_UART_INDEX { 1, 2, 3, 5, 11, 12, 8, 7 } + +#define IOMUX_TABLE_UART \ + { IOMUXC_GPIO_AD_24_LPUART1_TXD }, { IOMUXC_GPIO_AD_25_LPUART1_RXD }, \ + { IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD }, { IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD }, \ + { IOMUXC_GPIO_AD_30_LPUART3_TXD }, { IOMUXC_GPIO_AD_31_LPUART3_RXD }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_AD_28_LPUART5_TXD }, { IOMUXC_GPIO_AD_29_LPUART5_RXD }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_AD_00_LPUART7_TXD }, { IOMUXC_GPIO_AD_01_LPUART7_RXD }, \ + { IOMUXC_GPIO_AD_02_LPUART8_TXD }, { IOMUXC_GPIO_AD_03_LPUART8_RXD }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_LPSR_04_LPUART11_TXD }, { IOMUXC_GPIO_LPSR_05_LPUART11_RXD }, \ + { IOMUXC_GPIO_LPSR_10_LPUART12_TXD }, { IOMUXC_GPIO_LPSR_11_LPUART12_RXD }, + +// Define the mapping hardware SPI # to logical SPI # +// SCK/CS/SDO/SDI HW-SPI Logical SPI +// D13/D10/D11/D12 LPSPI1 -> 0 +// D26/D28/D25/D24 LPSPI6 -> 1 +// D24/ - /D14/D15 LPSPI5 -> 2 + +#define MICROPY_HW_SPI_INDEX { 1, 6, 5 } + +#define IOMUX_TABLE_SPI \ + { IOMUXC_GPIO_AD_28_LPSPI1_SCK }, { IOMUXC_GPIO_AD_29_LPSPI1_PCS0 }, \ + { IOMUXC_GPIO_AD_30_LPSPI1_SOUT }, { IOMUXC_GPIO_AD_31_LPSPI1_SIN }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_LPSR_12_LPSPI5_SCK }, { IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 }, \ + { IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT }, { IOMUXC_GPIO_LPSR_05_LPSPI5_SIN }, \ + { IOMUXC_GPIO_LPSR_10_LPSPI6_SCK }, { IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 }, \ + { IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT }, { IOMUXC_GPIO_LPSR_12_LPSPI6_SIN }, + + +#define DMA_REQ_SRC_RX { 0, kDmaRequestMuxLPSPI1Rx, kDmaRequestMuxLPSPI2Rx, \ + kDmaRequestMuxLPSPI3Rx, kDmaRequestMuxLPSPI4Rx } + +#define DMA_REQ_SRC_TX { 0, kDmaRequestMuxLPSPI1Tx, kDmaRequestMuxLPSPI2Tx, \ + kDmaRequestMuxLPSPI3Tx, kDmaRequestMuxLPSPI4Tx } + +// Define the mapping hardware I2C # to logical I2C # +// SDA/SCL HW-I2C Logical I2C +// D14/D15 LPI2C5 -> 0 +// D1/D0 LPI2C3 -> 1 +// A4/A5 LPI2C1 -> 2 +// D26/D25 LPI2C6 -> 3 +// D19/D18 LPI2C2 -> 4 + +#define MICROPY_HW_I2C_INDEX { 5, 3, 1, 6, 2 } + +#define IOMUX_TABLE_I2C \ + { IOMUXC_GPIO_AD_08_LPI2C1_SCL }, { IOMUXC_GPIO_AD_09_LPI2C1_SDA }, \ + { IOMUXC_GPIO_AD_18_LPI2C2_SCL }, { IOMUXC_GPIO_AD_19_LPI2C2_SDA }, \ + { IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL }, { IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA }, \ + { 0 }, { 0 }, \ + { IOMUXC_GPIO_LPSR_05_LPI2C5_SCL }, { IOMUXC_GPIO_LPSR_04_LPI2C5_SDA }, \ + { IOMUXC_GPIO_LPSR_11_LPI2C6_SCL }, { IOMUXC_GPIO_LPSR_10_LPI2C6_SDA }, + +#define MICROPY_PY_MACHINE_I2S (1) +#define MICROPY_HW_I2S_NUM (1) +#define I2S_CLOCK_MUX { 0, kCLOCK_Root_Sai1, kCLOCK_Root_Sai2, kCLOCK_Root_Sai3, kCLOCK_Root_Sai4 } +#define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx, kDmaRequestMuxSai3Rx, kDmaRequestMuxSai4Rx } +#define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx, kDmaRequestMuxSai3Tx, kDmaRequestMuxSai4Tx } +#define I2S_WM8960_RX_MODE (1) +#define I2S_AUDIO_PLL_CLOCK (4U) +#define DMAMUX DMAMUX0 + +#define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ + { \ + .hw_id = _hwid, \ + .fn = _fn, \ + .mode = _mode, \ + .name = MP_QSTR_##_pin, \ + .iomux = {_iomux}, \ + } + +#define I2S_GPIO_MAP \ + { \ + I2S_GPIO(1, MCK, TX, GPIO_AD_17, IOMUXC_GPIO_AD_17_SAI1_MCLK), \ + I2S_GPIO(1, SCK, RX, GPIO_AD_19, IOMUXC_GPIO_AD_19_SAI1_RX_BCLK), \ + I2S_GPIO(1, WS, RX, GPIO_AD_18, IOMUXC_GPIO_AD_18_SAI1_RX_SYNC), \ + I2S_GPIO(1, SD, RX, GPIO_AD_20, IOMUXC_GPIO_AD_20_SAI1_RX_DATA00), \ + I2S_GPIO(1, SCK, TX, GPIO_AD_22, IOMUXC_GPIO_AD_22_SAI1_TX_BCLK), \ + I2S_GPIO(1, WS, TX, GPIO_AD_23, IOMUXC_GPIO_AD_23_SAI1_TX_SYNC), \ + I2S_GPIO(1, SD, TX, GPIO_AD_21, IOMUXC_GPIO_AD_21_SAI1_TX_DATA00), \ + } + +// USDHC1 + +#define USDHC_DUMMY_PIN NULL, 0 +#define MICROPY_USDHC1 \ + { \ + .cmd = {GPIO_SD_B1_00_USDHC1_CMD}, \ + .clk = { GPIO_SD_B1_01_USDHC1_CLK }, \ + .cd_b = { USDHC_DUMMY_PIN }, \ + .data0 = { GPIO_SD_B1_02_USDHC1_DATA0 }, \ + .data1 = { GPIO_SD_B1_03_USDHC1_DATA1 }, \ + .data2 = { GPIO_SD_B1_04_USDHC1_DATA2 }, \ + .data3 = { GPIO_SD_B1_05_USDHC1_DATA3 }, \ + } +#define USDHC_DATA3_PULL_DOWN_ON_BOARD (1) + +// Network definitions + +// Transceiver Phy Parameters +#define ENET_PHY_ADDRESS (2) +#define ENET_PHY KSZ8081 +#define ENET_PHY_OPS phyksz8081_ops + +// 10/100 Ethernet PIN definitions +#define ENET_RESET_PIN &pin_GPIO_LPSR_12 +#define ENET_INT_PIN &pin_GPIO_AD_12 + +#define IOMUX_TABLE_ENET \ + { IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00, 0, 0x02u }, \ + { IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01, 0, 0x02u }, \ + { IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN, 0, 0x06u }, \ + { IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK, 1, 0x03u }, \ + { IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER, 0, 0x06u }, \ + { IOMUXC_GPIO_AD_33_ENET_MDIO, 0, 0x06u }, \ + { IOMUXC_GPIO_AD_32_ENET_MDC, 0, 0x06u }, + +// A second ETH port is present. +#define ENET_DUAL_PORT (1) +// 1G Transceiver Phy Parameters +#define ENET_1_PHY_ADDRESS (1) +#define ENET_1_PHY RTL8211F +#define ENET_1_PHY_OPS phyrtl8211f_ops + +// 1G Ethernet PIN definitions +// No INT pin for ENET_1G +#define ENET_1_RESET_PIN &pin_GPIO_DISP_B2_13 +#define ENET_1_INT_PIN NULL + +#define IOMUX_TABLE_ENET_1 \ + { IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03, 0, 0x08U }, \ + { IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN, 0, 0x0CU }, \ + { IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO, 0, 0x0CU }, \ + { IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO, 0, 0x06u }, \ + { IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC, 0, 0x06u }, + +// --- SEMC --- // +#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 +#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 +#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 +#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 +#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 +#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 +#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 +#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 +#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 +#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 +#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 +#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 +#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 +#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 +#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 +#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 + +#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 +#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 +#define MIMXRT_IOMUXC_SEMC_ADDR02 IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 +#define MIMXRT_IOMUXC_SEMC_ADDR03 IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 +#define MIMXRT_IOMUXC_SEMC_ADDR04 IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 +#define MIMXRT_IOMUXC_SEMC_ADDR05 IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 +#define MIMXRT_IOMUXC_SEMC_ADDR06 IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 +#define MIMXRT_IOMUXC_SEMC_ADDR07 IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 +#define MIMXRT_IOMUXC_SEMC_ADDR08 IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 +#define MIMXRT_IOMUXC_SEMC_ADDR09 IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 +#define MIMXRT_IOMUXC_SEMC_ADDR10 IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 +#define MIMXRT_IOMUXC_SEMC_ADDR11 IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 +#define MIMXRT_IOMUXC_SEMC_ADDR12 IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 + +#define MIMXRT_IOMUXC_SEMC_BA0 IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 +#define MIMXRT_IOMUXC_SEMC_BA1 IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 +#define MIMXRT_IOMUXC_SEMC_CAS IOMUXC_GPIO_EMC_B1_24_SEMC_CAS +#define MIMXRT_IOMUXC_SEMC_RAS IOMUXC_GPIO_EMC_B1_25_SEMC_RAS +#define MIMXRT_IOMUXC_SEMC_CLK IOMUXC_GPIO_EMC_B1_26_SEMC_CLK +#define MIMXRT_IOMUXC_SEMC_CKE IOMUXC_GPIO_EMC_B1_27_SEMC_CKE +#define MIMXRT_IOMUXC_SEMC_WE IOMUXC_GPIO_EMC_B1_28_SEMC_WE +#define MIMXRT_IOMUXC_SEMC_DM00 IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 +#define MIMXRT_IOMUXC_SEMC_DM01 IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 +#define MIMXRT_IOMUXC_SEMC_DQS IOMUXC_GPIO_EMC_B1_39_SEMC_DQS + +#define MIMXRT_IOMUXC_SEMC_CS0 IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 + +#define MIMXRT_IOMUXC_SEMC_DATA16 IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 +#define MIMXRT_IOMUXC_SEMC_DATA17 IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 +#define MIMXRT_IOMUXC_SEMC_DATA18 IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 +#define MIMXRT_IOMUXC_SEMC_DATA19 IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 +#define MIMXRT_IOMUXC_SEMC_DATA20 IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 +#define MIMXRT_IOMUXC_SEMC_DATA21 IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 +#define MIMXRT_IOMUXC_SEMC_DATA22 IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 +#define MIMXRT_IOMUXC_SEMC_DATA23 IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 +#define MIMXRT_IOMUXC_SEMC_DM02 IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 + +#define MIMXRT_IOMUXC_SEMC_DATA24 IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 +#define MIMXRT_IOMUXC_SEMC_DATA25 IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 +#define MIMXRT_IOMUXC_SEMC_DATA26 IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 +#define MIMXRT_IOMUXC_SEMC_DATA27 IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 +#define MIMXRT_IOMUXC_SEMC_DATA28 IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 +#define MIMXRT_IOMUXC_SEMC_DATA29 IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 +#define MIMXRT_IOMUXC_SEMC_DATA30 IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 +#define MIMXRT_IOMUXC_SEMC_DATA31 IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 +#define MIMXRT_IOMUXC_SEMC_DM03 IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 +#define MIMXRT_IOMUXC_SEMC_DQS4 IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 + +#if MICROPY_PY_MACHINE_I2S +#define MICROPY_BOARD_ROOT_POINTERS \ + struct _machine_i2s_obj_t *machine_i2s_obj[MICROPY_HW_I2S_NUM]; +#endif diff --git a/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.mk b/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.mk new file mode 100644 index 0000000000..ea72008d51 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1170_EVK/mpconfigboard.mk @@ -0,0 +1,23 @@ +MCU_SERIES = MIMXRT1176 +MCU_VARIANT = MIMXRT1176DVMAA +MCU_CORE = _cm7 + +MICROPY_FLOAT_IMPL = double +MICROPY_PY_MACHINE_SDCARD = 1 +MICROPY_HW_FLASH_TYPE ?= qspi_nor_flash +MICROPY_HW_FLASH_SIZE ?= 0x1000000 # 16MB +MICROPY_HW_FLASH_RESERVED ?= 0x100000 # 1MB CM4 Code address space + +MICROPY_HW_SDRAM_AVAIL = 1 +MICROPY_HW_SDRAM_SIZE = 0x4000000 # 64MB + +MICROPY_PY_LWIP = 1 +MICROPY_PY_USSL = 1 +MICROPY_SSL_MBEDTLS = 1 + +CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7 \ + -DMIMXRT117x_SERIES \ + -DENET_ENHANCEDBUFFERDESCRIPTOR_MODE=1 \ + -DCPU_HEADER_H='<$(MCU_SERIES)$(MCU_CORE).h>' \ + -DUSB1_BASE=USB_OTG1_BASE \ + -DUSB2_BASE=USB_OTG2_BASE diff --git a/ports/mimxrt/boards/MIMXRT1170_EVK/pins.csv b/ports/mimxrt/boards/MIMXRT1170_EVK/pins.csv new file mode 100644 index 0000000000..77f87e8ba1 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1170_EVK/pins.csv @@ -0,0 +1,59 @@ +D0,GPIO_DISP_B2_11 +D1,GPIO_DISP_B2_10 +D2,GPIO_DISP_B2_12 +D3,GPIO_AD_04 +D4,GPIO_AD_06 +D5,GPIO_AD_05 +D6,GPIO_AD_00 +D7,GPIO_AD_14 +D8,GPIO_AD_07 +D9,GPIO_AD_01 +D10,GPIO_AD_29 +D11,GPIO_AD_30 +D12,GPIO_AD_31 +D13,GPIO_AD_28 +D14,GPIO_LPSR_04 +D15,GPIO_LPSR_05 +D16,GPIO_AD_19 +D17,GPIO_DISP_B2_12 +D18,GPIO_AD_18 +D19,GPIO_AD_20 +D20,GPIO_AD_21 +D21,GPIO_AD_22 +D22,GPIO_AD_23 +D23,GPIO_AD_17 +D24,GPIO_LPSR_12 +D25,GPIO_LPSR_11 +D26,GPIO_LPSR_10 +D27,GPIO_LPSR_09 +D29,GPIO_DISP_B2_11 +D30,GPIO_DISP_B2_10 +D31,GPIO_AD_05 +D32,GPIO_AD_04 +D33,GPIO_AD_03 +D34,GPIO_AD_02 +D35,GPIO_AD_01 +D36,GPIO_AD_00 +A0,GPIO_AD_10 +A1,GPIO_AD_11 +A2,GPIO_AD_12 +A3,GPIO_AD_13 +A4,GPIO_AD_09 +A5,GPIO_AD_08 +RX,GPIO_DISP_B2_11 +TX,GPIO_DISP_B2_10 +SCL,GPIO_LPSR_05 +SDA,GPIO_LPSR_04 +SCK,GPIO_AD_28 +SDI,GPIO_AD_31 +SDO,GPIO_AD_30 +CS,GPIO_AD_29 +LED1,GPIO_AD_04 +LED2,GPIO_AD_26 +MCK,GPIO_AD_17 +SCK_RX,GPIO_AD_19 +WS_RX,GPIO_AD_18 +SD_RX,GPIO_AD_20 +SCK_TX,GPIO_AD_22 +WS_TX,GPIO_AD_23 +SD_TX,GPIO_AD_21 diff --git a/ports/mimxrt/boards/MIMXRT1176.ld b/ports/mimxrt/boards/MIMXRT1176.ld new file mode 100644 index 0000000000..2408977b94 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1176.ld @@ -0,0 +1,59 @@ +/* Memory configuration */ + +/* Reserved Area + * Users can create a reserved area at the end of the flash memory via + * 'reserved_size' variable. The size of the reserved area should be a multiple + * of the sector size of the flash memory! + */ +#if defined MICROPY_HW_FLASH_RESERVED +reserved_size = MICROPY_HW_FLASH_RESERVED; +#endif + +#if MICROPY_HW_FLASH_TYPE == qspi_nor +flash_start = 0x30000000; +#else +#error Unknown MICROPY_HW_FLASH_TYPE +#endif +flash_size = MICROPY_HW_FLASH_SIZE; +flash_end = DEFINED(reserved_size) ? ((flash_start) + (flash_size - reserved_size)) : ((flash_start) + (flash_size)); +flash_config_start = flash_start + 0x400; /* TODO: check why config_start is on 0x400 instead of 0x0 offset */ +flash_config_size = 0x00000C00; +ivt_start = flash_start + 0x00001000; +ivt_size = 0x00001000; +interrupts_start = flash_start + 0x00002000; +interrupts_size = 0x00000400; +text_start = flash_start + 0x00002400; +vfs_start = flash_start + 0x00200000; + +#if defined MULTI_CORE +m_core1_image_start = vfs_start - 0x00040000; +m_core1_image_size = 0x00040000; +#endif + +text_size = ((vfs_start) - (text_start)); +vfs_size = ((flash_end) - (vfs_start)); +itcm_start = 0x00000000; +itcm_size = 0x00020000; +dtcm_start = 0x20000000; +dtcm_size = 0x00020000; +ocrm_start = 0x20240000; +ocrm_size = 0x00100000; + +#ifdef MICROPY_HW_SDRAM_AVAIL +sdram_start = 0x80000000; +sdram_size = MICROPY_HW_SDRAM_SIZE; +#endif + +/* 32kiB stack. */ +__stack_size__ = 0x8000; +_estack = __StackTop; +_sstack = __StackLimit; + +#ifdef MICROPY_HW_SDRAM_AVAIL +_gc_heap_start = ORIGIN(m_sdram); +_gc_heap_end = ORIGIN(m_sdram) + LENGTH(m_sdram); +#else +/* Use second OCRAM bank for GC heap. */ +_gc_heap_start = ORIGIN(m_ocrm); +_gc_heap_end = ORIGIN(m_ocrm) + LENGTH(m_ocrm); +#endif diff --git a/ports/mimxrt/boards/MIMXRT1176_af.csv b/ports/mimxrt/boards/MIMXRT1176_af.csv new file mode 100644 index 0000000000..fe31f502e4 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1176_af.csv @@ -0,0 +1,173 @@ +Pad,ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ADC,ACMP,Default +GPIO_SD_B1_00,USDHC1_CMD,,XBAR1_INOUT20,GPT4_CAPTURE1,,GPIO4_IO03,FLEXSPI2_A_SS0_B,,KPP_ROW07,,GPIO10_IO03,,, +GPIO_SD_B1_01,USDHC1_CLK,,XBAR1_INOUT21,GPT4_CAPTURE2,,GPIO4_IO04,FLEXSPI2_A_SCLK,,KPP_COL07,,GPIO10_IO04,,, +GPIO_SD_B1_02,USDHC1_DATA0,,XBAR1_INOUT22,GPT4_COMPARE1,,GPIO4_IO05,FLEXSPI2_A_DATA00,,KPP_ROW06,FLEXSPI1_A_SS1_B,GPIO10_IO05,,, +GPIO_SD_B1_03,USDHC1_DATA1,,XBAR1_INOUT23,GPT4_COMPARE2,,GPIO4_IO06,FLEXSPI2_A_DATA01,,KPP_COL06,FLEXSPI1_B_SS1_B,GPIO10_IO06,,, +GPIO_SD_B1_04,USDHC1_DATA2,,XBAR1_INOUT24,GPT4_COMPARE3,,GPIO4_IO07,FLEXSPI2_A_DATA02,,FLEXSPI1_B_SS0_B,ENET_QOS_1588_EVENT2_AUX_IN,GPIO10_IO07,,, +GPIO_SD_B1_05,USDHC1_DATA3,,XBAR1_INOUT25,GPT4_CLK,,GPIO4_IO08,FLEXSPI2_A_DATA03,,FLEXSPI1_B_DQS,ENET_QOS_1588_EVENT3_AUX_IN,GPIO10_IO08,,, +GPIO_SD_B2_00,USDHC2_DATA3,FLEXSPI1_B_DATA03,ENET_1G_RX_EN,LPUART9_TXD,LPSPI4_SCK,GPIO4_IO09,,,,,GPIO10_IO09,,, +GPIO_SD_B2_01,USDHC2_DATA2,FLEXSPI1_B_DATA02,ENET_1G_RX_CLK,LPUART9_RXD,LPSPI4_PCS0,GPIO4_IO10,,,,,GPIO10_IO10,,, +GPIO_SD_B2_02,USDHC2_DATA1,FLEXSPI1_B_DATA01,ENET_1G_RX_DATA00,LPUART9_CTS_B,LPSPI4_SOUT,GPIO4_IO11,,,,,GPIO10_IO11,,, +GPIO_SD_B2_03,USDHC2_DATA0,FLEXSPI1_B_DATA00,ENET_1G_RX_DATA01,LPUART9_RTS_B,LPSPI4_SIN,GPIO4_IO12,,,,,GPIO10_IO12,,, +GPIO_SD_B2_04,USDHC2_CLK,FLEXSPI1_B_SCLK,ENET_1G_RX_DATA02,FLEXSPI1_A_SS1_B,LPSPI4_PCS1,GPIO4_IO13,,,,,GPIO10_IO13,,, +GPIO_SD_B2_05,USDHC2_CMD,FLEXSPI1_A_DQS,ENET_1G_RX_DATA03,FLEXSPI1_B_SS0_B,LPSPI4_PCS2,GPIO4_IO14,,,,,GPIO10_IO14,,, +GPIO_SD_B2_06,USDHC2_RESET_B,FLEXSPI1_A_SS0_B,ENET_1G_TX_DATA03,LPSPI4_PCS3,GPT6_CAPTURE1,GPIO4_IO15,,,,,GPIO10_IO15,,, +GPIO_SD_B2_07,USDHC2_STROBE,FLEXSPI1_A_SCLK,ENET_1G_TX_DATA02,LPUART3_CTS_B,GPT6_CAPTURE2,GPIO4_IO16,LPSPI2_SCK,,ENET_TX_ER,ENET_QOS_REF_CLK,GPIO10_IO16,,, +GPIO_SD_B2_08,USDHC2_DATA4,FLEXSPI1_A_DATA00,ENET_1G_TX_DATA01,LPUART3_RTS_B,GPT6_COMPARE1,GPIO4_IO17,LPSPI2_PCS0,,,,GPIO10_IO17,,, +GPIO_SD_B2_09,USDHC2_DATA5,FLEXSPI1_A_DATA01,ENET_1G_TX_DATA00,LPUART5_CTS_B,GPT6_COMPARE2,GPIO4_IO18,LPSPI2_SOUT,,,,GPIO10_IO18,,, +GPIO_SD_B2_10,USDHC2_DATA6,FLEXSPI1_A_DATA02,ENET_1G_TX_EN,LPUART5_RTS_B,GPT6_COMPARE3,GPIO4_IO19,LPSPI2_SIN,,,,GPIO10_IO19,,, +GPIO_SD_B2_11,USDHC2_DATA7,FLEXSPI1_A_DATA03,ENET_1G_TX_CLK_IO,ENET_1G_REF_CLK,GPT6_CLK,GPIO4_IO20,LPSPI2_PCS1,,,,GPIO10_IO20,,, +GPIO_EMC_B1_00,SEMC_DATA00,FLEXPWM4_PWM0_A,,,,GPIO1_IO00,,,FLEXIO1_D00,,GPIO7_IO00,,, +GPIO_EMC_B1_01,SEMC_DATA01,FLEXPWM4_PWM0_B,,,,GPIO1_IO01,,,FLEXIO1_D01,,GPIO7_IO01,,, +GPIO_EMC_B1_02,SEMC_DATA02,FLEXPWM4_PWM1_A,,,,GPIO1_IO02,,,FLEXIO1_D02,,GPIO7_IO02,,, +GPIO_EMC_B1_03,SEMC_DATA03,FLEXPWM4_PWM1_B,,,,GPIO1_IO03,,,FLEXIO1_D03,,GPIO7_IO03,,, +GPIO_EMC_B1_04,SEMC_DATA04,FLEXPWM4_PWM2_A,,,,GPIO1_IO04,,,FLEXIO1_D04,,GPIO7_IO04,,, +GPIO_EMC_B1_05,SEMC_DATA05,FLEXPWM4_PWM2_B,,,,GPIO1_IO05,,,FLEXIO1_D05,,GPIO7_IO05,,, +GPIO_EMC_B1_06,SEMC_DATA06,FLEXPWM2_PWM0_A,,,,GPIO1_IO06,,,FLEXIO1_D06,,GPIO7_IO06,,, +GPIO_EMC_B1_07,SEMC_DATA07,FLEXPWM2_PWM0_B,,,,GPIO1_IO07,,,FLEXIO1_D07,,GPIO7_IO07,,, +GPIO_EMC_B1_08,SEMC_DM00,FLEXPWM2_PWM1_A,,,,GPIO1_IO08,,,FLEXIO1_D08,,GPIO7_IO08,,, +GPIO_EMC_B1_09,SEMC_ADDR00,FLEXPWM2_PWM1_B,GPT5_CAPTURE1,,,GPIO1_IO09,,,FLEXIO1_D09,,GPIO7_IO09,,, +GPIO_EMC_B1_10,SEMC_ADDR01,FLEXPWM2_PWM2_A,GPT5_CAPTURE2,,,GPIO1_IO10,,,FLEXIO1_D10,,GPIO7_IO10,,, +GPIO_EMC_B1_11,SEMC_ADDR02,FLEXPWM2_PWM2_B,GPT5_COMPARE1,,,GPIO1_IO11,,,FLEXIO1_D11,,GPIO7_IO11,,, +GPIO_EMC_B1_12,SEMC_ADDR03,XBAR1_INOUT04,GPT5_COMPARE2,,,GPIO1_IO12,,,FLEXIO1_D12,,GPIO7_IO12,,, +GPIO_EMC_B1_13,SEMC_ADDR04,XBAR1_INOUT05,GPT5_COMPARE3,,,GPIO1_IO13,,,FLEXIO1_D13,,GPIO7_IO13,,, +GPIO_EMC_B1_14,SEMC_ADDR05,XBAR1_INOUT06,GPT5_CLK,,,GPIO1_IO14,,,FLEXIO1_D14,,GPIO7_IO14,,, +GPIO_EMC_B1_15,SEMC_ADDR06,XBAR1_INOUT07,,,,GPIO1_IO15,,,FLEXIO1_D15,,GPIO7_IO15,,, +GPIO_EMC_B1_16,SEMC_ADDR07,XBAR1_INOUT08,,,,GPIO1_IO16,,,FLEXIO1_D16,,GPIO7_IO16,,, +GPIO_EMC_B1_17,SEMC_ADDR08,FLEXPWM4_PWM3_A,TMR1_TIMER0,,,GPIO1_IO17,,,FLEXIO1_D17,,GPIO7_IO17,,, +GPIO_EMC_B1_18,SEMC_ADDR09,FLEXPWM4_PWM3_B,TMR2_TIMER0,,,GPIO1_IO18,,,FLEXIO1_D18,,GPIO7_IO18,,, +GPIO_EMC_B1_19,SEMC_ADDR11,FLEXPWM2_PWM3_A,TMR3_TIMER0,,,GPIO1_IO19,,,FLEXIO1_D19,,GPIO7_IO19,,, +GPIO_EMC_B1_20,SEMC_ADDR12,FLEXPWM2_PWM3_B,TMR4_TIMER0,,,GPIO1_IO20,,,FLEXIO1_D20,,GPIO7_IO20,,, +GPIO_EMC_B1_21,SEMC_BA0,FLEXPWM3_PWM3_A,,,,GPIO1_IO21,,,FLEXIO1_D21,,GPIO7_IO21,,, +GPIO_EMC_B1_22,SEMC_BA1,FLEXPWM3_PWM3_B,,,,GPIO1_IO22,,,FLEXIO1_D22,,GPIO7_IO22,,, +GPIO_EMC_B1_23,SEMC_ADDR10,FLEXPWM1_PWM0_A,,,,GPIO1_IO23,,,FLEXIO1_D23,,GPIO7_IO23,,, +GPIO_EMC_B1_24,SEMC_CAS,FLEXPWM1_PWM0_B,,,,GPIO1_IO24,,,FLEXIO1_D24,,GPIO7_IO24,,, +GPIO_EMC_B1_25,SEMC_RAS,FLEXPWM1_PWM1_A,,,,GPIO1_IO25,,,FLEXIO1_D25,,GPIO7_IO25,,, +GPIO_EMC_B1_26,SEMC_CLK,FLEXPWM1_PWM1_B,,,,GPIO1_IO26,,,FLEXIO1_D26,,GPIO7_IO26,,, +GPIO_EMC_B1_27,SEMC_CKE,FLEXPWM1_PWM2_A,,,,GPIO1_IO27,,,FLEXIO1_D27,,GPIO7_IO27,,, +GPIO_EMC_B1_28,SEMC_WE,FLEXPWM1_PWM2_B,,,,GPIO1_IO28,,,FLEXIO1_D28,,GPIO7_IO28,,, +GPIO_EMC_B1_29,SEMC_CS0,FLEXPWM3_PWM0_A,,,,GPIO1_IO29,,,FLEXIO1_D29,,GPIO7_IO29,,, +GPIO_EMC_B1_30,SEMC_DATA08,FLEXPWM3_PWM0_B,,,,GPIO1_IO30,,,FLEXIO1_D30,,GPIO7_IO30,,, +GPIO_EMC_B1_31,SEMC_DATA09,FLEXPWM3_PWM1_A,,,,GPIO1_IO31,,,FLEXIO1_D31,,GPIO7_IO31,,, +GPIO_EMC_B1_32,SEMC_DATA10,FLEXPWM3_PWM1_B,,,,GPIO2_IO00,,,,,GPIO8_IO00,,, +GPIO_EMC_B1_33,SEMC_DATA11,FLEXPWM3_PWM2_A,,,,GPIO2_IO01,,,,,GPIO8_IO01,,, +GPIO_EMC_B1_34,SEMC_DATA12,FLEXPWM3_PWM2_B,,,,GPIO2_IO02,,,,,GPIO8_IO02,,, +GPIO_EMC_B1_35,SEMC_DATA13,XBAR1_INOUT09,,,,GPIO2_IO03,,,,,GPIO8_IO03,,, +GPIO_EMC_B1_36,SEMC_DATA14,XBAR1_INOUT10,,,,GPIO2_IO04,,,,,GPIO8_IO04,,, +GPIO_EMC_B1_37,SEMC_DATA15,XBAR1_INOUT11,,,,GPIO2_IO05,,,,,GPIO8_IO05,,, +GPIO_EMC_B1_38,SEMC_DM01,FLEXPWM1_PWM3_A,TMR1_TIMER1,,,GPIO2_IO06,,,,,GPIO8_IO06,,, +GPIO_EMC_B1_39,SEMC_DQS,FLEXPWM1_PWM3_B,TMR2_TIMER1,,,GPIO2_IO07,,,,,GPIO8_IO07,,, +GPIO_EMC_B1_40,SEMC_RDY,XBAR1_INOUT12,MQS_RIGHT,LPUART6_TXD,,GPIO2_IO08,,ENET_1G_MDC,,CCM_CLKO1,GPIO8_IO08,,, +GPIO_EMC_B1_41,SEMC_CSX00,XBAR1_INOUT13,MQS_LEFT,LPUART6_RXD,FLEXSPI2_B_DATA07,GPIO2_IO09,,ENET_1G_MDIO,,CCM_CLKO2,GPIO8_IO09,,, +GPIO_EMC_B2_00,SEMC_DATA16,CCM_ENET_REF_CLK_25M,TMR3_TIMER1,LPUART6_CTS_B,FLEXSPI2_B_DATA06,GPIO2_IO10,XBAR1_INOUT20,ENET_QOS_1588_EVENT1_OUT,LPSPI1_SCK,LPI2C2_SCL,GPIO8_IO10,,, +GPIO_EMC_B2_01,SEMC_DATA17,USDHC2_CD_B,TMR4_TIMER1,LPUART6_RTS_B,FLEXSPI2_B_DATA05,GPIO2_IO11,XBAR1_INOUT21,ENET_QOS_1588_EVENT1_IN,LPSPI1_PCS0,LPI2C2_SDA,GPIO8_IO11,,, +GPIO_EMC_B2_02,SEMC_DATA18,USDHC2_WP,,VIDEO_MUX_CSI_DATA23,FLEXSPI2_B_DATA04,GPIO2_IO12,XBAR1_INOUT22,ENET_QOS_1588_EVENT1_AUX_IN,LPSPI1_SOUT,,GPIO8_IO12,,, +GPIO_EMC_B2_03,SEMC_DATA19,USDHC2_VSELECT,,VIDEO_MUX_CSI_DATA22,FLEXSPI2_B_DATA03,GPIO2_IO13,XBAR1_INOUT23,ENET_1G_TX_DATA03,LPSPI1_SIN,,GPIO8_IO13,,, +GPIO_EMC_B2_04,SEMC_DATA20,USDHC2_RESET_B,SAI2_MCLK,VIDEO_MUX_CSI_DATA21,FLEXSPI2_B_DATA02,GPIO2_IO14,XBAR1_INOUT24,ENET_1G_TX_DATA02,LPSPI3_SCK,,GPIO8_IO14,,, +GPIO_EMC_B2_05,SEMC_DATA21,GPT3_CLK,SAI2_RX_SYNC,VIDEO_MUX_CSI_DATA20,FLEXSPI2_B_DATA01,GPIO2_IO15,XBAR1_INOUT25,ENET_1G_RX_CLK,LPSPI3_PCS0,PIT1_TRIGGER0,GPIO8_IO15,,, +GPIO_EMC_B2_06,SEMC_DATA22,GPT3_CAPTURE1,SAI2_RX_BCLK,VIDEO_MUX_CSI_DATA19,FLEXSPI2_B_DATA00,GPIO2_IO16,XBAR1_INOUT26,ENET_1G_TX_ER,LPSPI3_SOUT,PIT1_TRIGGER1,GPIO8_IO16,,, +GPIO_EMC_B2_07,SEMC_DATA23,GPT3_CAPTURE2,SAI2_RX_DATA,VIDEO_MUX_CSI_DATA18,FLEXSPI2_B_DQS,GPIO2_IO17,XBAR1_INOUT27,ENET_1G_RX_DATA03,LPSPI3_SIN,PIT1_TRIGGER2,GPIO8_IO17,,, +GPIO_EMC_B2_08,SEMC_DM02,GPT3_COMPARE1,SAI2_TX_DATA,VIDEO_MUX_CSI_DATA17,FLEXSPI2_B_SS0_B,GPIO2_IO18,XBAR1_INOUT28,ENET_1G_RX_DATA02,LPSPI3_PCS1,PIT1_TRIGGER3,GPIO8_IO18,,, +GPIO_EMC_B2_09,SEMC_DATA24,GPT3_COMPARE2,SAI2_TX_BCLK,VIDEO_MUX_CSI_DATA16,FLEXSPI2_B_SCLK,GPIO2_IO19,XBAR1_INOUT29,ENET_1G_CRS,LPSPI3_PCS2,TMR1_TIMER0,GPIO8_IO19,,, +GPIO_EMC_B2_10,SEMC_DATA25,GPT3_COMPARE3,SAI2_TX_SYNC,VIDEO_MUX_CSI_FIELD,FLEXSPI2_A_SCLK,GPIO2_IO20,XBAR1_INOUT30,ENET_1G_COL,LPSPI3_PCS3,TMR1_TIMER1,GPIO8_IO20,,, +GPIO_EMC_B2_11,SEMC_DATA26,SPDIF_IN,ENET_1G_TX_DATA00,SAI3_RX_SYNC,FLEXSPI2_A_SS0_B,GPIO2_IO21,XBAR1_INOUT31,,EMVSIM1_IO,TMR1_TIMER2,GPIO8_IO21,,, +GPIO_EMC_B2_12,SEMC_DATA27,SPDIF_OUT,ENET_1G_TX_DATA01,SAI3_RX_BCLK,FLEXSPI2_A_DQS,GPIO2_IO22,XBAR1_INOUT32,,EMVSIM1_CLK,TMR1_TIMER3,GPIO8_IO22,,, +GPIO_EMC_B2_13,SEMC_DATA28,,ENET_1G_TX_EN,SAI3_RX_DATA,FLEXSPI2_A_DATA00,GPIO2_IO23,XBAR1_INOUT33,,EMVSIM1_RST,TMR2_TIMER0,GPIO8_IO23,,, +GPIO_EMC_B2_14,SEMC_DATA29,,ENET_1G_TX_CLK_IO,SAI3_TX_DATA,FLEXSPI2_A_DATA01,GPIO2_IO24,XBAR1_INOUT34,SFA_ipp_do_atx_clk_under_test,EMVSIM1_SVEN,TMR2_TIMER1,GPIO8_IO24,,, +GPIO_EMC_B2_15,SEMC_DATA30,,ENET_1G_RX_DATA00,SAI3_TX_BCLK,FLEXSPI2_A_DATA02,GPIO2_IO25,XBAR1_INOUT35,,EMVSIM1_PD,TMR2_TIMER2,GPIO8_IO25,,, +GPIO_EMC_B2_16,SEMC_DATA31,XBAR1_INOUT14,ENET_1G_RX_DATA01,SAI3_TX_SYNC,FLEXSPI2_A_DATA03,GPIO2_IO26,,,EMVSIM1_POWER_FAIL,TMR2_TIMER3,GPIO8_IO26,,, +GPIO_EMC_B2_17,SEMC_DM03,XBAR1_INOUT15,ENET_1G_RX_EN,SAI3_MCLK,FLEXSPI2_A_DATA04,GPIO2_IO27,,,WDOG1_ANY,TMR3_TIMER0,GPIO8_IO27,,, +GPIO_EMC_B2_18,SEMC_DQS4,XBAR1_INOUT16,ENET_1G_RX_ER,EWM_OUT_B,FLEXSPI2_A_DATA05,GPIO2_IO28,FLEXSPI1_A_DQS,,WDOG1_B,TMR3_TIMER1,GPIO8_IO28,,, +GPIO_EMC_B2_19,SEMC_CLKX00,ENET_MDC,ENET_1G_MDC,ENET_1G_REF_CLK,FLEXSPI2_A_DATA06,GPIO2_IO29,,,ENET_QOS_MDC,TMR3_TIMER2,GPIO8_IO29,,, +GPIO_EMC_B2_20,SEMC_CLKX01,ENET_MDIO,ENET_1G_MDIO,ENET_QOS_REF_CLK,FLEXSPI2_A_DATA07,GPIO2_IO30,,,ENET_QOS_MDIO,TMR3_TIMER3,GPIO8_IO30,,, +GPIO_SNVS_00,SNVS_TAMPER0,,,,,GPIO13_IO03,,,,,,,, +GPIO_SNVS_01,SNVS_TAMPER1,,,,,GPIO13_IO04,,,,,,,, +GPIO_SNVS_02,SNVS_TAMPER2,,,,,GPIO13_IO05,,,,,,,, +GPIO_SNVS_03,SNVS_TAMPER3,,,,,GPIO13_IO06,,,,,,,, +GPIO_SNVS_04,SNVS_TAMPER4,,,,,GPIO13_IO07,,,,,,,, +GPIO_SNVS_05,SNVS_TAMPER5,,,,,GPIO13_IO08,,,,,,,, +GPIO_SNVS_06,SNVS_TAMPER6,,,,,GPIO13_IO09,,,,,,,, +GPIO_SNVS_07,SNVS_TAMPER7,,,,,GPIO13_IO10,,,,,,,, +GPIO_SNVS_08,SNVS_TAMPER8,,,,,GPIO13_IO11,,,,,,,, +GPIO_SNVS_09,SNVS_TAMPER9,,,,,GPIO13_IO12,,,,,,,, +GPIO_LPSR_00,FLEXCAN3_TX,MIC_CLK,MQS_RIGHT,ARM_CM4_EVENTO,,GPIO6_IO00,LPUART12_TXD,SAI4_MCLK,,,GPIO12_IO00,,, +GPIO_LPSR_01,FLEXCAN3_RX,MIC_BITSTREAM0,MQS_LEFT,ARM_CM4_EVENTI,,GPIO6_IO01,LPUART12_RXD,,,,GPIO12_IO01,,, +GPIO_LPSR_02,SRC_BOOT_MODE00,LPSPI5_SCK,SAI4_TX_DATA,MQS_RIGHT,,GPIO6_IO02,,,,,GPIO12_IO02,,, +GPIO_LPSR_03,SRC_BOOT_MODE01,LPSPI5_PCS0,SAI4_TX_SYNC,MQS_LEFT,,GPIO6_IO03,,,,,GPIO12_IO03,,, +GPIO_LPSR_04,LPI2C5_SDA,LPSPI5_SOUT,SAI4_TX_BCLK,LPUART12_RTS_B,,GPIO6_IO04,LPUART11_TXD,,,,GPIO12_IO04,,, +GPIO_LPSR_05,LPI2C5_SCL,LPSPI5_SIN,SAI4_MCLK,LPUART12_CTS_B,,GPIO6_IO05,LPUART11_RXD,NMI_GLUE_NMI,,,GPIO12_IO05,,, +GPIO_LPSR_06,LPI2C6_SDA,,SAI4_RX_DATA,LPUART12_TXD,LPSPI6_PCS3,GPIO6_IO06,FLEXCAN3_TX,PIT2_TRIGGER3,LPSPI5_PCS1,,GPIO12_IO06,,, +GPIO_LPSR_07,LPI2C6_SCL,,SAI4_RX_BCLK,LPUART12_RXD,LPSPI6_PCS2,GPIO6_IO07,FLEXCAN3_RX,PIT2_TRIGGER2,LPSPI5_PCS2,,GPIO12_IO07,,, +GPIO_LPSR_08,LPUART11_TXD,FLEXCAN3_TX,SAI4_RX_SYNC,MIC_CLK,LPSPI6_PCS1,GPIO6_IO08,LPI2C5_SDA,PIT2_TRIGGER1,LPSPI5_PCS3,,GPIO12_IO08,,, +GPIO_LPSR_09,LPUART11_RXD,FLEXCAN3_RX,PIT2_TRIGGER0,MIC_BITSTREAM0,LPSPI6_PCS0,GPIO6_IO09,LPI2C5_SCL,SAI4_TX_DATA,,,GPIO12_IO09,,, +GPIO_LPSR_10,JTAG_MUX_TRSTB,LPUART11_CTS_B,LPI2C6_SDA,MIC_BITSTREAM1,LPSPI6_SCK,GPIO6_IO10,LPI2C5_SCLS,SAI4_TX_SYNC,LPUART12_TXD,,GPIO12_IO10,,, +GPIO_LPSR_11,JTAG_MUX_TDO,LPUART11_RTS_B,LPI2C6_SCL,MIC_BITSTREAM2,LPSPI6_SOUT,GPIO6_IO11,LPI2C5_SDAS,ARM_TRACE_SWO,LPUART12_RXD,,GPIO12_IO11,,, +GPIO_LPSR_12,JTAG_MUX_TDI,PIT2_TRIGGER0,,MIC_BITSTREAM3,LPSPI6_SIN,GPIO6_IO12,LPI2C5_HREQ,SAI4_TX_BCLK,LPSPI5_SCK,,GPIO12_IO12,,, +GPIO_LPSR_13,JTAG_MUX_MOD,MIC_BITSTREAM1,PIT2_TRIGGER1,,,GPIO6_IO13,,SAI4_RX_DATA,LPSPI5_PCS0,,GPIO12_IO13,,, +GPIO_LPSR_14,JTAG_MUX_TCK,MIC_BITSTREAM2,PIT2_TRIGGER2,,,GPIO6_IO14,,SAI4_RX_BCLK,LPSPI5_SOUT,,GPIO12_IO14,,, +GPIO_LPSR_15,JTAG_MUX_TMS,MIC_BITSTREAM3,PIT2_TRIGGER3,,,GPIO6_IO15,,SAI4_RX_SYNC,LPSPI5_SIN,,GPIO12_IO15,,, +WAKEUP_DIG,,,,,,GPIO13_IO00,,NMI_GLUE_NMI,,,,,, +GPIO_DISP_B1_00,VIDEO_MUX_LCDIF_CLK,ENET_1G_RX_EN,,TMR1_TIMER0,XBAR1_INOUT26,GPIO4_IO21,,,ENET_QOS_RX_EN,,GPIO10_IO21,,, +GPIO_DISP_B1_01,VIDEO_MUX_LCDIF_ENABLE,ENET_1G_RX_CLK,ENET_1G_RX_ER,TMR1_TIMER1,XBAR1_INOUT27,GPIO4_IO22,,,ENET_QOS_RX_CLK,ENET_QOS_RX_ER,GPIO10_IO22,,, +GPIO_DISP_B1_02,VIDEO_MUX_LCDIF_HSYNC,ENET_1G_RX_DATA00,LPI2C3_SCL,TMR1_TIMER2,XBAR1_INOUT28,GPIO4_IO23,,,ENET_QOS_RX_DATA00,LPUART1_TXD,GPIO10_IO23,,, +GPIO_DISP_B1_03,VIDEO_MUX_LCDIF_VSYNC,ENET_1G_RX_DATA01,LPI2C3_SDA,TMR2_TIMER0,XBAR1_INOUT29,GPIO4_IO24,,,ENET_QOS_RX_DATA01,LPUART1_RXD,GPIO10_IO24,,, +GPIO_DISP_B1_04,VIDEO_MUX_LCDIF_DATA00,ENET_1G_RX_DATA02,LPUART4_RXD,TMR2_TIMER1,XBAR1_INOUT30,GPIO4_IO25,,,ENET_QOS_RX_DATA02,LPSPI3_SCK,GPIO10_IO25,,, +GPIO_DISP_B1_05,VIDEO_MUX_LCDIF_DATA01,ENET_1G_RX_DATA03,LPUART4_CTS_B,TMR2_TIMER2,XBAR1_INOUT31,GPIO4_IO26,,,ENET_QOS_RX_DATA03,LPSPI3_SIN,GPIO10_IO26,,, +GPIO_DISP_B1_06,VIDEO_MUX_LCDIF_DATA02,ENET_1G_TX_DATA03,LPUART4_TXD,TMR3_TIMER0,XBAR1_INOUT32,GPIO4_IO27,SRC_BT_CFG00,,ENET_QOS_TX_DATA03,LPSPI3_SOUT,GPIO10_IO27,,, +GPIO_DISP_B1_07,VIDEO_MUX_LCDIF_DATA03,ENET_1G_TX_DATA02,LPUART4_RTS_B,TMR3_TIMER1,XBAR1_INOUT33,GPIO4_IO28,SRC_BT_CFG01,,ENET_QOS_TX_DATA02,LPSPI3_PCS0,GPIO10_IO28,,, +GPIO_DISP_B1_08,VIDEO_MUX_LCDIF_DATA04,ENET_1G_TX_DATA01,USDHC1_CD_B,TMR3_TIMER2,XBAR1_INOUT34,GPIO4_IO29,SRC_BT_CFG02,,ENET_QOS_TX_DATA01,LPSPI3_PCS1,GPIO10_IO29,,, +GPIO_DISP_B1_09,VIDEO_MUX_LCDIF_DATA05,ENET_1G_TX_DATA00,USDHC1_WP,TMR4_TIMER0,XBAR1_INOUT35,GPIO4_IO30,SRC_BT_CFG03,,ENET_QOS_TX_DATA00,LPSPI3_PCS2,GPIO10_IO30,,, +GPIO_DISP_B1_10,VIDEO_MUX_LCDIF_DATA06,ENET_1G_TX_EN,USDHC1_RESET_B,TMR4_TIMER1,XBAR1_INOUT36,GPIO4_IO31,SRC_BT_CFG04,,ENET_QOS_TX_EN,LPSPI3_PCS3,GPIO10_IO31,,, +GPIO_DISP_B1_11,VIDEO_MUX_LCDIF_DATA07,ENET_1G_TX_CLK_IO,ENET_1G_REF_CLK,TMR4_TIMER2,XBAR1_INOUT37,GPIO5_IO00,SRC_BT_CFG05,,ENET_QOS_TX_CLK,ENET_QOS_REF_CLK,GPIO11_IO00,,, +GPIO_DISP_B2_00,VIDEO_MUX_LCDIF_DATA08,WDOG1_B,MQS_RIGHT,ENET_1G_TX_ER,SAI1_TX_DATA03,GPIO5_IO01,SRC_BT_CFG06,,ENET_QOS_TX_ER,,GPIO11_IO01,,, +GPIO_DISP_B2_01,VIDEO_MUX_LCDIF_DATA09,USDHC1_VSELECT,MQS_LEFT,WDOG2_B,SAI1_TX_DATA02,GPIO5_IO02,SRC_BT_CFG07,,EWM_OUT_B,CCM_ENET_REF_CLK_25M,GPIO11_IO02,,, +GPIO_DISP_B2_02,VIDEO_MUX_LCDIF_DATA10,ENET_TX_DATA00,PIT1_TRIGGER3,ARM_TRACE00,SAI1_TX_DATA01,GPIO5_IO03,SRC_BT_CFG08,,ENET_QOS_TX_DATA00,,GPIO11_IO03,,, +GPIO_DISP_B2_03,VIDEO_MUX_LCDIF_DATA11,ENET_TX_DATA01,PIT1_TRIGGER2,ARM_TRACE01,SAI1_MCLK,GPIO5_IO04,SRC_BT_CFG09,,ENET_QOS_TX_DATA01,,GPIO11_IO04,,, +GPIO_DISP_B2_04,VIDEO_MUX_LCDIF_DATA12,ENET_TX_EN,PIT1_TRIGGER1,ARM_TRACE02,SAI1_RX_SYNC,GPIO5_IO05,SRC_BT_CFG10,,ENET_QOS_TX_EN,,GPIO11_IO05,,, +GPIO_DISP_B2_05,VIDEO_MUX_LCDIF_DATA13,ENET_TX_CLK,ENET_REF_CLK,ARM_TRACE03,SAI1_RX_BCLK,GPIO5_IO06,SRC_BT_CFG11,,ENET_QOS_TX_CLK,,GPIO11_IO06,,, +GPIO_DISP_B2_06,VIDEO_MUX_LCDIF_DATA14,ENET_RX_DATA00,LPUART7_TXD,ARM_TRACE_CLK,SAI1_RX_DATA00,GPIO5_IO07,,,ENET_QOS_RX_DATA00,,GPIO11_IO07,,, +GPIO_DISP_B2_07,VIDEO_MUX_LCDIF_DATA15,ENET_RX_DATA01,LPUART7_RXD,ARM_TRACE_SWO,SAI1_TX_DATA00,GPIO5_IO08,,,ENET_QOS_RX_DATA01,,GPIO11_IO08,,, +GPIO_DISP_B2_08,VIDEO_MUX_LCDIF_DATA16,ENET_RX_EN,LPUART8_TXD,ARM_CM7_EVENTO,SAI1_TX_BCLK,GPIO5_IO09,,,ENET_QOS_RX_EN,LPUART1_TXD,GPIO11_IO09,,, +GPIO_DISP_B2_09,VIDEO_MUX_LCDIF_DATA17,ENET_RX_ER,LPUART8_RXD,ARM_CM7_EVENTI,SAI1_TX_SYNC,GPIO5_IO10,,,ENET_QOS_RX_ER,LPUART1_RXD,GPIO11_IO10,,, +GPIO_DISP_B2_10,VIDEO_MUX_LCDIF_DATA18,EMVSIM2_IO,LPUART2_TXD,WDOG2_RESET_B_DEB,XBAR1_INOUT38,GPIO5_IO11,LPI2C3_SCL,,ENET_QOS_RX_ER,SPDIF_IN,GPIO11_IO11,,, +GPIO_DISP_B2_11,VIDEO_MUX_LCDIF_DATA19,EMVSIM2_CLK,LPUART2_RXD,WDOG1_RESET_B_DEB,XBAR1_INOUT39,GPIO5_IO12,LPI2C3_SDA,,ENET_QOS_CRS,SPDIF_OUT,GPIO11_IO12,,, +GPIO_DISP_B2_12,VIDEO_MUX_LCDIF_DATA20,EMVSIM2_RST,FLEXCAN1_TX,LPUART2_CTS_B,XBAR1_INOUT40,GPIO5_IO13,LPI2C4_SCL,,ENET_QOS_COL,LPSPI4_SCK,GPIO11_IO13,,, +GPIO_DISP_B2_13,VIDEO_MUX_LCDIF_DATA21,EMVSIM2_SVEN,FLEXCAN1_RX,LPUART2_RTS_B,ENET_REF_CLK,GPIO5_IO14,LPI2C4_SDA,,ENET_QOS_1588_EVENT0_OUT,LPSPI4_SIN,GPIO11_IO14,,, +GPIO_DISP_B2_14,VIDEO_MUX_LCDIF_DATA22,EMVSIM2_PD,WDOG2_B,VIDEO_MUX_EXT_DCIC1,ENET_1G_REF_CLK,GPIO5_IO15,FLEXCAN1_TX,,ENET_QOS_1588_EVENT0_IN,LPSPI4_SOUT,GPIO11_IO15,,, +GPIO_DISP_B2_15,VIDEO_MUX_LCDIF_DATA23,EMVSIM2_POWER_FAIL,WDOG1_B,VIDEO_MUX_EXT_DCIC2,PIT1_TRIGGER0,GPIO5_IO16,FLEXCAN1_RX,,ENET_QOS_1588_EVENT0_AUX_IN,LPSPI4_PCS0,GPIO11_IO16,,, +GPIO_AD_00,EMVSIM1_IO,FLEXCAN2_TX,ENET_1G_1588_EVENT1_IN,GPT2_CAPTURE1,FLEXPWM1_PWM0_A,GPIO2_IO31,LPUART7_TXD,,FLEXIO2_D00,FLEXSPI2_B_SS1_B,GPIO8_IO31,,ACMP1_IN1, +GPIO_AD_01,EMVSIM1_CLK,FLEXCAN2_RX,ENET_1G_1588_EVENT1_OUT,GPT2_CAPTURE2,FLEXPWM1_PWM0_B,GPIO3_IO00,LPUART7_RXD,,FLEXIO2_D01,FLEXSPI2_A_SS1_B,GPIO9_IO00,,ACMP1_IN2, +GPIO_AD_02,EMVSIM1_RST,LPUART7_CTS_B,ENET_1G_1588_EVENT2_IN,GPT2_COMPARE1,FLEXPWM1_PWM1_A,GPIO3_IO01,LPUART8_TXD,,FLEXIO2_D02,VIDEO_MUX_EXT_DCIC1,GPIO9_IO01,,ACMP1_IN3, +GPIO_AD_03,EMVSIM1_SVEN,LPUART7_RTS_B,ENET_1G_1588_EVENT2_OUT,GPT2_COMPARE2,FLEXPWM1_PWM1_B,GPIO3_IO02,LPUART8_RXD,,FLEXIO2_D03,VIDEO_MUX_EXT_DCIC2,GPIO9_IO02,,ACMP1_IN4, +GPIO_AD_04,EMVSIM1_PD,LPUART8_CTS_B,ENET_1G_1588_EVENT3_IN,GPT2_COMPARE3,FLEXPWM1_PWM2_A,GPIO3_IO03,WDOG1_B,,FLEXIO2_D04,TMR4_TIMER0,GPIO9_IO03,,ACMP2_IN1, +GPIO_AD_05,EMVSIM1_POWER_FAIL,LPUART8_RTS_B,ENET_1G_1588_EVENT3_OUT,GPT2_CLK,FLEXPWM1_PWM2_B,GPIO3_IO04,WDOG2_B,,FLEXIO2_D05,TMR4_TIMER1,GPIO9_IO04,,ACMP2_IN2, +GPIO_AD_06,USB_OTG2_OC,FLEXCAN1_TX,EMVSIM2_IO,GPT3_CAPTURE1,VIDEO_MUX_CSI_DATA15,GPIO3_IO05,ENET_1588_EVENT1_IN,,FLEXIO2_D06,TMR4_TIMER2,GPIO9_IO05,ADC1_CH0A,, +GPIO_AD_07,USB_OTG2_PWR,FLEXCAN1_RX,EMVSIM2_CLK,GPT3_CAPTURE2,VIDEO_MUX_CSI_DATA14,GPIO3_IO06,ENET_1588_EVENT1_OUT,,FLEXIO2_D07,TMR4_TIMER3,GPIO9_IO06,ADC1_CH0B,, +GPIO_AD_08,USBPHY2_OTG_ID,LPI2C1_SCL,EMVSIM2_RST,GPT3_COMPARE1,VIDEO_MUX_CSI_DATA13,GPIO3_IO07,ENET_1588_EVENT2_IN,,FLEXIO2_D08,,GPIO9_IO07,ADC1_CH1A,, +GPIO_AD_09,USBPHY1_OTG_ID,LPI2C1_SDA,EMVSIM2_SVEN,GPT3_COMPARE2,VIDEO_MUX_CSI_DATA12,GPIO3_IO08,ENET_1588_EVENT2_OUT,,FLEXIO2_D09,,GPIO9_IO08,ADC1_CH1B,, +GPIO_AD_10,USB_OTG1_PWR,LPI2C1_SCLS,EMVSIM2_PD,GPT3_COMPARE3,VIDEO_MUX_CSI_DATA11,GPIO3_IO09,ENET_1588_EVENT3_IN,,FLEXIO2_D10,,GPIO9_IO09,ADC1_CH2A,, +GPIO_AD_11,USB_OTG1_OC,LPI2C1_SDAS,EMVSIM2_POWER_FAIL,GPT3_CLK,VIDEO_MUX_CSI_DATA10,GPIO3_IO10,ENET_1588_EVENT3_OUT,,FLEXIO2_D11,,GPIO9_IO10,ADC1_CH2B,, +GPIO_AD_12,SPDIF_LOCK,LPI2C1_HREQ,GPT1_CAPTURE1,FLEXSPI1_B_DATA03,VIDEO_MUX_CSI_PIXCLK,GPIO3_IO11,ENET_TX_DATA03,,FLEXIO2_D12,EWM_OUT_B,GPIO9_IO11,"ADC1_CH3A,ADC2_CH3A",, +GPIO_AD_13,SPDIF_SR_CLK,PIT1_TRIGGER0,GPT1_CAPTURE2,FLEXSPI1_B_DATA02,VIDEO_MUX_CSI_MCLK,GPIO3_IO12,ENET_TX_DATA02,,FLEXIO2_D13,REF_CLK_32K,GPIO9_IO12,"ADC1_CH3B,ADC2_CH3B",, +GPIO_AD_14,SPDIF_EXT_CLK,REF_CLK_24M,GPT1_COMPARE1,FLEXSPI1_B_DATA01,VIDEO_MUX_CSI_VSYNC,GPIO3_IO13,ENET_RX_CLK,,FLEXIO2_D14,CCM_ENET_REF_CLK_25M,GPIO9_IO13,"ADC1_CH4A,ADC2_CH4A",, +GPIO_AD_15,SPDIF_IN,LPUART10_TXD,GPT1_COMPARE2,FLEXSPI1_B_DATA00,VIDEO_MUX_CSI_HSYNC,GPIO3_IO14,ENET_TX_ER,,FLEXIO2_D15,,GPIO9_IO14,"ADC1_CH4B,ADC2_CH4B",, +GPIO_AD_16,SPDIF_OUT,LPUART10_RXD,GPT1_COMPARE3,FLEXSPI1_B_SCLK,VIDEO_MUX_CSI_DATA09,GPIO3_IO15,ENET_RX_DATA03,,FLEXIO2_D16,ENET_1G_MDC,GPIO9_IO15,"ADC1_CH5A,ADC2_CH5A",, +GPIO_AD_17,SAI1_MCLK,ACMP1_OUT,GPT1_CLK,FLEXSPI1_A_DQS,VIDEO_MUX_CSI_DATA08,GPIO3_IO16,ENET_RX_DATA02,,FLEXIO2_D17,ENET_1G_MDIO,GPIO9_IO16,"ADC1_CH5B,ADC2_CH5B",ACMP1_OUT, +GPIO_AD_18,SAI1_RX_SYNC,ACMP2_OUT,LPSPI1_PCS1,FLEXSPI1_A_SS0_B,VIDEO_MUX_CSI_DATA07,GPIO3_IO17,ENET_CRS,,FLEXIO2_D18,LPI2C2_SCL,GPIO9_IO17,ADC2_CH0A,ACMP2_OUT, +GPIO_AD_19,SAI1_RX_BCLK,ACMP3_OUT,LPSPI1_PCS2,FLEXSPI1_A_SCLK,VIDEO_MUX_CSI_DATA06,GPIO3_IO18,ENET_COL,,FLEXIO2_D19,LPI2C2_SDA,GPIO9_IO18,ADC2_CH0B,ACMP3_OUT, +GPIO_AD_20,SAI1_RX_DATA00,ACMP4_OUT,LPSPI1_PCS3,FLEXSPI1_A_DATA00,VIDEO_MUX_CSI_DATA05,GPIO3_IO19,KPP_ROW07,,FLEXIO2_D20,ENET_QOS_1588_EVENT2_OUT,GPIO9_IO19,ADC2_CH1A,ACMP4_OUT, +GPIO_AD_21,SAI1_TX_DATA00,,LPSPI2_PCS1,FLEXSPI1_A_DATA01,VIDEO_MUX_CSI_DATA04,GPIO3_IO20,KPP_COL07,,FLEXIO2_D21,ENET_QOS_1588_EVENT2_IN,GPIO9_IO20,ADC2_CH1B,, +GPIO_AD_22,SAI1_TX_BCLK,,LPSPI2_PCS2,FLEXSPI1_A_DATA02,VIDEO_MUX_CSI_DATA03,GPIO3_IO21,KPP_ROW06,,FLEXIO2_D22,ENET_QOS_1588_EVENT3_OUT,GPIO9_IO21,ADC2_CH2A,, +GPIO_AD_23,SAI1_TX_SYNC,,LPSPI2_PCS3,FLEXSPI1_A_DATA03,VIDEO_MUX_CSI_DATA02,GPIO3_IO22,KPP_COL06,,FLEXIO2_D23,ENET_QOS_1588_EVENT3_IN,GPIO9_IO22,ADC2_CH2B,, +GPIO_AD_24,LPUART1_TXD,LPSPI2_SCK,VIDEO_MUX_CSI_DATA00,ENET_RX_EN,FLEXPWM2_PWM0_A,GPIO3_IO23,KPP_ROW05,,FLEXIO2_D24,LPI2C4_SCL,GPIO9_IO23,ADC2_CH6A,, +GPIO_AD_25,LPUART1_RXD,LPSPI2_PCS0,VIDEO_MUX_CSI_DATA01,ENET_RX_ER,FLEXPWM2_PWM0_B,GPIO3_IO24,KPP_COL05,,FLEXIO2_D25,LPI2C4_SDA,GPIO9_IO24,ADC2_CH6B,, +GPIO_AD_26,LPUART1_CTS_B,LPSPI2_SOUT,SEMC_CSX01,ENET_RX_DATA00,FLEXPWM2_PWM1_A,GPIO3_IO25,KPP_ROW04,,FLEXIO2_D26,ENET_QOS_MDC,GPIO9_IO25,,ACMP2_IN3, +GPIO_AD_27,LPUART1_RTS_B,LPSPI2_SIN,SEMC_CSX02,ENET_RX_DATA01,FLEXPWM2_PWM1_B,GPIO3_IO26,KPP_COL04,,FLEXIO2_D27,ENET_QOS_MDIO,GPIO9_IO26,,ACMP2_IN4, +GPIO_AD_28,LPSPI1_SCK,LPUART5_TXD,SEMC_CSX03,ENET_TX_EN,FLEXPWM2_PWM2_A,GPIO3_IO27,KPP_ROW03,,FLEXIO2_D28,VIDEO_MUX_EXT_DCIC1,GPIO9_IO27,,ACMP3_IN1, +GPIO_AD_29,LPSPI1_PCS0,LPUART5_RXD,ENET_REF_CLK,ENET_TX_CLK,FLEXPWM2_PWM2_B,GPIO3_IO28,KPP_COL03,,FLEXIO2_D29,VIDEO_MUX_EXT_DCIC2,GPIO9_IO28,,ACMP3_IN2, +GPIO_AD_30,LPSPI1_SOUT,USB_OTG2_OC,FLEXCAN2_TX,ENET_TX_DATA00,LPUART3_TXD,GPIO3_IO29,KPP_ROW02,,FLEXIO2_D30,WDOG2_RESET_B_DEB,GPIO9_IO29,,ACMP3_IN3, +GPIO_AD_31,LPSPI1_SIN,USB_OTG2_PWR,FLEXCAN2_RX,ENET_TX_DATA01,LPUART3_RXD,GPIO3_IO30,KPP_COL02,,FLEXIO2_D31,WDOG1_RESET_B_DEB,GPIO9_IO30,,ACMP3_IN4, +GPIO_AD_32,LPI2C1_SCL,USBPHY2_OTG_ID,PGMC_PMIC_RDY,ENET_MDC,USDHC1_CD_B,GPIO3_IO31,KPP_ROW01,,LPUART10_TXD,ENET_1G_MDC,GPIO9_IO31,,ACMP4_IN1, +GPIO_AD_33,LPI2C1_SDA,USBPHY1_OTG_ID,XBAR1_INOUT17,ENET_MDIO,USDHC1_WP,GPIO4_IO00,KPP_COL01,,LPUART10_RXD,ENET_1G_MDIO,GPIO10_IO00,,ACMP4_IN2, +GPIO_AD_34,ENET_1G_1588_EVENT0_IN,USB_OTG1_PWR,XBAR1_INOUT18,ENET_1588_EVENT0_IN,USDHC1_VSELECT,GPIO4_IO01,KPP_ROW00,,LPUART10_CTS_B,WDOG1_ANY,GPIO10_IO01,,ACMP4_IN3, +GPIO_AD_35,ENET_1G_1588_EVENT0_OUT,USB_OTG1_OC,XBAR1_INOUT19,ENET_1588_EVENT0_OUT,USDHC1_RESET_B,GPIO4_IO02,KPP_COL00,,LPUART10_RTS_B,FLEXSPI1_B_SS1_B,GPIO10_IO02,,ACMP4_IN4, diff --git a/ports/mimxrt/boards/MIMXRT1176_clock_config.c b/ports/mimxrt/boards/MIMXRT1176_clock_config.c new file mode 100644 index 0000000000..4e01448ba3 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1176_clock_config.c @@ -0,0 +1,693 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +#include CLOCK_CONFIG_H +#include "fsl_iomuxc.h" +#include "fsl_dcdc.h" +#include "fsl_pmu.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) { + BOARD_BootClockRUN(); +} + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +/* This function should not run from SDRAM since it will change SEMC configuration. */ +AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void)); +void UpdateSemcClock(void) { + /* Enable self-refresh mode and update semc clock root to 200MHz. */ + SEMC->IPCMD = 0xA55A000D; + while ((SEMC->INTR & 0x3) == 0) { + ; + } + SEMC->INTR = 0x3; + SEMC->DCCR = 0x0B; + /* + * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only + * need to change the SEMC clock root here. If customer is using their own DCD and + * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be + * adjusted here to fine tune the SDRAM performance + */ + CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602; +} +#endif +#endif + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ + +#ifndef SKIP_POWER_ADJUSTMENT +#if __CORTEX_M == 7 +#define BYPASS_LDO_LPSR 1 +#define SKIP_LDO_ADJUSTMENT 1 +#elif __CORTEX_M == 4 +#define SKIP_DCDC_ADJUSTMENT 1 +#define SKIP_FBB_ENABLE 1 +#endif +#endif + +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ +}; + +const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = { + .pllDiv2En = true, +}; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ +}; + +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = { + .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ + .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ + .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ +}; + +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) { + clock_root_config_t rootCfg = {0}; + + #if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT) + if ((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU)) { + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); + } else { + /* Set 1.125V for production samples to align with data sheet requirement */ + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V); + } + #endif + + #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE) + /* Check if FBB need to be enabled in OverDrive(OD) mode */ + if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); + } else { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); + } + #endif + + #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR + PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); + PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); + #endif + + #if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT) + pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; + pmu_static_lpsr_dig_config_t lpsrDigConfig; + + if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) { + PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); + PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); + } + + if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) { + PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); + lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; + PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); + } + #endif + + /* PLL LDO shall be enabled first before enable PLLs */ + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 16M */ + ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + CLOCK_OSC_GateOscRc400M(true); + + /* Init OSC RC 48M */ + CLOCK_OSC_EnableOsc48M(true); + CLOCK_OSC_EnableOsc48MDiv2(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { + } + + /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + #if __CORTEX_M == 7 + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); + #endif + #if __CORTEX_M == 4 + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); + #endif + + /* + * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code. + */ + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Bypass Sys Pll1. */ + // CLOCK_SetPllBypass(kCLOCK_PllSys1, true); + + /* Init Sys Pll1 and enable PllSys1_Div2 output */ + CLOCK_InitSysPll1(&sysPll1Config_BOARD_BootClockRUN); + + + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); + + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); + + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); + + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); + + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); + + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Init Video Pll. */ + CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN); + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ + #if __CORTEX_M == 7 + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); + #endif + + /* Configure M4 using SYS_PLL3_PFD3_CLK */ + #if __CORTEX_M == 4 + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); + #endif + + /* Configure BUS using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); + + /* Configure BUS_LPSR using SYS_PLL3_CLK */ + /* BUS_LPSR must not be more than 120MHz */ + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); + + /* Configure SEMC using SYS_PLL2_PFD1_CLK */ + #ifndef SKIP_SEMC_INIT + rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); + #endif + + #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) + #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + UpdateSemcClock(); + #endif + #endif + + /* Configure CSSYS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); + + /* Configure CSTRACE using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); + + // Strange settings for SYSTICK: 24MHz for M4, 100kHz for M7 ? + /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ + #if __CORTEX_M == 4 + rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); + #endif + + /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ + #if __CORTEX_M == 7 + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); + #endif + + /* Configure ADC1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); + + /* Configure ADC2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure GPT1 using OSC_24M*/ + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOsc24MOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); + + /* Configure GPT2 using OSC_24M */ + rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOsc24MOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); + + /* Configure GPT3 using OSC_24M */ + rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOsc24MOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg); + + /* Configure GPT4 using OSC_24M */ + rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOsc24MOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg); + + /* Configure GPT5 using OSC_24M */ + rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOsc24MOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg); + + /* Configure GPT6 using OSC_24M */ + rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOsc24MOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg); + + /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ + #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); + #endif + + /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg); + + /* Configure CAN1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART1 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); + + /* Configure LPUART2 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); + + /* Configure LPUART3 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg); + + /* Configure LPUART4 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg); + + /* Configure LPUART5 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg); + + /* Configure LPUART6 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg); + + /* Configure LPUART7 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg); + + /* Configure LPUART8 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg); + + /* Configure LPUART9 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg); + + /* Configure LPUART10 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg); + + /* Configure LPUART11 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg); + + /* Configure LPUART12 using SYS_PLL3_PFD3_CLK */ + rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg); + + + /* Configure LPI2C1 using SYS_PLL3_DIV2 (240MHz) */ + rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); + + /* Configure LPI2C2 using SYS_PLL3_DIV2 (240MHz) */ + rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg); + + /* Configure LPI2C3 using SYS_PLL3_DIV2 (240MHz) */ + rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg); + + /* Configure LPI2C4 using SYS_PLL3_DIV2 (240MHz) */ + rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg); + + /* Configure LPI2C5 using SYS_PLL3_OUT (480MHz) */ + rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out; + rootCfg.div = 8; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); + + /* Configure LPI2C6 using SYS_PLL3_OUT (480MHz) */ + rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out; + rootCfg.div = 8; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg); + + + /* Configure LPSPI1 using SYS_PLL_3_PDF2 (270MHz) */ + rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); + + /* Configure LPSPI2 using SYS_PLL_3_PDF2 (270MHz) */ + rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg); + + /* Configure LPSPI3 using SYS_PLL_3_PDF2 (270MHz) */ + rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg); + + /* Configure LPSPI4 using SYS_PLL_3_PDF2 (270MHz) */ + rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg); + + /* Configure LPSPI5 using SYS_PLL_3_PDF2 (270MHz) */ + rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg); + + /* Configure LPSPI6 using SYS_PLL_3_PDF2 (270MHz) */ + rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg); + + + /* Configure EMV1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg); + + /* Configure EMV2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg); + + /* Configure ENET1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); + + /* Configure ENET2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); + + /* Configure ENET_QOS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg); + + /* Configure ENET_25M using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg); + + /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); + + /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg); + + /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg); + + /* Configure USDHC1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure ASRC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MQS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg); + + /* Configure MIC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure SPDIF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure SAI1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOsc24MOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure GC355 using PLL_VIDEO_CLK */ + rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg); + + /* Configure LCDIF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); + + /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg); + + /* Configure MIPI_REF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg); + + /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg); + + /* Configure CSI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg); + + /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg); + + /* Configure CSI2_UI using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg); + + /* Configure CSI using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg); + + /* Configure CKO1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Tx clock source. */ + IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK; + /* Set ENET_1G Tx clock source. */ + IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK; + /* Set GPT3 High frequency reference clock source. */ + IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK; + /* Set GPT4 High frequency reference clock source. */ + IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK; + /* Set GPT5 High frequency reference clock source. */ + IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK; + /* Set GPT6 High frequency reference clock source. */ + IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK; + + #if __CORTEX_M == 7 + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); + #else + SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4); + #endif +} diff --git a/ports/mimxrt/boards/MIMXRT1176_clock_config.h b/ports/mimxrt/boards/MIMXRT1176_clock_config.h new file mode 100644 index 0000000000..df2748a658 --- /dev/null +++ b/ports/mimxrt/boards/MIMXRT1176_clock_config.h @@ -0,0 +1,210 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */ +#endif + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL +#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 160000000UL // 160MHz +#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 120000000UL // 120MHz +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL +#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 60000000UL // 60MHz +#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 60000000UL // 60MHz +#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 60000000UL // 60MHz +#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 60000000UL // 60MHz +#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 60000000UL // 60MHz +#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 60000000UL // 60MHz +#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 13500000UL // 135MHz +#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 13500000UL // 135MHz +#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 13500000UL // 135MHz +#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 13500000UL // 135MHz +#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 13500000UL // 135MHz +#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 13500000UL // 135MHz +#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 74250000UL +#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL +#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL + + +// Configuration for all instances of peripherals are identical +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL // 60MHz +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 135000000UL // 135MHz +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 160000000UL // 160MHz +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 74250000UL // 74.25MHz +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/ports/mimxrt/boards/OLIMEX_RT1010/mpconfigboard.h b/ports/mimxrt/boards/OLIMEX_RT1010/mpconfigboard.h index 8c6d159fb7..6f4c528f9b 100644 --- a/ports/mimxrt/boards/OLIMEX_RT1010/mpconfigboard.h +++ b/ports/mimxrt/boards/OLIMEX_RT1010/mpconfigboard.h @@ -57,6 +57,7 @@ #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, 0, kIOMUXC_GPR_SAI3MClkOutputDir } #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, 0, kDmaRequestMuxSai3Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, 0, kDmaRequestMuxSai3Tx } +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ diff --git a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h index d366b4535d..37ff6a94c2 100644 --- a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h +++ b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h @@ -73,6 +73,7 @@ #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir } #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx } +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ @@ -116,6 +117,8 @@ // Etherner PIN definitions // No reset and interrupt pin by intention +#define ENET_RESET_PIN NULL +#define ENET_INT_PIN NULL #define IOMUX_TABLE_ENET \ { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \ diff --git a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk index 2312d11311..82a95c493c 100644 --- a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk +++ b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk @@ -12,3 +12,5 @@ MICROPY_HW_SDRAM_SIZE = 0x2000000 # 32MB MICROPY_PY_LWIP = 1 MICROPY_PY_USSL = 1 MICROPY_SSL_MBEDTLS = 1 + +CFLAGS += -DSPI_RETRY_TIMES=1000000 \ No newline at end of file diff --git a/ports/mimxrt/boards/TEENSY40/mpconfigboard.h b/ports/mimxrt/boards/TEENSY40/mpconfigboard.h index 877573d038..07da87db10 100644 --- a/ports/mimxrt/boards/TEENSY40/mpconfigboard.h +++ b/ports/mimxrt/boards/TEENSY40/mpconfigboard.h @@ -66,6 +66,7 @@ #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir } #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ diff --git a/ports/mimxrt/boards/TEENSY41/mpconfigboard.h b/ports/mimxrt/boards/TEENSY41/mpconfigboard.h index 3c6a05185d..7fe97fd9cc 100644 --- a/ports/mimxrt/boards/TEENSY41/mpconfigboard.h +++ b/ports/mimxrt/boards/TEENSY41/mpconfigboard.h @@ -66,6 +66,7 @@ #define I2S_IOMUXC_GPR_MODE { 0, kIOMUXC_GPR_SAI1MClkOutputDir, kIOMUXC_GPR_SAI2MClkOutputDir } #define I2S_DMA_REQ_SRC_RX { 0, kDmaRequestMuxSai1Rx, kDmaRequestMuxSai2Rx } #define I2S_DMA_REQ_SRC_TX { 0, kDmaRequestMuxSai1Tx, kDmaRequestMuxSai2Tx } +#define I2S_AUDIO_PLL_CLOCK (2U) #define I2S_GPIO(_hwid, _fn, _mode, _pin, _iomux) \ { \ @@ -113,8 +114,8 @@ #define ENET_PHY_OPS phydp83825_ops // Ethernet PIN definitions -#define ENET_RESET_PIN pin_GPIO_B0_14 -#define ENET_INT_PIN pin_GPIO_B0_15 +#define ENET_RESET_PIN &pin_GPIO_B0_14 +#define ENET_INT_PIN &pin_GPIO_B0_15 #define IOMUX_TABLE_ENET \ { IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \ diff --git a/ports/mimxrt/boards/common.ld b/ports/mimxrt/boards/common.ld index 3aaa14c83b..c2aa369f66 100644 --- a/ports/mimxrt/boards/common.ld +++ b/ports/mimxrt/boards/common.ld @@ -96,7 +96,7 @@ SECTIONS .text : { . = ALIGN(4); - *(EXCLUDE_FILE(*fsl_flexspi.o *gc*.o *vm.o *parse.o *runtime*.o *mpirq.o *map.o) .text*) /* .text* sections (code) */ + *(EXCLUDE_FILE(*fsl_flexspi.o *gc.o *vm.o *parse*.o *runtime*.o *map.o *mpirq.o ) .text*) /* .text* sections (code) */ *(.rodata) /* .rodata sections (constants, strings, etc.) */ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ *(.glue_7) /* glue arm to thumb code */ diff --git a/ports/mimxrt/boards/make-flexram-config.py b/ports/mimxrt/boards/make-flexram-config.py index 5d9c1a8c7c..1afa7f7985 100644 --- a/ports/mimxrt/boards/make-flexram-config.py +++ b/ports/mimxrt/boards/make-flexram-config.py @@ -169,6 +169,43 @@ def mimxrt_106x_gen_code(extract_dict): ) +def mimxrt_1176_gen_code(extract_dict): + flexram_bank_cfg = "0b" + avail_flexram = extract_dict["fsl_ram_bank_size"] * extract_dict["fsl_bank_nbr"] + flexram_configurable_ocram = ( + extract_dict["ocram_size"] % 524288 + ) # 512kB OCRAM are not part of FlexRAM configurable memory + + if ( + flexram_configurable_ocram + extract_dict["dtcm_size"] + extract_dict["itcm_size"] + ) > avail_flexram: + raise ValueError("Configuration exceeds available FlexRAM!") + + for size, pattern in ( + (flexram_configurable_ocram, "01"), + (extract_dict["dtcm_size"], "10"), + (extract_dict["itcm_size"], "11"), + ): + for _ in range(0, size, extract_dict["fsl_ram_bank_size"]): + flexram_bank_cfg += pattern + + # Generate GPR Register config + print(".equ __iomux_gpr14_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x38)) + print(".equ __iomux_gpr16_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x40)) + print(".equ __iomux_gpr17_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x44)) + print(".equ __iomux_gpr18_adr, 0x{:08X}".format(extract_dict["gpr_base_addr"] + 0x48)) + print( + ".equ __iomux_gpr17_value, 0x{:08X} /* {}k OCRAM (512k OCRAM, {}k from FlexRAM), {}k DTCM, {}k ITCM */".format( + int(flexram_bank_cfg, 2) & 0xFFFF, + extract_dict["ocram_size"] // 1024, + flexram_configurable_ocram // 1024, + extract_dict["dtcm_size"] // 1024, + extract_dict["itcm_size"] // 1024, + ) + ) + print(".equ __iomux_gpr18_value, 0x{:08X}".format((int(flexram_bank_cfg, 2) >> 16) & 0xFFFF)) + + def main(defines_file, features_file, ld_script, controller): dispatcher = { "MIMXRT1011": (mimxrt_default_parser, mimxrt_default_gen_code), @@ -177,6 +214,7 @@ def main(defines_file, features_file, ld_script, controller): "MIMXRT1052": (mimxrt_default_parser, mimxrt_default_gen_code), "MIMXRT1062": (mimxrt_default_parser, mimxrt_106x_gen_code), "MIMXRT1064": (mimxrt_default_parser, mimxrt_106x_gen_code), + "MIMXRT1176": (mimxrt_default_parser, mimxrt_1176_gen_code), } extractor, code_generator = dispatcher[controller] diff --git a/ports/mimxrt/boards/make-pins.py b/ports/mimxrt/boards/make-pins.py index 441676adde..9d11feb13a 100644 --- a/ports/mimxrt/boards/make-pins.py +++ b/ports/mimxrt/boards/make-pins.py @@ -21,6 +21,9 @@ regexes = [ r"IOMUXC_(?PGPIO_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", r"IOMUXC_(?PGPIO_AD_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", r"IOMUXC_(?PGPIO_SD_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_(?PGPIO_EMC_B\d_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_(?PGPIO_DISP_B\d_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", + r"IOMUXC_(?PGPIO_LPSR_\d\d)_(?P\w+) (?P\w+), (?P\w+), (?P\w+), (?P\w+), (?P\w+)", ] @@ -62,6 +65,7 @@ class Pin(object): def parse_adc(self, adc_str): adc_regex = r"ADC(?P\d*)_IN(?P\d*)" + lpadc_regex = r"ADC(?P\d*)_CH(?P\d*)" # LPADC for MIMXRT11xx chips matches = re.finditer(adc_regex, adc_str, re.MULTILINE) for match in matches: @@ -69,6 +73,16 @@ class Pin(object): AdcFunction(instance=match.group("instance"), channel=match.group("channel")) ) + matches = re.finditer(lpadc_regex, adc_str, re.MULTILINE) + for match in matches: + self.adc_fns.append( + AdcFunction( + peripheral="LPADC", + instance=match.group("instance"), + channel=match.group("channel"), + ) + ) + def parse_af(self, af_idx, af_strs_in): pass @@ -104,18 +118,16 @@ class Pin(object): self.print_pin_af() self.print_pin_adc() - if self.adc_fns: - print( - "const machine_pin_obj_t pin_{0} = PIN({0}, {1}, {2}, pin_{0}_af, {3}, pin_{0}_adc);\n".format( - self.name, self.gpio, int(self.pin), len(self.adc_fns) - ) - ) - else: - print( - "const machine_pin_obj_t pin_{0} = PIN({0}, {1}, {2}, pin_{0}_af, {3}, NULL);\n".format( - self.name, self.gpio, int(self.pin), len(self.adc_fns) - ) + print( + "const machine_pin_obj_t pin_{0} = {1}({0}, {2}, {3}, pin_{0}_af, {4}, {5});\n".format( + self.name, + "PIN_LPSR" if "LPSR" in self.name else "PIN", + self.gpio, + int(self.pin), + len(self.adc_fns), + "pin_{}_adc".format(self.name) if self.adc_fns else "NULL", ) + ) else: raise ValueError("Pin '{}' has no alternative functions".format(self.name)) @@ -126,13 +138,14 @@ class Pin(object): class AdcFunction(object): """Holds the information associated with a pins ADC function.""" - def __init__(self, instance, channel): + def __init__(self, instance, channel, peripheral="ADC"): + self.peripheral = peripheral self.instance = instance self.channel = channel def print(self): """Prints the C representation of this AF.""" - print(f" PIN_ADC(ADC{self.instance}, {self.channel}),") + print(f" PIN_ADC({self.peripheral}{self.instance}, {self.channel}),") class AlternateFunction(object): @@ -190,11 +203,8 @@ class Pins(object): if pin and row[0]: # Only add board pins that have a name self.board_pins.append(NamedPin(row[0], pin.pad, pin.idx)) - def parse_af_file(self, filename, iomux_filename, pad_col, af_start_col): - af_end_col = af_start_col + MAX_AF - + def parse_af_file(self, filename, iomux_filename): iomux_pin_config = dict() - with open(iomux_filename, "r") as ipt: input_str = ipt.read() for regex in regexes: @@ -213,16 +223,23 @@ class Pins(object): with open(filename, "r") as csvfile: rows = csv.reader(csvfile) header = next(rows) + # Extract indexes from header row + pad_col = header.index("Pad") + adc_col = header.index("ADC") + acmp_col = header.index("ACMP") + # for idx, row in enumerate(rows): pad = row[pad_col] gpio, pin = row[6].split("_") pin_number = pin.lstrip("IO") - pin = Pin(pad, gpio, pin_number, idx=idx) + if any(s in pad for s in ("SNVS", "WAKEUP")): + continue + # Parse alternate functions af_idx = 0 - for af_idx, af in enumerate(row[af_start_col:af_end_col]): + for af_idx, af in enumerate(row[(pad_col + 1) : adc_col]): if af and af_supported(af): pin.add_af( AlternateFunction( @@ -235,7 +252,7 @@ class Pins(object): ) ) - pin.parse_adc(row[ADC_COL]) + pin.parse_adc(row[adc_col]) self.cpu_pins.append(pin) @@ -363,7 +380,7 @@ def main(): if args.af_filename: print("// --af {:s}".format(args.af_filename)) - pins.parse_af_file(args.af_filename, args.iomux_filename, 0, 1) + pins.parse_af_file(args.af_filename, args.iomux_filename) if args.board_filename: print("// --board {:s}".format(args.board_filename)) diff --git a/ports/mimxrt/boards/mimxrt_prefix.c b/ports/mimxrt/boards/mimxrt_prefix.c index 938efc8104..09c0aa109e 100644 --- a/ports/mimxrt/boards/mimxrt_prefix.c +++ b/ports/mimxrt/boards/mimxrt_prefix.c @@ -35,3 +35,17 @@ .adc_list = (_adc_list), \ } \ +#define PIN_LPSR(_name, _gpio, _pin, _af_list, _adc_list_len, _adc_list) \ + { \ + .base = { &machine_pin_type }, \ + .name = MP_QSTR_##_name, \ + .gpio = (_gpio), \ + .pin = (uint32_t)(_pin), \ + .muxRegister = (uint32_t)&(IOMUXC_LPSR->SW_MUX_CTL_PAD[kIOMUXC_LPSR_SW_MUX_CTL_PAD_##_name]), \ + .configRegister = (uint32_t)&(IOMUXC_LPSR->SW_PAD_CTL_PAD[kIOMUXC_LPSR_SW_PAD_CTL_PAD_##_name]), \ + .af_list_len = (uint8_t)(sizeof((_af_list)) / sizeof(machine_pin_af_obj_t)), \ + .adc_list_len = (_adc_list_len), \ + .af_list = (_af_list), \ + .adc_list = (_adc_list), \ + } \ + diff --git a/ports/mimxrt/eth.c b/ports/mimxrt/eth.c index 50e1cbb0fe..ad015941a2 100644 --- a/ports/mimxrt/eth.c +++ b/ports/mimxrt/eth.c @@ -43,7 +43,9 @@ #include "hal/phy/mdio/enet/fsl_enet_mdio.h" #include "hal/phy/device/phyksz8081/fsl_phyksz8081.h" #include "hal/phy/device/phydp83825/fsl_phydp83825.h" +#include "hal/phy/device/phydp83848/fsl_phydp83848.h" #include "hal/phy/device/phylan8720/fsl_phylan8720.h" +#include "hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.h" #include "eth.h" #include "lwip/etharp.h" @@ -53,50 +55,9 @@ #include "ticks.h" -// Configuration values -enet_config_t enet_config; -phy_config_t phyConfig = {0}; - -// Prepare the buffer configuration. - #define ENET_RXBD_NUM (5) #define ENET_TXBD_NUM (5) -AT_NONCACHEABLE_SECTION_ALIGN(enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT); -AT_NONCACHEABLE_SECTION_ALIGN(enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT); -SDK_ALIGN(uint8_t g_rxDataBuff[ENET_RXBD_NUM][SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT)], - ENET_BUFF_ALIGNMENT); -SDK_ALIGN(uint8_t g_txDataBuff[ENET_TXBD_NUM][SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT)], - ENET_BUFF_ALIGNMENT); - -// ENET Handles & Buffers -enet_handle_t g_handle; - -static mdio_handle_t mdioHandle = {.ops = &enet_ops}; -static phy_handle_t phyHandle = {.phyAddr = ENET_PHY_ADDRESS, .mdioHandle = &mdioHandle, .ops = &ENET_PHY_OPS}; - -enet_buffer_config_t buffConfig[] = {{ - ENET_RXBD_NUM, - ENET_TXBD_NUM, - SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT), - SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT), - &g_rxBuffDescrip[0], - &g_txBuffDescrip[0], - &g_rxDataBuff[0][0], - &g_txDataBuff[0][0], - #if FSL_ENET_DRIVER_VERSION >= 0x020300 - 0, - 0, - NULL - #endif - }}; - -static uint8_t hw_addr[6]; // The MAC address field -eth_t eth_instance; - -#define PHY_INIT_TIMEOUT_MS (10000) -#define PHY_AUTONEGO_TIMEOUT_US (5000000) - typedef struct _eth_t { uint32_t trace_flags; struct netif netif; @@ -113,16 +74,108 @@ typedef struct _iomux_table_t { uint32_t configValue; } iomux_table_t; +// ETH0 buffers and handles +static AT_NONCACHEABLE_SECTION_ALIGN(enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT); +static AT_NONCACHEABLE_SECTION_ALIGN(enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT); +static SDK_ALIGN(uint8_t g_rxDataBuff[ENET_RXBD_NUM][SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT)], + ENET_BUFF_ALIGNMENT); +static SDK_ALIGN(uint8_t g_txDataBuff[ENET_TXBD_NUM][SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT)], + ENET_BUFF_ALIGNMENT); + +// ENET Handles & Buffers +static enet_handle_t g_handle; +static mdio_handle_t mdioHandle = {.ops = &enet_ops}; +static phy_handle_t phyHandle; +eth_t eth_instance0; + +static enet_buffer_config_t buffConfig[] = {{ + ENET_RXBD_NUM, + ENET_TXBD_NUM, + SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT), + SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT), + &g_rxBuffDescrip[0], + &g_txBuffDescrip[0], + &g_rxDataBuff[0][0], + &g_txDataBuff[0][0], + #if FSL_ENET_DRIVER_VERSION >= 0x020300 + true, + true, + NULL, + #endif + }}; + static const iomux_table_t iomux_table_enet[] = { IOMUX_TABLE_ENET }; -#define IOTE (iomux_table_enet[i]) +static uint8_t hw_addr[6]; // The MAC address field -#define TRACE_ASYNC_EV (0x0001) -#define TRACE_ETH_TX (0x0002) -#define TRACE_ETH_RX (0x0004) -#define TRACE_ETH_FULL (0x0008) +#if defined(ENET_DUAL_PORT) + +// ETH1 buffers and handles +static AT_NONCACHEABLE_SECTION_ALIGN(enet_rx_bd_struct_t g_rxBuffDescrip_1[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT); +static AT_NONCACHEABLE_SECTION_ALIGN(enet_tx_bd_struct_t g_txBuffDescrip_1[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT); +static SDK_ALIGN(uint8_t g_rxDataBuff_1[ENET_RXBD_NUM][SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT)], + ENET_BUFF_ALIGNMENT); +static SDK_ALIGN(uint8_t g_txDataBuff_1[ENET_TXBD_NUM][SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT)], + ENET_BUFF_ALIGNMENT); + +static enet_handle_t g_handle_1; +static mdio_handle_t mdioHandle_1 = {.ops = &enet_ops}; +static phy_handle_t phyHandle_1; +eth_t eth_instance1; + +static enet_buffer_config_t buffConfig_1[] = {{ + ENET_RXBD_NUM, + ENET_TXBD_NUM, + SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT), + SDK_SIZEALIGN(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT), + &g_rxBuffDescrip_1[0], + &g_txBuffDescrip_1[0], + &g_rxDataBuff_1[0][0], + &g_txDataBuff_1[0][0], + #if FSL_ENET_DRIVER_VERSION >= 0x020300 + true, + true, + NULL, + #endif + }}; + +static const iomux_table_t iomux_table_enet_1[] = { + IOMUX_TABLE_ENET_1 +}; + +static uint8_t hw_addr_1[6]; // The MAC address field + +#endif + +#if defined(ENET_DUAL_PORT) +#if defined MIMXRT117x_SERIES +#define ENET_1 ENET_1G +#else +#define ENET_1 ENET2 +#endif +#else +#define ENET_1 ENET +#endif + +#define PHY_AUTONEGO_TIMEOUT_US (5000000) +#define PHY_SETTLE_TIME_US (1000) +// Settle time must be 500000 for the 1G interface +#define PHY_SETTLE_TIME_US_1 (500000) +#define ENET_RESET_LOW_TIME_US (10000) +#define ENET_RESET_WAIT_TIME_US (30000) + +#define IOTE (iomux_table[i]) + +#ifndef ENET_TX_CLK_OUTPUT +#define ENET_TX_CLK_OUTPUT true +#endif + +#define TRACE_ASYNC_EV (0x0001) +#define TRACE_ETH_TX (0x0002) +#define TRACE_ETH_RX (0x0004) +#define TRACE_ETH_FULL (0x0008) STATIC void eth_trace(eth_t *self, size_t len, const void *data, unsigned int flags) { if (((flags & NETUTILS_TRACE_IS_TX) && (self->trace_flags & TRACE_ETH_TX)) @@ -186,106 +239,146 @@ void eth_irq_handler(ENET_Type *base, enet_handle_t *handle, } } -// eth_init: Set up GPIO and the transceiver -void eth_init(eth_t *self, int mac_idx, const phy_operations_t *phy_ops, int phy_addr, bool phy_clock) { - - self->netif.num = mac_idx; // Set the interface number +// Configure the ethernet clock +STATIC uint32_t eth_clock_init(int eth_id, bool phy_clock) { CLOCK_EnableClock(kCLOCK_Iomuxc); - gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; - (void)gpio_config; + #if defined MIMXRT117x_SERIES - #ifdef ENET_RESET_PIN - // Configure the Reset Pin - const machine_pin_obj_t *reset_pin = &ENET_RESET_PIN; - const machine_pin_af_obj_t *af_obj = pin_find_af(reset_pin, PIN_AF_MODE_ALT5); + clock_root_config_t rootCfg = {0}; - IOMUXC_SetPinMux(reset_pin->muxRegister, af_obj->af_mode, 0, 0, reset_pin->configRegister, 0U); - IOMUXC_SetPinConfig(reset_pin->muxRegister, af_obj->af_mode, 0, 0, reset_pin->configRegister, - pin_generate_config(PIN_PULL_DISABLED, PIN_MODE_OUT, PIN_DRIVE_5, reset_pin->configRegister)); - GPIO_PinInit(reset_pin->gpio, reset_pin->pin, &gpio_config); - #endif - - #ifdef ENET_INT_PIN - // Configure the Int Pin - const machine_pin_obj_t *int_pin = &ENET_INT_PIN; - af_obj = pin_find_af(int_pin, PIN_AF_MODE_ALT5); - - IOMUXC_SetPinMux(int_pin->muxRegister, af_obj->af_mode, 0, 0, int_pin->configRegister, 0U); - IOMUXC_SetPinConfig(int_pin->muxRegister, af_obj->af_mode, 0, 0, int_pin->configRegister, - pin_generate_config(PIN_PULL_UP_47K, PIN_MODE_IN, PIN_DRIVE_5, int_pin->configRegister)); - GPIO_PinInit(int_pin->gpio, int_pin->pin, &gpio_config); - #endif - - // Configure the Transceiver Pins, Settings except for CLK: - // Slew Rate Field: Fast Slew Rate, Drive Strength, R0/5, Speed max(200MHz) - // Open Drain Disabled, Pull Enabled, Pull 100K Ohm Pull Up - // Hysteresis Disabled - - for (int i = 0; i < ARRAY_SIZE(iomux_table_enet); i++) { - IOMUXC_SetPinMux(IOTE.muxRegister, IOTE.muxMode, IOTE.inputRegister, IOTE.inputDaisy, IOTE.configRegister, IOTE.inputOnfield); - IOMUXC_SetPinConfig(IOTE.muxRegister, IOTE.muxMode, IOTE.inputRegister, IOTE.inputDaisy, IOTE.configRegister, IOTE.configValue); + if (eth_id == MP_HAL_MAC_ETH0) { + // Generate 50M root clock. + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; // 500 MHz + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); + // 50M ENET_REF_CLOCK output to PHY and ENET module. + // if required, handle phy_clock direction here + IOMUXC_GPR->GPR4 |= 0x3; + } else { + // Generate 125M root clock. + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; // 500 MHz + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); + IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK; /* bit1:iomuxc_gpr_enet_clk_dir + bit0:GPR_ENET_TX_CLK_SEL(internal or OSC) */ } + return CLOCK_GetRootClockFreq(kCLOCK_Root_Bus); + + #else const clock_enet_pll_config_t config = { .enableClkOutput = phy_clock, .enableClkOutput25M = false, .loopDivider = 1 }; CLOCK_InitEnetPll(&config); - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); // Do not use the 25 MHz MII clock - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, phy_clock); // Set the clock pad direction + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); // Drive ENET_REF_CLK from PAD + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, phy_clock); // Enable output driver + + return CLOCK_GetFreq(kCLOCK_IpgClk); - // Reset transceiver - // pull up the ENET_INT before RESET. - #ifdef ENET_INT_PIN - GPIO_WritePinOutput(int_pin->gpio, int_pin->pin, 1); #endif +} - #ifdef ENET_RESET_PIN - GPIO_WritePinOutput(reset_pin->gpio, reset_pin->pin, 0); - mp_hal_delay_us(1000); - GPIO_WritePinOutput(reset_pin->gpio, reset_pin->pin, 1); - mp_hal_delay_us(1000); - #endif +// eth_gpio_init: Configure the GPIO pins +STATIC void eth_gpio_init(const iomux_table_t iomux_table[], size_t iomux_table_size, + const machine_pin_obj_t *reset_pin, const machine_pin_obj_t *int_pin) { - mp_hal_get_mac(0, hw_addr); + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 1, kGPIO_NoIntmode}; + (void)gpio_config; + const machine_pin_af_obj_t *af_obj; - phyHandle.ops = phy_ops; - phyConfig.phyAddr = phy_addr; - phyConfig.autoNeg = true; - mdioHandle.resource.base = ENET; - mdioHandle.resource.csrClock_Hz = CLOCK_GetFreq(kCLOCK_IpgClk); + if (reset_pin != NULL) { + // Configure the Reset Pin + af_obj = pin_find_af(reset_pin, PIN_AF_MODE_ALT5); + + IOMUXC_SetPinMux(reset_pin->muxRegister, af_obj->af_mode, 0, 0, reset_pin->configRegister, 0U); + IOMUXC_SetPinConfig(reset_pin->muxRegister, af_obj->af_mode, 0, 0, reset_pin->configRegister, + pin_generate_config(PIN_PULL_DISABLED, PIN_MODE_OUT, PIN_DRIVE_5, reset_pin->configRegister)); + GPIO_PinInit(reset_pin->gpio, reset_pin->pin, &gpio_config); + } + + if (int_pin != NULL) { + // Configure the Int Pin + af_obj = pin_find_af(int_pin, PIN_AF_MODE_ALT5); + + IOMUXC_SetPinMux(int_pin->muxRegister, af_obj->af_mode, 0, 0, int_pin->configRegister, 0U); + IOMUXC_SetPinConfig(int_pin->muxRegister, af_obj->af_mode, 0, 0, int_pin->configRegister, + pin_generate_config(PIN_PULL_UP_47K, PIN_MODE_IN, PIN_DRIVE_5, int_pin->configRegister)); + GPIO_PinInit(int_pin->gpio, int_pin->pin, &gpio_config); + } + + // Configure the Transceiver Pins, Settings except for CLK: + // Slew Rate Field: Fast Slew Rate, Drive Strength, R0/5, Speed max(200MHz) + // Open Drain Disabled, Pull Enabled, Pull 100K Ohm Pull Up + // Hysteresis Disabled + for (int i = 0; i < iomux_table_size; i++) { + IOMUXC_SetPinMux(IOTE.muxRegister, IOTE.muxMode, IOTE.inputRegister, IOTE.inputDaisy, IOTE.configRegister, IOTE.inputOnfield); + IOMUXC_SetPinConfig(IOTE.muxRegister, IOTE.muxMode, IOTE.inputRegister, IOTE.inputDaisy, IOTE.configRegister, IOTE.configValue); + } + + // Reset the transceiver + if (reset_pin != NULL) { + GPIO_PinWrite(reset_pin->gpio, reset_pin->pin, 0); + mp_hal_delay_us(ENET_RESET_LOW_TIME_US); + GPIO_PinWrite(reset_pin->gpio, reset_pin->pin, 1); + mp_hal_delay_us(ENET_RESET_WAIT_TIME_US); + } +} + +// eth_phy_init: Initilaize the PHY interface +STATIC void eth_phy_init(phy_handle_t *phyHandle, phy_config_t *phy_config, + phy_speed_t *speed, phy_duplex_t *duplex, uint32_t phy_settle_time) { - // Init the PHY interface & negotiate the speed bool link = false; bool autonego = false; - phy_speed_t speed = kENET_MiiSpeed100M; - phy_duplex_t duplex = kENET_MiiFullDuplex; + phy_config->autoNeg = true; - - status_t status = PHY_Init(&phyHandle, &phyConfig); + status_t status = PHY_Init(phyHandle, phy_config); if (status == kStatus_Success) { - if (phyConfig.autoNeg) { - uint64_t t = ticks_us64() + PHY_AUTONEGO_TIMEOUT_US; - // Wait for auto-negotiation success and link up - do { - PHY_GetAutoNegotiationStatus(&phyHandle, &autonego); - PHY_GetLinkStatus(&phyHandle, &link); - if (autonego && link) { - break; - } - } while (ticks_us64() < t); - if (!autonego) { - mp_raise_msg(&mp_type_OSError, MP_ERROR_TEXT("PHY Auto-negotiation failed.")); + uint64_t t = ticks_us64() + PHY_AUTONEGO_TIMEOUT_US; + // Wait for auto-negotiation success and link up + do { + PHY_GetAutoNegotiationStatus(phyHandle, &autonego); + PHY_GetLinkStatus(phyHandle, &link); + if (autonego && link) { + break; } - PHY_GetLinkSpeedDuplex(&phyHandle, &speed, &duplex); - } else { - PHY_SetLinkSpeedDuplex(&phyHandle, speed, duplex); + } while (ticks_us64() < t); + if (!autonego) { + mp_raise_msg(&mp_type_OSError, MP_ERROR_TEXT("PHY Auto-negotiation failed.")); } + PHY_GetLinkSpeedDuplex(phyHandle, speed, duplex); } else { mp_raise_msg(&mp_type_OSError, MP_ERROR_TEXT("PHY Init failed.")); } + mp_hal_delay_us(phy_settle_time); +} + +// eth_init: Set up GPIO and the transceiver +void eth_init_0(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int phy_addr, bool phy_clock) { + // Configuration values + enet_config_t enet_config; + + phy_config_t phy_config = {0}; + + uint32_t source_clock = eth_clock_init(eth_id, phy_clock); + + eth_gpio_init(iomux_table_enet, ARRAY_SIZE(iomux_table_enet), ENET_RESET_PIN, ENET_INT_PIN); + + mp_hal_get_mac(0, hw_addr); + + // Init the PHY interface & negotiate the speed + phyHandle.ops = phy_ops; + phy_config.phyAddr = phy_addr; + phyHandle.mdioHandle = &mdioHandle; + mdioHandle.resource.base = ENET; + mdioHandle.resource.csrClock_Hz = source_clock; + + phy_speed_t speed = kENET_MiiSpeed100M; + phy_duplex_t duplex = kENET_MiiFullDuplex; + eth_phy_init(&phyHandle, &phy_config, &speed, &duplex, PHY_SETTLE_TIME_US); ENET_Reset(ENET); ENET_GetDefaultConfig(&enet_config); @@ -297,14 +390,70 @@ void eth_init(eth_t *self, int mac_idx, const phy_operations_t *phy_ops, int phy // Set interrupt enet_config.interrupt |= ENET_TX_INTERRUPT | ENET_RX_INTERRUPT; - ENET_Init(ENET, &g_handle, &enet_config, &buffConfig[0], hw_addr, CLOCK_GetFreq(kCLOCK_IpgClk)); + ENET_Init(ENET, &g_handle, &enet_config, &buffConfig[0], hw_addr, source_clock); ENET_SetCallback(&g_handle, eth_irq_handler, (void *)self); NVIC_SetPriority(ENET_IRQn, IRQ_PRI_PENDSV); ENET_EnableInterrupts(ENET, ENET_RX_INTERRUPT); ENET_ClearInterruptStatus(ENET, ENET_TX_INTERRUPT | ENET_RX_INTERRUPT | ENET_ERR_INTERRUPT); + NVIC_SetPriority(ENET_IRQn, IRQ_PRI_PENDSV); + ENET_EnableInterrupts(ENET, ENET_RX_INTERRUPT); ENET_ActiveRead(ENET); } +#if defined(ENET_DUAL_PORT) + +// eth_init: Set up GPIO and the transceiver +void eth_init_1(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int phy_addr, bool phy_clock) { + // Configuration values + enet_config_t enet_config; + + phy_config_t phy_config = {0}; + + uint32_t source_clock = eth_clock_init(eth_id, phy_clock); + + eth_gpio_init(iomux_table_enet_1, ARRAY_SIZE(iomux_table_enet_1), ENET_1_RESET_PIN, ENET_1_INT_PIN); + + #if defined MIMXRT117x_SERIES + NVIC_SetPriority(ENET_1G_MAC0_Tx_Rx_1_IRQn, IRQ_PRI_PENDSV); + NVIC_SetPriority(ENET_1G_MAC0_Tx_Rx_2_IRQn, IRQ_PRI_PENDSV); + NVIC_SetPriority(ENET_1G_IRQn, IRQ_PRI_PENDSV); + EnableIRQ(ENET_1G_MAC0_Tx_Rx_1_IRQn); + EnableIRQ(ENET_1G_MAC0_Tx_Rx_2_IRQn); + phy_speed_t speed = kENET_MiiSpeed1000M; + #else + NVIC_SetPriority(ENET2_IRQn, IRQ_PRI_PENDSV); + phy_speed_t speed = kENET_MiiSpeed100M; + #endif + + mp_hal_get_mac(1, hw_addr_1); + + // Init the PHY interface & negotiate the speed + phyHandle_1.ops = phy_ops; + phy_config.phyAddr = phy_addr; + phyHandle_1.mdioHandle = &mdioHandle_1; + mdioHandle_1.resource.base = ENET_1; + mdioHandle_1.resource.csrClock_Hz = source_clock; + + phy_duplex_t duplex = kENET_MiiFullDuplex; + eth_phy_init(&phyHandle_1, &phy_config, &speed, &duplex, PHY_SETTLE_TIME_US_1); + + ENET_Reset(ENET_1); + ENET_GetDefaultConfig(&enet_config); + enet_config.miiSpeed = (enet_mii_speed_t)speed; + enet_config.miiDuplex = (enet_mii_duplex_t)duplex; + // Enable checksum generation by the ENET controller + enet_config.txAccelerConfig = kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled; + // Set interrupt + enet_config.interrupt = ENET_TX_INTERRUPT | ENET_RX_INTERRUPT; + + ENET_Init(ENET_1, &g_handle_1, &enet_config, &buffConfig_1[0], hw_addr_1, source_clock); + ENET_SetCallback(&g_handle_1, eth_irq_handler, (void *)self); + ENET_ClearInterruptStatus(ENET_1, ENET_TX_INTERRUPT | ENET_RX_INTERRUPT | ENET_ERR_INTERRUPT); + ENET_EnableInterrupts(ENET_1, ENET_RX_INTERRUPT); + ENET_ActiveRead(ENET_1); +} + +#endif // Initialize the phy interface STATIC int eth_mac_init(eth_t *self) { return 0; @@ -312,6 +461,8 @@ STATIC int eth_mac_init(eth_t *self) { // Deinit the interface STATIC void eth_mac_deinit(eth_t *self) { + // Just as a reminder: Calling ENET_Deinit() twice causes the board to stall + // with a bus error. Reason unclear. So don't do that for now (or ever). } void eth_set_trace(eth_t *self, uint32_t value) { @@ -332,7 +483,7 @@ STATIC err_t eth_send_frame_blocking(ENET_Type *base, enet_handle_t *handle, uin if (status != kStatus_ENET_TxFrameBusy) { break; } - ticks_delay_us64(100); + ticks_delay_us64(base == ENET ? 100 : 20); } return status; } @@ -340,12 +491,20 @@ STATIC err_t eth_send_frame_blocking(ENET_Type *base, enet_handle_t *handle, uin STATIC err_t eth_netif_output(struct netif *netif, struct pbuf *p) { // This function should always be called from a context where PendSV-level IRQs are disabled status_t status; + ENET_Type *enet = ENET; + enet_handle_t *handle = &g_handle; + + #if defined ENET_DUAL_PORT + if (netif->state == ð_instance1) { + enet = ENET_1; + handle = &g_handle_1; + } + #endif - LINK_STATS_INC(link.xmit); eth_trace(netif->state, (size_t)-1, p, NETUTILS_TRACE_IS_TX | NETUTILS_TRACE_NEWLINE); if (p->next == NULL) { - status = eth_send_frame_blocking(ENET, &g_handle, p->payload, p->len); + status = eth_send_frame_blocking(enet, handle, p->payload, p->len); } else { // frame consists of several parts. Copy them together and send them size_t length = 0; @@ -356,7 +515,7 @@ STATIC err_t eth_netif_output(struct netif *netif, struct pbuf *p) { length += p->len; p = p->next; } - status = eth_send_frame_blocking(ENET, &g_handle, tx_frame, length); + status = eth_send_frame_blocking(enet, handle, tx_frame, length); } return status == kStatus_Success ? ERR_OK : ERR_BUF; } @@ -378,20 +537,27 @@ STATIC err_t eth_netif_init(struct netif *netif) { } STATIC void eth_lwip_init(eth_t *self) { + struct netif *n = &self->netif; ip_addr_t ipconfig[4]; - IP4_ADDR(&ipconfig[0], 192, 168, 0, 2); + + self->netif.hwaddr_len = 6; + if (self == ð_instance0) { + memcpy(self->netif.hwaddr, hw_addr, 6); + IP4_ADDR(&ipconfig[0], 192, 168, 0, 2); + #if defined ENET_DUAL_PORT + } else { + memcpy(self->netif.hwaddr, hw_addr_1, 6); + IP4_ADDR(&ipconfig[0], 192, 168, 0, 3); + #endif + } IP4_ADDR(&ipconfig[1], 255, 255, 255, 0); IP4_ADDR(&ipconfig[2], 192, 168, 0, 1); IP4_ADDR(&ipconfig[3], 8, 8, 8, 8); - self->netif.hwaddr_len = 6; - memcpy(self->netif.hwaddr, hw_addr, 6); - MICROPY_PY_LWIP_ENTER - struct netif *n = &self->netif; n->name[0] = 'e'; - n->name[1] = '0'; + n->name[1] = (self == ð_instance0 ? '0' : '1'); netif_add(n, &ipconfig[0], &ipconfig[1], &ipconfig[2], self, eth_netif_init, ethernet_input); netif_set_hostname(n, "MPY"); netif_set_default(n); @@ -433,7 +599,11 @@ int eth_link_status(eth_t *self) { } } else { bool link; + #if defined ENET_DUAL_PORT + PHY_GetLinkStatus(self == ð_instance0 ? &phyHandle : &phyHandle_1, &link); + #else PHY_GetLinkStatus(&phyHandle, &link); + #endif if (link) { return 1; // link up } else { @@ -463,6 +633,10 @@ int eth_stop(eth_t *self) { } void eth_low_power_mode(eth_t *self, bool enable) { + #if defined ENET_DUAL_PORT + ENET_EnableSleepMode(self == ð_instance0 ? ENET : ENET_1, enable); + #else ENET_EnableSleepMode(ENET, enable); + #endif } #endif // defined(MICROPY_HW_ETH_MDC) diff --git a/ports/mimxrt/eth.h b/ports/mimxrt/eth.h index b225d00492..afb5d5edf3 100644 --- a/ports/mimxrt/eth.h +++ b/ports/mimxrt/eth.h @@ -28,9 +28,14 @@ #define MICROPY_INCLUDED_MIMXRT_ETH_H typedef struct _eth_t eth_t; -extern eth_t eth_instance; +extern eth_t eth_instance0; +extern eth_t eth_instance1; +void eth_init_0(eth_t *self, int mac_idx, const phy_operations_t *phy_ops, int phy_addr, bool phy_clock); + +#if defined(ENET_DUAL_PORT) +void eth_init_1(eth_t *self, int mac_idx, const phy_operations_t *phy_ops, int phy_addr, bool phy_clock); +#endif -void eth_init(eth_t *self, int mac_idx, const phy_operations_t *phy_ops, int phy_addr, bool phy_clock); void eth_set_trace(eth_t *self, uint32_t value); struct netif *eth_netif(eth_t *self); int eth_link_status(eth_t *self); @@ -43,6 +48,7 @@ enum { PHY_DP83825, PHY_DP83848, PHY_LAN8720, + PHY_RTL8211F, }; enum { diff --git a/ports/mimxrt/hal/flexspi_hyper_flash.c b/ports/mimxrt/hal/flexspi_hyper_flash.c index c7b41658a4..a9f17f2d1c 100644 --- a/ports/mimxrt/hal/flexspi_hyper_flash.c +++ b/ports/mimxrt/hal/flexspi_hyper_flash.c @@ -51,11 +51,11 @@ __attribute__((always_inline)) static inline void clock_disable_clock(clock_ip_n static void SetFlexSPIDiv(uint32_t div) __attribute__((section(".ram_functions"))); static void SetFlexSPIDiv(uint32_t div) { - FLEXSPI_Enable(FLEXSPI, false); + FLEXSPI_Enable(BOARD_FLEX_SPI, false); clock_disable_clock(kCLOCK_FlexSpi); clock_set_div(kCLOCK_FlexspiDiv, div); /* flexspi clock 332M, DDR mode, internal clock 166M. */ clock_enable_clock(kCLOCK_FlexSpi); - FLEXSPI_Enable(FLEXSPI, true); + FLEXSPI_Enable(BOARD_FLEX_SPI, true); } status_t flexspi_nor_hyperbus_read(FLEXSPI_Type *base, uint32_t addr, uint32_t *buffer, uint32_t bytes) __attribute__((section(".ram_functions"))); diff --git a/ports/mimxrt/hal/flexspi_hyper_flash.h b/ports/mimxrt/hal/flexspi_hyper_flash.h index dbd028fd6f..fe9acea429 100644 --- a/ports/mimxrt/hal/flexspi_hyper_flash.h +++ b/ports/mimxrt/hal/flexspi_hyper_flash.h @@ -26,14 +26,24 @@ #ifndef MICROPY_INCLUDED_MIMXRT_HAL_FLEXSPI_HYPER_FLASH_H #define MICROPY_INCLUDED_MIMXRT_HAL_FLEXSPI_HYPER_FLASH_H -#include "fsl_flexspi.h" #include "mpconfigboard.h" -#include BOARD_FLASH_CONFIG_HEADER_H +#include "flexspi_flash_config.h" +#include "fsl_flexspi.h" +// #include BOARD_FLASH_CONFIG_HEADER_H + +#if defined MIMXRT117x_SERIES +#define BOARD_FLEX_SPI FLEXSPI1 +#define BOARD_FLEX_SPI_ADDR_BASE FlexSPI1_AMBA_BASE +#else +#define BOARD_FLEX_SPI FLEXSPI +#define BOARD_FLEX_SPI_ADDR_BASE FlexSPI_AMBA_BASE +#endif // Defined in boards flash_config.c extern flexspi_nor_config_t qspiflash_config; status_t flexspi_nor_hyperflash_cfi(FLEXSPI_Type *base); +void flexspi_hyper_flash_init(void); void flexspi_nor_update_lut(void); status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src, uint32_t size); diff --git a/ports/mimxrt/hal/flexspi_nor_flash.c b/ports/mimxrt/hal/flexspi_nor_flash.c index 8c04150d12..48792ec487 100644 --- a/ports/mimxrt/hal/flexspi_nor_flash.c +++ b/ports/mimxrt/hal/flexspi_nor_flash.c @@ -193,7 +193,7 @@ status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t dstAddr, co status = flexspi_nor_wait_bus_busy(base); - flexspi_nor_reset(FLEXSPI); + flexspi_nor_reset(BOARD_FLEX_SPI); return status; } diff --git a/ports/mimxrt/hal/flexspi_nor_flash.h b/ports/mimxrt/hal/flexspi_nor_flash.h index f8c31488a9..69d57da691 100644 --- a/ports/mimxrt/hal/flexspi_nor_flash.h +++ b/ports/mimxrt/hal/flexspi_nor_flash.h @@ -27,36 +27,23 @@ #define MICROPY_INCLUDED_MIMXRT_HAL_FLEXSPI_NOR_FLASH_H #include "fsl_flexspi.h" -#include "mpconfigboard.h" #include BOARD_FLASH_CONFIG_HEADER_H +#if defined MIMXRT117x_SERIES +#define BOARD_FLEX_SPI FLEXSPI1 +#define BOARD_FLEX_SPI_ADDR_BASE FlexSPI1_AMBA_BASE +#else +#define BOARD_FLEX_SPI FLEXSPI +#define BOARD_FLEX_SPI_ADDR_BASE FlexSPI_AMBA_BASE +#endif + // Defined in boards flash_config.c extern flexspi_nor_config_t qspiflash_config; status_t flexspi_nor_get_vendor_id(FLEXSPI_Type *base, uint8_t *vendorId); +status_t flexspi_nor_init(void); void flexspi_nor_update_lut(void); status_t flexspi_nor_flash_erase_sector(FLEXSPI_Type *base, uint32_t address); status_t flexspi_nor_flash_page_program(FLEXSPI_Type *base, uint32_t address, const uint32_t *src, uint32_t size); -static inline uint32_t flexspi_get_frequency(void) { - uint32_t div; - uint32_t fre; - - /* Clock divider: - 000 divided by 1 - 001 divided by 2 - 010 divided by 3 - 011 divided by 4 - 100 divided by 5 - 101 divided by 6 - 110 divided by 7 - 111 divided by 8 - */ - div = CLOCK_GetDiv(kCLOCK_FlexspiDiv); - /* Get frequency */ - fre = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (div + 0x01U); - - return fre; -} - #endif // MICROPY_INCLUDED_MIMXRT_HAL_FLEXSPI_NOR_FLASH_H diff --git a/ports/mimxrt/hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c b/ports/mimxrt/hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c new file mode 100644 index 0000000000..0c6cf82dae --- /dev/null +++ b/ports/mimxrt/hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c @@ -0,0 +1,387 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_phyrtl8211f.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the PHY RTL8211F vendor defined registers. */ +#define PHY_SPECIFIC_STATUS_REG 0x1AU /*!< The PHY specific status register. */ +#define PHY_PAGE_SELECT_REG 0x1FU /*!< The PHY page select register. */ + +/*! @brief Defines the PHY RTL8211F ID number. */ +#define PHY_CONTROL_ID1 0x001CU /*!< The PHY ID1 . */ + +/*! @brief Defines the mask flag in specific status register. */ +#define PHY_SSTATUS_LINKSTATUS_MASK 0x04U /*!< The PHY link status mask. */ +#define PHY_SSTATUS_LINKSPEED_MASK 0x30U /*!< The PHY link speed mask. */ +#define PHY_SSTATUS_LINKDUPLEX_MASK 0x08U /*!< The PHY link duplex mask. */ +#define PHY_SSTATUS_LINKSPEED_SHIFT 4U /*!< The link speed shift */ + +/*! @brief Defines the PHY RTL8211F extra page and the registers in specified page. */ +#define PHY_PAGE_RGMII_TXRX_DELAY_ADDR 0xD08U /*!< The register page including RGMII TX/RX delay setting. */ +#define PHY_RGMII_TX_DELAY_REG 0x11U /*!< The RGMII TXC delay register. */ +#define PHY_RGMII_RX_DELAY_REG 0x15U /*!< The RGMII RXC delay register. */ +#define PHY_RGMII_TX_DELAY_MASK 0x100U /*!< The RGMII TXC delay mask. */ +#define PHY_RGMII_RX_DELAY_MASK 0x8U /*!< The RGMII RXC delay mask. */ + +/*! @brief MDIO MMD Devices .*/ +#define PHY_MDIO_MMD_PCS 3U +#define PHY_MDIO_MMD_AN 7U + +/*! @brief MDIO MMD Physical Coding layer device registers .*/ +#define PHY_MDIO_PCS_EEE_CAP 0x14U /* EEE capability */ + +/*! @brief MDIO MMD AutoNegotiation device registers .*/ +#define PHY_MDIO_AN_EEE_ADV 0x3CU /* EEE advertisement */ + +/*! @brief MDIO MMD EEE mask flags. (common for adv and cap) */ +#define PHY_MDIO_EEE_100TX 0x2U +#define PHY_MDIO_EEE_1000T 0x4U + +/*! @brief Defines the timeout macro. */ +#define PHY_READID_TIMEOUT_COUNT 1000U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static status_t PHY_RTL8211F_MMD_SetDevice(phy_handle_t *handle, + uint8_t device, + uint16_t addr, + phy_mmd_access_mode_t mode); +static inline status_t PHY_RTL8211F_MMD_ReadData(phy_handle_t *handle, uint32_t *data); +static inline status_t PHY_RTL8211F_MMD_WriteData(phy_handle_t *handle, uint32_t data); +static status_t PHY_RTL8211F_MMD_Read(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t *data); +static status_t PHY_RTL8211F_MMD_Write(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t data); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +const phy_operations_t phyrtl8211f_ops = {.phyInit = PHY_RTL8211F_Init, + .phyWrite = PHY_RTL8211F_Write, + .phyRead = PHY_RTL8211F_Read, + .getAutoNegoStatus = PHY_RTL8211F_GetAutoNegotiationStatus, + .getLinkStatus = PHY_RTL8211F_GetLinkStatus, + .getLinkSpeedDuplex = PHY_RTL8211F_GetLinkSpeedDuplex, + .setLinkSpeedDuplex = PHY_RTL8211F_SetLinkSpeedDuplex, + .enableLoopback = PHY_RTL8211F_EnableLoopback}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_RTL8211F_Init(phy_handle_t *handle, const phy_config_t *config) { + uint32_t counter = PHY_READID_TIMEOUT_COUNT; + status_t result; + uint32_t regValue = 0U; + + /* Init MDIO interface. */ + MDIO_Init(handle->mdioHandle); + + /* Assign phy address. */ + handle->phyAddr = config->phyAddr; + + /* Check PHY ID. */ + do + { + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, ®Value); + if (result != kStatus_Success) { + return result; + } + counter--; + } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U)); + + if (counter == 0U) { + return kStatus_Fail; + } + + /* Reset PHY. */ + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result != kStatus_Success) { + return result; + } + + /* The RGMII specifies output TXC/RXC and TXD/RXD without any clock skew. Need to add skew on clock line + to make sure the other side sample right data. This can also be done in PCB traces. */ + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_PAGE_SELECT_REG, PHY_PAGE_RGMII_TXRX_DELAY_ADDR); + if (result != kStatus_Success) { + return result; + } + /* Set Tx Delay. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_RGMII_TX_DELAY_REG, ®Value); + if (result == kStatus_Success) { + regValue |= PHY_RGMII_TX_DELAY_MASK; + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_RGMII_TX_DELAY_REG, regValue); + if (result != kStatus_Success) { + return result; + } + } else { + return result; + } + /* Set Rx Delay. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_RGMII_RX_DELAY_REG, ®Value); + if (result == kStatus_Success) { + regValue |= PHY_RGMII_RX_DELAY_MASK; + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_RGMII_RX_DELAY_REG, regValue); + if (result != kStatus_Success) { + return result; + } + } else { + return result; + } + /* Restore to default page 0 */ + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_PAGE_SELECT_REG, 0x0); + if (result != kStatus_Success) { + return result; + } + + /* Energy Efficient Ethernet configuration */ + if (config->enableEEE) { + /* Get capabilities */ + result = PHY_RTL8211F_MMD_Read(handle, PHY_MDIO_MMD_PCS, PHY_MDIO_PCS_EEE_CAP, ®Value); + if (result == kStatus_Success) { + /* Enable EEE for 100TX and 1000T */ + result = PHY_RTL8211F_MMD_Write(handle, PHY_MDIO_MMD_AN, PHY_MDIO_AN_EEE_ADV, + regValue & (PHY_MDIO_EEE_1000T | PHY_MDIO_EEE_100TX)); + } + } else { + result = PHY_RTL8211F_MMD_Write(handle, PHY_MDIO_MMD_AN, PHY_MDIO_AN_EEE_ADV, 0); + } + if (result != kStatus_Success) { + return result; + } + + if (config->autoNeg) { + /* Set the auto-negotiation. */ + result = + MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_AUTONEG_ADVERTISE_REG, + PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK | + PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK); + if (result == kStatus_Success) { + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_1000BASET_CONTROL_REG, + PHY_1000BASET_FULLDUPLEX_MASK); + if (result == kStatus_Success) { + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value); + if (result == kStatus_Success) { + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, + (regValue | PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + } + } else { + /* Disable isolate mode */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value); + if (result != kStatus_Success) { + return result; + } + regValue &= PHY_BCTL_ISOLATE_MASK; + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); + if (result != kStatus_Success) { + return result; + } + + /* Disable the auto-negotiation and set user-defined speed/duplex configuration. */ + result = PHY_RTL8211F_SetLinkSpeedDuplex(handle, config->speed, config->duplex); + } + return result; +} + +status_t PHY_RTL8211F_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data) { + return MDIO_Write(handle->mdioHandle, handle->phyAddr, phyReg, data); +} + +status_t PHY_RTL8211F_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr) { + return MDIO_Read(handle->mdioHandle, handle->phyAddr, phyReg, dataPtr); +} + +status_t PHY_RTL8211F_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status) { + assert(status); + + status_t result; + uint32_t regValue; + + *status = false; + + /* Check auto negotiation complete. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, ®Value); + if (result == kStatus_Success) { + if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) { + *status = true; + } + } + return result; +} + +status_t PHY_RTL8211F_GetLinkStatus(phy_handle_t *handle, bool *status) { + assert(status); + + status_t result; + uint32_t regValue; + + /* Read the basic status register. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_SPECIFIC_STATUS_REG, ®Value); + if (result == kStatus_Success) { + if ((PHY_SSTATUS_LINKSTATUS_MASK & regValue) != 0U) { + /* Link up. */ + *status = true; + } else { + /* Link down. */ + *status = false; + } + } + return result; +} + +status_t PHY_RTL8211F_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex) { + assert(!((speed == NULL) && (duplex == NULL))); + + status_t result; + uint32_t regValue; + + /* Read the status register. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_SPECIFIC_STATUS_REG, ®Value); + if (result == kStatus_Success) { + if (speed != NULL) { + switch ((regValue & PHY_SSTATUS_LINKSPEED_MASK) >> PHY_SSTATUS_LINKSPEED_SHIFT) + { + case (uint32_t)kPHY_Speed10M: + *speed = kPHY_Speed10M; + break; + case (uint32_t)kPHY_Speed100M: + *speed = kPHY_Speed100M; + break; + case (uint32_t)kPHY_Speed1000M: + *speed = kPHY_Speed1000M; + break; + default: + *speed = kPHY_Speed10M; + break; + } + } + + if (duplex != NULL) { + if ((regValue & PHY_SSTATUS_LINKDUPLEX_MASK) != 0U) { + *duplex = kPHY_FullDuplex; + } else { + *duplex = kPHY_HalfDuplex; + } + } + } + return result; +} + +status_t PHY_RTL8211F_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex) { + status_t result; + uint32_t regValue; + + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value); + if (result == kStatus_Success) { + /* Disable the auto-negotiation and set according to user-defined configuration. */ + regValue &= ~PHY_BCTL_AUTONEG_MASK; + if (speed == kPHY_Speed1000M) { + regValue &= PHY_BCTL_SPEED0_MASK; + regValue |= PHY_BCTL_SPEED1_MASK; + } else if (speed == kPHY_Speed100M) { + regValue |= PHY_BCTL_SPEED0_MASK; + regValue &= ~PHY_BCTL_SPEED1_MASK; + } else { + regValue &= ~PHY_BCTL_SPEED0_MASK; + regValue &= ~PHY_BCTL_SPEED1_MASK; + } + if (duplex == kPHY_FullDuplex) { + regValue |= PHY_BCTL_DUPLEX_MASK; + } else { + regValue &= ~PHY_BCTL_DUPLEX_MASK; + } + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); + } + return result; +} + +status_t PHY_RTL8211F_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable) { + /* This PHY only supports local loopback. */ + assert(mode == kPHY_LocalLoop); + + status_t result; + uint32_t regValue; + + /* Set the loop mode. */ + if (enable) { + if (speed == kPHY_Speed1000M) { + regValue = PHY_BCTL_SPEED1_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } else if (speed == kPHY_Speed100M) { + regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } else { + regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue); + } else { + /* First read the current status in control register. */ + result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, ®Value); + if (result == kStatus_Success) { + regValue &= ~PHY_BCTL_LOOP_MASK; + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, + (regValue | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + return result; +} + +static status_t PHY_RTL8211F_MMD_SetDevice(phy_handle_t *handle, + uint8_t device, + uint16_t addr, + phy_mmd_access_mode_t mode) { + status_t result = kStatus_Success; + + /* Set Function mode of address access(b00) and device address. */ + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_CONTROL_REG, device); + if (result != kStatus_Success) { + return result; + } + + /* Set register address. */ + result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, addr); + if (result != kStatus_Success) { + return result; + } + + /* Set Function mode of data access(b01~11) and device address. */ + result = + MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_CONTROL_REG, (uint32_t)mode | (uint32_t)device); + return result; +} + +static inline status_t PHY_RTL8211F_MMD_ReadData(phy_handle_t *handle, uint32_t *data) { + return MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, data); +} + +static inline status_t PHY_RTL8211F_MMD_WriteData(phy_handle_t *handle, uint32_t data) { + return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, data); +} + +static status_t PHY_RTL8211F_MMD_Read(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t *data) { + status_t result = kStatus_Success; + result = PHY_RTL8211F_MMD_SetDevice(handle, device, addr, kPHY_MMDAccessNoPostIncrement); + if (result == kStatus_Success) { + result = PHY_RTL8211F_MMD_ReadData(handle, data); + } + return result; +} + +static status_t PHY_RTL8211F_MMD_Write(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t data) { + status_t result = kStatus_Success; + + result = PHY_RTL8211F_MMD_SetDevice(handle, device, addr, kPHY_MMDAccessNoPostIncrement); + if (result == kStatus_Success) { + result = PHY_RTL8211F_MMD_WriteData(handle, data); + } + return result; +} diff --git a/ports/mimxrt/hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.h b/ports/mimxrt/hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.h new file mode 100644 index 0000000000..225c249a6e --- /dev/null +++ b/ports/mimxrt/hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.h @@ -0,0 +1,163 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/***************************************************************************** + * PHY RTL8211F driver change log + *****************************************************************************/ + +/*! +@page driver_log Driver Change Log + +@section phyrtl8211 PHYRTL8211F + The current PHYRTL8211F driver version is 2.0.0. + + - 2.0.0 + - Initial version. +*/ + +#ifndef _FSL_PHYRTL8211F_H_ +#define _FSL_PHYRTL8211F_H_ + +#include "fsl_phy.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) + +/*! @brief PHY operations structure. */ +extern const phy_operations_t phyrtl8211f_ops; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize PHY. + * + * @param handle PHY device handle. + * @param config Pointer to structure of phy_config_t. + * @retval kStatus_Success PHY initialization succeeds + * @retval kStatus_Fail PHY initialization fails + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_Init(phy_handle_t *handle, const phy_config_t *config); + +/*! + * @brief PHY Write function. This function writes data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface reads data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param handle PHY device handle. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Gets the PHY auto-negotiation status. + * + * @param handle PHY device handle. + * @param status The auto-negotiation status of the PHY. + * - true the auto-negotiation is over. + * - false the auto-negotiation is on-going or not started. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status); + +/*! + * @brief Gets the PHY link status. + * + * @param handle PHY device handle. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY gets link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_GetLinkStatus(phy_handle_t *handle, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @brief This function gets the speed and duplex mode of PHY. User can give one of speed + * and duplex address paramter and set the other as NULL if only wants to get one of them. + * + * @param handle PHY device handle. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY gets link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex); + +/*! + * @brief Sets the PHY link speed and duplex. + * + * @param handle PHY device handle. + * @param speed Specified PHY link speed. + * @param duplex Specified PHY link duplex. + * @retval kStatus_Success PHY gets status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param handle PHY device handle. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * All loopback modes should not be set together, when one loopback mode is set + * another should be disabled. + * @param speed PHY speed for loopback mode. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_RTL8211F_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/ports/mimxrt/hal/resethandler_MIMXRT10xx.S b/ports/mimxrt/hal/resethandler_MIMXRT10xx.S index 8fe0611033..efca1a7ec6 100644 --- a/ports/mimxrt/hal/resethandler_MIMXRT10xx.S +++ b/ports/mimxrt/hal/resethandler_MIMXRT10xx.S @@ -37,6 +37,13 @@ Reset_Handler: str r1,[r0] /* store FLEXRAM configuration value to IOMUXC_GPR17 */ dsb isb +#if defined MIMXRT117x_SERIES + ldr r0, =__iomux_gpr18_adr /* load IOMUXC_GPR18 register address to R0 */ + ldr r1, =__iomux_gpr18_value /* move FlexRAM configuration value to R1 */ + str r1,[r0] /* store FLEXRAM configuration value to IOMUXC_GPR18 */ + dsb + isb +#endif ldr r0, =__iomux_gpr16_adr /* load IOMUXC_GPR16 register address to R0 */ ldr r1,[r0] /* load IOMUXC_GPR16 register value to R1 */ orr r1, r1, #4 /* set corresponding FLEXRAM_BANK_CFG_SEL bit */ diff --git a/ports/mimxrt/machine_adc.c b/ports/mimxrt/machine_adc.c index d63157d36e..36e5fafc98 100644 --- a/ports/mimxrt/machine_adc.c +++ b/ports/mimxrt/machine_adc.c @@ -29,7 +29,12 @@ #include "py/runtime.h" #include "py/mphal.h" +#if defined(MIMXRT117x_SERIES) +#include "fsl_lpadc.h" +#else #include "fsl_adc.h" +#endif + #include "fsl_gpio.h" #include "fsl_iomuxc.h" @@ -72,12 +77,14 @@ STATIC mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_ ADC_Type *adc_instance = pin->adc_list[0].instance; // NOTE: we only use the first ADC assignment - multiple assignments are not supported for now uint8_t channel = pin->adc_list[0].channel; + #if 0 // done in adc_read_u16 // Configure ADC peripheral channel adc_channel_config_t channel_config = { .channelNumber = (uint32_t)channel, .enableInterruptOnConversionCompleted = false, }; ADC_SetChannelConfig(adc_instance, 0UL, &channel_config); // NOTE: we always choose channel group '0' since we only perform software triggered conversion + #endif // Create ADC Instance machine_adc_obj_t *o = mp_obj_malloc(machine_adc_obj_t, &machine_adc_type); @@ -90,6 +97,43 @@ STATIC mp_obj_t adc_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_ } // read_u16() +#if defined(MIMXRT117x_SERIES) +STATIC mp_obj_t machine_adc_read_u16(mp_obj_t self_in) { + machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); + lpadc_conv_command_config_t adc_config; + lpadc_conv_trigger_config_t trigger_config; + + // Set ADC configuration + LPADC_GetDefaultConvCommandConfig(&adc_config); + adc_config.channelNumber = self->channel; + adc_config.sampleScaleMode = kLPADC_SamplePartScale; + LPADC_SetConvCommandConfig(self->adc, 1, &adc_config); + + // Set Trigger mode + LPADC_GetDefaultConvTriggerConfig(&trigger_config); + trigger_config.targetCommandId = 1; + LPADC_SetConvTriggerConfig(self->adc, 0U, &trigger_config); + + // Measure input voltage + LPADC_DoSoftwareTrigger(self->adc, 1U); + lpadc_conv_result_t result_struct; + while (!LPADC_GetConvResult(self->adc, &result_struct)) { + } + + return MP_OBJ_NEW_SMALL_INT(result_struct.convValue * 2); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_adc_read_u16_obj, machine_adc_read_u16); + +void machine_adc_init(void) { + lpadc_config_t adc_config; // Set ADC configuration + LPADC_GetDefaultConfig(&adc_config); + adc_config.enableAnalogPreliminary = true; + adc_config.referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + LPADC_Init(LPADC1, &adc_config); +} + +#else + STATIC mp_obj_t machine_adc_read_u16(mp_obj_t self_in) { machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); @@ -111,21 +155,6 @@ STATIC mp_obj_t machine_adc_read_u16(mp_obj_t self_in) { } STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_adc_read_u16_obj, machine_adc_read_u16); -STATIC const mp_rom_map_elem_t adc_locals_dict_table[] = { - { MP_ROM_QSTR(MP_QSTR_read_u16), MP_ROM_PTR(&machine_adc_read_u16_obj) }, -}; - -STATIC MP_DEFINE_CONST_DICT(adc_locals_dict, adc_locals_dict_table); - -MP_DEFINE_CONST_OBJ_TYPE( - machine_adc_type, - MP_QSTR_ADC, - MP_TYPE_FLAG_NONE, - make_new, adc_obj_make_new, - print, adc_obj_print, - locals_dict, &adc_locals_dict - ); - void machine_adc_init(void) { for (int i = 1; i < sizeof(adc_bases) / sizeof(ADC_Type *); ++i) { ADC_Type *adc_instance = adc_bases[i]; @@ -143,3 +172,19 @@ void machine_adc_init(void) { } } } +#endif + +STATIC const mp_rom_map_elem_t adc_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_read_u16), MP_ROM_PTR(&machine_adc_read_u16_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(adc_locals_dict, adc_locals_dict_table); + +MP_DEFINE_CONST_OBJ_TYPE( + machine_adc_type, + MP_QSTR_ADC, + MP_TYPE_FLAG_NONE, + make_new, adc_obj_make_new, + print, adc_obj_print, + locals_dict, &adc_locals_dict + ); diff --git a/ports/mimxrt/machine_i2c.c b/ports/mimxrt/machine_i2c.c index f00ba6b1ba..c0a3dee98a 100644 --- a/ports/mimxrt/machine_i2c.c +++ b/ports/mimxrt/machine_i2c.c @@ -30,6 +30,7 @@ #include "extmod/machine_i2c.h" #include "modmachine.h" #include CLOCK_CONFIG_H +#include "pin.h" #include "fsl_iomuxc.h" #include "fsl_lpi2c.h" @@ -37,13 +38,6 @@ #define DEFAULT_I2C_FREQ (400000) #define DEFAULT_I2C_DRIVE (6) -// Select USB1 PLL (480 MHz) as master lpi2c clock source -#define LPI2C_CLOCK_SOURCE_SELECT (0U) -// Clock divider for master lpi2c clock source -#define LPI2C_CLOCK_SOURCE_DIVIDER (1U) -// Get frequency of lpi2c clock = 30 MHz -#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U)) - typedef struct _machine_i2c_obj_t { mp_obj_base_t base; LPI2C_Type *i2c_inst; diff --git a/ports/mimxrt/machine_i2s.c b/ports/mimxrt/machine_i2s.c index 1733140fb5..32daad0853 100644 --- a/ports/mimxrt/machine_i2s.c +++ b/ports/mimxrt/machine_i2s.c @@ -99,7 +99,6 @@ #define NUM_I2S_USER_FORMATS (4) #define I2S_RX_FRAME_SIZE_IN_BYTES (8) -#define AUDIO_PLL_CLOCK (2U) #define SAI_CHANNEL_0 (0) #define SAI_NUM_AUDIO_CHANNELS (2U) @@ -208,42 +207,69 @@ STATIC const int8_t i2s_frame_map[NUM_I2S_USER_FORMATS][I2S_RX_FRAME_SIZE_IN_BYT // PLL output frequency = 24MHz * (.loopDivider + .numerator/.denominator) // Configuration 1: for sampling frequencies [Hz]: 8000, 12000, 16000, 24000, 32000, 48000 -// Clock frequency = 786,432,480 Hz +// Clock frequency = 786,432,000 Hz = 48000 * 64 * 256 STATIC const clock_audio_pll_config_t audioPllConfig_8000_48000 = { .loopDivider = 32, // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54 .postDivider = 1, // Divider after the PLL, should only be 1, 2, 4, 8, 16 - .numerator = 76802, // 30 bit numerator of fractional loop divider + .numerator = 76800, // 30 bit numerator of fractional loop divider .denominator = 100000, // 30 bit denominator of fractional loop divider + #if !defined(MIMXRT117x_SERIES) .src = kCLOCK_PllClkSrc24M // Pll clock source + #endif }; // Configuration 2: for sampling frequencies [Hz]: 11025, 22050, 44100 -// Clock frequency = 722,534,880 +// Clock frequency = 722,534,400 = 44100 * 64 * 256 STATIC const clock_audio_pll_config_t audioPllConfig_11025_44100 = { .loopDivider = 30, // PLL loop divider. Valid range for DIV_SELECT divider value: 27~54 .postDivider = 1, // Divider after the PLL, should only be 1, 2, 4, 8, 16 - .numerator = 10562, // 30 bit numerator of fractional loop divider + .numerator = 10560, // 30 bit numerator of fractional loop divider .denominator = 100000, // 30 bit denominator of fractional loop divider + #if !defined(MIMXRT117x_SERIES) .src = kCLOCK_PllClkSrc24M // Pll clock source + #endif }; +#if defined(MIMXRT117x_SERIES) +// for 1176 the pre_div value is used for post_div of the Audio PLL, +// which is 2**n: 0->1, 1->2, 2->4, 3->8, 4->16, 5->32 +// The divider is 8 bit and must be given as n (not n-1) +// So the total division factor is given by (2**p) * d STATIC const i2s_clock_config_t clock_config_map[] = { - {kSAI_SampleRate8KHz, &audioPllConfig_8000_48000, 5, 63}, - {kSAI_SampleRate11025Hz, &audioPllConfig_11025_44100, 3, 63}, - {kSAI_SampleRate12KHz, &audioPllConfig_8000_48000, 3, 63}, - {kSAI_SampleRate16KHz, &audioPllConfig_8000_48000, 2, 63}, - {kSAI_SampleRate22050Hz, &audioPllConfig_11025_44100, 1, 63}, - {kSAI_SampleRate24KHz, &audioPllConfig_8000_48000, 1, 63}, - {kSAI_SampleRate32KHz, &audioPllConfig_8000_48000, 1, 47}, - {kSAI_SampleRate44100Hz, &audioPllConfig_11025_44100, 0, 63}, - {kSAI_SampleRate48KHz, &audioPllConfig_8000_48000, 0, 63} + {kSAI_SampleRate8KHz, &audioPllConfig_8000_48000, 1, 192}, // 384 + {kSAI_SampleRate11025Hz, &audioPllConfig_11025_44100, 1, 128}, // 256 + {kSAI_SampleRate12KHz, &audioPllConfig_8000_48000, 1, 128}, // 256 + {kSAI_SampleRate16KHz, &audioPllConfig_8000_48000, 0, 192}, // 192 + {kSAI_SampleRate22050Hz, &audioPllConfig_11025_44100, 0, 128}, // 128 + {kSAI_SampleRate24KHz, &audioPllConfig_8000_48000, 0, 128}, // 128 + {kSAI_SampleRate32KHz, &audioPllConfig_8000_48000, 0, 96}, // 96 + {kSAI_SampleRate44100Hz, &audioPllConfig_11025_44100, 0, 64}, // 64 + {kSAI_SampleRate48KHz, &audioPllConfig_8000_48000, 0, 64} // 64 +}; + +STATIC const clock_root_t i2s_clock_mux[] = I2S_CLOCK_MUX; +#else +// for 10xx the total division factor is given by (p + 1) * (d + 1) +STATIC const i2s_clock_config_t clock_config_map[] = { + {kSAI_SampleRate8KHz, &audioPllConfig_8000_48000, 5, 63}, // 384 + {kSAI_SampleRate11025Hz, &audioPllConfig_11025_44100, 3, 63}, // 256 + {kSAI_SampleRate12KHz, &audioPllConfig_8000_48000, 3, 63}, // 256 + {kSAI_SampleRate16KHz, &audioPllConfig_8000_48000, 2, 63}, // 192 + {kSAI_SampleRate22050Hz, &audioPllConfig_11025_44100, 1, 63}, // 128 + {kSAI_SampleRate24KHz, &audioPllConfig_8000_48000, 1, 63}, // 128 + {kSAI_SampleRate32KHz, &audioPllConfig_8000_48000, 1, 47}, // 96 + {kSAI_SampleRate44100Hz, &audioPllConfig_11025_44100, 0, 63}, // 64 + {kSAI_SampleRate48KHz, &audioPllConfig_8000_48000, 0, 63} // 64 }; -STATIC const I2S_Type *i2s_base_ptr[] = I2S_BASE_PTRS; STATIC const clock_mux_t i2s_clock_mux[] = I2S_CLOCK_MUX; STATIC const clock_div_t i2s_clock_pre_div[] = I2S_CLOCK_PRE_DIV; STATIC const clock_div_t i2s_clock_div[] = I2S_CLOCK_DIV; STATIC const iomuxc_gpr_mode_t i2s_iomuxc_gpr_mode[] = I2S_IOMUXC_GPR_MODE; +#endif + +STATIC const I2S_Type *i2s_base_ptr[] = I2S_BASE_PTRS; + STATIC const dma_request_source_t i2s_dma_req_src_tx[] = I2S_DMA_REQ_SRC_TX; STATIC const dma_request_source_t i2s_dma_req_src_rx[] = I2S_DMA_REQ_SRC_RX; STATIC const gpio_map_t i2s_gpio_map[] = I2S_GPIO_MAP; @@ -674,10 +700,24 @@ STATIC void edma_i2s_callback(edma_handle_t *handle, void *userData, bool transf STATIC bool i2s_init(machine_i2s_obj_t *self) { + #if defined(MIMXRT117x_SERIES) + clock_audio_pll_config_t pll_config = *get_pll_config(self->rate); + pll_config.postDivider = get_clock_pre_divider(self->rate); + CLOCK_InitAudioPll(&pll_config); + CLOCK_SetRootClockMux(i2s_clock_mux[self->i2s_id], I2S_AUDIO_PLL_CLOCK); + CLOCK_SetRootClockDiv(i2s_clock_mux[self->i2s_id], get_clock_divider(self->rate)); + uint32_t clock_freq = CLOCK_GetFreq(kCLOCK_AudioPllOut) / get_clock_divider(self->rate); + + #else + CLOCK_InitAudioPll(get_pll_config(self->rate)); - CLOCK_SetMux(i2s_clock_mux[self->i2s_id], AUDIO_PLL_CLOCK); + CLOCK_SetMux(i2s_clock_mux[self->i2s_id], I2S_AUDIO_PLL_CLOCK); CLOCK_SetDiv(i2s_clock_pre_div[self->i2s_id], get_clock_pre_divider(self->rate)); CLOCK_SetDiv(i2s_clock_div[self->i2s_id], get_clock_divider(self->rate)); + uint32_t clock_freq = + (CLOCK_GetFreq(kCLOCK_AudioPllClk) / (get_clock_divider(self->rate) + 1U) / + (get_clock_pre_divider(self->rate) + 1U)); + #endif if (!set_iomux(self->sck, SCK, self->i2s_id)) { return false; @@ -695,7 +735,24 @@ STATIC bool i2s_init(machine_i2s_obj_t *self) { if (!set_iomux(self->mck, MCK, self->i2s_id)) { return false; } + #if defined(MIMXRT117x_SERIES) + switch (self->i2s_id) { + case 1: + IOMUXC_GPR->GPR0 |= IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK; + break; + case 2: + IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK; + break; + case 3: + IOMUXC_GPR->GPR2 |= IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK; + break; + case 4: + IOMUXC_GPR->GPR2 |= IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK; + break; + } + #else IOMUXC_EnableMode(IOMUXC_GPR, i2s_iomuxc_gpr_mode[self->i2s_id], true); + #endif } self->dma_channel = allocate_dma_channel(); @@ -743,10 +800,6 @@ STATIC bool i2s_init(machine_i2s_obj_t *self) { return false; // should never happen } - uint32_t clock_freq = - (CLOCK_GetFreq(kCLOCK_AudioPllClk) / (get_clock_divider(self->rate) + 1U) / - (get_clock_pre_divider(self->rate) + 1U)); - SAI_TxSetBitClockRate(self->i2s_inst, clock_freq, self->rate, get_dma_bits(self->mode, self->bits), SAI_NUM_AUDIO_CHANNELS); SAI_RxSetBitClockRate(self->i2s_inst, clock_freq, self->rate, get_dma_bits(self->mode, self->bits), diff --git a/ports/mimxrt/machine_pin.c b/ports/mimxrt/machine_pin.c index bb2c820100..d44e649964 100644 --- a/ports/mimxrt/machine_pin.c +++ b/ports/mimxrt/machine_pin.c @@ -149,6 +149,16 @@ void GPIO5_Combined_16_31_IRQHandler(void) { call_handler(gpiobases[5], 5, 16); } +#if defined(MIMXRT117x_SERIES) +void GPIO6_Combined_0_15_IRQHandler(void) { + call_handler(gpiobases[6], 6, 0); +} + +void GPIO6_Combined_16_31_IRQHandler(void) { + call_handler(gpiobases[6], 6, 16); +} +#endif + // Deinit all pin IRQ handlers. void machine_pin_irq_deinit(void) { for (int i = 0; i < ARRAY_SIZE(MP_STATE_PORT(machine_pin_irq_objects)); ++i) { diff --git a/ports/mimxrt/machine_pwm.c b/ports/mimxrt/machine_pwm.c index d5bb029e68..661ec16658 100644 --- a/ports/mimxrt/machine_pwm.c +++ b/ports/mimxrt/machine_pwm.c @@ -214,7 +214,11 @@ STATIC void configure_flexpwm(machine_pwm_obj_t *self) { pwm_signal_param_u16_t pwmSignal; // Initialize PWM module. + #if defined(MIMXRT117x_SERIES) + uint32_t pwmSourceClockInHz = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus); + #else uint32_t pwmSourceClockInHz = CLOCK_GetFreq(kCLOCK_IpgClk); + #endif int prescale = calc_prescaler(pwmSourceClockInHz, self->freq); if (prescale < 0) { @@ -296,10 +300,15 @@ STATIC void configure_flexpwm(machine_pwm_obj_t *self) { STATIC void configure_qtmr(machine_pwm_obj_t *self) { qtmr_config_t qtmrConfig; int prescale; + #if defined(MIMXRT117x_SERIES) + uint32_t pwmSourceClockInHz = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus); + #else + uint32_t pwmSourceClockInHz = CLOCK_GetFreq(kCLOCK_IpgClk); + #endif TMR_Type *instance = (TMR_Type *)self->instance; - prescale = calc_prescaler(CLOCK_GetFreq(kCLOCK_IpgClk), self->freq); + prescale = calc_prescaler(pwmSourceClockInHz, self->freq); if (prescale < 0) { mp_raise_ValueError(MP_ERROR_TEXT(ERRMSG_FREQ)); } @@ -311,7 +320,7 @@ STATIC void configure_qtmr(machine_pwm_obj_t *self) { } // Set up the PWM channel if (QTMR_SetupPwm_u16(instance, self->channel1, self->freq, self->duty_u16, - self->invert, CLOCK_GetFreq(kCLOCK_IpgClk) / (1 << prescale), self->is_init) == kStatus_Fail) { + self->invert, pwmSourceClockInHz / (1 << prescale), self->is_init) == kStatus_Fail) { mp_raise_ValueError(MP_ERROR_TEXT(ERRMSG_INIT)); } // Start the output @@ -325,7 +334,9 @@ STATIC void configure_pwm(machine_pwm_obj_t *self) { static bool set_frequency = true; // set the frequency only once if (set_frequency) { + #if !defined(MIMXRT117x_SERIES) CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); // Set IPG PODF to 3, divide by 4 + #endif set_frequency = false; } diff --git a/ports/mimxrt/machine_sdcard.c b/ports/mimxrt/machine_sdcard.c index 9254faf14a..35e1ef7eeb 100644 --- a/ports/mimxrt/machine_sdcard.c +++ b/ports/mimxrt/machine_sdcard.c @@ -30,7 +30,12 @@ #include "py/mperrno.h" #include "extmod/vfs.h" #include "ticks.h" + +#if defined(MIMXRT1170x_SERIES) +#include "cm7/fsl_cache.h" +#else #include "fsl_cache.h" +#endif #include "sdcard.h" diff --git a/ports/mimxrt/machine_spi.c b/ports/mimxrt/machine_spi.c index a3a6bb414e..d6aff2a329 100644 --- a/ports/mimxrt/machine_spi.c +++ b/ports/mimxrt/machine_spi.c @@ -45,6 +45,14 @@ #define DEFAULT_SPI_FIRSTBIT (kLPSPI_MsbFirst) #define DEFAULT_SPI_DRIVE (6) +#define CLOCK_DIVIDER (1) + +#if defined(MIMXRT117x_SERIES) +#define LPSPI_DMAMUX DMAMUX0 +#else +#define LPSPI_DMAMUX DMAMUX +#endif + #define MICROPY_HW_SPI_NUM MP_ARRAY_SIZE(spi_index_table) #define SCK (iomux_table[index]) diff --git a/ports/mimxrt/machine_uart.c b/ports/mimxrt/machine_uart.c index a0706c8f4f..ac9351da8a 100644 --- a/ports/mimxrt/machine_uart.c +++ b/ports/mimxrt/machine_uart.c @@ -33,6 +33,7 @@ #include "fsl_lpuart.h" #include "fsl_iomuxc.h" #include CLOCK_CONFIG_H +#include "pin.h" #define DEFAULT_UART_BAUDRATE (115200) #define DEFAULT_BUFFER_SIZE (256) @@ -221,7 +222,7 @@ STATIC mp_obj_t machine_uart_init_helper(machine_uart_obj_t *self, size_t n_args self->timeout_char = min_timeout_char; } - LPUART_Init(self->lpuart, &self->config, BOARD_BOOTCLOCKRUN_UART_CLK_ROOT); // ?? + LPUART_Init(self->lpuart, &self->config, BOARD_BOOTCLOCKRUN_UART_CLK_ROOT); LPUART_TransferCreateHandle(self->lpuart, &self->handle, LPUART_UserCallback, self); uint8_t *buffer = m_new(uint8_t, rxbuf_len + 1); LPUART_TransferStartRingBuffer(self->lpuart, &self->handle, buffer, rxbuf_len); diff --git a/ports/mimxrt/main.c b/ports/mimxrt/main.c index b81a44e278..907de373de 100644 --- a/ports/mimxrt/main.c +++ b/ports/mimxrt/main.c @@ -58,9 +58,6 @@ int main(void) { led_init(); pendsv_init(); - mp_stack_set_top(&_estack); - mp_stack_set_limit(&_estack - &_sstack - 1024); - #if MICROPY_PY_LWIP // lwIP doesn't allow to reinitialise itself by subsequent calls to this function // because the system timeout list (next_timeout) is only ever reset by BSS clearing. @@ -69,10 +66,14 @@ int main(void) { #if LWIP_MDNS_RESPONDER mdns_resp_init(); #endif + systick_enable_dispatch(SYSTICK_DISPATCH_LWIP, mod_network_lwip_poll_wrapper); #endif for (;;) { + mp_stack_set_top(&_estack); + mp_stack_set_limit(&_estack - &_sstack - 1024); + gc_init(&_gc_heap_start, &_gc_heap_end); mp_init(); diff --git a/ports/mimxrt/mbedtls/mbedtls_port.c b/ports/mimxrt/mbedtls/mbedtls_port.c index e2002274b1..a9db174726 100644 --- a/ports/mimxrt/mbedtls/mbedtls_port.c +++ b/ports/mimxrt/mbedtls/mbedtls_port.c @@ -26,14 +26,14 @@ #ifdef MICROPY_SSL_MBEDTLS -#include "fsl_trng.h" #include "mbedtls_config.h" +void trng_random_data(unsigned char *output, size_t len); int mbedtls_hardware_poll(void *data, unsigned char *output, size_t len, size_t *olen) { // assumes that TRNG_Init was called during startup *olen = len; - TRNG_GetRandomData(TRNG, output, len); + trng_random_data(output, len); return 0; } diff --git a/ports/mimxrt/mimxrt_flash.c b/ports/mimxrt/mimxrt_flash.c index fd2e7558f9..536fb60981 100644 --- a/ports/mimxrt/mimxrt_flash.c +++ b/ports/mimxrt/mimxrt_flash.c @@ -68,7 +68,7 @@ status_t flash_erase_block(uint32_t erase_addr) { SCB_CleanInvalidateDCache(); SCB_DisableDCache(); __disable_irq(); - status = flexspi_nor_flash_erase_sector(FLEXSPI, erase_addr); + status = flexspi_nor_flash_erase_sector(BOARD_FLEX_SPI, erase_addr); __enable_irq(); SCB_EnableDCache(); return status; @@ -93,7 +93,7 @@ status_t flash_write_block(uint32_t dest_addr, const uint8_t *src, uint32_t leng size = length; } __disable_irq(); - status = flexspi_nor_flash_page_program(FLEXSPI, dest_addr, (uint32_t *)src, size); + status = flexspi_nor_flash_page_program(BOARD_FLEX_SPI, dest_addr, (uint32_t *)src, size); __enable_irq(); if (status != kStatus_Success) { break; @@ -112,15 +112,15 @@ STATIC mp_obj_t mimxrt_flash_make_new(const mp_obj_type_t *type, size_t n_args, // Upload the custom flash configuration // This should be performed by the boot ROM but for some reason it is not. - FLEXSPI_UpdateLUT(FLEXSPI, 0, + FLEXSPI_UpdateLUT(BOARD_FLEX_SPI, 0, qspiflash_config.memConfig.lookupTable, ARRAY_SIZE(qspiflash_config.memConfig.lookupTable)); - // Configure FLEXSPI IP FIFO access. - FLEXSPI->MCR0 &= ~(FLEXSPI_MCR0_ARDFEN_MASK); - FLEXSPI->MCR0 &= ~(FLEXSPI_MCR0_ATDFEN_MASK); - FLEXSPI->MCR0 |= FLEXSPI_MCR0_ARDFEN(0); - FLEXSPI->MCR0 |= FLEXSPI_MCR0_ATDFEN(0); + // Configure BOARD_FLEX_SPI IP FIFO access. + BOARD_FLEX_SPI->MCR0 &= ~(FLEXSPI_MCR0_ARDFEN_MASK); + BOARD_FLEX_SPI->MCR0 &= ~(FLEXSPI_MCR0_ATDFEN_MASK); + BOARD_FLEX_SPI->MCR0 |= FLEXSPI_MCR0_ARDFEN(0); + BOARD_FLEX_SPI->MCR0 |= FLEXSPI_MCR0_ATDFEN(0); // Update information based on linker symbols. mimxrt_flash_obj.flash_base = MICROPY_HW_FLASH_STORAGE_BASE; @@ -142,7 +142,7 @@ STATIC mp_obj_t mimxrt_flash_readblocks(size_t n_args, const mp_obj_t *args) { if (n_args == 4) { offset += mp_obj_get_int(args[3]); } - memcpy(bufinfo.buf, (uint8_t *)(FlexSPI_AMBA_BASE + self->flash_base + offset), bufinfo.len); + memcpy(bufinfo.buf, (uint8_t *)(BOARD_FLEX_SPI_ADDR_BASE + self->flash_base + offset), bufinfo.len); return mp_const_none; } STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(mimxrt_flash_readblocks_obj, 3, 4, mimxrt_flash_readblocks); diff --git a/ports/mimxrt/mimxrt_sdram.c b/ports/mimxrt/mimxrt_sdram.c index 8c336bb607..c6c1776a55 100644 --- a/ports/mimxrt/mimxrt_sdram.c +++ b/ports/mimxrt/mimxrt_sdram.c @@ -29,123 +29,176 @@ #include "modmachine.h" #include "fsl_semc.h" #include "fsl_iomuxc.h" +#include "fsl_clock.h" // Linker symbols extern uint8_t __sdram_start; +#if defined(MIMXRT117x_SERIES) +// Pull Up, High drive strength +#define SDRAM_PIN_CONFIG (0x07UL) +#else +// Pull up 22K, high slew rate +#define SDRAM_PIN_CONFIG (0xE1UL) +#endif void mimxrt_sdram_init(void) { + + #if !defined(MIMXRT117x_SERIES) // Set Clocks CLOCK_InitSysPfd(kCLOCK_Pfd2, 29); // '29' PLL2 PFD2 frequency = 528MHz * 18 / 29 = 327.72MHz (with 528MHz = PLL2 frequency) CLOCK_SetMux(kCLOCK_SemcAltMux, 0); // '0' PLL2 PFD2 will be selected as alternative clock for SEMC root clock CLOCK_SetMux(kCLOCK_SemcMux, 1); // '1' SEMC alternative clock will be used as SEMC clock root CLOCK_SetDiv(kCLOCK_SemcDiv, 1); // '1' divide by 2 -> SEMC clock = 163.86 MHz + #endif // Set Pins - // Data Pins + // Data Pins 0..15 IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA00, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA00, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA00, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA01, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA01, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA01, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA02, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA02, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA02, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA03, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA03, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA03, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA04, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA04, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA04, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA05, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA05, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA05, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA06, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA06, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA06, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA07, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA07, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA07, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA08, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA08, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA08, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA09, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA09, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA09, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA10, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA10, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA10, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA11, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA11, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA11, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA12, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA12, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA12, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA13, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA13, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA13, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA14, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA14, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA14, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA15, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA15, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA15, SDRAM_PIN_CONFIG); // Address Pins IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR00, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR00, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR00, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR01, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR01, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR01, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR02, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR02, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR02, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR03, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR03, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR03, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR04, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR04, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR04, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR05, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR05, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR05, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR06, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR06, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR06, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR07, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR07, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR07, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR08, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR08, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR08, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR09, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR09, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR09, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR10, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR10, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR10, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR11, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR11, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR11, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_ADDR12, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR12, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_ADDR12, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM00, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM00, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM00, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA0, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA0, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA0, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_BA1, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA1, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_BA1, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CAS, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CAS, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CAS, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_RAS, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_RAS, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_RAS, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CLK, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CLK, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CLK, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CKE, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CKE, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CKE, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_WE, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_WE, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_WE, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM01, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM01, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM01, SDRAM_PIN_CONFIG); IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DQS, 1UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DQS, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DQS, SDRAM_PIN_CONFIG); + + #if defined(MIMXRT117x_SERIES) + // Data Pins 16..31 + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA16, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA16, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA17, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA17, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA18, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA18, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA19, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA19, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA20, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA20, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA21, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA21, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA22, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA22, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA23, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA23, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA24, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA24, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA25, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA25, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA26, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA26, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA27, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA27, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA28, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA28, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA29, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA29, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA30, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA30, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DATA31, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DATA31, SDRAM_PIN_CONFIG); + + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM02, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM02, SDRAM_PIN_CONFIG); + IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_DM03, 0UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_DM03, SDRAM_PIN_CONFIG); + + #endif // Chip Select Pins #ifndef MIMXRT_IOMUXC_SEMC_CS0 #error No SEMC CS0 defined! #endif IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS0, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS0, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS0, SDRAM_PIN_CONFIG); #ifdef MIMXRT_IOMUXC_SEMC_CS1 IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS1, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS1, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS1, SDRAM_PIN_CONFIG); #endif #ifdef MIMXRT_IOMUXC_SEMC_CS2 IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS2, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS2, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS2, SDRAM_PIN_CONFIG); #endif #ifdef MIMXRT_IOMUXC_SEMC_CS3 IOMUXC_SetPinMux(MIMXRT_IOMUXC_SEMC_CS3, 0UL); - IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS3, 0xE1UL); + IOMUXC_SetPinConfig(MIMXRT_IOMUXC_SEMC_CS3, SDRAM_PIN_CONFIG); #endif // Configure SEMC @@ -155,6 +208,36 @@ void mimxrt_sdram_init(void) { semc_cfg.dqsMode = kSEMC_Loopbackdqspad; // For more accurate timing. SEMC_Init(SEMC, &semc_cfg); + #if defined(MIMXRT117x_SERIES) + + uint32_t clock_freq = CLOCK_GetRootClockFreq(kCLOCK_Root_Semc); + + semc_sdram_config_t sdram_cfg = { + .csxPinMux = kSEMC_MUXCSX0, + .address = 0x80000000, + .memsize_kbytes = (MICROPY_HW_SDRAM_SIZE >> 10), + .portSize = kSEMC_PortSize32Bit, // two 16-bit SDRAMs make up 32-bit portsize + .burstLen = kSEMC_Sdram_BurstLen8, + .columnAddrBitNum = kSEMC_SdramColunm_9bit, + .casLatency = kSEMC_LatencyThree, + .tPrecharge2Act_Ns = 15, // tRP 15ns + .tAct2ReadWrite_Ns = 15, // tRCD 15ns + .tRefreshRecovery_Ns = 70, // Use the maximum of the (Trfc , Txsr). + .tWriteRecovery_Ns = 2, // tWR 2ns + .tCkeOff_Ns = 42, // The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS. + .tAct2Prechage_Ns = 40, // tRAS 40ns + .tSelfRefRecovery_Ns = 70, + .tRefresh2Refresh_Ns = 60, + .tAct2Act_Ns = 2, // tRC/tRDD 2ns + .tPrescalePeriod_Ns = 160 * (1000000000 / clock_freq), + .refreshPeriod_nsPerRow = 64 * 1000000 / 8192, // 64ms/8192 + .refreshUrgThreshold = sdram_cfg.refreshPeriod_nsPerRow, + .refreshBurstLen = 1, + .delayChain = 2, + }; + + #else + uint32_t clock_freq = CLOCK_GetFreq(kCLOCK_SemcClk); semc_sdram_config_t sdram_cfg = { .csxPinMux = kSEMC_MUXCSX0, @@ -180,6 +263,8 @@ void mimxrt_sdram_init(void) { .refreshBurstLen = 1 }; + #endif + (status_t)SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdram_cfg, clock_freq); } diff --git a/ports/mimxrt/modmachine.c b/ports/mimxrt/modmachine.c index 9eb2431c03..9097289e79 100644 --- a/ports/mimxrt/modmachine.c +++ b/ports/mimxrt/modmachine.c @@ -37,7 +37,6 @@ #include "led.h" #include "pin.h" #include "modmachine.h" -#include "fsl_clock.h" #include "fsl_wdog.h" #if MICROPY_PY_MACHINE diff --git a/ports/mimxrt/moduos.c b/ports/mimxrt/moduos.c index ddb4826db9..b3f97693fa 100644 --- a/ports/mimxrt/moduos.c +++ b/ports/mimxrt/moduos.c @@ -30,10 +30,44 @@ #include "py/runtime.h" #include "py/mphal.h" + +#if defined(MIMXRT117x_SERIES) +#include "fsl_caam.h" +#else #include "fsl_trng.h" +#endif static bool initialized = false; +#if defined(MIMXRT117x_SERIES) +STATIC caam_handle_t caam_handle; +STATIC caam_rng_state_handle_t caam_state_handle = kCAAM_RngStateHandle0; + +#if defined(FSL_FEATURE_HAS_L1CACHE) || defined(__DCACHE_PRESENT) +AT_NONCACHEABLE_SECTION(static caam_job_ring_interface_t s_jrif0); +#else +static caam_job_ring_interface_t s_jrif0; +#endif + +STATIC void trng_start(void) { + caam_config_t config; + + if (!initialized) { + CAAM_GetDefaultConfig(&config); + config.jobRingInterface[0] = &s_jrif0; + CAAM_Init(CAAM, &config); + initialized = true; + } +} + +void trng_random_data(unsigned char *output, size_t len) { + trng_start(); + CAAM_RNG_GetRandomData(CAAM, &caam_handle, caam_state_handle, output, len, + kCAAM_RngDataAny, NULL); +} + +#else + STATIC void trng_start(void) { trng_config_t trngConfig; @@ -46,11 +80,18 @@ STATIC void trng_start(void) { } } +void trng_random_data(unsigned char *output, size_t len) { + trng_start(); + TRNG_GetRandomData(TRNG, output, len); +} + +#endif + uint32_t trng_random_u32(void) { uint32_t rngval; trng_start(); - TRNG_GetRandomData(TRNG, (uint8_t *)&rngval, 4); + trng_random_data((uint8_t *)&rngval, 4); return rngval; } @@ -61,7 +102,7 @@ STATIC mp_obj_t mp_uos_urandom(mp_obj_t num) { vstr_init_len(&vstr, n); trng_start(); - TRNG_GetRandomData(TRNG, vstr.buf, n); + trng_random_data((uint8_t *)vstr.buf, n); return mp_obj_new_bytes_from_vstr(&vstr); } diff --git a/ports/mimxrt/mpconfigport.h b/ports/mimxrt/mpconfigport.h index d86885814c..88c5e9e881 100644 --- a/ports/mimxrt/mpconfigport.h +++ b/ports/mimxrt/mpconfigport.h @@ -29,9 +29,13 @@ // Board specific definitions #include "mpconfigboard.h" #include "fsl_common.h" +#include "lib/nxp_driver/sdk/CMSIS/Include/core_cm7.h" uint32_t trng_random_u32(void); +// Config level +#define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_FULL_FEATURES) + // Memory allocation policies #define MICROPY_GC_STACK_ENTRY_TYPE uint16_t #define MICROPY_GC_ALLOC_THRESHOLD (0) @@ -44,8 +48,8 @@ uint32_t trng_random_u32(void); #define MICROPY_EMIT_INLINE_THUMB (1) // Optimisations -#define MICROPY_OPT_LOAD_ATTR_FAST_PATH (1) #define MICROPY_OPT_MAP_LOOKUP_CACHE (1) +#define MICROPY_OPT_LOAD_ATTR_FAST_PATH (1) // Python internal features #define MICROPY_TRACKED_ALLOC (MICROPY_SSL_MBEDTLS) @@ -234,16 +238,21 @@ extern const struct _mp_obj_type_t network_lan_type; #define MICROPY_HW_PIT_NUM_CHANNELS 3 +#ifndef MICROPY_BOARD_ROOT_POINTERS +#define MICROPY_BOARD_ROOT_POINTERS +#endif + #define MP_STATE_PORT MP_STATE_VM // Miscellaneous settings - +#ifndef MICROPY_EVENT_POLL_HOOK #define MICROPY_EVENT_POLL_HOOK \ do { \ extern void mp_handle_pending(bool); \ mp_handle_pending(true); \ __WFE(); \ } while (0); +#endif #define MICROPY_MAKE_POINTER_CALLABLE(p) ((void *)((mp_uint_t)(p) | 1)) diff --git a/ports/mimxrt/mphalport.c b/ports/mimxrt/mphalport.c index 33f9c2691d..2730b9a855 100644 --- a/ports/mimxrt/mphalport.c +++ b/ports/mimxrt/mphalport.c @@ -146,8 +146,13 @@ uint64_t mp_hal_time_ns(void) { // MAC address void mp_hal_get_unique_id(uint8_t id[]) { + #if defined CPU_MIMXRT1176_cm7 + *(uint32_t *)id = OCOTP->FUSEN[0x10].FUSE; + *(uint32_t *)(id + 4) = OCOTP->FUSEN[0x11].FUSE; + #else *(uint32_t *)id = OCOTP->CFG0; *(uint32_t *)(id + 4) = OCOTP->CFG1; + #endif } // Generate a random locally administered MAC address (LAA) diff --git a/ports/mimxrt/network_lan.c b/ports/mimxrt/network_lan.c index 0842cde82d..59c3310a5b 100644 --- a/ports/mimxrt/network_lan.c +++ b/ports/mimxrt/network_lan.c @@ -36,25 +36,36 @@ #include "hal/phy/device/phydp83825/fsl_phydp83825.h" #include "hal/phy/device/phydp83848/fsl_phydp83848.h" #include "hal/phy/device/phylan8720/fsl_phylan8720.h" +#include "hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.h" #include "lwip/netif.h" +#include "lwip/apps/mdns.h" #ifndef ENET_TX_CLK_OUTPUT #define ENET_TX_CLK_OUTPUT true #endif +#ifndef ENET_1_TX_CLK_OUTPUT +#define ENET_1_TX_CLK_OUTPUT true +#endif + typedef struct _network_lan_obj_t { mp_obj_base_t base; eth_t *eth; } network_lan_obj_t; -STATIC const network_lan_obj_t network_lan_eth0 = { { &network_lan_type }, ð_instance }; + +STATIC const network_lan_obj_t network_lan_eth0 = { { &network_lan_type }, ð_instance0 }; +#if defined(ENET_DUAL_PORT) +STATIC const network_lan_obj_t network_lan_eth1 = { { &network_lan_type }, ð_instance1 }; +#endif STATIC void network_lan_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { network_lan_obj_t *self = MP_OBJ_TO_PTR(self_in); struct netif *netif = eth_netif(self->eth); int status = eth_link_status(self->eth); - mp_printf(print, "", + mp_printf(print, "", + self->eth == ð_instance0 ? 0 : 1, status, netif->ip_addr.addr & 0xff, netif->ip_addr.addr >> 8 & 0xff, @@ -68,14 +79,30 @@ STATIC mp_obj_t network_lan_make_new(const mp_obj_type_t *type, size_t n_args, s static const mp_arg_t allowed_args[] = { { MP_QSTR_id, MP_ARG_INT, {.u_int = 0} }, { MP_QSTR_phy_type, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, - { MP_QSTR_phy_addr, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = ENET_PHY_ADDRESS} }, - { MP_QSTR_phy_clock, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = ENET_TX_CLK_OUTPUT} }, + { MP_QSTR_phy_addr, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_phy_clock, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, }; // Parse args. mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); - const phy_operations_t *phy_ops = &ENET_PHY_OPS; + const phy_operations_t *phy_ops; + int phy_addr; + bool phy_clock; + + int mac_id = args[ARG_id].u_int; + // set default + if (mac_id == 0) { + phy_ops = &ENET_PHY_OPS; + phy_addr = ENET_PHY_ADDRESS; + phy_clock = ENET_TX_CLK_OUTPUT; + #if defined(ENET_DUAL_PORT) + } else { + phy_ops = &ENET_1_PHY_OPS; + phy_addr = ENET_1_PHY_ADDRESS; + phy_clock = ENET_1_TX_CLK_OUTPUT; + #endif + } // Select PHY driver int phy_type = args[ARG_phy_type].u_int; @@ -88,28 +115,34 @@ STATIC mp_obj_t network_lan_make_new(const mp_obj_type_t *type, size_t n_args, s phy_ops = &phydp83848_ops; } else if (phy_type == PHY_LAN8720) { phy_ops = &phylan8720_ops; + } else if (phy_type == PHY_RTL8211F) { + phy_ops = &phyrtl8211f_ops; } else { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Invalid value %d for phy"), phy_type); } } - int phy_addr = args[ARG_phy_addr].u_int; + if (args[ARG_phy_addr].u_int != -1) { + phy_addr = args[ARG_phy_addr].u_int; + } - bool phy_clock = args[ARG_phy_clock].u_int; + if (args[ARG_phy_clock].u_int != -1) { + phy_clock = args[ARG_phy_clock].u_int; + } // Prepare for two ETH interfaces. const network_lan_obj_t *self; - int mac_id = args[ARG_id].u_int; if (mac_id == 0) { self = &network_lan_eth0; - mac_id = MP_HAL_MAC_ETH0; + eth_init_0(self->eth, MP_HAL_MAC_ETH0, phy_ops, phy_addr, phy_clock); + #if defined(ENET_DUAL_PORT) } else if (mac_id == 1) { - self = &network_lan_eth0; - mac_id = MP_HAL_MAC_ETH1; + self = &network_lan_eth1; + eth_init_1(self->eth, MP_HAL_MAC_ETH1, phy_ops, phy_addr, phy_clock); + #endif } else { mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Invalid LAN interface %d"), mac_id); } - eth_init(self->eth, mac_id, phy_ops, phy_addr, phy_clock); // register with network module mod_network_register_nic((mp_obj_t *)self); return MP_OBJ_FROM_PTR(self); @@ -215,6 +248,7 @@ STATIC const mp_rom_map_elem_t network_lan_locals_dict_table[] = { { MP_ROM_QSTR(MP_QSTR_PHY_DP83825), MP_ROM_INT(PHY_DP83825) }, { MP_ROM_QSTR(MP_QSTR_PHY_DP83848), MP_ROM_INT(PHY_DP83848) }, { MP_ROM_QSTR(MP_QSTR_PHY_LAN8720), MP_ROM_INT(PHY_LAN8720) }, + { MP_ROM_QSTR(MP_QSTR_PHY_RTL8211F), MP_ROM_INT(PHY_RTL8211F) }, { MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(PHY_TX_CLK_IN) }, { MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(PHY_TX_CLK_OUT) }, }; diff --git a/ports/mimxrt/pin.h b/ports/mimxrt/pin.h index 583d1c3023..63db55f8a7 100644 --- a/ports/mimxrt/pin.h +++ b/ports/mimxrt/pin.h @@ -69,6 +69,7 @@ enum { PIN_AF_MODE_ALT7, PIN_AF_MODE_ALT8, PIN_AF_MODE_ALT9, + PIN_AF_MODE_ALT10, }; enum { diff --git a/ports/mimxrt/ticks.c b/ports/mimxrt/ticks.c index 0fc9babc04..858a5c574f 100644 --- a/ports/mimxrt/ticks.c +++ b/ports/mimxrt/ticks.c @@ -41,7 +41,11 @@ void ticks_init(void) { ticks_ms_upper = 0; gpt_config_t config; + #if defined MIMXRT117x_SERIES + config.clockSource = kGPT_ClockSource_HighFreq; + #else config.clockSource = kGPT_ClockSource_Osc; + #endif config.divider = 24; // XTAL is 24MHz config.enableFreeRun = true; config.enableRunInWait = true;