kopia lustrzana https://github.com/micropython/micropython
mimxrt: Tidy up the board flash related files.
- Move the qspi_xxxx_flash_config.c files to hal. It turned out that they are less board than flash type specific. - Change to a common flexspi_flash_config.h header file.pull/8051/head
robert-hh
rodzic
c5dbbf71c0
commit
5ca56aaf16
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@ -90,7 +90,6 @@ CFLAGS += -DXIP_EXTERNAL_FLASH=1 \
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-DCPU_HEADER_H='<$(MCU_SERIES).h>' \
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-DBOARD_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
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-DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
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-DBOARD_FLASH_CONFIG_HEADER_H=\"$(BOARD)_flexspi_nor_config.h\"
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ifeq ($(MICROPY_HW_FLASH_TYPE), qspi_nor)
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CFLAGS += -DBOARD_FLASH_OPS_HEADER_H=\"hal/flexspi_nor_flash.h\"
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@ -277,11 +276,11 @@ SRC_C += \
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ifeq ($(MICROPY_HW_FLASH_TYPE), qspi_nor)
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SRC_C += \
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hal/flexspi_nor_flash.c \
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$(BOARD_DIR)/qspi_nor_flash_config.c
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hal/qspi_nor_flash_config.c
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else ifeq ($(MICROPY_HW_FLASH_TYPE), hyperflash)
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SRC_C += \
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hal/flexspi_hyper_flash.c \
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$(BOARD_DIR)/qspi_hyper_flash_config.c
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hal/qspi_hyper_flash_config.c
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else
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$(error Error: Unknown board flash type $(MICROPY_HW_FLASH_TYPE))
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endif
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@ -1,257 +0,0 @@
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/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Based on tinyusb/hw/bsp/teensy_40/evkmimxrt1010_flexspi_nor_config.h
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#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
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#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__
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#include <stdint.h>
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#include <stdbool.h>
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#include "fsl_common.h"
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/*! @name Driver version */
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/*@{*/
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/*! @brief XIP_BOARD driver version 2.0.0. */
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#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/* FLEXSPI memory config block related defintions */
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
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#define FLEXSPI_CFG_BLK_SIZE (512)
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/* FLEXSPI Feature related definitions */
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#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
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/* Lookup table related defintions */
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_WRITEENABLE 2
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#define CMD_INDEX_WRITE 4
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define DUMMY_RWDS_SDR 0x0D
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#define DUMMY_RWDS_DDR 0x2D
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define FLEXSPI_1PAD 0
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#define FLEXSPI_2PAD 1
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#define FLEXSPI_4PAD 2
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#define FLEXSPI_8PAD 3
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// !@brief Definitions for FlexSPI Serial Clock Frequency
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typedef enum _FlexSpiSerialClockFreq
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{
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_120MHz = 7,
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kFlexSpiSerialClk_133MHz = 8,
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} flexspi_serial_clk_freq_t;
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// !@brief FlexSPI clock configuration type
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enum
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{
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kFlexSpiClk_SDR, // !< Clock configure for SDR mode
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kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
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};
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// !@brief FlexSPI Read Sample Clock Source definition
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typedef enum _FlashReadSampleClkSource
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{
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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} flexspi_read_sample_clk_t;
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// !@brief Misc feature bit definitions
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enum
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{
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kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
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kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
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kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
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kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
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kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
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};
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// !@brief Flash Type Definition
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enum
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{
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kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
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kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
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kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
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kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
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kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
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};
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// !@brief Flash Pad Definitions
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enum
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{
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kSerialFlash_1Pad = 1,
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kSerialFlash_2Pads = 2,
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kSerialFlash_4Pads = 4,
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kSerialFlash_8Pads = 8,
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};
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// !@brief FlexSPI LUT Sequence structure
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typedef struct _lut_sequence
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{
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uint8_t seqNum; // !< Sequence Number, valid number: 1-16
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uint8_t seqId; // !< Sequence Index, valid number: 0-15
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uint16_t reserved;
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} flexspi_lut_seq_t;
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// !@brief Flash Configuration Command Type
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enum
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{
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kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
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kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
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kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
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kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
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kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
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kDeviceConfigCmdType_Reset, // !< Reset device command
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};
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// !@brief FlexSPI Memory Configuration Block
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typedef struct _FlexSPIConfig
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{
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uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
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uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
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uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
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uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
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uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
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uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
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uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
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// ! Serial NAND, need to refer to datasheet
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uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
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uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
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// ! Generic configuration, etc.
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uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
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// ! DPI/QPI/OPI switch or reset command
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flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
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// ! sequence number, [31:16] Reserved
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uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
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uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
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uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
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flexspi_lut_seq_t
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configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
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uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
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uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
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uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
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uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
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// ! details
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uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
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uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
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uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
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// ! Chapter for more details
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uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
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// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
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uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
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uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
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uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
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uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
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uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
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uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
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uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
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uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
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uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
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uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
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uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
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uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
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uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
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uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
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// ! busy flag is 0 when flash device is busy
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uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
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flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
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uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
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} flexspi_mem_config_t;
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/* */
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#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
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#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
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#define NOR_CMD_LUT_SEQ_IDX_READID 8
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
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#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
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#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
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#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
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/*
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* Serial NOR configuration block
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*/
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typedef struct _flexspi_nor_config
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{
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flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
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uint32_t pageSize; // !< Page size of Serial NOR
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uint32_t sectorSize; // !< Sector size of Serial NOR
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uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
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uint8_t isUniformBlockSize; // !< Sector/Block size is the same
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uint8_t reserved0[2]; // !< Reserved for future use
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uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
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uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
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uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
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uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
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uint32_t blockSize; // !< Block size
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uint32_t reserve2[11]; // !< Reserved for future use
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} flexspi_nor_config_t;
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#define FLASH_BUSY_STATUS_POL 0
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#define FLASH_BUSY_STATUS_OFFSET 0
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */
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@ -1,124 +0,0 @@
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/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Based on tinyusb/hw/bsp/teensy_40/evkmimxrt1010_flexspi_nor_config.c
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#include BOARD_FLASH_CONFIG_HEADER_H
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_board"
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_100MHz,
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.sflashA1Size = MICROPY_HW_FLASH_SIZE,
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.lookupTable =
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{
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// 0 Read LUTs 0 -> 0
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 1 Read status register -> 1
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 2 Fast read quad mode - SDR
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 3 Write Enable -> 3
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 4 Read extend parameters
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 5 Erase Sector -> 5
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 6 Write Status Reg
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 7 Page Program - quad mode (-> 9)
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 8 Read ID
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 9 Page Program - single mode -> 9
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 10 Enter QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 11 Erase Chip
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 12 Exit QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
/*
|
||||
* Copyright 2019 NXP.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Based on tinyusb/hw/bsp/teensy_40/evkmimxrt1020_flexspi_nor_config.h
|
||||
|
||||
#ifndef __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
// !@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
kFlexSpiSerialClk_200MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
// !@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, // !< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
// !@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
// !@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
// !@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
// !@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; // !< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; // !< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
// !@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, // !< Reset device command
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
// ! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
// ! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
// ! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
// ! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
// ! details
|
||||
uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
// ! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
// ! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READID 8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; // !< Page size of Serial NOR
|
||||
uint32_t sectorSize; // !< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; // !< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; // !< Reserved for future use
|
||||
uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; // !< Block size
|
||||
uint32_t reserve2[11]; // !< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#define FLASH_BUSY_STATUS_POL 0
|
||||
#define FLASH_BUSY_STATUS_OFFSET 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ */
|
||||
|
|
@ -1,186 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.columnAddressWidth = 3u,
|
||||
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
|
||||
.controllerMiscOption =
|
||||
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
|
||||
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
|
||||
.sflashPadType = kSerialFlash_8Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = MICROPY_HW_FLASH_SIZE,
|
||||
.dataValidTime = {16u, 16u},
|
||||
.lookupTable =
|
||||
{
|
||||
/* 0 Read Data */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
|
||||
|
||||
/* 1 Write Data */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
|
||||
/* 2 Read Status */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
|
||||
|
||||
/* 4 Write Enable */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
|
||||
/* 6 Erase Sector */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
// +2
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
// +3
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
|
||||
|
||||
/* 10 program page with word program command sequence */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
|
||||
|
||||
/* 12 Erase chip */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80),
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
// +2
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
// +3
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10),
|
||||
},
|
||||
},
|
||||
.pageSize = 512u,
|
||||
.sectorSize = 256u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = true,
|
||||
};
|
||||
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.columnAddressWidth = 3u,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.controllerMiscOption =
|
||||
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
|
||||
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
|
||||
.sflashPadType = kSerialFlash_8Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = MICROPY_HW_FLASH_SIZE,
|
||||
.dataValidTime = {16u, 16u},
|
||||
.lookupTable =
|
||||
{
|
||||
// 0 Read LUTs 0 -> 0
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 1 Read status register -> 1
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 2 Fast read quad mode - SDR
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 3 Write Enable -> 3
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 4 Read extend parameters
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 5 Erase Sector -> 5
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 6 Write Status Reg
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 7 Page Program - quad mode (-> 9)
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 8 Read ID
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 9 Page Program - single mode -> 9
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 10 Enter QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 11 Erase Chip
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 12 Exit QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
},
|
||||
},
|
||||
.pageSize = 512u,
|
||||
.sectorSize = 256u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = true,
|
||||
};
|
||||
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -1,264 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_flexspi.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
// !@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_120MHz = 7,
|
||||
kFlexSpiSerialClk_133MHz = 8,
|
||||
kFlexSpiSerialClk_166MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
// !@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, // !< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
// !@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
// !@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
// !@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
// !@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; // !< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; // !< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
// !@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, // !< Reset device command
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
// ! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
// ! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
// ! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
// ! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
// ! details
|
||||
uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
// ! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
// ! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READID 8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
|
||||
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP 12
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; // !< Page size of Serial NOR
|
||||
uint32_t sectorSize; // !< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; // !< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; // !< Reserved for future use
|
||||
uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; // !< Block size
|
||||
uint32_t reserve2[11]; // !< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#define FLASH_BUSY_STATUS_POL 0
|
||||
#define FLASH_BUSY_STATUS_OFFSET 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
|
||||
|
|
@ -1,186 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.columnAddressWidth = 3u,
|
||||
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
|
||||
.controllerMiscOption =
|
||||
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
|
||||
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
|
||||
.sflashPadType = kSerialFlash_8Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = MICROPY_HW_FLASH_SIZE,
|
||||
.dataValidTime = {16u, 16u},
|
||||
.lookupTable =
|
||||
{
|
||||
/* 0 Read Data */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
|
||||
|
||||
/* 1 Write Data */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
|
||||
/* 2 Read Status */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
|
||||
|
||||
/* 4 Write Enable */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
|
||||
/* 6 Erase Sector */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
// +2
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
// +3
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
|
||||
|
||||
/* 10 program page with word program command sequence */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
|
||||
kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
|
||||
|
||||
/* 12 Erase chip */
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80),
|
||||
// +1
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
// +2
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
|
||||
// +3
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
|
||||
[4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] =
|
||||
FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10),
|
||||
},
|
||||
},
|
||||
.pageSize = 512u,
|
||||
.sectorSize = 256u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = true,
|
||||
};
|
||||
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.columnAddressWidth = 3u,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.controllerMiscOption =
|
||||
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
|
||||
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
|
||||
.sflashPadType = kSerialFlash_8Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = MICROPY_HW_FLASH_SIZE,
|
||||
.dataValidTime = {16u, 16u},
|
||||
.lookupTable =
|
||||
{
|
||||
// 0 Read LUTs 0 -> 0
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 1 Read status register -> 1
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 2 Fast read quad mode - SDR
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 3 Write Enable -> 3
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 4 Read extend parameters
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 5 Erase Sector -> 5
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 6 Write Status Reg
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 7 Page Program - quad mode (-> 9)
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 8 Read ID
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 9 Page Program - single mode -> 9
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 10 Enter QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 11 Erase Chip
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 12 Exit QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
},
|
||||
},
|
||||
.pageSize = 512u,
|
||||
.sectorSize = 256u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = true,
|
||||
};
|
||||
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -1,264 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_flexspi.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related defintions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
// !@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_120MHz = 7,
|
||||
kFlexSpiSerialClk_133MHz = 8,
|
||||
kFlexSpiSerialClk_166MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
// !@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, // !< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
// !@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
// !@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
// !@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
// !@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; // !< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; // !< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
// !@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, // !< Reset device command
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
// ! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
// ! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
// ! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
// ! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
// ! details
|
||||
uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
// ! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
// ! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READID 8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
|
||||
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
|
||||
#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP 12
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; // !< Page size of Serial NOR
|
||||
uint32_t sectorSize; // !< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; // !< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; // !< Reserved for future use
|
||||
uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; // !< Block size
|
||||
uint32_t reserve2[11]; // !< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#define FLASH_BUSY_STATUS_POL 0
|
||||
#define FLASH_BUSY_STATUS_OFFSET 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ */
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
.columnAddressWidth = 3u,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.controllerMiscOption =
|
||||
(1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
|
||||
(1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
|
||||
.sflashPadType = kSerialFlash_8Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = MICROPY_HW_FLASH_SIZE,
|
||||
.dataValidTime = {16u, 16u},
|
||||
.lookupTable =
|
||||
{
|
||||
// 0 Read LUTs 0 -> 0
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 1 Read status register -> 1
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 2 Fast read quad mode - SDR
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 3 Write Enable -> 3
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 4 Read extend parameters
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 5 Erase Sector -> 5
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 6 Write Status Reg
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 7 Page Program - quad mode (-> 9)
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 8 Read ID
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 9 Page Program - single mode -> 9
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 10 Enter QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 11 Erase Chip
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 12 Exit QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
},
|
||||
},
|
||||
.pageSize = 512u,
|
||||
.sectorSize = 256u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.isUniformBlockSize = true,
|
||||
};
|
||||
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -1,259 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Based on tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.h
|
||||
|
||||
#ifndef __TEENSY40_FLEXSPI_NOR_CONFIG__
|
||||
#define __TEENSY40_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related definitions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_ERASE 5
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
// !@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_120MHz = 7,
|
||||
kFlexSpiSerialClk_133MHz = 8,
|
||||
kFlexSpiSerialClk_166MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
// !@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, // !< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
// !@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
// !@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
// !@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
// !@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; // !< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; // !< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
// !@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, // !< Reset device command
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
// ! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
// ! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
// ! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
// ! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
// ! details
|
||||
uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
// ! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
// ! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READID 8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; // !< Page size of Serial NOR
|
||||
uint32_t sectorSize; // !< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; // !< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; // !< Reserved for future use
|
||||
uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; // !< Block size
|
||||
uint32_t reserve2[11]; // !< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#define FLASH_BUSY_STATUS_POL 0
|
||||
#define FLASH_BUSY_STATUS_OFFSET 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Based on tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.c
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
|
||||
.busyOffset = FLASH_BUSY_STATUS_OFFSET, // Status bit 0 indicates busy.
|
||||
.busyBitPolarity = FLASH_BUSY_STATUS_POL, // Busy when the bit is 1.
|
||||
|
||||
.deviceModeCfgEnable = 1u,
|
||||
.deviceModeType = kDeviceConfigCmdType_QuadEnable,
|
||||
.deviceModeSeq = {
|
||||
.seqId = 4u,
|
||||
.seqNum = 1u,
|
||||
},
|
||||
.deviceModeArg = 0x0200,
|
||||
.configCmdEnable = 1u,
|
||||
.configModeType[0] = kDeviceConfigCmdType_Generic,
|
||||
.configCmdSeqs[0] = {
|
||||
.seqId = 2u,
|
||||
.seqNum = 1u,
|
||||
},
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_60MHz,
|
||||
.sflashA1Size = MICROPY_HW_FLASH_SIZE,
|
||||
.lookupTable =
|
||||
{
|
||||
// 0 Read LUTs 0 -> 0
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 1 Read status register -> 1
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 2 Fast read quad mode - SDR
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 3 Write Enable -> 3
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 4 Read extend parameters
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 5 Erase Sector -> 5
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 6 Write Status Reg
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 7 Page Program - quad mode (-> 9)
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 8 Read ID
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 9 Page Program - single mode -> 9
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 10 Enter QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 11 Erase Chip
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 12 Exit QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
|
||||
.blockSize = 0x00010000,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -1,259 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Based on tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.h
|
||||
|
||||
#ifndef __TEENSY40_FLEXSPI_NOR_CONFIG__
|
||||
#define __TEENSY40_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.0. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related definitions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_ERASE 5
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
// !@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_75MHz = 4,
|
||||
kFlexSpiSerialClk_80MHz = 5,
|
||||
kFlexSpiSerialClk_100MHz = 6,
|
||||
kFlexSpiSerialClk_120MHz = 7,
|
||||
kFlexSpiSerialClk_133MHz = 8,
|
||||
kFlexSpiSerialClk_166MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
// !@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, // !< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, // !< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
// !@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, // !< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, // !< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, // !< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, // !< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, // !< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, // !< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, // !< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
// !@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, // !< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, // !< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, // !< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, // !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, // !< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
// !@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
// !@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; // !< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; // !< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
// !@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, // !< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, // !< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, // !< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, // !< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, // !< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, // !< Reset device command
|
||||
};
|
||||
|
||||
// !@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; // !< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; // !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; // !< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; // !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; // !< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; // !< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; // !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
// ! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; // !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; // !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
// ! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; // !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
// ! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; // !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
// ! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; // !< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; // !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; // !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; // !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; // !< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; // !< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; // !< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; // !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
// ! details
|
||||
uint8_t deviceType; // !< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; // !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; // !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
// ! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; // !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
// ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; // !< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; // !< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; // !< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; // !< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; // !< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; // !< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; // !< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; // !< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; // !< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; // !< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; // !< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; // !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; // !< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; // !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
// ! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; // !< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; // !< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; // !< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READID 8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; // !< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; // !< Page size of Serial NOR
|
||||
uint32_t sectorSize; // !< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; // !< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; // !< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; // !< Reserved for future use
|
||||
uint8_t serialNorType; // !< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; // !< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; // !< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; // !< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; // !< Block size
|
||||
uint32_t reserve2[11]; // !< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#define FLASH_BUSY_STATUS_POL 0
|
||||
#define FLASH_BUSY_STATUS_OFFSET 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
/*
|
||||
* Copyright 2018 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
// Based on tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.c
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
|
||||
.busyOffset = FLASH_BUSY_STATUS_OFFSET, // Status bit 0 indicates busy.
|
||||
.busyBitPolarity = FLASH_BUSY_STATUS_POL, // Busy when the bit is 1.
|
||||
|
||||
.deviceModeCfgEnable = 1u,
|
||||
.deviceModeType = kDeviceConfigCmdType_QuadEnable,
|
||||
.deviceModeSeq = {
|
||||
.seqId = 4u,
|
||||
.seqNum = 1u,
|
||||
},
|
||||
.deviceModeArg = 0x0200,
|
||||
.configCmdEnable = 1u,
|
||||
.configModeType[0] = kDeviceConfigCmdType_Generic,
|
||||
.configCmdSeqs[0] = {
|
||||
.seqId = 2u,
|
||||
.seqNum = 1u,
|
||||
},
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_60MHz,
|
||||
.sflashA1Size = MICROPY_HW_FLASH_SIZE,
|
||||
.lookupTable =
|
||||
{
|
||||
// 0 Read LUTs 0 -> 0
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 1 Read status register -> 1
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 2 Fast read quad mode - SDR
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 3 Write Enable -> 3
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 4 Read extend parameters
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 5 Erase Sector -> 5
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 6 Write Status Reg
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 7 Page Program - quad mode (-> 9)
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 8 Read ID
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 9 Page Program - single mode -> 9
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
|
||||
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 10 Enter QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 11 Erase Chip
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
|
||||
// 12 Exit QPI mode
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
|
||||
.blockSize = 0x00010000,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
|
|
@ -5,8 +5,8 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKMIMXRT1050_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1050_FLEXSPI_NOR_CONFIG__
|
||||
#ifndef __FLEXSPI_FLASH_CONFIG__
|
||||
#define __FLEXSPI_FLASH_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
|
@ -260,4 +260,4 @@ extern "C" {
|
|||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1050_FLEXSPI_NOR_CONFIG__ */
|
||||
#endif /* __FLEXSPI_FLASH_CONFIG__ */
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
#include "fsl_flexspi.h"
|
||||
#include "mpconfigboard.h"
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
#include "flexspi_flash_config.h"
|
||||
|
||||
// Defined in boards flash_config.c
|
||||
extern flexspi_nor_config_t qspiflash_config;
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
|
||||
#include "fsl_flexspi.h"
|
||||
#include "mpconfigboard.h"
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
#include "flexspi_flash_config.h"
|
||||
|
||||
// Defined in boards flash_config.c
|
||||
extern flexspi_nor_config_t qspiflash_config;
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
#include "flexspi_flash_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
// Based on tinyusb/hw/bsp/teensy_40/evkmimxrt1010_flexspi_nor_config.c
|
||||
|
||||
#include BOARD_FLASH_CONFIG_HEADER_H
|
||||
#include "flexspi_flash_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
|
|
@ -129,7 +129,7 @@ const flexspi_nor_config_t qspiflash_config = {
|
|||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.blockSize = 256u * 1024u,
|
||||
.blockSize = 64u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
// .ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
|
||||
};
|
||||
Ładowanie…
Reference in New Issue