kopia lustrzana https://github.com/micropython/micropython
stm32/octospi: Add preliminary support for OCTOSPI peripheral.
It currently operates in 1-line (SPI) mode only. Signed-off-by: Damien George <damien@micropython.org>pull/11138/head
Damien George
rodzic
ec4232b32e
commit
56a22ddc8b
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@ -320,6 +320,7 @@ SRC_C += \
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spi.c \
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pyb_spi.c \
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qspi.c \
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octospi.c \
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uart.c \
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ulpi.c \
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can.c \
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@ -0,0 +1,343 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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// This OCTOSPI driver is currently configured to run in 1-line (SPI) mode.
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// It uses the mp_qspi_proto_t QSPI protocol and translates quad-commands
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// into 1-line commands.
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#include "py/mperrno.h"
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#include "py/mphal.h"
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#include "octospi.h"
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#include "pin_static_af.h"
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#if defined(MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2)
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#ifndef MICROPY_HW_OSPI_PRESCALER
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#define MICROPY_HW_OSPI_PRESCALER (3) // F_CLK = F_AHB/3
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#endif
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#ifndef MICROPY_HW_OSPI_CS_HIGH_CYCLES
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#define MICROPY_HW_OSPI_CS_HIGH_CYCLES (2) // nCS stays high for 2 cycles
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#endif
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void octospi_init(void) {
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// Configure OCTOSPI pins (allows 1, 2, 4 or 8 line configuration).
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_CS, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_NCS);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_SCK, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_CLK);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO0, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO0);
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#if defined(MICROPY_HW_OSPIFLASH_IO1)
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO1, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO1);
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#if defined(MICROPY_HW_OSPIFLASH_IO2)
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO2, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO2);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO3, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO3);
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#if defined(MICROPY_HW_OSPIFLASH_IO4)
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO4, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO4);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO5, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO5);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO6, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO6);
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mp_hal_pin_config_alt_static_speed(MICROPY_HW_OSPIFLASH_IO7, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, MP_HAL_PIN_SPEED_VERY_HIGH, STATIC_AF_OCTOSPI1_IO7);
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#endif
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#endif
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#endif
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// Reset and turn on the OCTOSPI peripheral.
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__HAL_RCC_OSPI1_CLK_ENABLE();
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__HAL_RCC_OSPI1_FORCE_RESET();
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__HAL_RCC_OSPI1_RELEASE_RESET();
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// Configure the OCTOSPI peripheral.
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OCTOSPI1->CR =
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3 << OCTOSPI_CR_FTHRES_Pos // 4 bytes must be available to read/write
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| 0 << OCTOSPI_CR_MSEL_Pos // FLASH 0 selected
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| 0 << OCTOSPI_CR_DMM_Pos // dual-memory mode disabled
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;
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OCTOSPI1->DCR1 =
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(MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) << OCTOSPI_DCR1_DEVSIZE_Pos
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| (MICROPY_HW_OSPI_CS_HIGH_CYCLES - 1) << OCTOSPI_DCR1_CSHT_Pos
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| 0 << OCTOSPI_DCR1_CKMODE_Pos // CLK idles at low state
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;
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OCTOSPI1->DCR2 =
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(MICROPY_HW_OSPI_PRESCALER - 1) << OCTOSPI_DCR2_PRESCALER_Pos
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;
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OCTOSPI1->DCR3 = 0;
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OCTOSPI1->DCR4 = 0;
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// Enable the OCTOSPI peripheral.
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OCTOSPI1->CR |= OCTOSPI_CR_EN;
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}
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STATIC int octospi_ioctl(void *self_in, uint32_t cmd) {
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(void)self_in;
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switch (cmd) {
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case MP_QSPI_IOCTL_INIT:
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octospi_init();
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break;
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case MP_QSPI_IOCTL_BUS_ACQUIRE:
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// Abort any ongoing transfer if peripheral is busy.
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if (OCTOSPI1->SR & OCTOSPI_SR_BUSY) {
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OCTOSPI1->CR |= OCTOSPI_CR_ABORT;
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while (OCTOSPI1->CR & OCTOSPI_CR_ABORT) {
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}
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}
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break;
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case MP_QSPI_IOCTL_BUS_RELEASE:
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break;
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}
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return 0; // success
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}
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STATIC int octospi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t data) {
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(void)self_in;
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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OCTOSPI1->CR = (OCTOSPI1->CR & ~OCTOSPI_CR_FMODE_Msk) | 0 << OCTOSPI_CR_FMODE_Pos; // indirect write mode
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if (len == 0) {
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OCTOSPI1->CCR =
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0 << OCTOSPI_CCR_DDTR_Pos // DD mode disabled
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| 0 << OCTOSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << OCTOSPI_CCR_DMODE_Pos // no data
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| 0 << OCTOSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << OCTOSPI_CCR_ADMODE_Pos // no address
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| 1 << OCTOSPI_CCR_IMODE_Pos // instruction on 1 line
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;
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OCTOSPI1->TCR = 0 << OCTOSPI_TCR_DCYC_Pos; // 0 dummy cycles
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// This triggers the start of the operation.
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OCTOSPI1->IR = cmd << OCTOSPI_IR_INSTRUCTION_Pos; // write opcode
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} else {
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OCTOSPI1->DLR = len - 1;
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OCTOSPI1->CCR =
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0 << OCTOSPI_CCR_DDTR_Pos // DD mode disabled
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| 0 << OCTOSPI_CCR_SIOO_Pos // send instruction every transaction
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| 1 << OCTOSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << OCTOSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << OCTOSPI_CCR_ADMODE_Pos // no address
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| 1 << OCTOSPI_CCR_IMODE_Pos // instruction on 1 line
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;
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OCTOSPI1->TCR = 0 << OCTOSPI_TCR_DCYC_Pos; // 0 dummy cycles
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OCTOSPI1->IR = cmd << OCTOSPI_IR_INSTRUCTION_Pos; // write opcode
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// Wait for at least 1 free byte location in the FIFO.
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while (!(OCTOSPI1->SR & OCTOSPI_SR_FTF)) {
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}
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// This triggers the start of the operation.
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// This assumes len==2
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*(uint16_t *)&OCTOSPI1->DR = data;
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}
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// Wait for write to finish
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while (!(OCTOSPI1->SR & OCTOSPI_SR_TCF)) {
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if (OCTOSPI1->SR & OCTOSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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return 0;
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}
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STATIC int octospi_write_cmd_addr_data(void *self_in, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src) {
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(void)self_in;
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uint8_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2;
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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OCTOSPI1->CR = (OCTOSPI1->CR & ~OCTOSPI_CR_FMODE_Msk) | 0 << OCTOSPI_CR_FMODE_Pos; // indirect write mode
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if (len == 0) {
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OCTOSPI1->CCR =
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0 << OCTOSPI_CCR_DDTR_Pos // DD mode disabled
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| 0 << OCTOSPI_CCR_SIOO_Pos // send instruction every transaction
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| 0 << OCTOSPI_CCR_DMODE_Pos // no data
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| 0 << OCTOSPI_CCR_ABMODE_Pos // no alternate byte
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| adsize << OCTOSPI_CCR_ADSIZE_Pos // 32/24-bit address size
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| 1 << OCTOSPI_CCR_ADMODE_Pos // address on 1 line
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| 1 << OCTOSPI_CCR_IMODE_Pos // instruction on 1 line
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;
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OCTOSPI1->TCR = 0 << OCTOSPI_TCR_DCYC_Pos; // 0 dummy cycles
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OCTOSPI1->IR = cmd << OCTOSPI_IR_INSTRUCTION_Pos; // write opcode
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// This triggers the start of the operation.
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OCTOSPI1->AR = addr;
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} else {
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OCTOSPI1->DLR = len - 1;
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OCTOSPI1->CCR =
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0 << OCTOSPI_CCR_DDTR_Pos // DD mode disabled
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| 0 << OCTOSPI_CCR_SIOO_Pos // send instruction every transaction
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| 1 << OCTOSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << OCTOSPI_CCR_ABMODE_Pos // no alternate byte
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| adsize << OCTOSPI_CCR_ADSIZE_Pos // 32/24-bit address size
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| 1 << OCTOSPI_CCR_ADMODE_Pos // address on 1 line
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| 1 << OCTOSPI_CCR_IMODE_Pos // instruction on 1 line
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;
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OCTOSPI1->TCR = 0 << OCTOSPI_TCR_DCYC_Pos; // 0 dummy cycles
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OCTOSPI1->IR = cmd << OCTOSPI_IR_INSTRUCTION_Pos; // write opcode
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OCTOSPI1->AR = addr;
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// Write out the data 1 byte at a time
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// This triggers the start of the operation.
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while (len) {
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while (!(OCTOSPI1->SR & OCTOSPI_SR_FTF)) {
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if (OCTOSPI1->SR & OCTOSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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*(volatile uint8_t *)&OCTOSPI1->DR = *src++;
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--len;
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}
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}
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// Wait for write to finish
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while (!(OCTOSPI1->SR & OCTOSPI_SR_TCF)) {
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if (OCTOSPI1->SR & OCTOSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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return 0;
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}
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STATIC int octospi_read_cmd(void *self_in, uint8_t cmd, size_t len, uint32_t *dest) {
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(void)self_in;
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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OCTOSPI1->DLR = len - 1; // number of bytes to read
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OCTOSPI1->CR = (OCTOSPI1->CR & ~OCTOSPI_CR_FMODE_Msk) | 1 << OCTOSPI_CR_FMODE_Pos; // indirect read mode
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OCTOSPI1->CCR =
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0 << OCTOSPI_CCR_DDTR_Pos // DD mode disabled
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| 0 << OCTOSPI_CCR_SIOO_Pos // send instruction every transaction
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| 1 << OCTOSPI_CCR_DMODE_Pos // data on 1 line
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| 0 << OCTOSPI_CCR_ABMODE_Pos // no alternate byte
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| 0 << OCTOSPI_CCR_ADMODE_Pos // no address
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| 1 << OCTOSPI_CCR_IMODE_Pos // instruction on 1 line
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;
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OCTOSPI1->TCR = 0 << OCTOSPI_TCR_DCYC_Pos; // 0 dummy cycles
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// This triggers the start of the operation.
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OCTOSPI1->IR = cmd << OCTOSPI_IR_INSTRUCTION_Pos; // read opcode
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// Wait for read to finish
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while (!(OCTOSPI1->SR & OCTOSPI_SR_TCF)) {
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if (OCTOSPI1->SR & OCTOSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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// Read result
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*dest = OCTOSPI1->DR;
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return 0;
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}
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STATIC int octospi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) {
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(void)self_in;
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uint32_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2;
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uint32_t dmode = 1; // data on 1-line
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uint32_t admode = 1; // address on 1-line
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uint32_t dcyc = 0; // 0 dummy cycles
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if (cmd == 0xeb) {
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// Convert to 1-line command.
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cmd = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 0x13 : 0x03;
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}
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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OCTOSPI1->DLR = len - 1; // number of bytes to read
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OCTOSPI1->CR = (OCTOSPI1->CR & ~OCTOSPI_CR_FMODE_Msk) | 1 << OCTOSPI_CR_FMODE_Pos; // indirect read mode
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OCTOSPI1->CCR =
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0 << OCTOSPI_CCR_DDTR_Pos // DD mode disabled
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| 0 << OCTOSPI_CCR_SIOO_Pos // send instruction every transaction
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| dmode << OCTOSPI_CCR_DMODE_Pos // data on n lines
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| 0 << OCTOSPI_CCR_ABSIZE_Pos // 8-bit alternate byte
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| 0 << OCTOSPI_CCR_ABMODE_Pos // no alternate byte
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| adsize << OCTOSPI_CCR_ADSIZE_Pos // 32 or 24-bit address size
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| admode << OCTOSPI_CCR_ADMODE_Pos // address on n lines
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| 1 << OCTOSPI_CCR_IMODE_Pos // instruction on 1 line
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;
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OCTOSPI1->TCR = dcyc << OCTOSPI_TCR_DCYC_Pos; // n dummy cycles
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OCTOSPI1->IR = cmd << OCTOSPI_IR_INSTRUCTION_Pos; // quad read opcode
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// This triggers the start of the operation.
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OCTOSPI1->AR = addr; // address to read from
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// Read in the data 4 bytes at a time if dest is aligned
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if (((uintptr_t)dest & 3) == 0) {
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while (len >= 4) {
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while (!(OCTOSPI1->SR & OCTOSPI_SR_FTF)) {
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if (OCTOSPI1->SR & OCTOSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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*(uint32_t *)dest = OCTOSPI1->DR;
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dest += 4;
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len -= 4;
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}
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}
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// Read in remaining data 1 byte at a time
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while (len) {
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while (!((OCTOSPI1->SR >> OCTOSPI_SR_FLEVEL_Pos) & 0x3f)) {
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if (OCTOSPI1->SR & OCTOSPI_SR_TEF) {
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return -MP_EIO;
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}
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}
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*dest++ = *(volatile uint8_t *)&OCTOSPI1->DR;
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--len;
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}
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OCTOSPI1->FCR = OCTOSPI_FCR_CTCF; // clear TC flag
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return 0;
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}
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const mp_qspi_proto_t octospi_proto = {
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.ioctl = octospi_ioctl,
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.write_cmd_data = octospi_write_cmd_data,
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.write_cmd_addr_data = octospi_write_cmd_addr_data,
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.read_cmd = octospi_read_cmd,
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.read_cmd_qaddr_qdata = octospi_read_cmd_qaddr_qdata,
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};
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#endif // defined(MICROPY_HW_OSPIFLASH_SIZE_BITS_LOG2)
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@ -0,0 +1,33 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
|
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*
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* The MIT License (MIT)
|
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*
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* Copyright (c) 2023 Damien P. George
|
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*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
#ifndef MICROPY_INCLUDED_STM32_OCTOSPI_H
|
||||
#define MICROPY_INCLUDED_STM32_OCTOSPI_H
|
||||
|
||||
#include "drivers/bus/qspi.h"
|
||||
|
||||
extern const mp_qspi_proto_t octospi_proto;
|
||||
|
||||
#endif // MICROPY_INCLUDED_STM32_OCTOSPI_H
|
||||
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Reference in New Issue