kopia lustrzana https://github.com/micropython/micropython
mimxrt/boards: Add board configuration files for Teensy 4.1.
These are at the moment more or less identical to the Teensy 4.0 files, except for the pins.csv file and the flash size.pull/7349/head
robert-hh
Damien George
rodzic
b8c65b174f
commit
53fea8598e
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@ -0,0 +1,2 @@
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flash_size = 8M;
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reserved_size = 4K;
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@ -0,0 +1,144 @@
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/*
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* Copyright 2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Based on tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.c
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#include "teensy41_flexspi_nor_config.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_board"
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#endif
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 3u,
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.csSetupTime = 3u,
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.busyOffset = FLASH_BUSY_STATUS_OFFSET, // Status bit 0 indicates busy.
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.busyBitPolarity = FLASH_BUSY_STATUS_POL, // Busy when the bit is 1.
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.deviceModeCfgEnable = 1u,
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.deviceModeType = kDeviceConfigCmdType_QuadEnable,
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.deviceModeSeq = {
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.seqId = 4u,
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.seqNum = 1u,
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},
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.deviceModeArg = 0x0200,
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.configCmdEnable = 1u,
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.configModeType[0] = kDeviceConfigCmdType_Generic,
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.configCmdSeqs[0] = {
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.seqId = 2u,
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.seqNum = 1u,
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},
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_60MHz,
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.sflashA1Size = 8u * 1024u * 1024u,
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.lookupTable =
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{
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// 0 Read LUTs 0 -> 0
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 1 Read status register -> 1
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x01),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 2 Fast read quad mode - SDR
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x6B, RADDR_SDR, FLEXSPI_1PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x08, READ_SDR, FLEXSPI_4PAD, 0x04),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 3 Write Enable -> 3
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 4 Read extend parameters
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x81, READ_SDR, FLEXSPI_1PAD, 0x04),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 5 Erase Sector -> 5
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 24),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 6 Write Status Reg
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x01, WRITE_SDR, FLEXSPI_1PAD, 0x04),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 7 Page Program - quad mode (-> 9)
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32, RADDR_SDR, FLEXSPI_1PAD, 0x18),
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FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04, STOP, FLEXSPI_1PAD, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 8 Read ID
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x90, DUMMY_SDR, FLEXSPI_1PAD, 24),
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FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, 0x00, 0, 0, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 9 Page Program - single mode -> 9
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 24),
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FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0, 0, 0, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 10 Enter QPI mode
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x35, STOP, FLEXSPI_1PAD, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 11 Erase Chip
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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// 12 Exit QPI mode
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_4PAD, 0xF5, STOP, FLEXSPI_1PAD, 0),
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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FLEXSPI_LUT_SEQ(0, 0, 0, 0, 0, 0), // Filler
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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};
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#endif /* XIP_BOOT_HEADER_ENABLE */
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@ -0,0 +1,10 @@
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#define MICROPY_HW_BOARD_NAME "Teensy 4.1"
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#define MICROPY_HW_MCU_NAME "MIMXRT1062DVJ6A"
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#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
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// Teensy 4.1 has 1 board LED
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#define MICROPY_HW_LED1_PIN (pin_GPIO_B0_03)
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#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_high(pin))
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#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_low(pin))
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#define BOARD_FLASH_CONFIG_HEADER_H "teensy41_flexspi_nor_config.h"
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@ -0,0 +1,7 @@
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MCU_SERIES = MIMXRT1062
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MCU_VARIANT = MIMXRT1062DVJ6A
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MICROPY_FLOAT_IMPL = double
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deploy: $(BUILD)/firmware.hex
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teensy_loader_cli --mcu=imxrt1062 -v -w $<
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@ -0,0 +1,83 @@
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D0,GPIO_AD_B0_03
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D1,GPIO_AD_B0_02
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D2,GPIO_EMC_04
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D3,GPIO_EMC_05
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D4,GPIO_EMC_06
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D5,GPIO_EMC_08
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D6,GPIO_B0_10
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D7,GPIO_B1_01
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D8,GPIO_B1_00
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D9,GPIO_B0_11
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D10,GPIO_B0_00
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D11,GPIO_B0_02
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D12,GPIO_B0_01
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D13,GPIO_B0_03
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D14,GPIO_AD_B1_02
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D15,GPIO_AD_B1_03
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D16,GPIO_AD_B1_07
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D17,GPIO_AD_B1_06
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D18,GPIO_AD_B1_01
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D19,GPIO_AD_B1_00
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D20,GPIO_AD_B1_10
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D21,GPIO_AD_B1_11
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D22,GPIO_AD_B1_08
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D23,GPIO_AD_B1_09
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D24,GPIO_AD_B0_12
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D25,GPIO_AD_B0_13
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D26,GPIO_AD_B1_14
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D27,GPIO_AD_B1_15
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D28,GPIO_EMC_32
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D29,GPIO_EMC_31
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D30,GPIO_EMC_37
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D31,GPIO_EMC_36
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D32,GPIO_B0_12
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D33,GPIO_EMC_07
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D34,GPIO_B1_13
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D35,GPIO_B1_12
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D36,GPIO_B1_02
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D37,GPIO_B1_03
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D38,GPIO_AD_B1_12
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D39,GPIO_AD_B1_13
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D40,GPIO_AD_B1_04
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D41,GPIO_AD_B1_05
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D42,GPIO_SD_B0_03
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D43,GPIO_SD_B0_02
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D44,GPIO_SD_B0_01
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D45,GPIO_SD_B0_00
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D46,GPIO_SD_B0_05
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D47,GPIO_SD_B0_04
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D48,GPIO_EMC_24
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D49,GPIO_EMC_27
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D50,GPIO_EMC_28
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D51,GPIO_EMC_22
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D52,GPIO_EMC_26
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D53,GPIO_EMC_25
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D54,GPIO_EMC_29
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DAT1,GPIO_SD_B0_03
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DAT0,GPIO_SD_B0_02
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CLK,GPIO_SD_B0_01
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CMD,GPIO_SD_B0_00
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DAT3,GPIO_SD_B0_05
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DAT2,GPIO_SD_B0_04
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PSRAM_CS,GPIO_EMC_24
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QSPI_IO1,GPIO_EMC_27
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QSPI_IO2,GPIO_EMC_28
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FLASH_CS,GPIO_EMC_22
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QSPI_IO0,GPIO_EMC_26
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QSPI_CLK,GPIO_EMC_25
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QSPI_IO3,GPIO_EMC_29
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A0,GPIO_AD_B1_02
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A1,GPIO_AD_B1_03
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A2,GPIO_AD_B1_07
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A3,GPIO_AD_B1_06
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A4,GPIO_AD_B1_01
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A5,GPIO_AD_B1_00
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A6,GPIO_AD_B1_10
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A7,GPIO_AD_B1_11
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A8,GPIO_AD_B1_08
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A9,GPIO_AD_B1_09
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A10,GPIO_AD_B0_12
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A11,GPIO_AD_B0_13
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A12,GPIO_AD_B1_14
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A13,GPIO_AD_B1_15
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LED,GPIO_B0_03
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@ -0,0 +1,259 @@
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/*
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* Copyright 2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// Based on tinyusb/hw/bsp/teensy_40/teensy40_flexspi_nor_config.h
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#ifndef __TEENSY40_FLEXSPI_NOR_CONFIG__
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#define __TEENSY40_FLEXSPI_NOR_CONFIG__
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#include <stdint.h>
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#include <stdbool.h>
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#include "fsl_common.h"
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/*! @name Driver version */
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/*@{*/
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/*! @brief XIP_BOARD driver version 2.0.0. */
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#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
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/*@}*/
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/* FLEXSPI memory config block related defintions */
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#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
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#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
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#define FLEXSPI_CFG_BLK_SIZE (512)
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/* FLEXSPI Feature related definitions */
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#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
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/* Lookup table related definitions */
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#define CMD_INDEX_READ 0
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#define CMD_INDEX_READSTATUS 1
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#define CMD_INDEX_WRITEENABLE 2
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#define CMD_INDEX_WRITE 4
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#define CMD_LUT_SEQ_IDX_READ 0
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#define CMD_LUT_SEQ_IDX_READSTATUS 1
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#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
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#define CMD_LUT_SEQ_IDX_ERASE 5
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#define CMD_LUT_SEQ_IDX_WRITE 9
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#define CMD_SDR 0x01
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#define CMD_DDR 0x21
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#define RADDR_SDR 0x02
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#define RADDR_DDR 0x22
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#define CADDR_SDR 0x03
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#define CADDR_DDR 0x23
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#define MODE1_SDR 0x04
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#define MODE1_DDR 0x24
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#define MODE2_SDR 0x05
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#define MODE2_DDR 0x25
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#define MODE4_SDR 0x06
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#define MODE4_DDR 0x26
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#define MODE8_SDR 0x07
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#define MODE8_DDR 0x27
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#define WRITE_SDR 0x08
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#define WRITE_DDR 0x28
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#define READ_SDR 0x09
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#define READ_DDR 0x29
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#define LEARN_SDR 0x0A
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#define LEARN_DDR 0x2A
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#define DATSZ_SDR 0x0B
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#define DATSZ_DDR 0x2B
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#define DUMMY_SDR 0x0C
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#define DUMMY_DDR 0x2C
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#define DUMMY_RWDS_SDR 0x0D
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#define DUMMY_RWDS_DDR 0x2D
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#define JMP_ON_CS 0x1F
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#define STOP 0
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#define FLEXSPI_1PAD 0
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#define FLEXSPI_2PAD 1
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#define FLEXSPI_4PAD 2
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#define FLEXSPI_8PAD 3
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#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
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FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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//!@brief Definitions for FlexSPI Serial Clock Frequency
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typedef enum _FlexSpiSerialClockFreq
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{
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kFlexSpiSerialClk_30MHz = 1,
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kFlexSpiSerialClk_50MHz = 2,
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kFlexSpiSerialClk_60MHz = 3,
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kFlexSpiSerialClk_75MHz = 4,
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kFlexSpiSerialClk_80MHz = 5,
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kFlexSpiSerialClk_100MHz = 6,
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kFlexSpiSerialClk_120MHz = 7,
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kFlexSpiSerialClk_133MHz = 8,
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kFlexSpiSerialClk_166MHz = 9,
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} flexspi_serial_clk_freq_t;
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//!@brief FlexSPI clock configuration type
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enum
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{
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kFlexSpiClk_SDR, //!< Clock configure for SDR mode
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kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
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};
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//!@brief FlexSPI Read Sample Clock Source definition
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typedef enum _FlashReadSampleClkSource
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{
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kFlexSPIReadSampleClk_LoopbackInternally = 0,
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kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
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kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
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kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
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} flexspi_read_sample_clk_t;
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//!@brief Misc feature bit definitions
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enum
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{
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kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
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kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
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kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
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kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
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kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
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kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
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kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
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};
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//!@brief Flash Type Definition
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enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 0
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 1
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 2
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI 4
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 6
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 7
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READID 8
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 12
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t reserved0[2]; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t reserve2[11]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#define FLASH_BUSY_STATUS_POL 0
|
||||
#define FLASH_BUSY_STATUS_OFFSET 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */
|
||||
Ładowanie…
Reference in New Issue