kopia lustrzana https://github.com/micropython/micropython
samd/DMA: Add a DMA manager.
Used for allocation of DMA channels. It will be needed for planned modules and methods like adc_timed(), dac_timed(), I2S. It includes management code for DMA IRQ handlers, similar to what was made for Sercom. Signed-off-by: robert-hh <robert@hammelrath.com>pull/9624/head
robert-hh
rodzic
d11ca092f7
commit
43d33289df
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <string.h>
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#include "py/mpconfig.h"
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#include "sam.h"
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#include "dma_manager.h"
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#include "samd_soc.h"
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// Set a number of dma channels managed here. samd21 has 21 dma channels, samd51
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// has 32 channels, as defined by the lib macro DMAC_CH_NUM.
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// At first, we use a smaller number here to save RAM. May be increased as needed.
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#ifndef MICROPY_HW_DMA_CHANNELS
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#if defined(MCU_SAMD21)
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#define MICROPY_HW_DMA_CHANNELS 2
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#elif defined(MCU_SAMD51)
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#define MICROPY_HW_DMA_CHANNELS 4
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#endif
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#endif
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#if MICROPY_HW_DMA_CHANNELS > DMAC_CH_NUM
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#error Number of DMA channels too large
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#endif
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volatile DmacDescriptor dma_desc[MICROPY_HW_DMA_CHANNELS] __attribute__ ((aligned(16)));
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static volatile DmacDescriptor dma_write_back[MICROPY_HW_DMA_CHANNELS] __attribute__ ((aligned(16)));
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// List of channel flags: true: channel used, false: channel available
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static bool channel_list[MICROPY_HW_DMA_CHANNELS];
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STATIC bool dma_initialized = false;
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// allocate_channel(): retrieve an available channel. Return the number or -1
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int allocate_dma_channel(void) {
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for (int i = 0; i < MP_ARRAY_SIZE(channel_list); i++) {
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if (channel_list[i] == false) { // Channel available
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channel_list[i] = true;
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return i;
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}
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}
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mp_raise_ValueError(MP_ERROR_TEXT("no dma channel available"));
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}
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// free_channel(n): Declare channel as free
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void free_dma_channel(int n) {
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if (n >= 0 && n < MP_ARRAY_SIZE(channel_list)) {
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channel_list[n] = false;
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}
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}
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void dma_init(void) {
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if (!dma_initialized) {
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// Enable the DMA clock
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#if defined(MCU_SAMD21)
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PM->AHBMASK.reg |= PM_AHBMASK_DMAC;
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PM->APBBMASK.reg |= PM_APBBMASK_DMAC;
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#elif defined(MCU_SAMD51)
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MCLK->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
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#endif
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// Setup the initial DMA configuration
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DMAC->CTRL.reg = DMAC_CTRL_SWRST;
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while (DMAC->CTRL.reg & DMAC_CTRL_SWRST) {
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}
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// Set the DMA descriptor pointers
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DMAC->BASEADDR.reg = (uint32_t)dma_desc;
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DMAC->WRBADDR.reg = (uint32_t)dma_write_back;
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// Enable the DMA
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DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
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dma_initialized = true;
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}
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}
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void dma_deinit(void) {
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memset((uint8_t *)dma_desc, 0, sizeof(dma_desc));
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memset((uint8_t *)dma_write_back, 0, sizeof(dma_write_back));
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memset((uint8_t *)channel_list, 0, sizeof(channel_list));
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dma_initialized = false;
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// Disable DMA
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DMAC->CTRL.reg = 0;
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for (int ch = 0; ch < DMAC_CH_NUM; ch++) {
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dma_register_irq(ch, NULL);
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}
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}
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void dac_stop_dma(int dma_channel, bool wait) {
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#if defined(MCU_SAMD21)
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NVIC_DisableIRQ(DMAC_IRQn);
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DMAC->CHID.reg = dma_channel;
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DMAC->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_TERR | DMAC_CHINTENSET_SUSP;
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DMAC->CHCTRLA.reg = 0;
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while (wait && DMAC->CHCTRLA.bit.ENABLE) {
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}
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#elif defined(MCU_SAMD51)
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if (0 <= dma_channel && dma_channel < 4) {
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NVIC_DisableIRQ(DMAC_0_IRQn + dma_channel);
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} else if (dma_channel >= 4) {
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NVIC_DisableIRQ(DMAC_4_IRQn);
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}
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DMAC->Channel[dma_channel].CHINTENCLR.reg =
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DMAC_CHINTENSET_TCMPL | DMAC_CHINTENSET_TERR | DMAC_CHINTENSET_SUSP;
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DMAC->Channel[dma_channel].CHCTRLA.reg = 0;
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while (wait && DMAC->Channel[dma_channel].CHCTRLA.bit.ENABLE) {
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}
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#endif
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}
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@ -0,0 +1,38 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MICROPY_INCLUDED_SAMD_DMACHANNEL_H
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#define MICROPY_INCLUDED_SAMD_DMACHANNEL_H
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#include "py/runtime.h"
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int allocate_dma_channel(void);
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void free_dma_channel(int n);
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void dma_init(void);
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void dma_deinit(void);
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extern volatile DmacDescriptor dma_desc[];
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#endif // MICROPY_INCLUDED_SAMD_DMACHANNEL_H
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@ -164,6 +164,51 @@ void Sercom7_Handler(void) {
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}
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#endif
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// DMAC IRQ handler support
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#if defined(MCU_SAMD21)
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#define DMAC_FIRST_CHANNEL 0
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#else
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#define DMAC_FIRST_CHANNEL 4
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#endif
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void (*dma_irq_handler_table[DMAC_CH_NUM])(int num) = {};
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void dma_register_irq(int dma_channel, void (*dma_irq_handler)) {
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if (dma_channel < DMAC_CH_NUM) {
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dma_irq_handler_table[dma_channel] = dma_irq_handler;
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}
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}
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void DMAC0_Handler(void) {
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if (dma_irq_handler_table[0]) {
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dma_irq_handler_table[0](0);
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}
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}
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void DMAC1_Handler(void) {
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if (dma_irq_handler_table[1]) {
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dma_irq_handler_table[1](1);
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}
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}
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void DMAC2_Handler(void) {
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if (dma_irq_handler_table[2]) {
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dma_irq_handler_table[2](2);
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}
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}
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void DMAC3_Handler(void) {
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if (dma_irq_handler_table[3]) {
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dma_irq_handler_table[3](3);
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}
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}
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void DMACn_Handler(void) {
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for (uint32_t mask = 1 << DMAC_FIRST_CHANNEL, dma_channel = DMAC_FIRST_CHANNEL;
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dma_channel < DMAC_CH_NUM;
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mask <<= 1, dma_channel += 1) {
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if ((DMAC->INTSTATUS.reg & mask) && dma_irq_handler_table[dma_channel]) {
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dma_irq_handler_table[dma_channel](dma_channel);
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}
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}
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}
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#if defined(MCU_SAMD21)
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const ISR isr_vector[] __attribute__((section(".isr_vector"))) = {
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(ISR)&_estack,
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@ -188,7 +233,7 @@ const ISR isr_vector[] __attribute__((section(".isr_vector"))) = {
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0, // 3 Real-Time Counter (RTC)
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&EIC_Handler, // 4 External Interrupt Controller (EIC)
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0, // 5 Non-Volatile Memory Controller (NVMCTRL)
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0, // 6 Direct Memory Access Controller (DMAC)
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&DMACn_Handler, // 6 Direct Memory Access Controller (DMAC)
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USB_Handler_wrapper,// 7 Universal Serial Bus (USB)
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0, // 8 Event System Interface (EVSYS)
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&Sercom0_Handler, // 9 Serial Communication Interface 0 (SERCOM0)
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@ -261,11 +306,11 @@ const ISR isr_vector[] __attribute__((section(".isr_vector"))) = {
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0, // 28 Frequency Meter (FREQM)
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0, // 29 Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0 - _7
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0, // 30 Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_8 - _10
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0, // 31 Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0
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0, // 32 Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1
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0, // 33 Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2
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0, // 34 Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3
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0, // 35 Direct Memory Access Controller (DMAC): DMAC_SUSP_4 - _31, DMAC_TCMPL_4 _31, DMAC_TERR_4- _31
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&DMAC0_Handler, // 31 Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0
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&DMAC1_Handler, // 32 Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1
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&DMAC2_Handler, // 33 Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2
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&DMAC3_Handler, // 34 Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3
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&DMACn_Handler, // 35 Direct Memory Access Controller (DMAC): DMAC_SUSP_4 - _31, DMAC_TCMPL_4 _31, DMAC_TERR_4- _31
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0, // 36 Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0
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0, // 37 Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1
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0, // 38 Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2
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@ -43,6 +43,7 @@ void USB_Handler_wrapper(void);
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void sercom_enable(Sercom *spi, int state);
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void sercom_register_irq(int sercom_id, void (*sercom_irq_handler));
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void dma_register_irq(int dma_channel, void (*dma_irq_handler));
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// Each device has a unique 128-bit serial number. The uniqueness of the serial number is
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// guaranteed only when using all 128 bits.
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