diff --git a/ports/stm32/boards/ARDUINO_GIGA/bdev.c b/ports/stm32/boards/ARDUINO_GIGA/bdev.c new file mode 100644 index 0000000000..caadc2b649 --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/bdev.c @@ -0,0 +1,45 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2023 Arduino SA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "storage.h" +#include "qspi.h" + +#if MICROPY_HW_SPIFLASH_ENABLE_CACHE +// Shared cache for first and second SPI block devices +STATIC mp_spiflash_cache_t spi_bdev_cache; +#endif + +// First external SPI flash uses hardware QSPI interface +const mp_spiflash_config_t spiflash_config = { + .bus_kind = MP_SPIFLASH_BUS_QSPI, + .bus.u_qspi.data = NULL, + .bus.u_qspi.proto = &qspi_proto, + #if MICROPY_HW_SPIFLASH_ENABLE_CACHE + .cache = &spi_bdev_cache, + #endif +}; + +spi_bdev_t spi_bdev; diff --git a/ports/stm32/boards/ARDUINO_GIGA/board.json b/ports/stm32/boards/ARDUINO_GIGA/board.json new file mode 100644 index 0000000000..3a6ddc9ed1 --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/board.json @@ -0,0 +1,21 @@ +{ + "deploy": [ + "./deploy.md" + ], + "docs": "", + "features": [ + "8MB SDRAM", + "16MB Flash", + "Dual-core processor", + "USB Full speed", + "CYW43 WiFi/BT Module" + ], + "images": [ + "ABX00063_01.front_1000x750.jpg" + ], + "mcu": "STM32H747", + "product": "Arduino Giga", + "thumbnail": "", + "url": "https://store.arduino.cc/products/giga-r1-wifi", + "vendor": "Arduino" +} diff --git a/ports/stm32/boards/ARDUINO_GIGA/board_init.c b/ports/stm32/boards/ARDUINO_GIGA/board_init.c new file mode 100644 index 0000000000..bdec04643b --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/board_init.c @@ -0,0 +1,95 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2023 Arduino SA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "py/mphal.h" +#include "storage.h" +#include "sdram.h" + +void GIGA_board_startup(void) { +} + +void GIGA_board_early_init(void) { + HAL_InitTick(0); + + #if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE == 1 + // The Arduino/mbed bootloader uses the MPU to protect sector 1 + // which is used for the flash filesystem. The following code + // resets and disables all MPU regions configured in the bootloader. + HAL_MPU_Disable(); + MPU_Region_InitTypeDef MPU_InitStruct; + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; + MPU_InitStruct.SubRegionDisable = 0x00; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; + + for (int i = MPU_REGION_NUMBER0; i < MPU_REGION_NUMBER15; i++) { + MPU_InitStruct.Number = i; + MPU_InitStruct.Enable = MPU_REGION_DISABLE; + HAL_MPU_ConfigRegion(&MPU_InitStruct); + } + #endif +} + +void GIGA_board_enter_bootloader(void) { + RTC_HandleTypeDef RTCHandle; + RTCHandle.Instance = RTC; + HAL_RTCEx_BKUPWrite(&RTCHandle, RTC_BKP_DR0, 0xDF59); + NVIC_SystemReset(); +} + +void GIGA_board_low_power(int mode) { + switch (mode) { + case 0: // Leave stop mode. + sdram_leave_low_power(); + break; + case 1: // Enter stop mode. + sdram_enter_low_power(); + break; + case 2: // Enter standby mode. + sdram_enter_power_down(); + break; + } + + #if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE == 0 + // Enable QSPI deepsleep for modes 1 and 2 + mp_spiflash_deepsleep(&spi_bdev.spiflash, (mode != 0)); + #endif + + #if defined(M4_APP_ADDR) + // Signal Cortex-M4 to go to Standby mode. + if (mode == 2) { + __HAL_RCC_HSEM_CLK_ENABLE(); + HAL_HSEM_FastTake(0); + HAL_HSEM_Release(0, 0); + __HAL_RCC_HSEM_CLK_DISABLE(); + HAL_Delay(100); + } + #endif +} diff --git a/ports/stm32/boards/ARDUINO_GIGA/deploy.md b/ports/stm32/boards/ARDUINO_GIGA/deploy.md new file mode 100644 index 0000000000..6013ef30ac --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/deploy.md @@ -0,0 +1,14 @@ +### Via dfu-util + +This board can programmed via DFU bootloader, using e.g. [dfu-util](http://dfu-util.sourceforge.net/). +To enter the DFU bootloader, double tap the reset (blue) button, or you can use `machine.bootloader()` from the MicroPython REPL. + +```bash +dfu-util -w -a 0 -d 2341:035b -D build-ARDUINO_GIGA/firmware.dfu +``` + +Or from MicroPython source repository: + +```bash +make BOARD=ARDUINO_GIGA deploy +``` diff --git a/ports/stm32/boards/ARDUINO_GIGA/manifest.py b/ports/stm32/boards/ARDUINO_GIGA/manifest.py new file mode 100644 index 0000000000..1db4b8054c --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/manifest.py @@ -0,0 +1,11 @@ +include("$(PORT_DIR)/boards/manifest.py") + +# Networking +require("bundle-networking") + +# Utils +require("time") +require("logging") + +# Bluetooth +require("aioble") diff --git a/ports/stm32/boards/ARDUINO_GIGA/mbedtls_config_board.h b/ports/stm32/boards/ARDUINO_GIGA/mbedtls_config_board.h new file mode 100644 index 0000000000..0e1703f1bf --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/mbedtls_config_board.h @@ -0,0 +1,8 @@ +#ifndef MICROPY_INCLUDED_MBEDTLS_CONFIG_BOARD_H +#define MICROPY_INCLUDED_MBEDTLS_CONFIG_BOARD_H + +#define MBEDTLS_ECP_NIST_OPTIM + +#include "ports/stm32/mbedtls/mbedtls_config.h" + +#endif /* MICROPY_INCLUDED_MBEDTLS_CONFIG_BOARD_H */ diff --git a/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h new file mode 100644 index 0000000000..cc38b0a7ca --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.h @@ -0,0 +1,318 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2023 Arduino SA + */ + +#define MICROPY_HW_BOARD_NAME "GIGA" +#define MICROPY_HW_MCU_NAME "STM32H747" +#define MICROPY_PY_SYS_PLATFORM "Giga" +#define MICROPY_HW_FLASH_FS_LABEL "Giga" + +#define MICROPY_OBJ_REPR (MICROPY_OBJ_REPR_C) +#define UINT_FMT "%u" +#define INT_FMT "%d" +typedef int mp_int_t; // must be pointer size +typedef unsigned int mp_uint_t; // must be pointer size + +#define MICROPY_FATFS_EXFAT (1) +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_ENABLE_RNG (1) +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_ENABLE_DAC (1) +#define MICROPY_HW_ENABLE_USB (1) +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_SERVO (1) +#define MICROPY_HW_ENABLE_TIMER (1) +#define MICROPY_HW_ENABLE_SDCARD (0) +#define MICROPY_HW_ENABLE_MMCARD (0) + +// Flash storage config +#define MICROPY_HW_SPIFLASH_ENABLE_CACHE (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +#define MICROPY_BOARD_STARTUP GIGA_board_startup +void GIGA_board_startup(void); + +#define MICROPY_BOARD_EARLY_INIT GIGA_board_early_init +void GIGA_board_early_init(void); + +#define MICROPY_BOARD_ENTER_BOOTLOADER(nargs, args) GIGA_board_enter_bootloader() +void GIGA_board_enter_bootloader(void); + +void GIGA_board_low_power(int mode); +#define MICROPY_BOARD_LEAVE_STOP GIGA_board_low_power(0); +#define MICROPY_BOARD_ENTER_STOP GIGA_board_low_power(1); +#define MICROPY_BOARD_ENTER_STANDBY GIGA_board_low_power(2); + +void GIGA_board_osc_enable(int enable); +#define MICROPY_BOARD_OSC_ENABLE GIGA_board_osc_enable(1); +#define MICROPY_BOARD_OSC_DISABLE GIGA_board_osc_enable(0); + +// PLL1 480MHz/48MHz SDMMC and FDCAN +// USB and RNG are clocked from the HSI48 +#define MICROPY_HW_CLK_PLLM (4) +#define MICROPY_HW_CLK_PLLN (240) +#define MICROPY_HW_CLK_PLLP (2) +#define MICROPY_HW_CLK_PLLQ (20) +#define MICROPY_HW_CLK_PLLR (2) +#define MICROPY_HW_CLK_PLLVCI (RCC_PLL1VCIRANGE_2) +#define MICROPY_HW_CLK_PLLVCO (RCC_PLL1VCOWIDE) +#define MICROPY_HW_CLK_PLLFRAC (0) + +// PLL2 200MHz for FMC and QSPI. +#define MICROPY_HW_CLK_PLL2M (4) +#define MICROPY_HW_CLK_PLL2N (100) +#define MICROPY_HW_CLK_PLL2P (2) +#define MICROPY_HW_CLK_PLL2Q (2) +#define MICROPY_HW_CLK_PLL2R (2) +#define MICROPY_HW_CLK_PLL2VCI (RCC_PLL2VCIRANGE_2) +#define MICROPY_HW_CLK_PLL2VCO (RCC_PLL2VCOWIDE) +#define MICROPY_HW_CLK_PLL2FRAC (0) + +// PLL3 160MHz for ADC and SPI123 +#define MICROPY_HW_CLK_PLL3M (4) +#define MICROPY_HW_CLK_PLL3N (80) +#define MICROPY_HW_CLK_PLL3P (2) +#define MICROPY_HW_CLK_PLL3Q (2) +#define MICROPY_HW_CLK_PLL3R (2) +#define MICROPY_HW_CLK_PLL3VCI (RCC_PLL3VCIRANGE_2) +#define MICROPY_HW_CLK_PLL3VCO (RCC_PLL3VCOWIDE) +#define MICROPY_HW_CLK_PLL3FRAC (0) + +// HSE in BYPASS mode. +#define MICROPY_HW_CLK_USE_BYPASS (0) + +// Bus clock divider values +#define MICROPY_HW_CLK_AHB_DIV (RCC_HCLK_DIV2) +#define MICROPY_HW_CLK_APB1_DIV (RCC_APB1_DIV2) +#define MICROPY_HW_CLK_APB2_DIV (RCC_APB2_DIV2) +#define MICROPY_HW_CLK_APB3_DIV (RCC_APB3_DIV2) +#define MICROPY_HW_CLK_APB4_DIV (RCC_APB4_DIV2) + +// Peripheral clock sources +#define MICROPY_HW_RCC_HSI48_STATE (RCC_HSI48_ON) +#define MICROPY_HW_RCC_USB_CLKSOURCE (RCC_USBCLKSOURCE_HSI48) +#define MICROPY_HW_RCC_RTC_CLKSOURCE (RCC_RTCCLKSOURCE_LSI) +#define MICROPY_HW_RCC_FMC_CLKSOURCE (RCC_FMCCLKSOURCE_PLL2) +#define MICROPY_HW_RCC_RNG_CLKSOURCE (RCC_RNGCLKSOURCE_HSI48) +#define MICROPY_HW_RCC_ADC_CLKSOURCE (RCC_ADCCLKSOURCE_PLL3) +#define MICROPY_HW_RCC_SDMMC_CLKSOURCE (RCC_SDMMCCLKSOURCE_PLL) +#define MICROPY_HW_RCC_FDCAN_CLKSOURCE (RCC_FDCANCLKSOURCE_PLL) +#define MICROPY_HW_RCC_SPI123_CLKSOURCE (RCC_SPI123CLKSOURCE_PLL3) +#define MICROPY_HW_RCC_I2C123_CLKSOURCE (RCC_I2C123CLKSOURCE_D2PCLK1) +#define MICROPY_HW_RCC_QSPI_CLKSOURCE (RCC_QSPICLKSOURCE_PLL2) + +// SMPS configuration +#define MICROPY_HW_PWR_SMPS_CONFIG (PWR_LDO_SUPPLY) + +// There is an external 32kHz oscillator +#define RTC_ASYNCH_PREDIV (0) +#define RTC_SYNCH_PREDIV (0x7fff) +#define MICROPY_HW_RTC_USE_BYPASS (0) +#define MICROPY_HW_RTC_USE_US (1) +#define MICROPY_HW_RTC_USE_CALOUT (1) + +#if !MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE +// QSPI flash #1 for storage +#define MICROPY_HW_QSPI_PRESCALER (2) // 100MHz +#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (27) +// Reserve 1MiB at the end for compatibility with alternate firmware that places WiFi blob here. +#define MICROPY_HW_SPIFLASH_SIZE_BITS (120 * 1024 * 1024) +#define MICROPY_HW_QSPIFLASH_CS (pyb_pin_QSPI2_CS) +#define MICROPY_HW_QSPIFLASH_SCK (pyb_pin_QSPI2_CLK) +#define MICROPY_HW_QSPIFLASH_IO0 (pyb_pin_QSPI2_D0) +#define MICROPY_HW_QSPIFLASH_IO1 (pyb_pin_QSPI2_D1) +#define MICROPY_HW_QSPIFLASH_IO2 (pyb_pin_QSPI2_D2) +#define MICROPY_HW_QSPIFLASH_IO3 (pyb_pin_QSPI2_D3) + +// SPI flash #1, block device config +extern const struct _mp_spiflash_config_t spiflash_config; +extern struct _spi_bdev_t spi_bdev; +#define MICROPY_HW_BDEV_IOCTL(op, arg) ( \ + (op) == BDEV_IOCTL_NUM_BLOCKS ? (MICROPY_HW_SPIFLASH_SIZE_BITS / 8 / FLASH_BLOCK_SIZE) : \ + (op) == BDEV_IOCTL_INIT ? spi_bdev_ioctl(&spi_bdev, (op), (uint32_t)&spiflash_config) : \ + spi_bdev_ioctl(&spi_bdev, (op), (arg)) \ + ) +#define MICROPY_HW_BDEV_READBLOCKS(dest, bl, n) spi_bdev_readblocks(&spi_bdev, (dest), (bl), (n)) +#define MICROPY_HW_BDEV_WRITEBLOCKS(src, bl, n) spi_bdev_writeblocks(&spi_bdev, (src), (bl), (n)) +#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev) +#endif + +// 4 wait states +#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_2 + +// UART config +#define MICROPY_HW_UART1_TX (pyb_pin_UART1_TX) +#define MICROPY_HW_UART1_RX (pyb_pin_UART1_RX) +#define MICROPY_HW_UART_REPL PYB_UART_1 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +#define MICROPY_HW_UART2_TX (pyb_pin_UART2_TX) +#define MICROPY_HW_UART2_RX (pyb_pin_UART2_RX) + +#define MICROPY_HW_UART4_TX (pyb_pin_UART4_TX) +#define MICROPY_HW_UART4_RX (pyb_pin_UART4_RX) + +#define MICROPY_HW_UART6_TX (pyb_pin_UART6_TX) +#define MICROPY_HW_UART6_RX (pyb_pin_UART6_RX) + +#define MICROPY_HW_UART7_TX (pyb_pin_BT_TXD) +#define MICROPY_HW_UART7_RX (pyb_pin_BT_RXD) +#define MICROPY_HW_UART7_RTS (pyb_pin_BT_RTS) +#define MICROPY_HW_UART7_CTS (pyb_pin_BT_CTS) + +// I2C busses +#define MICROPY_HW_I2C1_SCL (pyb_pin_I2C1_SCL) +#define MICROPY_HW_I2C1_SDA (pyb_pin_I2C1_SDA) + +#define MICROPY_HW_I2C2_SCL (pyb_pin_I2C2_SCL) +#define MICROPY_HW_I2C2_SDA (pyb_pin_I2C2_SDA) + +#define MICROPY_HW_I2C4_SCL (pyb_pin_I2C4_SCL) +#define MICROPY_HW_I2C4_SDA (pyb_pin_I2C4_SDA) + +// SPI config +// #define MICROPY_HW_SPI1_NSS (pyb_pin_SPI1_NSS) +#define MICROPY_HW_SPI1_SCK (pyb_pin_SPI1_SCK) +#define MICROPY_HW_SPI1_MISO (pyb_pin_SPI1_MISO) +#define MICROPY_HW_SPI1_MOSI (pyb_pin_SPI1_MOSI) + +#define MICROPY_HW_SPI5_NSS (pyb_pin_SPI5_NSS) +#define MICROPY_HW_SPI5_SCK (pyb_pin_SPI5_SCK) +#define MICROPY_HW_SPI5_MISO (pyb_pin_SPI5_MISO) +#define MICROPY_HW_SPI5_MOSI (pyb_pin_SPI5_MOSI) + +// USRSW is pulled low. Pressing the button makes the input go high. +#define MICROPY_HW_USRSW_PIN (pin_C13) +#define MICROPY_HW_USRSW_PULL (GPIO_PULLDOWN) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING) +#define MICROPY_HW_USRSW_PRESSED (1) + +// LEDs +#define MICROPY_HW_LED1 (pyb_pin_LEDR) // red +#define MICROPY_HW_LED2 (pyb_pin_LEDG) // green +#define MICROPY_HW_LED3 (pyb_pin_LEDB) // yellow +#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin)) +#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin)) + +// WiFi SDMMC +#define MICROPY_HW_SDIO_SDMMC (1) +#define MICROPY_HW_SDIO_CK (pyb_pin_WL_SDIO_CLK) +#define MICROPY_HW_SDIO_CMD (pyb_pin_WL_SDIO_CMD) +#define MICROPY_HW_SDIO_D0 (pyb_pin_WL_SDIO_0) +#define MICROPY_HW_SDIO_D1 (pyb_pin_WL_SDIO_1) +#define MICROPY_HW_SDIO_D2 (pyb_pin_WL_SDIO_2) +#define MICROPY_HW_SDIO_D3 (pyb_pin_WL_SDIO_3) + +// CYW43 config +#define CYW43_WIFI_NVRAM_INCLUDE_FILE "wifi_nvram_1dx.h" + +// USB config +#define MICROPY_HW_USB_FS (1) + +#define MICROPY_HW_USB_CDC_RX_DATA_SIZE (1024) +#define MICROPY_HW_USB_CDC_TX_DATA_SIZE (1024) +#define MICROPY_HW_USB_CDC_1200BPS_TOUCH (1) + +// Bluetooth config +#define MICROPY_HW_BLE_UART_ID (PYB_UART_7) +#define MICROPY_HW_BLE_UART_BAUDRATE (115200) +#define MICROPY_HW_BLE_UART_BAUDRATE_SECONDARY (3000000) + +// SDRAM +#define MICROPY_HW_SDRAM_SIZE (64 / 8 * 1024 * 1024) // 64 Mbit +#define MICROPY_HW_SDRAM_STARTUP_TEST (1) +#define MICROPY_HW_SDRAM_TEST_FAIL_ON_ERROR (true) + +// Timing configuration for 200MHz/2=100MHz (10ns) +#define MICROPY_HW_SDRAM_CLOCK_PERIOD 2 +#define MICROPY_HW_SDRAM_CAS_LATENCY 2 +#define MICROPY_HW_SDRAM_FREQUENCY (100000) // 100 MHz +#define MICROPY_HW_SDRAM_TIMING_TMRD (2) +#define MICROPY_HW_SDRAM_TIMING_TXSR (7) +#define MICROPY_HW_SDRAM_TIMING_TRAS (5) +#define MICROPY_HW_SDRAM_TIMING_TRC (7) +#define MICROPY_HW_SDRAM_TIMING_TWR (2) +#define MICROPY_HW_SDRAM_TIMING_TRP (3) +#define MICROPY_HW_SDRAM_TIMING_TRCD (3) + +#define MICROPY_HW_SDRAM_ROW_BITS_NUM 12 +#define MICROPY_HW_SDRAM_MEM_BUS_WIDTH 16 +#define MICROPY_HW_SDRAM_REFRESH_CYCLES 4096 + +#define MICROPY_HW_SDRAM_COLUMN_BITS_NUM 8 +#define MICROPY_HW_SDRAM_INTERN_BANKS_NUM 4 +#define MICROPY_HW_SDRAM_RPIPE_DELAY 0 +#define MICROPY_HW_SDRAM_RBURST (1) +#define MICROPY_HW_SDRAM_WRITE_PROTECTION (0) + +#define MICROPY_HW_SDRAM_AUTOREFRESH_NUM (8) +#define MICROPY_HW_SDRAM_BURST_LENGTH 1 +#define MICROPY_HW_SDRAM_REFRESH_RATE (64) // ms + +// SDRAM configuration +#define MICROPY_HW_FMC_SDCKE0 (pin_H2) +#define MICROPY_HW_FMC_SDNE0 (pin_H3) +#define MICROPY_HW_FMC_SDNBL0 (pin_E0) +#define MICROPY_HW_FMC_SDNBL1 (pin_E1) +#define MICROPY_HW_FMC_SDCLK (pin_G8) +#define MICROPY_HW_FMC_SDNCAS (pin_G15) +#define MICROPY_HW_FMC_SDNRAS (pin_F11) +#define MICROPY_HW_FMC_SDNWE (pin_H5) +#define MICROPY_HW_FMC_BA0 (pin_G4) +#define MICROPY_HW_FMC_BA1 (pin_G5) +#define MICROPY_HW_FMC_NBL0 (pin_E0) +#define MICROPY_HW_FMC_NBL1 (pin_E1) +#define MICROPY_HW_FMC_A0 (pin_F0) +#define MICROPY_HW_FMC_A1 (pin_F1) +#define MICROPY_HW_FMC_A2 (pin_F2) +#define MICROPY_HW_FMC_A3 (pin_F3) +#define MICROPY_HW_FMC_A4 (pin_F4) +#define MICROPY_HW_FMC_A5 (pin_F5) +#define MICROPY_HW_FMC_A6 (pin_F12) +#define MICROPY_HW_FMC_A7 (pin_F13) +#define MICROPY_HW_FMC_A8 (pin_F14) +#define MICROPY_HW_FMC_A9 (pin_F15) +#define MICROPY_HW_FMC_A10 (pin_G0) +#define MICROPY_HW_FMC_A11 (pin_G1) +#define MICROPY_HW_FMC_A12 (pin_G2) +#define MICROPY_HW_FMC_D0 (pin_D14) +#define MICROPY_HW_FMC_D1 (pin_D15) +#define MICROPY_HW_FMC_D2 (pin_D0) +#define MICROPY_HW_FMC_D3 (pin_D1) +#define MICROPY_HW_FMC_D4 (pin_E7) +#define MICROPY_HW_FMC_D5 (pin_E8) +#define MICROPY_HW_FMC_D6 (pin_E9) +#define MICROPY_HW_FMC_D7 (pin_E10) +#define MICROPY_HW_FMC_D8 (pin_E11) +#define MICROPY_HW_FMC_D9 (pin_E12) +#define MICROPY_HW_FMC_D10 (pin_E13) +#define MICROPY_HW_FMC_D11 (pin_E14) +#define MICROPY_HW_FMC_D12 (pin_E15) +#define MICROPY_HW_FMC_D13 (pin_D8) +#define MICROPY_HW_FMC_D14 (pin_D9) +#define MICROPY_HW_FMC_D15 (pin_D10) + +#define MICROPY_HW_USB_VID 0x2341 +#define MICROPY_HW_USB_PID 0x0566 +#define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_MSC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC2_MSC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC2 (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC3 (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC3_MSC (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC_MSC_HID (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC2_MSC_HID (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_PID_CDC3_MSC_HID (MICROPY_HW_USB_PID) +#define MICROPY_HW_USB_LANGID_STRING 0x409 +#define MICROPY_HW_USB_MANUFACTURER_STRING "Arduino" +#define MICROPY_HW_USB_PRODUCT_FS_STRING "Giga Virtual Comm Port in FS Mode" +#define MICROPY_HW_USB_PRODUCT_HS_STRING "Giga Virtual Comm Port in HS Mode" +#define MICROPY_HW_USB_INTERFACE_FS_STRING "Giga Interface" +#define MICROPY_HW_USB_INTERFACE_HS_STRING "Giga Interface" +#define MICROPY_HW_USB_CONFIGURATION_FS_STRING "Giga Config" +#define MICROPY_HW_USB_CONFIGURATION_HS_STRING "Giga Config" diff --git a/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.mk b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.mk new file mode 100644 index 0000000000..135b12b8c8 --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/mpconfigboard.mk @@ -0,0 +1,28 @@ +USE_MBOOT = 0 +USE_PYDFU = 0 +# For dual core HAL drivers. +CFLAGS += -DCORE_CM7 + +# Arduino bootloader PID:VID +BOOTLOADER_DFU_USB_VID = 0x2341 +BOOTLOADER_DFU_USB_PID = 0x0366 + +# MCU settings +MCU_SERIES = h7 +CMSIS_MCU = STM32H747xx +MICROPY_FLOAT_IMPL = single +AF_FILE = boards/stm32h743_af.csv +LD_FILES = boards/ARDUINO_GIGA/stm32h747.ld +TEXT0_ADDR = 0x08040000 + +# MicroPython settings +MICROPY_PY_BLUETOOTH = 1 +MICROPY_BLUETOOTH_NIMBLE = 1 +MICROPY_BLUETOOTH_BTSTACK = 0 +MICROPY_PY_LWIP = 1 +MICROPY_PY_NETWORK_CYW43 = 1 +MICROPY_PY_USSL = 1 +MICROPY_SSL_MBEDTLS = 1 + +FROZEN_MANIFEST = $(BOARD_DIR)/manifest.py +MBEDTLS_CONFIG_FILE = '"$(BOARD_DIR)/mbedtls_config_board.h"' diff --git a/ports/stm32/boards/ARDUINO_GIGA/pins.csv b/ports/stm32/boards/ARDUINO_GIGA/pins.csv new file mode 100644 index 0000000000..c27b5d8cd4 --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/pins.csv @@ -0,0 +1,219 @@ +PA0,PA0 +PA1,PA1 +PA2,-PA2 +PA3,-PA3 +PA4,PA4 +PA5,-PA5 +PA6,-PA6 +PA7,-PA7 +PA8,PA8 +PA9,PA9 +PA10,PA10 +PA11,PA11 +PA12,PA12 +PA13,PA13 +PA14,PA14 +PA15,PA15 +PB0,-PB0 +PB1,-PB1 +PB2,PB2 +PB3,PB3 +PB4,PB4 +PB5,PB5 +PB6,PB6 +PB7,PB7 +PB8,PB8 +PB9,PB9 +PB10,PB10 +PB11,PB11 +PB12,PB12 +PB13,PB13 +PB14,PB14 +PB15,PB15 +PC0,-PC0 +PC1,-PC1 +PC2,PC2 +PC3,PC3 +PC4,-PC4 +PC5,-PC5 +PC6,PC6 +PC7,PC7 +PC8,PC8 +PC9,PC9 +PC10,PC10 +PC11,PC11 +PC12,PC12 +PC13,PC13 +PC14,PC14 +PC15,PC15 +PD0,PD0 +PD1,PD1 +PD2,PD2 +PD3,PD3 +PD4,PD4 +PD5,PD5 +PD6,PD6 +PD7,PD7 +PD8,PD8 +PD9,PD9 +PD10,PD10 +PD11,PD11 +PD12,PD12 +PD13,PD13 +PD14,PD14 +PD15,PD15 +PE0,PE0 +PE1,PE1 +PE2,PE2 +PE3,PE3 +PE4,PE4 +PE5,PE5 +PE6,PE6 +PE7,PE7 +PE8,PE8 +PE9,PE9 +PE10,PE10 +PE11,PE11 +PE12,PE12 +PE13,PE13 +PE14,PE14 +PE15,PE15 +PF0,PF0 +PF1,PF1 +PF2,PF2 +PF3,-PF3 +PF4,-PF4 +PF5,-PF5 +PF6,-PF6 +PF7,-PF7 +PF8,-PF8 +PF9,-PF9 +PF10,-PF10 +PF11,-PF11 +PF12,PF12 +PF13,PF13 +PF14,-PF14 +PF15,PF15 +PG0,PG0 +PG1,PG1 +PG2,PG2 +PG3,PG3 +PG4,PG4 +PG5,PG5 +PG6,PG6 +PG7,PG7 +PG8,PG8 +PG9,PG9 +PG10,PG10 +PG11,PG11 +PG12,PG12 +PG13,PG13 +PG14,PG14 +PG15,PG15 +PH0,PH0 +PH1,PH1 +PH2,-PH2 +PH3,-PH3 +PH4,-PH4 +PH5,-PH5 +PH6,PH6 +PH7,PH7 +PH8,PH8 +PH9,PH9 +PH10,PH10 +PH11,PH11 +PH12,PH12 +PH13,PH13 +PH14,PH14 +PH15,PH15 +PI0,PI0 +PI1,PI1 +PI2,PI2 +PI3,PI3 +PI4,PI4 +PI5,PI5 +PI6,PI6 +PI7,PI7 +PI8,PI8 +PI9,PI9 +PI10,PI10 +PI11,PI11 +PI12,PI12 +PI13,PI13 +PI14,PI14 +PI15,PI15 +PJ0,PJ0 +PJ1,PJ1 +PJ2,PJ2 +PJ3,PJ3 +PJ4,PJ4 +PJ5,PJ5 +PJ6,PJ6 +PJ7,PJ7 +PJ8,PJ8 +PJ9,PJ9 +PJ10,PJ10 +PJ11,PJ11 +PJ12,PJ12 +PJ13,PJ13 +PJ14,PJ14 +PJ15,PJ15 +PK0,PK0 +PK1,PK1 +PK2,PK2 +PK3,PK3 +PK4,PK4 +PK5,PK5 +PK6,PK6 +PK7,PK7 +UART1_TX,PA9 +UART1_RX,PB7 +UART2_TX,PD5 +UART2_RX,PD6 +UART4_TX,PH13 +UART4_RX,PI9 +UART6_TX,PG14 +UART6_RX,PC7 +-USB_DM,PA11 +-USB_DP,PA12 +BOOT0,BOOT0 +DAC1,PA4 +DAC2,PA5 +LEDR,PI12 +LEDG,PJ13 +LEDB,PE3 +I2C1_SDA,PB9 +I2C1_SCL,PB8 +I2C2_SDA,PB11 +I2C2_SCL,PH4 +I2C4_SDA,PH12 +I2C4_SCL,PB6 +-WL_REG_ON,PB10 +-WL_HOST_WAKE,PI8 +-WL_SDIO_0,PC8 +-WL_SDIO_1,PC9 +-WL_SDIO_2,PC10 +-WL_SDIO_3,PC11 +-WL_SDIO_CMD,PD2 +-WL_SDIO_CLK,PC12 +-BT_RXD,-PA8 +-BT_TXD,PF7 +-BT_CTS,-PF9 +-BT_RTS,-PF8 +-BT_REG_ON,PA10 +-BT_HOST_WAKE,PG3 +-BT_DEV_WAKE,PH7 +-QSPI2_CS,PG6 +-QSPI2_CLK,PF10 +-QSPI2_D0,PD11 +-QSPI2_D1,PD12 +-QSPI2_D2,PE2 +-QSPI2_D3,PF6 +-SPI1_NSS,NC +-SPI1_SCK,PB3 +-SPI1_MISO,PG9 +-SPI1_MOSI,PD7 +-SPI5_NSS,PK1 +-SPI5_SCK,PH6 +-SPI5_MISO,PJ11 +-SPI5_MOSI,PJ10 \ No newline at end of file diff --git a/ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld b/ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld new file mode 100644 index 0000000000..d5bd9598f9 --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/stm32h747.ld @@ -0,0 +1,47 @@ +/* + GNU linker script for STM32H747 +*/ + +/* Specify the memory areas */ +MEMORY +{ + ITCM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + DTCM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K /* AXI SRAM D1 */ + SRAM1 (xrw) : ORIGIN = 0x30000000, LENGTH = 128K /* SRAM1 D2 */ + SRAM2 (xrw) : ORIGIN = 0x30020000, LENGTH = 128K /* SRAM2 D2 */ + SRAM3 (xrw) : ORIGIN = 0x30040000, LENGTH = 32K /* SRAM3 D2 */ + SRAM4 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K /* SRAM4 D3 */ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K /* Total available flash */ + FLASH_EXT (rx) : ORIGIN = 0x90000000, LENGTH = 16384K /* 16MBs external QSPI flash */ + FLASH_FS (r) : ORIGIN = 0x08020000, LENGTH = 128K /* sector 1 -> Flash storage */ + FLASH_TEXT (rx) : ORIGIN = 0x08040000, LENGTH = 1792K /* Sector 0 -> Arduino Bootloader + Sector 1 -> Reserved for CM4/FS + Sectors 2 -> 15 firmware */ +} + +/* produce a link error if there is not this amount of RAM for these sections */ +_minimum_stack_size = 2K; +_minimum_heap_size = 16K; + +/* Define the stack. The stack is full descending so begins just above last byte + of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve; +_sstack = _estack - 16K; /* tunable */ + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = _ebss; /* heap starts just after statically allocated memory */ +_heap_end = _sstack; + +/* Note the following varilables are only used if the filesystem flash storage is enabled */ +/* Location of filesystem RAM cache */ +_micropy_hw_internal_flash_storage_ram_cache_start = ORIGIN(DTCM); +_micropy_hw_internal_flash_storage_ram_cache_end = ORIGIN(DTCM) + LENGTH(DTCM); + +/* Location of filesystem flash storage */ +_micropy_hw_internal_flash_storage_start = ORIGIN(FLASH_FS); +_micropy_hw_internal_flash_storage_end = ORIGIN(FLASH_FS) + LENGTH(FLASH_FS); + +INCLUDE common_blifs.ld diff --git a/ports/stm32/boards/ARDUINO_GIGA/stm32h7xx_hal_conf.h b/ports/stm32/boards/ARDUINO_GIGA/stm32h7xx_hal_conf.h new file mode 100644 index 0000000000..b3b2e00dbb --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/stm32h7xx_hal_conf.h @@ -0,0 +1,51 @@ +/* This file is part of the MicroPython project, http://micropython.org/ + * The MIT License (MIT) + * Copyright (c) 2019 Damien P. George + */ +#ifndef MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H +#define MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H + +#include "boards/stm32h7xx_hal_conf_base.h" + +// Oscillator values in Hz +#define HSE_VALUE (16000000) +#define LSE_VALUE (32768) +#define EXTERNAL_CLOCK_VALUE (12288000) + +// Oscillator timeouts in ms +#define HSE_STARTUP_TIMEOUT (5000) +#define LSE_STARTUP_TIMEOUT (5000) + +#define DATA_CACHE_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define DATA_CACHE_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 1 +#define PREFETCH_ENABLE 1 +#define USE_RTOS 0 + +#define HAL_HSEM_MODULE_ENABLED +#define HAL_JPEG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_LTDC_MODULE_ENABLED +#define HAL_MDIOS_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_OPAMP_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPDIFRX_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_SWPMI_MODULE_ENABLED + +#ifdef HAL_HSEM_MODULE_ENABLED +#include "stm32h7xx_hal_hsem.h" +#endif + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32h7xx_hal_mmc.h" +#endif + +#endif // MICROPY_INCLUDED_STM32H7XX_HAL_CONF_H diff --git a/ports/stm32/boards/ARDUINO_GIGA/wifi_nvram_1dx.h b/ports/stm32/boards/ARDUINO_GIGA/wifi_nvram_1dx.h new file mode 100644 index 0000000000..7b98edad11 --- /dev/null +++ b/ports/stm32/boards/ARDUINO_GIGA/wifi_nvram_1dx.h @@ -0,0 +1,49 @@ +static const uint8_t wifi_nvram_4343[] CYW43_RESOURCE_ATTRIBUTE = + // Type1DX_Final_nvram2.txt + // 2.4 GHz, 20 MHz BW mode + "manfid=0x2d0\x00" + "prodid=0x0726\x00" + "vendid=0x14e4\x00" + "devid=0x43e2\x00" + "boardtype=0x0726\x00" + "boardrev=0x1202\x00" + "boardnum=22\x00" + "macaddr=00:90:4c:c5:12:38\x00" + "sromrev=11\x00" + "boardflags=0x00404201\x00" + "boardflags3=0x04000000\x00" + "xtalfreq=37400\x00" + "nocrc=1\x00" + "ag0=0\x00" + "aa2g=1\x00" + "ccode=ALL\x00" + // "pa0itssit=0x20\x00" + "extpagain2g=0\x00" + "pa2ga0=-145,6667,-751\x00" + "AvVmid_c0=0x0,0xc8\x00" + "cckpwroffset0=2\x00" + "maxp2ga0=74\x00" + // "txpwrbckof=6\x00" + "cckbw202gpo=0\x00" + "legofdmbw202gpo=0x88888888\x00" + "mcsbw202gpo=0xaaaaaaaa\x00" + "propbw202gpo=0xdd\x00" + "ofdmdigfilttype=18\x00" + "ofdmdigfilttypebe=18\x00" + "papdmode=1\x00" + "papdvalidtest=1\x00" + "pacalidx2g=48\x00" + "papdepsoffset=-22\x00" + "papdendidx=58\x00" + "il0macaddr=00:90:4c:c5:12:38\x00" + "wl0id=0x431b\x00" + "muxenab=0x10\x00" + // BT COEX deferral limit setting + // "btc_params 8 45000\x00" + // "btc_params 10 20000\x00" + // "spurconfig=0x3\x00" + // Antenna diversity + "swdiv_en=1\x00" + "swdiv_gpio=1\x00" + "\x00\x00" +;