kopia lustrzana https://github.com/micropython/micropython
samd/DAC: Add the dac.write_timed().
Call: dac.write_timed(data, freq [, count]) dac.deinit() Working range for dac_timed(): SAMD21: 1 Hz - 100 kHz (1 MHz clock, 10 bit) SAMD51: 1 Hz - ~500 kHz (8 MHz clock, 12 bit) The buffer has to be a byte array or a halfword array, and the data is sent once. The default for count is 1. If set to a value > 0, the data will be transmitted count times. If set to 0 or < 0, the date will be transmitted until deliberately stopped. The playback can be stopped with dac.deinit(). dac.deinit() just releases the timer and DMA channel needed by dac_timed(). The DAC object itself does not have to be released. Signed-off-by: robert-hh <robert@hammelrath.com>pull/9624/head
rodzic
9226188a46
commit
3b08312c16
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@ -101,6 +101,7 @@ MPY_CROSS_FLAGS += -march=$(MPY_CROSS_MCU_ARCH)
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SRC_C += \
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SRC_C += \
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mcu/$(MCU_SERIES_LOWER)/clock_config.c \
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mcu/$(MCU_SERIES_LOWER)/clock_config.c \
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dma_manager.c \
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help.c \
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help.c \
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machine_bitstream.c \
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machine_bitstream.c \
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machine_dac.c \
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machine_dac.c \
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@ -119,6 +120,7 @@ SRC_C += \
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samd_soc.c \
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samd_soc.c \
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samd_spiflash.c \
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samd_spiflash.c \
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usbd.c \
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usbd.c \
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tc_manager.c \
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SHARED_SRC_C += \
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SHARED_SRC_C += \
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drivers/dht/dht.c \
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drivers/dht/dht.c \
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@ -32,6 +32,7 @@ int allocate_dma_channel(void);
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void free_dma_channel(int n);
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void free_dma_channel(int n);
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void dma_init(void);
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void dma_init(void);
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void dma_deinit(void);
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void dma_deinit(void);
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void dac_stop_dma(int dma_channel, bool wait);
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extern volatile DmacDescriptor dma_desc[];
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extern volatile DmacDescriptor dma_desc[];
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@ -36,32 +36,39 @@
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#include "sam.h"
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#include "sam.h"
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#include "pin_af.h"
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#include "pin_af.h"
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#include "modmachine.h"
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#include "modmachine.h"
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#include "samd_soc.h"
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#include "dma_manager.h"
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#include "tc_manager.h"
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typedef struct _dac_obj_t {
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typedef struct _dac_obj_t {
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mp_obj_base_t base;
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mp_obj_base_t base;
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uint8_t id;
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uint8_t id;
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bool initialized;
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mp_hal_pin_obj_t gpio_id;
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mp_hal_pin_obj_t gpio_id;
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uint8_t vref;
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uint8_t vref;
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int8_t dma_channel;
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int8_t tc_index;
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uint32_t count;
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} dac_obj_t;
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} dac_obj_t;
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static dac_obj_t dac_obj[] = {
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#if defined(MCU_SAMD21)
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{{&machine_dac_type}, 0, PIN_PA02},
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#elif defined(MCU_SAMD51)
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{{&machine_dac_type}, 0, PIN_PA02},
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{{&machine_dac_type}, 1, PIN_PA05},
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#endif
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};
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Dac *const dac_bases[] = DAC_INSTS;
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Dac *const dac_bases[] = DAC_INSTS;
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STATIC void dac_init(dac_obj_t *self, Dac *dac);
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#if defined(MCU_SAMD21)
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#if defined(MCU_SAMD21)
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STATIC dac_obj_t dac_obj[] = {
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{{&machine_dac_type}, 0, PIN_PA02},
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};
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#define MAX_DAC_VALUE (1023)
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#define MAX_DAC_VALUE (1023)
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#define DEFAULT_DAC_VREF (1)
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#define DEFAULT_DAC_VREF (1)
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#define MAX_DAC_VREF (2)
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#define MAX_DAC_VREF (2)
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#elif defined(MCU_SAMD51)
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#elif defined(MCU_SAMD51)
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STATIC dac_obj_t dac_obj[] = {
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{{&machine_dac_type}, 0, PIN_PA02},
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{{&machine_dac_type}, 1, PIN_PA05},
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};
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// According to Errata 2.9.2, VDDANA as ref value is not available. However it worked
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// According to Errata 2.9.2, VDDANA as ref value is not available. However it worked
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// in tests. So I keep the selection here but set the default to Aref, which is usually
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// in tests. So I keep the selection here but set the default to Aref, which is usually
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// connected at the Board to VDDANA
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// connected at the Board to VDDANA
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@ -72,9 +79,37 @@ static uint8_t dac_vref_table[] = {
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#define MAX_DAC_VALUE (4095)
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#define MAX_DAC_VALUE (4095)
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#define DEFAULT_DAC_VREF (2)
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#define DEFAULT_DAC_VREF (2)
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#define MAX_DAC_VREF (3)
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#define MAX_DAC_VREF (3)
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static bool dac_init = false;
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#endif
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#endif // defined SAMD21 or SAMD51
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void dac_irq_handler(int dma_channel) {
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dac_obj_t *self;
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#if defined(MCU_SAMD21)
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DMAC->CHID.reg = dma_channel;
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DMAC->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
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self = &dac_obj[0];
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if (self->count > 1) {
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self->count -= 1;
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dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID;
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DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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}
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#elif defined(MCU_SAMD51)
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DMAC->Channel[dma_channel].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
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if (dac_obj[0].dma_channel == dma_channel) {
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self = &dac_obj[0];
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} else {
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self = &dac_obj[1];
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}
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if (self->count > 1) {
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self->count -= 1;
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dma_desc[self->dma_channel].BTCTRL.reg |= DMAC_BTCTRL_VALID;
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DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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}
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#endif
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}
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static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw,
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static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw,
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const mp_obj_t *all_args) {
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const mp_obj_t *all_args) {
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@ -103,68 +138,76 @@ static mp_obj_t dac_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_
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}
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}
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Dac *dac = dac_bases[0]; // Just one DAC
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Dac *dac = dac_bases[0]; // Just one DAC
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dac_init(self, dac);
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// Init DAC
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#if defined(MCU_SAMD21)
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// Configuration SAMD21
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// Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz
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PM->APBCMASK.reg |= PM_APBCMASK_DAC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC;
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Reset DAC registers
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dac->CTRLA.bit.SWRST = 1;
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while (dac->CTRLA.bit.SWRST) {
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}
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dac->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL(self->vref);
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// Enable DAC and wait to be ready
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dac->CTRLA.bit.ENABLE = 1;
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while (dac->STATUS.bit.SYNCBUSY) {
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}
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#elif defined(MCU_SAMD51)
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// Configuration SAMD51
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// Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz
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dac_init = true;
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC;
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GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
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// Reset DAC registers
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dac->CTRLA.bit.SWRST = 1;
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while (dac->CTRLA.bit.SWRST) {
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}
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dac->CTRLB.reg = DAC_CTRLB_REFSEL(dac_vref_table[self->vref]);
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dac->DACCTRL[self->id].reg = DAC_DACCTRL_ENABLE | DAC_DACCTRL_REFRESH(2) | DAC_DACCTRL_CCTRL_CC12M;
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// Enable DAC and wait to be ready
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dac->CTRLA.bit.ENABLE = 1;
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while (dac->SYNCBUSY.bit.ENABLE) {
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}
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#endif
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// Set the port as given in self->gpio_id as DAC
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// Set the port as given in self->gpio_id as DAC
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mp_hal_set_pin_mux(self->gpio_id, ALT_FCT_DAC);
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mp_hal_set_pin_mux(self->gpio_id, ALT_FCT_DAC);
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return MP_OBJ_FROM_PTR(self);
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return MP_OBJ_FROM_PTR(self);
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}
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}
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static void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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STATIC void dac_init(dac_obj_t *self, Dac *dac) {
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// Init DAC
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if (self->initialized == false) {
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#if defined(MCU_SAMD21)
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// Configuration SAMD21
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// Enable APBC clocks and PCHCTRL clocks; GCLK3 at 1 MHz
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PM->APBCMASK.reg |= PM_APBCMASK_DAC;
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_DAC;
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while (GCLK->STATUS.bit.SYNCBUSY) {
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}
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// Reset DAC registers
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dac->CTRLA.bit.SWRST = 1;
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while (dac->CTRLA.bit.SWRST) {
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}
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dac->CTRLB.reg = DAC_CTRLB_EOEN | DAC_CTRLB_REFSEL(self->vref);
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// Enable DAC and wait to be ready
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dac->CTRLA.bit.ENABLE = 1;
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while (dac->STATUS.bit.SYNCBUSY) {
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}
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#elif defined(MCU_SAMD51)
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// Configuration SAMD51
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// Enable APBD clocks and PCHCTRL clocks; GCLK3 at 8 MHz
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_DAC;
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GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
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// Reset DAC registers
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dac->CTRLA.bit.SWRST = 1;
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while (dac->CTRLA.bit.SWRST) {
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}
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dac->CTRLB.reg = DAC_CTRLB_REFSEL(dac_vref_table[self->vref]);
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dac->DACCTRL[self->id].reg = DAC_DACCTRL_ENABLE | DAC_DACCTRL_REFRESH(2) | DAC_DACCTRL_CCTRL_CC12M;
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// Enable DAC and wait to be ready
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dac->CTRLA.bit.ENABLE = 1;
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while (dac->SYNCBUSY.bit.ENABLE) {
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}
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#endif // defined SAMD21 or SAMD51
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}
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self->initialized = true;
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}
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STATIC void dac_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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dac_obj_t *self = self_in;
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dac_obj_t *self = self_in;
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mp_printf(print, "DAC(%u, Pin=%q, vref=%d)", self->id, pin_find_by_id(self->gpio_id)->name, self->vref);
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mp_printf(print, "DAC(%u, Pin=%q, vref=%d)", self->id, pin_find_by_id(self->gpio_id)->name, self->vref);
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}
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}
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static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) {
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static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) {
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Dac *dac = dac_bases[0]; // Just one DAC
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Dac *dac = dac_bases[0]; // Just one DAC
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dac_obj_t *self = self_in;
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int value = mp_obj_get_int(value_in);
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int value = mp_obj_get_int(value_in);
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if (value < 0 || value > MAX_DAC_VALUE) {
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if (value < 0 || value > MAX_DAC_VALUE) {
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mp_raise_ValueError(MP_ERROR_TEXT("value out of range"));
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mp_raise_ValueError(MP_ERROR_TEXT("value out of range"));
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}
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}
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// Re-init, if required
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dac_init(self, dac);
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#if defined(MCU_SAMD21)
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#if defined(MCU_SAMD21)
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dac->DATA.reg = value;
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dac->DATA.reg = value;
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#elif defined(MCU_SAMD51)
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#elif defined(MCU_SAMD51)
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dac_obj_t *self = self_in;
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dac->DATA[self->id].reg = value;
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dac->DATA[self->id].reg = value;
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#endif
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#endif
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@ -172,8 +215,116 @@ static mp_obj_t dac_write(mp_obj_t self_in, mp_obj_t value_in) {
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}
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}
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MP_DEFINE_CONST_FUN_OBJ_2(dac_write_obj, dac_write);
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MP_DEFINE_CONST_FUN_OBJ_2(dac_write_obj, dac_write);
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static const mp_rom_map_elem_t dac_locals_dict_table[] = {
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STATIC mp_obj_t dac_write_timed(size_t n_args, const mp_obj_t *args) {
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Dac *dac = dac_bases[0]; // Just one DAC used
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dac_obj_t *self = args[0];
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mp_buffer_info_t src;
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// Re-init, if required
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dac_init(self, dac);
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mp_get_buffer_raise(args[1], &src, MP_BUFFER_READ);
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if (n_args > 3) {
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self->count = mp_obj_get_int(args[3]);
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} else {
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self->count = 1;
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}
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if (src.len >= 2) {
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int freq = mp_obj_get_int(args[2]);
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if (self->dma_channel == -1) {
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self->dma_channel = allocate_dma_channel();
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dma_init();
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dma_register_irq(self->dma_channel, dac_irq_handler);
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}
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if (self->tc_index == -1) {
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self->tc_index = allocate_tc_instance();
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}
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// Configure TC; no need to check the return value
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configure_tc(self->tc_index, freq);
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// Configure DMA for halfword output to the DAC
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#if defined(MCU_SAMD21)
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dma_desc[self->dma_channel].BTCTRL.reg =
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DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_STEPSEL |
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DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
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dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
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dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(src.buf) + src.len;
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dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(&dac->DATA.reg);
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if (self->count >= 1) {
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dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
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} else {
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dma_desc[self->dma_channel].DESCADDR.reg = (uint32_t)(&dma_desc[self->dma_channel].BTCTRL.reg);
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}
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DMAC->CHID.reg = self->dma_channel;
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DMAC->CHCTRLA.reg = 0;
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while (DMAC->CHCTRLA.bit.ENABLE) {
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}
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DMAC->CHCTRLB.reg =
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DMAC_CHCTRLB_LVL(0) |
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DMAC_CHCTRLB_TRIGACT_BEAT |
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DMAC_CHCTRLB_TRIGSRC(TC3_DMAC_ID_OVF + 3 * self->tc_index);
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DMAC->CHINTENSET.reg = DMAC_CHINTFLAG_TCMPL;
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DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
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NVIC_EnableIRQ(DMAC_IRQn);
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#elif defined(MCU_SAMD51)
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dma_desc[self->dma_channel].BTCTRL.reg =
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DMAC_BTCTRL_VALID | DMAC_BTCTRL_BLOCKACT_NOACT |
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DMAC_BTCTRL_BEATSIZE_HWORD | DMAC_BTCTRL_SRCINC | DMAC_BTCTRL_STEPSEL |
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||||||
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DMAC_BTCTRL_STEPSIZE(DMAC_BTCTRL_STEPSIZE_X1_Val);
|
||||||
|
dma_desc[self->dma_channel].BTCNT.reg = src.len / 2;
|
||||||
|
dma_desc[self->dma_channel].SRCADDR.reg = (uint32_t)(src.buf) + src.len;
|
||||||
|
dma_desc[self->dma_channel].DSTADDR.reg = (uint32_t)(&dac->DATA[self->id].reg);
|
||||||
|
if (self->count >= 1) {
|
||||||
|
dma_desc[self->dma_channel].DESCADDR.reg = 0; // ONE_SHOT
|
||||||
|
} else {
|
||||||
|
dma_desc[self->dma_channel].DESCADDR.reg = (uint32_t)(&dma_desc[self->dma_channel].BTCTRL.reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
DMAC->Channel[self->dma_channel].CHCTRLA.reg =
|
||||||
|
DMAC_CHCTRLA_BURSTLEN(DMAC_CHCTRLA_BURSTLEN_SINGLE_Val) |
|
||||||
|
DMAC_CHCTRLA_TRIGACT(DMAC_CHCTRLA_TRIGACT_BURST_Val) |
|
||||||
|
DMAC_CHCTRLA_TRIGSRC(TC0_DMAC_ID_OVF + 3 * self->tc_index);
|
||||||
|
DMAC->Channel[self->dma_channel].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
|
||||||
|
DMAC->Channel[self->dma_channel].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
|
||||||
|
|
||||||
|
if (self->dma_channel < 4) {
|
||||||
|
NVIC_EnableIRQ(DMAC_0_IRQn + self->dma_channel);
|
||||||
|
} else {
|
||||||
|
NVIC_EnableIRQ(DMAC_4_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // defined SAMD21 or SAMD51
|
||||||
|
}
|
||||||
|
return mp_const_none;
|
||||||
|
}
|
||||||
|
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(dac_write_timed_obj, 3, 4, dac_write_timed);
|
||||||
|
|
||||||
|
STATIC mp_obj_t dac_deinit(mp_obj_t self_in) {
|
||||||
|
dac_obj_t *self = self_in;
|
||||||
|
self->initialized = false;
|
||||||
|
// Reset the DAC to lower the current consumption as SAMD21
|
||||||
|
dac_bases[0]->CTRLA.bit.SWRST = 1;
|
||||||
|
if (self->dma_channel >= 0) {
|
||||||
|
dac_stop_dma(self->dma_channel, true);
|
||||||
|
free_dma_channel(self->dma_channel);
|
||||||
|
self->dma_channel = -1;
|
||||||
|
}
|
||||||
|
if (self->tc_index >= 0) {
|
||||||
|
free_tc_instance(self->tc_index);
|
||||||
|
self->tc_index = -1;
|
||||||
|
}
|
||||||
|
return mp_const_none;
|
||||||
|
}
|
||||||
|
MP_DEFINE_CONST_FUN_OBJ_1(dac_deinit_obj, dac_deinit);
|
||||||
|
|
||||||
|
STATIC const mp_rom_map_elem_t dac_locals_dict_table[] = {
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&dac_deinit_obj) },
|
||||||
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) },
|
{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&dac_write_obj) },
|
||||||
|
{ MP_ROM_QSTR(MP_QSTR_write_timed), MP_ROM_PTR(&dac_write_timed_obj) },
|
||||||
};
|
};
|
||||||
|
|
||||||
static MP_DEFINE_CONST_DICT(dac_locals_dict, dac_locals_dict_table);
|
static MP_DEFINE_CONST_DICT(dac_locals_dict, dac_locals_dict_table);
|
||||||
|
|
|
@ -35,6 +35,8 @@
|
||||||
#include "shared/runtime/softtimer.h"
|
#include "shared/runtime/softtimer.h"
|
||||||
#include "shared/tinyusb/mp_usbd.h"
|
#include "shared/tinyusb/mp_usbd.h"
|
||||||
#include "clock_config.h"
|
#include "clock_config.h"
|
||||||
|
#include "dma_manager.h"
|
||||||
|
#include "tc_manager.h"
|
||||||
|
|
||||||
extern uint8_t _sstack, _estack, _sheap, _eheap;
|
extern uint8_t _sstack, _estack, _sheap, _eheap;
|
||||||
extern void adc_deinit_all(void);
|
extern void adc_deinit_all(void);
|
||||||
|
@ -87,6 +89,8 @@ void samd_main(void) {
|
||||||
|
|
||||||
soft_reset_exit:
|
soft_reset_exit:
|
||||||
mp_printf(MP_PYTHON_PRINTER, "MPY: soft reboot\n");
|
mp_printf(MP_PYTHON_PRINTER, "MPY: soft reboot\n");
|
||||||
|
dma_deinit();
|
||||||
|
tc_deinit();
|
||||||
#if MICROPY_PY_MACHINE_ADC
|
#if MICROPY_PY_MACHINE_ADC
|
||||||
adc_deinit_all();
|
adc_deinit_all();
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -68,7 +68,6 @@ static void usb_init(void) {
|
||||||
void init_us_counter(void) {
|
void init_us_counter(void) {
|
||||||
#if defined(MCU_SAMD21)
|
#if defined(MCU_SAMD21)
|
||||||
|
|
||||||
PM->APBCMASK.bit.TC3_ = 1; // Enable TC3 clock
|
|
||||||
PM->APBCMASK.bit.TC4_ = 1; // Enable TC4 clock
|
PM->APBCMASK.bit.TC4_ = 1; // Enable TC4 clock
|
||||||
// Select multiplexer generic clock source and enable.
|
// Select multiplexer generic clock source and enable.
|
||||||
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_TC4_TC5;
|
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | GCLK_CLKCTRL_ID_TC4_TC5;
|
||||||
|
|
Ładowanie…
Reference in New Issue