From 62760e0dadbfcd7bcc4080ef5a4bf49ba7ce7942 Mon Sep 17 00:00:00 2001 From: Victor Rajewski Date: Tue, 4 Jul 2023 15:11:06 +1000 Subject: [PATCH 1/2] stm32/qspi.c: Allow qspi_write_cmd_data to write cmd with 1 data byte. The existing qspi for stm32 implementation can only send a spi command with exactly 0 or 2 data bytes. Certain spiflash chips (e.g. AT25SF321B) have commands that only take a single data byte, and will ignore the command if more than that is sent. This allows sending a command with a single data byte. Would be nicer to have a general function to send `n` bytes, but there probably aren't many commands that require this. Signed-off-by: Victor Rajewski --- ports/stm32/qspi.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/ports/stm32/qspi.c b/ports/stm32/qspi.c index a79e692e0e..c10bec2365 100644 --- a/ports/stm32/qspi.c +++ b/ports/stm32/qspi.c @@ -232,8 +232,12 @@ STATIC int qspi_write_cmd_data(void *self_in, uint8_t cmd, size_t len, uint32_t while (!(QUADSPI->SR & QUADSPI_SR_FTF)) { } - // This assumes len==2 - *(uint16_t *)&QUADSPI->DR = data; + if (len == 1) { + *(uint8_t *)&QUADSPI->DR = data; + } else { + // This assumes len==2 + *(uint16_t *)&QUADSPI->DR = data; + } } // Wait for write to finish From 5d72f6862b503c91060233fb2414491550775d80 Mon Sep 17 00:00:00 2001 From: Victor Rajewski Date: Tue, 4 Jul 2023 16:11:19 +1000 Subject: [PATCH 2/2] drivers/memory/spiflash.c: Write 2nd byte of SR as separate command. The existing spiflash driver writes both bytes of SR as a single command. Some flash chips don't support multi-byte writes such as this, and have a seperate command to write SR byte 1 and SR byte 2 (referred to in the code as CR). This used in the spiflash initialisation to enable quad mode. The quad enable bit is in the second SR byte. This change still issues the multi-byte command, then issues a single byte command for just the second SR byte. For chips that only support one of the commands, the unsupported command should be ignored silently. For chips that support both types of command, the SR will be written twice. This depends on https://github.com/micropython/micropython/pull/11931 for the stm32 port to allow single-byte spi commands. Signed-off-by: Victor Rajewski --- drivers/memory/spiflash.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/memory/spiflash.c b/drivers/memory/spiflash.c index 52739b1d8b..e05d8bb850 100644 --- a/drivers/memory/spiflash.c +++ b/drivers/memory/spiflash.c @@ -40,6 +40,7 @@ #define CMD_RDSR (0x05) #define CMD_WREN (0x06) #define CMD_SEC_ERASE (0x20) +#define CMD_WRCR (0x31) // sometimes referred to as SR byte 2 #define CMD_RDCR (0x35) #define CMD_RD_DEVID (0x9f) #define CMD_CHIP_ERASE (0xc7) @@ -199,10 +200,17 @@ void mp_spiflash_init(mp_spiflash_t *self) { } uint32_t data = (sr & 0xff) | (cr & 0xff) << 8; if (ret == 0 && !(data & (QSPI_QE_MASK << 8))) { + // Write both bytes of SR data |= QSPI_QE_MASK << 8; mp_spiflash_write_cmd(self, CMD_WREN); mp_spiflash_write_cmd_data(self, CMD_WRSR, 2, data); mp_spiflash_wait_wip0(self); + + // Write just byte 2 of SR for flash that only supports that mode of setting SR + data = (cr & 0xff) | QSPI_QE_MASK; + mp_spiflash_write_cmd(self, CMD_WREN); + mp_spiflash_write_cmd_data(self, CMD_WRCR, 1, data); + mp_spiflash_wait_wip0(self); } }