From 2a08f14a67274003a88cf2f2e0eb897517dc309c Mon Sep 17 00:00:00 2001 From: Peter Hinch Date: Thu, 14 Apr 2022 10:43:56 +0100 Subject: [PATCH] ENCODERS.md: add schematics. --- encoders/ENCODERS.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/encoders/ENCODERS.md b/encoders/ENCODERS.md index 32a3043..8e6dcd8 100644 --- a/encoders/ENCODERS.md +++ b/encoders/ENCODERS.md @@ -295,3 +295,7 @@ These can use the above circuits, but as they produce good logic levels an alternative is to use two d-type flip-flops on each channel, clocked using a signal from the host. Typically this might be produced by a PWM channel running continuously. Clock rate depends on the expected worst-case interrupt latency. + +This [Wikipedia image](https://en.wikipedia.org/wiki/Incremental_encoder#/media/File:2FF_synchronizer.gif) +illustrates the idea, along with the metastability problem. +