kopia lustrzana https://github.com/markondej/fm_transmitter
Marcin Kondej
GitHub
commit
cec3dad1bc
104
transmitter.cpp
104
transmitter.cpp
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@ -43,14 +43,6 @@
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#define PERIPHERALS_PHYS_BASE 0x7e000000
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#define BCM2835_PERI_VIRT_BASE 0x20000000
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#define BCM2711_PERI_VIRT_BASE 0xfe000000
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#define DMA0_BASE_OFFSET 0x00007000
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#define DMA15_BASE_OFFSET 0x00e05000
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#define CLK0_BASE_OFFSET 0x00101070
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#define CLK1_BASE_OFFSET 0x00101078
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#define PWMCLK_BASE_OFFSET 0x001010a0
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#define GPIO_BASE_OFFSET 0x00200000
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#define PWM_BASE_OFFSET 0x0020c000
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#define TIMER_BASE_OFFSET 0x00003000
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#define BCM2835_MEM_FLAG 0x0c
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#define BCM2711_MEM_FLAG 0x04
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@ -58,9 +50,54 @@
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#define BCM2835_PLLD_FREQ 500
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#define BCM2711_PLLD_FREQ 750
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#define BUFFER_TIME 1000000
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#define PWM_WRITES_PER_SAMPLE 10
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#define GPIO_BASE_OFFSET 0x00200000
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#define TIMER_BASE_OFFSET 0x00003000
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#define CLK0_BASE_OFFSET 0x00101070
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#define CLK1_BASE_OFFSET 0x00101078
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#define CLK_PASSWORD (0x5a << 24)
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#define CLK_CTL_SRC_PLLA 0x04
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#define CLK_CTL_SRC_PLLC 0x05
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#define CLK_CTL_SRC_PLLD 0x06
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#define CLK_CTL_ENAB (0x01 << 4)
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#define CLK_CTL_MASH(x) ((x & 0x03) << 9)
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#define PWMCLK_BASE_OFFSET 0x001010a0
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#define PWM_BASE_OFFSET 0x0020c000
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#define PWM_CHANNEL_RANGE 32
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#define PWM_WRITES_PER_SAMPLE 10
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#define PWM_CTL_CLRF1 (0x01 << 6)
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#define PWM_CTL_USEF1 (0x01 << 5)
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#define PWM_CTL_RPTL1 (0x01 << 2)
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#define PWM_CTL_MODE1 (0x01 << 1)
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#define PWM_CTL_PWEN1 0x01
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#define PWM_STA_BERR (0x01 << 8)
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#define PWM_STA_GAPO4 (0x01 << 7)
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#define PWM_STA_GAPO3 (0x01 << 6)
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#define PWM_STA_GAPO2 (0x01 << 5)
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#define PWM_STA_GAPO1 (0x01 << 4)
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#define PWM_STA_RERR1 (0x01 << 3)
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#define PWM_STA_WERR1 (0x01 << 2)
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#define PWM_STA_EMPT1 (0x01 << 1)
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#define PWM_STA_FULL1 0x01
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#define PWM_DMAC_ENAB (0x01 << 31)
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#define PWM_DMAC_PANIC(x) ((x & 0x0f) << 8)
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#define PWM_DMAC_DREQ(x) (x & 0x0f)
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#define DMA0_BASE_OFFSET 0x00007000
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#define DMA15_BASE_OFFSET 0x00e05000
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#define DMA_CS_RESET (0x01 << 31)
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#define DMA_CS_PANIC_PRIORITY(x) ((x & 0x0f) << 20)
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#define DMA_CS_PRIORITY(x) ((x & 0x0f) << 16)
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#define DMA_CS_INT (0x01 << 2)
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#define DMA_CS_END (0x01 << 1)
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#define DMA_CS_ACTIVE 0x01
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#define DMA_TI_NO_WIDE_BURST (0x01 << 26)
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#define DMA_TI_PERMAP(x) ((x & 0x0f) << 16)
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#define DMA_TI_DEST_DREQ (0x01 << 6)
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#define DMA_TI_WAIT_RESP (0x01 << 3)
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#define BUFFER_TIME 1000000
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#define PAGE_SIZE 4096
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struct TimerRegisters {
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@ -224,13 +261,12 @@ class ClockDevice : public Device
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ClockDevice() = delete;
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ClockDevice(uintptr_t address, unsigned divisor) {
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clock = reinterpret_cast<ClockRegisters *>(peripherals->GetVirtualAddress(address));
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clock->ctl = (0x5a << 24) | 0x06;
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std::this_thread::sleep_for(std::chrono::microseconds(1000));
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clock->div = (0x5a << 24) | (0xffffff & divisor);
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clock->ctl = (0x5a << 24) | (0x01 << 9) | (0x01 << 4) | 0x06;
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}
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clock->ctl = CLK_PASSWORD | CLK_CTL_SRC_PLLD;
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std::this_thread::sleep_for(std::chrono::microseconds(100));
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clock->div = CLK_PASSWORD | (0xffffff & divisor);
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clock->ctl = CLK_PASSWORD | CLK_CTL_MASH(0x1) | CLK_CTL_ENAB | CLK_CTL_SRC_PLLD; }
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virtual ~ClockDevice() {
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clock->ctl = (0x5a << 24) | 0x06;
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clock->ctl = CLK_PASSWORD | CLK_CTL_SRC_PLLD;
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}
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protected:
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volatile ClockRegisters *clock;
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@ -258,7 +294,7 @@ class ClockOutput : public ClockDevice
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#endif
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}
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inline void SetDivisor(unsigned divisor) {
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clock->div = (0x5a << 24) | (0xffffff & divisor);
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clock->div = CLK_PASSWORD | (0xffffff & divisor);
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}
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inline volatile uint32_t &GetDivisor() {
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return clock->div;
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@ -274,13 +310,13 @@ class PWMController : public ClockDevice
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PWMController(unsigned sampleRate) : ClockDevice(PWMCLK_BASE_OFFSET, static_cast<unsigned>(Peripherals::GetClockFrequency() * 1000000.f * (0x01 << 12) / (PWM_WRITES_PER_SAMPLE * PWM_CHANNEL_RANGE * sampleRate))) {
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pwm = reinterpret_cast<PWMRegisters *>(peripherals->GetVirtualAddress(PWM_BASE_OFFSET));
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pwm->ctl = 0x00000000;
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std::this_thread::sleep_for(std::chrono::microseconds(1000));
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pwm->status = 0x01fc;
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pwm->ctl = (0x01 << 6);
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std::this_thread::sleep_for(std::chrono::microseconds(1000));
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std::this_thread::sleep_for(std::chrono::microseconds(100));
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pwm->status = PWM_STA_BERR | PWM_STA_GAPO1 | PWM_STA_RERR1 | PWM_STA_WERR1;
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pwm->ctl = PWM_CTL_CLRF1;
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std::this_thread::sleep_for(std::chrono::microseconds(100));
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pwm->chn1Range = PWM_CHANNEL_RANGE;
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pwm->dmaConf = (0x01 << 31) | 0x0707;
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pwm->ctl = (0x01 << 5) | (0x01 << 2) | 0x01;
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pwm->dmaConf = PWM_DMAC_ENAB | PWM_DMAC_PANIC(0x7) | PWM_DMAC_DREQ(0x7);
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pwm->ctl = PWM_CTL_USEF1 | PWM_CTL_RPTL1 | PWM_CTL_MODE1 | PWM_CTL_PWEN1;
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}
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virtual ~PWMController() {
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pwm->ctl = 0x00000000;
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@ -298,14 +334,14 @@ class DMAController : public Device
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DMAController() = delete;
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DMAController(uint32_t address, unsigned dmaChannel) {
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dma = reinterpret_cast<DMARegisters *>(peripherals->GetVirtualAddress((dmaChannel < 15) ? DMA0_BASE_OFFSET + dmaChannel * 0x100 : DMA15_BASE_OFFSET));
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dma->ctlStatus = (0x01 << 31);
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std::this_thread::sleep_for(std::chrono::microseconds(1000));
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dma->ctlStatus = (0x01 << 2) | (0x01 << 1);
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dma->ctlStatus = DMA_CS_RESET;
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std::this_thread::sleep_for(std::chrono::microseconds(100));
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dma->ctlStatus = DMA_CS_INT | DMA_CS_END;
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dma->cbAddress = address;
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dma->ctlStatus = (0xff << 16) | 0x01;
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dma->ctlStatus = DMA_CS_PANIC_PRIORITY(0xf) | DMA_CS_PRIORITY(0xf) | DMA_CS_ACTIVE;
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}
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virtual ~DMAController() {
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dma->ctlStatus = (0x01 << 31);
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dma->ctlStatus = DMA_CS_RESET;
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}
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inline void SetControllBlockAddress(uint32_t address) {
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dma->cbAddress = address;
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@ -444,8 +480,8 @@ void Transmitter::TransmitViaDma(WaveReader &reader, ClockOutput &output, unsign
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volatile uint32_t *pwmFifoData = reinterpret_cast<uint32_t *>(reinterpret_cast<uintptr_t>(clkDiv) + sizeof(uint32_t) * bufferSize);
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for (i = 0; i < bufferSize; i++) {
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float value = samples[i].GetMonoValue();
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clkDiv[i] = (0x5a << 24) | (0xffffff & (clockDivisor - static_cast<int32_t>(round(value * divisorRange))));
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dmaCb[cbOffset].transferInfo = (0x01 << 26) | (0x01 << 3);
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clkDiv[i] = CLK_PASSWORD | (0xffffff & (clockDivisor - static_cast<int32_t>(round(value * divisorRange))));
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dmaCb[cbOffset].transferInfo = DMA_TI_NO_WIDE_BURST | DMA_TI_WAIT_RESP;;
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dmaCb[cbOffset].srcAddress = allocated.GetPhysicalAddress(&clkDiv[i]);
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dmaCb[cbOffset].dstAddress = peripherals.GetPhysicalAddress(&output.GetDivisor());
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dmaCb[cbOffset].transferLen = sizeof(uint32_t);
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@ -453,7 +489,7 @@ void Transmitter::TransmitViaDma(WaveReader &reader, ClockOutput &output, unsign
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dmaCb[cbOffset].nextCbAddress = allocated.GetPhysicalAddress(&dmaCb[cbOffset + 1]);
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cbOffset++;
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dmaCb[cbOffset].transferInfo = (0x01 << 26) | (0x05 << 16) | (0x01 << 6) | (0x01 << 3);
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dmaCb[cbOffset].transferInfo = DMA_TI_NO_WIDE_BURST | DMA_TI_PERMAP(0x5) | DMA_TI_DEST_DREQ | DMA_TI_WAIT_RESP;
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dmaCb[cbOffset].srcAddress = allocated.GetPhysicalAddress(pwmFifoData);
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dmaCb[cbOffset].dstAddress = peripherals.GetPhysicalAddress(&pwm.GetFifoIn());
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dmaCb[cbOffset].transferLen = sizeof(uint32_t) * PWM_WRITES_PER_SAMPLE;
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@ -465,7 +501,7 @@ void Transmitter::TransmitViaDma(WaveReader &reader, ClockOutput &output, unsign
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DMAController dma(allocated.GetPhysicalAddress(dmaCb), dmaChannel);
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std::this_thread::sleep_for(std::chrono::microseconds(BUFFER_TIME / 4));
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std::this_thread::sleep_for(std::chrono::microseconds(BUFFER_TIME / 100));
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auto finally = [&]() {
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dmaCb[(cbOffset < 2 * bufferSize) ? cbOffset : 0].nextCbAddress = 0x00000000;
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@ -486,9 +522,9 @@ void Transmitter::TransmitViaDma(WaveReader &reader, ClockOutput &output, unsign
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for (i = 0; i < samples.size(); i++) {
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float value = samples[i].GetMonoValue();
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while (i == ((dma.GetControllBlockAddress() - allocated.GetPhysicalAddress(dmaCb)) / (2 * sizeof(DMAControllBlock)))) {
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std::this_thread::sleep_for(std::chrono::milliseconds(1));
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std::this_thread::sleep_for(std::chrono::microseconds(BUFFER_TIME / 100));
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}
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clkDiv[i] = (0x5a << 24) | (0xffffff & (clockDivisor - static_cast<int>(round(value * divisorRange))));
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clkDiv[i] = CLK_PASSWORD | (0xffffff & (clockDivisor - static_cast<int>(round(value * divisorRange))));
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cbOffset += 2;
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}
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}
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